verilator-5.044/0000755000542200017500000000000015125463617014125 5ustar mahmoudyfreeshellverilator-5.044/CITATION.cff0000644000542200017500000000152115125463617016016 0ustar mahmoudyfreeshell--- # See https://citation-file-format.github.io/ cff-version: 1.2.0 title: Verilator message: >- If you use this software, please cite it using the metadata from this file. type: software authors: - given-names: Wilson family-names: Snyder email: wsnyder@wsnyder.org affiliation: Veripool - given-names: Paul family-names: Wasson - given-names: Duane family-names: Galbi - given-names: Geza family-names: Lore - name: 'et al' repository-code: 'https://github.com/verilator/verilator' url: 'https://verilator.org' abstract: >- The Verilator package converts Verilog and SystemVerilog hardware description language (HDL) designs into a fast C++ or SystemC model that, after compiling, can be executed. Verilator is not only a traditional simulator but a compiler. license: [LGPL-3.0-only, Artistic-2.0] verilator-5.044/ci/0000755000542200017500000000000015125463617014520 5ustar mahmoudyfreeshellverilator-5.044/ci/docker/0000755000542200017500000000000015125463617015767 5ustar mahmoudyfreeshellverilator-5.044/ci/docker/buildenv/0000755000542200017500000000000015125463617017577 5ustar mahmoudyfreeshellverilator-5.044/ci/docker/buildenv/build.sh0000755000542200017500000000117215125463617021236 0ustar mahmoudyfreeshell#!/bin/bash -e # DESCRIPTION: Build Verilator (inside container) # # Copyright 2020 by Stefan Wallentowitz. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 : "${REPO:=https://github.com/verilator/verilator}" : "${REV:=master}" : "${CXX:=g++}" SRCS=$PWD/verilator git clone "$REPO" "$SRCS" cd "$SRCS" git checkout "$REV" autoconf ./configure --enable-longtests make -j $(nproc) if [ "${1:-''}" == "test" ]; then make test fi verilator-5.044/ci/docker/buildenv/README.rst0000644000542200017500000000353715125463617021276 0ustar mahmoudyfreeshell.. Copyright 2003-2026 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _verilator build docker container: Verilator Build Docker Container ================================ This Verilator Build Docker Container is set up to compile and test a Verilator build. It uses the following parameters: - Source repository (default: https://github.com/verilator/verilator) - Source revision (default: master) - Compiler (GCC 13.3.0, clang 18.1.3, default: 13.3.0) The container is published as ``verilator/verilator-buildenv`` on `docker hub `__. To run the basic build using the current Verilator master: :: docker run -ti verilator/verilator-buildenv To also run tests: :: docker run -ti verilator/verilator-buildenv test To change the compiler use the `-e` switch to pass environment variables: :: docker run -ti -e CXX=clang++-18 verilator/verilator-buildenv test The tests, that involve numactl are not working due to security restrictions. To run those too, add the CAP_SYS_NICE capability during the start of the container: :: docker run -ti --cap-add=CAP_SYS_NICE verilator/verilator-buildenv test Rather then building using a remote git repository you may prefer to use a working copy on the local filesystem. Mount the local working copy path as a volume and use that in place of git. When doing this be careful to have all changes committed to the local git area. To build the current HEAD from top of a repository: :: docker run -ti -v ${PWD}:/tmp/repo -e REPO=/tmp/repo -e REV=`git rev-parse --short HEAD` verilator/verilator-buildenv test Rebuilding ---------- To rebuild the Verilator-buildenv docker image, run: :: docker build . This will also build SystemC under all supported compiler variants to reduce the SystemC testing time. verilator-5.044/ci/docker/buildenv/Dockerfile0000644000542200017500000000415415125463617021575 0ustar mahmoudyfreeshell# DESCRIPTION: Dockerfile for env to build and fully test Verilator # # Copyright 2020 by Stefan Wallentowitz. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 FROM ubuntu:24.04 # Create the user RUN groupadd verilator \ && useradd -g verilator -m verilator -s /bin/bash \ && apt-get update \ && apt-get install --no-install-recommends -y sudo \ && apt-get clean \ && rm -rf /var/lib/apt/lists/* \ && echo verilator ALL=\(root\) NOPASSWD:ALL > /etc/sudoers.d/verilator \ && chmod 0440 /etc/sudoers.d/verilator RUN apt-get update \ && DEBIAN_FRONTEND=noninteractive \ apt-get install --no-install-recommends -y \ autoconf \ bc \ bison \ build-essential \ ca-certificates \ ccache \ clang \ cmake \ flex \ gdb \ git \ gtkwave \ help2man \ libfl2 \ libfl-dev \ libclang-rt-18-dev \ libgoogle-perftools-dev \ libsystemc \ libsystemc-dev \ numactl \ perl \ python3 \ python3-distro \ wget \ z3 \ zlib1g \ zlib1g-dev \ && apt-get clean \ && rm -rf /var/lib/apt/lists/* WORKDIR /tmp RUN git clone https://github.com/veripool/vcddiff.git && \ make -C vcddiff && \ cp -p vcddiff/vcddiff /usr/local/bin/vcddiff && \ rm -rf vcddiff COPY build.sh /tmp/build.sh ENV VERILATOR_AUTHOR_SITE=1 USER verilator WORKDIR /work ENTRYPOINT [ "/tmp/build.sh" ] verilator-5.044/ci/docker/run/0000755000542200017500000000000015125463617016573 5ustar mahmoudyfreeshellverilator-5.044/ci/docker/run/verilator-wrap.sh0000755000542200017500000000204615125463617022112 0ustar mahmoudyfreeshell#!/bin/bash # DESCRIPTION: Wrap a Verilator call and copy vlt includes # (inside docker container) # # Copyright 2020 by Stefan Wallentowitz. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 perl /usr/local/bin/verilator "$@" status=$? if [ $status -ne 0 ]; then exit $status fi # Check if user set an obj_dir obj_dir=$(echo " $@" | grep -oP '\s--Mdir\s*\K\S+') if [ "$obj_dir" == "" ]; then obj_dir="obj_dir" fi # If the run was successful: Copy required files to allow build without this container if [ -e ${obj_dir} ]; then # Copy files required for the build mkdir -p ${obj_dir}/vlt cp -r /usr/local/share/verilator/bin ${obj_dir}/vlt cp -r /usr/local/share/verilator/include ${obj_dir}/vlt # Point Makefile to that folder sed -i 's/VERILATOR_ROOT = \/usr\/local\/share\/verilator/VERILATOR_ROOT = vlt/g' ${obj_dir}/*.mk fi verilator-5.044/ci/docker/run/hooks/0000755000542200017500000000000015125463617017716 5ustar mahmoudyfreeshellverilator-5.044/ci/docker/run/hooks/post_push0000755000542200017500000000075615125463617021700 0ustar mahmoudyfreeshell#!/bin/bash # DESCRIPTION: Docker hub hook to tag the latest release (stable) # # Copyright 2020 by Stefan Wallentowitz. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 if [ "$SOURCE_BRANCH"="stable" ]; then docker tag $IMAGE_NAME $DOCKER_REPO:latest docker push $DOCKER_REPO:latest fi verilator-5.044/ci/docker/run/hooks/build0000644000542200017500000000070515125463617020742 0ustar mahmoudyfreeshell#!/bin/bash # DESCRIPTION: Docker hub hook to pass SOURCE_COMMIT # # Copyright 2020 by Stefan Wallentowitz. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 docker build --build-arg SOURCE_COMMIT=${SOURCE_COMMIT} -f $DOCKERFILE_PATH -t $IMAGE_NAME . verilator-5.044/ci/docker/run/verilator-docker0000755000542200017500000000077015125463617022001 0ustar mahmoudyfreeshell#!/bin/bash # DESCRIPTION: Wrap a verilator call to run a docker container # # Copyright 2020 by Stefan Wallentowitz. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 docker pull verilator/verilator:$1 >/dev/null docker run -ti -v ${PWD}:/work --user $(id -u):$(id -g) verilator/verilator:$1 "${@:2}" verilator-5.044/ci/docker/run/README.rst0000644000542200017500000000436215125463617020267 0ustar mahmoudyfreeshell.. Copyright 2003-2026 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 Verilator Executable Docker Container ===================================== The Verilator Executable Docker Container allows you to run Verilator easily as a docker image, e.g.: :: docker run -ti verilator/verilator:latest --version This will pull the container from `Docker Hub `_, run the latest Verilator and print Verilator's version. Containers are automatically built and pushed to docker hub for all released versions, so you may easily compare results across versions, e.g.: :: docker run -ti verilator/verilator:4.030 --version Verilator needs to read and write files on the local system. To simplify this process, use the ``verilator-docker`` convenience script. This script takes the version number, and all remaining arguments are passed through to Verilator. e.g.: :: ./verilator-docker 4.030 --version or :: ./verilator-docker 4.030 --cc test.v If you prefer not to use ``verilator-docker`` you must give the container access to your files as a volume with appropriate user rights. For example to Verilate test.v: :: docker run -ti -v ${PWD}:/work --user $(id -u):$(id -g) verilator/verilator:latest --cc test.v This method can only access files below the current directory. An alternative is setup the volume ``-workdir``. You can also work in the container by setting the entrypoint (don't forget to mount a volume if you want your work persistent): :: docker run -ti --entrypoint /bin/bash verilator/verilator:latest You can also use the container to build Verilator at a specific commit: :: docker build --build-arg SOURCE_COMMIT= . Internals --------- The Dockerfile builds Verilator and removes the tree when completed to reduce the image size. The entrypoint is a wrapper script (``verilator-wrap.sh``). That script 1. calls Verilator, and 2. copies the Verilated runtime files to the ``obj_dir`` or the ``-Mdir`` respectively. This allows the user to have the files to they may later build the C++ output with the matching runtime files. The wrapper also patches the Verilated Makefile accordingly. A hook is also defined and run by Docker Hub via automated builds. verilator-5.044/ci/docker/run/Dockerfile0000644000542200017500000000334515125463617020572 0ustar mahmoudyfreeshell# DESCRIPTION: Dockerfile for image to run Verilator inside # # Copyright 2020 by Stefan Wallentowitz. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 FROM ubuntu:24.04 RUN apt-get update \ && DEBIAN_FRONTEND=noninteractive \ && apt-get install --no-install-recommends -y \ autoconf \ bc \ bison \ build-essential \ ca-certificates \ ccache \ flex \ git \ help2man \ libfl2 \ libfl-dev \ libgoogle-perftools-dev \ numactl \ perl \ perl-doc \ python3 \ zlib1g \ zlib1g-dev \ && apt-get clean \ && rm -rf /var/lib/apt/lists/* ARG REPO=https://github.com/verilator/verilator ARG SOURCE_COMMIT=master WORKDIR /tmp # Add an exception for the linter, we want to cd here in one layer # to reduce the number of layers (and thereby size). # hadolint ignore=DL3003 RUN git clone "${REPO}" verilator && \ cd verilator && \ git checkout "${SOURCE_COMMIT}" && \ autoconf && \ ./configure && \ make && \ make install && \ cd .. && \ rm -r verilator && \ ccache -C COPY verilator-wrap.sh /usr/local/bin/verilator-wrap.sh WORKDIR /work ENTRYPOINT [ "/usr/local/bin/verilator-wrap.sh" ] verilator-5.044/ci/ci-pages.bash0000755000542200017500000001315515125463617017057 0ustar mahmoudyfreeshell#!/usr/bin/env bash # DESCRIPTION: Verilator: CI script for 'pages.yml', builds the GitHub Pages # # Copyright 2025 by Geza Lore. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # This scipt build the content of the GitHub Pages for the repository. # Currently this only hosts code coverage reports, but it would be possible to # add any other contents to the page in parallel here. # Developer note: You should be able to run this script in your local checkout # if you have GitHub CLI (command 'gh') setup, authenticated ('gh auth login'), # and have set a default repository ('gh repo set-default'). # Create pages root directory. The contents of this directory will be deployed # and served via GitHubPages readonly PAGES_ROOT=pages mkdir -p ${PAGES_ROOT} # Get the current repo URL - might differ on a fork readonly REPO_URL=$(gh repo view --json url --jq .url) # Set GITHUB_OUTPUT when run locally for testing if [[ -z "$GITHUB_OUTPUT" ]]; then GITHUB_OUTPUT=github-output.txt fi # Populates ${PAGES_ROOT}/coverage-reports compile_coverage_reports() { # We will process all runs up to and including this date. This is chosen to be # slightly less than the artifact retention period for simplicity. local OLDEST=$(date --date="28 days ago" --iso-8601=date) # Gather all coverage workflow runs within the time window gh run list -w coverage.yml --limit 1000 --created ">=${OLDEST}" --json "databaseId,event,status,conclusion,createdAt,number" > recentRuns.json echo @@@ Recent runs: jq "." recentRuns.json # Select completd runs that were not cancelled or skipped, sort by descending run number jq 'sort_by(-.number) | map(select(.status == "completed" and (.conclusion == "success" or .conclusion == "failure")))' recentRuns.json > completedRuns.json echo @@@ Completed with success or failure: jq "." completedRuns.json # Create artifacts root directory local ARTIFACTS_ROOT=artifacts mkdir -p ${ARTIFACTS_ROOT} # Create coverage reports root directory local COVERAGE_ROOT=${PAGES_ROOT}/coverage-reports mkdir -p ${COVERAGE_ROOT} # Create index page contents fragment local CONTENTS=contents.tmp echo > ${CONTENTS} # Run IDs of PR jobs processed local PR_RUN_IDS="" # Iterate over all unique event types that triggered the workflows for EVENT in $(jq -r 'map(.event) | sort | unique | .[]' completedRuns.json); do echo "@@@ Processing '${EVENT}' runs" # Emit section header if a report exists with this event type EMIT_SECTION_HEADER=1 # For each worfklow run that was triggered by this event type for RUN_ID in $(jq ".[] | select(.event == \"${EVENT}\") |.databaseId" completedRuns.json); do echo "@@@ Processing run ${RUN_ID}" # Extract the info of this run jq ".[] | select(.databaseId == $RUN_ID)" completedRuns.json > workflow.json jq "." workflow.json # Record run ID of PR job if [[ $EVENT == "pull_request" ]]; then if [[ -z "$PR_RUN_IDS" ]]; then PR_RUN_IDS="$RUN_ID" else PR_RUN_IDS="$PR_RUN_IDS,$RUN_ID" fi fi # Create workflow artifacts directory local ARTIFACTS_DIR=${ARTIFACTS_ROOT}/${RUN_ID} mkdir -p ${ARTIFACTS_DIR} # Download artifacts of this run, if exists gh run download ${RUN_ID} --name coverage-report --dir ${ARTIFACTS_DIR} || true ls -lsha ${ARTIFACTS_DIR} # Move on if no coverage report is available if [ ! -d ${ARTIFACTS_DIR}/report ]; then echo "No coverage report found" continue fi echo "Coverage report found" # Emit section header if [[ -n $EMIT_SECTION_HEADER ]]; then unset EMIT_SECTION_HEADER if [[ $EVENT == "pull_request" ]]; then echo "

Patch coverage reports for '${EVENT}' runs:

" >> ${CONTENTS} else echo "

Code coverage reports for '${EVENT}' runs:

" >> ${CONTENTS} fi fi # Create pages subdirectory mv ${ARTIFACTS_DIR}/report ${COVERAGE_ROOT}/${RUN_ID} # Add index page content local WORKFLOW_CREATED=$(jq -r '.createdAt' workflow.json) local WOFKRLOW_NUMBER=$(jq -r '.number' workflow.json) cat >> ${CONTENTS} <#${WOFKRLOW_NUMBER} | GitHub: ${RUN_ID} | started at: ${WORKFLOW_CREATED} CONTENTS_TEMPLATE if [ -e ${ARTIFACTS_DIR}/pr-number.txt ]; then local PRNUMBER=$(cat ${ARTIFACTS_DIR}/pr-number.txt) echo " | Pull request: #${PRNUMBER}" >> ${CONTENTS} fi echo "
" >> ${CONTENTS} done # Section break if [[ -z "$EMIT_SECTION_HEADER" ]]; then echo "
" >> ${CONTENTS} fi done # Write coverage report index.html cat > ${COVERAGE_ROOT}/index.html < Verilator CI coverage reports $(cat ${CONTENTS})

Assembled $(date --iso-8601=minutes --utc)

INDEX_TEMPLATE # Report size du -shc ${COVERAGE_ROOT}/* # Set output echo "coverage-pr-run-ids=${PR_RUN_IDS}" >> $GITHUB_OUTPUT } # Compilie coverage reports compile_coverage_reports; # You can build any other content here to be put under ${PAGES_ROOT} verilator-5.044/ci/ci-pages-notify.bash0000755000542200017500000000310715125463617020361 0ustar mahmoudyfreeshell#!/usr/bin/env bash # DESCRIPTION: Verilator: CI script for 'pages.yml', notifies PRs # # Copyright 2025 by Geza Lore. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Notify PRs via comment that their coverage reports are available # Get the current repo URL - might differ on a fork readonly REPO_URL=$(gh repo view --json url --jq .url) # Create artifacts root directory ARTIFACTS_ROOT=artifacts mkdir -p ${ARTIFACTS_ROOT} for RUN_ID in ${COVERAGE_PR_RUN_IDS//,/ }; do echo "@@@ Processing run ${RUN_ID}" # Create workflow artifacts directory ARTIFACTS_DIR=${ARTIFACTS_ROOT}/${RUN_ID} mkdir -p ${ARTIFACTS_DIR} # Download artifact of this run, if exists gh run download ${RUN_ID} --name coverage-pr-notification --dir ${ARTIFACTS_DIR} || true ls -lsha ${ARTIFACTS_DIR} # Move on if no notification is required if [ ! -f ${ARTIFACTS_DIR}/pr-number.txt ]; then echo "No notification found" continue fi echo "Posting notification found" cat ${ARTIFACTS_DIR}/body.txt gh pr comment $(cat ${ARTIFACTS_DIR}/pr-number.txt) --body-file ${ARTIFACTS_DIR}/body.txt # Get the artifact ID ARTIFACT_ID=$(gh api "repos/{owner}/{repo}/actions/runs/${RUN_ID}/artifacts" --jq '.artifacts[] | select(.name == "coverage-pr-notification") | .id') # Delete it, so we only notify once gh api --method DELETE "repos/{owner}/{repo}/actions/artifacts/${ARTIFACT_ID}" done verilator-5.044/ci/ci-win-test.ps10000644000542200017500000000127215125463617017312 0ustar mahmoudyfreeshell# DESCRIPTION: Verilator: CI Windows Power Shell - Verilate a test # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ################################################################################ Set-PSDebug -Trace 1 cd install $Env:VERILATOR_ROOT=$PWD cd examples/cmake_tracing_c mkdir build cd build cmake .. cmake --build . --config Release -j 3 # TODO put this back in, see issue# 5163 # Release/example.exe cd .. Remove-Item -path build -recurse verilator-5.044/ci/ci-script.bash0000755000542200017500000001622415125463617017264 0ustar mahmoudyfreeshell#!/usr/bin/env bash # DESCRIPTION: Verilator: CI main job script # # Copyright 2020 by Geza Lore. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ################################################################################ # This is the main script executed in the 'script' phase by all jobs. We use a # single script to keep the CI setting simple. We pass job parameters via # environment variables using 'env' keys. ################################################################################ set -e set -x fatal() { echo "ERROR: $(basename "$0"): $1" >&2; exit 1; } if [ "$CI_OS_NAME" = "linux" ]; then export MAKE=make NPROC=$(nproc) elif [ "$CI_OS_NAME" = "osx" ]; then export MAKE=make NPROC=$(sysctl -n hw.logicalcpu) # Disable ccache, doesn't always work in GitHub Actions export OBJCACHE= elif [ "$CI_OS_NAME" = "freebsd" ]; then export MAKE=gmake NPROC=$(sysctl -n hw.ncpu) else fatal "Unknown os: '$CI_OS_NAME'" fi NPROC=$(expr $NPROC '+' 1) if [ "$CI_BUILD_STAGE_NAME" = "build" ]; then ############################################################################## # Build verilator autoconf CONFIGURE_ARGS="--enable-longtests --enable-ccwarn" if [ "$CI_DEV_ASAN" = 1 ]; then CONFIGURE_ARGS="$CONFIGURE_ARGS --enable-dev-asan" CXX="$CXX -DVL_LEAK_CHECKS" fi if [ "$CI_DEV_GCOV" = 1 ]; then CONFIGURE_ARGS="$CONFIGURE_ARGS --enable-dev-gcov" fi ./configure $CONFIGURE_ARGS --prefix="$INSTALL_DIR" ccache -z "$MAKE" -j "$NPROC" -k # 22.04: ccache -s -v ccache -s if [ "$CI_OS_NAME" = "osx" ]; then file bin/verilator_bin file bin/verilator_bin_dbg md5 bin/verilator_bin md5 bin/verilator_bin_dbg stat bin/verilator_bin stat bin/verilator_bin_dbg fi elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then ############################################################################## # Run tests export VERILATOR_TEST_NO_CONTRIBUTORS=1 # Separate workflow check export VERILATOR_TEST_NO_LINT_PY=1 # Separate workflow check if [ "$CI_OS_NAME" = "osx" ]; then export VERILATOR_TEST_NO_GDB=1 # Pain to get GDB to work on OS X # TODO below may no longer be required as configure checks for -pg export VERILATOR_TEST_NO_GPROF=1 # Apple Clang has no -pg # export PATH="/Applications/gtkwave.app/Contents/Resources/bin:$PATH" # fst2vcd file bin/verilator_bin file bin/verilator_bin_dbg md5 bin/verilator_bin md5 bin/verilator_bin_dbg stat bin/verilator_bin stat bin/verilator_bin_dbg # For some reason, the dbg exe is corrupted by this point ('file' reports # it as data rather than a Mach-O). Unclear if this is an OS X issue or # CI's. Remove the file and re-link... rm bin/verilator_bin_dbg "$MAKE" -j "$NPROC" -k elif [ "$CI_OS_NAME" = "freebsd" ]; then export VERILATOR_TEST_NO_GDB=1 # Disable for now, ideally should run # TODO below may no longer be required as configure checks for -pg export VERILATOR_TEST_NO_GPROF=1 # gprof is a bit different on FreeBSD, disable fi TEST_REGRESS=test_regress if [ "$CI_RELOC" == 1 ]; then # Testing that the installation is relocatable. "$MAKE" install mkdir -p "$RELOC_DIR" mv "$INSTALL_DIR" "$RELOC_DIR/relocated-install" export VERILATOR_ROOT="$RELOC_DIR/relocated-install/share/verilator" TEST_REGRESS="$RELOC_DIR/test_regress" mv test_regress "$TEST_REGRESS" NODIST="$RELOC_DIR/nodist" mv nodist "$NODIST" # Feeling brave? find . -delete ls -la . fi # Run the specified test ccache -z case $TESTS in dist-vlt-0) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--dist --vlt --driver-clean" DRIVER_HASHSET=--hashset=0/4 ;; dist-vlt-1) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--dist --vlt --driver-clean" DRIVER_HASHSET=--hashset=1/4 ;; dist-vlt-2) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--dist --vlt --driver-clean" DRIVER_HASHSET=--hashset=2/4 ;; dist-vlt-3) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--dist --vlt --driver-clean" DRIVER_HASHSET=--hashset=3/4 ;; vltmt-0) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt --driver-clean" DRIVER_HASHSET=--hashset=0/3 ;; vltmt-1) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt --driver-clean" DRIVER_HASHSET=--hashset=1/3 ;; vltmt-2) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt --driver-clean" DRIVER_HASHSET=--hashset=2/3 ;; coverage-dist) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--dist" ;; coverage-vlt-0) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt" DRIVER_HASHSET=--hashset=0/10 ;; coverage-vlt-1) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt" DRIVER_HASHSET=--hashset=1/10 ;; coverage-vlt-2) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt" DRIVER_HASHSET=--hashset=2/10 ;; coverage-vlt-3) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt" DRIVER_HASHSET=--hashset=3/10 ;; coverage-vlt-4) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt" DRIVER_HASHSET=--hashset=4/10 ;; coverage-vlt-5) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt" DRIVER_HASHSET=--hashset=5/10 ;; coverage-vlt-6) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt" DRIVER_HASHSET=--hashset=6/10 ;; coverage-vlt-7) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt" DRIVER_HASHSET=--hashset=7/10 ;; coverage-vlt-8) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt" DRIVER_HASHSET=--hashset=8/10 ;; coverage-vlt-9) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt" DRIVER_HASHSET=--hashset=9/10 ;; coverage-vltmt-0) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt" DRIVER_HASHSET=--hashset=0/10 ;; coverage-vltmt-1) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt" DRIVER_HASHSET=--hashset=1/10 ;; coverage-vltmt-2) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt" DRIVER_HASHSET=--hashset=2/10 ;; coverage-vltmt-3) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt" DRIVER_HASHSET=--hashset=3/10 ;; coverage-vltmt-4) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt" DRIVER_HASHSET=--hashset=4/10 ;; coverage-vltmt-5) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt" DRIVER_HASHSET=--hashset=5/10 ;; coverage-vltmt-6) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt" DRIVER_HASHSET=--hashset=6/10 ;; coverage-vltmt-7) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt" DRIVER_HASHSET=--hashset=7/10 ;; coverage-vltmt-8) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt" DRIVER_HASHSET=--hashset=8/10 ;; coverage-vltmt-9) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt" DRIVER_HASHSET=--hashset=9/10 ;; *) fatal "Unknown test: $TESTS" ;; esac # To see load average (1 minute, 5 minute, 15 minute) uptime # 22.04: ccache -s -v ccache -s else ############################################################################## # Unknown build stage fatal "Unknown build stage: '$CI_BUILD_STAGE_NAME'" fi verilator-5.044/ci/ci-win-compile.ps10000644000542200017500000000165215125463617017765 0ustar mahmoudyfreeshell# DESCRIPTION: Verilator: CI Windows Power Shell - Compile Verilator # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ################################################################################ Set-PSDebug -Trace 1 if (-Not (Test-Path $PWD/../.ccache/win_bison.exe)) { git clone --depth 1 https://github.com/lexxmark/winflexbison cd winflexbison mkdir build cd build cmake .. --install-prefix $PWD/../../../.ccache cmake --build . --config Release -j 3 cmake --install . --prefix $PWD/../../../.ccache cd ../.. } mkdir build cd build cmake .. --install-prefix $PWD/../install cmake --build . --config Release -j 3 cmake --install . --prefix $PWD/../install verilator-5.044/ci/ci-install.bash0000755000542200017500000001134315125463617017423 0ustar mahmoudyfreeshell#!/usr/bin/env bash # DESCRIPTION: Verilator: CI dependency install script # # Copyright 2020 by Geza Lore. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ################################################################################ # This script runs in the 'install' phase of all jobs, in all stages. We try to # minimize the time spent in this by selectively installing only the components # required by the particular build stage. ################################################################################ set -e set -x cd $(dirname "$0")/.. # Avoid occasional cpan failures "Issued certificate has expired." export PERL_LWP_SSL_VERIFY_HOSTNAME=0 echo "check_certificate = off" >> ~/.wgetrc fatal() { echo "ERROR: $(basename "$0"): $1" >&2; exit 1; } if [ "$CI_OS_NAME" = "linux" ]; then MAKE=make elif [ "$CI_OS_NAME" = "osx" ]; then MAKE=make elif [ "$CI_OS_NAME" = "freebsd" ]; then MAKE=gmake else fatal "Unknown os: '$CI_OS_NAME'" fi if [ "$CI_OS_NAME" = "linux" ]; then # Avoid slow "processing triggers for man db" echo "path-exclude /usr/share/doc/*" | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc echo "path-exclude /usr/share/man/*" | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc echo "path-exclude /usr/share/info/*" | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc fi install-vcddiff() { TMP_DIR="$(mktemp -d)" git clone https://github.com/veripool/vcddiff "$TMP_DIR" git -C "${TMP_DIR}" checkout dca845020668887fd13498c772939814d9264fd5 "$MAKE" -C "${TMP_DIR}" sudo cp "${TMP_DIR}/vcddiff" /usr/local/bin } if [ "$CI_BUILD_STAGE_NAME" = "build" ]; then ############################################################################## # Dependencies of jobs in the 'build' stage, i.e.: packages required to # build Verilator if [ "$CI_OS_NAME" = "linux" ]; then sudo apt-get update || sudo apt-get update sudo apt-get install ccache help2man libfl-dev || sudo apt-get install ccache help2man libfl-dev if [[ ! "$CI_RUNS_ON" =~ "ubuntu-22.04" ]]; then # Some conflict of libunwind verison on 22.04, can live without it for now sudo apt-get install libgoogle-perftools-dev || sudo apt-get install libgoogle-perftools-dev fi if [[ "$CI_RUNS_ON" =~ "ubuntu-20.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-22.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-24.04" ]]; then sudo apt-get install libsystemc libsystemc-dev || sudo apt-get install libsystemc libsystemc-dev fi if [[ "$CI_RUNS_ON" =~ "ubuntu-22.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-24.04" ]]; then sudo apt-get install bear mold || sudo apt-get install bear mold fi elif [ "$CI_OS_NAME" = "osx" ]; then brew update brew install ccache perl gperftools autoconf bison flex help2man elif [ "$CI_OS_NAME" = "freebsd" ]; then sudo pkg install -y autoconf bison ccache gmake perl5 else fatal "Unknown os: '$CI_OS_NAME'" fi if [ -n "$CCACHE_DIR" ]; then mkdir -p "$CCACHE_DIR" fi elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then ############################################################################## # Dependencies of jobs in the 'test' stage, i.e.: packages required to # run the tests if [ "$CI_OS_NAME" = "linux" ]; then sudo apt-get update || sudo apt-get update # libfl-dev needed for internal coverage's test runs sudo apt-get install gdb gtkwave lcov libfl-dev ccache jq z3 || sudo apt-get install gdb gtkwave lcov libfl-dev ccache jq z3 # Required for test_regress/t/t_dist_attributes.py if [[ "$CI_RUNS_ON" =~ "ubuntu-22.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-24.04" ]]; then sudo apt-get install python3-clang mold || sudo apt-get install python3-clang mold fi if [[ "$CI_RUNS_ON" =~ "ubuntu-20.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-22.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-24.04" ]]; then sudo apt-get install libsystemc-dev || sudo apt-get install libsystemc-dev fi elif [ "$CI_OS_NAME" = "osx" ]; then brew update # brew cask install gtkwave # fst2vcd hangs at launch, so don't bother brew install ccache perl jq z3 elif [ "$CI_OS_NAME" = "freebsd" ]; then # fst2vcd fails with "Could not open '', exiting." sudo pkg install -y ccache gmake perl5 python3 jq z3 else fatal "Unknown os: '$CI_OS_NAME'" fi # Common installs install-vcddiff # Workaround -fsanitize=address crash sudo sysctl -w vm.mmap_rnd_bits=28 else ############################################################################## # Unknown build stage fatal "Unknown build stage: '$CI_BUILD_STAGE_NAME'" fi verilator-5.044/verilator-config-version.cmake.in0000644000542200017500000000166015125463617022474 0ustar mahmoudyfreeshell###################################################################### # # DESCRIPTION: CMake version configuration file for Verilator # # This allows specifying a minimum Verilator version. # Include it in your CMakeLists.txt using: # # find_package(verilator 4.0) # # Copyright 2003-2026 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### set(PACKAGE_VERSION "@PACKAGE_VERSION_NUMBER@") if(PACKAGE_VERSION VERSION_LESS PACKAGE_FIND_VERSION) set(PACKAGE_VERSION_COMPATIBLE FALSE) else() set(PACKAGE_VERSION_COMPATIBLE TRUE) if(PACKAGE_FIND_VERSION STREQUAL PACKAGE_VERSION) set(PACKAGE_VERSION_EXACT TRUE) endif() endif() verilator-5.044/configure.ac0000644000542200017500000006456215125463617016430 0ustar mahmoudyfreeshell# DESCRIPTION: Process this file with autoconf to produce a configure script. # # Copyright 2003-2026 by Wilson Snyder. Verilator is free software; you # can redistribute it and/or modify it under the terms of either the GNU Lesser # General Public License Version 3 or the Perl Artistic License Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # When releasing, also update header of Changes file, and CMakeLists.txt, # and commit using "devel release" or "Version bump" message # Then 'make distclean' 'autoconf' './configure' 'make' 'make test' # Then 'make maintainer-dist' #AC_INIT([Verilator],[#.### YYYY-MM-DD]) #AC_INIT([Verilator],[#.### devel]) AC_INIT([Verilator],[5.044 2026-01-01], [https://verilator.org], [verilator],[https://verilator.org]) AC_CONFIG_HEADERS(src/config_package.h) AC_CONFIG_FILES(Makefile src/Makefile src/Makefile_obj include/verilated.mk include/verilated_config.h verilator.pc verilator-config.cmake verilator-config-version.cmake) # Version AC_MSG_RESULT([configuring for $PACKAGE_STRING]) PACKAGE_VERSION_NUMBER=`AS_ECHO("$PACKAGE_VERSION") | sed 's/ .*//g'` AC_SUBST(PACKAGE_VERSION_NUMBER) AC_DEFINE_UNQUOTED([PACKAGE_VERSION_NUMBER_STRING],["$PACKAGE_VERSION_NUMBER"],[Package version as a number]) VERILATOR_VERSION_INTEGER=`AS_ECHO("$PACKAGE_VERSION") | [sed 's/\([0-9]\)\.\([0-9][0-9][0-9]\) .*/\1\2000/g']` AC_SUBST(VERILATOR_VERSION_INTEGER) AC_DEFINE_UNQUOTED([PACKAGE_VERSION_STRING_CHAR], [static const char* const PACKAGE_STRING_UNUSED = "$PACKAGE_STRING";], [Package version as a number]) AC_SUBST(PACKAGE_VERSION_STRING_CHAR) ###################################################################### ## Arguments/flag checking # Ignore automake flags passed by Ubuntu builds AC_ARG_ENABLE([dependency-tracking], [AS_HELP_STRING([--disable-dependency-tracking], [ignored])]) AC_ARG_ENABLE([maintainer-mode], [AS_HELP_STRING([--enable-maintainer-mode], [ignored])]) AC_ARG_ENABLE([silent-rules], [AS_HELP_STRING([--disable-silent-rules], [ignored])]) # Flag to enable linking specific libraries statically AC_MSG_CHECKING(whether to perform partial static linking of Verilator binary) AC_ARG_ENABLE([partial-static], [AS_HELP_STRING([--disable-partial-static], [By default, for Verilation performance, Verilator is linked against some of its dependencies statically. Use this to link the Verilator binary fully dynamically.])], [case "${enableval}" in yes) CFG_ENABLE_PARTIAL_STATIC=yes ;; no) CFG_ENABLE_PARTIAL_STATIC=no ;; *) AC_MSG_ERROR([bad value '${enableval}' for --disable-partial-static]) ;; esac], CFG_ENABLE_PARTIAL_STATIC=yes) AC_MSG_RESULT($CFG_ENABLE_PARTIAL_STATIC) # Flag to enable compiling with AddressSanitizer AC_MSG_CHECKING(whether to use AddressSanitizer) AC_ARG_ENABLE([dev-asan], [AS_HELP_STRING([--enable-dev-asan], [Enable compiling Verilator with ASAN AddressSanitizer for memory error detection. This disables tcmalloc. Does not affect Verilated models using ASAN.])], [case "${enableval}" in yes) CFG_WITH_DEV_ASAN=yes ;; no) CFG_WITH_DEV_ASAN=no ;; *) AC_MSG_ERROR([bad value '${enableval}' for --enable-dev-asan]) ;; esac], CFG_WITH_DEV_ASAN=no) AC_MSG_RESULT($CFG_WITH_DEV_ASAN) # Flag to enable linking Verilator with tcmalloc if available AC_MSG_CHECKING(whether to use tcmalloc) AC_ARG_ENABLE([tcmalloc], [AS_HELP_STRING([--enable-tcmalloc], [Use libtcmalloc_minimal for faster dynamic memory management in Verilator binary @<:@default=check@:>@])], [case "${enableval}" in yes) CFG_WITH_TCMALLOC=yes ;; no) CFG_WITH_TCMALLOC=no ;; *) AC_MSG_ERROR([bad value '${enableval}' for --enable-tcmalloc]) ;; esac], [CFG_WITH_TCMALLOC=check;]) if test "$CFG_WITH_DEV_ASAN" = "yes"; then CFG_WITH_TCMALLOC=no AC_MSG_RESULT("disabled by --enable-dev-asan") else AC_MSG_RESULT($CFG_WITH_TCMALLOC) fi # Flag to enable code coverage build with gcov AC_MSG_CHECKING(whether to build for gcov code coverage collection) AC_ARG_ENABLE([dev-gcov], [AS_HELP_STRING([--enable-dev-gcov], [Build Verilator for code coverage collection with gcov. For developers only.])], [case "${enableval}" in yes) CFG_WITH_DEV_GCOV=yes ;; no) CFG_WITH_DEV_GCOV=no ;; *) AC_MSG_ERROR([bad value '${enableval}' for --enable-dev-gcov]) ;; esac], CFG_WITH_DEV_GCOV=no) AC_SUBST(CFG_WITH_DEV_GCOV) AC_MSG_RESULT($CFG_WITH_DEV_GCOV) # Special Substitutions - CFG_WITH_DEFENV AC_MSG_CHECKING(whether to use hardcoded paths) AC_ARG_ENABLE([defenv], [AS_HELP_STRING([--disable-defenv], [disable using some hardcoded data paths extracted from some default environment variables (the default is to use hardcoded paths) in Verilator binary])], [case "${enableval}" in yes) CFG_WITH_DEFENV=yes ;; no) CFG_WITH_DEFENV=no ;; *) AC_MSG_ERROR([bad value ${enableval} for --disable-defenv]) ;; esac], CFG_WITH_DEFENV=yes) AC_SUBST(CFG_WITH_DEFENV) AC_MSG_RESULT($CFG_WITH_DEFENV) # Special Substitutions - CFG_WITH_CCWARN AC_MSG_CHECKING(whether to show and stop on compilation warnings) AC_ARG_ENABLE([ccwarn], [AS_HELP_STRING([--enable-ccwarn], [enable showing and stopping on compilation warnings in Verilator binary and Verilated makefiles])], [case "${enableval}" in yes) CFG_WITH_CCWARN=yes ;; no) CFG_WITH_CCWARN=no ;; *) AC_MSG_ERROR([bad value ${enableval} for --enable-ccwarn]) ;; esac], [case "x${VERILATOR_AUTHOR_SITE}" in x) CFG_WITH_CCWARN=no ;; *) CFG_WITH_CCWARN=yes ;; esac] ) AC_SUBST(CFG_WITH_CCWARN) AC_MSG_RESULT($CFG_WITH_CCWARN) # Special Substitutions - CFG_WITH_LONGTESTS AC_MSG_CHECKING(whether to run long tests) AC_ARG_ENABLE([longtests], [AS_HELP_STRING([--enable-longtests], [enable running long developer tests])], [case "${enableval}" in yes) CFG_WITH_LONGTESTS=yes ;; no) CFG_WITH_LONGTESTS=no ;; *) AC_MSG_ERROR([bad value ${enableval} for --enable-longtests]) ;; esac], [case "x${VERILATOR_AUTHOR_SITE}" in x) CFG_WITH_LONGTESTS=no ;; *) CFG_WITH_LONGTESTS=yes ;; esac] ) AC_SUBST(CFG_WITH_LONGTESTS) AC_MSG_RESULT($CFG_WITH_LONGTESTS) AC_CHECK_PROG(HAVE_Z3,z3,yes) AC_CHECK_PROG(HAVE_CVC5,cvc5,yes) AC_CHECK_PROG(HAVE_CVC4,cvc4,yes) # Special Substitutions - CFG_WITH_SOLVER AC_MSG_CHECKING(for SMT solver) AC_ARG_WITH([solver], [AS_HELP_STRING([--with-solver='z3 --in'], [set default SMT solver for constrained randomization])], [CFG_WITH_SOLVER="${withval}"], [CFG_WITH_SOLVER=no if test "x$HAVE_Z3" = "xyes"; then CFG_WITH_SOLVER="z3 --in" elif test "x$HAVE_CVC5" = "xyes"; then CFG_WITH_SOLVER="cvc5 --incremental" elif test "x$HAVE_CVC4" = "xyes"; then CFG_WITH_SOLVER="cvc4 --lang=smt2 --incremental" fi] ) AC_SUBST(CFG_WITH_SOLVER) AC_MSG_RESULT($CFG_WITH_SOLVER) ###################################################################### ## Compiler checks AC_MSG_RESULT([compiler CXX inbound is set to... $CXX]) # Compiler flags (ensure they are not empty to avoid configure defaults) CFLAGS="$CFLAGS " CPPFLAGS="$CPPFLAGS " CXXFLAGS="$CXXFLAGS " LDFLAGS="$LDFLAGS " # Checks for programs. AC_PROG_CC AC_PROG_CXX AC_PROG_INSTALL AC_LANG_PUSH(C++) CFG_CXX_VERSION=`$CXX --version | head -1` AC_MSG_RESULT([compiler version... $CXX --version = $CFG_CXX_VERSION]) AC_SUBST(CFG_CXX_VERSION) AC_MSG_CHECKING([that C++ compiler can compile simple program]) AC_RUN_IFELSE( [AC_LANG_SOURCE([int main() { return 0; }])], AC_MSG_RESULT(yes), AC_MSG_RESULT(no);AC_MSG_ERROR([a working C++ compiler is required]), AC_MSG_RESULT(yes)) AC_CHECK_PROG(AR,ar,ar) if test "x$AR" = "x" ; then AC_MSG_ERROR([Cannot find "ar" in your PATH, please install it]) fi AC_CHECK_PROG(PERL,perl,perl) if test "x$PERL" = "x" ; then AC_MSG_ERROR([Cannot find "perl" in your PATH, please install it]) fi AC_CHECK_PROG(PYTHON3,python3,python3) if test "x$PYTHON3" = "x" ; then AC_MSG_ERROR([Cannot find "python3" in your PATH, please install it]) fi python3_version=$($PYTHON3 --version | head -1) AC_MSG_RESULT([$PYTHON3 --version = $python3_version]) AC_CHECK_PROG(LEX,flex,flex) if test "x$LEX" = "x" ; then AC_MSG_ERROR([Cannot find "flex" in your PATH, please install it]) fi flex_version=$($LEX --version | head -1) AC_MSG_RESULT([$LEX --version = $flex_version]) AC_CHECK_PROG(YACC,bison,bison) if test "x$YACC" = "x" ; then AC_MSG_ERROR([Cannot find "bison" in your PATH, please install it]) fi bison_version=$($YACC --version | head -1) AC_MSG_RESULT([$YACC --version = $bison_version]) AC_CHECK_PROG(OBJCACHE,ccache,ccache) if test "x$OBJCACHE" != "x" ; then objcache_version=$($OBJCACHE --version | head -1) AC_MSG_RESULT([objcache is $OBJCACHE --version = $objcache_version]) fi # Checks for libraries. # Checks for typedefs, structures AC_CHECK_TYPE(size_t,unsigned int) AC_TYPE_SIZE_T # Checks for compiler characteristics. AC_C_INLINE AC_LINK_IFELSE( [AC_LANG_PROGRAM([#include ], [[int* a=new int; delete a; ]])], [], [AC_MSG_ERROR([$CXX does not seem to successfully compile a simple C++ program])]) AC_DEFUN([_MY_CXX_CHECK_FLAG], [# _MY_CXX_CHECK_FLAG(flag) -- Check if compiler supports specific options # Set $_my_result appropriately ACO_SAVE_CXXFLAGS="$CXXFLAGS" # -Werror needed otherwise unknown -Wno-div-by-zero won't report problems # new/delete is needed to find -faligned-new link problem on Darwin CXXFLAGS="$CXXFLAGS $1 -Werror" AC_MSG_CHECKING([whether $CXX accepts $1]) AC_LINK_IFELSE( [AC_LANG_PROGRAM([#include ], [[int* a=new int; delete a; ]])], [_my_result=yes if test -s conftest.err; then if grep -e "$1" conftest.err >/dev/null; then _my_result=no fi fi], [_my_result=no]) # GCC is annoying, trying to be helpful, it postpones unknown -Wno- # options if there's no error We want to see them regardless, so try # forcing an error and see if we get a gcc warning AC_COMPILE_IFELSE( [AC_LANG_PROGRAM([[an_error "intentional-error-for-test.h" ]],[])], [], # Ignore ok exit [if test -s conftest.err; then if grep -e "$1" conftest.err >/dev/null; then _my_result=no fi fi]) AC_MSG_RESULT($_my_result) CXXFLAGS="$ACO_SAVE_CXXFLAGS" ]) AC_DEFUN([_MY_CXX_CHECK_IFELSE], [# _MY_CXX_CHECK_IFELSE(option,action-if-supported,action-if-not-supported) # Check if compiler supports specific option. If it does, # do action-if-supported, otherwise do action-if-not-supported _MY_CXX_CHECK_FLAG($1) if test "$_my_result" = "yes" ; then true $2 else true $3 fi ]) AC_DEFUN([_MY_CXX_CHECK_SET], [# _MY_CXX_CHECK_SET(variable,option) # Check if compiler supports specific option. If it does, # set variable to option, only if not previously set. if test "$$1" = ""; then _MY_CXX_CHECK_IFELSE($2, $1="$2") fi ]) AC_DEFUN([_MY_CXX_CHECK_OPT], [# _MY_CXX_CHECK_OPT(variable,option) # Check if compiler supports specific option. If it does, # append option to variable _MY_CXX_CHECK_IFELSE($2, $1="$$1 $2") ]) AC_DEFUN([_MY_CXX_CHECK_CORO_SET], [# _MY_CXX_CHECK_CORO_SET(variable,option) # Check if compiler supports coroutines with specific option. If it does, # set variable to option, only if not previously set. # Define HAVE_COROUTINES if supported. if test "$$1" = ""; then if test "$2" != ""; then _my_msg_opt=" with $2" else _my_msg_opt="" fi AC_MSG_CHECKING([whether coroutines are supported by $CXX$_my_msg_opt]) ACO_SAVE_CXXFLAGS="$CXXFLAGS" CXXFLAGS="$CXXFLAGS $2" AC_LINK_IFELSE( [AC_LANG_PROGRAM([ #if defined(__clang__) && !defined(__cpp_impl_coroutine) #define __cpp_impl_coroutine 1 #endif #include ],[[std::coroutine_handle<> h;]])], [_my_result=yes], [AC_LINK_IFELSE( [AC_LANG_PROGRAM( [#include ], [[std::experimental::coroutine_handle<> h;]])], [_my_result=yes], [_my_result=no])]) AC_MSG_RESULT($_my_result) CXXFLAGS="$ACO_SAVE_CXXFLAGS" if test "$_my_result" = "yes" ; then $1="$2" AC_DEFINE([HAVE_COROUTINES],[1],[Defined if coroutines are supported by $CXX]) fi fi ]) AC_DEFUN([_MY_LDLIBS_CHECK_FLAG], [# _MY_LDLIBS_CHECK_FLAG(flag) -- Check if linker supports specific options # Set $_my_result appropriately ACO_SAVE_LIBS="$LIBS" LIBS="$LIBS $1" AC_MSG_CHECKING([whether $CXX linker accepts $1]) AC_LINK_IFELSE( [AC_LANG_PROGRAM([[]])], [_my_result=yes if test -s conftest.err; then if grep -e "$1" conftest.err >/dev/null; then _my_result=no fi fi], [_my_result=no]) AC_MSG_RESULT($_my_result) LIBS="$ACO_SAVE_LIBS" ]) AC_DEFUN([_MY_LDLIBS_CHECK_IFELSE], [# _MY_LDLIBS_CHECK_IFELSE(flag,action-if-supported,action-if-not-supported) # Check if linker supports specific flag, if it does do action-if-supported # otherwise do action-if-not-supported _MY_LDLIBS_CHECK_FLAG($1) if test "$_my_result" = "yes" ; then true $2 else true $3 fi ]) AC_DEFUN([_MY_LDLIBS_CHECK_OPT], [# _MY_LDLIBS_CHECK_OPT(variable, flag) -- Check if linker supports specific # options. If it does, append flag to variable. _MY_LDLIBS_CHECK_IFELSE($2, $1="$$1 $2") ]) # Add the coverage flags early as they influence later checks. if test "$CFG_WITH_DEV_GCOV" = "yes"; then _MY_CXX_CHECK_OPT(CXX,--coverage) # Otherwise inline may not show as uncovered # If we use this then e.g. verilated.h functions properly show up # if unused. # However, VerilatedSerialize::write then changes from covered # to uncovered (in G++ 9.3.0) even with all inlining turned off. # Having false negative coverage is more effort then missing negatives. # Also this seems to explode the runtime (since a lot more data). # _MY_CXX_CHECK_OPT(CXX,-fkeep-inline-functions) # Otherwise static may not show as uncovered _MY_CXX_CHECK_OPT(CXX,-fkeep-static-functions) # Similarly for inline functions. - This is too slow. See Makefile_obj instead. #_MY_CXX_CHECK_OPT(CXX,-fkeep-inline-functions) # Make sure profiling is thread-safe _MY_CXX_CHECK_OPT(CXX,-fprofile-update=atomic) # Ensure data files can be written from parallel runs _MY_CXX_CHECK_OPT(CXX,-fprofile-reproducible=parallel-runs) # Save source files as absolute paths in gcno files _MY_CXX_CHECK_OPT(CXX,-fprofile-abs-path) # Define so compiled code can know _MY_CXX_CHECK_OPT(CXX,-DVL_GCOV) AC_DEFINE([HAVE_DEV_GCOV],[1],[Defined if compiled with code coverage collection for gcov])] fi AC_SUBST(HAVE_DEV_GCOV) # Compiler flags to enable profiling _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_PROFILE,-pg) AC_SUBST(CFG_CXXFLAGS_PROFILE) # Flag to select newest language standard supported # Macros work such that first option that passes is the one we take # Currently enable c++17/c++14 due to packaged SystemC dependency # c++17 is the newest that Verilator is regularly tested to support # c++14 is the oldest that Verilator supports # gnu is required for Cygwin to compile verilated.h successfully #_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++20) #_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++20) _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++17) _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++17) _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++14) _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++14) AC_SUBST(CFG_CXXFLAGS_STD_NEWEST) # Flags for compiling Verilator internals including parser, and Verilated files # These turn on extra warnings and are only used with 'configure --enable-ccwarn' _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_WEXTRA,-Wextra) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_WEXTRA,-Wfloat-conversion) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_WEXTRA,-Wlogical-op) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_WEXTRA,-Wthread-safety) AC_SUBST(CFG_CXXFLAGS_WEXTRA) # Flags for coroutine support for dynamic scheduling _MY_CXX_CHECK_CORO_SET(CFG_CXXFLAGS_COROUTINES, "") _MY_CXX_CHECK_CORO_SET(CFG_CXXFLAGS_COROUTINES,-fcoroutines-ts) _MY_CXX_CHECK_CORO_SET(CFG_CXXFLAGS_COROUTINES,-fcoroutines) _MY_CXX_CHECK_CORO_SET(CFG_CXXFLAGS_COROUTINES,-fcoroutines-ts -Wno-deprecated-experimental-coroutine) _MY_CXX_CHECK_CORO_SET(CFG_CXXFLAGS_COROUTINES,-std=gnu++20) AC_SUBST(CFG_CXXFLAGS_COROUTINES) AC_SUBST(HAVE_COROUTINES) # Flags for compiling Verilator internals including parser always if test "$CFG_WITH_DEV_ASAN" = "yes"; then _MY_CXX_CHECK_IFELSE(-fsanitize=address -DVL_ASAN, [CFG_CXXFLAGS_SRC="$CFG_CXXFLAGS_SRC -fsanitize=address -DVL_ASAN" CFG_LDFLAGS_SRC="$CFG_LDFLAGS_SRC -fsanitize=address" AC_DEFINE([HAVE_DEV_ASAN],[1],[Defined if built with AddresSanitizer])] ) fi AC_SUBST(HAVE_DEV_ASAN) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Qunused-arguments) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Wno-shadow) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Wno-unused-parameter) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Xclang -fno-pch-timestamp) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-faligned-new) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-fno-exceptions) AC_SUBST(CFG_CXXFLAGS_SRC) # Flags for compiling Verilator parser always (in addition to above CFG_CXXFLAGS_SRC) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_PARSER,-Wno-char-subscripts) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_PARSER,-Wno-null-conversion) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_PARSER,-Wno-parentheses-equality) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_PARSER,-Wno-unused) AC_SUBST(CFG_CXXFLAGS_PARSER) # Flags for compiling the debug version of Verilator (in addition to above CFG_CXXFLAGS_SRC) if test "$CFG_WITH_DEV_GCOV" = "no"; then # Do not optimize for the coverage build _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_DBG,-Og) fi _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_DBG,-ggdb) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_DBG,-gz) AC_SUBST(CFG_CXXFLAGS_DBG) # Flags for linking the debug version of Verilator (in addition to above CFG_LDFLAGS_SRC) _MY_LDLIBS_CHECK_OPT(CFG_LDFLAGS_DBG,-gz) AC_SUBST(CFG_LDFLAGS_DBG) # Flags for compiling the optimized version of Verilator (in addition to above CFG_CXXFLAGS_SRC) if test "$CFG_WITH_DEV_GCOV" = "no"; then # Do not optimize for the coverage build _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_OPT,-O3) fi AC_SUBST(CFG_CXXFLAGS_OPT) # Flags for Verilated makefile # For example, -Wno-div-by-zero isn't in 4.1.2 # Random code often does / 0. Unfortunately VL_DIV_I(0,0) will warn # without this flag, even though there's a conditional to prevent the divide. # We still don't add no-div-by-zero as it throws message to stdout, though doesn't die. #_MY_CXX_CHECK_OPT(-Wno-div-by-zero) # For some reason -faligned-new does not work under Travis w/ clang but the # configure test doesn't catch this either AS_IF([test "x$TRAVIS_COMPILER" != xclang], [_MY_CXX_CHECK_OPT(CFG_CXXFLAGS_NO_UNUSED,-faligned-new)]) CFG_CXX_FLAGS_CMAKE="-faligned-new" m4_foreach([cflag],[ [-fbracket-depth=4096], [-fcf-protection=none], [-Xclang -fno-pch-timestamp], [-mno-cet], [-Qunused-arguments], [-Wno-bool-operation], [-Wno-c++11-narrowing], [-Wno-constant-logical-operand], [-Wno-int-in-bool-context], [-Wno-non-pod-varargs], [-Wno-parentheses-equality], [-Wno-shadow], [-Wno-sign-compare], [-Wno-subobject-linkage], [-Wno-tautological-bitwise-compare], [-Wno-tautological-compare], [-Wno-uninitialized], [-Wno-unused-but-set-parameter], [-Wno-unused-but-set-variable], [-Wno-unused-parameter], [-Wno-unused-variable], [-Wno-vla-cxx-extension]],[ _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_NO_UNUSED,cflag) # CMake will test what flags work itself, so pass all flags through to it CFG_CXX_FLAGS_CMAKE="$CFG_CXX_FLAGS_CMAKE cflag" ]) AC_SUBST(CFG_CXXFLAGS_NO_UNUSED) AC_SUBST(CFG_CXX_FLAGS_CMAKE) # Find multithread linker flags m4_foreach([ldflag], [ [-mt], [-pthread], [-lpthread], [-latomic]],[ _MY_LDLIBS_CHECK_OPT(CFG_LDLIBS_THREADS,ldflag) # CMake will test what flags work itself, so pass all flags through to it CFG_LDFLAGS_THREADS_CMAKE="$CFG_LDFLAGS_THREADS_CMAKE ldflag" ]) AC_SUBST(CFG_LDLIBS_THREADS) AC_SUBST(CFG_LDFLAGS_THREADS_CMAKE) # If 'mold' is installed, use it to link for faster buildtimes _MY_LDLIBS_CHECK_OPT(CFG_LDFLAGS_SRC, -fuse-ld=mold) _MY_LDLIBS_CHECK_OPT(CFG_LDFLAGS_VERILATED, -fuse-ld=mold) # When linking partially statically if test "$CFG_ENABLE_PARTIAL_STATIC" = "yes"; then _MY_LDLIBS_CHECK_OPT(CFG_LDFLAGS_SRC, -static-libgcc) _MY_LDLIBS_CHECK_OPT(CFG_LDFLAGS_SRC, -static-libstdc++) _MY_LDLIBS_CHECK_OPT(CFG_LDFLAGS_SRC, -Xlinker -gc-sections) LTCMALLOC="-Wl,--whole-archive -l:libtcmalloc_minimal.a -Wl,--no-whole-archive" else LTCMALLOC=-ltcmalloc_minimal fi AC_SUBST(CFG_LDFLAGS_SRC) AC_SUBST(CFG_LDFLAGS_VERILATED) # The pthread library is required by tcmalloc, so add it if it exists. If it # does not, the tcmalloc check below will fail anyway, and linking against # pthreads is harmless otherwise. CFG_LIBS="$LIBS $CFG_LIBS" _MY_LDLIBS_CHECK_OPT(CFG_LIBS, -lpthread) _MY_LDLIBS_CHECK_OPT(CFG_LIBS, -latomic) # Check libraries for MingW _MY_LDLIBS_CHECK_OPT(CFG_LIBS, -lbcrypt) _MY_LDLIBS_CHECK_OPT(CFG_LIBS, -lpsapi) # Check if tcmalloc is available based on --enable-tcmalloc _MY_LDLIBS_CHECK_IFELSE( $LTCMALLOC, [if test "$CFG_WITH_TCMALLOC" != "no"; then CFG_LIBS="$LTCMALLOC $CFG_LIBS"; # If using tcmalloc, add some extra options to make the compiler not assume # it is using its own versions of the standard library functions _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-fno-builtin-malloc) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-fno-builtin-calloc) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-fno-builtin-realloc) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-fno-builtin-free) AC_DEFINE([HAVE_TCMALLOC],[1],[Defined if have tcmalloc]) fi], [if test "$CFG_WITH_TCMALLOC" = "yes"; then AC_MSG_ERROR([--enable-tcmalloc was given but test for ${LTCMALLOC} failed]) fi]) AC_SUBST(HAVE_TCMALLOC) AC_SUBST(CFG_LIBS) # Need C++14 at least #Alternative: AX_CXX_COMPILE_STDCXX([14]) AC_DEFUN([_MY_CXX_CHECK_CXX_VER], [# _MY_CXX_CHECK_CXX_VER(flag) -- Check if compiler runs C++14 # Set $_my_result AC_RUN_IFELSE( [AC_LANG_PROGRAM([#include #if (__cplusplus < 201402L) # error "Too old" #endif ], [[ ]])], [_my_result=yes], [_my_result=no], [_my_result=no]) ]) # Add $CFG_CXXFLAGS_STD only if can't compile correctly otherwise, # as adding std= when not needed can cause errors with the C++ std library. CFG_CXXFLAGS_STD=$CFG_CXXFLAGS_STD_NEWEST AC_MSG_CHECKING(whether $CXX supports C++14) _MY_CXX_CHECK_CXX_VER() AC_MSG_RESULT($_my_result) if test "$_my_result" = "no" ; then CXXFLAGS="$CXXFLAGS $CFG_CXXFLAGS_STD" CFG_CXX_FLAGS_CMAKE="$CFG_CXX_FLAGS_CMAKE $CFG_CXXFLAGS_STD" AC_MSG_CHECKING(whether $CXX supports C++14 with $CFG_CXXFLAGS_STD) _MY_CXX_CHECK_CXX_VER() AC_MSG_RESULT($_my_result) else # CFG_CXXFLAGS_STD is also propagated to include/verilated.mk.in # make sure we use the same std flag while compiling verilator and verilated design CFG_CXXFLAGS_STD="" fi if test "$_my_result" = "no" ; then AC_MSG_NOTICE([[]]) AC_MSG_ERROR([[the $CXX compiler appears to not support C++14. Verilator requires a C++14 or newer compiler.]]) fi AC_SUBST(CFG_CXXFLAGS_STD) # Compiler precompiled header options (assumes either gcc or clang++) AC_MSG_CHECKING([for $CXX precompile header include option]) if $CXX --help | grep include-pch >/dev/null 2>/dev/null ; then # clang CFG_CXXFLAGS_PCH_I=-include-pch CFG_GCH_IF_CLANG=.gch else # GCC CFG_CXXFLAGS_PCH_I=-include CFG_GCH_IF_CLANG= fi AC_MSG_RESULT($CFG_CXXFLAGS_PCH_I) AC_SUBST(CFG_CXXFLAGS_PCH_I) AC_SUBST(CFG_GCH_IF_CLANG) # Checks for library functions. AC_CHECK_MEMBER([struct stat.st_mtim.tv_nsec], [AC_DEFINE([HAVE_STAT_NSEC],[1],[Defined if struct stat has st_mtim.tv_nsec])], [], [#include ]) # HAVE_SYSTEMC # - If found the default search path has it, so support is always enabled. # - If not found or not system-wide, user can set SYSTEMC_INCLUDE. # AC_CHECK_HEADERS seems to not locate on Travis-CI but include does work. AC_MSG_CHECKING([whether SystemC is found (in system path)]) ACO_SAVE_LIBS="$LIBS" LIBS="$LIBS -lsystemc" AC_LINK_IFELSE( [AC_LANG_PROGRAM([[#include extern "C" int sc_main(int argc, char* argv[]) { return 0; } ]],[[sc_version()]])], [_my_result=yes AC_DEFINE([HAVE_SYSTEMC],[1],[Defined if have SystemC library])], [_my_result=no]) AC_MSG_RESULT($_my_result) LIBS="$ACO_SAVE_LIBS" AC_SUBST(HAVE_SYSTEMC) # Checks for system services ###################################################################### ## Output # Other install directories pkgdatadir=${datadir}/verilator AC_SUBST(pkgdatadir) pkgconfigdir=${datadir}/pkgconfig AC_SUBST(pkgconfigdir) AC_OUTPUT AC_MSG_RESULT([]) AC_MSG_RESULT([Now type 'make' (or sometimes 'gmake') to build Verilator.]) AC_MSG_RESULT([]) verilator-5.044/.github/0000755000542200017500000000000015125463617015465 5ustar mahmoudyfreeshellverilator-5.044/.github/labels.toml0000644000542200017500000001173015125463617017626 0ustar mahmoudyfreeshell["area: assertions"] color = "ffffe8" name = "area: assertions" description = "Issue involves assertions" ["area: configure/compiling"] color = "ffffe8" name = "area: configure/compiling" description = "Issue involves configuring or compilating Verilator itself" ["area: coverage"] color = "ffffe8" name = "area: coverage" description = "Issue involves coverage generation" ["area: data-types"] color = "ffffe8" name = "area: data-types" description = "Issue involves data-types" ["area: documentation"] color = "ffffe8" name = "area: documentation" description = "Issue involves documentation" ["area: elaboration"] color = "ffffe8" name = "area: elaboration" description = "Issue involves elaboration phase" ["area: invoking/options"] color = "ffffe8" name = "area: invoking/options" description = "Issue involves options passed to Verilator" ["area: lint"] color = "ffffe8" name = "area: lint" description = "Issue involves SystemVerilog lint checking" ["area: parser"] color = "ffffe8" name = "area: parser" description = "Issue involves SystemVerilog parsing" ["area: performance"] color = "ffffe8" name = "area: performance" description = "Issue involves performance issues" ["area: portability"] color = "ffffe8" name = "area: portability" description = "Issue involves operating system/compiler portability" ["area: runtime result"] color = "ffffe8" name = "area: runtime result" description = "Issue involves an incorrect runtine result from Verilated model" ["area: scheduling"] color = "ffffe8" name = "area: scheduling" description = "Issue involves scheduling/ordering of events" ["area: tests"] color = "ffffe8" name = "area: tests" description = "Issue involves the testing system" ["area: usability"] color = "ffffe8" name = "area: usability" description = "Issue involves general usability" ["effort: days"] color = "d0c0b0" name = "effort: days" description = "Expect this issue to require roughly days of invested effort to resolve" ["effort: hours"] color = "f5e6d6" name = "effort: hours" description = "Expect this issue to require roughly hours of invested effort to resolve" ["effort: minutes"] color = "f5e6d6" name = "effort: minutes" description = "Expect this issue to require less than an hour of invested effort to resolve" ["effort: weeks"] color = "d0c0b0" name = "effort: weeks" description = "Expect this issue to require weeks or more of invested effort to resolve" ["good first issue"] color = "7057ff" name = "good first issue" description = "Good for newcomers" ["help wanted"] color = "008672" name = "help wanted" description = "Extra attention is needed" ["new"] color = "ff4400" name = "new" description = "New issue, not yet seen by maintainers" ["resolution: abandoned"] color = "cfd3d7" name = "resolution: abandoned" description = "Closed; not enough information or otherwise never finished" ["resolution: answered"] color = "cfd3d7" name = "resolution: answered" description = "Closed; only applies to questions which were answered" ["resolution: duplicate"] color = "cfd3d7" name = "resolution: duplicate" description = "Closed; issue or pull request already exists" ["resolution: external"] color = "cfd3d7" name = "resolution: external" description = "Closed; passed to another tool's bug tracker" ["resolution: fixed"] color = "cfd3d7" name = "resolution: fixed" description = "Closed; fixed" ["resolution: invalid"] color = "cfd3d7" name = "resolution: invalid" description = "Closed; issue or pull request is no longer relevant" ["resolution: no fix needed"] color = "cfd3d7" name = "resolution: no fix needed" description = "Closed; no fix required (not a bug)" ["resolution: wontfix"] color = "cfd3d7" name = "resolution: wontfix" description = "Closed; work won't continue on an issue or pull request" ["status: asked reporter"] color = "ffffff" name = "status: asked reporter" description = "Bug is waiting for reporter to answer a question" ["status: assigned"] color = "a0f0ff" name = "status: assigned" description = "Issue is assigned to someone to work on" ["status: blocked"] color = "00007f" name = "status: blocked" description = "Issue is waiting for another bug, when other bug is fixed, then goes to 'status: assigned'" ["status: discussion"] color = "d876e3" name = "status: discussion" description = "Issue is waiting for discussions to resolve" ["status: ready"] color = "b6c92a" name = "status: ready" description = "Issue is ready for someone to fix; then goes to 'status: assigned'" ["type: bug"] color = "d73a4a" name = "type: bug" description = "Defect" ["type: feature-IEEE"] color = "cfccff" name = "type: feature-IEEE" description = "Request to add new feature, described in IEEE 1800" ["type: feature-non-IEEE"] color = "cfccff" name = "type: feature-non-IEEE" description = "Request to add new feature, outside IEEE 1800" ["type: maintenance"] color = "cfccff" name = "type: maintenance" description = "Internal maintenance task" ["type: q and a"] color = "84ba34" name = "type: q and a" description = "Question and answer about some feature or user question" verilator-5.044/.github/ISSUE_TEMPLATE/0000755000542200017500000000000015125463617017650 5ustar mahmoudyfreeshellverilator-5.044/.github/ISSUE_TEMPLATE/questions.md0000644000542200017500000000064515125463617022231 0ustar mahmoudyfreeshell--- name: Q and A, or Other about: Use this to ask a question, not related to a specific bug nor feature request. (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst) title: '' labels: new assignees: '' --- How may we help - what is your question? (If reporting a bug or requesting a feature please hit BACK on your browser and use a different issue templates.) verilator-5.044/.github/ISSUE_TEMPLATE/issue.md0000644000542200017500000000221115125463617021316 0ustar mahmoudyfreeshell--- name: Bug or feature about: Use this to report that something isn't working as expected, or is a desired feature. (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst) title: '' labels: new assignees: '' --- Thanks for taking the time to report this. Can you please attach an example that shows the issue or missing feature? (Must be openly licensed, completely self-contained so can directly run what you provide. Ideally use test_regress format, see https://veripool.org/guide/latest/contributing.html?highlight=test_regress#reporting-bugs) What output from that test indicates it is wrong, and what is the correct or expected output? (Or, please make test self-checking if possible.) What 'verilator' command line do we use to run your example? What 'verilator --version' are you using? Did you try it with the git master version? Did you try it with other simulators? What OS and distribution are you using? May we assist you in trying to fix this in Verilator yourself? (Please avoid attaching screenshots that show text - you can convert images to text using e.g. https://ocr.space) verilator-5.044/.github/PULL_REQUEST_TEMPLATE.md0000644000542200017500000000026715125463617021273 0ustar mahmoudyfreeshellWe appreciate your contributing to Verilator. If this is your first commit, please add your name to docs/CONTRIBUTORS, and read our contributing guidelines in docs/CONTRIBUTING.rst. verilator-5.044/.github/dependabot.yml0000644000542200017500000000037615125463617020323 0ustar mahmoudyfreeshell--- # See https://docs.github.com/code-security/dependabot/dependabot-version-updates/configuration-options-for-the-dependabot.yml-file version: 2 updates: - package-ecosystem: "github-actions" directory: "/" schedule: interval: "weekly" verilator-5.044/.github/workflows/0000755000542200017500000000000015125463617017522 5ustar mahmoudyfreeshellverilator-5.044/.github/workflows/rtlmeter.yml0000644000542200017500000003677515125463617022125 0ustar mahmoudyfreeshell--- # DESCRIPTION: Github actions config # This name is key to badges in README.rst, so we use the name build # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 name: RTLMeter on: workflow_dispatch: schedule: - cron: '0 2 * * *' # Daily, starting at 02:00 UTC pull_request: types: [opened, synchronize, reopened, labeled, unlabeled] permissions: contents: read defaults: run: shell: bash concurrency: # At most 1 job per branch. Auto cancel all but scheduled jobs group: ${{ github.workflow }}-${{ github.ref }} cancel-in-progress: ${{ github.event_name != 'schedule' }} jobs: start: name: Start # Only run scheduled jobs if explicitly enabled for that repo (e.g.: not on forks) # Only run pull request jobs if labelled as needing an RTLMeter run # Always run workflow dispatch jobs if: | (github.event_name == 'schedule' && vars.ENABLE_SCHEDULED_JOBS == 'true') || (github.event_name == 'pull_request' && contains(github.event.pull_request.labels.*.name, 'pr: rtlmeter')) || (github.event_name == 'workflow_dispatch') runs-on: ubuntu-24.04 steps: - name: Startup run: echo build-gcc: name: Build GCC needs: start uses: ./.github/workflows/reusable-rtlmeter-build.yml with: runs-on: ubuntu-24.04 cc: gcc build-clang: name: Build Clang needs: start uses: ./.github/workflows/reusable-rtlmeter-build.yml with: runs-on: ubuntu-24.04 cc: clang run-gcc: name: Run GCC | ${{ matrix.cases }} needs: build-gcc uses: ./.github/workflows/reusable-rtlmeter-run.yml with: tag: gcc runs-on: ubuntu-24.04 cc: gcc cases: ${{ matrix.cases }} run-name: "gcc" compileArgs: "" executeArgs: "" strategy: fail-fast: false max-parallel: ${{ github.event == 'schedule' && 2 || 7 }} matrix: cases: - "BlackParrot:1x1:*" - "BlackParrot:2x2:*" - "BlackParrot:4x4:*" - "Caliptra:default:*" - "NVDLA:*" - "OpenPiton:1x1:*" - "OpenPiton:2x2:*" - "OpenPiton:4x4:*" - "OpenTitan:*" - "VeeR-EH1:asic*" - "VeeR-EH1:default*" - "VeeR-EH1:hiperf*" - "VeeR-EH2:asic*" - "VeeR-EH2:default*" - "VeeR-EH2:hiperf*" - "VeeR-EL2:asic*" - "VeeR-EL2:default*" - "VeeR-EL2:hiperf*" - "Vortex:mini:*" - "Vortex:sane:*" - "XiangShan:default-chisel3:* !*:linux" - "XiangShan:default-chisel6:* !*:linux" - "XiangShan:mini-chisel3:* !*:linux" - "XiangShan:mini-chisel6:* !*:linux" - "XuanTie-E902:*" - "XuanTie-E906:*" - "XuanTie-C906:*" - "XuanTie-C910:*" run-clang: name: Run Clang | ${{ matrix.cases }} needs: build-clang uses: ./.github/workflows/reusable-rtlmeter-run.yml with: tag: clang runs-on: ubuntu-24.04 cc: clang cases: ${{ matrix.cases }} run-name: "clang --threads 4" compileArgs: "--threads 4" executeArgs: "" strategy: fail-fast: false max-parallel: ${{ github.event == 'schedule' && 2 || 7 }} matrix: cases: - "BlackParrot:1x1:*" - "BlackParrot:2x2:*" - "BlackParrot:4x4:*" - "Caliptra:default:*" - "NVDLA:*" - "OpenPiton:1x1:*" - "OpenPiton:2x2:*" - "OpenPiton:4x4:*" - "OpenTitan:*" - "VeeR-EH1:asic*" - "VeeR-EH1:default*" - "VeeR-EH1:hiperf*" - "VeeR-EH2:asic*" - "VeeR-EH2:default*" - "VeeR-EH2:hiperf*" - "VeeR-EL2:asic*" - "VeeR-EL2:default*" - "VeeR-EL2:hiperf*" - "Vortex:mini:*" - "Vortex:sane:*" - "XiangShan:default-chisel3:* !*:linux" - "XiangShan:default-chisel6:* !*:linux" - "XiangShan:mini-chisel3:* !*:linux" - "XiangShan:mini-chisel6:* !*:linux" - "XuanTie-E902:*" - "XuanTie-E906:*" - "XuanTie-C906:*" - "XuanTie-C910:*" run-gcc-hier: name: Run GCC hier | ${{ matrix.cases }} needs: build-gcc uses: ./.github/workflows/reusable-rtlmeter-run.yml with: tag: gcc-hier runs-on: ubuntu-24.04 cc: gcc cases: ${{ matrix.cases }} run-name: "gcc --hierarchical" compileArgs: "--hierarchical" executeArgs: "" strategy: fail-fast: false max-parallel: ${{ github.event == 'schedule' && 2 || 7 }} matrix: cases: - "BlackParrot:1x1:* !-hier" - "BlackParrot:2x2:* !-hier" - "BlackParrot:4x4:* !-hier" - "NVDLA:* !-hier" - "OpenPiton:1x1:* !-hier" - "OpenPiton:2x2:* !-hier" - "OpenPiton:4x4:* !-hier" - "OpenPiton:8x8:* !-hier" - "OpenPiton:16x16:dhry !-hier" - "XuanTie-C910:* !-hier" combine-results: name: Combine results needs: [run-gcc, run-clang, run-gcc-hier] # Run if any of the dependencies have run, even if failed. # That is: do not run if all skipped, or the workflow was cancelled. if: ${{ (contains(needs.*.result, 'success') || contains(needs.*.result, 'failure')) && !cancelled() }} runs-on: ubuntu-24.04 strategy: fail-fast: false matrix: tag: [gcc, clang, gcc-hier] steps: - name: Checkout RTLMeter uses: actions/checkout@v6 with: repository: "verilator/rtlmeter" path: rtlmeter - name: Setup RTLMeter venv working-directory: rtlmeter run: make venv - name: Download all results uses: actions/download-artifact@v7 with: pattern: rtlmeter-${{ matrix.tag }}-results-* path: all-results-${{ matrix.tag }} merge-multiple: true - name: Combine results working-directory: rtlmeter run: | ./rtlmeter collate ../all-results-${{ matrix.tag }}/*.json > ../all-results-${{ matrix.tag }}.json - name: Upload combined results uses: actions/upload-artifact@v6 with: path: all-results-${{ matrix.tag }}.json name: all-results-${{ matrix.tag }} overwrite: true retention-days: 30 publish-scheduled-results: name: Publish results to verilator/verilator-rtlmeter-results needs: combine-results # Only run on scheduled builds on the main repository. We also restrict # the publishing to run only on the first run_attempt. This is required # to prevent multiple uploads the same day (if rerunning), as the # dashboard UI currently assumes there is only one data point per # calendar day. Results from reruns can be imported manually if needed. if: ${{ github.event_name == 'schedule' && github.repository == 'verilator/verilator' && github.run_attempt == 1 && contains(needs.*.result, 'success') && !cancelled() }} runs-on: ubuntu-24.04 steps: - name: Download combined results uses: actions/download-artifact@v7 with: pattern: all-results-* path: results merge-multiple: true - name: Upload published results uses: actions/upload-artifact@v6 with: path: results/*.json name: published-results # Pushing to verilator/verilator-rtlmeter-results requires elevated permissions - name: Generate access token id: generate-token uses: actions/create-github-app-token@v2.2.1 with: app-id: ${{ vars.VERILATOR_CI_ID }} private-key: ${{ secrets.VERILATOR_CI_KEY }} owner: verilator repositories: verilator-rtlmeter-results permission-contents: write - name: Checkout verilator-rtlmeter-results uses: actions/checkout@v6 with: repository: "verilator/verilator-rtlmeter-results" token: ${{ steps.generate-token.outputs.token }} path: verilator-rtlmeter-results - name: Import results id: import-results working-directory: verilator-rtlmeter-results run: | for f in $(find ../results -name "*.json"); do \ echo "Importing $f"; \ ./bin/add-rtlmeter-result $f; \ done test -z "$(git status --porcelain)" || echo "valid=1" >> "$GITHUB_OUTPUT" - name: Push to verilator-rtlmeter-results if: ${{ steps.import-results.outputs.valid }} working-directory: verilator-rtlmeter-results run: | git config --global user.email "action@example.com" git config --global user.name "github action" git add . git commit -m "Verilator CI: Results of 'RTLMeter' workflow run #${{ github.run_number }}" git push origin prepare-pr-results: name: Prepare Pull Request results needs: combine-results if: ${{ github.event_name == 'pull_request' && github.repository == 'verilator/verilator' && contains(needs.*.result, 'success') && !cancelled() }} runs-on: ubuntu-24.04 permissions: actions: read steps: - name: Checkout RTLMeter uses: actions/checkout@v6 with: repository: "verilator/rtlmeter" path: rtlmeter - name: Setup RTLMeter venv working-directory: rtlmeter run: make venv - name: Download combined results uses: actions/download-artifact@v7 with: pattern: all-results-* path: all-results merge-multiple: true - name: Get scheduled run info id: scheduled-info env: GH_TOKEN: ${{ secrets.GITHUB_TOKEN }} run: | ID=$(gh run --repo ${{ github.repository }} list --workflow RTLMeter --event schedule --status success --limit 1 --json databaseId --jq ".[0].databaseId") echo "id=$ID" >> $GITHUB_OUTPUT URL=$(gh run --repo ${{ github.repository }} view $ID --json url --jq ".url") echo "url=$URL" >> $GITHUB_OUTPUT NUM=$(gh run --repo ${{ github.repository }} view $ID --json number --jq ".number") echo "num=$NUM" >> $GITHUB_OUTPUT DATE=$(gh run --repo ${{ github.repository }} view $ID --json createdAt --jq ".createdAt") echo "date=$DATE" >> $GITHUB_OUTPUT - name: Download scheduled run results uses: actions/download-artifact@v7 with: name: published-results path: nightly-results run-id: ${{ steps.scheduled-info.outputs.id }} github-token: ${{ secrets.GITHUB_TOKEN }} - name: Compare results working-directory: rtlmeter run: | for tag in gcc clang gcc-hier; do ADATA=../nightly-results/all-results-${tag}.json BDATA=../all-results/all-results-${tag}.json touch ../verilate-${tag}.txt touch ../execute-${tag}.txt touch ../cppbuild-${tag}.txt if [[ ! -e $ADATA ]]; then continue fi ./rtlmeter compare --cases '* !Example:* !*:hello' --steps "verilate" --metrics "elapsed memory" $ADATA $BDATA > ../verilate-${tag}.txt cat ../verilate-${tag}.txt ./rtlmeter compare --cases '* !Example:* !*:hello' --steps "execute" --metrics "speed memory elapsed" $ADATA $BDATA > ../execute-${tag}.txt cat ../execute-${tag}.txt ./rtlmeter compare --cases '* !Example:* !*:hello' --steps "cppbuild" --metrics "elapsed memory cpu codeSize" $ADATA $BDATA > ../cppbuild-${tag}.txt cat ../cppbuild-${tag}.txt done - name: Create report env: GH_TOKEN: ${{ secrets.GITHUB_TOKEN }} run: | set -x NUM=$(gh run --repo ${{ github.repository }} view ${{ github.run_id }} --json number --jq ".number") URL=$(gh run --repo ${{ github.repository }} view ${{ github.run_id }} --json url --jq ".url") echo -n "Performance metrics for PR workflow [#$NUM]($URL) (B) compared to scheduled run" > report.txt echo -n " [#${{ steps.scheduled-info.outputs.num }}](${{ steps.scheduled-info.outputs.url }}) (A)" >> report.txt echo " from ${{ steps.scheduled-info.outputs.date }}" >> report.txt for tag in gcc clang gcc-hier; do echo "" >> report.txt if [[ $tag == "gcc" ]]; then echo "
" >> report.txt else echo "
" >> report.txt fi echo -n "" >> report.txt jq -rj ".[0].runName" all-results/all-results-${tag}.json >> report.txt echo "" >> report.txt awk -v RS= -v tag=${tag} '{print > sprintf("frag-%02d-verilate-%s.txt",NR,tag)}' verilate-${tag}.txt awk -v RS= -v tag=${tag} '{print > sprintf("frag-%02d-execute-%s.txt" ,NR,tag)}' execute-${tag}.txt awk -v RS= -v tag=${tag} '{print > sprintf("frag-$02d-cppbuild-%s.txt",NR,tag)}' cppbuild-${tag}.txt for f in $(ls -1 frag-*-verilate-${tag}.txt | sort) $(ls -1 frag-*-execute-${tag}.txt | sort) $(ls -1 frag-*-cppbuild-${tag}.txt | sort); do if [[ $f == frag-01-verilate-${tag}.txt || $f == frag-01-execute-${tag}.txt ]]; then echo "
" >> report.txt else echo "
" >> report.txt fi echo -n "" >> report.txt head -n 1 $f | tr -d '\n' >> report.txt echo "" >> report.txt echo '
' >> report.txt
              tail -n +2 $f >> report.txt
              echo '
' >> report.txt echo "
" >> report.txt done echo "
" >> report.txt done cat report.txt - name: Upload report uses: actions/upload-artifact@v6 with: path: report.txt name: rtlmeter-pr-results - name: Save PR number run: echo ${{ github.event.number }} > pr-number.txt - name: Upload PR number uses: actions/upload-artifact@v6 with: path: pr-number.txt name: pr-number # Create GitHub issue for failed scheduled jobs # This should always be the last job (we want an issue if anything breaks) create-issue: name: Create issue on failure needs: publish-scheduled-results if: ${{ github.event_name == 'schedule' && github.repository == 'verilator/verilator' && github.run_attempt == 1 && failure() && !cancelled() }} runs-on: ubuntu-24.04 steps: # Creating issues requires elevated privilege - name: Generate access token id: generate-token uses: actions/create-github-app-token@v2.2.1 with: app-id: ${{ vars.VERILATOR_CI_ID }} private-key: ${{ secrets.VERILATOR_CI_KEY }} owner: verilator repositories: verilator permission-issues: write - name: Create issue env: GH_TOKEN: ${{ steps.generate-token.outputs.token }} run: |- echo "This issue was created automatically by the GitHub Actions CI due to the failure of a scheduled RTLMeter run." >> body.txt echo "" >> body.txt echo "Workflow status: ${{ github.server_url }}/${{ github.repository }}/actions/runs/${{ github.run_id }}" >> body.txt gh issue --repo ${{ github.repository }} create \ --title "RTLMeter run #${{ github.run_number }} Failed" \ --body-file body.txt \ --label new \ --assignee gezalore,wsnyder verilator-5.044/.github/workflows/build-test.yml0000644000542200017500000002154715125463617022332 0ustar mahmoudyfreeshell--- # DESCRIPTION: Github actions config # This name is key to badges in README.rst, so we use the name build # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 name: build-test on: push: branches-ignore: - 'dependabot/**' # Avoid duplicates: only run the PR, not the push pull_request: workflow_dispatch: schedule: - cron: '0 0 * * 0' # weekly permissions: contents: read defaults: run: working-directory: repo concurrency: # At most 1 job per branch. Auto cancel on pull requests and on all forks group: ${{ github.workflow }}-${{ github.ref }} cancel-in-progress: ${{ github.event_name == 'pull_request' || github.repository != 'verilator/verilator' }} jobs: build-2404-gcc: name: Build | ${{ matrix.os }} | ${{ matrix.cc }}${{ matrix.asan && ' | asan' || '' }} uses: ./.github/workflows/reusable-build.yml with: sha: ${{ github.sha }} os: ${{ matrix.os }} os-name: linux cc: ${{ matrix.cc }} dev-asan: ${{ matrix.asan }} dev-gcov: 0 strategy: fail-fast: false matrix: include: - {os: ubuntu-24.04, cc: gcc, asan: 0} build-2404-clang: name: Build | ${{ matrix.os }} | ${{ matrix.cc }}${{ matrix.asan && ' | asan' || '' }} uses: ./.github/workflows/reusable-build.yml with: sha: ${{ github.sha }} os: ${{ matrix.os }} os-name: linux cc: ${{ matrix.cc }} dev-asan: ${{ matrix.asan }} dev-gcov: 0 strategy: fail-fast: false matrix: include: - {os: ubuntu-24.04, cc: clang, asan: 1} build-2204-gcc: name: Build | ${{ matrix.os }} | ${{ matrix.cc }}${{ matrix.asan && ' | asan' || '' }} uses: ./.github/workflows/reusable-build.yml with: sha: ${{ github.sha }} os: ${{ matrix.os }} os-name: linux cc: ${{ matrix.cc }} dev-asan: ${{ matrix.asan }} dev-gcov: 0 strategy: fail-fast: false matrix: include: - {os: ubuntu-22.04, cc: gcc, asan: 0} build-2204-clang: name: Build | ${{ matrix.os }} | ${{ matrix.cc }}${{ matrix.asan && ' | asan' || '' }} uses: ./.github/workflows/reusable-build.yml with: sha: ${{ github.sha }} os: ${{ matrix.os }} os-name: linux cc: ${{ matrix.cc }} dev-asan: ${{ matrix.asan }} dev-gcov: 0 strategy: fail-fast: false matrix: include: - {os: ubuntu-22.04, cc: clang, asan: 0} build-osx-gcc: name: Build | ${{ matrix.os }} | ${{ matrix.cc }}${{ matrix.asan && ' | asan' || '' }} uses: ./.github/workflows/reusable-build.yml with: sha: ${{ github.sha }} os: ${{ matrix.os }} os-name: osx cc: ${{ matrix.cc }} dev-asan: ${{ matrix.asan }} dev-gcov: 0 strategy: fail-fast: false matrix: include: - {os: macos-15, cc: gcc, asan: 0} build-osx-clang: name: Build | ${{ matrix.os }} | ${{ matrix.cc }}${{ matrix.asan && ' | asan' || '' }} uses: ./.github/workflows/reusable-build.yml with: sha: ${{ github.sha }} os: ${{ matrix.os }} os-name: osx cc: ${{ matrix.cc }} dev-asan: ${{ matrix.asan }} dev-gcov: 0 strategy: fail-fast: false matrix: include: - {os: macos-15, cc: clang, asan: 0} build-windows: name: Build | ${{ matrix.os }} | ${{ matrix.cc }} runs-on: ${{ matrix.os }} strategy: fail-fast: false matrix: include: - {os: windows-2025, cc: msvc} env: CI_OS_NAME: win CCACHE_COMPRESS: 1 CCACHE_DIR: ${{ github.workspace }}/.ccache CCACHE_LIMIT_MULTIPLE: 0.95 steps: - uses: actions/checkout@v6 with: path: repo - name: Cache $CCACHE_DIR uses: actions/cache@v5 with: path: ${{ env.CCACHE_DIR }} key: msbuild-msvc-cmake - name: compile env: WIN_FLEX_BISON: ${{ github.workspace }}/.ccache run: ./ci/ci-win-compile.ps1 - name: test build run: ./ci/ci-win-test.ps1 - name: Zip up repository run: Compress-Archive -LiteralPath install -DestinationPath verilator.zip - name: Upload zip archive uses: actions/upload-artifact@v6 with: path: ${{ github.workspace }}/repo/verilator.zip name: verilator-win.zip test-2404-gcc: name: Test | ${{ matrix.os }} | ${{ matrix.cc }} | ${{ matrix.reloc && 'reloc | ' || '' }} ${{ matrix.suite }} needs: build-2404-gcc uses: ./.github/workflows/reusable-test.yml with: archive: ${{ needs.build-2404-gcc.outputs.archive }} os: ${{ matrix.os }} cc: ${{ matrix.cc }} reloc: ${{ matrix.reloc }} suite: ${{ matrix.suite }} dev-gcov: 0 strategy: fail-fast: false matrix: include: # Ubuntu 24.04 gcc - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: dist-vlt-0} - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: dist-vlt-1} - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: dist-vlt-2} - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: dist-vlt-3} - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: vltmt-0} - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: vltmt-1} - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: vltmt-2} test-2404-clang: name: Test | ${{ matrix.os }} | ${{ matrix.cc }} | ${{ matrix.reloc && 'reloc | ' || '' }} ${{ matrix.suite }} needs: build-2404-clang uses: ./.github/workflows/reusable-test.yml with: archive: ${{ needs.build-2404-clang.outputs.archive }} os: ${{ matrix.os }} cc: ${{ matrix.cc }} reloc: ${{ matrix.reloc }} suite: ${{ matrix.suite }} dev-gcov: 0 strategy: fail-fast: false matrix: include: # Ubuntu 24.04 clang - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: dist-vlt-0} - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: dist-vlt-1} - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: dist-vlt-2} - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: dist-vlt-3} - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: vltmt-0} - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: vltmt-1} - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: vltmt-2} test-2204-gcc: name: Test | ${{ matrix.os }} | ${{ matrix.cc }} | ${{ matrix.reloc && 'reloc | ' || '' }} ${{ matrix.suite }} needs: build-2204-gcc uses: ./.github/workflows/reusable-test.yml with: archive: ${{ needs.build-2204-gcc.outputs.archive }} os: ${{ matrix.os }} cc: ${{ matrix.cc }} reloc: ${{ matrix.reloc }} suite: ${{ matrix.suite }} dev-gcov: 0 strategy: fail-fast: false matrix: include: # Ubuntu 22.04 gcc - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: dist-vlt-0} - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: dist-vlt-1} - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: dist-vlt-2} - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: dist-vlt-3} - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: vltmt-0} - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: vltmt-1} - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: vltmt-2} test-2204-clang: name: Test | ${{ matrix.os }} | ${{ matrix.cc }} | ${{ matrix.reloc && 'reloc | ' || '' }} ${{ matrix.suite }} needs: build-2204-clang uses: ./.github/workflows/reusable-test.yml with: archive: ${{ needs.build-2204-clang.outputs.archive }} os: ${{ matrix.os }} cc: ${{ matrix.cc }} reloc: ${{ matrix.reloc }} suite: ${{ matrix.suite }} dev-gcov: 0 strategy: fail-fast: false matrix: include: # Ubuntu 22.04 clang, also test relocation - {os: ubuntu-22.04, cc: clang, reloc: 1, suite: dist-vlt-0} - {os: ubuntu-22.04, cc: clang, reloc: 1, suite: dist-vlt-1} - {os: ubuntu-22.04, cc: clang, reloc: 1, suite: dist-vlt-2} - {os: ubuntu-22.04, cc: clang, reloc: 1, suite: dist-vlt-3} - {os: ubuntu-22.04, cc: clang, reloc: 1, suite: vltmt-0} - {os: ubuntu-22.04, cc: clang, reloc: 1, suite: vltmt-1} - {os: ubuntu-22.04, cc: clang, reloc: 1, suite: vltmt-2} lint-py: name: Lint Python uses: ./.github/workflows/reusable-lint-py.yml passed: name: Test suite passed if: always() needs: - build-2404-gcc - build-2404-clang - build-2204-gcc - build-2204-clang - build-osx-gcc - build-osx-clang - build-windows - test-2404-gcc - test-2404-clang - test-2204-gcc - test-2204-clang - lint-py runs-on: ubuntu-24.04 steps: - name: Decide whether the needed jobs succeeded or failed uses: re-actors/alls-green@release/v1 with: jobs: ${{ toJSON(needs) }} verilator-5.044/.github/workflows/reusable-test.yml0000644000542200017500000000560515125463617023032 0ustar mahmoudyfreeshell--- # DESCRIPTION: Github actions config # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 name: reusable-test on: workflow_call: inputs: archive: description: "Name of the repository archive artifact from reusable-build" required: true type: string os: # e.g. ubuntu-24.04 required: true type: string cc: # gcc or clang required: true type: string reloc: # 0 or 1 required: true type: number suite: # e.g. dist-vlt-0 required: true type: string dev-gcov: required: true type: number env: CI_OS_NAME: linux CCACHE_COMPRESS: 1 CCACHE_DIR: ${{ github.workspace }}/.ccache CCACHE_LIMIT_MULTIPLE: 0.95 INSTALL_DIR: ${{ github.workspace }}/install RELOC_DIR: ${{ github.workspace }}/relloc defaults: run: shell: bash working-directory: repo jobs: test: runs-on: ${{ inputs.os }} name: Test env: CI_BUILD_STAGE_NAME: test CI_RUNS_ON: ${{ inputs.os }} CI_RELOC: ${{inputs.reloc }} CXX: ${{ inputs.cc == 'clang' && 'clang++' || 'g++' }} CACHE_BASE_KEY: test-${{ inputs.os }}-${{ inputs.cc }}-${{inputs.reloc }}-${{ inputs.suite }} CCACHE_MAXSIZE: 100M # Per build per suite (* 5 * 5 = 2500M in total) steps: - name: Download repository archive uses: actions/download-artifact@v7 with: name: ${{ inputs.archive }} path: ${{ github.workspace }} - name: Unpack repository archive working-directory: ${{ github.workspace }} run: | tar -x -z -f ${{ inputs.archive }} ls -lsha - name: Cache $CCACHE_DIR uses: actions/cache@v5 env: CACHE_KEY: ${{ env.CACHE_BASE_KEY }}-ccache2 with: path: ${{ env.CCACHE_DIR }} key: ${{ env.CACHE_KEY }}-${{ github.sha }} restore-keys: | ${{ env.CACHE_KEY }}- - name: Install test dependencies run: | ./ci/ci-install.bash make venv - name: Test id: run-test continue-on-error: true env: TESTS: ${{ inputs.suite }} run: | source .venv/bin/activate ./ci/ci-script.bash - name: Combine code coverage data if: ${{ inputs.dev-gcov }} run: | make coverage-combine mv obj_coverage/verilator.info obj_coverage/verilator-${{ inputs.suite }}.info ls -lsha obj_coverage - name: Upload code coverage data if: ${{ inputs.dev-gcov }} uses: actions/upload-artifact@v6 with: path: ${{ github.workspace }}/repo/obj_coverage/verilator-${{ inputs.suite }}.info name: code-coverage-${{ inputs.suite }} - name: Fail job if a test failed if: ${{ steps.run-test.outcome == 'failure' && !cancelled() }} run: exit 1 verilator-5.044/.github/workflows/reusable-lint-py.yml0000644000542200017500000000171215125463617023442 0ustar mahmoudyfreeshell--- # DESCRIPTION: Github actions config # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 name: reusable-lint-py on: workflow_call: env: CI_OS_NAME: linux CI_BUILD_STAGE_NAME: build CI_RUNS_ON: ubuntu-22.04 CCACHE_COMPRESS: 1 CCACHE_DIR: ${{ github.workspace }}/.ccache CCACHE_LIMIT_MULTIPLE: 0.95 defaults: run: shell: bash working-directory: repo jobs: lint-py: runs-on: ubuntu-22.04 name: Sub-lint | Python steps: - name: Checkout uses: actions/checkout@v6 with: path: repo - name: Install packages for build run: ./ci/ci-install.bash - name: Configure run: | autoconf ./configure --enable-longtests --enable-ccwarn - name: Install python dependencies run: | sudo apt install python3-clang make venv - name: Lint run: |- source .venv/bin/activate make -k lint-py verilator-5.044/.github/workflows/contributor.yml0000644000542200017500000000074215125463617022622 0ustar mahmoudyfreeshell--- # DESCRIPTION: Github actions config # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # name: Contributor Agreement on: push: branches-ignore: - 'dependabot/**' # Avoid duplicates: only run the PR, not the push pull_request: workflow_dispatch: permissions: contents: read jobs: Test: name: "'docs/CONTRIBUTORS' was signed" runs-on: ubuntu-24.04 steps: - uses: actions/checkout@v6 - run: test_regress/t/t_dist_contributors.py verilator-5.044/.github/workflows/reusable-rtlmeter-build.yml0000644000542200017500000000427415125463617025007 0ustar mahmoudyfreeshell--- # DESCRIPTION: Github actions config # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 name: reusable-rtlmeter-build on: workflow_call: inputs: runs-on: description: "Runner to use, e.g.: ubuntu-24.04" type: string required: true cc: description: "Compiler to use: 'gcc' or 'clang'" type: string required: true defaults: run: shell: bash env: CCACHE_DIR: ${{ github.workspace }}/ccache CCACHE_MAXSIZE: 512M jobs: build: runs-on: ${{ inputs.runs-on }} name: Build steps: - name: Install dependencies run: | echo "path-exclude /usr/share/doc/*" | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc echo "path-exclude /usr/share/man/*" | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc echo "path-exclude /usr/share/info/*" | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc sudo apt update sudo apt install ccache mold help2man libfl-dev libgoogle-perftools-dev libsystemc-dev - name: Use saved ccache uses: actions/cache@v5 with: path: ccache key: rtlmeter-build-ccache-${{ inputs.runs-on }}-${{ inputs.cc }}-${{ github.run_id }}-${{ github.run_attempt }} restore-keys: rtlmeter-build-ccache-${{ inputs.runs-on }}-${{ inputs.cc }} - name: Checkout uses: actions/checkout@v6 with: path: repo fetch-depth: 0 # Required for 'git describe' used for 'verilator --version' - name: Configure working-directory: repo run: | autoconf ./configure --prefix=${{ github.workspace }}/install CXX=${{ inputs.cc == 'clang' && 'clang++' || 'g++' }} - name: Make working-directory: repo run: make -j $(nproc) - name: Install working-directory: repo run: make install - name: Tar up installation run: tar --posix -c -z -f verilator-rtlmeter.tar.gz install - name: Upload Verilator installation archive uses: actions/upload-artifact@v6 with: path: verilator-rtlmeter.tar.gz name: verilator-rtlmeter-${{ inputs.runs-on }}-${{ inputs.cc }} overwrite: true verilator-5.044/.github/workflows/reusable-build.yml0000644000542200017500000000547215125463617023154 0ustar mahmoudyfreeshell--- # DESCRIPTION: Github actions config # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 name: reusable-build on: workflow_call: inputs: sha: description: "Commit SHA to build" required: true type: string os: # e.g. ubuntu-24.04 required: true type: string cc: # 'clang' or 'gcc' required: true type: string os-name: # 'linux' or 'osx' required: true type: string dev-asan: required: true type: number dev-gcov: required: true type: number outputs: archive: description: "Name of the built repository archive artifact" value: ${{ jobs.build.outputs.archive }} env: CI_OS_NAME: ${{ inputs.os-name }} CCACHE_COMPRESS: 1 CCACHE_DIR: ${{ github.workspace }}/.ccache CCACHE_LIMIT_MULTIPLE: 0.95 INSTALL_DIR: ${{ github.workspace }}/install RELOC_DIR: ${{ github.workspace }}/relloc defaults: run: shell: bash working-directory: repo jobs: build: name: Build runs-on: ${{ inputs.os }} outputs: archive: ${{ steps.create-archive.outputs.archive }} env: CI_BUILD_STAGE_NAME: build CI_DEV_ASAN: ${{ inputs.dev-asan }} CI_DEV_GCOV: ${{ inputs.dev-gcov }} CI_RUNS_ON: ${{ inputs.os }} CXX: ${{ inputs.cc == 'clang' && 'clang++' || 'g++' }} CACHE_BASE_KEY: build-${{ inputs.os }}-${{ inputs.cc }} CCACHE_MAXSIZE: 1000M # Per build matrix entry (* 5 = 5000M in total) steps: - name: Checkout uses: actions/checkout@v6 with: path: repo ref: ${{ inputs.sha }} fetch-depth: ${{ inputs.dev-gcov && '0' || '1' }} # Coverage flow needs full history - name: Cache $CCACHE_DIR uses: actions/cache@v5 env: CACHE_KEY: ${{ env.CACHE_BASE_KEY }}-ccache with: path: ${{ env.CCACHE_DIR }} key: ${{ env.CACHE_KEY }}-${{ inputs.sha }} restore-keys: | ${{ env.CACHE_KEY }}- - name: Install packages for build run: ./ci/ci-install.bash - name: Build run: ./ci/ci-script.bash - name: Create repository archive id: create-archive working-directory: ${{ github.workspace }} run: | # Name of the archive must be unique based on the build parameters ARCHIVE=verilator-${{ inputs.sha }}-${{ inputs.os }}-${{ inputs.cc }}-${{ inputs.dev-asan }}-${{ inputs.dev-gcov }}.tar.gz tar --posix -c -z -f $ARCHIVE repo echo "archive=$ARCHIVE" >> "$GITHUB_OUTPUT" - name: Upload repository archive uses: actions/upload-artifact@v6 with: path: ${{ github.workspace }}/${{ steps.create-archive.outputs.archive }} name: ${{ steps.create-archive.outputs.archive }} verilator-5.044/.github/workflows/format.yml0000644000542200017500000000230215125463617021532 0ustar mahmoudyfreeshell--- # DESCRIPTION: Github actions config # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # name: format on: push: branches-ignore: - 'dependabot/**' # Avoid duplicates: only run the PR, not the push permissions: contents: write jobs: format: runs-on: ubuntu-24.04 name: Ubuntu 24.04 | format env: CI_OS_NAME: linux CI_RUNS_ON: ubuntu-24.04 CI_COMMIT: ${{ github.sha }} steps: - name: Checkout uses: actions/checkout@v6 with: token: ${{ secrets.GITHUB_TOKEN }} - name: Install packages for build env: CI_BUILD_STAGE_NAME: build run: | sudo apt install clang-format-18 git config --global user.email "action@example.com" git config --global user.name "github action" - name: Format code run: | autoconf ./configure make venv source .venv/bin/activate make -j 2 format CLANGFORMAT=clang-format-18 git status - name: Push run: |- if [ -n "$(git status --porcelain)" ]; then git commit . -m "Apply 'make format'" && git push origin fi verilator-5.044/.github/workflows/reusable-rtlmeter-run.yml0000644000542200017500000001111715125463617024506 0ustar mahmoudyfreeshell--- # DESCRIPTION: Github actions config # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 name: reusable-rtlmeter-run on: workflow_call: inputs: tag: description: "Unique identifier for storing results" type: string required: true runs-on: description: "Runner to use, e.g.: ubuntu-24.04" type: string required: true cc: description: "Compiler to use: 'gcc' or 'clang'" type: string required: true # Note: The combination of 'cases' and 'run-name' must be unique for all # invocations of this workflow within a run of the parent workflow. # These two are used together to generate a unique results file name. cases: description: "RTLMeter cases to run" type: string required: true run-name: description: "Run name (identifier) to add to collated results" type: string required: true compileArgs: description: "Additional Verilator command line arguments" type: string default: "" executeArgs: description: "Additional simulator command line arguments" type: string default: "" defaults: run: shell: bash env: CCACHE_DIR: ${{ github.workspace }}/ccache CCACHE_MAXSIZE: 512M CCACHE_DISABLE: 1 jobs: run: runs-on: ${{ inputs.runs-on }} name: Run steps: - name: Install dependencies run: | echo "path-exclude /usr/share/doc/*" | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc echo "path-exclude /usr/share/man/*" | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc echo "path-exclude /usr/share/info/*" | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc sudo apt update sudo apt install ccache mold libfl-dev libgoogle-perftools-dev libsystemc-dev - name: Download Verilator installation archive uses: actions/download-artifact@v7 with: name: verilator-rtlmeter-${{ inputs.runs-on }}-${{ inputs.cc }} - name: Unpack Verilator installation archive run: | tar -x -z -f verilator-rtlmeter.tar.gz echo "${{ github.workspace }}/install/bin" >> $GITHUB_PATH - name: Use saved ccache if: ${{ env.CCACHE_DISABLE == 0 }} uses: actions/cache@v5 with: path: ${{ env.CCACHE_DIR }} key: rtlmeter-run-ccache-${{ inputs.runs-on }}-${{ inputs.cc }}-${{ inputs.cases }}-${{ inputs.compileArgs }}-${{ github.run_id }}-${{ github.run_attempt }} restore-keys: rtlmeter-run-ccache-${{ inputs.runs-on }}-${{ inputs.cc }}-${{ inputs.cases }}-${{ inputs.compileArgs }} - name: Checkout RTLMeter uses: actions/checkout@v6 with: repository: "verilator/rtlmeter" path: rtlmeter - name: Setup RTLMeter venv working-directory: rtlmeter run: make venv - name: Compile cases working-directory: rtlmeter run: | ./rtlmeter run --timeout 60 --verbose --cases='${{inputs.cases}}' --compileArgs='${{inputs.compileArgs}}' --executeArgs='${{inputs.executeArgs}}' --nExecute=0 - name: Execute cases working-directory: rtlmeter continue-on-error: true # Do not fail on error, so we can at least save the successful results run: | ./rtlmeter run --timeout 60 --verbose --cases='${{inputs.cases}}' --compileArgs='${{inputs.compileArgs}}' --executeArgs='${{inputs.executeArgs}}' - name: Collate results id: results working-directory: rtlmeter run: | # Use 'inputs.cases' and 'inputs.run-name' to generate a unique file name hash=$(md5sum <<< '${{ inputs.cases }} ${{ inputs.run-name }}' | awk '{print $1}') echo "hash=${hash}" >> $GITHUB_OUTPUT ./rtlmeter collate --runName "${{ inputs.run-name }}" > ../results-${hash}.json - name: Report results working-directory: rtlmeter run: | ./rtlmeter report --steps '*' --metrics '*' ../results-${{ steps.results.outputs.hash }}.json - name: Upload results uses: actions/upload-artifact@v6 with: path: results-${{ steps.results.outputs.hash }}.json name: rtlmeter-${{ inputs.tag }}-results-${{ steps.results.outputs.hash }} overwrite: true retention-days: 2 - name: Report status working-directory: rtlmeter run: |- # This will fail the job if any of the runs failed ./rtlmeter run --verbose --cases='${{inputs.cases}}' --compileArgs='${{inputs.compileArgs}}' --executeArgs='${{inputs.executeArgs}}' verilator-5.044/.github/workflows/rtlmeter-pr-results.yml0000644000542200017500000000302615125463617024222 0ustar mahmoudyfreeshell--- # DESCRIPTION: Github actions config # This name is key to badges in README.rst, so we use the name build # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 name: RTLMeter PR results on: workflow_run: workflows: [RTLMeter] types: [completed] jobs: publish: name: Publish runs-on: ubuntu-latest if: ${{ github.event.workflow_run.event == 'pull_request' && github.event.workflow_run.conclusion == 'success' }} permissions: actions: read pull-requests: write steps: - name: Download report uses: actions/download-artifact@v7 with: name: rtlmeter-pr-results run-id: ${{ github.event.workflow_run.id }} github-token: ${{ secrets.GITHUB_TOKEN }} - name: Download PR number uses: actions/download-artifact@v7 with: name: pr-number run-id: ${{ github.event.workflow_run.id }} github-token: ${{ secrets.GITHUB_TOKEN }} # Use the Verilator CI app to post the comment - name: Generate access token id: generate-token uses: actions/create-github-app-token@v2.2.1 with: app-id: ${{ vars.VERILATOR_CI_ID }} private-key: ${{ secrets.VERILATOR_CI_KEY }} permission-pull-requests: write - name: Comment on PR env: GH_TOKEN: ${{ steps.generate-token.outputs.token }} run: |- ls -la cat report.txt gh pr --repo ${{ github.repository }} comment $(cat pr-number.txt) --body-file report.txt verilator-5.044/.github/workflows/docker.yml0000644000542200017500000000556015125463617021522 0ustar mahmoudyfreeshell--- # Build and push verilator docker image when tags are pushed to the repository. # The following variable(s) must be configured in the github repository: # DOCKER_HUB_NAMESPACE: docker hub namespace. # The following secrets must be configured in the github repository: # DOCKER_HUB_USER: user name for logging into docker hub # DOCKER_HUB_ACCESS_TOKEN: docker hub access token. name: Build Verilator Container on: push: tags: ['v*'] workflow_dispatch: inputs: manual_tag: description: 'Git tag to use for image build' required: true type: string add_latest_tag: description: 'Tag workflow_dispatch docker image as "latest"' required: true type: boolean default: false permissions: contents: write jobs: build: runs-on: ubuntu-24.04 strategy: matrix: contexts: - "ci/docker/run:verilator" # - "ci/docker/buildenv:verilator-buildenv" steps: - name: Checkout uses: actions/checkout@v6 - name: Extract context variables run: | echo "${{ matrix.contexts }}" | sed -r 's/(.*):.*/build_context=\1/' >> "$GITHUB_ENV" echo "${{ matrix.contexts }}" | sed -r 's/.*:(.*)/image_name=\1/' >> "$GITHUB_ENV" echo "git_tag=${GITHUB_REF#refs/*/}" >> "$GITHUB_ENV" - name: Use manual tag if: ${{ inputs.manual_tag }} run: | echo "git_tag=${{ inputs.manual_tag }}" >> "$GITHUB_ENV" - name: Docker meta id: docker_meta uses: docker/metadata-action@v5 with: images: | ${{ vars.DOCKER_HUB_NAMESPACE }}/${{ env.image_name }} tags: | type=match,pattern=(v.*),group=1,enable=${{ startsWith(github.ref, 'refs/tags/v') }} type=raw,value=${{ inputs.manual_tag }},enable=${{ inputs.manual_tag != '' }} type=raw,value=latest,enable=${{ inputs.add_latest_tag == true }} - name: Set up QEMU uses: docker/setup-qemu-action@v3 - name: Set up Docker Buildx uses: docker/setup-buildx-action@v3 with: buildkitd-flags: --debug - name: Login to Docker Hub uses: docker/login-action@v3 with: username: ${{ secrets.DOCKER_HUB_USER }} password: ${{ secrets.DOCKER_HUB_ACCESS_TOKEN }} - name: Build and Push to Docker uses: docker/build-push-action@v6 if: startsWith(github.ref, 'refs/tags/v') || github.event_name == 'workflow_dispatch' with: context: ${{ env.build_context }} build-args: SOURCE_COMMIT=${{ env.git_tag }} platforms: linux/arm64,linux/amd64 push: ${{ !env.ACT && (startsWith(github.ref, 'refs/tags/v') || github.event_name == 'workflow_dispatch') }} tags: ${{ steps.docker_meta.outputs.tags }} labels: ${{ steps.docker_meta.outputs.labels }} verilator-5.044/.github/workflows/coverage.yml0000644000542200017500000001740615125463617022050 0ustar mahmoudyfreeshell--- # DESCRIPTION: Github actions config # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 name: Code coverage on: workflow_dispatch: schedule: - cron: '0 0 * * 0' # weekly pull_request: types: [opened, synchronize, reopened, labeled, unlabeled] permissions: contents: read defaults: run: shell: bash concurrency: # At most 1 job per branch. Auto cancel all but scheduled jobs group: ${{ github.workflow }}-${{ github.ref }} cancel-in-progress: ${{ github.event_name != 'schedule' }} jobs: build: name: Build # Only run scheduled jobs if explicitly enabled for that repo (e.g.: not on forks) # Only run pull request jobs if labelled as needing an coverage run # Always run workflow dispatch jobs if: | (github.event_name == 'schedule' && vars.ENABLE_SCHEDULED_JOBS == 'true') || (github.event_name == 'pull_request' && contains(github.event.pull_request.labels.*.name, 'pr: dev-coverage')) || (github.event_name == 'workflow_dispatch') uses: ./.github/workflows/reusable-build.yml with: # For pull requests, build the head of the pull request branch, not the # merge commit, otherwise patch coverage would include the changes # between the root of the pull request and the target branch sha: ${{ github.event_name == 'pull_request' && github.event.pull_request.head.sha || github.sha }} os: ubuntu-24.04 os-name: linux cc: gcc dev-asan: 0 dev-gcov: 1 test: name: Test | ${{ matrix.test }}${{ matrix.num }} needs: build uses: ./.github/workflows/reusable-test.yml with: archive: ${{ needs.build.outputs.archive }} os: ubuntu-24.04 cc: gcc reloc: 0 suite: ${{ matrix.test }}${{ matrix.num }} dev-gcov: 1 strategy: fail-fast: false matrix: test: [coverage-vlt-, coverage-vltmt-] num: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9] include: - {test: coverage-dist, num: ''} publish-codecov: name: Publish results to codecov.io needs: test if: ${{ contains(needs.*.result, 'success') && !cancelled() }} runs-on: ubuntu-24.04 steps: - name: Checkout uses: actions/checkout@v6 - name: Download code coverage data uses: actions/download-artifact@v7 with: pattern: code-coverage-* path: obj_coverage merge-multiple: true - name: List files id: list-files run: | ls -lsha obj_coverage find obj_coverage -type f | paste -sd, | sed "s/^/files=/" >> "$GITHUB_OUTPUT" - name: Upload to codecov.io uses: codecov/codecov-action@v5 with: disable_file_fixes: true disable_search: true fail_ci_if_error: true files: ${{ steps.list-files.outputs.files }} plugins: noop token: ${{ secrets.CODECOV_TOKEN }} verbose: true prepare-report: name: Prepare HTML report needs: [build, test] if: ${{ contains(needs.*.result, 'success') && !cancelled() }} runs-on: ubuntu-24.04 steps: - name: Install dependencies run: | echo 'set man-db/auto-update false' | sudo debconf-communicate >/dev/null sudo dpkg-reconfigure man-db sudo apt install lcov - name: Download repository archive uses: actions/download-artifact@v7 with: name: ${{ needs.build.outputs.archive }} path: ${{ github.workspace }} - name: Unpack repository archive run: | tar -x -z -f ${{ needs.build.outputs.archive }} ls -lsha - name: Download code coverage data uses: actions/download-artifact@v7 with: pattern: code-coverage-* path: repo/obj_coverage merge-multiple: true - name: Create report working-directory: repo env: GH_TOKEN: ${{ github.token }} run: | ls -lsha obj_coverage # Combine reports from test jobs nodist/fastcov.py -C obj_coverage/verilator-*.info --lcov -o obj_coverage/verilator.info # For a PR, report patch coverage against the merge-base between the head of the PR and the target branch if [[ "${{ github.event_name }}" == "pull_request" ]]; then COVERAGE_BASE=$(git rev-parse --short $(git merge-base ${{ github.event.pull_request.base.sha }} ${{ github.event.pull_request.head.sha }})) make coverage-report COVERAGE_BASE=${COVERAGE_BASE} |& tee ${{ github.workspace }}/make-coverage-report.log else make coverage-report fi # Remove data files rm -f obj_coverage/verilator*.info # Some extra work for PRs only if [[ "${{ github.event_name }}" == "pull_request" ]]; then # Save PR number in report echo ${{ github.event.number }} > obj_coverage/pr-number.txt # Generate notification comment content mkdir -p notification echo ${{ github.event.number }} > notification/pr-number.txt NUM=$(gh run view ${{ github.run_id }} --json number --jq ".number") URL=$(gh run view ${{ github.run_id }} --json url --jq ".url") echo "Patch coverage from PR workflow [#$NUM]($URL) (code coverage of lines changed relative to ${COVERAGE_BASE}):" > notification/body.txt if [[ ! -f obj_coverage/empty-patch ]]; then echo "
" >> notification/body.txt
              grep -E "(lines|branches)\.*:" ${{ github.workspace }}/make-coverage-report.log | sed "s/\.*:/:/" >> notification/body.txt || true
              echo "
" >> notification/body.txt echo "Report: [${{ github.run_id }}](https://${{ github.repository_owner }}.github.io/verilator/coverage-reports/${{ github.run_id }}/index.html)" >> notification/body.txt else echo "Patch contains no code changes" >> notification/body.txt fi cat notification/body.txt fi - name: Upload report uses: actions/upload-artifact@v6 with: path: repo/obj_coverage name: coverage-report - name: Upload notification if: ${{ github.event_name == 'pull_request' }} uses: actions/upload-artifact@v6 with: path: repo/notification name: coverage-pr-notification # Create GitHub issue for failed scheduled jobs # This should always be the last job (we want an issue if anything breaks) create-issue: name: Create issue on failure needs: [publish-codecov, prepare-report] if: ${{ github.event_name == 'schedule' && github.repository == 'verilator/verilator' && github.run_attempt == 1 && failure() && !cancelled() }} runs-on: ubuntu-24.04 steps: # Creating issues requires elevated privilege - name: Generate access token id: generate-token uses: actions/create-github-app-token@v2.2.1 with: app-id: ${{ vars.VERILATOR_CI_ID }} private-key: ${{ secrets.VERILATOR_CI_KEY }} owner: verilator repositories: verilator permission-issues: write - name: Create issue env: GH_TOKEN: ${{ steps.generate-token.outputs.token }} run: |- echo "This issue was created automatically by the GitHub Actions CI due to the failure of a scheduled Code coverage run." >> body.txt echo "" >> body.txt echo "Workflow status: ${{ github.server_url }}/${{ github.repository }}/actions/runs/${{ github.run_id }}" >> body.txt gh issue --repo ${{ github.repository }} create \ --title "Code coverage run #${{ github.run_number }} Failed" \ --body-file body.txt \ --label new \ --assignee gezalore,wsnyder verilator-5.044/.github/workflows/pages.yml0000644000542200017500000000437315125463617021353 0ustar mahmoudyfreeshell--- # DESCRIPTION: Github actions config # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 name: Pages on: push: branches: [master] paths: ["ci/**", ".github/workflows"] workflow_dispatch: workflow_run: workflows: ["Code coverage"] types: [completed] # Sets permissions of the GITHUB_TOKEN to allow deployment to GitHub Pages permissions: contents: read pages: write id-token: write # Allow only one concurrent deployment, skipping runs queued between the run # in-progress and latest queued. However, do NOT cancel in-progress runs as we # want to allow these deployments to complete. concurrency: group: "pages" cancel-in-progress: false defaults: run: shell: bash jobs: build: name: Build content runs-on: ubuntu-24.04 outputs: coverage-pr-run-ids: ${{ steps.build.outputs.coverage-pr-run-ids }} steps: - name: Checkout uses: actions/checkout@v6 - name: Build pages id: build env: GH_TOKEN: ${{ github.token }} run: | bash -x ./ci/ci-pages.bash ls -lsha tree -L 3 pages - name: Upload pages artifact uses: actions/upload-pages-artifact@v4 with: path: pages deploy: name: Deploy needs: build runs-on: ubuntu-24.04 environment: name: github-pages url: ${{ steps.deployment.outputs.page_url }} steps: - name: Deploy to GitHub Pages uses: actions/deploy-pages@v4 notify: name: Notify needs: [build, deploy] runs-on: ubuntu-24.04 if: ${{ github.repository == 'verilator/verilator' }} steps: - name: Checkout uses: actions/checkout@v6 # Use the Verilator CI app to post the comment - name: Generate access token id: generate-token uses: actions/create-github-app-token@v2.2.1 with: app-id: ${{ vars.VERILATOR_CI_ID }} private-key: ${{ secrets.VERILATOR_CI_KEY }} permission-actions: write permission-pull-requests: write - name: Comment on PR env: GH_TOKEN: ${{ steps.generate-token.outputs.token }} COVERAGE_PR_RUN_IDS: ${{ needs.build.outputs.coverage-pr-run-ids }} run: bash -x ./ci/ci-pages-notify.bash verilator-5.044/.codecov.yml0000644000542200017500000000104315125463617016346 0ustar mahmoudyfreeshell--- # DESCRIPTION: codecov.io config # # Copyright 2020-2026 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 #################### # Validate: # curl --data-binary @.codecov.yml https://codecov.io/validate # coverage: precision: 2 range: 75...100 round: down status: project: false patch: false comment: false verilator-5.044/.gitattributes0000644000542200017500000000027215125463617017021 0ustar mahmoudyfreeshell*.v linguist-language=SystemVerilog *.vh linguist-language=SystemVerilog *.sv linguist-language=SystemVerilog Changes linguist-language=reStructuredText nodist linguist-detectable=false verilator-5.044/README.rst0000644000542200017500000001547715125463617015632 0ustar mahmoudyfreeshell.. Github doesn't render images unless absolute URL .. Do not know of a conditional tag, "only: github" nor "github display" works |badge1| |badge2| |badge3| |badge4| |badge5| |badge7| |badge8| .. |badge1| image:: https://img.shields.io/badge/Website-Verilator.org-181717.svg :target: https://verilator.org .. |badge2| image:: https://img.shields.io/badge/License-LGPL%20v3-blue.svg :target: https://www.gnu.org/licenses/lgpl-3.0 .. |badge3| image:: https://img.shields.io/badge/License-Artistic%202.0-0298c3.svg :target: https://opensource.org/licenses/Artistic-2.0 .. |badge4| image:: https://repology.org/badge/tiny-repos/verilator.svg?header=distro%20packages :target: https://repology.org/project/verilator/versions .. |badge5| image:: https://img.shields.io/docker/pulls/verilator/verilator :target: https://hub.docker.com/r/verilator/verilator .. |badge7| image:: https://github.com/verilator/verilator/workflows/build/badge.svg :target: https://github.com/verilator/verilator/actions?query=workflow%3Abuild .. |badge8| image:: https://img.shields.io/github/actions/workflow/status/verilator/verilator/rtlmeter.yml?branch=master&event=schedule&label=benchmarks :target: https://verilator.github.io/verilator-rtlmeter-results Welcome to Verilator ==================== .. list-table:: * - **Welcome to Verilator, the fastest Verilog/SystemVerilog simulator.** * Accepts Verilog or SystemVerilog * Performs lint code-quality checks * Compiles into multithreaded C++, or SystemC * Creates XML to front-end your own tools - |Logo| * - |verilator multithreaded performance| - **Fast** * Outperforms many closed-source commercial simulators * Single- and multithreaded output models * - **Widely Used** * Wide industry and academic deployment * Out-of-the-box support from Arm and RISC-V vendor IP * Over 700 contributors - |verilator usage| * - |verilator community| - **Community Driven & Openly Licensed** * Guided by the `CHIPS Alliance`_ and `Linux Foundation`_ * Open, and free as in both speech and beer * More simulation for your verification budget * - **Commercial Support Available** * Commercial support contracts * Design support contracts * Enhancement contracts - |verilator support| What Verilator Does =================== Verilator is invoked with parameters similar to GCC or Synopsys's VCS. It "Verilates" the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multithreaded .cpp and .h files, the "Verilated" code. These Verilated C++/SystemC files are then compiled by a C++ compiler (gcc/clang/MSVC++), optionally along with a user's own C++/SystemC wrapper file, to instantiate the Verilated model. Executing the resulting executable performs the design simulation. Verilator also supports linking Verilated generated libraries, optionally encrypted, into other simulators. Verilator may not be the best choice if you are expecting a full-featured replacement for a closed-source Verilog simulator, need SDF annotation, mixed-signal simulation, or are doing a quick class project (we recommend `Icarus Verilog`_ for classwork). However, if you are looking for a path to migrate SystemVerilog to C++/SystemC, or want high-speed simulation of designs, Verilator is the tool for you. Performance =========== Verilator does not directly translate Verilog HDL to C++ or SystemC. Rather, Verilator compiles your code into a much faster optimized and optionally thread-partitioned model, which is in turn wrapped inside a C++/SystemC module. The results are a compiled Verilog model that executes even on a single thread over 10x faster than standalone SystemC, and on a single thread is about 100 times faster than interpreted Verilog simulators such as `Icarus Verilog`_. Another 2-10x speedup might be gained from multithreading (yielding 200-1000x total over interpreted simulators). Verilator has typically similar or better performance versus closed-source Verilog simulators (e.g., Aldec Riviera-Pro, Cadence Incisive/NC-Verilog, Mentor ModelSim/Questa, Synopsys VCS, VTOC, and Pragmatic CVer/CVC). But, Verilator is open-sourced, so you can spend on computes rather than licenses. Thus, Verilator gives you the best simulation cycles/dollar. Installation & Documentation ============================ For more information: - `Verilator installation and package directory structure `_ - `Verilator manual (HTML) `_, or `Verilator manual (PDF) `_ - `Subscribe to Verilator announcements `_ - `Verilator forum `_ - `Verilator issues `_ Support ======= Verilator is a community project, guided by the `CHIPS Alliance`_ under the `Linux Foundation`_. We appreciate and welcome your contributions in whatever form; please see `Contributing to Verilator `_. Thanks to our `Contributors and Sponsors `_. Verilator also supports and encourages commercial support models and organizations; please see `Verilator Commercial Support `_. Related Projects ================ - `GTKwave `_ - Waveform viewer for Verilator traces. - `Icarus Verilog`_ - Icarus is a highly-featured interpreted Verilog simulator. If Verilator does not support your needs, perhaps Icarus may. - `Surfer `_ - Web or offline waveform viewer for Verilator traces. Open License ============ Verilator is Copyright 2003-2026 by Wilson Snyder. (Report bugs to `Verilator Issues `_.) Verilator is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. See the documentation for more details. .. _chips alliance: https://chipsalliance.org .. _icarus verilog: https://steveicarus.github.io/iverilog .. _linux foundation: https://www.linuxfoundation.org .. |Logo| image:: https://www.veripool.org/img/verilator_256_200_min.png .. |verilator multithreaded performance| image:: https://www.veripool.org/img/verilator_multithreaded_performance_bg-min.png .. |verilator usage| image:: https://www.veripool.org/img/verilator_usage_400x200-min.png .. |verilator community| image:: https://www.veripool.org/img/verilator_community_400x125-min.png .. |verilator support| image:: https://www.veripool.org/img/verilator_support_400x125-min.png verilator-5.044/verilator-config.cmake.in0000644000542200017500000007346415125463617021024 0ustar mahmoudyfreeshell###################################################################### # # DESCRIPTION: CMake configuration file for Verilator # # Include it in your CMakeLists.txt using: # # find_package(verilator) # # This script adds a verilate function. # # add_executable(simulator ) # verilate(simulator SOURCES ) # # Copyright 2003-2026 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### cmake_minimum_required(VERSION 3.19) # Prefer VERILATOR_ROOT from environment if(DEFINED ENV{VERILATOR_ROOT}) set(VERILATOR_ROOT "$ENV{VERILATOR_ROOT}" CACHE PATH "VERILATOR_ROOT") endif() set(VERILATOR_ROOT "${CMAKE_CURRENT_LIST_DIR}" CACHE PATH "VERILATOR_ROOT") find_program( VERILATOR_BIN NAMES verilator_bin verilator_bin.exe HINTS ${VERILATOR_ROOT}/bin ENV VERILATOR_ROOT NO_CMAKE_PATH NO_CMAKE_ENVIRONMENT_PATH NO_CMAKE_SYSTEM_PATH ) if(NOT VERILATOR_ROOT) message( FATAL_ERROR "VERILATOR_ROOT cannot be detected. Set it to the appropriate directory (e.g. /usr/share/verilator) as an environment variable or CMake define." ) endif() if(NOT VERILATOR_BIN) message(FATAL_ERROR "Cannot find verilator_bin excecutable.") endif() set(verilator_FOUND 1) include(CheckCXXSourceCompiles) function(_verilator_check_cxx_libraries LIBRARIES RESVAR) # Check whether a particular link option creates a valid executable set(_VERILATOR_CHECK_CXX_LINK_OPTIONS_SRC "int main() {return 0;}\n") set(CMAKE_REQUIRED_FLAGS) set(CMAKE_REQUIRED_DEFINITIONS) set(CMAKE_REQUIRED_INCLUDES) set(CMAKE_REQUIRED_LINK_OPTIONS) set(CMAKE_REQUIRED_LIBRARIES ${LIBRARIES}) set(CMAKE_REQUIRED_QUIET) check_cxx_source_compiles( "${_VERILATOR_CHECK_CXX_LINK_OPTIONS_SRC}" "${RESVAR}" ) set("${RESVAR}" "${${RESVAR}}" PARENT_SCOPE) endfunction() function(_verilator_check_cxx_compiler_flag FLAG RESVAR) # Check whether the compiler understands the flag FLAG set(_VERILATOR_CHECK_CXX_COMPILER_FLAG_SRC " #warning warning int main() { return 0; } " ) set(CMAKE_REQUIRED_FLAGS ${FLAG}) # Make sure the compiler warning is not turned into an error string(APPEND CMAKE_REQUIRED_FLAGS " -Wno-error=cpp") set(CMAKE_REQUIRED_DEFINITIONS) set(CMAKE_REQUIRED_INCLUDES) set(CMAKE_REQUIRED_LINK_OPTIONS) set(CMAKE_REQUIRED_LIBRARIES) set(CMAKE_REQUIRED_QUIET) check_compiler_flag_common_patterns(_common_patterns) check_cxx_source_compiles( "${_VERILATOR_CHECK_CXX_COMPILER_FLAG_SRC}" "${RESVAR}" FAIL_REGEX "command[ -]line option .* is valid for .* but not for C[+][+]" FAIL_REGEX "-Werror=.* argument .* is not valid for C[+][+]" ${_common_patterns} ) set("${RESVAR}" "${${RESVAR}}" PARENT_SCOPE) endfunction() # Check compiler flag support. Skip on MSVC, these are all GCC flags. if(NOT CMAKE_CXX_COMPILER_ID MATCHES MSVC) if(NOT DEFINED VERILATOR_CFLAGS OR NOT DEFINED VERILATOR_MT_CFLAGS) include(CheckCXXCompilerFlag) foreach(FLAG @CFG_CXX_FLAGS_CMAKE@) string(MAKE_C_IDENTIFIER ${FLAG} FLAGNAME) _verilator_check_cxx_compiler_flag(${FLAG} ${FLAGNAME}) if(${FLAGNAME}) list(APPEND VERILATOR_CFLAGS $<$:${FLAG}>) endif() endforeach() foreach(FLAG @CFG_LDFLAGS_THREADS_CMAKE@) string(MAKE_C_IDENTIFIER ${FLAG} FLAGNAME) _verilator_check_cxx_libraries("${FLAG}" ${FLAGNAME}) if(${FLAGNAME}) list(APPEND VERILATOR_MT_CFLAGS ${FLAG}) endif() endforeach() endif() endif() if(APPLE) add_link_options(-Wl,-U,__Z15vl_time_stamp64v,-U,__Z13sc_time_stampv) endif() define_property( TARGET PROPERTY VERILATOR_THREADED BRIEF_DOCS "Deprecated and has no effect (ignored)" FULL_DOCS "Deprecated and has no effect (ignored)" ) define_property( TARGET PROPERTY VERILATOR_TRACE_THREADED BRIEF_DOCS "Verilator multithread tracing enabled" FULL_DOCS "Verilator multithread tracing enabled" ) define_property( TARGET PROPERTY VERILATOR_TIMING BRIEF_DOCS "Verilator timing enabled" FULL_DOCS "Verilator timing enabled" ) define_property( TARGET PROPERTY VERILATOR_COVERAGE BRIEF_DOCS "Verilator coverage enabled" FULL_DOCS "Verilator coverage enabled" ) define_property( TARGET PROPERTY VERILATOR_TRACE BRIEF_DOCS "Verilator trace enabled" FULL_DOCS "Verilator trace enabled" ) define_property( TARGET PROPERTY VERILATOR_TRACE_FST BRIEF_DOCS "Verilator FST trace enabled" FULL_DOCS "Verilator FST trace enabled" ) define_property( TARGET PROPERTY VERILATOR_TRACE_SAIF BRIEF_DOCS "Verilator SAIF trace enabled" FULL_DOCS "Verilator SAIF trace enabled" ) define_property( TARGET PROPERTY VERILATOR_TRACE_VCD BRIEF_DOCS "Verilator VCD trace enabled" FULL_DOCS "Verilator VCD trace enabled" ) define_property( TARGET PROPERTY VERILATOR_SYSTEMC BRIEF_DOCS "Verilator SystemC enabled" FULL_DOCS "Verilator SystemC enabled" ) define_property( TARGET PROPERTY VERILATOR_TRACE_STRUCTS BRIEF_DOCS "Verilator trace structs enabled" FULL_DOCS "Verilator trace structs enabled" ) function(json_get_string RET JSON SECTION VARIABLE) string(JSON JV ERROR_VARIABLE STATUS GET "${JSON}" ${SECTION} ${VARIABLE}) if(NOT ${STATUS} STREQUAL "NOTFOUND") set(JV "") endif() set(${RET} ${JV} PARENT_SCOPE) endfunction() function(json_get_bool RET JSON SECTION VARIABLE) string(JSON JV GET "${JSON}" ${SECTION} ${VARIABLE}) if(JV) set(${RET} 1 PARENT_SCOPE) else() set(${RET} 0 PARENT_SCOPE) endif() endfunction() function(json_get_int RET JSON SECTION VARIABLE) string(JSON JV GET "${JSON}" ${SECTION} ${VARIABLE}) set(${RET} ${JV} PARENT_SCOPE) endfunction() function(json_get_submodules SUBMODULES NSUBMODULES JSON) string(JSON JV ERROR_VARIABLE STATUS GET "${JSON}" submodules) if(NOT ${STATUS} STREQUAL "NOTFOUND") set(${SUBMODULES} "" PARENT_SCOPE) set(${NSUBMODULES} 0 PARENT_SCOPE) return() endif() string(JSON L ERROR_VARIABLE STATUS LENGTH "${JSON}" submodules) math(EXPR L "${L}-1") set(${SUBMODULES} ${JV} PARENT_SCOPE) set(${NSUBMODULES} ${L} PARENT_SCOPE) endfunction() function(json_get_list RET JSON SECTION VARIABLE) string(JSON L ERROR_VARIABLE STATUS LENGTH "${JSON}" ${SECTION} ${VARIABLE}) if(NOT ${STATUS} STREQUAL "NOTFOUND" OR NOT ${L}) set(${RET} "" PARENT_SCOPE) return() endif() math(EXPR L "${L}-1") foreach(I RANGE ${L}) string(JSON JV GET "${JSON}" ${SECTION} ${VARIABLE} ${I}) if(NOT JL) string(APPEND JL "${JV}") else() string(APPEND JL " ${JV}") endif() endforeach() set(${RET} ${JL} PARENT_SCOPE) endfunction() function(verilate TARGET) cmake_parse_arguments( VERILATE "COVERAGE;SYSTEMC;TRACE_FST;TRACE_SAIF;TRACE_VCD;TRACE;TRACE_STRUCTS" "PREFIX;TOP_MODULE;THREADS;TRACE_THREADS;DIRECTORY" "SOURCES;VERILATOR_ARGS;INCLUDE_DIRS;OPT_SLOW;OPT_FAST;OPT_GLOBAL" ${ARGN} ) if(VERILATE_TRACE) if(NOT VERILATE_TRACE_VCD) set(VERILATE_TRACE_VCD TRUE) endif() message( DEPRECATION "The `TRACE` argument is deprecated. Please use `TRACE_VCD` instead." ) endif() if(NOT VERILATE_SOURCES) message(FATAL_ERROR "Need at least one source") endif() if(NOT VERILATE_PREFIX) list(LENGTH VERILATE_SOURCES NUM_SOURCES) if(${NUM_SOURCES} GREATER 1) message(WARNING "Specify PREFIX if there are multiple SOURCES") endif() list(GET VERILATE_SOURCES 0 TOPSRC) get_filename_component(_SRC_NAME ${TOPSRC} NAME_WE) string(MAKE_C_IDENTIFIER V${_SRC_NAME} VERILATE_PREFIX) endif() if(VERILATE_TOP_MODULE) list(APPEND VERILATOR_ARGS --top ${VERILATE_TOP_MODULE}) endif() if(VERILATE_THREADS) list(APPEND VERILATOR_ARGS --threads ${VERILATE_THREADS}) endif() if(VERILATE_TRACE_THREADS) list(APPEND VERILATOR_ARGS --trace-threads ${VERILATE_TRACE_THREADS}) endif() if(VERILATE_COVERAGE) list(APPEND VERILATOR_ARGS --coverage) endif() if(VERILATE_SYSTEMC) list(APPEND VERILATOR_ARGS --sc) else() list(APPEND VERILATOR_ARGS --cc) endif() if(VERILATE_TRACE AND VERILATE_TRACE_FST) message(FATAL_ERROR "Cannot have both TRACE and TRACE_FST") endif() if(VERILATE_TRACE_FST AND VERILATE_TRACE_VCD) message(FATAL_ERROR "Cannot have both TRACE_FST and TRACE_VCD") endif() if(VERILATE_TRACE_SAIF AND VERILATE_TRACE_VCD) message(FATAL_ERROR "Cannot have both TRACE_SAIF and TRACE_VCD") endif() if(VERILATE_TRACE) list(APPEND VERILATOR_ARGS --trace-vcd) endif() if(VERILATE_TRACE_FST) list(APPEND VERILATOR_ARGS --trace-fst) endif() if(VERILATE_TRACE_SAIF) list(APPEND VERILATOR_ARGS --trace-saif) endif() if(VERILATE_TRACE_VCD) list(APPEND VERILATOR_ARGS --trace-vcd) endif() if(VERILATE_TRACE_STRUCTS) list(APPEND VERILATOR_ARGS --trace-structs) endif() foreach(INC ${VERILATE_INCLUDE_DIRS}) list(APPEND VERILATOR_ARGS -y "${INC}") endforeach() string(TOLOWER ${CMAKE_CXX_COMPILER_ID} COMPILER) if(COMPILER STREQUAL "appleclang") set(COMPILER clang) elseif(NOT COMPILER MATCHES "^msvc$|^clang$") set(COMPILER gcc) endif() set(OBJCACHE "" CACHE STRING "Path for ccache, auto-detected if empty") option(OBJCACHE_ENABLED "Compile Verilator with ccache" ON) if(OBJCACHE_ENABLED) if(OBJCACHE STREQUAL "") find_program(OBJCACHE_PATH ccache) if(OBJCACHE_PATH STREQUAL "OBJCACHE_PATH-NOTFOUND") set(OBJCACHE_PATH "") endif() else() set(OBJCACHE_PATH "${OBJCACHE}") endif() if(NOT OBJCACHE_PATH STREQUAL "") execute_process( COMMAND "${OBJCACHE_PATH}" --version OUTPUT_VARIABLE objcache_version ) string( REGEX MATCH "[^\n\r]+" objcache_version "${objcache_version}" ) message( STATUS "Found ccache: ${OBJCACHE_PATH} (\"${objcache_version}\")" ) set_property(GLOBAL PROPERTY RULE_LAUNCH_COMPILE "${OBJCACHE_PATH}") endif() endif() get_target_property(BINARY_DIR "${TARGET}" BINARY_DIR) get_target_property(TARGET_NAME "${TARGET}" NAME) set(VDIR "${BINARY_DIR}/CMakeFiles/${TARGET_NAME}.dir/${VERILATE_PREFIX}.dir" ) if(VERILATE_DIRECTORY) set(VDIR "${VERILATE_DIRECTORY}") endif() file(MAKE_DIRECTORY ${VDIR}) set(VERILATOR_COMMAND "${CMAKE_COMMAND}" -E env "VERILATOR_ROOT=${VERILATOR_ROOT}" "${VERILATOR_BIN}" --compiler ${COMPILER} --prefix ${VERILATE_PREFIX} --Mdir ${VDIR} --make json ${VERILATOR_ARGS} ${VERILATE_VERILATOR_ARGS} ${VERILATE_SOURCES} ) set(VARGS_FILE "${VDIR}/verilator_args.txt") set(VCMAKE "${VDIR}/${VERILATE_PREFIX}.cmake") set(VCMAKE_COPY "${VDIR}/${VERILATE_PREFIX}_copy.cmake") if(NOT EXISTS "${VARGS_FILE}" OR NOT EXISTS "${VCMAKE_COPY}") set(VERILATOR_OUTDATED ON) else() file(READ "${VARGS_FILE}" PREVIOUS_VERILATOR_COMMAND) if(NOT VERILATOR_COMMAND STREQUAL PREVIOUS_VERILATOR_COMMAND) set(VERILATOR_OUTDATED ON) endif() endif() if(VERILATOR_OUTDATED) message(STATUS "Executing Verilator...") execute_process( COMMAND ${VERILATOR_COMMAND} WORKING_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}" RESULT_VARIABLE _VERILATOR_RC OUTPUT_VARIABLE _VERILATOR_OUTPUT ERROR_VARIABLE _VERILATOR_OUTPUT ) if(_VERILATOR_RC) string( REPLACE ";" " " VERILATOR_COMMAND_READABLE "${VERILATOR_COMMAND}" ) message("Verilator command: \"${VERILATOR_COMMAND_READABLE}\"") message("Output:\n${_VERILATOR_OUTPUT}") message( FATAL_ERROR "Verilator command failed (return code=${_VERILATOR_RC})" ) endif() file(READ ${VDIR}/${VERILATE_PREFIX}.json MANIFEST) json_get_string(JSYSTEM_PERL "${MANIFEST}" system perl) json_get_string(JSYSTEM_PYTHON3 "${MANIFEST}" system python3) json_get_string(JSYSTEM_VERILATOR_ROOT "${MANIFEST}" system verilator_root) json_get_string(JSYSTEM_VERILATOR_SOLVER "${MANIFEST}" system verilator_solver) json_get_list(JOPTIONS_CFLAGS "${MANIFEST}" options cflags) json_get_list(JOPTIONS_LDFLAGS "${MANIFEST}" options ldflags) json_get_bool(JOPTIONS_SYSTEM_C "${MANIFEST}" options system_c) json_get_bool(JOPTIONS_COVERAGE "${MANIFEST}" options coverage) json_get_bool(JOPTIONS_USE_TIMING "${MANIFEST}" options use_timing) json_get_int(JOPTIONS_THREADS "${MANIFEST}" options threads) json_get_bool(JOPTIONS_TRACE_FST "${MANIFEST}" options trace_fst) json_get_bool(JOPTIONS_TRACE_SAIF "${MANIFEST}" options trace_saif) json_get_bool(JOPTIONS_TRACE_VCD "${MANIFEST}" options trace_vcd) json_get_list(JSOURCES_GLOBAL "${MANIFEST}" sources global) json_get_list(JSOURCES_CLASSES_SLOW "${MANIFEST}" sources classes_slow) json_get_list(JSOURCES_CLASSES_FAST "${MANIFEST}" sources classes_fast) json_get_list(JSOURCES_SUPPORT_SLOW "${MANIFEST}" sources support_slow) json_get_list(JSOURCES_SUPPORT_FAST "${MANIFEST}" sources support_fast) json_get_list(JSOURCES_USER_CLASSES "${MANIFEST}" sources user_classes) json_get_list(JSOURCES_DEPS "${MANIFEST}" sources deps) file( WRITE ${VDIR}/${VERILATE_PREFIX}.cmake "# Verilated -*- CMake -*-\n" "# DESCRIPTION: Verilator output: CMake include script with class lists\n" "#\n" "# This CMake script lists generated Verilated files, for including in higher level CMake scripts.\n" "# This file is meant to be consumed by the verilate() function,\n" "# which becomes available after executing `find_package(verilator).\n\n" "### Constants...\n" "set(PERL \"${JSYSTEM_PERL}\" CACHE FILEPATH \"Perl executable (from \$PERL, defaults to 'perl' if not set)\")\n" "set(PYTHON3 \"${JSYSTEM_PYTHON3}\" CACHE FILEPATH \"Python3 executable (from \$PYTHON3, defaults to 'python3' if not set)\")\n" "set(VERILATOR_ROOT \"${JSYSTEM_VERILATOR_ROOT}\" CACHE PATH \"Path to Verilator kit (from $VERILATOR_ROOT)\")\n" "set(VERILATOR_SOLVER \"${JSYSTEM_VERILATOR_SOLVER}\" CACHE STRING \"Default SMT solver for constrained randomization (from \$VERILATOR_SOLVER)\")\n\n" "### Compiler flags...\n" "# User CFLAGS (from -CFLAGS on Verilator command line)\n" "set(${VERILATE_PREFIX}_USER_CFLAGS ${JOPTIONS_CFLAGS})\n" "# User LDLIBS (from -LDFLAGS on Verilator command line)\n" "set(${VERILATE_PREFIX}_USER_LDLIBS ${JOPTIONS_LDFLAGS})\n\n" "### Switches...\n" "# SystemC output mode? 0/1 (from --sc)\n" "set(${VERILATE_PREFIX}_SC ${JOPTIONS_SYSTEM_C})\n" "# Coverage output mode? 0/1 (from --coverage)\n" "set(${VERILATE_PREFIX}_COVERAGE ${JOPTIONS_COVERAGE})\n" "# Timing mode? 0/1\n" "set(${VERILATE_PREFIX}_TIMING ${JOPTIONS_USE_TIMING})\n" "# Threaded output mode? 1/N threads (from --threads)\n" "set(${VERILATE_PREFIX}_THREADS ${JOPTIONS_THREADS})\n" "# FST Tracing output mode? 0/1 (from --trace-fst)\n" "set(${VERILATE_PREFIX}_TRACE_FST ${JOPTIONS_TRACE_FST})\n\n" "# SAIF Tracing output mode? 0/1 (from --trace-saif)\n" "set(${VERILATE_PREFIX}_TRACE_SAIF ${JOPTIONS_TRACE_SAIF})\n\n" "# VCD Tracing output mode? 0/1 (from --trace-vcd)\n" "set(${VERILATE_PREFIX}_TRACE_VCD ${JOPTIONS_TRACE_VCD})\n" "### Sources...\n" "# Global classes, need linked once per executable\n" "set(${VERILATE_PREFIX}_GLOBAL ${JSOURCES_GLOBAL})\n" "# Generated module classes, non-fast-path, compile with low/medium optimization\n" "set(${VERILATE_PREFIX}_CLASSES_SLOW ${JSOURCES_CLASSES_SLOW})\n" "# Generated module classes, fast-path, compile with highest optimization\n" "set(${VERILATE_PREFIX}_CLASSES_FAST ${JSOURCES_CLASSES_FAST})\n" "# Generated support classes, non-fast-path, compile with low/medium optimization\n" "set(${VERILATE_PREFIX}_SUPPORT_SLOW ${JSOURCES_SUPPORT_SLOW})\n" "# Generated support classes, fast-path, compile with highest optimization\n" "set(${VERILATE_PREFIX}_SUPPORT_FAST ${JSOURCES_SUPPORT_FAST})\n" "# All dependencies\n" "set(${VERILATE_PREFIX}_DEPS ${JSOURCES_DEPS})\n" "# User .cpp files (from .cpp's on Verilator command line)\n" "set(${VERILATE_PREFIX}_USER_CLASSES ${JSOURCES_USER_CLASSES})\n" ) json_get_submodules(JSUBMODULES JNSUBMODULES "${MANIFEST}") if(JNSUBMODULES) file( APPEND ${VDIR}/${VERILATE_PREFIX}.cmake "# Verilate hierarchical blocks\n" "get_target_property(TOP_TARGET_NAME \"\${TARGET}\" NAME)\n" ) foreach(I RANGE ${JNSUBMODULES}) json_get_string(JSUBMODULE_PREFIX "${JSUBMODULES}" ${I} prefix) json_get_string(JSUBMODULE_TOP "${JSUBMODULES}" ${I} top) json_get_list(JSUBMODULE_DEPS "${JSUBMODULES}" ${I} deps) json_get_string(JSUBMODULE_DIRECTORY "${JSUBMODULES}" ${I} directory) json_get_list(JSUBMODULE_SOURCES "${JSUBMODULES}" ${I} sources) json_get_list(JSUBMODULE_CFLAGS "${JSUBMODULES}" ${I} cflags) json_get_string(JSUBMODILE_VERILATOR_ARGS "${JSUBMODULES}" ${I} verilator_args) set(SUBMODULE_CMAKE "") set(SUBMODULE_VERILATE_ARGS "") if(NOT ${I} STREQUAL ${JNSUBMODULES}) string( APPEND SUBMODULE_CMAKE "add_library(${JSUBMODULE_PREFIX} STATIC)\n" "target_link_libraries(\${TOP_TARGET_NAME} PRIVATE ${JSUBMODULE_PREFIX})\n" ) if(JSUBMODULE_DEPS) string( APPEND SUBMODULE_CMAKE "target_link_libraries(${JSUBMODULE_PREFIX} INTERFACE ${JSUBMODULE_DEPS})\n" ) endif() string( APPEND SUBMODULE_VERILATE_ARGS "${JSUBMODULE_PREFIX} PREFIX ${JSUBMODULE_PREFIX} TOP_MODULE ${JSUBMODULE_TOP} DIRECTORY ${JSUBMODULE_DIRECTORY} SOURCES ${JSUBMODULE_SOURCES}" ) else() string( APPEND SUBMODULE_CMAKE "# Verilate the top module that refers to lib-create wrappers of above\n" ) string( APPEND SUBMODULE_VERILATE_ARGS "\${TOP_TARGET_NAME} PREFIX ${JSUBMODULE_PREFIX} TOP_MODULE ${JSUBMODULE_TOP} DIRECTORY ${JSUBMODULE_DIRECTORY} SOURCES ${JSUBMODULE_SOURCES}" ) endif() if(JSUBMODILE_VERILATOR_ARGS) string( APPEND SUBMODULE_VERILATE_ARGS " VERILATOR_ARGS -f ${JSUBMODILE_VERILATOR_ARGS}" ) endif() if(JSUBMODULE_CFLAGS) string( APPEND SUBMODULE_VERILATE_ARGS " -CFLAGS ${JSUBMODULE_CFLAGS}" ) endif() file( APPEND ${VDIR}/${VERILATE_PREFIX}.cmake "${SUBMODULE_CMAKE}" "verilate(${SUBMODULE_VERILATE_ARGS})\n" ) endforeach() endif() execute_process( COMMAND "${CMAKE_COMMAND}" -E copy "${VCMAKE}" "${VCMAKE_COPY}" ) endif() file(WRITE "${VARGS_FILE}" "${VERILATOR_COMMAND}") include("${VCMAKE_COPY}") set(GENERATED_C_SOURCES ${${VERILATE_PREFIX}_CLASSES_FAST} ${${VERILATE_PREFIX}_CLASSES_SLOW} ${${VERILATE_PREFIX}_SUPPORT_FAST} ${${VERILATE_PREFIX}_SUPPORT_SLOW} ) # No need for .h's as the .cpp will get written same time set(GENERATED_SOURCES ${GENERATED_C_SOURCES}) add_custom_command( OUTPUT ${GENERATED_SOURCES} "${VCMAKE}" COMMAND ${VERILATOR_COMMAND} WORKING_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}" DEPENDS "${VERILATOR_BIN}" ${${VERILATE_PREFIX}_DEPS} VERBATIM ) # Reconfigure if file list has changed # (check contents rather than modified time to avoid unnecessary reconfiguration) add_custom_command( OUTPUT "${VCMAKE_COPY}" COMMAND "${CMAKE_COMMAND}" -E copy_if_different "${VCMAKE}" "${VCMAKE_COPY}" DEPENDS "${VCMAKE}" VERBATIM ) if(${VERILATE_PREFIX}_COVERAGE) # If any verilate() call specifies COVERAGE, define VM_COVERAGE in the final build set_property(TARGET ${TARGET} PROPERTY VERILATOR_COVERAGE ON) endif() if(${VERILATE_PREFIX}_SC) # If any verilate() call specifies SYSTEMC, define VM_SC in the final build set_property(TARGET ${TARGET} PROPERTY VERILATOR_SYSTEMC ON) endif() if(${VERILATE_PREFIX}_TRACE_FST) # If any verilate() call specifies TRACE_FST, define VM_TRACE_FST in the final build set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE ON) set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE_FST ON) endif() if(${VERILATE_PREFIX}_TRACE_SAIF) # If any verilate() call specifies TRACE_SAIF, define VM_TRACE_SAIF in the final build set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE ON) set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE_SAIF ON) endif() if(${VERILATE_PREFIX}_TRACE_VCD) # If any verilate() call specifies TRACE, define VM_TRACE_VCD in the final build set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE ON) set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE_VCD ON) endif() if(${VERILATE_PREFIX}_TRACE_STRUCTS) set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE_STRUCTS ON) endif() # Add the compile flags only on Verilated sources target_include_directories(${TARGET} PUBLIC ${VDIR}) target_sources( ${TARGET} PRIVATE ${GENERATED_SOURCES} "${VCMAKE_COPY}" ${${VERILATE_PREFIX}_GLOBAL} ${${VERILATE_PREFIX}_USER_CLASSES} ) foreach(_VSOURCE ${VERILATE_SOURCES} ${${VERILATE_PREFIX}_DEPS}) get_filename_component(_VSOURCE "${_VSOURCE}" ABSOLUTE BASE_DIR) list(APPEND VHD_SOURCES "${_VSOURCE}") endforeach() target_sources(${TARGET} PRIVATE ${VHD_SOURCES}) # Add the compile flags only on Verilated sources foreach( VSLOW ${${VERILATE_PREFIX}_CLASSES_SLOW} ${${VERILATE_PREFIX}_SUPPORT_SLOW} ) foreach(OPT_SLOW ${VERILATE_OPT_SLOW} ${${VERILATE_PREFIX}_USER_CFLAGS}) set_property( SOURCE "${VSLOW}" APPEND_STRING PROPERTY COMPILE_FLAGS " ${OPT_SLOW}" ) endforeach() endforeach() foreach( VFAST ${${VERILATE_PREFIX}_CLASSES_FAST} ${${VERILATE_PREFIX}_SUPPORT_FAST} ) foreach(OPT_FAST ${VERILATE_OPT_FAST} ${${VERILATE_PREFIX}_USER_CFLAGS}) set_property( SOURCE "${VFAST}" APPEND_STRING PROPERTY COMPILE_FLAGS " ${OPT_FAST}" ) endforeach() endforeach() foreach(VGLOBAL ${${VERILATE_PREFIX}_GLOBAL}) foreach( OPT_GLOBAL ${VERILATE_OPT_GLOBAL} ${${VERILATE_PREFIX}_USER_CFLAGS} ) set_property( SOURCE "${VGLOBAL}" APPEND_STRING PROPERTY COMPILE_FLAGS " ${OPT_GLOBAL}" ) endforeach() endforeach() target_include_directories( ${TARGET} PUBLIC "${VERILATOR_ROOT}/include" "${VERILATOR_ROOT}/include/vltstd" ) target_compile_definitions( ${TARGET} PRIVATE VM_COVERAGE=$> VM_SC=$> VM_TRACE=$> VM_TRACE_VCD=$> VM_TRACE_FST=$> VM_TRACE_SAIF=$> ) target_link_libraries(${TARGET} PUBLIC ${${VERILATE_PREFIX}_USER_LDLIBS}) target_link_libraries(${TARGET} PUBLIC ${VERILATOR_MT_CFLAGS}) target_compile_features(${TARGET} PRIVATE cxx_std_11) if(${VERILATE_PREFIX}_TIMING) check_cxx_compiler_flag(-fcoroutines-ts COROUTINES_TS_FLAG) target_compile_options( ${TARGET} PRIVATE $,-fcoroutines-ts,-fcoroutines> ) endif() endfunction() function(_verilator_find_systemc) if(NOT TARGET Verilator::systemc) # Find SystemC include file "systemc.h" in the following order: # 1. SYSTEMC_INCLUDE (environment) variable # 2. SYSTEMC_ROOT (environment) variable # 3. SYSTEMC (environment) variable # 4. Use CMake module provided by SystemC installation # (eventually requires CMAKE_PREFIX_PATH set) find_path( SYSTEMC_INCLUDEDIR NAMES systemc.h HINTS "${SYSTEMC_INCLUDE} " ENV SYSTEMC_INCLUDE ) find_path( SYSTEMC_INCLUDEDIR NAMES systemc.h HINTS "${SYSTEMC_ROOT}" ENV SYSTEMC_ROOT PATH_SUFFIXES include ) find_path( SYSTEMC_INCLUDEDIR NAMES systemc.h HINTS "${SYSTEMC}" ENV SYSTEMC PATH_SUFFIXES include ) # Find SystemC library in the following order: # 1. SYSTEMC_LIBDIR (environment) variable # 2. SYSTEMC_ROOT (environment) variable # 3. SYSTEMC (environment) variable # 4. Use CMake module provided by SystemC installation # (eventually requires CMAKE_PREFIX_PATH set) # Find SystemC using include and library paths find_library( SYSTEMC_LIBRARY NAMES systemc HINTS "${SYSTEMC_LIBDIR}" ENV SYSTEMC_LIBDIR ) find_library( SYSTEMC_LIBRARY NAMES systemc HINTS "${SYSTEMC_ROOT}" ENV SYSTEMC_ROOT PATH_SUFFIXES lib ) find_library( SYSTEMC_LIBRARY NAMES systemc HINTS "${SYSTEMC}" ENV SYSTEMC PATH_SUFFIXES lib ) if(SYSTEMC_INCLUDEDIR AND SYSTEMC_LIBRARY) add_library(Verilator::systemc INTERFACE IMPORTED) set_target_properties( Verilator::systemc PROPERTIES INTERFACE_INCLUDE_DIRECTORIES "${SYSTEMC_INCLUDEDIR}" INTERFACE_LINK_LIBRARIES "${SYSTEMC_LIBRARY}" ) return() endif() find_package(SystemCLanguage QUIET) if(SystemCLanguage_FOUND) add_library(Verilator::systemc INTERFACE IMPORTED) set_target_properties( Verilator::systemc PROPERTIES INTERFACE_LINK_LIBRARIES "SystemC::systemc" ) return() endif() message( "SystemC not found. This can be fixed by doing either of the following steps:" ) message( "- set the SYSTEMC_INCLUDE and SYSTEMC_LIBDIR (environment) variables; or" ) message("- set SYSTEMC_ROOT (environment) variable; or") message("- set SYSTEMC (environment) variable; or") message( "- use the CMake module of your SystemC installation (may require CMAKE_PREFIX_PATH)" ) message(FATAL_ERROR "SystemC not found") endif() endfunction() function(verilator_link_systemc TARGET) _verilator_find_systemc() target_link_libraries("${TARGET}" PUBLIC Verilator::systemc) target_compile_options( ${TARGET} PRIVATE $ENV{SYSTEMC_CXX_FLAGS} ${SYSTEMC_CXX_FLAGS} ) endfunction() function(verilator_generate_key OUTPUT_VARIABLE) execute_process( COMMAND ${VERILATOR_BIN} --generate-key OUTPUT_VARIABLE KEY_VAL RESULT_VARIABLE KEY_RET ) if(KEY_RET) message(FATAL_ERROR "verilator --generate-key failed") endif() string(STRIP ${KEY_VAL} KEY_VAL) set(${OUTPUT_VARIABLE} ${KEY_VAL} PARENT_SCOPE) endfunction() verilator-5.044/.clang-tidy0000644000542200017500000000304115125463617016157 0ustar mahmoudyfreeshellChecks: '*,-hicpp*,-android-cloexec-fopen,-cert-dcl50-cpp,-cert-env33-c,-cert-err34-c,-cert-err58-cpp,-clang-analyzer-core.UndefinedBinaryOperatorResult,-clang-analyzer-security*,-cppcoreguidelines-avoid-magic-numbers,-cppcoreguidelines-no-malloc,-cppcoreguidelines-owning-memory,-cppcoreguidelines-pro-bounds-array-to-pointer-decay,-cppcoreguidelines-pro-bounds-array-to-pointer-decay,-cppcoreguidelines-pro-bounds-constant-array-index,-cppcoreguidelines-pro-bounds-pointer-arithmetic,-cppcoreguidelines-pro-type-const-cast,-cppcoreguidelines-pro-type-reinterpret-cast,-cppcoreguidelines-pro-type-static-cast-downcast,-cppcoreguidelines-pro-type-union-access,-cppcoreguidelines-pro-type-vararg,-cppcoreguidelines-special-member-functions,-fuchsia-*,-google-default-arguments,-google-readability-todo,-google-runtime-references,-llvm-header-guard,-llvm-include-order,-misc-string-integer-assignment,-misc-string-literal-with-embedded-nul,-modernize-use-auto,-modernize-use-trailing-return-type,-readability-braces-around-statements,-readability-container-size-empty,-readability-delete-null-pointer,-readability-else-after-return,-readability-implicit-bool-conversion,-readability-named-parameter,-readability-static-accessed-through-instance,-llvmlibc-*,-altera-*' WarningsAsErrors: '' HeaderFilterRegex: '' FormatStyle: none CheckOptions: - key: google-readability-braces-around-statements.ShortStatementLines value: '2' - key: google-readability-namespace-comments.SpacesBeforeComments value: '2' verilator-5.044/Changes0000644000542200017500000074534715125463617015444 0ustar mahmoudyfreeshell.. for github, vim: syntax=reStructuredText =============================== Revision History and Change Log =============================== The changes in each Verilator version are described below. The contributors that suggested or implemented a given issue are shown in []. Thanks! Verilator 5.044 2026-01-01 ========================== **Important:** * This is the last release supporting the deprecated `--xml-only` and `--make cmake` options. * Change `--lint-only` and `--json-only` to imply `--timing` (#6790). **Other:** * Add `--unroll-limit` option (#6654) (#6668). [Geza Lore, Fractile Ltd.] * Add `-fno-inline-funcs-eager` option to disable excessive inlining (#6682). [Geza Lore, Fractile Ltd.] * Add `-param`/`-port` options to `public_flat*` control directives (#6685). [Geza Lore, Fractile Ltd.] * Add `--top` specifying `config` name (#6710). [Dan Ruelas-Petrisko] * Add `sc_biguint` pragma (#6712). [Jakub Wasilewski, Antmicro Ltd.] * Add `make venv` target (#6775). [Geza Lore] * Add SUPERNFIRST error on super.new on non-first statement (#6784). [Artur Bieniek] * Add fargs for reusability of `--dump-inputs` output (#6812). [Geza Lore] * Add `--quiet-build` to suppress make/compiler informationals. * Support `std::randomize(){...}` (#4706) (#6573). [Yilou Wang] * Support force assignments to unpacked array elements (partial #4735) (#6787). [Ryszard Rozak, Antmicro Ltd.] * Support `config' (#5891) (#6714) (#6717) (#6745) (#6764). [Dan Ruelas-Petrisko] * Support unpacked struct in localparam (#6053 partial) (#6708). [Jonathan Drolet] * Support `randsequence` (#6131). * Support array reference arguments into 'std::randomize()' (#6384) (#6719). [Yilou Wang] * Support basic global constraints (#6551) (#6552). [Yilou Wang] * Support SystemC time resolution with step 10/100 (#6633) (#6715). [Aliaksei Chapyzhenka] * Support `this.randomize()` with constraints (#6634). [Artur Bieniek, Antmicro Ltd.] * Support multi-expression sequences (#6639). [Bartłomiej Chmiel, Antmicro Ltd.] * Support `#1step` delay as statement (#6671). [Pawel Kojma, Antmicro Ltd.] * Support clocking output delay `1step` (#6681). [Ondrej Ille] * Support parsing of dotted `bins_expression` (#6683). [Pawel Kojma, Antmicro Ltd.] * Support constant expression cycle delays in sequences (#6691). [Ryszard Rozak, Antmicro Ltd.] * Support general global constraints (#6709) (#6711). [Yilou Wang] * Support complex std::randomize patterns (#6736) (#6737). [Yilou Wang] * Support `rand_mode` in global constraint gathering (#6740) (#6752). [Yilou Wang] * Support reduction or in constraints (#6840). [Pawel Kojma, Antmicro Ltd.] * Support vpiSigned (#6868) (#6870). [Kaleb Barrett] * Optimize away calls to empty functions (#6626). [Geza Lore] * Optimize redundant headers in Syms implementation files. [Geza Lore, Fractile Ltd.] * Optimize constructor/destructor VerilatedModules (#6660). [Geza Lore, Fractile Ltd.] * Optimize repeated function call during symbol table initialization (#6665). [Geza Lore, Fractile Ltd.] * Optimize functions reading external parameters as pure (#6684). [Geza Lore, Fractile Ltd.] * Optimize `$past` delayed variable reuse (#6689). [Geza Lore, Fractile Ltd.] * Optimize combinational loops through sign extension (#6724). [Geza Lore] * Optimize trace initialization code size (#6749). [Geza Lore] * Optimize combinational cycles in DFG (#6744) (#6746) (#6744). [Geza Lore] * Optimize inlining small C functions and add `-inline-cfuncs` (#6815). [Jose Drowne] * Fix generate function(s) inside of generate blocks (#1011) (#6789). [em2machine] * Fix typedef derived from type defined inside interface (#3441) (#6776). [em2machine] * Fix warning lint directive ordering and consistency (#4185) (#5368) (#5610) (#6876). * Fix extern function that returns parameterized class (#4924). * Fix type deduction for variable parameterized classes (#6281) (#6813). [em2machine] * Fix randomize called within func/task (#6144) (#6753). [Yilou Wang] * Fix pre/post_randomize on extended classes (#6467). [Alex Solomatnikov] * Fix expression short circuiting (#6483). [Todd Strader] * Fix resized lvalues with warning suppressed (#6497) (#6816). [Alex Solomatnikov] * Fix unsupported `if` virtual interface warning (#6558) (#6861). [Krzysztof Bieganski, Antmicro Ltd.] * Fix expression coverage of system calls (#6592). [Todd Strader] * Fix `--timing` with `--x-initial-edge` (#6603) (#6631). [Krzysztof Bieganski, Antmicro Ltd.] * Fix merging of impure assignments in gate optimization (#6629) (#6630). [Geza Lore] * Fix determining Verilator revision when within git submodules without tags. * Fix initial random values for verilator-created variables (#6611). [Todd Strader] * Fix parsing of `with` clause inside covergroups (#6618). [Pawel Kojma, Antmicro Ltd.] * Fix slice memory overflow on large output arrays (#6636) (#6638). [Jens Yuechao Liu] * Fix localparam type assignment from interface type parameters (#6637) (#6732). [em2machine] * Fix memory usage statistics on MacOS (#6644). [Geza Lore, Fractile Ltd.] * Fix command line statistics with --stats (#6645) (#6646). [Geza Lore, Fractile Ltd.] * Fix slow compilation of generated sampled value code (#6652). [Geza Lore, Fractile Ltd.] * Fix non-deterministic output when splitting Syms file. [Geza Lore, Fractile Ltd.] * Fix crash on DFG driver lookup (#6649). [Geza Lore] * Fix ccache-report with PCH files. [Geza Lore, Fractile Ltd.] * Fix parameterized class function (#6659) (#6802). [em2machine] * Fix local interface parameter hierarchical access (#6661) (#6666). [Paul Swirhun] * Fix splitting of Syms constructor/destructor bodies (#6662). [Geza Lore, Fractile Ltd.] * Fix long C++ compilation due to VerilatedScope constructors (#6664). [Geza Lore, Fractile Ltd.] * Fix large array initialization (#6669). [Artur Bieniek, Antmicro Ltd.] * Fix `--expand-limit` not respected for expressions (#6670). [Geza Lore, Fractile Ltd.] * Fix `free` name collision (#6675). [Todd Strader] * Fix bounds checking in non-inlined function (#6677). [Geza Lore, Fractile Ltd.] * Fix stream operator widening (#6693) (#6697). [Jean-Nicolas Strauss] * Fix multitop cross references (#6699). * Fix DFG independent bits analysis performance (#6713) (#6743). [Geza Lore] * Fix deleting linked node error in V3Randomize (#6718). [Igor Zaworski, Antmicro Ltd.] * Fix runtime worker thread stack sizes on MacOS (#6721). [Geza Lore] * Fix X handling in UDPs (#6722) (#6723). [Michael Bikovitsky] * Fix `--prof-exec` using `--lib-create`. [Geza Lore] * Fix fork scheduling semantics (#6730). [Artur Bieniek, Antmicro Ltd.] * Fix JSON output case statements (#6733). * Fix internal fault when cross-class calling with DPI (#6735) (#6742). [Matthew Ballance] * Fix write variable placement for global constraints (#6740) (#6750) (#6797). [Yilou Wang] * Fix JSON dump missing output ports (#6751) (#6831). [Oleh Maksymenko] * Fix resolution of specialized typedefs (#6754) (#6808) (#6834). [em2machine] * Fix UNSUPPORTED on force / release with complex selects (#6755). [Ryszard Rozak, Antmicro Ltd.] * Fix select assignment expansion (#6757). [Geza Lore] * Fix `--lib-create` with multi-bit clocks (#6759). [Geza Lore] * Fix DFG reusing volatile variables. [Geza Lore] * Fix DFG assertion on out-of-bounds selects. [Geza Lore] * Fix process reference giving no return statement error (#6767) (#6823). [Krzysztof Bieganski, Antmicro Ltd.] * Fix class param static not found again error (#6768). * Fix crash when super.new() called without a base class (#6772). [Matthew Ballance] * Fix class-in-class extends with parameters (#6773). * Fix enum item references in class extends with parameters. * Fix reordering of function body inlined on RHS of <= NBA (#6780). [Geza Lore] * Fix clang `-Wno-vla-cxx-extension` warning for UVM DPI tests (#6782) * Fix `disable iff` in simple properties (#6783). [Ryszard Rozak, Antmicro Ltd.] * Fix input sampling of clocking block signals (#6788). [Pawel Kojma, Antmicro Ltd.] * Fix O(n*2) analysis in const-bit-op-tree (#6791). [Geza Lore] * Fix member select of variable without randmode (#6800) (#6833). [Yilou Wang] * Fix duplicate name error with interface initial blocks (#6804) (#6805). [Thomas Dybdahl Ahle] * Fix nested struct within parameter port list (#6818) (#6824). [Luca Colagrande] * Fix setting thread count in VerilatedContext (#6826 partial) (#6841). [Yangyu Chen] * Fix firing array selects of events (#6829). [Amal Araweelo Almis] * Fix false IMPLICITSTATIC on localparam (#6835). [Geza Lore] * Fix randcase under fork (#6843). [Amal Araweelo Almis] * Fix JSON missing `signed` indication (#6845). * Fix class reference throwing cannot detect changes error (#6851). * Fix `randc` on extended class (#6852). * Fix typedef `::` class reference error (#6862). * Fix missing include on FreeBSD (#6864). * Fix `--Wwarn-lint` to be inverse of `--Wno-lint`. Verilator 5.042 2025-11-02 ========================== **Other:** * Add HIERPARAM error on hierarchical parameter values (#1626) (#6456) (#6484) (#6587) (#6609) (#6621) (#6623). [Todd Strader] [Luca Rufer] [Paul Swirhun] * Add error on zero/negative unpacked dimensions (#1642). [Stefan Wallentowitz] * Add verilator_gantt profiling of DPI imports (#3084). [Geza Lore] * Add ASSIGNEQEXPR when use `=` inside expressions (#5567). [Ethan Sifferman] * Add error on non-packed struct randc (#5999). [Seth Pellegrino] * Add configure `--enable-dev-asan` to compile verilator_bin with the address sanitizer (#6404). [Geza Lore] * Add $(LDFLAGS) and $(LIBS) to when building shared libraries (#6425) (#6426). [Ahmed El-Mahmoudy] * Add IMPLICITSTATIC also on procedure variables. * Add FUNCTIMCTL error on function invoking task or time-controlling statements (#6385). * Add error on `virtual new` (#6486). [Alex Solomatnikov] * Add error on ranges with tristate values (#6534). [Alex Solomatnikov] * Add NORETURN warning on functions without return values (#6534). [Alex Solomatnikov] * Add `--aslr` and `--no-aslr` options. * Add `$cpure` (#6580). [Igor Zaworski, Antmicro Ltd.] * Add `--preproc-defines`. * Deprecate sensitivity list on public_flat_rw attributes (#6443). [Geza Lore] * Deprecate clocker attribute and --clk option (#6463). [Geza Lore] * Deprecate '--make cmake' option (#6540). [Geza Lore] * Change default `--expand-limit` to 256 (#3419). * Change developer coverage flow and add configure `--enable-dev-gcov` (#6526). [Geza Lore] * Change `verilator_difftree` to return exit code 1 on mismatch, 2 on error. * Change default thread pool sizes to respect processor affinity (#6604). [Geza Lore] * Change `--preproc-comments` to be new name of `--pp-comments` option. * Support modports referencing clocking blocks (#4555) (#6436). [Ryszard Rozak, Antmicro Ltd.] * Support class package reference on pattern keys (#5653). [Todd Strader] * Support digits in `$sscanf` field width formats (#6083). [Iztok Jeras] * Support assert under assert (#6146). [Alex Solomatnikov] * Support pure functions in sensitivity lists (#6393). [Krzysztof Bieganski, Antmicro Ltd.] * Support simple alias statements (#6339) (#6501). [Ryszard Rozak, Antmicro Ltd.] * Support simple cycle delay sequence expressions inside properties (#6508). [Bartłomiej Chmiel, Antmicro Ltd.] * Support impure expressions in `inside` (#6562). [Igor Zaworski, Antmicro Ltd.] * Support `case` impure expressions (#6563). [Igor Zaworski, Antmicro Ltd.] * Support dotted access to ports of a direct hier_block instance. (#6595). [Geza Lore] * Improve `lint_off` to allow multiple messages and comments (#2755). * Improve automatic selection of logic for DFG synthesis (#6370). [Geza Lore] * Improve `covergroup with function sample` handling (#6387). [Jakub Wasilewski] * Improve DFG type system (#6390). [Geza Lore] * Improve DFG variable removal and temporary insertion (#6401). [Geza Lore] * Improve memory usage of statistics (#6513). [Geza Lore] * Improve conditional merging to preserve branch prediction. [Geza Lore] * Optimize duplicate 'if' and '?:' conditions (#3807) (#6495) * Optimize dead functions in more cases (#6380) (#6430). [Artur Bieniek, Antmicro Ltd.] * Optimize constant folding in wide expression expansion (#6381). [Geza Lore] * Fix `--trace-max-width` and increase to 4096. (#2385). * Fix missing BLKSEQ when connecting module port to array (#2973). * Fix LATCH warning with CASEINCOMPLETE (#3301). * Fix unused parameterized class causing internal error (#4013). [Alberto Del Rio] * Fix false CONSTVAR error on initializers (#4992). * Fix hierarchical references with parameterized modules and interfaces (#5649) (#6566). [Ryszard Rozak, Antmicro Ltd.] * Fix interface exposure with `--public-depth` or `--trace-depth` (#5758). * Fix cell scoping performance (#6059). [Jerry Tianchen] * Fix hierarchical `--prof-pgo` (#6213). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix while loop hang on timing-delayed assignment (#6343) (#6354). [Krzysztof Bieganski, Antmicro Ltd.] * Fix driver analysis of partially assigned variables (#6364) (#6378). [Geza Lore] * Fix V3Hash MacOS ambiguity (#6350). [Lan Zongwei] * Fix cmake APPLE variable (#6351). [Lan Zongwei] * Fix randomize local after parameters applied (#6371). [Alex Solomatnikov] * Fix package imports not found after parameters applied (#6373). [Alex Solomatnikov] * Fix deep shift pattern performance (#6379) (#6420). [Geza Lore] * Fix COVERAGEIGN-ignored `get_inst_coverage` and other covergroup methods (#6383). [Alex Solomatnikov] * Fix error when modport variable is unresolved (#6386). [Ryszard Rozak, Antmicro Ltd.] * Fix resolving parameters (#6388) (#6418) (#6421) (#6438) (#6429). [Artur Bieniek, Antmicro Ltd.] * Fix wire array with initial assignment (#6391). [Alex Solomatnikov] * Fix import of class with default params (#6396) (#6410) (#6413). [Krzysztof Bieganski, Antmicro Ltd.] * Fix use after free in elaboration (#6403). [Geza Lore] * Fix address sanitizer issues (#6406). [Geza Lore] * Fix timing control under fork under function (#6407). [Krzysztof Bieganski, Antmicro Ltd.] * Fix memory leaks and reduce requirements (#6411) (#6417) (#6419) (#6437) (#6439) (#6517). [Geza Lore] * Fix parameter implicit type from string (#6414). [Alex Solomatnikov] * Fix parsing for sequence expressions (#6427). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix parameterized class super functions (#6431) (#6438). [Artur Bieniek, Antmicro Ltd.] * Fix external function declarations with class typedef references (#6433). * Fix internal error on out-of-bounds real array access. * Fix pre/post increments in assertions (#6434). * Fix elaboration displays with `%m` and some `%p` (#6445) (#6451). [Alex Solomatnikov] * Fix cast in gdbinit.py (#6447). [Artur Bieniek, Antmicro Ltd.] * Fix false unique assertions on `else ;` (#6450). [Don Owen] * Fix loss of clock attribute in DFG variable removal (#6453). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix data types of method calls without parenthesis (#6457). [Artur Bieniek, Antmicro Ltd.] * Fix segfault on unsupported PLI calls (#6458). [Krzysztof Bieganski, Antmicro Ltd.] * Fix false assertion failure on failed DFG driver tracing (#6459). [Geza Lore] * Fix side effects when using select (#6460). [Igor Zaworski, Antmicro Ltd.] * Fix timeprecision backward assignment (#6469). [Artur Bieniek, Antmicro Ltd.] * Fix splitting hierarchically referenced variables (#6475). [Ryszard Rozak, Antmicro Ltd.] * Fix Windows compilation of Verilator with spaces in the path (#6477). [Fabian Keßler-Schulz] * Fix PROTOTYPEMIS error on implicit logic (#6482). [Alex Solomatnikov] * Fix configure misdetecting C++14 (#6488) (#6515). [Thomas O'Keeffe] * Fix false BLKSEQ on non-edged sensitivity list (#6492). [Oron Port] * Fix .vlt public_flat* and others to support long identifier names (#6516). [Szymon Gizler, Antmicro Ltd.] * Fix always_ff on constants (#6519). [Todd Strader] * Fix fault on operations on uninitialized strings (#6520). [Artur Bieniek, Antmicro Ltd.] * Fix find_index methods of associative arrays (#6525). [Ryszard Rozak, Antmicro Ltd.] * Fix parsing of `eventually[]` and property expression memory leaks (#6530). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix memory leak for unsupported `$past` (#6535). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix inconsistent force assignment (#6541). [Artur Bieniek, Antmicro Ltd.] * Fix DFG circular driver tracing with partial assignments. [Geza Lore] * Fix passing typedef value as parameter (#6543) (#6547). [Igor Zaworski, Antmicro Ltd.] * Fix indent error on quoted strings (#6544). * Fix incorrect nested interface-class error (#6549). [Matthew Ballance] * Fix std::process::get_randstate to not affect random stability (#6550) (#6565). [Aleksander Kiryk] * Fix exit code signal number reporting (#6554). [Artur Bieniek, Antmicro Ltd.] * Fix `$finish` inside fork blocks (#6555). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix single element unpacked array DPI parameters. [Geza Lore] * Fix DFG synthesis non-determinism (#6557) (#6568). [Todd Strader] * Fix side effects for improved function/task/process purity (#6559). [Igor Zaworski, Antmicro Ltd.] * Fix excessive logic replication in DFG circular driver tracing (#6561) (#6594). [Geza Lore] * Fix hierarchical with parameterized instances under hier block (#6572). [Geza Lore] * Fix segfault on type casts (#6574). [David Moberg] * Fix references to interfaces containing generate blocks (#6579). [Ryszard Rozak, Antmicro Ltd.] * Fix missing net type mappings in FST traces (#6582) (#6583). [Matt Stroud] * Fix function call expression coverage (#6589). [Todd Strader] * Fix V3Life eliminating assignments across timing controls (#6593) (#6596). [Geza Lore] * Fix incorrectly resuming process waiting on multiple events (#6597). [Geza Lore] * Fix `--hierarchical` with `--binary` (#6602). [Geza Lore] * Fix mis-ignoring virtual interface member triggers (#5116 reopened) (#6613). [Geza Lore] * Fix ENUMVALUE warning when overriding parameter using `-G/-pvalue` options. [Geza Lore] * Fix `-G` and `-pvalue` with `--hierarchical`. [Geza Lore] * Fix waiving messages with empty contents (#6610). [Yoshitomo KANEDA] * Fix constant-arrayed instance parameters (#6614). [Alex Solomatnikov] Verilator 5.040 2025-08-30 ========================== **Other:** * Add ENUMITEMWIDTH error, and apply to X-extended and ranged values. * Add NOEFFECT warning, replacing previous `foreach` error. * Add SPECIFYIGN warning for specify constructs that were previously silently ignored. * Add PARAMNODEFAULT error, for parameters without defaults. * Add enum base data type, wire data type, and I/O versus data declaration checking per IEEE. * Add PROTOTYPEMIS error on missing and mismatching prototypes (#6206) (#6207). [Alex Solomatnikov] * Add error when trying to assign class object to variable of non-class types (#6237). [Igor Zaworski, Antmicro Ltd.] * Add ALWNEVER warning, for `always @*` that never execute (#6291). * Add separate coverage counters for toggles 0->1 and 1->0 (#6086). [Ryszard Rozak, Antmicro Ltd.] * Add error on class 'function static'. * Add error on force/release non-constant selects. * Add `-DVERILATOR=1` definition to compiler flags when using verilated.mk. * Support member-level triggers for virtual interfaces (#5166) (#6148). [Yilou Wang] * Support unassigned virtual interfaces (#5265) (#6245). [Szymon Gizler, Antmicro Ltd.] * Support randomization of scope variables with 'std::randomize()' (#5438) (#6185). [Yilou Wang] * Support disabling a fork in additional contexts (#5432 partial) (#6174) (#6183). [Ryszard Rozak, Antmicro Ltd.] * Support bit queue streaming (#5830) (#6103). [Paul Swirhun] * Support `$fread` with missing start (#6125). [Iztok Jeras] * Support unpacked array `with` methods (#6134). * Support Verilog real ports as SystemC double ports (#6136) (#6158). [George Polack] * Support `$countones` in constraints (#6144 partial) (#6235). [Ryszard Rozak, Antmicro Ltd.] * Support disable dotted references (#6154). [Ryszard Rozak, Antmicro Ltd.] * Support randomize() on class member selects (#6161) (#6195). [Igor Zaworski, Ryszard Rozak, Antmicro Ltd.] * Support multiple variables on RHS of a `force` assignment (#6163). [Artur Bieniek, Antmicro Ltd.] * Support covergroup extends, etc., as unsupported (#6160). [Artur Bieniek, Antmicro Ltd.] * Support parameter resolution of 1D unpacked array slices (#6257) (#6268). [Michael Bedford Taylor] * Support generic interfaces (#6272). [Igor Zaworski, Antmicro Ltd.] * Support disabling a fork from within that fork (#6314). [Ryszard Rozak, Antmicro Ltd.] * Support future sampled value functions. * Support simple disable within task (#6334). [Ryszard Rozak, Antmicro Ltd.] * Support recursive constant functions. * Change control file `public_flat_*` and other signal attributes to support __ in names (#6140). * Change runtime to exit() instead of abort(), unless under +verilated+debug. * Change `$display("%p")` to remove space after `}`. * Improve `--skip-identical` to skip on identical input file contents (#6109). * Improve testing on FreeBSD (#6328). [Aleksander Kiryk] * Optimize to return memory when using -build (#6192) (#6226). [Michael B. Taylor] * Optimize 2 ** X to 1 << X if base is signed (#6203). [Max Wipfli] * Optimize more complex combinational logic in DFG (#6205) (#6209) (#6298). [Geza Lore] * Optimize combinational cycles through arrays in DFG (#6210). [Geza Lore] * Optimize variable removal in scoped DFG (#6260). [Geza Lore] * Optimize acyclic DFG components into the original acyclic sub-graph. (#6261). [Geza Lore] * Optimize multiplexers in DFG synthesis (#6331). [Geza Lore] * Optimize interfaces in DFG (#6332). [Geza Lore] * Optimize logic in non-virtual interfaces with DFG (#6347). [Geza Lore] * Fix loop initialization visibility outside loop (#4237). * Fix constructor parameters in inheritance hierarchies (#6036) (#6070). [Petr Nohavica] * Fix replicate of negative giving 'REPLICATE has no expected width' internal error (#6048) (#6229). * Fix cmake `-Wno` compiler flag testing (#6145). [Martin Stadler] * Fix class extends dotted error (#6162). [Igor Zaworski, Antmicro Ltd.] * Fix genvar error with `-O0` (#6165). [Max Wipfli] * Fix uninitialized thread PGO counters (#6167). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix additional UNOPTFLAT combinational cycles automatically in DFG (#6168) (#6173) (#6176). [Geza Lore] * Fix omitting error when assigning to an input (#6169). [Artur Bieniek, Antmicro Ltd.] * Fix parameter-dependent type linking (#6170). [Igor Zaworski, Antmicro Ltd.] * Fix param-dependent class typedef linking (#6171). [Igor Zaworski, Antmicro Ltd.] * Fix virtual interface member propagation (#6175) (#6184). [Yilou Wang] * Fix `--coverage-expr` null pointer dereference (#6181). [Igor Zaworski, Antmicro Ltd.] * Fix conflicting function/class name linking error (#6182). [Igor Zaworski, Antmicro Ltd.] * Fix negate of wide structure selections (#6186). * Fix VPI signal range order (#6189) (#6200). [Ibrahim Burak Yorulmaz] * Fix structure select causing 'Wide Op' error (#6191). [Danny Oler] * Fix automatic task variables in unrolled loops with forks (#6194) (#6201). [Danny Oler] * Fix 'driver same component' assertion (#6211) (#6215). [Geza Lore] * Fix `--stats` overridden by skipping identical build (#6220). [Geza Lore] * Fix MODDUP with duplicate packages to take first package (#6222). * Fix replicate with unsigned count but MSB set (#6231) (#6233). [Geza Lore] * Fix randomize on function-local variable (#6234). * Fix queue typedef with unbounded slice (#6236). * Fix error when force assignment is used with ref function args (#6244). [Ryszard Rozak, Antmicro Ltd.] * Fix write of 0 in '%c' (#6248) (#6249). [Rodrigo Batista de Moraes] * Fix coverage of variables of complex types (#6250). [Ryszard Rozak, Antmicro Ltd.] * Fix broken support of unassigned virtual interfaces (#6253) (#6338). [Szymon Gizler, Antmicro Ltd.] * Fix partial DFG conversion of concat assignments (#6255). [Geza Lore] * Fix dynamic cast purity (#6267). [Igor Zaworski, Antmicro Ltd.] * Fix same variable on the RHS forced to two different LHSs. (#6269). [Artur Bieniek, Antmicro Ltd.] * Fix spurious VPI value change callbacks (#6274). [Todd Strader] * Fix stray ']' in Verilog code output for non-constant select (#6277). [Geza Lore] * Fix hierarchical NBAs (#6286) (#6300). [Geza Lore] * Fix variables hiding package imports (#6289). [Johan Wouters] * Fix DFG circular driver tracing. [Geza Lore] * Fix no matching function calls for randomized `VlWide` in unpacked and dynamic arrays (#6290). [Mateusz Gancarz, Antmicro Ltd.] * Fix PowerPC support (#6292). [Sergey Fedorov] * Fix referencing module variables above classes (#6304). [Artur Bieniek, Antmicro Ltd.] * Fix direct NBA to dynamically-sized variable (#6310). [Artur Bieniek, Antmicro Ltd.] * Fix static vars under member select (#6313). [Igor Zaworski, Antmicro Ltd.] * Fix expression type comparison (#6316). [Igor Zaworski, Antmicro Ltd.] * Fix of inline constraints with member selects (#6321). [Igor Zaworski, Antmicro Ltd.] * Fix corner case bugs in module and variable inlining (#6322). [Geza Lore] * Fix queue extend to check bounds (#6324). [Aleksander Kiryk] * Fix gathering sensitivities from virtual interface members (#6325). [Aleksander Kiryk] * Fix FreeBSD missing headers (#6326). [Aleksander Kiryk] * Fix to select UDPs when they are the only candidate for a top module. * Fix splitting of assignments to SC variables (#6329) (#6336). [Geza Lore] * Fix to localize for super constructors with function calls as arguments (#6330). [Igor Zaworski, Antmicro Ltd.] * Fix wide select expansion and substitution (#6341) (#6345). [Geza Lore] * Fix upcasting class type parameters (#6344). [Krzysztof Bieganski, Antmicro Ltd.] * Fix undefined weak link for Apple GCC etc (#6348). [Congcong Cai] Verilator 5.038 2025-07-08 ========================== **Important:** * Change `--assert` to be the default; use `--no-assert` for legacy behavior and faster runtimes. **Other:** * Support redeclaring type as non-type; major parsing change (#2412) (#6020) (#6042) (#6044). * Support scoped `new` (#4199). * Support elaboration-time printing of unpacked array with `%p` (#4732). * Support constrained random for associative arrays (#5985) (#5986). [Yilou Wang] * Support assignments to concatenations with impure RHS (#6002). [Ryszard Rozak, Antmicro Ltd.] * Support SARIF JSON diagnostic output with `--diagnostics-sarif`. (#6017) * Support 1-bit params with -G and -pvalue (#6051) (#6082). [Paul Swirhun] * Support `specparam` (#5767) (#6142). * Support `$timeformat` with missing arguments (#6113). [Alex Solomatnikov] * Support non-overlapping blocking/non-blocking assignments (#6137). [Geza Lore] * Support parameter forward types. * Support constant functions with left-hand-side concatenates. * Add PROCINITASSIGN on initial assignments to process variables (#2481). [Niraj Menon] * Add BADVLTPRAGMA on unknown Verilator pragmas (#5945). [Shou-Li Hsu] * Add ternary operator into branch coverage (#5880). [Ryszard Rozak, Antmicro Ltd.] * Add aggregate type error checks (#5570) (#5950). [Shou-Li Hsu] * Add `--work` library-selection option (#5891 partial). * Add `--filter-type` to verilator_coverage (#6030). [Ryszard Rozak, Antmicro Ltd.] * Add `--hierarchical-threads` (#6037). [Bartłomiej Chmiel] * Add `MODMISSING` error, in place of unnamed error (#6054). [Paul Swirhun] * Add DFG binToOneHot pass to generate one-hot decoders (#6096). [Geza Lore] * Add hint of the signed right-hand-side in oversized replication error (#6098). [Peter Birch] * Improve hierarchical scheduling visualization in V3ExecGraph (#6009). [Bartłomiej Chmiel, Antmicro Ltd.] * Improve DPI temporary 'for' loop performance (#6079). [Bartłomiej Chmiel, Antmicro Ltd.] * Improve memory usage for SenTrees in V3OrderProcessDomains (#6112). [Geza Lore] * Improve docker image size (#6139). [Tobias Rosenkranz, bitaggregat GmbH] * Update docker base image to Ubuntu 24.04 (#6147). [Tobias Rosenkranz, bitaggregat GmbH] * Optimize DFG De Morgan patterns (#6090). [Geza Lore] * Optimize DFG variable elimination (#6091). [Geza Lore] * Optimize DFG PUSH_SEL_THROUGH_CONCAT pattern (#6092). [Geza Lore] * Optimize DFG before V3Gate (#6141). [Geza Lore] * Optimize DFG peephole patterns (#6149). [Geza Lore] * Optimize constification within Expand and Subst stages (#6111). [Geza Lore] * Fix --x-initial and --x-assign random stability (#2662) (#5958) (#6018) (#6025) (#6075). [Todd Strader] * Fix trace hierarchical-name runtime errors (#5668) (#6076). [Paul Swirhun] * Fix streaming operator packing order (#5903) (#6077). [Paul Swirhun] * Fix filename backslash escapes in C code (#5947). * Fix C++ widths in V3Expand (#5953) (#5975). [Geza Lore] * Fix dependencies from different hierarchical schedules (#5954). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix constant propagation of post-expand stages (#5955) (#5963) (#5969) (#5972) (#5983). * Fix sign extension of signed compared with unsigned case items (#5968). * Fix always processes ignoring $finish (#5971). [Hennadii Chernyshchyk] * Fix method calls and new to access interface arrays (#5973). [Nick Brereton] * Fix streaming to/from packed arrays (#5976). [Geza Lore] * Fix segfault writing timestamp to VCD after buffer flush (#5978) (#5980). [Dominick Grochowina] * Fix inconsistent assignment error with split-var (#5984) (#5988). [Yutetsu TAKATSUKASA] * Fix AstAssignW conversion (#5991) (#5992). [Ryszard Rozak, Antmicro Ltd.] * Fix const-bit-op-tree with single-bit masks (#5993) (#5998). [Yutetsu TAKATSUKASA] * Fix arithmetic right-shift by constants over 32 bits (#5994). [Zhen Yan] * Fix array bounds checking with class member selects (#5996) (#5997). [Krzysztof Starecki] * Fix checking for too-wide divide and modulus (#6003) (#6006). [Zhen Yan] * Fix folding of LteS in DfgPeephole (#6000) (#6004). [Geza Lore] * Fix slicing of AstExprStmt nodes (#6005). [Ryszard Rozak, Antmicro Ltd.] * Fix skipped generate blocks in toggle coverage (#6010). [Ryszard Rozak, Antmicro Ltd.] * Fix arithmetic left-shift by constants over 32 bits (#6007) (#6015). [Zhen Yan] * Fix concatenation and type casting (#6012) (#6013). [Todd Strader] * Fix wrong optimization result of shifted out variable (#6016) (#6019). [Yutetsu TAKATSUKASA] * Fix missing FreeBSD include (#6027) (#6028). [Joel Bodenmann] * Fix associative arrays with enum keys (#6034) (#6035). [Petr Nohavica] * Fix GCC 10 read-only linker error (#6040). [Todd Strader] * Fix WIDTHCONCAT on packed pattern assignment (#6045). [Dan Petrisko] * Fix type operator for interface signals (#6049) (#6050). [Todd Strader] * Fix V3OrderParallel scoring contraction hang (#6052). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix virtual interface array typedef expressions (#6057). * Fix DFG peephole select conditionals (#6064) (#6071). [Geza Lore] * Fix `--skip-identical` skipping on some errors (#6066). [Todd Strader] * Fix class typedef elaboration (#6080). [Kamil Rakoczy, Antmicro Ltd.] * Fix unpacked to packed parameter assignment (#6081) (#6088). [Todd Strader] * Fix casting reals to large integrals (#6085). [Todd Strader] * Fix nested hier blocks workers error (#6087). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix `--lib-create` with double-underscore (#6099). * Fix DFG binToOneHot table index missing driver (#6100). [Geza Lore] * Fix decoding octal string escapes with 1-2 digits (#6108). * Fix colon-divide operator without space (#6121). [Alex Solomatnikov] * Fix variables declared in fork after taskify (#6126). [Kamil Rakoczy, Antmicro Ltd.] * Fix method calls without parenthesis (#6127). [Alex Solomatnikov] * Fix `pre_randomize`/`post_randomize` when no randomize (#6128). [Alex Solomatnikov] * Fix wide non-blocking assignment mis-optimization (#6150) (#6152) (#6155). [Todd Strader] * Fix interface array connections with non-zero low declaration index. * Fix developer build error on MacOS/Flex2.6.4 (#6153). [Paul Swirhun] * Fix crash with --dumpi-V3LinkDot without --debug (#6159). [Igor Zaworski, Antmicro Ltd.] * Fix dereferencing stale iterator in DfgVertex::scopep() (#6225) (#6227). [Geza Lore] * Fix component numbers of new Vertices in V3DfgBreakCycles (#6225) (#6228). [Geza Lore] Verilator 5.036 2025-04-27 ========================== **Important:** * Change `--output-groups` to default to value of `--build-jobs` (#5751). Those using build farms may need to now use `--output-groups 0` or otherwise. * Support user-defined primitives (UDPs) (#468) (#5807) (#5936). [Zhou Shen, Krzysztof Sychla, et al] * Add `--trace-saif` for SAIF power traces (#5812) (#5914). [Mateusz Gancarz, Antmicro Ltd.] **Other:** * Change `--trace` to `--trace-vcd`. * Support simple `checker` blocks (#4066). [Srinivasan Venkataramanan] * Support force/release with a variable reference (#5721) (#5810). [Bartłomiej Chmiel, Antmicro Ltd.] * Support constraint random for StructArray (#5805) (#5937). [Yilou Wang] * Support command-line overriding `define (#5900) (#5908). [Brian Li] * Support soft unions (#5912) (#5932). [Robin Heinemann] * Support `$setuphold` (#5884). [Krzysztof Sychla] * Support assigning unpacked arrays to queues (#5924) (#5928). [Brian Li] * Support `systemc_interface and related inside `class`. * Support class extends with arguments. * Add multi-thread hierarchical simulation (#2583) (#5871). [Bartłomiej Chmiel, Antmicro Ltd.] * Add check for `let` misused in statement context (#5733). * Add used language to `--preproc-resolve` output (#5795). [Kamil Rakoczy, Antmicro Ltd.] * Add `--make json` to enable integration with non-make/cmake build systems (#5799). [Andrew Voznytsa] * Add numactl-like automatic assignment of processor affinity (#5911). * Add ccache support for generated cmake files (#5926) (#5930). [Andrew Voznytsa] * Add visualization of multi-threaded waiting time with verilator_gantt (#5929). [Bartłomiej Chmiel, Antmicro Ltd.] * Add suggesting isolate_assignments to UNOPTFLAT (#5942). [John Khoo] * Add profiling of hierarchical mtasks with verilator_gantt (#5956). [Bartłomiej Chmiel, Antmicro Ltd.] * Add empty veriuser.h for legacy compatibility. * Add DEPRECATED warning on `--xml-only` and `--xml-output`. * Remove unused gtkwave/wavealloca.h. [Geza Lore] * Optimize automatic splitting of some packed variables (#5843). [Geza Lore] * Optimize trigger vector in whole words (#5857). [Geza Lore] * Fix parameters referencing interface fields (#1593) (#5910). [Ryszard Rozak, Antmicro Ltd.] * Fix interface array assignments (#5270) (#5633) (#5869). [Nick Brereton] * Fix change detection at time 0 (#5499) (#5864). [Geza Lore] * Fix foreach of associative array inside a constraint block (#5727) (#5841). [Yilou Wang] * Fix reset of automatic function variables (#5747). [Augustin Fabre] * Fix invalid code motion over branches (#5811) (#5814). [Geza Lore] * Fix sorting of wide SenItems (#5816). [Geza Lore] * Fix tcmalloc static link and non-22.04 builds (#5817) (#5818). [Geza Lore] * Fix error on out-of-range lvalue part select (#5820). * Fix UNOPTFLAT warnings with `--coverage-trace` and always_comb (#5821). * Fix function locals in SenExprBuilder (#5822). [Geza Lore] * Fix type_id package scope resolution (#5826). [Krzysztof Bieganski, Antmicro Ltd.] * Fix `rand_mode` method with cast (#5831). * Fix invalidating variable caches in SenExprBulider (#5834) (#5835). [Geza Lore] * Fix assignment pattern as function argument (#5839). * Fix checking built-in method arguments (#5839). * Fix splitting of packed ports with non-zero based ranges (#5842). [Geza Lore] * Fix delays inside interface functions, and classes inside interfaces (#5846). * Fix NBA shared flag reuse (#5848). [Geza Lore] * Fix multiple expression coverage issues (#5849 partial) (#5867) (#5870). [Todd Strader] * Fix unresolved typedefs as parameters (#5850). [Eugene Feinberg, Brian Li] * Fix removal of callbacks no longer in current list (#5851) (#5852). [Gilberto Abram] * Fix segmentation fault on member compare (#5853). * Fix recursive error on virtual interfaces (#5854). [Yilou Wang] * Fix streaming of unpacked arrays concatenations (#5856). [Ryszard Rozak, Antmicro Ltd.] * Fix Windows paths in Perl (#5858) (#5860). [Tobias Jensen] * Fix algorithm header portability in V3Os.cpp (for std::replace) (#5861). [William D. Jones] * Fix `$fscanf` not returning -1 on EOF (#5881). * Fix PGO profiling for multi-threaded hierarchical scenarios (#5888). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix V3Gate assertion on eliminated circular logic (#5889) (#5898). [Geza Lore] * Fix process comparisons (#5896). * Fix ccache with clang (#5899). [Geza Lore] * Fix delayed assignment malformed LHS assertion (#5904). * Fix segfault in fork synchronization (#5906). [Krzysztof Bieganski, Antmicro Ltd.] * Fix `new this` (#5909). * Fix assignments with stream expressions and unpacked arrays (#5915). [Ryszard Rozak, Antmicro Ltd.] * Fix LATCH warning for automatic variables (#5918). [Yutetsu TAKATSUKASA] * Fix %% on elaboration severity tasks (#5922). [Ethan Sifferman] * Fix port default values with `--coverage-line` creating `0=0` (#5920). [Drew Ranck] * Fix vlSelf error on fork repeats (#5927). [Drew Ranck] * Fix missing C++ regeneration when Verilog files are updated (#5934). [Zhouyi Shen] * Fix stream expressions (#5938). [Ryszard Rozak, Antmicro Ltd.] * Fix packed selection using over 32-bit index (#5957). Verilator 5.034 2025-02-24 ========================== **Important:** * This is likely the last version to support Ubuntu 20.04, which is at end-of-life. * Add expression coverage (#4677) (#5719). [Todd Strader] **Other:** * Add `COVERIGN` warning, as a more specific UNSUPPORTED error. * Add `--public-ignore` to ignore public metacomments (#5716). [Andrew Nolte] * Add `--preproc-token-limit` (#5768). [Krzysztof Bieganski, Antmicro Ltd.] * Add lint error on importing package within a class (#5634) (#5679). [Nick Brereton] * Add `--preproc-resolve` for modules in preprocessor output (#5789). [Kamil Rakoczy, Antmicro Ltd.] * Support multidimensional array access via VPI (#2812) (#5573). [Krzysztof Starecki] * Support nested classes (#4178) (#5778). [Kamil Rakoczy, Antmicro Ltd.] * Support VPI array accessors (#5612). [Moubarak Jeje] * Support unpacked structure constrained randomization (#5657) (#5759). [Yilou Wang] * Support generated classes (#5665). [Shou-Li Hsu] * Support constraints on associative array user-defined keys (#5671) (#5729). [Yilou Wang] * Support `+incdir` with multiple directories. * Support integer atom type ports in `--hierarchical` (#5748). [Bartłomiej Chmiel, Antmicro Ltd.] * Support constrained random for arrays in structs (#5765) (#5802). [Yilou Wang] * Support selects on arbitrary string expressions (#5773). [Krzysztof Bieganski, Antmicro Ltd.] * Support side effects of form 'variable[index_function()]++'. * Improve hierarchical DPI wrapper scheduling performance (#2583) (#5734). [Bartłomiej Chmiel, Antmicro Ltd.] * Improve VPI write errors (#5712). [Andrew Nolte] * Improve `resetall support (#5728) (#5730). [Ethan Sifferman] * Optimize labels as final `if` block statements (#5744). * Optimize empty function definition bodies (#5750). * Optimize splitting trigger computation and dump (#5798). [Geza Lore] * Optimize some DFG multiplexers (#6822). [Yangyu Chen] * Fix error message when call task as a function (#3089). [Matthew Ballance] * Fix force VPI public signal visibility (#5225). [Frédéric Requin] * Fix VPI iteration over hierarchy (#5314) (#5731). [Natan Kreimer] * Fix constrained random for > 64-bit associative arrays (#5670) (#5682). [Yilou Wang] * Fix mis-optimizing away `$urandom` (#5703). [Parker Schless] * Fix packages with `--public-depth 1` (#5708). [Andrew Nolte] * Fix V3Simulate constant reuse (#5709). [Geza Lore] * Fix man pages what-is section (#5710). [Ahmed El-Mahmoudy] * Fix pattern assignment to real inside struct (#5713). * Fix %p format output for real inside struct (#5713). * Fix segfault when only enum value referenced in package (#5714). [Dan Katz] * Fix `BLKSEQ` on suspendable processes (#5722). [Krzysztof Bieganski, Antmicro Ltd.] * Fix vpiDefName issues with non-inlined scopes and dpi conflicts (#5732). [Andrew Nolte] * Fix inlined expression with assignment under LHS of NBA (#5736) (#5740). [Geza Lore] * Fix duplicate-named class variable equivalence (#5737). * Fix `-j` ignored after `-f` (#5749). [Luca Colagrande] * Fix handling forced assigns in V3Life (#5757). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix VFileContent reference count (#5769) (#5771). [Dave Sargeant] * Fix ignoring joins in stringify in preprocessor (#5777). [Krzysztof Bieganski, Antmicro Ltd.] * Fix unpacked split_var (#5782) (#5785). [Yutetsu TAKATSUKASA] * Fix time import error on time parameters (#5786). [Luca Colagrande] * Fix dpi context functions (#5788). [Ryszard Rozak, Antmicro Ltd.] * Fix `$monitor` with dotted references (#5794). [Ahmed Elzeftawi] * Fix parsing input wire with default and range (#5800). [RJ Cunningham] * Fix matching language extension options including dots. Verilator 5.032 2025-01-01 ========================== **Minor:** * Support queue's assignment `push_back/push_front('{})` (#5585) (#5586). [Yilou Wang] * Support basic constrained random for multi-dimensional dynamic array and queue (#5591). [Yilou Wang] * Support vpiDefName (#3906) (#5572). [Krzysztof Starecki] * Support parameter names in pattern initialization (#5593) (#5596). [Greg Davill] * Support randomize size constraints with restrictions (#5582 partial) (#5611). [Ryszard Rozak, Antmicro Ltd.] * Support associative array basic constrained randomization (#5658) (#5670). [Yilou Wang] * Support `default disable iff` and `$inferred_disable` (#4016). [Srinivasan Venkataramanan] * Support `extern constraint` and `pure constraint`. * Add `--no-std-waiver` and default reading of standard lint waivers file (#5607). * Add `--no-std-package` as subset-alias of `--no-std` (#5607). * Add `lint_off --contents` in configuration files (#5606). * Add `--waiver-multiline` for context-sensitive `--waiver-output` (#5608). * Add `--fno-inline-funcs` to disable function inlining. * Add `--fno-slice` to disable array assignment slicing (#5644). * Add error on illegal enum base type (#3010). [Iztok Jeras] * Add error on `wait` with missing `.triggered` (#4457). * Add error when improperly storing to parameter (#5147). [Gökçe Aydos] * Add error on illegal `--prefix` etc. values (#5507). [Fabian Keßler] * Add error on `--savable --timing` (#5690). [Narcis Rodas] * Add coverage point hierarchy to coverage reports (#5575) (#5576). [Andrew Nolte] * Add warning on global constraints (#5625). [Ryszard Rozak, Antmicro Ltd.] * Add default CMAKE_BUILD_TYPE (#5691) (#5692). [Anthony Moore] * Add error on `solve before` or soft constraints of `randc` variable. * Improve concatenation performance (#5598) (#5599) (#5602). [Geza Lore] * Improve optimization of duplicate wide expressions (#5637). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix dotted reference in delay value (#2410). * Fix `function fork...join_none` regression with unknown type (#4449). * Fix public_module requiring a wire to become public (#4916). [Andrew Nolte] * Fix --hierarchical on projects with dot-f dependency lists (#5199) (#5669). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix can't locate scope error in interface task delayed assignment (#5462) (#5568). [Zhou Shen] * Fix BLKANDNBLK for for VARXREFs (#5569). [Todd Strader] * Fix VPI error instead of fatal for vpi_get_value() on large signals (#5571). [Todd Strader] * Fix --output-groups leftover files issue (#5574). [Todd Strader] * Fix slow unsized number parsing (#5577). [Geza Lore] * Fix negative assignment pattern keys (#5580). [Iztok Jeras] * Fix duplicate scope identifiers decoding (#5584). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix `rand` dynamic arrays with null handles (#5594). [Ryszard Rozak, Antmicro Ltd.] * Fix NBAs to unpacked arrays of unpacked structs (#5603). [Geza Lore] * Fix array of struct member overwrites on member update (#5605) (#5618) (#5628). [sumpster] * Fix interface and struct pattern collision (#5639) (#5640). [Todd Strader] * Fix mis-aliasing of instances with mailbox parameter types (#5632 partial). * Fix error on duplicated declaration of gen block (#5663). [Ryszard Rozak, Antmicro Ltd.] * Fix wildcard equality and inside operators for non-fourstate expressions (#5673). [Ryszard Rozak, Antmicro Ltd.] * Fix `randomize..with` of parameterized classes (#5676). [Ryszard Rozak, Antmicro Ltd.] * Fix interface bracketed array parameter access (#5677) (#5678). [Todd Strader] * Fix width extension of operands of `inside` operator (#5685). [Ryszard Rozak, Antmicro Ltd.] * Fix VPI + SYMRSVDWORD intersection (#5686). [Todd Strader] * Fix verilator_gantt for hierarchically Verilated models (#5700). [Bartłomiej Chmiel, Antmicro Ltd.] Verilator 5.030 2024-10-27 ========================== **Major:** * Add `-output-groups` to build with concatenated .cpp files (#5257). [Mariusz Glebocki] * Self-tests have been converted to Python, run `{test_name}.py` instead of `{test_name}.pl`. **Minor:** * Change .vlt config files to be read before .v files (#5185). [David Moberg] * Change to use maximum for cover point aggregation (#5402). [Andrew Nolte] * Change `--main` and `--binary` to use a TOP hierarchy name of "" (#5482). * Change install of public executables into bindir instead of pkgdatadir (#5140) (#5544). [Geza Lore] * Support IEEE-compliant intra-assign delays (#3711) (#5441). [Krzysztof Bieganski, Antmicro Ltd.] * Support `wor`, `trior`, `wand`, `triand` (#5386) (#5496). [Zhou Shen] * Support unconstrained randomization for unions (#5395) (#5396). [Yilou Wang] * Support basic constrained queue randomization (#5413). [Arkadiusz Kozdra, Antmicro Ltd.] * Support packed/unpacked and dynamic array unconstrained randomization (#5414) (#5415). [Yilou Wang] * Support appending to queue via `[]` (#5421). [Krzysztof Bieganski, Antmicro Ltd.] * Support named event locals (#5422). [Krzysztof Bieganski, Antmicro Ltd.] * Support basic `dist` constraints (#5431). [Arkadiusz Kozdra, Antmicro Ltd.] * Support unpacked array constrained randomization (#5437) (#5489). [Yilou Wang] * Support inside array constraints (#5448). [Arkadiusz Kozdra, Antmicro Ltd.] * Support DPI imports and exports with double underscores (#5481). * Support ccache when compiling Verilated files with cmake. * Support `local` and `protected` on `typedef` (#5460). * Support unconstrained randomization for associative array and queue (#5515). [Yilou Wang] * Support `rand` dynamic arrays of objects (#5557) (#5564). [Ryszard Rozak, Antmicro Ltd.] * Add error on misused genvar (#408). [Alex Solomatnikov] * Add error on instances without parenthesis. * Add Docker pre-commit hook (#5238) (#5452). [Chris Bachhuber] * Add partial coverage symbol and branch data in lcov info files (#5388). [Andrew Nolte] * Add method to check if there are VPI callbacks of the given type (#5399). [Kaleb Barrett] * Remove warning on unsized numbers exceeding 32-bits. * Improve Verilation thread pool (#5161). [Bartłomiej Chmiel, Antmicro Ltd.] * Improve performance of V3VariableOrder with parallelism (#5406). [Bartłomiej Chmiel, Antmicro Ltd.] * Improve parser error handling (#5493). [Arkadiusz Kozdra, Antmicro Ltd.] * Improve process trigger performance (#5483). [Geza Lore] * Fix suppression of WIDTH* warnings when immediately under a size cast (#3417). * Fix `$fatal` to not be affected by `+verilator+error+limit` (#5135). [Gökçe Aydos] * Fix equivalence checking when replacing type parameters (#5213) (#5255). [Han Qi] * Fix display with multiple string formats (#5311). [Luiza de Melo] * Fix performance of V3Trace when many activity blocks (#5372). [Deniz Güzel] * Fix REALCVT warning on integral timescale conversions (#5378). [Liam Braun] * Fix multidimensional function return value selects (#5382). [Gökçe Aydos] * Fix internal error in out-of-range select (#5393) (#5443). [Geza Lore] * Fix dot fallback finding wrong symbols (#5394). [Arkadiusz Kozdra, Antmicro Ltd.] * Fix infinite recursion due to recursive functions/tasks (#5398). [Krzysztof Bieganski, Antmicro Ltd.] * Fix V3Randomize compile error on old GCC (#5403) (#5417). [Krzysztof Bieganski, Antmicro Ltd.] * Fix extra events in traces (#5405). * Fix empty `foreach` in `if` in constraints (#5408). [Krzysztof Bieganski, Antmicro Ltd.] * Fix queue `[$-i]` select as reference argument (#5411). [Krzysztof Bieganski, Antmicro Ltd.] * Fix `pre`/`post_randomize` on `randomize() with` (#5412). [Krzysztof Bieganski, Antmicro Ltd.] * Fix capturing params in `randomize() with` (#5416) (#5418). [Krzysztof Bieganski, Antmicro Ltd.] * Fix `sformatf` internal error on initial automatics (#5423). [Todd Strader] * Fix clearing trigger of events with no sensitivity trees (#5426). [Arkadiusz Kozdra, Antmicro Ltd.] * Fix driving clocking block in reactive region (#5430). [Krzysztof Bieganski, Antmicro Ltd.] * Fix associative array next/prev/first/last mis-propagating constants (#5435). [Ethan Sifferman] * Fix randomize treated as std::randomize in classes (#5436). [Arkadiusz Kozdra, Antmicro Ltd.] * Fix `foreach` colliding index names (#5444). [Arkadiusz Kozdra, Antmicro Ltd.] * Fix fault on defparam with UNSUPPORTED ignored (#5450). [Luiza de Melo] * Fix class reference with pin that is a class reference (#5454). * Fix not reporting class reference with extra parameters (#5467). * Fix user-type parameter overlap (#5469). [Todd Strader] * Fix tracing when name() is empty (#5470). [Sam Shahrestani] * Fix timing mode not exiting on empty events (#5472). * Fix coverage counts missing due to table optimization (#5473) (#5474). [Vito Gamberini] * Fix `--binary` with .cpp PLI filenames under relative directory paths. * Fix extra dot in coverage point hierarchy when using name()=''. * Fix short-circuiting with associative array access (#5484). [Ethan Sifferman] * Fix short-circuiting on method calls (#5486). [Ethan Sifferman] * Fix exponential concatenate performance (#5488). [Arkadiusz Kozdra, Antmicro Ltd.] * Fix V3Table trying to generate 'x' bits in the lookup table (#5491). [Geza Lore] * Fix randomize with foreach constraints (#5492). [Arkadiusz Kozdra, Antmicro Ltd.] * Fix explicit CMAKE_INSTALL_PREFIX usages (#5500). [Fabian Keßler] * Fix configure inserting absolute paths for Python and Perl (#5504) (#5505). [Nathan Graybeal] * Fix pattern initialization with typedef key (#5512). [Eugene Feinberg] * Fix `-j` option without argument in hierarchical Verilation (#5514). [Ryszard Rozak, Antmicro Ltd.] * Fix `foreach` with 2-D queues and dynamic arrays (#5525) (#5529). [Yilou Wang] * Fix struct array assignment (#5455) (#5537). [Yilou Wang] * Fix copy constructor of classes that use std::process (#5528). [Ryszard Rozak, Antmicro Ltd.] * Fix foreach on associative array (#5530). [Yilou Wang] * Fix multi-range indices assignment (#5534) (#5547). [Yilou Wang] * Fix static function wrappers (#5536). [Ryszard Rozak, Antmicro Ltd.] * Fix assignments of concatenation to queues and dynamic arrays (#5540). [Ryszard Rozak, Antmicro Ltd.] * Fix container reduction methods (#5542). [Krzysztof Boroński] * Fix complex user type problem with `--x-assign` (#5543). [Todd Strader] * Fix long module names crashing string handling (#5546). [Filip Badáň] * Fix array trace splitting (#5549). [Todd Strader] * Fix queue element access (#5551). [Ryszard Rozak, Antmicro Ltd.] * Fix struct literal on pattern assignment (#5552) (#5559). [Todd Strader] * Fix build on gcc when using the Spack wrapper (#5555). [Eric Müller] * Fix enum name method (#5563). [Todd Strader] * Fix `$countbits` in assert with non-tristates (#5566). [Shou-Li Hsu] * Fix missing VlProcess handle in coroutines with splits (#5623) (#5650). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix imported array assignment literals (#5642) (#5648). [Todd Strader] * Fix foreach mixed array (#5655) (#5656). [Yilou Wang] Verilator 5.028 2024-08-21 ========================== **Minor:** * Support state-dependent constraints (#5217). [Arkadiusz Kozdra, Antmicro Ltd.] * Support cross-module clocking variable access (#5184). [Arkadiusz Kozdra, Antmicro Ltd.] * Support inline constraints for class randomization methods (#5234). [Krzysztof Boroński] * Support clocking blocks in virtual interfaces (#5235). [Arkadiusz Kozdra, Antmicro Ltd.] * Support `$assertcontrol` assertion_type (#5236). [Bartłomiej Chmiel, Antmicro Ltd.] * Support conditional constraints (#5245). [Arkadiusz Kozdra, Antmicro Ltd.] * Support`--compiler-include` headers in user-supplied cpp files (#5271). [Bartłomiej Chmiel, Antmicro Ltd.] * Support `rand_mode` (#5273). [Krzysztof Bieganski, Antmicro Ltd.] * Support `this.randomize with` (#5282). [Arkadiusz Kozdra, Antmicro Ltd.] * Support foreach constraints (#5302). [Arkadiusz Kozdra, Antmicro Ltd.] * Support `parameter type` in hierarchical blocks (#5309) (#5333). [Bartłomiej Chmiel, Antmicro Ltd.] * Support assertcontrol directive type (#5310). [Bartłomiej Chmiel, Antmicro Ltd.] * Support inline random variable control (#5317). [Krzysztof Bieganski, Antmicro Ltd.] * Support streaming operator on arrays and wide data (#5326). [Arkadiusz Kozdra, Antmicro Ltd.] * Support streams to/from arrays of wide data (#5334). [Arkadiusz Kozdra, Antmicro Ltd.] * Support `constraint_mode` (#5338). [Krzysztof Bieganski, Antmicro Ltd.] * Support constraining AstSel (#5344). [Arkadiusz Kozdra, Antmicro Ltd.] * Support default value on module input (#5358) (#5373). [Drew Ranck] * Add `--compiler-include` for additional C++ includes (#5139) (#5202). [Bartłomiej Chmiel, Antmicro Ltd.] * Add `--emit-accessors` (#5182) (#5227). [Ryan Ziegler] * Add suggestions on misspelled PLI functions. * Add warning on dist in constraints (#5264). [Arkadiusz Kozdra, Antmicro Ltd.] * Add more `rand_mode` unsupported errors (#5329). [Krzysztof Bieganski, Antmicro Ltd.] * Add parsing but otherwise ignore std::randomize (#5354). [Arkadiusz Kozdra, Antmicro Ltd.] * Add Verilated cc define when `--timing` used (#5383). [Kaleb Barrett] * Improve emitted code to use a reference for VlSelf (#5254). [Yangyu Chen] * Fix monitor block sensitivity items (#4040) (#4400) (#5294). [Udaya Raj Subedi] * Fix fusing macro arguments to not ignore whitespace (#5061). [Tudor Timi] * Fix optimized-out sensitivity trees with `--timing` (#5080) (#5349). [Krzysztof Bieganski, Antmicro Ltd.] * Fix classes/modules of case-similar names (#5109). [Arkadiusz Kozdra] * Fix mis-removing $value$plusargs calls (#5127) (#5137). [Seth Pellegrino] * Fix incorrect result of width mismatch (#5186) (#5189). [Yutetsu TAKATSUKASA] * Fix compiler coroutine check (#5190) (#5300). [Ricardo Barbedo] * Fix shortened module names when searching for files (#5196) (#5246). [Tim Hutt] * Fix `--x-assign` to be independent from `+verilator+rand+reset` (#5214). [Andrew Nolte] * Fix splitting if statements with impure conditions (#5219). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix unknown conversion on queues (#5220). [Alex Solomatnikov] * Fix top-level unpacked structure resets (#5221). * Fix concurrency for mailbox and semaphores (#5222). [Liam Braun] * Fix forks capturing non-input ports in tasks (#5237) (#5343). [Krzysztof Bieganski, Antmicro Ltd.] * Fix toggle coverage aggregation on same line (#5248). [Krzysztof Obłonczek] * Fix error on empty generate with -O0 (#5250). * Fix unconstrained randomization of unpacked structs (#5252). [Krzysztof Bieganski, Antmicro Ltd.] * Fix inlining of variables driven from forced vars (#5259). [Geza Lore] * Fix tracing with `--main-top-name -` (#5261). [Ethan Sifferman] * Fix randomization when used with inheritance (#5268). [Krzysztof Bieganski, Antmicro Ltd.] * Fix inline constraints creating class random generator (#5280). [Krzysztof Bieganski, Antmicro Ltd.] * Fix WIDTHEXPAND on left shift of intuitive amount (#5284). [Greg Taylor] * Fix elaborating foreach loops (#5285). [Arkadiusz Kozdra, Antmicro Ltd.] * Fix initializing static array in dynamic arrays and queues (#5287). [Baruch Sterin] * Fix static variable initializers in procedures (#5296). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix randomizing current object with `rand` class instance member (#5292). [Krzysztof Bieganski, Antmicro Ltd.] * Fix handling of rand fields not referenced in constraints (#5305). [Ryszard Rozak, Antmicro Ltd.] * Fix Python3 path discovery in make flows to avoid mixing system and user python interpreters (#5307). [Markus Krause] * Fix make flows to pass PYTHON3 (like PERL) (#5307) (#5308). [Markus Krause] * Fix assert on wide expression (#5319) (#5324). [Varun Koyyalagunta] * Fix output clock variable overwriting signal (#5320) (#5347). [Krzysztof Bieganski, Antmicro Ltd.] * Fix stringify in nested preprocessor macros (#5323). [Krzysztof Bieganski, Antmicro Ltd.] * Fix $sformat with array arguments (#5330). [Abe Jordan] * Fix -Wunused-but-set-variable clang warning (#5331). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix purity of functions with AstJumpBlock or AstStmtExpr (#5332). [Ryszard Rozak, Antmicro Ltd.] * Fix compilation error on unreachable disable fork / wait fork (#5339). [Arkadiusz Kozdra, Antmicro Ltd.] * Fix missing type coercion in 'inside {array}' (#5340). [Arkadiusz Kozdra, Antmicro Ltd.] * Fix +: and -: unpacked array slicing when array has nonzero low index (#5345) (#5387). [James Bailey] * Fix tracing_{on,off} in the presence of non-inlined modules (#5346). [Geza Lore] * Fix NBAs in suspendables (#5348). [Krzysztof Bieganski, Antmicro Ltd.] * Fix lint_off on Errors (#5351) (#5363). [Ethan Sifferman] * Fix cache config file resolution performance (#5369). [Geza Lore] * Fix capturing fields from superclass in `randomize() with` (#5389). [Krzysztof Bieganski, Antmicro Ltd.] * Fix virtual interface null checks (#5391). [Krzysztof Bieganski, Antmicro Ltd.] * Fix ==? and !=? with X values. * Fix CPU time being zero. * Fix inline function ref port persistence. Verilator 5.026 2024-06-15 ========================== **Major:** * Support constrained randomization with external solvers (#4947). [Arkadiusz Kozdra, Antmicro Ltd.] **Minor:** * Support `$psprintf` system function (#4314) (#5169). [Arkadiusz Kozdra, Antmicro Ltd.] * Support 2D dynamic array initialization (#4700) (#5122). [Valentin Atepalikhin] * Support __en/__out signals on top level inout ports (#4812) (#4856). [Paul Wright] * Support empty queue as dynarray default value (#5055). [Arkadiusz Kozdra, Antmicro Ltd.] * Support vpiInertialDelay (#5087). [Todd Strader] * Support NBAs to arrays inside loops (#5092). [Geza Lore] * Support parsing and otherwise ignoring inline constraints (#5126). [Arkadiusz Kozdra, Antmicro Ltd.] * Support `inout` clocking items (#5160). [Arkadiusz Kozdra, Antmicro Ltd.] * Support StructSel in unpacked array assignments (#5176). [Geza Lore] * Add error on zero width select (#5028). * Add CITATION.cff (#5057) (#5058). [Gijs Burghoorn] * Add VPI eval needed tracking (#5065). [Todd Strader] * Add `--localize-max-size` option and optimization (#5072). * Add parameterless assert control system tasks (#5010). [Bartłomiej Chmiel] * Add traceCapable indication to model header (#5053). [Vito Gamberini] * Add increasing of stack size when possible (#5071) (#5104). [Yinan Xu] * Add assertion on reusing VerilatedContext (#5167). * Add `--pins-sc-uint-bool` to force SystemC uint type (#5192). [Bartłomiej Chmiel, Antmicro Ltd.] * Improve DFG regularization in cyclic graphs (#5142). [Geza Lore] * Improve VerilatedVpiPutHolder storage requirements (#5144). [Kaleb Barrett] * Fix coroutines without awaits to have a co_return (#4208) (#5175). [Arkadiusz Kozdra, Antmicro Ltd.] * Fix missing flex include path variable (#4970) (#4971). [Christopher Taylor] * Fix missing parameters with comma to be errors (#4979) (#5012). [Paul Swirhun] * Fix 'experimental/coroutine' file not found on MacOS (#5030) (#5031) (#5151). [Paul Bowen-Huggett] * Fix bound queue printing (#5032). [Aleksander Kiryk, Antmicro Ltd.] * Fix consecutive zero-delays (#5038). [Krzysztof Bieganski, Antmicro Ltd.] * Fix attempted to destroy locked thread pool error (#5040). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix `$system` with string argument (#5042). * Fix width extension on delays (#5043). * Fix `$typename` on array.min and others (#5049). [Gökçe Aydos] * Fix `make $(info)` which cannot be silenced (#5059). [Gökçe Aydos] * Fix CMake builds to export VERILATOR_ROOT (#5063). [Michael Bikovitsky] * Fix false ASSIGNIN on functions with explicit port map (#5069). * Fix 4-state value support for $readmem (#5070) (#5078). [Ethan Sifferman] * Fix DFG assertion with SystemC (#5076). [Geza Lore] * Fix `$typename` string to be more standard (#5082) (#5083). [Andrew Nolte] * Fix missed optimization in V3Delayed (#5089). [Geza Lore] * Fix macro expansion in strings per 1800-2023 (#5094). [Geza Lore] * Fix width extension of unpacked array select (#5095). [Varun Koyyalagunta] * Fix MacOS missing header (#5096) (#5097). [Vito Gamberini] * Fix assertion failure in V3Gate (#5101). [Yutetsu TAKATSUKASA] * Fix aliases for forced port signals (#5105). [Geza Lore] * Fix tracing interface functions (#5108). [Alex Solomatnikov] * Fix method calls parsing in constraints (#5110). [Arkadiusz Kozdra, Antmicro Ltd.] * Fix vpiInertialDelay for memories (#5113). [Todd Strader] * Fix hierarchical compilation with nested -F (#5114) (#5124). [Alex Solomatnikov] * Fix references to ports in forks (#5123). [Krzysztof Bieganski, Antmicro Ltd.] * Fix output C++ type error on change detect of I/O arrays (#5125) (#5131). [Pawel Jewstafjew] * Fix x-valued parameters with `--x-assign unique` (#5129). [Ethan Sifferman] * Fix overflow of string on VPI reads (#5145) (#5146). [Kaleb Barrett] * Fix VerilatedVpiPutHolder class (#5156). [Kaleb Barrett] * Fix extending out-of-range select (#5159) (#5164). [Geza Lore] * Fix radix in width warnings (#5166). [Geza Lore] * Fix SystemC BITS_PER_DIGIT in VL_ASSIGN_SBW (#5170). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix non-constant replication in concats (#5171). [Arkadiusz Kozdra, Antmicro Ltd.] * Fix table optimization when applied on real data type (#5172) (#5173). [Arthur Rosa] * Fix signed types emitted in hierarchical Verilation (#5178). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix DPI import of null C-string (#5179). * Fix CMake installation missing verilated.mk (#5187) (#5188). [Philip Axer] * Fix linking with pthreads on CMake (#5194). [Tim Hutt] * Fix clang-17 coroutines configuration with -std=gnu++20 (#5200). [Gus Smith] Verilator 5.024 2024-04-05 ========================== **Major:** * Add printing summary reports, use `--quiet` or `+verilator+quiet` to suppress (#4909). * Support 1800-2023 keywords, and parsing with UNDEFINED warnings. * Support 1800-2023 preprocessor ifdef expressions. **Minor:** * Change 1800-2023 to be default language version. * Add DFG 'regularize' pass, and improve variable removal (#4937). [Geza Lore] * Add error when pass net to function argument (#4132) (#4966). [Fuad Ismail] * Add `UNUSEDLOOP` when unused loop is removed (#4926). [Bartłomiej Chmiel, Antmicro Ltd.] * Add custom version for verilator --version packaging (#4954). [Nolan Poe] * Add error on missing pure virtual functions (#4961). * Add error on calling static function without object (#4962). * Add JSON AST dumps (#5020). [Szymon Gizler] * Support 1800-2023 DPI headers, svGetTime/svgGetTimeUnit/svGetTimePrecision methods. * Support 1800-2023 class and function :initial, :extends, :final virtual overrides (#5025). * Support public packed struct / union (#860) (#4878). [Kefa Chen] * Support stream operation on unpacked array (#4714) (#5006). [Fuad Ismail] * Support implicitly-typed variable definitions in for-loop initializers (#4945) (#4986). [Kevin Nygaard] * Support inside range with implicit type conversion (#5026). [Arkadiusz Kozdra, Antmicro Ltd.] * Improve installation to be relocatable (#4927). [Geza Lore] * Improve internal ordering code (#4957) (#4990) (#4994) et al. [Geza Lore] * Fix generate blocks in vpi_iterate (#3609) (#4913). [Andrew Nolte] * Fix __Vlip undefined error in --freloop (#4824). [Justin Yao Du] * Fix missing VPI scopes (#4918). [Andrew Nolte] * Fix invalid cast on string structure creation (#4921). * Fix try-lock spuriously fails (#4931) (#4938). [Kamil Rakoczy] * Fix V3Unknown unpacked struct x-assign (#4934). [Yan Xu] * Fix DFG removing forceable signals (#4942). [Geza Lore] * Fix null characters in shortened identifiers (#4946). [Abdul Hameed] * Fix assignment of null into struct member (#4952). * Fix VPI missing scopes 2 (#4965). [Andrew Nolte] * Fix object assignment from conditionals (#4968). * Fix GCC14 warnings on template specialization syntax (#4974) (#4975). [Nolan Poe] * Fix unpacked structure upper bit cleaning (#4978). * Fix tests on MacOS (#4984) (#4985). [Kevin Nygaard] * Fix `--prof-exec` predicted time values (#4988). [Geza Lore] * Fix class type as an associative array parameter (#4997). * Fix inout ports of unpacked struct type (#5000). [Ryszard Rozak, Antmicro Ltd.] * Fix `unique {}` constraints missing semicolon (#5001). * Fix preprocessor to respect strings in joins (#5007). * Fix tracing class parameters (#5014). * Fix memory leaks (#5016). [Geza Lore] * Fix `$readmem` with missing newline (#5019). [Josse Van Delm] * Fix internal error on missing pattern key (#5023). * Fix tracing replicated hierarchical models (#5027). * Fix false LIFETIME warning on `repeat` in `fork-join` (#5456). Verilator 5.022 2024-02-24 ========================== **Minor:** * Add predicted stack overflow warning (#4799). * Add `+verilator+coverage+file` runtime option. * Add `--assert-case` option (#4919). [Yutetsu TAKATSUKASA] * Add `--decorations node` for inserting debug comments into emitted code. * Add `--json-only` and related JSON dumping (#4715) (#4831). [Szymon Gizler, Antmicro Ltd.] * Add `--[no]-stop-fail` option for continuing after assertions (#4904). [Yutetsu TAKATSUKASA] * Add `--runtime-debug` for Verilated executable runtime debugging. * Add `--valgrind` switch (#4828). [Szymon Gizler] * Add `unroll_disable` and `unroll_full` loop control metacomments (#3260). [Jiaxun Yang] * Remove deprecated 32-bit pointer mode (`gcc -m32`). * Deprecate --xml-only and XML dumping (#4715) (#4831). * Change zero replication width error to ZEROREPL warning (#4753) (#4762). [Pengcheng Xu] * Improve message for priority case assertion failure (#4905). [Yutetsu TAKATSUKASA] * Support dumping coverage with `--main`. * Support dumping DFG patterns with `--stats` (#4889). [Geza Lore] * Support `vpiConstType` in `vpi_get_str()` (#4797). [Marlon James] * Support SystemC 3.0.0 public review version (#4805) (#4807). [Anthony Donlon] * Support parsing anonymous primitive instantiations (#4809). [Anthony Donlon] * Fix to not emit already waived warnings in waiver output (#4574) (#4818). [Jonathan Schröter] * Fix `this` in member initialization (#4710). [eliasphanna] * Fix localparam elaboration (#3858) (#4794). [Andrew Nolte] * Fix lint_off disables on preprocessor warnings (#4703). [Srinivasan Venkataramanan] * Fix $time not rounding up (#4790) (#4792). [Paul Wright] * Fix `vpi_get()` and `vpi_get64()` to return vpiUndefined on errors (#4795). [Marlon James] * Fix VPI parameter iteration (#4798). [Marlon James] * Fix delays using wrong timeunit when modules inlined (#4806). [Paul Wright] * Fix warnings in verilated_sc_trace.h for Clang (#4807) (#4827). [Anthony Donlon] * Fix null pointer dereference (#4810) (#4825). [Adrian Sampson] * Fix compilation error on multi-inherited interface class usage (#4819). * Fix maybe-uninitialized compiler warning (#4820) (#4822). [Larry Doolittle] * Fix mis-splitting of dump control functions (#4821). [Fan Shupei] * Fix wrong utimes() parameter (#4829). [Szymon Gizler] * Fix incorrect bit-op-tree NOT optimization (#4832) (#4847). [Yutetsu TAKATSUKASA] * Fix width calculation in replaceShiftOp (#4837) (#4841) (#4849). [Yutetsu TAKATSUKASA] * Fix unsafe write in wide array insertion (#4850) (#4855). [Paul Swirhun] * Fix NOT when checking EQ/NEQ under AND/OR tree (#4857) (#4863). [Yutetsu TAKATSUKASA] * Fix tracing chandles (#4860). [Nathan Graybeal] * Fix $fwrite of null (#4862). [Jose Tejada] * Fix -fno-const-bit-op-tree wrong runtime result (#4864) (#4867). [Yutetsu TAKATSUKASA] * Fix SystemC biguint sign desynchronization (#4870). [Bartłomiej Chmiel] * Fix incorrect temporary insertion in loop conditions with statements (#4873). [Geza Lore] * Fix timing with expr on assign LHS (#4880). [Krzysztof Bieganski, Antmicro Ltd.] * Fix assertion for unique case (#4892). [Yutetsu TAKATSUKASA] * Fix GCC tautological-compare warnings. * Fix compile error on structs with queues (and ignore toggle coverage on queues). * Fix toggle coverage error on multi-edge driven signals. * Fix whitespace in `pragma protect version` (#4902) (#4914). [Paul Swirhun] * Fix incorrect code generation for change expression on typedefed unpacked array (#4915). [Geza Lore] * Fix inconsistent driver resolution with typedefs (#4917). [Geza Lore] Verilator 5.020 2024-01-01 ========================== **Major:** * Support compilation with precompiled headers with Make, and GCC or CLang. * Change include to systemc instead of systemc.h (#4622) (#4623). [Chih-Mao Chen] This may require that SystemC programs add 'using namespace sc_core', 'using namespace sc_dt'. **Minor:** * Add devcontainer support (#4748). [Stefan Wallentowitz] * Support `iff` in sensitivity list (#1482) (#4626). [Krzysztof Bieganski, Antmicro Ltd.] * Support parameterized virtual interfaces (#4047) (#4743). [Ryszard Rozak, Antmicro Ltd.] * Support --timing triggers for virtual interfaces (#4673). [Krzysztof Bieganski, Antmicro Ltd.] * Support ccache when compiling Verilator with CMake (#4678). [Anthony Donlon] * Support passing constraints to --xml-only output (still otherwise unsupported) (#4683). [Shahid Ikram] * Support node memory usage information in --stats (#4684). [Geza Lore] * Support vpiConstType in vpi_get() (#4761). [Todd Strader] * Support vpi_iterate on packages with vpiInstance (#4726). [Todd Strader] * Support multiple parameters in virtual interfaces (#4745). [Ryszard Rozak, Antmicro Ltd.] * Support user C/C++ code in final archive, and make a lib{model}.a (#4749) (#4754). [Fan Shupei] * Support inside operator on unpacked arrays and queues (#4751). [Ryszard Rozak, Antmicro Ltd.] * Support VPI parameter iteration (#4765). [Todd Strader] * Support packages in vpi_handle_by_name() (#4768). [Todd Strader] * Support invoking interface methods on virtual interface variables (#4774) (#4775). [Jordan McConnon] * Remove deprecated options (#4663). [Geza Lore] * Remove older compiler support; require C++14 or newer (#4784) (#4786). * Optimize timing-delayed queue (#4584). [qrqiuren] * Optimize substitute optimization memory usage (#4687). [Geza Lore] * Optimize wide primitive operations with -Oz (#4733). [Geza Lore] * Optimize V3Premit performance etc. (#4736). [Geza Lore] * Fix VPI TOP level variable iteration (#3919) (#4618). [Marlon James] * Fix display with no % printing assoc array (#4376). [Alex Solomatnikov] * Fix scheduling of external force signals (#4577) (#4668). [Geza Lore] * Fix a memory leak in V3Fork (#4628). [Krzysztof Boroński] * Fix linking parameterized hierarchical blocks and recursive hierarchical blocks (#4654). [Anthony Donlon] * Fix identifiers that end with '_' on Windows (#4655). [Anthony Donlon] * Fix 'for' loop with outside variable reference (#4660). [David Harris] * Fix tracing FST enums (#4661) (#4756). [Todd Strader] * Fix interface parameters used in loop generate constructs (#4664) (#4665). [Anthony Donlon] * Fix C++20 compilation errors (#4670). * Fix deadlocks in error handler (#4672). [Mariusz Glebocki, Antmicro Ltd.] * Fix MingW compilation (#4675). [David Ledger] * Fix trace when using SystemC with certain configurations (#4676). [Anthony Donlon] * Fix range access to classes depending on parameter resolution (#4681). [Krzysztof Boroński] * Fix select into constant And/Or/Xor pattern (#4689). [Geza Lore] * Fix access type of function arguments (#4692) (#4694). [Ryszard Rozak, Antmicro Ltd.] * Fix dynamic NBAs with automatic vars (#4696). [Krzysztof Bieganski, Antmicro Ltd.] * Fix # 0 delays for process resumption, etc. (#4697). [Krzysztof Boroński] * Fix conflicted namespace for coroutines (#4701) (#4707). [Jinyan Xu] * Fix compilers seeing empty input due to file system races (#4708). [Flavien Solt] * Fix shift of > 32-bit number (#4719). [Flavien Solt] * Fix Windows include gates in filesystem Flush implementation (#4720). [William D. Jones] * Fix power operator with wide numbers and constants (#4721) (#4763). [Flavien Solt] * Fix parameter passing to ports (#4723). [Ryszard Rozak, Antmicro Ltd.] * Fix block names of nested do..while loops (#4728). [Ryszard Rozak, Antmicro Ltd.] * Fix class name in error on 'new' on virtual class (#4739). [Ryszard Rozak, Antmicro Ltd.] * Fix typedefs pointing to parameterized classes (#4747). [Ryszard Rozak, Antmicro Ltd.] * Fix $finish twice to no longer exit (#4757). [Tim Hutt] * Fix dynamic NBA conditions (#4773). [Krzysztof Bieganski, Antmicro Ltd.] * Fix `V3Fork` stage to run only if `--timing` is set (#4778). [Krzysztof Bieganski, Antmicro Ltd.] * Fix max multiply width and add runtime assertions if too small (#4781). * Fix select value too wide (#5148) (#5153). [Dercury] Verilator 5.018 2023-10-30 ========================== **Major:** * Support compilation with precompiled headers with Make and GCC or CLang. * Change include of systemc instead of systemc.h (#4622) (#4623). [Chih-Mao Chen] This may require that SystemC programs add 'using namespace sc_core', 'using namespace sc_dt'. **Minor:** * Add SIDEEFFECT warning on mishandled side effect cases. * Add trace() API even when Verilated without --trace (#4462). [phelter] * Add warning on interface instantiation without parens (#4094). [Gökçe Aydos] * Add sv_vpi_user.h from IEEE 1800-2017 Annex M (#4606). [Marlon James] * Support 'disable fork' (#4125) (#4569). [Aleksander Kiryk, Antmicro Ltd.] * Support 'wait fork' (#4586). [Aleksander Kiryk, Antmicro Ltd.] * Support 'randc' (#4349). * Support assigning events (#4403). [Krzysztof Boroński] * Support resizing function call inout arguments (#4467). * Support NBAs in non-inlined functions/tasks (#4496) (#4572). [Krzysztof Bieganski, Antmicro Ltd.] * Support converting parameters inside modules to localparams (#4511). [Anthony Donlon] * Support concatenation of unpacked arrays (#4558). [Yutetsu TAKATSUKASA] * Support Clang 16 (#4592). [Mariusz Glebocki] * Support VPI variables of real and string data types (#4594). [Marlon James] * Support making VL_LOCK_SPINS configurable (#4599). [Geza Lore] * Change code --stats output (#4597). [Geza Lore] * Change --prof-exec infrastructure and report (#4602). [Geza Lore] * Change lint_off to not propagate upwards to files including where the lint_off is. * Optimize empty expression statements (#4544). * Optimize trace internals (#4610) (#4612). [Geza Lore] * Optimize internal performance issues (#4638). [Geza Lore] * Fix conversion of impure logical expressions to bit expressions (#487 partial) (#4437). [Ryszard Rozak, Antmicro Ltd.] * Fix enum functions in localparams (#3999). [Andrew Nolte] * Fix passing arguments by reference (#3385 partial) (#4489). [Ryszard Rozak, Antmicro Ltd.] * Fix multithreading handling to separate by code units that use/never use it (#4228). [Mariusz Glebocki, Antmicro Ltd.] * Fix usage of annotation options (#4486) (#4504). [Michal Czyz] * Fix detecting local vars in nested forks (#4493) (#4506). [Kamil Rakoczy] * Fix handling input file path separator (#4515) (#4516). [Anthony Donlon] * Fix mis-support for parameterized UDPs (#4518). [Anthony Donlon] * Fix constant conversion of $realtobits, $bitstoreal (#4522). [Andrew Nolte] * Fix conversion of integers in $display '%e' (#4528). [muzafferkal] * Fix non-inlined interface tracing (#3984) (#4530). [Todd Strader] * Fix stream operations with operands of struct type (#4531) (#4532). [Ryszard Rozak, Antmicro Ltd.] * Fix 'this' in a constructor (#4533). [Ryszard Rozak, Antmicro Ltd.] * Fix stream shift operator of 32 bits (#4536). [Julien Faucher] * Fix object destruction after a copy constructor (#4540) (#4541). [Ryszard Rozak, Antmicro Ltd.] * Fix inlining of real functions miscasting (#4543). [Andrew Nolte] * Fix broken link error for enum references (#4551). [Anthony Donlon] * Fix logical expressions with class objects - caching in v3Const (#4552). [Ryszard Rozak, Antmicro Ltd.] * Fix using functions/tasks following class definition inside module (#4553). [Anthony Donlon] * Fix large constant buffer overflow (#4556). [Varun Koyyalagunta] * Fix instance arrays connecting to array of structs (#4557). [raphmaster] * Fix error message for invalid parameter overrides (#4559). [Anthony Donlon] * Fix shift to remove operation side effects (#4563). * Fix compile warning on unused member function variable (#4567). * Fix method narrowing conversion compiler error (#4568). * Fix interface comparison (#4570). [Krzysztof Bieganski, Antmicro Ltd.] * Fix dynamic triggers for named events (#4571). [Krzysztof Bieganski, Antmicro Ltd.] * Fix dictionaries with keys of class types (#4576). [Ryszard Rozak, Antmicro Ltd.] * Fix to not remap local assign intervals in forks (#4583). [Krzysztof Bieganski, Antmicro Ltd.] * Fix display optimization ignoring side effects (#4585). * Fix PLI/DPI user defined system task/function grammar (#4587) (#4588). [Quentin Corradi] * Fix fault on empty clocking block (#4593). [Alex Mykyta] * Fix creating implicit nets for inputs of gate primitives (#4603). [Geza Lore] * Fix try_put method of unbounded mailbox (#4608). [Ryszard Rozak, Antmicro Ltd.] * Fix stable name generation in V3Fork (#4615) (#4624). [Krzysztof Boroński] * Fix virtual methods (#4616). [Ryszard Rozak, Antmicro Ltd.] * Fix insertion at queue end (#4619). [Krzysztof Boroński] * Fix rand fields of reference types (#4627). [Ryszard Rozak, Antmicro Ltd.] * Fix dynamic casts of null values (#4631). [Ryszard Rozak, Antmicro Ltd.] * Fix signals read via virtual interfaces being misoptimized (#4645). [Krzysztof Bieganski, Antmicro Ltd.] * Fix handling of static keyword in methods (#4649). [Ryszard Rozak, Antmicro Ltd.] * Fix preprocessor to show `line 2 on resumed file. Verilator 5.016 2023-09-16 ========================== **Minor:** * Add prepareClone and atClone APIs for Verilated models (#3503) (#4444). [Yinan Xu] * Add check for conflicting options e.g. binary and lint-only (#4409). [Ethan Sifferman] * Add --no-trace-top to not trace top signals (#4412) (#4422). [Frans Skarman] * Support recursive function calls (#3267). * Support assignments of packed values to stream expressions on queues (#4401). [Ryszard Rozak, Antmicro Ltd] * Support no-parentheses calls to static methods (#4432). [Krzysztof Boroński] * Support block_item_declaration in forks (#4455). [Krzysztof Boroński] * Support assignments of stream expressions on queues to packed values (#4458). [Ryszard Rozak, Antmicro Ltd] * Support function non-constant default arguments (#4470). * Support 'let'. * Optimize Verilator executable size by refactoring error reporting routines (#4446). [Anthony Donlon] * Optimize Verilation runtime pointers and graphs (#4396) (#4397) (#4398). [Krzysztof Bieganski, Antmicro Ltd] * Optimize preparations towards multithreaded Verilation (#4291) (#4463) (#4476) (#4477) (#4479). [Kamil Rakoczy, Antmicro Ltd] * Fix Windows filename format, etc (#3873) (#4421). [Anthony Donlon]. * Fix t_dist_cppstyle Perl performance issue (#4085). [Srinivasan Venkataramanan] * Fix using type in parameterized classes without #() (#4281) (#4440). [Anthony Donlon] * Fix false INFINITELOOP on forever..mailbox.get() (#4323). [Srinivasan Venkataramanan] * Fix data type of condition operation on class objects (#4345) (#4352). [Ryszard Rozak, Antmicro Ltd] * Fix variables mutated under fork..join_none/join_any blocks into anonymous objects (#4356). [Krzysztof Boroński] * Fix V3CUse, do not consider implementations (.cpp) at all (#4386). [Krzysztof Boroński] * Fix ++/-- under statements (#4399). [Aleksander Kiryk, Antmicro Ltd] * Fix detection of mixed blocking and nonblocking assignment in nested assignments (#4404). [Ryszard Rozak, Antmicro Ltd] * Fix jumping over object initialization (#4411). [Krzysztof Boroński] * Fix multiple issues towards short circuit support (#4413) (#4460). [Ryszard Rozak, Antmicro Ltd] * Fix variable lifetimes in extern methods (#4414). [Krzysztof Boroński] * Fix multiple function definitions in V3Sched (#4416). [Hennadii Chernyshchyk] * Fix false UNUSEDPARAM on generate localparam (#4427). [Bill Pringlemeir] * Fix checking for parameter and port connections in the wrong place (#4428). [Anthony Donlon] * Fix coroutine handle movement during queue manipulation (#4431). [Aleksander Kiryk, Antmicro Ltd] * Fix nested assignments on the LHS (#4435). [Ryszard Rozak, Antmicro Ltd] * Fix false MULTITOP on bound interfaces (#4438). [Alex Solomatnikov] * Fix internal error on real conversion (#4447). [vdhotre-ventana] * Fix lifetime unknown error on enum.name (#4448). [Johan Wouters] * Fix unstable output of VHashSha256 (#4453). [Anthony Donlon] * Fix static cast from a stream type (#4469) (#4485). [Ryszard Rozak, Antmicro Ltd] * Fix error on enum with VARHIDDEN of cell (#4482). [Michail Rontionov] * Fix lint of case statements with enum and wildcard bits (#4464) (#4487). [Anthony Donlon] * Fix reference to extended class in parameterized class (#4466). * Fix recursive display causing segfault (#4480). [Kuoping Hsu] * Fix the error message when the type of ref argument is wrong (#4490). [Ryszard Rozak, Antmicro Ltd] * Fix display %x formatting of real. * Fix mis-warning on #() in classes' own functions. * Fix IGNOREDRETURN to not warn on void-cast static function calls. * Fix ZERODLY to not warn on 'wait(0)'. Verilator 5.014 2023-08-06 ========================== **Minor:** * Deprecation planned for 32-bit pointer -m32 mode (#4268). * Deprecate CMake config below version 3.13 (#4389) (#4390). [Vito Gamberini] * Support some stream operations on queues (#4292). [Ryszard Rozak, Antmicro Ltd] * Support property declaration with empty parentheses (#4313) (#4317). [Anthony Donlon] * Support locator methods with "with" on assoc arrays (#4335). [Ryszard Rozak, Antmicro Ltd] * Support string replication with variable (#4341). [Aleksander Kiryk, Antmicro Ltd] * Support more types in wait (#4374). [Aleksander Kiryk, Antmicro Ltd] * Support static method calls as default values of function arguments (#4378). [Ryszard Rozak, Antmicro Ltd] * Add GENUNNAMED lint warning. [Srinivasan Venkataramanan, Deepa Palaniappan] * Add MISINDENT lint warning for misleading indentation. * Fix 'VlForkSync' redeclaration (#4277). [Krzysztof Bieganski, Antmicro Ltd] * Fix processes that can outlive their parents (#4253). [Krzysztof Boronski, Antmicro Ltd] * Fix duplicate fork names (#4295). [Ryszard Rozak, Antmicro Ltd] * Fix splitting coroutines (#4297) (#4307). [Jiamin Zhu] * Fix error when multiple duplicate DPI exports (#4301). * Fix class reference assignment checking (#4296). [Ryszard Rozak, Antmicro Ltd] * Fix handling of ref types in initial values of type parameters (#4304). [Ryszard Rozak, Antmicro Ltd] * Fix comparison of string parameters (#4308). [Ryszard Rozak, Antmicro Ltd] * Fix state update for always processes (#4311). [Aleksander Kiryk, Antmicro Ltd] * Fix multiple edge timing controls in class methods (#4318) (#4320) (#4344). [Krzysztof Bieganski, Antmicro Ltd] * Fix implicit calls of base class constructors with optional arguments (#4319). [Ryszard Rozak, Antmicro Ltd] * Fix propagation of process requirement (#4321). [Krzysztof Boroński] * Fix unhandled overloads in V3InstrCount (#4324). [Krzysztof Boroński] * Fix selects of static members (#4326). [Ryszard Rozak, Antmicro Ltd] * Fix references to members of results of static methods (#4327). [Ryszard Rozak, Antmicro Ltd] * Fix unique..with method on queues of class objects (#4328). [Ryszard Rozak, Antmicro Ltd] * Fix queue slicing (#4329). [Aleksander Kiryk, Antmicro Ltd] * Fix wildcard referring types (#4336) (#4342). [Aleksander Kiryk, Antmicro Ltd] * Fix comparison of class objects (#4346). [Ryszard Rozak, Antmicro Ltd] * Fix unexpected RefDType on assoc arrays (#4337). [Aleksander Kiryk, Antmicro Ltd] * Fix cmake astgen for Rocky Linux 8.7 (#4343). [Julian Daube] * Fix class timescale in class packages (#4348). [Krzysztof Bieganski, Antmicro Ltd] * Fix string concatenations (#4354). [Ryszard Rozak, Antmicro Ltd] * Fix unlinked task error from broken context (#4355) (#4402). [Aleksander Kiryk, Antmicro Ltd] * Fix selects on unpacked structs (#4359). [Ryszard Rozak, Antmicro Ltd] * Fix select operation on assoc array with wide keys (#4360). [Ryszard Rozak, Antmicro Ltd] * Fix non-public methods with wide output (#4364). [Ryszard Rozak, Antmicro Ltd] * Fix handling of super.new calls (#4366). [Ryszard Rozak, Antmicro Ltd] * Fix assign to input var in methods (#4367). [Aleksander Kiryk, Antmicro Ltd] * Fix VlProcess not found (#4368). [Aleksander Kiryk, Antmicro Ltd] * Fix order of evaluation of function calls in statements (#4375). [Ryszard Rozak, Antmicro Ltd] * Fix config_build.h issues (#4380) (#4381). [Andrew Miloradovsky] Verilator 5.012 2023-06-13 ========================== **Major:** * With -j or --build-jobs, multithread Verilator's emit phase of Verilation. [Kamil Rakoczy, Antmicro Ltd] Additional Verilator-internal stages will become multithreaded over time. **Minor:** * Add --main-top-name option for C main TOP name (#4235) (#4249). [Don Williamson] * Add creating __inputs.vpp file with --debug (#4177). [Tudor Timi] * Add NEWERSTD warning when using feature in newer language standard (#4168) (#4172). [Ethan Sifferman] * Add warning that timing controls in DPI exports are unsupported (#4238). [Krzysztof Bieganski, Antmicro Ltd] * Support std::process class (#4212). [Aleksander Kiryk, Antmicro Ltd] * Support inside expressions with strings and doubles (#4138) (#4139). [Krzysztof Boroński] * Support get_randstate/set_randstate class method functions. * Support for condition operator on class objects (#4214). [Ryszard Rozak, Antmicro Ltd] * Support array max (#4275). [Aleksander Kiryk, Antmicro Ltd] * Optimize VPI callValueCbs (#4155). [Hennadii Chernyshchyk] * Configure for faster C++ linking using 'mold', if it is installed. * Fix crash on duplicate imported modules (#3231). [Robert Balas] * Fix false WIDTHEXPAND on array declarations (#3959). [Jose Tejada] * Fix marking overridden methods as coroutines (#4120) (#4169). [Krzysztof Bieganski, Antmicro Ltd] * Fix SystemC signal copy macro use (#4135). [Josep Sans] * Fix duplicate static names in blocks in functions (#4144) (#4160). [Stefan Wallentowitz] * Fix initialization order of initial static after function/task (#4159). [Kamil Rakoczy, Antmicro Ltd] * Fix linking AstRefDType if it has parameterized class ref (#4164) (#4170). [Ryszard Rozak, Antmicro Ltd] * Fix crash caused by $display() optimization (#4165) (#4166). [Tudor Timi] * Fix arrays of unpacked structs (#4173). [Risto Pejašinović] * Fix $fscanf of decimals overflowing variables (#4174). [Ahmed El-Mahmoudy] * Fix super.new missing data type (#4147). [Tudor Timi] * Fix missing class forward declarations (#4151). [Krzysztof Boroński] * Fix hashes of instances of parameterized classes (#4182). [Ryszard Rozak, Antmicro Ltd] * Fix forced assignments that override non-continuous assignments (#4183) (#4192). [Krzysztof Bieganski, Antmicro Ltd] * Fix wide structure VL_TOSTRING_W generation (#4188) (#4189). [Aylon Chaim Porat] * Fix references to members of parameterized base classes (#4196). [Ryszard Rozak, Antmicro Ltd] * Fix tracing undefined alignment (#4201) (#4288) [John Wehle] * Fix class-specific same methods for AstVarScope, AstVar, and AstScope (#4203) (#4250). [John Wehle] * Fix dotted references in parameterized classes (#4206). [Ryszard Rozak, Antmicro Ltd] * Fix bit selections under parameterized classes (#4210). [Ryszard Rozak, Antmicro Ltd] * Fix duplicate std:: declaration with -I (#4215). [Harald Pretl] * Fix deep traversal of class inheritance timing (#4216). [Krzysztof Boroński] * Fix class parameters of enum types (#4219). [Ryszard Rozak, Antmicro Ltd] * Fix static methods with prototypes (#4220). [Ryszard Rozak, Antmicro Ltd] * Fix LATCH warning on function local variables (#4221) (#4284) [Julien Margetts] * Fix VCD scope types (#4227) (#4282). [Àlex Torregrosa] * Fix incorrect multi-driven lint warning (#4231) (#4248). [Adrien Le Masle] * Fix missing assignment for wide unpacked structs (#4233). [Jiamin Zhu] * Fix unpacked struct == and != operators (#4234) (#4240). [Risto Pejašinović] * Fix AstStructSel clean when data type is structure (#4241) (#4244). [Risto Pejašinović] * Fix function calls in with statements (#4245). [Ryszard Rozak, Antmicro Ltd] * Fix operator == for unpacked struct, if elements are VlUnpacked arrays (#4247). [Risto Pejašinović] * Fix STATIC lifetime for variables created from clocking items (#4262). [Krzysztof Boroński] * Fix names of foreach blocks (#4264). [Ryszard Rozak, Antmicro Ltd] * Fix iterated variables in foreach loops to have VAUTOM lifetimes (#4265). [Krzysztof Boroński] * Fix missing assignment for wide class members (#4267). [Jiamin Zhu] * Fix the global uses timing flag when forks exist (#4274). [Krzysztof Bieganski, Antmicro Ltd] * Fix struct redefinition (#4276). [Aleksander Kiryk, Antmicro Ltd] * Fix detection of wire/reg duplicates. * Fix false IMPLICITSTATIC on package functions. * Fix method calls on function return values. Verilator 5.010 2023-04-30 ========================== **Minor:** * Add --public-depth to force public to a certain instance depth (#3952). [Andrew Nolte] * Add --public-params flag (#3990). [Andrew Nolte] * Add CONSTRAINTIGN warning when constraint ignored. * Add STATICVAR warning and convert to automatic (#4018) (#4027) (#4030). [Ryszard Rozak, Antmicro Ltd] * Add error if class types don't match (#4064). [Ryszard Rozak, Antmicro Ltd] * Support class extends of package::class. * Support class srandom and class random stability. * Support class method calls without parenthesis (#3902) (#4082). [Srinivasan Venkataramanan] * Support method calls without parenthesis (#4034). [Ryszard Rozak, Antmicro Ltd] * Support parameterized return types of methods (#4122). [Ryszard Rozak, Antmicro Ltd] * Support parameterized class references in extends statement (#4146). [Ryszard Rozak, Antmicro Ltd] * Support complicated IEEE 'for' assignments. * Support $fopen as an expression. * Support ++/-- on dotted member variables. * Optimize static trigger evaluation (#4142). [Geza Lore, X-EPIC] * Optimize more xor trees (#4071). [Yutetsu TAKATSUKASA] * Change range order warning from LITENDIAN to ASCRANGE (#4010). [Iztok Jeras] * Change ZERODLY to a warning. * Fix random internal crashes (#666). [Dag Lem] * Fix install, standardization in cmake CMakeLists.txt (#3974). [Yu-Sheng Lin] * Fix UNDRIVEN warning seg fault (#3989). [Felix Neumärker] * Fix symbol entries when inheriting classes (#3995) (#3996). [Krzysztof Boroński] * Fix event controls reusing same variable (#4014). Kamil Rakoczy * Fix push to dynamic queue in struct (#4015). [ezchi] * Fix names for blocks in do..while loop (#4019). [Ryszard Rozak, Antmicro Ltd] * Fix randomize on null field (#4023). [Ryszard Rozak, Antmicro Ltd] * Fix rand fields in base classes (#4025). [Ryszard Rozak, Antmicro Ltd] * Fix large return blocks with --comp-limit-blocks (#4028). [tenghtt] * Fix clocking block scope internal error (#4032). [Srinivasan Venkataramanan] * Fix false LATCH warning on --assert 'unique else if' (#4033) ($4054). [Jesse Taube] * Fix characters from DEFENV literals for Conda (#4035) (#4044). [Tim Snyder] * Fix info message prints under --assert (#4036) (#4053). [Srinivasan Venkataramanan] * Fix C++ compile errors when passing class refs as task argument (#4063). [Krzysztof Bieganski, Antmicro Ltd] * Fix NBAs inside fork-joins (#4050). [Aleksander Kiryk, Antmicro Ltd] * Fix task calls as fork statements (#4055). [Krzysztof Bieganski, Antmicro Ltd] * Fix _Vilp used before declaration (#4057) (#4062). [Josep Sans] * Fix incorrect optimization of bit op tree (#4059) (#4070). [Yutetsu TAKATSUKASA] * Fix parameters in a class body to be localparam (#4061). [Ryszard Rozak, Antmicro Ltd] * Fix interface generate begin (#4065). [Srinivasan Venkataramanan] * Fix tracing with awaits at end of block (#4075) (#4076). [Krzysztof Bieganski, Antmicro Ltd] * Fix sense expression variable naming (#4081). [Kamil Rakoczy] * Fix importing symbols from base class (#4084). [Ryszard Rozak, Antmicro Ltd] * Fix false error on new const assignment (#4098). [Tudor Timi] * Fix unpacked structs under classes (#4102). [Tudor Timi] * Fix variables in class methods to be automatic (#4111) (#4137). [Peter Monsson] * Fix to use parallel build for projects with a lot of files (#4116). [Krzysztof Boroński] * Fix including __Syms header in generated C++ files (#4123). [Krzysztof Boroński] * Fix systemc namespace issues (#4126) (#4127). [Eyck Jentzsch] * Fix class param extends A=B (#4128). [Ryszard Rozak, Antmicro Ltd] * Fix missing begin block hierarchy in --xml-only cells section (#4129) (#4133). [Risto Pejašinović] * Fix resolution of class lvalues after parameterization (#4131). [Krzysztof Boroński] * Fix DFG error on $countbits (#4101) (#4143). [Paul Donahue] * Fix duplicating parameter class types (#4115). [Ryszard Rozak, Antmicro Ltd] * Fix class extend param references (#4136). [Ryszard Rozak, Antmicro Ltd] * Fix -CFLAGS to allow overriding optimization levels (#4140). [Peter Monsson] * Fix DPI function type alias (#4148) (#4149). [Toru Niina] * Fix deleting unused parameterized classes (#4150). [Ryszard Rozak, Antmicro Ltd] * Fix false ENUMVALUE on expressions and arrays. * Fix unnecessary verilated_std.sv waivers in --waiver-output. Verilator 5.008 2023-03-04 ========================== **Minor:** * Add --annotate-points option, change multipoint on line reporting (#3876). [Nassim Corteggiani] * Add --verilate-jobs option (#3889). [Kamil Rakoczy, Antmicro Ltd] * Add WIDTHEXPAND and WIDTHTRUNC warnings to replace WIDTH (#3900). [Andrew Nolte] * Add SOURCE_DATE_EPOCH for docs/guide/conf.py (#3918). [Larry Doolittle] * Add /*verilator public[flat|flat_rd|flat_rw| ]*/ metacomments (#3894). [Joseph Nwabueze] * Add lint warning on always_comb multidriven (#3888) (#3939). [Adam Bagley] * Add warning on ++/-- over expressions with potential side effects (#3976). [Krzysztof Boroński] * Add error on mixing .name and by-port instantiations. * Removed deprecated --cdc option. * Support unpacked unions. * Support interface classes and class implements. * Support global clocking and $global_clock. * Support class parameters without initial values. * Support cast to numbers from strings. * Support struct I/O in --lib-create (#3378) (#3892). [Varun Koyyalagunta] * Support function calls without parenthesis (#3903) (#3902). [Ryszard Rozak, Antmicro Ltd] * Support class extending its parameter (#3904). [Ryszard Rozak, Antmicro Ltd] * Support static function variables (#3830). [Ryszard Rozak, Antmicro Ltd] * Support recursive methods (#3987). [Ryszard Rozak, Antmicro Ltd] * Fix real parameters of infinity and NaN. * Fix pattern assignment to unpacked structs (#3510). [Mostafa Garnal] * Fix single-element replication to dynarray/unpacked/queue (#3548). [Gustav Svensk] * Fix constant enum methods (#3621). [Todd Strader] * Fix inconsistent naming of generate scope arrays (#3840). [Andrew Nolte] * Fix namespace fallback resolution (#3863) (#3942). [Aleksander Kiryk, Antmicro Ltd] * Fix std:: to be parsed first (#3864) (#3928). [Aleksander Kiryk, Antmicro Ltd] * Fix cmake warning if multiple SOURCES w/o PREFIX (#3916) (#3927). [Yoda Lee] * Fix parameterized class function linkage (#3917). [Ryszard Rozak] * Fix static members of type aliases of a parameterized class (#3922). [Ryszard Rozak, Antmicro Ltd] * Fix class extend parameter dot case (#3926). [Ryszard Rozak, Antmicro Ltd] * Fix MsWin missing directory exception, and ::std (#3928) (#3933) (#3935). [Kritik Bhimani] * Fix very long VPI signal names (#3929). [Marlon James] * Fix VPI upper interface scopes not found (#3937). [David Stanford] * Fix virus detection false positive (#3944). [Stuart Morris] * Fix constant string function assignment (#3945). [Todd Strader] * Fix constant format field widths (#3946). [Todd Strader] * Fix class field linking when a super classes is a param (#3949). [Ryszard Rozak, Antmicro Ltd] * Fix CMake bad C identifiers (#3948) (#3951). [Zixi Li] * Fix build on HP PA architecture (#3954). [John David Anglin] * Fix date on the front page of verilator.pdf (#3956) (#3957). [Larry Doolittle] * Fix associative arrays declared with ref type (#3960). [Ryszard Rozak, Antmicro Ltd] * Fix missing error on negative replicate (#3963). [Benjamin Menküc] * Fix self references to parameterized classes (#3962). [Ryszard Rozak, Antmicro Ltd] * Fix LITENDIAN warning is backwards (#3966) (#3967). [Cameron Kirk] * Fix subsequent parameter declarations (#3969). [Ryszard Rozak, Antmicro Ltd] * Fix timing delays to not truncate below 64 bits (#3973) (#3982). [Felix Neumärker] * Fix cmake on MacOS to mark weak symbols with -U linker flag (#3978) (#3979). [Peter Debacker] * Fix UNDRIVEN warning seg fault (#3989). [Felix Neumärker] * Fix coverage of class methods (#3998). [Tim Paine] * Fix packed array structure replication. * Fix enum.next(0) and enum.prev(0). Verilator 5.006 2023-01-22 ========================== **Minor:** * Support clocking blocks (#3674). [Krzysztof Bieganski, Antmicro Ltd] * Support unpacked structs (#3802). [Aleksander Kiryk, Antmicro Ltd] * Support Windows-native builds using cmake (#3814). [Kritik Bhimani] * Support p format for UnpackArray (#3877). [Aleksander Kiryk, Antmicro Ltd] * Support property calls without parenthesis (#3879) (#3893). [Ryszard Rozak, Antmicro Ltd] * Support import/export lists in modport (#3886). [Gökçe Aydos] * Support class queue equality (#3895). [Ilya Barkov] * Support type case and type equality comparisons. * Add IMPLICITSTATIC warning when a task/function is implicitly static (#3839). [Ryszard Rozak, Antmicro Ltd] * Add VL_VALUE_STRING_MAX_WORDS override (#3869). [Andrew Nolte] * Optimize expansion of extend operators. * Internal multithreading tests. [Mariusz Glebocki, et al, Antmicro Ltd] * Fix VPI one-time timed callbacks (#2778). [Marlon James, et al] * Fix initiation of function variables (#3815). [Dan Gisselquist] * Fix to zero possibly uninitialized bits in replications (#3815). * Fix crash in DFT due to width use after free (#3817) (#3820). [Jevin Sweval] * Fix signed/unsigned comparison compile warning (#3822). [Kamil Rakoczy] * Fix OS-X weak symbols with -U linker flag (#3823). [Jevin Sweval] * Fix wrong bit op tree optimization (#3824) (#3825). [Yutetsu TAKATSUKASA] * Fix self references when param class instantiated (#3833). [Ryszard Rozak, Antmicro Ltd] * Fix memory leak in V3Sched, etc. (#3834). [Geza Lore] * Fix compatibility with musl libc / Alpine Linux (#3845). [Sören Tempel] * Fix empty case items crash (#3851). [Rich Porter] * Fix VL_CPU_RELAX on MIPS/Armel/s390/sparc (#3843) (#3891). [Kamil Rakoczy] * Fix module parameter name collision (#3854) (#3855). [James Shi] * Fix unpacked array expansion (#3861). [Joey Liu] * Fix signed/unsigned parameter types (#3866). [James Shi] * Fix chain call of abstract class constructor (#3868) (#3883). [Ilya Barkov] * Fix to use same std in Verilator and Verilated compile (#3881). [Kamil Rakoczy, Antmicro Ltd] * Fix foreach unnamedblk duplicate error (#3885). [Ilya Barkov] * Fix elaboration of member selected classes (#3890). [Ilya Barkov] * Fix mismatched widths in DFG (#3872). [Geza Lore, Yike Zhou] * Fix lint for non-integral types in packed structs. * Fix generate case with empty body statements. Verilator 5.004 2022-12-14 ========================== **Major:** * Support named properties (#3667). [Ryszard Rozak, Antmicro Ltd] * Add ENUMVALUE warning when value misused for enum (#726) (#3777) (#3783). * Deprecate --no-threads; use --threads 1 for single threaded (#3703). [Kamil Rakoczy, Antmicro Ltd] **Minor:** * Support std::semaphore and typed std::mailbox (#3708). [Krzysztof Bieganski, Antmicro Ltd] * Support 'with' in unique, unique_index, min, max in queues (#3772). [Ryszard Rozak, Antmicro Ltd] * Support events in VCD/FST traces (#3759). [Yves Mathieu] * Support foreach loops on strings (#3760). [Ryszard Rozak, Antmicro Ltd] * Support member selects in with clauses (#3775). [Ryszard Rozak, Antmicro Ltd] * Support super.new calls (#3789). [Ryszard Rozak, Antmicro Ltd] * Support randcase. * Support pre_randomize and post_randomize. * Support $timeunit and $timeprecision. * Support assignment expressions. * Change ENDLABEL from warning into an error. * Internal AST improvements, also affect XML format (#3721). [Geza Lore] * Deprecate verilated_fst_sc.cpp and verilated_vcd_sc.cpp. * Disable stack size limit (#3706) (#3751). [Mariusz Glebocki] * Add error when use --exe with --lib-create (#3785). [Yinan Xu] * Fix jump handling in do while loops (#3731). [Ryszard Rozak, Antmicro Ltd] * Fix 'with' clause handling in functions (#3739). [Ryszard Rozak, Antmicro Ltd] * Fix CONTEXT compile error on MingW (#3741). [William D. Jones] * Fix MSVC compiler errors (#3742) (#3746). [Kritik Bhimani] * Fix CASEINCOMPLETE when covers all enum values (#3745) (#3782). [Guy-Armand Kamendje] * Fix return type of $countbits functions to int (#3725). [Ryszard Rozak, Antmicro Ltd] * Fix timing control in while-break loops (#3733) (#3769). [Ryszard Rozak, Antmicro Ltd] * Fix return in constructors (#3734). [Ryszard Rozak, Antmicro Ltd] * Fix missing UNUSED warnings with --coverage (#3736). [alejandro-castro-ortegon] * Fix tracing parameters overridden with -G (#3723). [Iztok Jeras] * Fix folding of LogAnd with non-bool operands (#3726). [Geza Lore] * Fix DFG optimization issues (#3740) (#3771). [Geza Lore] * Fix pre/postincrement operations (#3744) (#3756). [Ryszard Rozak, Antmicro Ltd] * Fix cross-compile for MingW, Arm and RISC-V (#3752). [Miodrag Milanović] * Fix $unit as base package for other packages (#3755). [Ryszard Rozak, Antmicro Ltd] * Fix make jobserver with submakes (#3758). [Gus Smith] * Fix to escape VERILATOR_ROOT file paths (#3764) (#3765). [Jiacheng Qian] * Fix empty string literals converting to string types (#3774). [miree] * Fix to remove $date from .vcd files (#3779). [Larry Doolittle] * Fix missing user objects in --lib-create mode (#3780) (#3784). [Yinan Xu] * Fix non-blocking assignments in forks (#3781) (#3800). [Krzysztof Bieganski, Antmicro Ltd] * Fix forks without any delayed statements (#3792) (#3801). [Krzysztof Bieganski, Antmicro Ltd] * Fix internal error in bit op tree optimization (#3793). [Yutetsu TAKATSUKASA] * Fix lint_off EOFNEWLINE in .vlt files (#3796). [Andrew Nolte] * Fix wait 0. * Fix comparing ranged slices of unpacked arrays. Verilator 5.002 2022-10-29 ========================== **Major:** * This is a major new release. * Require C++20 for the new --timing features. Upgrading to a C++20 or newer compiler is strongly recommended. * Support the Active and NBA scheduling regions as defined by the SystemVerilog standard (IEEE 1800-2017 chapter 4). This means all generated clocks are now simulated correctly (#3278, #3384). [Geza Lore, Shunyao CAD] * Support timing controls (delays, event controls in any location, wait statements) and forks. [Krzysztof Bieganski, Antmicro Ltd] This may require adding --timing or --no-timing. See docs for details. * Introduce a new combinational logic optimizer (DFG), that can yield significant performance improvements on some designs. [Geza Lore, Shunyao CAD] * Add --binary option as alias of --main --exe --build --timing (#3625). For designs where C++ was only used to make a simple no-I/O testbench, we recommend abandoning that C++, and instead letting Verilator build it with --binary (or --main). **Minor:** * Split UNUSED warning into genvar, param, and signal warnings (#3607). [Topa Topino] * Support standalone 'this' in classes (#2594) (#3248) (#3675). [Arkadiusz Kozdra, Antmicro Ltd] * Support tristate select/extend (#3604). [Ryszard Rozak, Antmicro Ltd> * Support linting for top module interfaces (#3635). [Kanad Kanhere] * Support virtual interfaces (#3654). [Arkadiusz Kozdra, Antmicro Ltd] * Support class type params without defaults (#3693). [Krzysztof Bieganski, Antmicro Ltd] * Support empty generate_regions (#3695). [mpb27] * Support access to constructs inside type parameters (#3702). [Arkadiusz Kozdra, Antmicro Ltd] * Add --dump-tree-dot to enable dumping Ast Tree .dot files (#3636). [Marcel Chang] * Add --get-supported to determine what features are in Verilator. * Add error on real edge event control. * Fix false LATCH warning on 'unique if' (#3088). [Rachit Nigam] * Fix cell assigning integer array parameters (#3299). [Michael Platzer] * Fix LSB error on --hierarchical submodules (#3539). [danbone] * Fix $display of fixed-width numbers (#3565). [Iztok Jeras] * Fix foreach and pre/post increment in functions (#3613). [Nandu Raj] * Fix linker errors in user-facing timing functions (#3657). [Krzysztof Bieganski, Antmicro Ltd] * Fix null access on optimized-out fork statements (#3658). [Krzysztof Bieganski, Antmicro Ltd] * Fix VPI inline module naming mismatch (#3690) (#3694). [Jiuyang Liu] * Fix deadlock in timeprecision when using SystemC (#3707). [Kamil Rakoczy, Antmicro Ltd] * Fix width mismatch on inside operator (#3714). [Àlex Torregrosa] Verilator 4.228 2022-10-01 ========================== **Announcement:** * The next release is anticipated to premiere Verilator Version 5. Please consider beta-testing the github 'develop-v5' branch, which will soon merge into the github 'master' branch (#3383). **Minor:** * Support some IEEE signal strengths (#3601) (#3629). [Ryszard Rozak, Antmicro Ltd] * Add --main to generate main() C++ (previously was experimental only). * Add --build-jobs, and rework arguments for -j (#3623). [Kamil Rakoczy] * Rename --bin to --build-dep-bin. * Rename debug flags --dumpi-tree, --dumpi-graph, etc. [Geza Lore] * Fix thread safety in SystemC VL_ASSIGN_SBW/WSB (#3494) (#3513). [Mladen Slijepcevic] * Fix crash in gate optimization of circular logic (#3543). [Bill Flynn] * Fix arguments in non-static method call (#3547) (#3582). [Gustav Svensk] * Fix default --mod-prefix when --prefix is repeated (#3603). [Geza Lore] * Fix calling trace() after open() segfault (#3610) (#3627). [Yu-Sheng Lin] * Fix typedef'ed class conversion to Boolean (#3616). [Aleksander Kiryk] * Fix Verilation speed when disabled warnings (#3632). [Kamil Rakoczy, Antmicro Ltd] Verilator 4.226 2022-08-31 ========================== **Minor:** * Add --future0 and --future1 options. * Support class parameters (#2231) (#3541). [Arkadiusz Kozdra, Antmicro Ltd] * Support wildcard index associative arrays (#3501). [Arkadiusz Kozdra, Antmicro Ltd] * Support negated properties (#3572). [Aleksander Kiryk] * Support $test$plusargs(expr) (#3489). * Rename trace rolloverSize() (#3570). * Improve Verilation speed with --threads on large designs. [Geza Lore] * Improve Verilation memory by reducing V3Number (#3521). [Mariusz Glebocki, Antmicro Ltd] * Fix struct pattern assignment (#2328) (#3517). [Mostafa Gamal] * Fix public combo propagation issues (#2905). [Todd Strader] * Fix incorrect tristate logic (#3399) [shareefj, Vighnesh Iyer] * Fix incorrect bit op tree optimization (#3470). [algrobman] * Fix bisonpre for MSYS2 (#3471). * Fix max memory usage (#3483). [Kamil Rakoczy, Antmicro Ltd] * Fix empty string arguments to display (#3484). [Grulfen] * Fix table optimizing away display (#3488). [Stefan Post] * Fix unique_ptr memory header for MinGW64 (#3493). * Fix $dump system task with --output-split-cfuncs (#3495) (#3497). [Varun Koyyalagunta] * Fix wrong bit op tree optimization (#3509). [Nathan Graybeal] * Fix nested default assignment for struct pattern (#3511) (#3524). [Mostafa Gamal] * Fix sformat string incorrectly cleared (#3515) (#3519). [Gustav Svensk] * Fix segfault exporting non-existent package (#3535). * Fix void-cast queue pop_front or pop_back (#3542) (#3364). [Drew Ranck] * Fix case statement comparing string literal (#3544). [Gustav Svensk] * Fix === with some tristate constants (#3551). [Ryszard Rozak, Antmicro Ltd] * Fix converting classes to string (#3552). [Arkadiusz Kozdra, Antmicro Ltd] * Fix --hierarchical with order-based pin connections (#3583) (#3585). [Kelin9298] Verilator 4.224 2022-06-19 ========================== **Major:** * VCD tracing is now parallelized with --threads (#3449). [Geza Lore, Shunyao CAD] **Minor:** * Add -f options to replace -O options (#3436). * Changed --no-merge-const-pool to -fno-merge-const-pool (#3436). * Changed --no-decoration to remove output whitespace (#3460). [Kamil Rakoczy] * Support compile time trace signal selection with tracing_on/off (#3323). [Shunyao CAD] * Support non-ANSI interface port declarations (#3439). [Geza Lore, Shunyao CAD] * Support concat assignment to packed array (#3446). * Improve conditional merging optimization (#3125). [Geza Lore, Shunyao CAD] * Define VM_TRACE_VCD when tracing in VCD format. [Geza Lore, Shunyao CAD] * Add assert when VerilatedContext is mis-deleted (#3121). [Rupert Swarbrick] * Internal prep work towards timing control. [Krzysztof Bieganski, Antmicro Ltd] * Fix hang with large case statement optimization (#3405). [Mike Urbach] * Fix UNOPTFLAT warning from initial static var (#3406). [Kamil Rakoczy] * Fix compile error when enable VL_LEAK_CHECKS (#3411). [HungMingWu] * Fix cmake rules to support higher-level targets (#3377) (#3386). [Martin Stadler] * Fix BLKANDNBLK on $readmem/$writemem (#3379). [Alex Solomatnikov] * Fix 'with' operator with type casting (#3387). [xiak95] * Fix incorrect conditional merging (#3409). [Raynard Qiao] * Fix passing VL_TRACE_FST_WRITER_THREAD in CMake build. [Geza Lore, Shunyao CAD] * Fix compile error under strict C++11 mode (#3463). [Kevin Kiningham] * Fix public unpacked input ports (#3465). [Todd Strader] Verilator 4.222 2022-05-02 ========================== **Minor:** * Split --prof-threads into --prof-exec and --prof-pgo (#3365). [Geza Lore, Shunyao CAD] * Deprecate 'vluint64_t' and similar types (#3255). * Raise error on assignment to const in initial blocks. [Geza Lore, Shunyao CAD] * Issue INITIALDLY/COMBDLY/BLKSEQ warnings consistent with Verilator execution. [Geza Lore, Shunyao CAD] * Support LoongArch ISA multithreading (#3353) (#3354). [Xi Zhang] * Fix MSVC localtime_s (#3124). * Fix Bison 3.8.2 error (#3366). [elike-ypq] * Fix rare bug in -Oz (V3Localize) (#3286). [Geza Lore, Shunyao CAD] * Fix tracing interfaces inside interfaces (#3309). [Kevin Millis] * Fix filenames with dots overwriting debug .vpp files (#3373). * Fix including VK_USER_OBJS in make library (#3370) (#3382). [Julien Margetts] * Fix hang in generate symbol references (#3391) (#3398). [Yoda Lee] * Fix missing #include (#3392). [Aliaksei Chapyzhenka] * Fix crash in recursive module inlining (#3393). [david-sawatzke] * Fix --protect-ids mangling names of library methods. [Geza Lore, Shunyao CAD] * Fix foreach segmentation fault (#3400). [Kamil Rakoczy] Verilator 4.220 2022-03-12 ========================== **Minor:** * Removed the deprecated lint_off flag -msg; use -rule instead. * Removed the deprecated "fl" attribute in XML output; use "loc" attribute instead. * Suppress WIDTH warning on negate using carry bit (#3295). [Peter Monsson] * Add trace dumpvars() call for selective runtime tracing (#3322). [Shunyao CAD] * Add VERILATOR_VERSION_INTEGER for determining API (#3343). [Larry Doolittle] * Improve various V3Combine algorithm details (#3328). [Yutetsu TAKATSUKASA] * Improve various V3Order algorithm details. [Geza Lore] * Fix MacOS arm64 build (#3285) (#3291). [Guokai Chen] * Fix signed number operation (#3294) (#3308). [Raynard Qiao] * Fix FST traces to include vector range (#3296) (#3297). [Jamie Iles] * Fix skipping public enum values with four-state values (#3303). * Fix $readmem file not found to be warning not error (#3310). [Alexander Grobman] * Fix class stringification on wide arrays (#3312). [Iru Cai] * Fix $fscanf etc to return -1 on EOF (#3313). [Jose Tejada] * Fix public function arguments that are arrayed (#3316). [pawel256] * Fix unnamedblk error on foreach (#3321). [Aliaksei Chapyzhenka] * Fix crash in recursive module inlining (#3324). [Larry Doolittle] * Fix VL_RESTORER behavior on passing a lvalue reference (#3326). [HungMingWu] * Fix compile error with --trace-fst --sc (#3332). [leavinel] * Fix cast to array types (#3333). [Todd Strader] * Fix Vdeeptemp error with --threads and --compiler clang (#3338). [Per Karlsson] Verilator 4.218 2022-01-17 ========================== **Major:** * Primary inputs and outputs (VL_INW/VL_OUTW) now use VlWide type. In general this should be backward compatible, but may lead to some wrapper code needing changes. * Option --cdc is deprecated and is planned for removal, file a bug if this is still being used. **Minor:** * Support class static members (#2233). * Support force/release (#2431) (#2593). [Shunyao CAD] * Add 'forceable' attribute to allow forcing from C++ (#3272). [Geza Lore, Shunyao CAD] * Support lower dimension looping in foreach loops (#3172). [Ehab Ibrahim] * Support up to 64 bit enums for .next/.prev/.name (#3244). [Alexander Grobman] * Reduce .rodata footprint of trace initialization (#3250). [Geza Lore, Shunyao CAD] * Support FST tracing in hierarchical Verilation (#3251). [Yutetsu TAKATSUKASA] * Use C++11 standard types for MacOS portability (#3254) (#3257). [Adrien Le Masle] * Fix make support for BSD ar (#2999) (#3256). [Julie Schwartz] * Fix bad ending address on $readmem (#3205). [Julie Schwartz] * Fix MSWIN compile error (#2681). [Unai Martinez-Corral] * Fix break under foreach loop (#3230). * Fix VL_STREAML_FAST_QQI with 64 bit left-hand-side (#3232) (#3235). [Adrien Le Masle] * Fix $sformat of inputs/outputs (#3236). [Adrien Le Masle] * Fix associative array first method as statement (#3228). [Adrien Le Masle] * Fix associative array foreach loop (#3229). * Fix $fclose not accepting expressions (#3237). [Julie Schwartz] * Fix $random not updating seed (#3238). [Julie Schwartz] * Fix top level param overwrite when package has same param (#3241) (#3247). [Adrien Le Masle] * Fix spurious UNUSED by ignoring inout pin connections (#3242). [Julie Schwartz] * Fix splitting of _eval and other top level functions. [Geza Lore, Shunyao CAD] * Fix internal error by inout port (#3258). [Yutetsu TAKATSUKASA] * Fix GCC 11 compile error (#3273). [HungMingWu] Verilator 4.216 2021-12-05 ========================== **Major:** * Add --lib-create, similar to --protect-lib but without protections. * Support tracing through --hierarchical/--lib-create libraries (#3200). **Minor:** * Internal code cleanups and improvements. [Geza Lore] * Improve --thread Verilation-time performance. * Support task name in $display %m (#3211). [Julie Schwartz] * Make 'bit', 'logic' and 'time' types unsigned by default. [Geza Lore] * Optimize $random concatenates/selects (#3114). * Fix array method names with parenthesis (#3181) (#3183). [Teng Huang] * Fix split_var assign merging (#3177) (#3179). [Yutetsu TAKATSUKASA] * Fix wrong bit op tree optimization (#3185). [Yutetsu TAKATSUKASA] * Fix some SliceSels not being constants (#3186) (#3218). [Michaël Lefebvre] * Fix nested generate if genblk naming (#3189). [yanx21] * Fix hang on recursive definition error (#3199). [Jonathan Kimmitt] * Fix display of signed without format (#3204). [Julie Schwartz] * Fix display of empty string constant (#3207) (#3215). [Julie Schwartz] * Fix incorrect width after and-or optimization (#3208). [Julie Schwartz] * Fix $fopen etc on integer arrays (#3214). [adrienlemasle] * Fix $size on dynamic strings (#3216). * Fix %0 format on $value$plusargs (#3217). * Fix timescale portability on Arm64 (#3222). Verilator 4.214 2021-10-17 ========================== **Major:** * Add profile-guided optimization of mtasks (#3150). **Minor:** * Verilator_gantt has removed the ASCII graphics, use the VCD output instead. * Verilator_gantt now shows the predicted mtask times, eval times, and additional statistics. * Verilator_gantt data files now include processor information, to allow later processing. * Support displaying x and z in $display task (#3107) (#3109). [Iru Cai] * Fix verilator_profcfunc profile accounting (#3115). * Fix display has no time units on class function (#3116). [Damien Pretet] * Fix removing if statement with side effect in condition (#3131). [Alexander Grobman] * Fix --waiver-output for multiline warnings (#2429) (#3141). [Keith Colbert] * Fix internal error on bad widths (#3140) (#3145). [Zhanglei Wang] * Fix crash on clang 12/13 (#3148). [Kuoping Hsu] * Fix cygwin compile error due to missing -std=gnu++14 (#3149). [Sun Kim] * Fix $urandom_range when the range is 0 ... UINT_MAX (#3161). [Iru Cai] * Fix constructor-parameter argument comma-separation in C++ (#3162). [Matthew Ballance] * Fix missing install of vl_file_copy/vl_hier_graph (#3165). [Popolon] * Fix calling new with arguments in same class (#3166). [Matthew Ballance] * Fix false EOFNEWLINE warning when DOS carriage returns present (#3171). Verilator 4.212 2021-09-01 ========================== **Minor:** * Fix re-evaluation of logic dependent on state set in DPI exports (#3091). [Geza Lore] * Support unpacked array localparams in tasks/functions (#3078). [Geza Lore] * Support timeunit/timeprecision in $unit. * Support assignment patterns as children of pins (#3041). [Krzysztof Bieganski, Antmicro Ltd] * Add --instr-count-dpi to tune assumed DPI import cost for multithreaded model scheduling. Default value changed to 200 (#3068). [Yinan Xu] * Output files are split based on the set of headers required in order to aid incremental compilation via ccache (#3071). [Geza Lore] * Parameter values are now emitted as 'static constexpr' instead of enum. C++ direct references to parameters might require updating (#3077). [Geza Lore] * Refactored Verilated include files; include verilated.h not verilated_heavy.h. * Add header guards on Dpi.h generated files (#2979). [Tood Strader] * Add XML ccall, constpool, initarray, and if/while begins (#3080). [Steven Hugg] * Add error when constant function under a generate (#3103). [Don Owen] * Fix -G to treat simple integer literals as signed (#3060). [Anikin1610] * Fix emitted string array initializers (#2895). [Iztok Jeras] * Fix bitop tree optimization dropping necessary & operator (#3096). [Flavien Solt] * Fix internal error on wide -x-initial unique (#3106). [Alexandre Joannou] * Fix traces to show array instances with brackets (#3092) (#3095). [Pieter Kapsenberg] Verilator 4.210 2021-07-07 ========================== **Major:** * Generated code is now emitted as global functions rather than methods. '$c' contents might need to be updated, see the docs (#3006). [Geza Lore] * The generated model class instantiated by the user is now an interface object and no longer the TOP module instance. User code with direct C++ member access to model internals, including verilator public_flat items will likely need to be updated. See the manual for instructions: https://verilator.org/guide/latest/connecting.html#porting-from-pre-4-210 (#3036). [Geza Lore] **Minor:** * Add --prof-c to pass profiling to compiler (#3059). [Alexander Grobman] * Optimize a lot more model variables into function locals (#3027). [Geza Lore] * Support middle-of-design nested top modules (#3026). [Dan Petrisko] * Remove deprecated --no-relative-cfuncs option (#3024). [Geza Lore] * Remove deprecated --inhibit-sim option (#3035). [Geza Lore] * Merge const static data globally into a new constant pool (#3013). [Geza Lore] * Allow configure override of AR program (#2999). [ahouska] * In XML, show pinIndex information (#2877). [errae233] * Fix error on unsupported recursive functions (#2957). [Trefor Southwell] * Fix type parameter specialization when struct names are same (#3055). [7FM] * Improve speed of table optimization (-OA) pass. [Geza Lore] Verilator 4.204 2021-06-12 ========================== **Minor:** * Add 'make ccache-report' (#3011). [Geza Lore] * Add --reloop-limit argument (#2943) (#2960). [Geza Lore] * Add --expand-limit argument (#3005). [Julien Margetts] * Add TRACE_THREADS to CMake (#2934). [Jonathan Drolet] * Optimize large lookup tables to static data (#2925). [Geza Lore] * Optimize reloop to accept constant index offsets (#2939). [Geza Lore] * Split always blocks to better respect --output-split-cfuncs. [Geza Lore] * Support ignoring "`pragma protect ..." (#2886). [Udi Finkelstein] * Support --trace-fst for SystemC with CMake (#2927). [Jonathan Drolet] * Update cmake latest C++ Standard Compilation flag (#2951). [Ameya Vikram Singh] * Prep work towards better ccache hashing/performance. [Geza Lore] * Fix assertion failure in bitOpTree optimization (#2891) (#2899). [Raynard Qiao] * Fix DPI functions not seen as vpiModule (#2893). [Todd Strader] * Fix bounds check in VL_SEL_IWII (#2910). [Krzysztof Bieganski, Antmicro Ltd] * Fix slowdown in elaboration (#2911). [Nathan Graybeal] * Fix initialization of assoc in assoc array (#2914). [myftptoyman] * Fix make support for gmake 3.x (#2920) (#2921). [Philipp Wagner] * Fix VPI memory access for packed arrays (#2922). [Todd Strader] * Fix MCD close also closing stdout (#2931). [Alexander Grobman] * Fix split procedures to better respect --output-split-cfuncs (#2942). [Geza Lore] * Fix to emit 'else if' without nesting (#2944). [Geza Lore] * Fix part select issues in LATCH warning (#2948) (#2938). [Julien Margetts] * Fix to not emit empty files with low split limits (#2961). [Geza Lore] * Fix merging of assignments in C++ code (#2970). [Rupert Swarbrick] * Fix unused variable warnings (#2991). [Pieter Kapsenberg] * Fix --protect-ids when using SV classes (#2994). [Geza Lore] * Fix constant function calls with uninitialized value (#2995). [yanx21] * Fix Makefiles to support Windows EXEEXT usage (#3008). [Miodrag Milanovic] Verilator 4.202 2021-04-24 ========================== **Major:** * Documentation has been rewritten into a book format. * Verilated signals now use VlWide and VlPacked in place of C arrays. **Minor:** * Add an URL on warnings to point to the manual's description. * Add EOFNEWLINE warning when missing a newline at EOF. * Changed TIMESCALEMOD from error into a warning. * Mark --no-relative-cfuncs as scheduled for deprecation. * Add --coverage-max-width (#2853). [xuejiazidi] * Add VerilatedCovContext::forcePerInstance (#2793). [Kevin Laeufer] * Add FST SystemC tracing (#2806). [Àlex Torregrosa] * Add PINNOTFOUND warning in place of error (#2868). [Udi Finkelstein] * Support overlaps in priority case statements (#2864). [Rupert Swarbrick] * Support for null ports (#2875). [Udi Finkelstein] * Fix class unpacked-array compile error (#2774). [Iru Cai] * Fix scope types in FST and VCD traces (#2805). [Àlex Torregrosa] * Fix exceeding command-line ar limit (#2834). [Yinan Xu] * Fix false $dumpfile warning on model save (#2834). [Yinan Xu] * Fix --timescale-override not suppressing TIMESCALEMOD (#2838). [Kaleb Barrett] * Fix false TIMESCALEMOD on generate-ignored instances (#2838). [Kaleb Barrett] * Fix --output-split with class extends (#2839). [Iru Cai] * Fix false WIDTHCONCAT on casted constant (#2849). [Rupert Swarbrick] * Fix tracing of long hashed names (#2854). [Graham Rushton] * Fix --public-flat-rw / DPI issue (#2858). [Todd Strader] * Fix interface localparam access (#2859). [Todd Strader] * Fix Cygwin example compile issues (#2856). [Mark Shaw] * Fix select of with index variable (#2880). [Alexander Grobman] * Fix cmake version number to be numeric (#2881). [Yuri Victorovich] * Fix MinGW not supporting 'localtime_r' (#2882). [HyungKi Jeong] * Fix cast from packed, typedef'ed interface signal (#2884). [Todd Strader] * Fix VPI package reported as vpiModule (#2885). [Todd Strader] * Fix dumping waveforms to multiple FST files (#2889). [David Metz] * Fix assertion failure in bitOpTree (#2892). [Yutetsu TAKATSUKASA] * Fix V3Premit infinite loop on always read-and-write (#2898). [Raynard Qiao] * Fix VPI packed vectors (#2900). [Todd Strader] * Fix VPI public interface parameters (#2901). [Todd Strader] Verilator 4.200 2021-03-12 ========================== **Announcement:** * --inhibit-sim is planned for deprecation, file a bug if this is still being used. **Major:** * Add simulation context (VerilatedContext) to allow multiple fully independent models to be in the same process. Please see the updated examples (#2660). * Add context->time() and context->timeInc() API calls, to set simulation time. These now are recommended in place of the legacy sc_time_stamp(). **Minor:** * Converted Asciidoc documentation into reStructuredText (RST) format. * Fix range inheritance on port without data type (#2753). [Embedded Go] * Fix slice-assign overflow (#2803) (#2811). [David Turner] * Fix interface array connection ordering broken in v4.110 (#2827). [Don Owen] * Fix or-reduction on different scopes broken in 4.110 (#2828). [Yinan Xu] * Fix MSVC++ compile error (#2831) (#2833). [Drew Taussig] Verilator 4.110 2021-02-25 ========================== **Major:** * Optimize bit operations and others (#2186) (#2632) (#2633) (#2751) (#2800) [Yutetsu TAKATSUKASA] **Minor:** * Support concat selection (#2721). * Support struct scopes when dumping structs to VCD (#2776) [Àlex Torregrosa] * Generate SELRANGE for potentially unreachable code (#2625) (#2754) [Pierre-Henri Horrein] * For --flatten, override inlining of public and no_inline modules (#2761) [James Hanlon] * Fix little endian interface pin swizzling (#2475). [Don Owen] * Fix range inheritance on port without data type (#2753). [Embedded Go] * Fix TIMESCALE warnings on primitives (#2763). [Xuanqi] * Fix to exclude strings from toggle coverage (#2766) (#2767) [Paul Wright] * Fix $fread extra semicolon inside statements. [Leendert van Doorn] * Fix class extends with VM_PARALLEL_BUILDS (#2775). [Iru Cai] * Fix shifts by > 32 bit values (#2785). [qrq992] * Fix examples not flushing vcd (#2787). [Richard E George] * Fix little endian packed array pattern assignment (#2795). [Àlex Torregrosa] Verilator 4.108 2021-01-10 ========================== **Major:** * Many VPI changes for IEEE compatibility, which may alter behavior from previous releases. * Support randomize() class method and rand (#2607). [Krzysztof Bieganski, Antmicro Ltd] **Minor:** * Support $cast and new CASTCONST warning. * Add --top option as alias of --top-module. * Add LATCH and NOLATCH warnings (#1609) (#2740). [Julien Margetts] * Remove Unix::Processors internal test dependency. * Report UNUSED on parameters, localparam and genvars (#2627). [Charles Eric LaForest] * Add error on real to non-real output pins (#2690). [Peter Monsson] * Support package imports before parameters in interfaces (#2714). [James Hanlon] * Support --sanitize in internal tests (#2705). [Yutetsu TAKATSUKASA] * Fix passing parameter type instantiations by position number. * Fix DPI open array handling issues. * Fix error when dotted refers to missing module (#2095). [Alexander Grobman] * Fix little endian packed array counting (#2499). [phantom-killua] * Fix showing reference locations for BLKANDNBLK (#2170). [Yuri Victorovich] * Fix genblk naming to match IEEE (#2686). [tinshark] * Fix VPI memory word indexing (#2695). [Marlon James] * Fix vpiLeftRange on little-endian memories (#2696). [Marlon James] * Fix VPI module tree (#2704). [Todd Strader] * Fix vpi_release_handle to be called implicitly per IEEE (#2706). * Fix to allow inheriting 'VerilatedVcdFile' class (#2720). [HyungKi Jeong] * Fix $urandom_range maximum value (#2723). [Nandu Raj] * Fix tracing empty sc module (#2729). * Fix generate for unrolling to be signed (#2730). [yanx21] * Fix to emit timescale in hierarchical blocks (#2735). [Yutetsu TAKATSUKASA] * Fix to ignore coverage on real ports (#2741) (#2745). [Paul Wright] Verilator 4.106 2020-12-02 ========================== **Major:** * Change -sv option to select 1800-2017 instead of 1800-2005. **Minor:** * Check for proper 'local' and 'protected' (#2228). * Support $random and $urandom seeds. * Support $monitor and $strobe. * Support complex function arguments. * Support 'super'. * Support 'with item.index'. * Fix the default GNU Make executable name on FreeBSD (#2553). [Yuri Victorovich] * Fix trace signal names getting hashed (#2643). [Barbara Gigerl] * Fix unpacked array parameters near functions (#2639). [Anderson Ignacio da Silva] * Fix access to non-overridden base class variable (#2654). [Tobias Rosenkranz] Verilator 4.104 2020-11-14 ========================== **Minor:** * Support queue and associative array 'with' statements (#2616). * Support queue slicing (#2326). * Support associative array pattern assignments and defaults. * Support static methods and typedefs in classes (#2615). [Krzysztof Bieganski, Antmicro Ltd] * Add error on typedef referencing self (#2539). [Cody Piersall] * With --debug, turn off address space layout randomization. * Fix iteration over mutating list bug in VPI (#2588). [Kaleb Barrett] * Fix cast width propagation (#2597). [flex-liu] * Fix return from callValueCbs (#2589) (#2605). [Marlon James] * Fix WIDTH warnings on comparisons with nullptr (#2602). [Rupert Swarbrick] * Fix fault when $fgets, $sscanf, etc used with string (#2604). [Yutetsu TAKATSUKASA] * Fix WIFEXITED missing from MinGW/MSYS2 (#2609). [Jean Berniolles] * Fix queue poping wrong value when otherwise unused (#2512). [nanduraj1] * Fix arrays of modport interfaces (#2614). [Thierry Tambe] * Fix split_var internal error (#2640) (#2641). [Yutetsu TAKATSUKASA] Verilator 4.102 2020-10-15 ========================== **Minor:** * Support const object new() assignments. * Support # as a comment in -f files (#2497). [phantom-killua] * Support 'this' (#2585). [Rafal Kapuscik] * Support defines for FST tracing (#2592). [Markus Krause] * Support non-overlapping implication inside properties (#1292). [Peter Monsson] * Fix timescale with --hierarchical (#2554). [Yutetsu TAKATSUKASA] * Fix cmake build with --hierarchical (#2560). [Yutetsu TAKATSUKASA] * Fix -G dropping public indication (#2561). [Andrew Goessling] * Fix $urandom_range passed variable (#2563). [nanduraj1] * Fix method calls to package class functions (#2565). [Peter Monsson] * Fix class wide member display (#2567). [Nandu Raj P] * Fix hierarchical references inside function (#2267) (#2572). [James Pallister] * Fix flushCall for backward compatibility (#2580). [chenguokai] * Fix preprocessor stringify of undefined macro. [Martin Whitaker] Verilator 4.100 2020-09-07 ========================== **Major:** * C++11 or newer compilers are now required. * SystemC 2.3.0 or newer (SYSTEMC_VERSION >= 20111121) is now required. * Support hierarchical Verilation (#2206). [Yutetsu TAKATSUKASA] **Minor:** * Support (with limitations) class extern, class extends, virtual class. * Support $urandom, $urandom_range without stability. * Support assume property. [Peter Monsson] * Support non-overlapping implication inside properties (#1292). [Peter Monsson] * Fix false DECLFILENAME on black-boxed modules (#2430). [Philipp Wagner] * Fix naming of "id : begin" blocks. * Fix class constructor error on assignments to const. * Fix splitting eval functions with --output-split-cfuncs (#2368). [Geza Lore] * Fix queues as class members (#2525). [nanduraj1] Verilator 4.040 2020-08-15 ========================== **Announcement:** * Version 4.040 is planned to be the final version that will support pre-C++11 compilers. Please move to C++11 or newer compilers. **Minor:** * Fix arrayed interfaces, broke in 4.038 (#2468). [Josh Redford] * Support $stable, $rose and $fell (#2148) (#2501). [Peter Monsson] * Support simple function localparams (#2461). [James Hanlon] * Miscellaneous parsing error changes towards UVM support. * Fix arrayed interfaces (#2469). [Josh Redford] * Fix protect lib VCS warning (#2479). [Julien Margetts] * Fix combining different-width parameters (#2484). [abirkmanis] * Fix protect-lib without sequential logic (#2492). [Yutetsu TAKATSUKASA] * Fix V3Unknown from running with flat XML output (#2494). [James Hanlon] * Fix non-32 bit conversion to float (#2495). [dsvf] * Fix casting non-self-determined subexpressions (#2493). [phantom-killua] * Fix SystemC net names (#2500). [Edgar E. Iglesias] * Fix build with Bison 3.7 and newer (#2505). [Rupert Swarbrick] * Fix slice of unpacked array (#2506) (#2507). [Yutetsu TAKATSUKASA] Verilator 4.038 2020-07-11 ========================== **Announcement:** * Versions 4.038 and 4.040 are planned to be the final versions that will support pre-C++11 compilers. Please move to C++11 or newer compilers. **Minor:** * Support VPI access to parameters and localparam. [Ludwig Rogiers] * Support parsing (not elaboration, yet) of UVM. * Add new UNSUPPORTED error code to replace most previous Unsupported: messages. * With --bbox-unsup continue parsing on many (not all) UVM constructs. * Support for-loop increments with commas. * Support $swrite with arbitrary arguments. * Support $writememb (#2450). [Fan Shupei] * Fix OS X, Free BSD, and -m32 portability issues. [Geza Lore] * Fix to flush FST trace on termination due to $stop or assertion failure. * Fix part select error when multipling by power-of-two (#2413). [Conor McCullough] * Fix division exception (#2460) [Kuoping Hsu] Verilator 4.036 2020-06-06 ========================== **Major:** * OPT_FAST is now -Os by default. See the BENCHMARKING & OPTIMIZATION part of the manual if you experience issues with compilation speed. * --output-split is now on by default. VM_PARALLEL_BUILDS is set by default iff the --output-split caused an actual file split to occur. --output-split-cfuncs and --output-split-ctrace now default to the value of --output-split. These changes should improve build times of medium and large designs with default options. User makefiles may require changes. **Minor:** * Configure now enables SystemC if it is installed as a system headers, e.g. with 'apt-get install systemc-dev'. * Add --waiver-output flag that writes a verilator config file (.vlt) with waivers to the warnings emitted during a Verilator run. * Support verilator_coverage --write-info for lcov HTML reports. * Line Coverage now tracks all statement lines, not just branch lines. * The run-time library is now compiled with -Os by default (#2369, #2373). * Support multi channel descriptor I/O (#2190) [Stephen Henry] * Support $countbits (#2287). [Yossi Nivin] * Support $isunbounded and parameter $ (#2104). * Support unpacked array .sum and .product. * Support prefix/postfix increment/decrement (#2223). [Maciej Sobkowski] * Fix FST tracing of little bit endian signals. [Geza Lore] * Fix +: and -: on unpacked arrays (#2304). [engr248] * Fix $isunknown with constant Z's. * Fix queues and dynamic array wide ops (#2352). [Vassilis Papaefstathiou] Verilator 4.034 2020-05-03 ========================== **Major:** * Support simplistic classes with many restrictions, see manual. (#377) * Support IEEE time units and time precisions. (#234) Includes `timescale, $printtimescale, $timeformat. VL_TIME_MULTIPLIER, VL_TIME_PRECISION, VL_TIME_UNIT have been removed and the time precision must now match the SystemC time precision. To get closer behavior to older versions, use e.g. --timescale-override "1ps/1ps". * Add --build to call make automatically. (#2249) [Yutetsu TAKATSUKASA] * Configuring with ccache present now defaults to using it; see OBJCACHE. * Fix DPI import/export to be standard compliant. (#2236) [Geza Lore] * Add --trace-threads for general multithreaded tracing. (#2269) [Geza Lore] **Minor:** * Add --flatten for use with --xml-only. (#2270) [James Hanlon] * Greatly improve FST/VCD dump performance (#2244) (#2246) (#2250) (#2257) [Geza Lore] * Support $ferror, and $fflush without arguments. (#1638) * Support event data type (with some restrictions). * Support $root. (#2150) [Keyi Zhang] * Add error if use SystemC 2.2 and earlier (pre-2011) as is deprecated. * Add support of --trace-structs for CMake (#2986). [Martin Schmidt] * Fix arrayed instances connecting to slices. (#2263) [Don/engr248] * Fix error on unpacked connecting to packed. (#2288) [Joseph Shaker] * Fix logical not optimization with empty begin. (#2291) [Baltazar Ortiz] * Fix reduction OR on wide data, broke in v4.026. (#2300) [Jack Koenig] * Fix clock enables with bit-extends. (#2299) [Marco Widmer] * Fix MacOs Homebrew by removing default LIBS. (#2298) [Ryan Clarke] Verilator 4.032 2020-04-04 ========================== **Minor:** * Add column numbers to errors and warnings. * Add GCC 9-style line number prefix when showing source text for errors. * Add setting VM_PARALLEL_BUILDS=1 when using --output-split. (#2185) * Change --quiet-exit to also suppress 'Exiting due to N errors'. * Suppress REALCVT for whole real numbers. * Support split_var in vlt files. (#2219) [Marco Widmer] * Fix parameter type redeclaring a type. (#2195) [hdzhangdoc] * Fix VCD open with empty filename. (#2198) [Julius Baxter] * Fix packages as enum base types. (#2202) [Driss Hafdi] * Fix duplicate typedefs in generate for. (#2205) [hdzhangdoc] * Fix MinW portability. (#2114) [Sean Cross] * Fix assertions with unique case inside. (#2199) [hdzhangdoc] * Fix implicit conversion of floats to wide integers. Verilator 4.030 2020-03-08 ========================== **Major:** * Add split_var metacomment to assist UNOPTFLAT fixes. (#2066) [Yutetsu TAKATSUKASA] * Support $dumpfile and $dumpvars. (#2126) [Alexander Grobman] * Support dynamic arrays. (#379) **Minor:** * Add +verilator+noassert flag to disable assertion checking. [Tobias Wölfel] * Add check for assertOn for asserts. (#2162) [Tobias Wölfel] * Add --structs-packed for forward compatibility. * Support $displayb/o/h, $writeb/o/h, etc. (#1637) * Use gcc -Os in examples instead of -O2 for better average performance. * Fix genblk naming with directly nested generate blocks. (#2176) [Alexander Grobman] * Fix undeclared VL_SHIFTR_WWQ. (#2114) [Alex Solomatnikov] Verilator 4.028 2020-02-08 ========================== **Major:** * Support attributes (public, isolate_assignments, etc.) in configuration files. * Add -match to lint_off to waive warnings. [Philipp Wagner] **Minor:** * Link Verilator binary partially statically. (#2146) [Geza Lore] * Verilation speed improvements (#2133) (#2138) [Geza Lore] * Support libgoogle-perftools-dev's libtcmalloc if available. (#2137) [Geza Lore] * Support $readmem/$writemem with assoc arrarys. (#2100) [agrobman] * Support type(expression) operator and $typename. (#1650) * Support left justified $display. (#2101) [Pieter Kapsenberg] * Support string character access via indexing. * Support enum.next(k) with constant k > 1. (#2125) [Tobias Rosenkranz] * Support parameter access from arrays of interfaces. (#2155) [Todd Strader] * Add parameter values in XML. #2110. [Pieter Kapsenberg] * Add loc column location in XML (replaces fl). (#2122) [Pieter Kapsenberg] * Add error on misused define. [Topa Tota] * Add parameter to set maximum signal width. (#2082) [Øyvind Harboe] * Add warning on genvar in normal for loop. (#2143) [Yuri Victorovich] * Fix VPI scope naming for public modules. [Nandu Raj] * Fix FST tracing of enums inside structs. [fsiegle] * Fix WIDTH warning on . * Support VerilatedFstC set_time_unit. (#1433) [Pieter Kapsenberg] * Support deferred assertions. (#1449) [Charles Eddleston] * Mark infrequently called functions with GCC cold attribute. * Fix sign-compare warning in verilated.cpp. (#1437) [Sergey Kvachonok] * Fix fault on $realtime with %t. (#1443) [Julien Margetts] * Fix $display with string without %s. (#1441) [Denis Rystsov] * Fix parameter function string returns. (#1441) [Denis Rystsov] * Fix invalid XML output due to special chars. (#1444) [Kanad Kanhere] * Fix performance when mulithreaded on 1 CPU. (#1455) [Stefan Wallentowitz] * Fix type and real parameter issues (#1427) (#1456) (#1458) [Todd Strader] * Fix build error on MinGW. (#1460) [Richard Myers] * Fix not reporting some duplicate signals. (#1462) [Peter Gerst] * Fix --savable invalid C++ on packed arrays. (#1465) [Alex Chadwick] * Fix constant function return of function var. (#1467) [Roman Popov] Verilator 4.014 2019-05-08 ========================== **Minor:** * Add --trace-fst-thread. * Support '#' comments in $readmem. (#1411) [Frédéric Requin] * Support "'dx" constants. (#1423) [Udi Finkelstein] * For FST tracing use LZ4 compression. [Tony Bybell] * Add error when use parameters without value. (#1424) [Peter Gerst] * Auto-extend and WIDTH warn on unsized X/Zs. (#1423) [Udi Finkelstein] * Fix missing VL_SHIFTL errors. (#1412) (#1415) [Larry Lee] * Fix MinGW GCC 6 printf formats. (#1413) [Sergey Kvachonok] * Fix test problems when missing fst2vcd. (#1417) [Todd Strader] * Fix GTKWave register warning. (#1421) [Pieter Kapsenberg] * Fix FST enums not displaying. (#1426) [Danilo Ramos] * Fix table compile error with multiinterfaces. (#1431) [Bogdan Vukobratovic] Verilator 4.012 2019-03-23 ========================== **Minor:** * Add +verilator+seed. (#1396) [Stan Sokorac] * Support $fread. [Leendert van Doorn] * Support void' cast on functions called as tasks. (#1383) [Al Grant] * Add IGNOREDRETURN warning. (#1383) * Report PORTSHORT errors on concat constants. (#1400) [Will Korteland] * Fix VERILATOR_GDB being ignored. (#2017) [Yu Sheng Lin] * Fix $value$plus$args missing verilated_heavy.h. [Yi-Chung Chen] * Fix MSVC compile error. (#1406) [Benjamin Gartner] * Fix maintainer test when no Parallel::Forker. (#1977) [Enzo Chi] * Fix +1364-1995ext flags applying too late. (#1384) [Al Grant] Verilator 4.010 2019-01-27 ========================== **Minor:** * Removed --trace-lxt2, use --trace-fst instead. * For --xml, add additional information. (#1372) [Jonathan Kimmitt] * Add circular typedef error. (#1388) [Al Grant] * Add unsupported for loops error. (#1986) [Yu Sheng Lin] * Fix FST tracing of wide arrays. (#1376) [Aleksander Osman] * Fix error when pattern assignment has too few elements. (#1378) [Viktor Tomov] * Fix error when no modules in $unit. (#1381) [Al Grant] * Fix missing too many digits warning. (#1380) [Jonathan Kimmitt] * Fix uninitialized data in verFiles and unroller. (#1385) (#1386) [Al Grant] * Fix internal error on xrefs into unrolled functions. (#1387) [Al Grant] * Fix DPI export void compiler error. (#1391) [Stan Sokorac] Verilator 4.008 2018-12-01 ========================== **Minor:** * Support "ref" and "const ref" pins and functions. (#1360) [Jake Longo] * In --xml-only show the original unmodified names, and add module_files and cells similar to Verilog-Perl, msg2719. [Kanad Kanhere] * Add CONTASSREG error on continuous assignments to regs. (#1369) [Peter Gerst] * Add PROCASSWIRE error on behavioral assignments to wires, msg2737. [Neil Turton] * Add IMPORTSTAR warning on import::* inside $unit scope. * Fix --trace-lxt2 compile error on MinGW. (#1990) [HyungKi Jeong] * Fix hang on bad pattern keys. (#1364) [Matt Myers] * Fix crash due to cygwin bug in getline. (#1349) [Affe Mao] * Fix __Slow files getting compiled with OPT_FAST. (#1370) [Thomas Watts] Verilator 4.006 2018-10-27 ========================== **Minor:** * Add --pp-comments. (#1988) [Robert Henry] * Add --dump-defines. * For --trace-fst, save enum decoding information. (#1358) [Sergi Granell] (To visualize enumeration data you must use GTKwave 3.3.95 or newer.) * For --trace-fst, combine hier information into FST. [Tony Bybell] * Fix --trace-lxt2 compile error on MinGW, msg2667. [HyungKi Jeong] * Fix Windows .exe not found. (#1361) [Patrick Stewart] Verilator 4.004 2018-10-06 ========================== **Major:** * Add GTKWave FST native tracing. (#1356) [Sergi Granell] (Verilator developers need to pull the latest vcddiff.) **Minor:** * Support $past. [Dan Gisselquist] * Support restrict. (#1350) [Clifford Wolf] * Rename include/lxt2 to include/gtkwave. * Fix replication of 64-bit signal change detects. * Fix Mac OSX 10.13.6 / LLVM 9.1 compile issues. (#1348) [Kevin Kiningham] * Fix MinGW compile issues. (#1979) [HyungKi Jeong] Verilator 4.002 2018-09-16 ========================== **Major:** * This is a major release. Any patches may require major rework to apply. [Thanks everyone] * Add multithreaded model generation. * Add runtime arguments. * Add GTKWave LXT2 native tracing. (#1333) [Yu Sheng Lin] * Note $random has new algorithm; results may vary vs. previous versions. **Minor:** * Better optimize large always block splitting. (#1244) [John Coiner] * Add new reloop optimization for repetitive assignment compression. * Support string.atoi and similar methods. (#1289) [Joel Holdsworth] * Fix internals to be C++ null-pointer-check clean. * Fix internals to avoid 'using namespace std'. * Fix Verilation performance issues. (#1316) [John Coiner] * Fix clocker attributes to not propagate on concats. [John Coiner] * Fix first clock edge and --x-initial-edge. (#1327) [Rupert Swarbrick] * Fix compile error on tracing of string arrays. (#1338) [Iztok Jeras] * Fix number parsing with newline after radix. (#1340) [George Cuan] * Fix string ?: conditional type resolution. (#1345) [Iztok Jeras] * Fix duplicate symbol error on generate tri. (#1347) [Tomas Dzetkulic] Verilator 3.926 2018-08-22 ========================== **Minor:** * Add OBJCACHE envvar support to examples and generated Makefiles. * Change MODDUP errors to warnings. (#1969) [Marshal Qiao] * Fix define argument stringification (`"), broke since 3.914. [Joe DErrico] * Fix to ignore Unicode UTF-8 BOM sequences. (#1967) [HyungKi Jeong] * Fix std:: build error. (#1322) * Fix function inlining inside certain while loops. (#1330) [Julien Margetts] Verilator 3.924 2018-06-12 ========================== **Minor:** * Renamed --profile-cfuncs to --prof-cfuncs. * Report interface ports connected to wrong interface. (#1294) [Todd Strader] * When tracing, use scalars on single bit arrays to appease vcddiff. * Fix parsing "output signed" in V2K port list, msg2540. [James Jung] * Fix parsing error on bad missing #. (#1308) [Dan Kirkham] * Fix $clog2 to be in verilog 2005. (#1319) [James Hutchinson] Verilator 3.922 2018-03-17 ========================== **Major:** * Support IEEE 1800-2017 as default language. **Minor:** * Support trig functions ($sin() etc). (#1281) [Patrick Stewart] * Support calling system functions as tasks. (#1285) [Joel Holdsworth] * Support assert properties. (#785) (#1290) [John Coiner, et al] * Support $writememh. [John Coiner] * Add --no-debug-leak to reduce memory use under debug. [John Coiner] * Fix severe runtime performance bug in certain foreach loops. [John Coiner] * On convergence errors, show activity. [John Coiner] * Fix GCC 8.0 issues. (#1273) * Fix pullup/pulldowns on bit selects. (#1274) [Rob Stoddard] * Fix verilator_coverage --annotate-min. (#1284) [Tymoteusz Blazejczyk] * Fix quoting of quoted arguments. [John Coiner] Verilator 3.920 2018-02-01 ========================== **Announcement:** * Moving forward, use the git "stable" branch to track the latest release, and git "v#.###" tags for specific releases. **Minor:** * Support 'assume' similar to 'assert'. (#1269) [Dan Gisselquist] * Remove c++filt. (#1265) [Stefan Wallentowitz] * Fix tracing example file output. (#1268) [Enzo Chi] * Fix gate optimization out of memory, add --gate-stmts. (#1260) [Alex Solomatnikov] * Fix compile error on public real parameters by suppressing. (#1261) [Alex Solomatnikov] * Fix input-only tristate comparisons. (#1267) [Alexis G] * Fix missing edge type in xml output. (#1955) [Alexis G] * Fix compile error with --public and interface bind. (#1264) [Alexis G] Verilator 3.918 2018-01-02 ========================== **Minor:** * Workaround GCC/clang bug with huge compile times. (#1248) * Support DPI open arrays. (#909) (#1245) [David Pierce, Victor Besyakov] * Add INFINITELOOP warning. (#1254) [Alex Solomatnikov] * Support > 64 bit decimal $display. * Support DPI time and svLogicVal. [Victor Besyakov] Note older version incorrectly assumed svBitVal even for logicals. * Support string len() method. [Victor Besyakov] * Add error if always_comb has sensitivity list. [Arjen Roodselaar] * Fix SystemC 2.3.2 compile error. (#1251) [Tymoteusz Blazejczyk] * Fix modport outputs being treated as inputs. (#1246) [Jeff Bush] * Fix false ALWCOMBORDER on interface references. (#1247) [Josh Redford] * Fix constant propagation across DPI imports of inout strings. [Victor Besyakov] * Fix resolving inline nested interface names. (#1250) [Arjen Roodselaar] * Fix GCC false warning on array bounds. (#2386) Verilator 3.916 2017-11-25 ========================== **Minor:** * Support self-recursive modules. (#659) [Sean Moore, et al] * Support $error/$warning in elaboration time blocks. * Support $size/$bits/etc on type references. * Add error when driving input-only modport. (#1110) [Trevor Elbourne] * Add BSSPACE and COLONPLUS lint warnings. * Detect MSB overflow when under VL_DEBUG. (#1238) [Junyi Xi] * Add data types to --xml. [Rui Terra] * Fix partial slicing with pattern assignments. (#991) [Johan Bjork] * Fix false unused warning on interfaces. (#1241) [Laurens van Dam] * Fix error on "unique case" with no cases. * Fix MacOS portability. (#1232) [Jeff Bush] Verilator 3.914 2017-10-14 ========================== **Major:** * Add new examples/ directory with appropriate examples. This replaces the old test_c and test_sc directories. **Minor:** * Add --getenv option for simplifying Makefiles. * Add --x-initial option for specifying initial value assignment behavior. * Add --no-relative-cfuncs and related default optimization. (#1224) [John Coiner] * Add /*verilator tag*/ for XML extraction applications. [Chris Randall] * The internal test_verilated test directory is moved to be part of test_regress. * The experimental VL_THREADED setting (only, not normal mode) now requires C++11. * Fix over-aggressive inlining. (#1223) [John Coiner] * Fix Ubuntu 17.10 issues. (#1223 partial). [John Coiner] * Fix compiler warning when WIDTH warning ignored on large compare. * Fix memory leak in VerilatedVcd dumps. (#1222 partial) [Shareef Jalloq] * Fix unnecessary Vdly variables. (#1224 partial) [John Coiner] * Fix conditional slices and add related optimizations. * Fix \`\` expansion of `defines. (#1225) (#1227) (#1228) [Odd Magne Reitan] * Fix -E duplicating output. (#1226) [Odd Magne Reitan] * Fix float-conversion warning. (#1229) [Robert Henry] * Fix MacOS portability. (#1230) (#1231) [Jeff Bush] Verilator 3.912 2017-09-23 ========================== **Major:** * Verilated headers no longer "use namespace std;" User's code without "std::" prefixes may need "use namespace std;" to compile. **Minor:** * Support or/and/xor array intrinsic methods. (#1210) [Michael Popoloski] * Support package export. (#1217) [Usuario Eda] * Support module port parameters without defaults. (#1213) [Michael Popoloski] * Add performance information to --stats file. * Simplify VL_CONST_W macro generation for faster compiles. * Optimize improvements for Shift-And, and replication constructs. * Fix ordering of arrayed cell wide connections. (#1202 partial) [Michael Popoloski] * Fix LITENDIAN warning on arrayed cells. (#1202) [Michael Popoloski] * Fix enum ranges without colons. (#1204) [Michael Popoloski] * Fix GCC noreturn compile error. (#1209) [Michael Popoloski] * Fix constant function default parameters. (#1211) [Michael Popoloski] * Fix non-colon array of interface modports. (#1212) [Michael Popoloski] * Fix .name connections on interfaces. (#1214) [Michael Popoloski] * Fix wide array indices causing compile error. Verilator 3.910 2017-09-07 ========================== **Major:** * SystemPerl mode (-sp-deprecated) has been removed. **Minor:** * Update keyword warnings to include C++11 and others. Verilator 3.908 2017-08-28 ========================== **Minor:** * Support x in $readmem. (#1180) [Arthur Kahlich] * Support packed struct DPI imports. (#1190) [Rob Stoddard] * Fix GCC 6 warnings. * Fix compile error on unused VL_VALUEPLUSARGS_IW. (#1181) [Thomas J Whatson] * Fix undefined VL_POW_WWI. [Clifford Wolf] * Fix internal error on unconnected inouts. (#1187) [Rob Stoddard] Verilator 3.906 2017-06-22 ========================== **Minor:** * Support set_time_unit/set_time_precision in C traces. (#1937) * Fix extract of packed array with non-zero LSB. (#1172) [James Pallister] * Fix shifts by more than 32-bit numbers. (#1174) [Clifford Wolf] * Fix power operator on wide constants. (#761) [Clifford Wolf] * Fix .* on interface pins. (#1176) [Maciej Piechotka] Verilator 3.904 2017-05-30 ========================== **Minor:** * Fix non-cutable ordering loops on clock arrays. (#1009) [Todd Strader] * Support ports of array of reals. (#1154) [J Briquet] * Support arrayed parameter overrides. (#1153) [John Stevenson] * Support $value$plusargs with variables. (#1165) [Wesley Terpstra] * Support modport access to un-modport objects. (#1161) [Todd Strader] * Add stack trace when can't optimize function. (#1158) [Todd Strader] * Add warning on mis-sized literal. (#1156) [Todd Strader] * Fix interface functions returning wrong parameters. (#996) [Todd Strader] * Fix non-arrayed cells with interface arrays. (#1153) [John Stevenson] * Fix --assert with complex case statements. (#1164) [Enzo Chi] Verilator 3.902 2017-04-02 ========================== **Major:** * Add -FI option to force includes. (#1916) [Amir Gonnen] * Add --relative-includes. [Rob Stoddard] **Minor:** * Add error on duplicate pattern assignments. (#1145) [Johan Bjork] * Fix error on improperly widthed default function. (#984) [Todd Strader] * Fix 2009 localparam syntax, msg2139. [Galen Seitz] * Fix ugly interface-to-non-interface errors. (#1112) [Johan Bjork] * Fix LDFLAGS and CFLAGS not preserving order. (#1130) [Olof Kindgren] * Fix internal error on initializing parameter array. (#1131) [Jie Xu] * Fix internal error on interface arrays. (#1135) [John Stevenson] * Fix calling sformatf to display, and elab $displays. (#1139) [Johan Bjork] * Fix realpath compile issue on MSVC++. (#1141) [Miodrag Milanovic] * Fix missing error on interface size mismatch. (#1143) [Johan Bjork] * Fix error on parameters with dotted references. (#1146) [Johan Bjork] * Fix wreal not handling continuous assign. (#1150) [J Briquet] * Fix nested structure parameter selects. (#1150) [J Briquet] Verilator 3.900 2017-01-15 ========================== **Major:** * Internal code changes for improved compatibility and performance. **Minor:** * Support old-style $display($time). (#467) [John Demme] * With --bbox-unsup, suppress desassign and mixed edges. (#1120) [Galen Seitz] * Fix parsing sensitivity with &&. (#934) [Luke Yang] * Fix internal error on double-for loop unrolling. (#1044) [Jan Egil Ruud] * Fix internal error on unique casez with --assert. (#1117) [Enzo Chi] * Fix bad code when tracing array of structs. (#1122) [Andrew Bardsley] Verilator 3.890 2016-11-25 ========================== **Minor:** * Honor --output-split on coverage constructors. (#1098) [Johan Bjork] * Fix various issues when making outside of the kit. * Fix flex 2.6.2 bug. (#1103) [Sergey Kvachonok] * Fix error on bad interface name. (#1097) [Todd Strader] * Fix error on referencing variable in parent. (#1099) [Ian Thompson] * Fix type parameters with low optimization. (#1101) [Stefan Wallentowitz] Verilator 3.888 2016-10-14 ========================== **Major:** * Support foreach. (#1078) [Xuan Guo] **Minor:** * Add --no-decoration to remove output comments, msg2015. [Frédéric Requin] * If VM_PARALLEL_BUILDS=1, use OPT_FAST and OPT_SLOW. [Frédéric Requin] Set VM_DEFAULT_RULES=0 for old behavior. * Add error on DPI functions > 32 bits. (#1898) [Elliot Mednick] * Improve Verilation performance on internal strings. (#1896) [Johan Bjork] * Improve Verilation performance on trace duplicates. (#1090) [Johan Bjork] * Fix SystemC compiles with VPI. (#1081) [Arthur Kahlich] * Fix error on wide numbers that represent shifts, msg1991. (#1088) [Mandy Xu] Verilator 3.886 2016-07-30 ========================== **Minor:** * Fix enum values of 11-16 bits wide using .next/.prev. (#1062) [Brian Flachs] * Fix false warnings on non-power-2 enums using .next/.prev. * Fix comparison of unpacked arrays. (#1071) [Andrew Bardsley] * Fix compiler warning in GCC 6. [David Horton] Verilator 3.884 2016-05-18 ========================== **Major:** * Support parameter type. (#376) [Alan Hunter, et al] * Support command-line -G/+pvalue param overrides. (#1045) [Stefan Wallentowitz] * Add --l2-name option for controlling "v" naming. * The default l2 scope name is now the same as the top-level module. (#1050) Use "--l2-name v" for the historical behavior. **Minor:** * Fix --output-split of constructors. (#1035) [Johan Bjork] * Fix removal of empty packages, modules and cells. (#1034) [Johan Bjork] * Fix core dump on Arch Linux/GCC 6.1.1. (#1058) [Jannis Harder] * Fix $value$plusargs to string. (#1880) [Frédéric Requin] Verilator 3.882 2016-03-01 ========================== **Minor:** * Internal Verilation-time performance enhancements. (#1021) [Johan Bjork] * Support inlining interfaces. (#1018) [Johan Bjork] * Support SV strings to readmemh. (#1040) [Stefan Wallentowitz] * Fix unrolling complicated for-loop bounds. (#677) [Johan Bjork] * Fix stats file containing multiple unroll entries. (#1020) [Johan Bjork] * Fix using short parameter names on negative params. (#1022) [Duraid Madina] * Fix read-after-free error. (#1031) [Johan Bjork] * Fix elaboration-time display warnings. (#1032) [Johan Bjork] * Fix crash on very deep function trees. (#1028) [Jonathan Kimmitt] * Fix slicing mix of big and little-endian. (#1033) [Geoff Barrett] * Fix pattern assignment width propagation. (#1037) [Johan Bjork] Verilator 3.880 2015-12-19 ========================== **Minor:** * Support display %u, %v, %p, %z. (#989) [Johan Bjork] * Fix real parameters causing bad module names. (#992) [Johan Bjork] * Fix size-changing cast on packed struct. (#993) [Johan Bjork] * Fix function calls on arrayed interface. (#994) [Johan Bjork] * Fix arrayed interfaces. (#879) (#1001) [Todd Strader] * Fix constant function assigned to packed structs. (#997) [Johan Bjork] * Fix interface inside generate. (#998) [Johan Bjork] * Fix $signed casts under generates. (#999) [Clifford Wolf] * Fix genvar constant propagation. (#1003) [Johan Bjork] * Fix parameter constant propagation from package. (#1004) [Johan Bjork] * Fix array slicing of non-const indexes. (#1006) [Johan Bjork] * Fix dotted generated array error. (#1005) [Jeff Bush, Johan Bjork] * Fix error instead of warning on large concat. (#1865) [Paul Rolfe] * Fix $bitstoreal constant propagation. (#1012) [Jonathan Kimmitt] * Fix model restore crash. (#1013) [Jason McMullan] * Fix arrayed instances to unpacked of same size. (#1015) [Varun Koyyalagunta] * Fix slices of unpacked arrays with non-zero LSBs. * Fix ternary operation with unpacked array. (#1017) [Varun Koyyalagunta]. Verilator 3.878 2015-11-01 ========================== **Major:** * Add --vpi flag, and fix VPI linkage. (#969) [Arthur Kahlich] * Support genvar indexes into arrayed cells. (#517) [Todd Strader] * Support $sformatf. (#977) [Johan Bjork] * Support elaboration assertions. (#973) [Johan Bjork] * Support $display with non-format arguments. (#467) [Jamey Hicks] **Minor:** * Add VerilatedScopeNameMap for introspection. (#966) [Todd Strader] * Ignore %l in $display. (#983) [Todd Strader] * Fix very long module names. (#937) [Todd Strader] * Fix internal error on dotted refs into generates. (#958) [Jie Xu] * Fix structure parameter constant propagation. (#968) [Todd Strader] * Fix enum constant propagation. (#970) [Todd Strader] * Fix mis-optimizing public DPI functions. (#963) [Wei Song] * Fix package:scope.scope variable references. * Fix $fwrite to constant stderr/stdout. (#961) [Wei Song] * Fix struct.enum.name method calls. (#855) [Jonathon Donaldson] * Fix dot indexing into arrayed inferfaces. (#978) [Johan Bjork] * Fix crash in commandArgsPlusMatch. (#987) [Jamie Iles] * Fix error message on missing interface. (#985) [Todd Strader] Verilator 3.876 2015-08-12 ========================== **Minor:** * Add tracing_on, etc to vlt files. (#932) [Frédéric Requin] * Support extraction of enum bits. (#951) [Jonathon Donaldson] * Fix MinGW compiler error. (#927) (#929) [Hans Tichelaar] * Fix .c files to be treated as .cpp. (#930) [Jonathon Donaldson] * Fix string-to-int space conversion. (#931) [Fabrizio Ferrandi] * Fix dpi imports inside generates. [Michael Tresidder] * Fix rounding in trace $timescale. (#946) [Frédéric Requin] * Fix $fopen with SV string. (#947) [Sven Stucki] * Fix hashed error with typedef inside block. (#948) [Sven Stucki] * Fix makefile with --coverage. (#953) [Eivind Liland] * Fix coverage documentation. (#954) [Thomas J Whatson] * Fix parameters with function parameter arguments. (#952) [Jie Xu] * Fix size casts as second argument of cast item. (#950) [Jonathon Donaldson] Verilator 3.874 2015-06-06 ========================== **Minor:** * Add pkg-config .pc file. (#919) [Stefan Wallentowitz] * Fix installing missing manpages. (#908) [Ahmed El-Mahmoudy] * Fix sign extension in large localparams. (#910) [Mike Thyer] * Fix core dump in sync-async warnings. (#911) [Sebastian Dressler] * Fix truncation warning with -pins-bv. (#912) [Alfonso Martinez] * Fix Cygwin uint32 compile. (#914) [Matthew Barr] * Fix preprocessing stringified newline escapes. (#915) [Anton Rapp] * Fix part-select in constant function. (#916) [Andrew Bardsley] * Fix width extension on mis-width ports. (#918) [Patrick Maupin] * Fix width propagation on sized casts. (#925) [Jonathon Donaldson] * Fix MSVC++ compiler error. (#927) [Hans Tichelaar] Verilator 3.872 2015-04-05 ========================== **Minor:** * Add VerilatedVcdFile to allow real-time waveforms. (#890) [HyungKi Jeong] * Add --clk and related optimizations. (#1840) [Jie Xu] * Fix order of C style arrays. [Duraid Madina] * Add --dump-treei-. (#894) [Jie Xu] * Fix comma-instantiations with parameters. (#884) [Franck Jullien] * Fix SystemC arrayed bit vectors. (#886) [David Poole] * Fix compile error on MinGW. (#887) [HyungKi Jeong] Verilator 3.870 2015-02-12 ========================== **Minor:** * Suppress COMBDLY when inside always_latch. (#864) [Iztok Jeras] * Support cast operator with expression size. (#865) [Iztok Jeras] * Add warning on slice selection out of bounds. (#875) [Cong Van Nguyen]. * Fix member select error broke in 3.868. (#867) [Iztok Jeras] * Fix $sccanf from string. (#866) [David Pierce] * Fix VM_PARALLEL_BUILDS broke in 3.868. (#870) [Hiroki Honda] * Fix non-ANSI modport instantiations. (#868) [Kevin Thompson] * Fix UNOPTFLAT change detect on multidim arrays. (#872) [Andrew Bardsley] * Fix slice connections of arrays to ports. (#880) [Varun Koyyalagunta] * Fix mis-optimizing gate assignments in unopt blocks. (#881) [Mike Thyer] * Fix sign extension of pattern members. (#882) [Iztok Jeras] * Fix clang compile warnings. Verilator 3.868 2014-12-20 ========================== **Major:** * New verilator_coverage program added to replace SystemPerl's vcoverage. * PSL support was removed, please use System Verilog assertions. * SystemPerl mode is deprecated and now untested. **Minor:** * Support enum.first/name and similar methods. (#460) (#848) * Add 'string' printing and comparisons. (#746) (#747) etc. * Inline C functions that are used only once. (#1838) [Jie Xu] * Fix tracing SystemC signals with structures. (#858) [Eivind Liland] Note that SystemC traces will no longer show the signals in the wrapper, they can be seen one level further down. * Add --stats-vars. (#851) [Jeremy Bennett] * Fix bare generates in interfaces. (#789) [Bob Newgard] * Fix underscores in real literals. (#863) [Jonathon Donaldson] Verilator 3.866 2014-11-15 ========================== **Minor:** * Fix +define+A+B to define A and B to match other simulators. (#847) [Adam Krolnik] * Add optimization of wires from arrayed cells. (#1831) [Jie Xu] * Add optimization of operators between concats. (#1831) [Jie Xu] * Add public enums. (#833) [Jonathon Donaldson] * Trace_off now operates on cells. (#826) [Lane Brooks] * Fix public parameters in unused packages. (#804) [Jonathon Donaldson] * Fix select when partially out-of-bound. (#823) [Clifford Wolf] * Fix generate unrolling with function call. (#830) [Steven Slatter] * Fix cast-to-size context-determined sizing. (#828) [Geoff Barrett] * Fix not tracing modules following primitives. (#837) [Jie Xu] * Fix trace overflow on huge arrays. (#834) [Geoff Barrett] * Fix quoted comment slashes in defines. (#845) [Adam Krolnik] Verilator 3.864 2014-09-21 ========================== **Minor:** * Support power operator with real. (#809) [Jonathon Donaldson] * Improve verilator_profcfunc time attributions. [Jonathon Donaldson] * Fix duplicate anonymous structures in $root. (#788) [Bob Newgard] * Fix mis-optimization of bit-swap in wide signal. (#800) [Jie Xu] * Fix error when tracing public parameters. (#722) [Jonathon Donaldson] * Fix dpiGetContext in dotted scopes. (#740) [Geoff Barrett] * Fix over-shift structure optimization error. (#803) [Jeff Bush] * Fix optional parameter keyword in module #(). (#810) [Iztok Jeras] * Fix $warning/$error multi-argument ordering. (#816) [Jonathon Donaldson] * Fix clang warnings. (#818) [Iztok Jeras] * Fix string formats under deep expressions. (#820) [Iztok Jeras] Verilator 3.862 2014-06-10 ========================== **Minor:** * Using command line -Wno-{WARNING} now overrides file-local lint_on. * Add -P to suppress `line and blanks with preprocessing. (#781) [Derek Lockhart] * Support SV 2012 package import before port list. * Change SYMRSVDWORD to print as warning rather than error. * Fix seg-fault with variable of parameterized interface. (#692) [Jie Xu] * Fix false name conflict on cells in generate blocks. (#749) [Igor Lesik] * Fix pattern assignment to basic types. (#767) [Jie Xu] * Fix pattern assignment to conditionals. (#769) [Jie Xu] * Fix shift corner-cases. (#765) (#766) (#768) (#772) (#774) (#776) [Clifford Wolf] * Fix C compiler interpreting signing. (#773) [Clifford Wolf] * Fix late constant division by zero giving X error. (#775) [Clifford Wolf] * Fix gate primitives with arrays and non-arrayed pins. * Fix DETECTARRAY error on packed arrays. (#770) [Jie Xu] * Fix ENDLABEL warnings on escaped identifiers. * Fix string corruption. (#780) [Derek Lockhart] Verilator 3.860 2014-05-11 ========================== **Major:** * PSL is no longer supported, please use System Verilog assertions. * Support '{} assignment pattern on arrays. (#355) * Support streaming operators. (#649) [Glen Gibb] * Fix expression problems with -Wno-WIDTH. (#729) (#736) (#737) (#759) Where WIDTH warnings were ignored this might result in different warning messages and results, though it should better match the spec. [Clifford Wolf] **Minor:** * Add --no-trace-params. * Add assertions on 'unique if'. (#725) [Jeff Bush] * Add PINCONNECTEMPTY warning. [Holger Waechtler] * Support parameter arrays. (#683) [Jeremy Bennett] * Documentation fixes. (#723) [Glen Gibb] * Support {} in always sensitivity lists. (#745) [Igor Lesik] * Fix begin_keywords "1800+VAMS". (#1806) * Fix tracing of package variables and real arrays. * Fix tracing of packed arrays without --trace-structs. (#742) [Jie Xu] * Fix missing coverage line on else-if. (#727) [Sharad Bagri] * Fix modport function import not-found error. * Fix power operator calculation. (#730) (#735) [Clifford Wolf] * Fix reporting struct members as reserved words. (#741) [Chris Randall] * Fix change detection error on unions. (#758) [Jie Xu] * Fix -Wno-UNOPTFLAT change detection with 64-bits. (#762) [Clifford Wolf] * Fix shift-right optimization. (#763) [Clifford Wolf] * Fix Mac OS-X test issues. [Holger Waechtler] * Fix C++-2011 warnings. Verilator 3.856 2014-03-11 ========================== **Minor:** * Support case inside. (#708) [Jan Egil Ruud] * Add parameters into trace files. (#706) [Alex Solomatnikov] * Fix parsing "#0 'b0". (#256) * Fix array bound checks on real variables. * Fix --skip-identical mis-detecting on OS-X. (#707) * Fix missing VL_SHIFTRS_IQI with WIDTH warning. (#714) [Fabrizio Ferrandi] * Fix signed shift right optimization. (#715) [Fabrizio Ferrandi] * Fix internal error on "input x =" syntax error. (#716) [Lane Brooks] * Fix slice extraction from packed array. (#717) [Jan Egil Ruud] * Fix inside statement EQWILD error. (#718) [Jan Egil Ruud] Verilator 3.855 2014-01-18 ========================== **Minor:** * Support modport import. (#696) [Jeremy Bennett] * Add --trace-structs to show struct names. (#673) [Chris Randall] * Fix tracing of packed structs. (#705) [Jie Xu] * Fix --lint-only with MinGW. (#1813) [HyungKi Jeong] * Fix some delayed assignments of typedefed unpacked arrays. * Fix wire declarations with size and not range. (#466) [Alex Solomatnikov] * Fix parameter pin vs. normal pin error. (#704) [Alex Solomatnikov] Verilator 3.854 2013-11-26 ========================== **Minor:** * Add UNPACKED warning to convert unpacked structs. [Jeremy Bennett] * Add --compiler clang to work around compiler bug. (#694) [Stefan Ludwig] * Support vpi_get of vpiSuppressVal. (#687) [Varun Koyyalagunta] * Support vpi_get_time. (#688) [Varun Koyyalagunta] * Fix evaluation of chained parameter functions. (#684) [Ted Campbell] * Fix enum value extension of '1. * Fix multiple VPI variable callbacks. (#679) [Rich Porter] * Fix vpi_get of vpiSize. (#680) [Rich Porter] * Fix vpi_remove_cb inside callback. (#689) [Varun Koyyalagunta] * Fix crash with coverage of structures. (#691) [Eivind Liland] * Fix array assignment from const var. (#693) [Jie Xu] Verilator 3.853 2013-09-30 ========================== **Minor:** * Add --no-order-clock-delay to work around #613. [Charlie Brej] Verilator 3.852 2013-09-29 ========================== **Minor:** * Support named function and task arguments. [Chris Randall] * Report SELRANGE warning for non-generate if. (#675) [Roland Kruse] * Fix ordering of $fgetc. (#1808) [Frédéric Requin] * Fix --output-split-cfunc to count internal functions. [Chris Randall] * Fix crash on 32-bit Ubuntu. (#670) [Mark Jackson Pulver] Verilator 3.851 2013-08-15 ========================== **Minor:** * Fix ordering of clock enables with delayed assigns. (#613) [Jeremy Bennett] * Fix vpi_iterate on memory words. (#655) [Rich Porter] * Fix final duplicate declarations when non-inlined. (#661) [Charlie Brej] * Fix interface ports with comma lists. (#1779) [Ed Lander] * Fix parameter real conversion from integer. * Fix clang warnings. (#668) [Yutetsu Takatsukasa] Verilator 3.850 2013-06-02 ========================== **Major:** * Support interfaces and modports. (#102) [Byron Bradley, Jeremy Bennett] **Minor:** * Duplicate clock gate optimization on by default. (#621) * Fix arrayed input compile error. (#645) [Krzysztof Jankowski] * Fix GCC version runtime changes. (#651) [Jeremy Bennett] * Fix packed array select internal error. (#652) [Krzysztof Jankowski] Verilator 3.847 2013-05-11 ========================== **Minor:** * Add ALWCOMBORDER warning. [KC Buckenmaier] * Add --pins-sc-uint and --pins-sc-biguint. (#638) [Alex Hornung] * Support "signal[vec]++". * Fix simulation error when inputs and MULTIDRIVEN. (#634) [Ted Campbell] * Fix module resolution with __. (#631) [Jason McMullan] * Fix packed array non-zero right index select crash. (#642) [Krzysztof Jankowski] * Fix nested union crash. (#643) [Krzysztof Jankowski] Verilator 3.846 2013-03-09 ========================== **Major:** * IEEE 1800-2012 is now the default language. This adds 4 new keywords and updates the svdpi.h and vpi_user.h header files. * Add --report-unoptflat. (#611) [Jeremy Bennett] **Minor:** * Add duplicate clock gate optimization. (#1772) [Varun Koyyalagunta] Disabled unless -OD or -O3 used, please try it as may get some significant speedups. * Support pattern assignment features. (#616) (#617) (#618) [Ed Lander] * Support bind in $unit. (#602) [Ed Lander] * Support '() sized casts. (#628) [Ed Lander] * Fix wrong dot resolution under inlining. [Art Stamness] * Fix DETECTARRAY on packed structures. (#610) [Jeremy Bennett] * Fix LITENDIAN on unpacked structures. (#614) [Wai Sum Mong] * Fix 32-bit OS VPI scan issue. (#615) [Jeremy Bennett, Rich Porter] * Fix opening a VerilatedVcdC file multiple times. (#1774) [Frédéric Requin] * Fix UNOPTFLAT circular array bounds crossing. (#630) [Jie Xu] Verilator 3.845 2013-02-04 ========================== **Minor:** * Fix nested packed arrays and struct. (#600) [Jeremy Bennett] Packed arrays are now represented as a single linear vector in Verilated models. This may affect packed arrays that are public or accessed via the VPI. * Support wires with data types. (#608) [Ed Lander] * Support bind, to module names only. (#602) [Ed Lander] * Support VPI product info, warning calls, etc. (#588) [Rick Porter] * Support $left, $right and related functions. (#448) [Iztok Jeras] * Support inside expressions. * Define SYSTEMVERILOG, SV_COV_START and other IEEE mandated predefines. * Fix pin width mismatch error. (#595) [Alex Solomatnikov] * Fix implicit one bit parameter selection. (#603) [Jeremy Bennett] * Fix signed/unsigned parameter misconversion. (#606) [Jeremy Bennett] * Fix segfault on multidimensional dotted arrays. (#607) [Jie Xu] * Fix per-bit array output connection error. (#414) [Jan Egil Ruud] * Fix package logic var compile error. * Fix enums with X values. Verilator 3.844 2013-01-09 ========================== **Minor:** * Support "unsigned int" DPI import functions. (#1770) [Alex Lee] * Fix package resolution of parameters. (#586) [Jeremy Bennett] * Fix non-integer vpi_get_value. (#587) [Rich Porter] * Fix task inlining under $display and case. (#589) (#598) [Holger Waechtler] * Fix package import of non-localparam parameter. (#474) (#591) [Jeremy Bennett] * Fix package import of package imports, partial #592. [Jeremy Bennett] * Fix package import preventing local var. (#599) [Jeremy Bennett] * Fix array extraction of implicit vars. (#601) [Joe Eiler] Verilator 3.843 2012-12-01 ========================== **Minor:** * Add +1364-1995ext and similar language options. (#532) [Jeremy Bennett] * Fix mis-optimized identical submodule subtract. (#581) [Charlie Brej] * Fix crash on dotted references into dead modules. (#583) [Jeremy Bennett] * Fix compile issues on MSVCC. (#571) (#577) [Amir Gonnen] * Fix --debug overriding preceding --dump-treei. (#580) [Jeremy Bennett] Verilator 3.842 2012-11-03 ========================== **Minor:** * Add -x-initial-edge. (#570) [Jeremy Bennett] * Fix parameter pins interspersed with cells broke in 3.840. [Bernard Deadman] * Fix large shift error on large shift constants. [David Welch] * Fix $display mangling on GCC 4.7 and speed up. (#1765) (#373) (#574) [R Diez] * Fix array of struct references giving false error. (#566) [Julius Baxter] * Fix missing var access functions when no DPI. (#572) [Amir Gonnen] * Fix name collision on unnamed blocks. (#567) [Chandan Egbert] * Fix name collision on task inputs. (#569) [Chandan Egbert] Verilator 3.841 2012-09-03 ========================== **Major:** * Add --savable to support model save/restore. [Jeremy Bennett] **Minor:** * Support '{} assignment pattern on structures, part of #355. * Fix double-deep parameter cell WIDTHs. (#541) [Hiroki Honda] * Fix imports under multiple instantiated cells. (#542) [Alex Solomatnikov] * Fix defparam in generate broke in 3.840. (#543) [Alex Solomatnikov] * Fix duplicate begin error broke in 3.840. (#548) [Alex Solomatnikov] * Fix triangle symbol resolution error broke in 3.840. (#550) [Ted Campbell] Verilator 3.840 2012-07-31 Beta =============================== **Major:** * Rewrote tristate handling; supports tri0, tri1, tristate bit selects, concatenates and pullup/pulldowns. (#395) (#56) (#54) (#51) [Alex Solomatnikov, Lane Brooks, et al] * Support packed structures and unions. (#181) Note this was a major internal change that may lead to some instability. **Minor:** * Support tri0 and tri1. (#462) [Alex Solomatnikov] * Support nmos and pmos. (#488) [Alex Solomatnikov] * Add INITIALDLY warning on initial assignments. (#478) [Alex Solomatnikov] * Add PINMISSING and PINNOCONNECT lint checks. * Add --converge-limit option. * Fix generate operators not short circuiting. (#413) [by Jeremy Bennett] * Fix parameters not supported in constant functions. (#474) [Alex Solomatnikov] * Fix duplicate warnings/errors. (#516) [Alex Solomatnikov] * Fix signed extending biops with WIDTH warning off. (#511) [Junji Hashimoto] * Fix ITOD internal error on real conversions. (#491) [Alex Solomatnikov] * Fix input and real loosing real data type. (#501) [Alex Solomatnikov] * Fix imports causing symbol table error. (#490) [Alex Solomatnikov] * Fix newlines in radix values. (#507) [Walter Lavino] * Fix loop error message to report line. (#513) [Jeremy Bennett] * Fix false UNUSED warning on file system calls. * Fix GCC 4.7.0 compile warnings. (#530) [Jeremy Bennett] * Fix svdpi.h compile error on Apple OS. * Fix compile error under git submodules. (#534) [Aurelien Francillon] Verilator 3.833 2012-04-15 ========================== **Minor:** * Support += and -= in standard for loops. (#463) [Alex Solomatnikov] * Fix processing unused parameterized modules. (#469) (#470) [Alex Solomatnikov] * Add SELRANGE as warning instead of error. (#477) [Alex Solomatnikov] * Add readme.pdf and internal.pdf and doxygen. (#483) [by Jeremy Bennett] * Fix change detections on arrays. (#364) [John Stevenson, Alex Solomatnikov] * Fix signed array warning. (#456) [Alex Solomatnikov] * Fix genvar and begin under generate. (#461) [Alex Solomatnikov] * Fix real constant parameter functions. (#475) [Alex Solomatnikov] * Fix and document --gdb option. (#454) [Jeremy Bennett] * Fix OpenSolaris compile error. [Sanjay Singh] Verilator 3.832 2012-03-07 ========================== **Minor:** * Fix memory delayed assignments from multiple clock domains. [Andrew Ling] * Support arrayed SystemC I/O pins. [Christophe Joly] * Report MULTIDRIVEN on memories set in multiple clock domains. * Report ENDLABEL on mismatching end labels. (#450) [Iztok Jeras] * Fix expansion of back-slashed escaped macros. (#441) [Alberto Del Rio] * Fix inheriting real and signed type across untyped parameters. * Fix core dump with over 100 deep UNOPTFLAT. (#432) [Joe Eiler] * Fix false command not found warning in makefiles. [Ruben Diez] * Fix hang when functions inside begin block. [David Welch] * Fix hang on recursive substitution `defines. (#443) [Alex Solomatnikov] Verilator 3.831 2012-01-20 ========================== **Major:** * Support SystemC 2.3.0 prerelease. This requires setting the new SYSTEMC_INCLUDE and SYSTEMC_LIBDIR variables in place of now deprecated SYSTEMC and SYSTEMC_ARCH. [Iztok Jeras] **Minor:** * Suppress VARHIDDEN on dpi import arguments. [Ruben Diez] * Support "generate for (genvar i=0; ...". [David Kravitz] * Fix dpi exports with > 32 bit but < 64 bit args. (#423) [Chandan Egbert] * Fix array of instantiations with sub-range output. (#414) [Jeremy Bennett] * Fix BLKSEQ warnings on variables declared inside always. [Ruben Diez] Verilator 3.830 2011-11-27 ========================== **Major:** * With "--language VAMS" support a touch of Verilog AMS. [Holger Waechtler] **Minor:** * Add sc_bv attribute to force bit vectors. (#402) [by Stefan Wallentowitz] * Search for user -y paths before default current directory. [Ruben Diez] * Support constants in sensitivity lists. (#412) [Jeremy Bennett] * Support $system. [Ruben Diez] * Support $sscanf with %g. [Holger Waechtler] * Indicate 'exiting due to errors' if errors, not warnings. [Ruben Diez] * Fix bad result with if-else-return optimization. (#420) [Alex Solomatnikov] * Fix reporting not found modules if generate-off. (#403) [Jeremy Bennett] * Fix $display with %d following %g. [Holger Waechtler] Verilator 3.824 2011-10-25 ========================== **Minor:** * Fix "always @ (* )". (#403) (#404) [Walter Lavino] * Add ASSIGNIN as suppressible error. [Jeremy Bennett] * Fix 3.823 constructor core dump on Debian. (#401) [Ahmed El-Mahmoudy] Verilator 3.823 2011-10-20 ========================== **Minor:** * Support $ceil, $floor, etc. [Alex Solomatnikov] * Add configure options for cc warnings and extended tests. [Ruben Diez] * Add -Wall reporting ASSIGNDLY on assignment delays. [Ruben Diez] * Fix UNDRIVEN warnings inside DPI import functions. [Ruben Diez] * Fix --help output to go to stderr, not stdout. (#397) [Ruben Diez] * Fix DPI import output of 64 bits. (#398) [Mike Denio] * Fix DPI import false BLKSEQ warnings. [Alex Solomatnikov] * Fix MSVC compile warning with trunc/round. (#394) [Amir Gonnen] * Fix autoconf and Makefile warnings. (#396) [Ruben Diez] Verilator 3.821 2011-09-14 ========================== **Minor:** * Fix PowerPC runtime error. (#288) [Ahmed El-Mahmoudy] * Fix internal error on integer casts. (#374) [Chandan Egbert] Verilator 3.820 2011-07-28 ========================== **Minor:** * Support 'real' numbers and related functions. * Support 'const' variables in limited cases; similar to enums. [Alex Solomatnikov] * Support disable for loop escapes. * Support $fopen and I/O with integer instead of `verilator_file_descriptor. * Support coverage in -cc and -sc output modes. [John Li] Note this requires SystemPerl 1.338 or newer. * Use 'vluint64_t' for SystemC instead of (same sized) 'uint64' for MSVC++. * Fix vpi_register_cb using bad s_cb_data. (#370) [by Thomas Watts] * Fix $display missing leading zeros in %0d. (#367) [Alex Solomatnikov] Verilator 3.813 2011-06-28 ========================== **Minor:** * Support bit vectors > 64 bits wide in DPI import and exports. * Fix out of memory on slice syntax error. (#354) [Alex Solomatnikov] * Fix error on enum references to other packages. (#339) [Alex Solomatnikov] * Fix DPI undeclared svBitVecVal compile error. (#346) [Chandan Egbert] * Fix DPI bit vector compile errors. (#347) (#359) [Chandan Egbert] * Fix CDCRSTLOGIC report showing endpoint flops without resets. * Fix compiler warnings on SPARC. (#288) [Ahmed El-Mahmoudy] Verilator 3.812 2011-04-06 ========================== **Minor:** * Add --trace-max-width and --trace-max-array. (#319) [Alex Solomatnikov] * Add --Wno-fatal to turn off abort on warnings. [by Stefan Wallentowitz] * Support ${...} and $(...) env vars in .vc files. [by Stefan Wallentowitz] * Support $bits(data_type). (#327) [Alex Solomatnikov] * Support loop unrolling on width mismatches. (#333) [Joe Eiler] * Support simple cast operators. (#335) [Alex Solomatnikov] * Accelerate bit-selected inversions. * Add error on circular parameter definitions. (#329) [Alex Solomatnikov] * Fix concatenates and vectored bufif1. (#326) [Iztok Jeras] Verilator 3.811 2011-02-14 ========================== **Minor:** * Report error on duplicated or empty pins. (#321) [Christian Leber] * Report error on function call output tied to constant. [Bernard Deadman] * Throw UNUSED/UNDRIVEN only once per net in a parameterized module. * Fix internal error on functions called as SV tasks. [Bernard Deadman] * Fix internal error on non-inlined inout pins. [Jeff Winston] * Fix false BLKSEQ on non-unrolled for loop indexes. [Jeff Winston] * Fix block comment not separating identifiers. (#311) [Gene Sullivan] * Fix warnings to point to lowest net usage, not upper level ports. * Fix error on constants connected to outputs. (#323) [Christian Leber] Verilator 3.810 2011-01-03 ========================== **Major:** * Add limited support for VPI access to public signals, see docs. * Add -F option to read relative option files. (#297) [Neil Hamilton] * Support ++,--,+= etc as standalone statements. [Alex Solomatnikov] * Add -Wall, -Wwarn-style, -Wno-style to enable code style warnings that have been added to this release, and disabled by default: * With --Wall, add BLKSEQ warning on blocking assignments in seq blocks. * With --Wall, add DECLFILENAME warning on modules not matching filename. * With --Wall, add DEFPARAM warning on deprecated defparam statements. * With --Wall, add IFDEPTH warning on deep if statements. * With --Wall, add INCABSPATH warning on `include with absolute paths. * With --Wall, add SYNCASYNCNET warning on mixed sync/async reset nets. * With --Wall, add UNDRIVEN warning on undriven nets. * With --Wall, add UNUSED warning on unused nets. **Minor:** * When running with VERILATOR_ROOT, optionally find binaries under bin. * Suppress WIDTH warnings when adding/subtracting 1'b1. * The VARHIDDEN warning is now disabled by default, use -Wall to enable. Verilator 3.805 2010-11-02 ========================== **Minor:** * Add warning when directory contains spaces. (#1705) [Salman Sheikh] * Fix wrong filename on include file errors. (#289) [Brad Parker] * Fix segfault on SystemVerilog "output wire foo=0". (#291) [Joshua Wise] * Fix DPI export name not found. (#1703) [Terry Chen] Verilator 3.804 2010-09-20 ========================== **Minor:** * Support tracing/coverage of underscore signals. (#280) [by Jason McMullan] * Increase define recursions before error. [Paul Liu] * On core dump, print debug suggestions. * Fix preprocessor \`\` of existing base define. (#283) [Usha Priyadharshini] Verilator 3.803 2010-07-10 ========================== **Minor:** * Fix preprocessor preservation of newlines across macro substitutions. * Fix preprocessor stringification of nested macros. * Fix some constant parameter functions causing crash. (#253) [Nick Bowler] * Fix do {...} while() not requiring final semicolon. Verilator 3.802 2010-05-01 ========================== **Minor:** * Support runtime access to public signal names. * Add /*verilator public_flat_rw*/ for timing-specific public access. * Fix word size to match uint64_t on -m64 systems. (#238) [Joe Eiler] * Improve error handling on slices of arrays. (#226) [by Byron Bradley] * Report errors when extra underscores used in meta-comments. * Fix bit reductions on multi-packed dimensions. (#227) [by Byron Bradley] * Fix removing $fscanf if assigned to unused var. (#248) [Ashutosh Das] * Fix "make install" with configure outside srcdir. [Stefan Wallentowitz] * Fix loop unroller out of memory; change --unroll-stmts. [Ashutosh Das] * Fix trace files with empty modules crashing some viewers. * Fix parsing single files > 2GB. [Jeffrey Short] * Fix installing data files as non-executable. (#168) [by Ahmed El-Mahmoudy] Verilator 3.801 2010-03-17 ========================== **Minor:** * Support "break", "continue", "return". * Support "`default_nettype none|wire". [Dominic Plunkett] * Skip SystemC tests if not installed. [Iztok Jeras] * Fix clock-gates with non-AND complex logic. (#220) [Ashutosh Das] * Fix flushing VCD buffers on $stop. [Ashutosh Das] * Fix Mac OS-X compile issues. (#217) [Joshua Wise, Trevor Williams] * Fix make uninstall. (#216) [Iztok Jeras] * Fix parameterized defines with empty arguments. Verilator 3.800 2010-02-07 ========================== **Major application visible changes:** * SystemPerl is no longer required for tracing. Applications must use VerilatedVcdC class in place of SpTraceVcdC. * SystemVerilog 1800-2009 is now the default language. Thus "global" etc are now keywords. See the --language option. **Major new features:** * Support SystemVerilog types "byte", "chandle", "int", "longint", "shortint", "time", "var" and "void" in variables and functions. * Support "program", "package", "import" and $unit. * Support typedef and enum. [by Donal Casey] * Support direct programming interface (DPI) "import" and "export". Includes an extension to map user $system PLI calls to the DPI. * Support assignments of multidimensional slices. (#170) [by Byron Bradley] * Support multidimensional inputs/outputs. (#171) [by Byron Bradley] * Support "reg [1:0][1:0][1:0]" and "reg x [3][2]". (#176) [Byron Bradley] * Support declarations in loop initializers. (#172) [by Byron Bradley] * Support $test$plusargs and $value$plusargs, but see the docs! * Support $sformat and $swrite. * Support 1800-2009 define defaults and `undefineall. * Add -CFLAGS, -LDFLAGS, .a, .o, and .so options. * Speed compiles by avoiding including the STL iostream header. Application programs may need to include it themselves to avoid errors. * Add experimental clock domain crossing checks. * Add experimental --pipe-filter to filter all Verilog input. * Add experimental config files to filter warnings outside of the source. * Add VARHIDDEN warning when signal name hides module name. * Support optional cell parenthesis. (#179) [by Byron Bradley] * Support for-loop i++, ++i, i--, --i. (#175) [by Byron Bradley] * Support 1800-2009 /*comments*/ in define values. * Add Makefile VM_GLOBAL_FAST, listing objects needed to link executables. * Add --bbox-unsup option to black-box unsupported UDP tables. * Add -Wno-MODDUP option to allow duplicate modules. **Bug fixes:** * Fix implicit variable issues. (#196) (#201) [Byron Bradley] * Fix 'for' variable typing. (#205) [by Byron Bradley] * Fix tracing with --pins-bv 1. (#195) [Michael S] * Fix MSVC++ 2008 compile issues. (#209) [Amir Gonnen] * Fix MinGW compilation. (#184) (#214) [by Shankar Giri, Amir Gonnen] * Fix Cygwin 1.7.x compiler error with uint32_t. (#204) [Ivan Djordjevic] * Fix `define argument mis-replacing system task of same name. (#191) * Fix Verilator core dump on wide integer divides. (#178) [Byron Bradley] * Fix lint_off/lint_on meta comments on same line as warning. Verilator 3.720 2009-10-26 ========================== **Major:** * Support little endian bit vectors ("reg [0:2] x;"). * Support division and modulus of > 64 bit vectors. [Gary Thomas] **Minor:** * Fix writing to out-of-bounds arrays writing element 0. * Fix core dump with SystemVerilog var declarations under unnamed begins. * Fix VCD files showing internal flattened hierarchy, broke in 3.714. * Fix cell port connection to unsized integer causing false width warning. * Fix erroring on strings with backslashed newlines. (#168) [Pete Nixon] Verilator 3.714 2009-09-18 ========================== **Major:** * Add --bbox-sys option to blackbox $system calls. **Minor:** * Support generate for var++, var--, ++var, --var. * Improved warning when "do" used as identifier. * Don't require SYSTEMPERL_INCLUDE if SYSTEMPERL/src exists. [Gary Thomas] * Fix deep defines causing flex scanner overflows. [Brad Dobbie] * Fix preprocessing commas in deep parameterized macros. [Brad Dobbie] * Fix tracing escaped dotted identifiers. (#107) * Fix $display with uppercase %M. * Fix --error-limit option being ignored. Verilator 3.713 2009-08-04 ========================== **Minor:** * Support constant function calls for parameters. [many!] * Support SystemVerilog "logic". (#101) [by Alex Duller] * Name SYMRSVDWORD error, and allow disabling it. (#103) [Gary Thomas] * Fix escaped preprocessor identifiers. (#106) [Nimrod Gileadi] Verilator 3.712 2009-07-14 ========================== **Major:** * Patching SystemC is no longer required to trace sc_bvs. **Minor:** * Add verilator --pins-uint8 option to use sc_in. * Add verilator -V option, to show verbose version. * Add BLKLOOPINIT error code, and describe --unroll-count. [Jeff Winston] * Support zero-width constants in concatenations. [Jeff Winston] * On WIDTH warnings, show variable name causing error. [Jeff Winston] Verilator 3.711 2009-06-23 ========================== **Minor:** * Support decimal constants of arbitrary widths. [Mark Marshall] * Fix error on case statement with all duplicate items. (#99) [Gary Thomas] * Fix segfault on unrolling for's with bad inits. (#90) [Andreas Olofsson] * Fix tristates causing "Assigned pin is neither...". [by Lane Brooks] * Fix compiler errors under Fedora release candidate 11. [Chitlesh Goorah] Verilator 3.710 2009-05-19 ========================== **Major:** * Verilator is now licensed under LGPL v3 and/or Artistic v2.0. **Minor:** * `__FILE__ now expands to a string, per draft SystemVerilog 2010(ish). * The front end parser has been re-factored to enable more SV parsing. Code should parse the same, but minor parsing bugs may pop up. * Verilator_includer is no longer installed twice. (#48) [Lane Brooks] * Fix escaped identifiers with '.' causing conflicts. (#83) [J Baxter] * Fix define formal arguments that contain newlines. (#84) [David A] Verilator 3.703 2009-05-02 ========================== **Minor:** * Fix $clog2 calculation error with powers-of-2. (#81) [Patricio Kaplan] * Fix error with tasks that have output first. (#78) [Andrea Foletto] * Fix "cloning" error with -y/--top-module. (#76) [Dimitris Nalbantis] * Fix segfault with error on bad --top-module. (#79) [Dimitris Nalbantis] * Fix "redefining I" error with complex includes. [Duraid Madina] * Fix GCC 4.3.2 compile warnings. Verilator 3.702 2009-03-28 ========================== **Minor:** * Add --pins-bv option to use sc_bv for all ports. [Brian Small] * Add SYSTEMPERL_INCLUDE envvar to assist RPM builds. [Chitlesh Goorah] * Report errors when duplicate labels are used. (#72) [Vasu Kandadi] * Fix the SC_MODULE name() to not include __PVT__. [Bob Fredieu] Verilator 3.701 2009-02-26 ========================== **Minor:** * Support repeat and forever statements. [Jeremy Bennett] * Add --debugi- option, for internal debugging. [Dennis Muhlestein] * Fix compile issues with GCC 4.3. (#47) [Lane Brooks] * Fix VL_RANDom to better randomize bits. [Art Stamness] * Fix error messages to consistently go to stderr. [Jeremy Bennett] * Fix left associativity for ?: operators. Verilator 3.700 2009-01-08 ========================== **Major:** * Support limited tristate inouts. Written by Lane Brooks, under support by Ubixum Inc. This allows common pad ring and tristate-mux structures to be Verilated. See the documentation for more information on supported constructs. * Add --coverage_toggle for toggle coverage analysis. Running coverage now requires SystemPerl 1.301 or newer. * Add coverage_on/_off metacomments to bracket coverage regions. **Minor:** * Support posedge of bit-selected signals. (#45) [Rodney Sinclair] * Optimize two-level shift and and/or trees, +23% on one test. * Line coverage now aggregates by hierarchy automatically. Previously this would be done inside SystemPerl, which was slower. * Minor performance improvements of Verilator compiler runtime. * Coverage of each parameterized module is counted separately. [Bob Fredieu] * Fix creating parameterized modules when no parameter values are changed. * Fix certain generate-if cells causing "clone" error. [Stephane Laurent] * Fix line coverage of public functions. [Soon Koh] * Fix SystemC 2.2 deprecated warnings about sensitive() and sc_start(). * Fix arrayed variables under function not compiling. (#44) [Ralf Karge] * Fix --output-split-cfuncs to also split trace code. [Niranjan Prabhu] * Fix 'bad select range' warning missing some cases. (#43) [Lane Brooks] * Fix internal signal names containing control characters (broke in 3.680). * Fix compile error on Ubuntu 8.10. [Christopher Boumenot] * Fix internal error on "output x; reg x = y;". * Fix wrong result for read of delayed FSM signal. (#46) [Rodney Sinclair] Verilator 3.681 2008-11-12 ========================== **Minor:** * Support SystemVerilog unique and priority case. * Include Verilog file's directory name in coverage reports. * Fix 'for' under 'generate-for' causing error. (#38) [Rafael Shirakawa] * Fix coverage hierarchy being backwards with inlining. [Vasu Arasanipalai] * Fix GCC 4.3 compile error. (#35) [Lane Brooks] * Fix MSVC compile error. (#42) [John Stroebel] Verilator 3.680 2008-10-08 ========================== **Major:** * Support negative bit indexes. [Stephane Laurent] Tracing negative indexes requires latest Verilog-Perl and SystemPerl. **Minor:** * Suppress width warnings between constant strings and wider vectors. [Rodney Sinclair] * Ignore SystemVerilog timeunit and timeprecision. * Expand environment variables in -f input files. [Lawrence Butcher] * Report error if port declaration is missing. (#32) [Guy-Armand Kamendje] * Fix genvars causing link error when using --public. [Chris Candler] Verilator 3.671 2008-09-19 ========================== **Major:** * SystemC uint64_t pins are now the default instead of sc_bv<64>. Use --no-pins64 for backward compatibility. * Support SystemVerilog "cover property" statements. **Minor:** * When warnings are disabled on signals that are flattened out, disable the warnings on the signal(s) that replace it. * Add by-design and by-module subtotals to verilator_profcfunc. * Add IMPERFECTSCH warning, disabled by default. * Support coverage under SystemPerl 1.285 and newer. * Support arbitrary characters in identifiers. [Stephane Laurent] * Fix extra evaluation of pure combo blocks in SystemC output. * Fix stack overflow on large ? : trees. [John Sanguinetti] Verilator 3.670 2008-07-23 ========================== **Major:** * Add --x-assign=fast option, and make it the default. This chooses performance over reset debugging. See the manual. * Add --autoflush, for flushing streams after $display. [Steve Tong] * Add CASEWITHX lint warning and if disabled fix handling of casez with Xs. **Minor:** * Add $feof, $fgetc, $fgets, $fflush, $fscanf, $sscanf. [Holger Waechtler] * Add $stime. [Holger Waechtler] * Add $random. * Add --Wfuture-, for improving forward compatibility. * Add WIDTH warning to $fopen etc file descriptors. * Fix verilator_includer not being installed properly. [Holger Waechtler] * Fix IMPURE errors due to X-assignment temporary variables. [Steve Tong] * Fix "lvalue" errors with public functions. (#25) [CY Wang] Verilator 3.665 2008-06-25 ========================== **Minor:** * Ignore "// verilator" comments alone on endif lines. [Rodney Sinclair] * "Make install" now installs verilator_includer and verilator_profcfunc. * Fix tracing missing changes on undriven public wires. [Rodney Sinclair] * Fix syntax error when "`include `defname" is ifdefed. [John Dickol] * Fix error when macro call has commas in concatenate. [John Dickol] * Fix compile errors under Fedora 9, GCC 4.3.0. [by Jeremy Bennett] * Fix Makefile to find headers/libraries under prefix. [by Holger Waechtler] Verilator 3.664 2008-05-08 ========================== **Minor:** * Fix missing file in kit. Verilator 3.663 2008-05-07 ========================== **Minor:** * Add DESTDIR to Makefiles to assist RPM construction. [Gunter Dannoritzer] * Fix compiler warnings under GCC 4.2.1. * Fix preprocessor `else after series of `elsif. [Mark Nodine] * Fix parameterized defines calling define with comma. [Joshua Wise] * Fix comma separated list of primitives. [by Bryan Brady] Verilator 3.662 2008-04-25 ========================== **Minor:** * Add Verilog 2005 $clog2() function. This is useful in calculating bus-widths from parameters. * Support C-style comments in -f option files. [Stefan Thiede] * Add error message when modules have duplicate names. [Stefan Thiede] * Support defines terminated in EOF, though against spec. [Stefan Thiede] * Support optional argument to $finish and $stop. [by Stefan Thiede] * Support ranges on gate primitive instantiations. [Stefan Thiede] * Ignore old standard(ish) Verilog-XL defines. [by Stefan Thiede] * Fix "always @ ((a) or (b))" syntax error. [by Niranjan Prabhu] * Fix "output reg name=expr;" syntax error. [Martin Scharrer] * Fix multiple .v files being read in random order. [Stefan Thiede] * Fix internal error when params get non-constants. [Johan Wouters] * Fix bug introduced in 3.661 with parameterized defines. Verilator 3.661 2008-04-04 ========================== **Major:** * The --enable-defenv configure option added in 3.660 is now the default. This hard-codes a default for VERILATOR_ROOT etc in the executables. * Add --language option for supporting older code. [Stefan Thiede] * Add --top-module option to select between multiple tops. [Stefan Thiede] **Minor:** * Unsized concatenates now give WIDTHCONCAT warnings. [Jonathan Kimmitt] Previously they threw fatal errors, which in most cases is correct according to spec, but can be incorrect in presence of parameter values. * Support functions with "input integer". [Johan Wouters] * Ignore delays attached to gate UDPs. [Stefan Thiede] * Fix SystemVerilog parameterized defines with \`\` expansion, and fix extra whitespace inserted on substitution. [Vladimir Matveyenko] * Fix no-module include files on command line. [Stefan Thiede] * Fix dropping of backslash quoted-quote at end of $display. * Fix task output pin connected to non-variables. [Jonathan Kimmitt] * Fix missing test_v in install datadir. [Holger Waechtler] * Fix internal error after MSB < LSB error reported to user. [Stefan Thiede] Verilator 3.660 2008-03-23 ========================== **Minor:** * Support hard-coding VERILATOR_ROOT etc in the executables, to enable easier use of Verilator RPMs. [Gunter Dannoritzer] * Allow multiple .v files on command line. [Stefan Thiede] * Convert re-defining macro error to warning. [Stefan Thiede] * Add --error-limit option. [Stefan Thiede] * Allow __ in cell names by quoting them in C. [Stefan Thiede] * Fix genvar to be signed, so "< 0" works properly. [Niranjan Prabhu] * Fix assignments to inputs inside functions/tasks. [Patricio Kaplan] * Fix definitions in main file.v, referenced in library. [Stefan Thiede] * Fix undefined assigns to be implicit warnings. [Stefan Thiede] Verilator 3.658 2008-02-25 ========================== **Minor:** * Fix unistd compile error in 3.657. [Patricio Kaplan, Jonathan Kimmitt] Verilator 3.657 2008-02-20 ========================== **Minor:** * Fix assignments of {a,b,c} = {c,b,a}. [Jonathan Kimmitt] * Fix Perl warning with --lint-only. [by Ding Xiaoliang] * Fix to avoid creating obj_dir with --lint-only. [Ding Xiaoliang] * Fix parsing of always @(*). [Patricio Kaplan] Verilator 3.656 2008-01-18 ========================== **Minor:** * Wide VL_CONST_W_#X functions are now made automatically. [Bernard Deadman] In such cases, a new {prefix}__Inlines.h file will be built and included. * Fix sign error when extracting from signed memory. [Peter Debacker] * Fix tracing of SystemC w/o SystemPerl. [Bernard Deadman, Johan Wouters] Verilator 3.655 2007-11-27 ========================== **Minor:** * Support "#delay ;" with associated STMTDLY warning. * Fix generate for loops with constant zero conditions. [Rodney Sinclair] * Fix divide-by-zero errors in constant propagator. [Rodney Sinclair] * Fix wrong result with obscure signed-shift underneath a "? :". * Fix many internal memory leaks, and added leak detector. Verilator 3.654 2007-10-18 ========================== **Minor:** * Don't exit early if many warnings but no errors are found. [Stan Mayer] * Fix parsing module #(parameter x,y) declarations. [Oleg Rodionov] * Fix parsing system functions with empty parens. [Oleg Rodionov] Verilator 3.653 2007-08-01 ========================== **Minor:** * Support SystemVerilog ==? and !=? operators. * Fix SC_LIBS missing from generated makefiles. [Ding Xiaoliang] Verilator 3.652 2007-06-21 ========================== **Minor:** * Report as many warning types as possible before exiting. * Support V2K portlists with "input a,b,...". [Mark Nodine] * Support V2K function/task argument lists. * Optimize constant $display arguments. * Fix preprocessor dropping some `line directives. [Mark Nodine] Verilator 3.651 2007-05-22 ========================== **Major:** * Add verilator_profcfunc utility. [Gene Weber] **Minor:** * Treat modules within `celldefine and `endcelldefine as if in library. * Support functions which return integers. [Mark Nodine] * Warn if flex is not installed. [Ralf Karge] * Ignore `protect and `endprotect. * Fix empty case/endcase blocks. Verilator 3.650 2007-04-20 ========================== **Major:** * Add --compiler msvc option. This is now required when Verilated code is to be run through MSVC++. This also enables fixing MSVC++ error C1061, blocks nested too deeply. [Ralf Karge] * Add --lint-only option, to lint without creating other output. **Minor:** * Add /*verilator lint_save*/ and /*verilator lint_restore*/ to allow friendly control over re-enabling lint messages. [Gerald Williams] * Support SystemVerilog .name and .* interconnect. * Support while and do-while loops. * Use $(LINK) instead of $(CXX) for Makefile link rules. [Gerald Williams] * Add USER_CPPFLAGS and USER_LDFLAGS to Makefiles. [Gerald Williams] * Fix compile errors under Windows MINGW compiler. [Gerald Williams] * Fix dotted bit reference to local memory. [Eugene Weber] * Fix 3.640 `verilog forcing IEEE 1364-1995 only. [David Hewson] Verilator 3.640 2007-03-12 ========================== **Minor:** * Support Verilog 2005 `begin_keywords and `end_keywords. * Updated list of SystemVerilog keywords to correspond to IEEE 1800-2005. * Add /*verilator public_flat*/. [Eugene Weber] * Try all +libext's in the exact order given. [Michael Shinkarovsky] * Fix elimination of public signals assigned to constants. [Eugene Weber] * Fix internal error when public for loop has empty body. [David Addison] * Fix "Loops detected" assertion when model exceeds 4GB. [David Hewson] * Fix display %m names inside named blocks. Verilator 3.633 2007-02-07 ========================== **Minor:** * Add --trace-depth option for minimizing VCD file size. [Emerson Suguimoto] * With VL_DEBUG, show wires causing convergence errors. [Mike Shinkarovsky] * Fix isolate_assignments when many signals per always. [Mike Shinkarovsky] * Fix isolate_assignments across task/func temporaries. [Mike Shinkarovsky] * Fix $display's with array select followed by wide AND. [David Hewson] Verilator 3.632 2007-01-17 ========================== **Minor:** * Add /*verilator isolate_assignments*/ attribute. [Mike Shinkarovsky] Verilator 3.631 2007-01-02 ========================== **Major:** * Support standard NAME[#] for cells created by arraying or generate for. This replaces the non-standard name__# syntax used in earlier versions. **Minor:** * Fix again dotted references into generate cells. [David Hewson] Verilator no longer accepts duplicated variables inside unique generate blocks as this is illegal according to the specification. * Fix $readmem* with filenames < 8 characters. [Emerson Suguimoto] Verilator 3.630 2006-12-19 ========================== **Major:** * Support $readmemb and $readmemh. [Eugene Weber, Arthur Kahlich] **Minor:** * When dotted signal lookup fails, help the user by showing known scopes. * Fix to reduce depth of priority encoded case statements. [Eugene Weber] * Fix configure and compiling under Solaris. [Bob Farrell] * Fix dotted references inside generated cells. [David Hewson] * Fix missed split optimization points underneath other re-split blocks. Verilator 3.623 2006-12-05 ========================== **Major:** * Add --output-split-cfuncs for accelerating GCC compile. [Eugene Weber] **Minor:** * Add M32 make variable to support -m32 compiles. [Eugene Weber] * Fix $signed mis-extending when input has a WIDTH violation. [Eugene Weber] Verilator 3.622 2006-10-17 Stable ================================= **Minor:** * Fix --skip-identical without --debug, broken in 3.621. [Andy Meier] Verilator 3.621 2006-10-11 Beta =============================== **Major:** * Add /*verilator no_inline_task*/ to prevent over-expansion. [Eugene Weber] **Minor:** * Public functions now allow > 64 bit arguments. * Remove .vpp intermediate files when not under --debug. * Fix link error when using --exe with --trace. [Eugene Weber] * Fix mis-optimization of wide concats with constants. * Fix core dump on printing error when not under --debug. [Allan Cochrane] Verilator 3.620 2006-10-04 Stable ================================= **Minor:** * Support simple inout task ports. [Eugene Weber] * Allow overriding Perl, Flex and Bison versions. [by Robert Farrell] * Optimize variables set to constants within basic blocks for ~3%. * Default make no longer makes the docs; if you edit the documentation. sources, run "make info" to get them. * Optimize additional Boolean identities (a|a = a, etc.) * Fix coredump when dotted cross-ref inside task call. [Eugene Weber] * Fix dotted variables in always sensitivity lists. [Allan Cochrane] Verilator 3.610 2006-09-20 Stable ================================= **Minor:** * Verilator now works under DJGPP (Pentium GCC). [John Stroebel] * Add default define for VL_PRINTF. [John Stroebel] * Removed coverage request variable; see Coverage limitations in docs. * Fix DOS carriage returns in multiline defines. [Ralf Karge] * Fix printf format warnings on 64-bit linux. Verilator 3.602 2006-09-11 Stable ================================= **Minor:** * Fix function references under top inlined module. [David Hewson] Verilator 3.601 2006-09-06 Beta =============================== **Major:** * Add --inhibit-sim flag for environments using old __Vm_inhibitSim. * Add `systemc_dtor for destructor extensions. [Allan Cochrane] * Add -MP to make phony dependencies, ala GCC's. **Minor:** * Changed how internal functions are invoked to reduce aliasing. Useful when using GCC's -O2 or -fstrict-aliasing, to gain another ~4%. * Declare optimized lookup tables as 'static', to reduce D-Cache miss rate. * Fix memory leak when destroying modules. [John Stroebel] * Fix coredump when unused modules have unused cells. [David Hewson] * Fix 3.600 internal error with arrayed instances. [David Hewson] * Fix 3.600 internal error with non-unrolled function loops. [David Hewson] * Fix $display %m name not matching Verilog name inside SystemC modules. Verilator 3.600 2006-08-28 Beta =============================== **Major:** * Support dotted cross-hierarchy variable and task references. **Minor:** * Lint for x's in generate case statements. * Fix line numbers being off by one when first file starts with newline. * Fix naming of generate for blocks to prevent non-inline name conflict. * Fix redundant statements remaining after table optimization. Verilator 3.542 2006-08-11 Stable ================================= **Minor:** * vl_finish and vl_fatal now print via VL_PRINTF rather then cerr/cout. * Fix extraneous UNSIGNED warning when comparing genvars. [David Hewson] * Fix extra white space in $display %c. [by David Addison] * Fix missing VL_CONST_W_24X macro. [Bernard Deadman] Verilator 3.541 2006-07-05 Beta =============================== **Minor:** * Add warning on changeDetect to arrayed structures. [David Hewson] * Fix "// verilator lint_on" not re-enabling warnings. [David Hewson] * Fix 3.540's multiple memory assignments to same block. [David Hewson] * Fix non-zero start number for arrayed instantiations. [Jae Hossell] * Fix GCC 4.0 header file warnings. Verilator 3.540 2006-06-27 Beta =============================== **Minor:** * Optimize combo assignments that are used only once, ~5-25% faster. * Optimize delayed assignments to memories inside loops, ~0-5% faster. * Fix mis-width warning on bit selects of memories. [David Hewson] * Fix mis-width warning on dead generate-if branches. [Jae Hossell] Verilator 3.533 2006-06-05 Stable ================================= **Minor:** * Add PDF user manual, verilator.pdf. * Fix delayed bit-selected arrayed assignments. [David Hewson] * Fix execution path to Perl. [Shanshan Xu] * Fix Bison compile errors in verilog.y. [by Ben Jackson] Verilator 3.531 2006-05-10 Stable ================================= **Minor:** * Support $c routines which return 64 bit values. * Fix `include `DEFINE. * Fix Verilator core dump when have empty public function. [David.Hewson] Verilator 3.530 2006-04-24 Stable ================================= **Major:** * $time is now 64 bits. The macro VL_TIME_I is now VL_TIME_Q, but calls the same sc_time_stamp() function to get the current time. Verilator 3.523 2006-03-06 Stable ================================= **Minor:** * Fix error line numbers being off due to multi-line defines. [Mat Zeno] * Fix GCC sign extending (uint64_t)(a>>, $signed, $unsigned. [MANY!] * Support multi-dimensional arrays. [Eugen Fekete] * Support very limited Property Specification Language (aka PSL or Sugar). The format and keywords are now very limited, but will grow with future releases. The --assert switch enables this feature. * With --assert, generate assertions for synthesis parallel_case and full_case. **Minor:** * Fix generate if's with empty if/else blocks. [Mat Zeno] * Fix generate for cell instantiations with same name. [Mat Zeno] Verilator 3.481 2005-10-12 Stable ================================= **Minor:** * Add /*verilator tracing_on/off*/ for waveform control. * Fix split optimization reordering $display statements. Verilator 3.480 2005-09-27 Beta =============================== **Major:** * Allow coverage of flattened modules, and multiple points per line. Coverage analysis requires SystemPerl 1.230 or newer. **Minor:** * Add preprocessor changes to support meta-comments. * Optimize sequential assignments of different bits of same bus; ~5% faster. * Optimize away duplicate lookup tables. * Optimize wide concatenates into individual words. [Ralf Karge] * Optimize local variables from delayed array assignments. Verilator 3.470 2005-09-06 Stable ================================= **Minor:** * Optimize staging flops under reset blocks. * Add '-Werror-...' to upgrade specific warnings to errors. * Add GCC branch prediction hints on generated if statements. * Fix bad simulation when same function called twice in same expression. * Fix preprocessor substitution of quoted parameterized defines. Verilator 3.464 2005-08-24 Stable ================================= **Major:** * Add `systemc_imp_header, for use when using --output-split. * Add --stats option to dump design statistics. **Minor:** * Fix core dump with clock inversion optimizations. Verilator 3.463 2005-08-05 Stable ================================= **Minor:** * Fix case defaults when not last statement in case list. [Wim Michiels] Verilator 3.462 2005-08-03 Stable ================================= **Minor:** * Fix reordering of delayed assignments to same memory index. [Wim Michiels] * Fix compile error with Flex 2.5.1. [Jens Arm] * Fix multiply-instantiated public tasks generating non-compilable code. Verilator 3.461 2005-07-28 Beta =============================== **Minor:** * Fix compile error with older versions of bison. [Jeff Dutton] Verilator 3.460 2005-07-27 Beta =============================== **Major:** * Add -output-split option to enable faster parallel GCC compiles. To support --output-split, the makefiles now split VM_CLASSES into VM_CLASSES_FAST and VM_CLASSES_SLOW. This may require a change to local makefiles. * Support -v argument to read library files. **Minor:** * When issuing unoptimizable warning, show an example path. * Internal tree dumps now indicate edit number that changed the node. * Fix false warning when a clock is constant. * Fix X/Z in decimal numbers. [Wim Michiels] * Fix genvar statements in non-named generate blocks. * Fix core dump when missing newline in `define. [David van der Bokke] Verilator 3.450 2005-07-12 ========================== **Major:** * $finish will no longer exit, but set Verilated::gotFinish(). This enables support for final statements, and for other cleanup code. If this is undesired, redefine the vl_user_finish routine. Top level loops should use Verilated::gotFinish() as an exit condition for their loop, and then call top->final(). To prevent an infinite loop, a double $finish will still exit; this may be removed in future releases. * Support SystemVerilog keywords $bits, $countones, $isunknown, $onehot, $onehot0, always_comb, always_ff, always_latch, finish. **Minor:** * Fix "=== 1'bx" to always be false, instead of random. Verilator 3.440 2005-06-28 Stable ================================= **Major:** * Add Verilog 2001 generate for/if/case statements. Verilator 3.431 2005-06-24 Stable ================================= **Minor:** * Fix selection bugs introduced in 3.430 beta. Verilator 3.430 2005-06-22 Beta =============================== **Minor:** * Add Verilog 2001 variable part selects [n+:m] and [n-:m]. [Wim Michiels] Verilator 3.422 2005-06-10 Stable ================================= **Minor:** * Add Verilog 2001 power (**) operator. [Danny Ding] * Fix crash and added error message when assigning to inputs. [Ralf Karge] * Fix tracing of modules with public functions. Verilator 3.421 2005-06-02 Beta =============================== **Minor:** * Fix error about reserved word on non-public signals. * Fix missing initialization compile errors in 3.420 beta. [Ralf Karge] Verilator 3.420 2005-06-02 Beta =============================== **Minor:** * Performance improvements worth ~20% * Add -x-assign options; ~5% faster if use -x-assign=0. * Add error message when multiple defaults in case statement. * Optimize shifts out of conditionals and if statements. * Optimize local 'short' wires. * Fix case defaults when not last statement in case list. [Ralf Karge] * Fix crash when wire self-assigns x=x. * Fix gate optimization with top-flattened modules. [Mahesh Kumashikar] Verilator 3.411 2005-05-30 Stable ================================= **Minor:** * Fix compile error in GCC 2.96. [Jeff Dutton] Verilator 3.410 2005-05-25 Beta =============================== **Major:** * Allow functions and tasks to be declared public. They will become public C++ functions, with appropriate C++ types. This allows users to make public accessor functions/tasks, instead of having to use public variables and `systemc_header hacks. **Minor:** * Skip producing output files if all inputs are identical This uses timestamps, similar to make. Disable with --no-skip-identical. * Improved compile performance with large case statements. * Fix internal error in V3Table. [Jeff Dutton] * Fix compile error in GCC 2.96, and with SystemC 1.2. [Jeff Dutton] Verilator 3.400 2005-04-29 Beta =============================== **Major:** * Internal changes to support future clocking features. * Verilog-Perl and SystemPerl are no longer required for C++ or SystemC output. If you want tracing or coverage analysis, they are still needed. * Add --sc to create pure SystemC output not requiring SystemPerl. * Add --pins64 to create 64 bit SystemC outputs instead of sc_bv<64>. * The --exe flag is now required to produce executables inside the makefile. This was previously the case any time .cpp files were passed on the command line. * Add -O3 and --inline-mult for performance tuning. [Ralf Karge] One experiment regained 5% performance, at a cost of 300% in compile time. **Minor:** * Improved performance of large case/always statements with low fanin by converting to internal lookup tables (ROMs). * Initialize SystemC port names. [S Shuba] * Add Doxygen comments to Verilated includes. * Fix -cc pins 8 bits wide and less to be uint8_t instead of uint16_t. * Fix crash when Mdir has same name as .v file. [Gernot Koch] * Fix crash with size mismatches on case items. [Gernot Koch] Verilator 3.340 2005-02-18 Stable ================================= **Minor:** * Report misconnected pins across all modules, instead of just first error. * Improved large netlist compile times. * Fix over-active inlining, resulting in compile slowness. Verilator 3.332 2005-01-27 ========================== **Major:** * Add -E preprocess only flag, similar to GCC. * Add CMPCONSTLR when comparison is constant due to > or < with all ones. **Minor:** * Fix loss of first -f file argument, introduced in 3.331. Verilator 3.331 2005-01-18 ========================== **Major:** * The Verilog::Perl preprocessor is now C++ code inside of Verilator. This improves performance, makes compilation easier, and enables some future features. **Minor:** * Support arrays of instantiations (non-primitives only). [Wim Michiels] * Fix unlinked error with defparam. [Shawn Wang] Verilator 3.320 2004-12-10 ========================== **Major:** * NEWS is now renamed Changes, to support CPAN indexing. * If Verilator is passed a C file, create a makefile link rule. This saves several user steps when compiling small projects. **Minor:** * Add new COMBDLY warning in place of fatal error. [Shawn Wang] * Fix mis-simulation with wide-arrays under bit selects. [Ralf Karge] * Add NC Verilog as alternative to VCS for reference tests. * Support implicit wire declarations on input-only signals. (Dangerous, as leads to wires without drivers, but allowed by spec.) * Fix compile warnings on Suse 9.1 Verilator 3.311 2004-11-29 ========================== **Major:** * Support implicit wire declarations (as a warning). [Shawn Wang] **Minor:** * Fix over-shift difference in Verilog vs C++. [Ralf Karge] Verilator 3.310 2004-11-15 ========================== **Major:** * Support defparam. * Support gate primitives: buf, not, and, nand, or, nor, xor, xnor. **Minor:** * Ignore all specify blocks. Verilator 3.302 2004-11-12 ========================== **Minor:** * Support NAND and NOR operators. * Better warnings when port widths don't match. * Fix internal error due to some port width mismatches. [Ralf Karge] * Fix WIDTH warnings on modules that are only used parameterized, not in 'default' state. * Fix selection of SystemC library on cygwin systems. [Shawn Wang] * Fix runtime bit-selection of parameter constants. Verilator 3.301 2004-11-04 ========================== **Minor:** * Fix 64 bit [31:0] = {#{}} mis-simulation. [Ralf Karge] * Fix shifts greater then word width mis-simulation. [Ralf Karge] * Fix to work around GCC 2.96 negation bug. Verilator 3.300 2004-10-21 ========================== **Major:** * New backend that eliminates most VL macros. Improves performance 20%-50%, depending on frequency of use of signals over 64 bits. GCC compile times with -O2 shrink by a factor of 10. **Minor:** * Fix "setting unsigned int from signed value" warning. Verilator 3.271 2004-10-21 ========================== **Minor:** * Fix "loops detected" error with some negedge clocks. * Fix some output code spacing issues. Verilator 3.270 2004-10-15 ========================== **Minor:** * Support Verilog 2001 parameters in module headers. [Ralf Karge] * Faster code to support compilers not inlining all Verilated functions. * Fix numeric fault when dividing by zero. Verilator 3.260 2004-10-07 ========================== **Major:** * Support Verilog 2001 named parameter instantiation. [Ralf Karge] **Minor:** * Return 1's when one bit wide extract indexes outside array bounds. * Fix compile warnings on 64-bit operating systems. * Fix incorrect dependency in .d file when setting VERILATOR_BIN. Verilator 3.251 2004-09-09 ========================== **Minor:** * Fix parenthesis overflow in Microsoft Visual C++ [Renga Sundararajan] Verilator 3.250 2004-08-30 ========================== **Major:** * Support Microsoft Visual C++ [Renga Sundararajan] **Minor:** * SystemPerl 1.161+ is required. Verilator 3.241 2004-08-17 ========================== **Minor:** * Support ,'s to separate multiple assignments. [Paul Nitza] * Fix shift sign extension problem using non-GCC compilers. Verilator 3.240 2004-08-13 ========================== **Major:** * Verilator now uses 64 bit math where appropriate. Inputs and outputs of 33-64 bits wide to the C++ Verilated model must now be uint64_t's; SystemC has not changed, they will remain sc_bv's. This increases performance by ~ 9% on x86 machines, varying with how frequently 33-64 bit signals occur. Signals 9-16 bits wide are now stored as 16 bit shorts instead of longs, this aids cache packing. **Minor:** * Fix SystemC compile error with feedthrus. [Paul Nitza] * Fix concat value error introduced in 3.230. Verilator 3.230 2004-08-10 ========================== **Minor:** * Add coverage output to test_sp example, SystemPerl 1.160+ is required. * Fix time 0 value of signals. [Hans Van Antwerpen] Earlier versions would not evaluate some combinatorial signals until posedge/negedge blocks had been activated. * Fix wide constant inputs to public submodules [Hans Van Antwerpen] * Fix wide signal width extension bug. Only applies when width mismatch warnings were overridden. Verilator 3.220 2004-06-22 ========================== **Major:** * Many waveform tracing changes: * Tracing is now supported on C++ standalone simulations. [John Brownlee] **Minor:** * When tracing, SystemPerl 1.150 or newer is required. * When tracing, Verilator must be called with the --trace switch. * Add SystemPerl example to documentation. [John Brownlee] * Various Cygwin compilation fixes. [John Brownlee] Verilator 3.210 2004-04-01 ========================== **Major:** * Compiler optimization switches have changed See the BENCHMARKING section of the documentation. * With Verilog-Perl 2.3 or newer, Verilator supports SystemVerilog preprocessor extensions. **Minor:** * Add localparam. [Thomas Hawkins] * Add warnings for SystemVerilog reserved words. Verilator 3.203 2004-03-10 ========================== **Minor:** * Notes and repairs for Solaris. [Fred Ma] Verilator 3.202 2004-01-27 ========================== **Major:** * The beta version is now the primary release. See below for many changes. If you have many problems, you may wish to try release 3.125. * Verilated::traceEverOn(true) must be called at time 0 if you will ever turn on tracing (waveform dumping) of signals. Future versions will need this switch to disable trace incompatible optimizations. **Minor:** * Optimize common replication operations. * Fix several tracing bugs Verilator 3.201-beta 2003-12-10 =============================== **Major:** * BETA VERSION, USE 3.124 for stable release! * Version 3.2XX includes an all new back-end. This includes automatic inlining, flattening of signals between hierarchy, and complete ordering of statements. This results in 60-300% execution speedups, though less pretty C++ output. Even better results are possible using GCC 3.2.2 (part of Redhat 9.1), as GCC has fixed some optimization problems which Verilator exposes. If you are using `systemc_ctor, beware pointers to submodules are now initialized after the constructor is called for a module, to avoid segfaults, move statements that reference subcells into initial statements. * C++ Constructor that creates a verilog module may take a char* name. This name will be used to prefix any $display %m arguments, so users may distinguish between multiple Verilated modules in a single executable. Verilator 3.125 2004-01-27 ========================== **Minor:** * Optimize bit replications Verilator 3.124 2003-12-05 ========================== **Major:** * An optimized executable will be made by default, in addition to a debug executable. Invoking Verilator with --debug will pick the debug version. **Minor:** * Many minor invisible changes to support the next version. Verilator 3.123 2003-11-10 ========================== **Minor:** * Wide bus performance enhancements. * Fix function call bug when width warning suppressed. [Leon Wildman] * Fix __DOT__ compile problem with funcs in last revision. [Leon Wildman] Verilator 3.122 2003-10-29 ========================== **Major:** * Modules which are accessed from external code now must be marked with /*verilator public_module*/ unless they already contain public signals. To enforce this, private cell names now have a string prepended. **Minor:** * Fix replicated function calls in one statement. [Robert A. Clark] * Fix function call bug when width warning suppressed. [Leon Wildman] Verilator 3.121 2003-09-29 ========================== **Minor:** * Support multiplication over 32 bits. [Chris Boumenot] Also improved speed of addition and subtraction over 32 bits. * Detect bit selection out of range errors. * Detect integer width errors. * Fix width problems on function arguments. [Robert A. Clark] Verilator 3.120 2003-09-24 ========================== **Minor:** * $finish now exits the model (via vl_finish function). * Support inputs/outputs in tasks. * Support V2K "integer int = {INITIAL_VALUE};" * Ignore floating point delay values. [Robert A. Clark] * Ignore `celldefine, `endcelldefine, etc. [Robert A. Clark] * Optimize reduction operators. * Fix converting "\ooo" into octal values. * Fix $display("%x"); Verilator 3.112 2003-09-16 ========================== **Minor:** * Fix functions in continuous assignments. [Robert A. Clark] * Fix inlining of modules with 2-level deep outputs. Verilator 3.111 2003-09-15 ========================== **Minor:** * Fix declaration of functions before using that module. [Robert A. Clark] * Fix module inlining bug with outputs. Verilator 3.110 2003-09-12 ========================== **Major:** * Support Verilog 2001 style input/output declarations. [Robert A. Clark] * Support local vars in headers of function/tasks. [Leon Wildman] Verilator 3.109 2003-08-28 ========================== **Major:** * Support local variables in named begin blocks. [Leon Wildman] Verilator 3.108 2003-08-11 ========================== **Major:** * Support functions. **Minor:** * Signals 8 bits and shorter are now stored as chars instead of uint32_t's. This improves Dcache packing and improves performance by ~7%. * $display now usually results in a single VL_PRINT rather then many. * Optimize conditionals (?:) Verilator 3.107 2003-07-15 ========================== **Major:** * --private and --l2name are now the default, as this enables additional optimizations. Use --noprivate or --nol2name to get the older behavior. **Minor:** * Now support $display of binary and wide format data. * Add detection of incomplete case statements, and added related optimizations worth ~4%. * Work around flex bug in Redhat 8.0. [Eugene Weber] * Add some additional C++ reserved words. * Additional constant optimizations, ~5% speed improvement. Verilator 3.106 2003-06-17 ========================== **Major:** * $c can now take multiple expressions as arguments. For example $c("foo","bar(",32+1,");") will insert "foobar(33);" This makes it easier to pass the values of signals. * Several changes to support future versions that may have signal-eliminating optimizations. Users should try to use these switch on designs, they will become the default in later versions. * Add --private switch and /*verilator public*/ metacomment. This renames all signals so that compile errors will result if any signals referenced by C++ code are missing a /*verilator public*/ metacomment. * With --l2name, the second level cell C++ cell is now named "v". Previously it was named based on the name of the verilog code. This means to get to signals, scope to "{topcell} ->v ->{mysignal}" instead of "{topcell} ->{verilogmod}. {mysignal}". This allows different modules to be substituted for the cell without requiring source changes. **Minor:** * Several cleanups for Redhat 8.0. Verilator 3.105 2003-05-08 ========================== **Minor:** * Fix more GCC 3.2 errors. [David Black] Verilator 3.104 2003-04-30 ========================== **Major:** * Indicate direction of ports with VL_IN and VL_OUT. * Allow $c32, etc, to specify width of the $c statement for VCS. * Numerous performance improvements, worth about 25% **Minor:** * Fix false "indent underflow" error inside `systemc_ctor sections. * Fix missing ordering optimizations when outputs also used internally. * Assign constant cell pins in initial blocks rather then every cycle. * Promote subcell's combo logic to sequential evaluation when possible. * Fix GCC 3.2 compile errors. [Narayan Bhagavatula] Verilator 3.103 2003-01-28 ========================== **Minor:** * Fix missing model evaluation when clock generated several levels of hierarchy across from where it is used as a clock. [Richard Myers] * Fix sign-extension bug introduced in 3.102. Verilator 3.102 2003-01-24 ========================== **Minor:** * Fix sign-extension of X/Z's ("32'hx") Verilator 3.101 2003-01-13 ========================== **Minor:** * Fix 'parameter FOO=#'bXXXX' [Richard Myers] * Allow spaces inside numbers ("32'h 1234") [Sam Gladstone] Verilator 3.100 2002-12-23 ========================== **Major:** * Support for simple tasks w/o vars or I/O. [Richard Myers] **Minor:** * Ignore DOS carriage returns in Linux files. [Richard Myers] Verilator 3.012 2002-12-18 ========================== **Minor:** * Fix parsing bug with casex statements containing case items with bit extracts of parameters. [Richard Myers] * Fix bug which could cause writes of non-power-of-2 sized arrays to corrupt memory beyond the size of the array. [Dan Lussier] * Fix bug which did not detect UNOPT problems caused by submodules. See the description in the verilator man page. [John Deroo] * Fix compile with threaded Perl. [Ami Keren] Verilator 3.010 2002-11-03 ========================== **Major:** * Support SystemC 2.0.1. SystemPerl version 1.130 or newer is required. **Minor:** * Fix bug with inlined modules under other inlined modules. [Scott Bleiweiss] Verilator 3.005 2002-10-21 ========================== **Minor:** * Fix X's in case (not casex/z) to constant propagate correctly. * Fix missing include. [Kurachi] Verilator 3.004 2002-10-10 ========================== **Minor:** * Add module_inline metacomment and associated optimizations. * Allow coverage_block_off metacomment in place of `coverage_block_off. This prevents problems with Emacs AUTORESET. [Ray Strouble] * Fix `coverage_block_off also disabling subsequent blocks. * Fix unrolling of loops with multiple simple statements. * Fix compile warnings on newer GCC. [Kurachi] * Additional concatenation optimizations. Verilator 3.003 2002-09-13 ========================== **Minor:** * Now compiles on Windows 2000 with Cygwin. * Fix bug with pin assignments to wide memories. * Optimize wire assignments to constants. Verilator 3.002 2002-08-19 ========================== **Major:** * First public release of version 3. Verilator 3.000 2002-08-03 ========================== **Major:** * All new code base. Many changes too numerous to mention. **Minor:** * Approximately 4 times faster then Verilator 2. * Support initial statements * Support correct blocking/nonblocking assignments * Support `defines across multiple modules * Optimize call ordering, constant propagation, and dead code elimination. Verilator 2.1.8 2002-04-03 ========================== **Major:** * All applications must now link against include/verilated.cpp **Minor:** * Paths specified to verilator_make should be absolute, or be formed to allow for execution in the object directory (prepend ../ to each path.) This allows relative filenames for makes which hash and cache dependencies. * Add warning when parameter constants are too large. [John Deroo] * Add warning when x/?'s used in non-casez statements. * Add warning when blocking assignments used in posedge blocks. [Dan Lussier] * Split evaluation function into clocked and non-clocked, 20% perf gain. Verilator 2.1.5 2001-12-01 ========================== **Major:** * Add coverage analysis. In conjunction with SystemC provide line coverage reports, without SystemC, provide a hook to user written accumulation function. See --coverage option of verilator_make. **Minor:** * Relaxed multiply range checking * Support for constants up to 128 bits * Randomize values used when assigning to X's. * Add -guard option of internal testing. * Changed indentation in emitted code to be automatically generated. * Fix corruption of assignments of signal over 32 bits with non-0 lsb. Verilator 2.1.4 2001-11-16 ========================== **Major:** * Add $c("c_commands();"); for embedding arbitrary C code in Verilog. Verilator 2.1.3 2001-11-03 ========================== **Major:** * Support for parameters. Verilator 2.1.2 2001-10-25 ========================== **Major:** * Verilog Errors now reference the .v file rather then the .vpp file. **Minor:** * Support strings in assignments: reg [31:0] foo = "STRG"; * Support %m in format strings. Ripped out old $info support, use Verilog-Perl's vpm program instead. * Convert $stop to call of v_stop() which user can define. * Fix bug where a==b==c would have wrong precedence rule. * Fix bug where XNOR on odd-bit-widths (~^ or ^~) had bad value. Verilator 2.1.1 2001-05-17 ========================== **Major:** * New test_sp directory for System-Perl (SystemC) top level instantiation of the Verilated code, lower modules are still C++ code. (Experimental). * New test_spp directory for Pure System-Perl (SystemC) where every module is true SystemC code. (Experimental) **Minor:** * Input ports are now loaded by pointer reference into the sub-cell. This is faster on I-386 machines, as the stack must be used when there are a large number of parameters. Also, this simplifies debugging as the value of input ports exists for tracing. * Many code cleanups towards standard C++ style conventions. Verilator 2.1.0 2001-05-08 ========================== **Minor:** * Many code cleanups towards standard C++ style conventions. Version history lost ==================== Verilator 1.8 1996-07-08 ======================== [Versions 0 to 1.8 were by Paul Wasson] * Fix single bit in concat from instance output incorrect offset bug. Verilator 1.7 1996-05-20 ======================== * Mask unused bits of DONTCAREs. Verilator 1.6 1996-05-13 ======================== * Add fasttrace script Verilator 1.5 1996-01-09 ======================== * Pass structure pointer into translated code, so multiple instances can use same functions. * Fix static value concat on casex items. Verilator 1.1 1995-03-30 ======================== * Bug fixes, added verimake_partial script, performance improvements. Verilator 1.0c 1994-09-30 ========================= * Initial release of Verilator Verilator 0.0 1994-07-08 ======================== * First code written. .. ---------------------------------------------------------------------- Copyright ========= Copyright 2001-2026 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 verilator-5.044/.bake.toml0000644000542200017500000000111315125463617015776 0ustar mahmoudyfreeshell# mbake configuration file [formatter] # Indentation settings use_tabs = true tab_width = 2 # Spacing settings space_around_assignment = true space_before_colon = false space_after_colon = true # Line continuation settings normalize_line_continuations = true max_line_length = 100 # PHONY settings group_phony_declarations = false phony_at_top = false auto_insert_phony_declarations = false # General settings remove_trailing_whitespace = true ensure_final_newline = true normalize_empty_lines = true max_consecutive_empty_lines = 2 # Global settings debug = false verbose = false verilator-5.044/nodist/0000755000542200017500000000000015125463617015425 5ustar mahmoudyfreeshellverilator-5.044/nodist/fuzzer/0000755000542200017500000000000015125463617016752 5ustar mahmoudyfreeshellverilator-5.044/nodist/fuzzer/run0000755000542200017500000000125115125463617017503 0ustar mahmoudyfreeshell#!/bin/bash ###################################################################### # DESCRIPTION: Fuzzer run script # # Copyright 2019-2019 by Eric Rippey. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### # Actually do the fuzzing. Note that this will not terminate in any reasonable # amount of time. However, it will give updates on its progress. afl-fuzz -i in1 -o out1 -x dictionary ./wrapper --cc @@ verilator-5.044/nodist/fuzzer/setup_user0000755000542200017500000000204515125463617021077 0ustar mahmoudyfreeshell#!/bin/bash ###################################################################### # DESCRIPTION: Fuzzer setup to be run as a normal user # # Copyright 2019-2019 by Eric Rippey. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### # This is the portion of the setup for fuzzing that does not require root access. set -e # Build instrumented version of verilator pushd ../.. autoconf AFL_HARDEN=1 CXX=afl-g++ ./configure $(cd ..; pwd) make clean make -j $(ncpus) popd # Create a listing of likely snippets for the fuzzer to use. # Not essential, but makes things likely to be found faster. ./generate_dictionary # Set up input directory mkdir in1 echo "module m; initial \$display(\"Hello world!\n\"); endmodule" > in1/1.v # Compile wrapper program AFL_HARDEN=1 CXX=afl-g++ make wrapper verilator-5.044/nodist/fuzzer/generate_dictionary0000755000542200017500000000431515125463617022722 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # pylint: disable=C0103,C0114,C0115,C0116,C0321 ###################################################################### # DESCRIPTION: Fuzzer dictionary generator # # Copyright 2019-2019 by Eric Rippey. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU Lesser # General Public License Version 3 or the Perl Artistic License Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### # Attempts to pull a list of keywords out of the Flex input # These are then put in a dictionary of "interesting" sequences # This will be used to help the fuzzer pick interesting inputs more quickly. from subprocess import getstatusoutput from os import system def take_while(f, a): # any(a) => (a->bool)->[a]->[a] # Does the same think as Haskell's takewhile. out = [] for elem in a: if f(elem): out.append(elem) else: return out return out def skip_while(f, a): # any(a) => (a->bool)->[a]->[a] # Basically, the opposite thing from skipwhile while len(a) and f(a[0]): a = a[1:] return a def print_lines(a): # printable(a) => [a]->void for elem in a: print(elem) def write_file(filename, contents): # str->str->void with open(filename, "w", encoding="utf8") as fh: fh.write(contents) def parse_line(s): # str->maybe str if len(s) == 0: return None part = skip_while(lambda x: x != '"', s) if len(part) == 0 or part[0] != '"': return None literal_part = take_while(lambda x: x != '"', part[1:]) return ''.join(filter(lambda x: x != '\\', literal_part)) def main(): status, output = getstatusoutput('flex -T ../../src/verilog.l') assert status == 0 lines = output.splitlines() lines = take_while(lambda x: 'beginning dump of nfa' not in x, lines) tokens = set(filter(lambda x: x, map(parse_line, lines))) dirname = 'dictionary' r = system('mkdir -p ' + dirname) assert r == 0 for i, token in enumerate(tokens): write_file(dirname + '/' + str(i), token) if __name__ == '__main__': main() verilator-5.044/nodist/fuzzer/.gitignore0000644000542200017500000000004215125463617020736 0ustar mahmoudyfreeshellwrapper dictionary/ in* lex.yy.cc verilator-5.044/nodist/fuzzer/all0000755000542200017500000000122415125463617017447 0ustar mahmoudyfreeshell#!/bin/bash ###################################################################### # DESCRIPTION: Fuzzer one-line setup & run # # Copyright 2019-2019 by Eric Rippey. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### # Run all steps needed to configure and start fuzzer # Note that this assumes the system is a Debian-like Linux distribution set -e sudo ./setup_root ./setup_user ./run verilator-5.044/nodist/fuzzer/wrapper.cpp0000644000542200017500000000201115125463617021130 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // DESCRIPTION: Verilator fuzzing wrapper for verilator_bin // // Copyright 2019 by Eric Rippey. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 //************************************************************************* #include #include #include // The purpose of this script is to make sure that the results folder that // is generated by running verilator does not change the results of // subsequent runs. // This does slow down the execution to some degree but makes the results // more reliable. int main(int argc, char** argv, char** envp) { auto r = system("rm -rf obj_dir"); assert(r == 0); return execve("../../bin/verilator_bin", argv, envp); } verilator-5.044/nodist/fuzzer/actual_fail0000755000542200017500000000326615125463617021153 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # mypy: disallow-untyped-defs # pylint: disable=C0103,C0114,C0115,C0116,C0321,R0911 ###################################################################### # DESCRIPTION: Fuzzer result checker # # Copyright 2019-2019 by Eric Rippey. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU Lesser # General Public License Version 3 or the Perl Artistic License Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### # This script is designed to rerun examples to see whether they have # unexpected types of output besides the ones that afl-fuzz detects as # such. from glob import glob from subprocess import getstatusoutput from argparse import ArgumentParser def interesting(s: str) -> bool: if 'assert' in s: return True if 'Assert' in s: return True if 'Aborted' in s: return True if 'terminate' in s: if 'unterminated' in s: return False return True if 'Segmentation' in s: return True if 'internal error' in s: return True return False def main() -> None: p = ArgumentParser() p.add_argument('--dir', default='out1/queue') args = p.parse_args() for infile in glob(args.dir + '/*'): # Input filenames are known not to contain spaces or other unusual # characters, therefore this works. status, output = getstatusoutput('../../bin/verilator_bin --cc ' + infile) if interesting(output): print(infile) print(status) print(output) if __name__ == '__main__': main() verilator-5.044/nodist/fuzzer/setup_root0000755000542200017500000000156015125463617021105 0ustar mahmoudyfreeshell#!/bin/bash ###################################################################### # DESCRIPTION: Fuzzer setup to be run as root # # Copyright 2019-2019 by Eric Rippey. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### # This is the portion of the fuzzer setup that must be run as root. # Note that this assumes a Debian-like distribution. set -e # Get dependencies apt-get install afl mdm apt-get build-dep verilator # Run a couple pieces of setup which should speed up the fuzzer echo core >/proc/sys/kernel/core_pattern cd /sys/devices/system/cpu echo performance | tee cpu*/cpufreq/scaling_governor verilator-5.044/nodist/fastcov.py0000755000542200017500000013773715125463617017471 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # SPDX-License-Identifier: MIT # Copyright 2018-present, Bryan Gillespie """ Author: Bryan Gillespie https://github.com/RPGillespie6/fastcov A massively parallel gcov wrapper for generating intermediate coverage formats fast The goal of fastcov is to generate code coverage intermediate formats as fast as possible, even for large projects with hundreds of gcda objects. The intermediate formats may then be consumed by a report generator such as lcov's genhtml, or a dedicated frontend such as coveralls. Sample Usage: $ cd build_dir $ ./fastcov.py --zerocounters $ $ ./fastcov.py --exclude /usr/include test/ --lcov -o report.info $ genhtml -o code_coverage report.info """ import re import os import sys import glob import json import time import fnmatch import logging import argparse import threading import subprocess import multiprocessing from pathlib import Path FASTCOV_VERSION = (1,17) MINIMUM_PYTHON = (3,5) MINIMUM_GCOV = (9,0,0) # Interesting metrics START_TIME = time.monotonic() GCOVS_TOTAL = 0 GCOVS_SKIPPED = 0 # Gcov Coverage File Extensions GCOV_GCNO_EXT = ".gcno" # gcno = "[gc]ov [no]te" GCOV_GCDA_EXT = ".gcda" # gcda = "[gc]ov [da]ta" # For when things go wrong... # Start error codes at 3 because 1-2 are special # See https://stackoverflow.com/a/1535733/2516916 EXIT_CODE = 0 EXIT_CODES = { "gcov_version": 3, "python_version": 4, "unsupported_coverage_format": 5, "excl_not_found": 6, "bad_chunk_file": 7, "missing_json_key": 8, "no_coverage_files": 9, } # Disable all logging in case developers are using this as a module logging.disable(level=logging.CRITICAL) class FastcovFormatter(logging.Formatter): def format(self, record): record.levelname = record.levelname.lower() log_message = super(FastcovFormatter, self).format(record) return "[{:.3f}s] {}".format(stopwatch(), log_message) class DiffParseError(Exception): pass class DiffParser(object): def _refinePaths(self, diff_metadata, diff_base_dir): diff_metadata.pop('/dev/null', None) diff_metadata.pop('', None) for key, value in diff_metadata.copy().items(): diff_metadata.pop(key) #sources without added lines will be excluded if value: newpath = os.path.join(diff_base_dir, key) if diff_base_dir else os.path.abspath(key) diff_metadata[newpath] = value def _parseTargetFile(self, line_with_target_file): #f.e. '+++ b/README.md1' or '+++ b/README.md1 timestamp' target_source = line_with_target_file[4:].partition('\t')[0].strip() target_source = target_source[2:] if target_source.startswith('b/') else target_source return target_source def _parseHunkBoundaries(self, line_with_hunk_boundaries, line_index): #f.e. '@@ -121,4 +122,4 @@ Time to process all gcda and parse all gcov:' # Here ['-121,4', '+122,4'] lines_info = line_with_hunk_boundaries[3:].partition("@@")[0].strip().split(' ') if len(lines_info) != 2: raise DiffParseError("Found invalid hunk. Line #{}. {}".format(line_index, line_with_hunk_boundaries)) # Here ['122','4'] target_lines_info = lines_info[1].strip('+').partition(',') target_line_current = int(target_lines_info[0]) target_lines_count = int(target_lines_info[2]) if target_lines_info[2] else 1 # Here ['121','4'] source_lines_info = lines_info[0].strip('-').partition(',') source_line_current = int(source_lines_info[0]) source_lines_count = int(source_lines_info[2]) if source_lines_info[2] else 1 return target_line_current, target_lines_count, source_line_current, source_lines_count def parseDiffFile(self, diff_file, diff_base_dir, fallback_encodings=[]): diff_metadata = {} target_source = None target_hunk = set() target_line_current = 0 target_line_end = 0 source_line_current = 0 source_line_end = 0 found_hunk = False for i, line in enumerate(getSourceLines(diff_file, fallback_encodings), 1): line = line.rstrip() if not found_hunk: if line.startswith('+++ '): # refresh file target_source = self._parseTargetFile(line) elif line.startswith('@@ '): # refresh hunk target_line_current, target_lines_count, source_line_current, source_lines_count = self._parseHunkBoundaries(line, i) target_line_end = target_line_current + target_lines_count source_line_end = source_line_current + source_lines_count target_hunk = set() found_hunk = True continue if target_line_current > target_line_end or source_line_current > source_line_end: raise DiffParseError("Hunk longer than expected. Line #{}. {}".format(i, line)) if line.startswith('+'): #line related to target target_hunk.add(target_line_current) target_line_current = target_line_current + 1 elif line.startswith(' ') or line == '': # line related to both target_line_current = target_line_current + 1 source_line_current = source_line_current + 1 elif line.startswith('-'): # line related to source source_line_current = source_line_current + 1 elif not line.startswith('\\'): # No newline at end of file # line with newline marker is not included into any boundaries raise DiffParseError("Found unrecognized hunk line type. Line #{}. {}".format(i, line)) if target_line_current == target_line_end and source_line_current == source_line_end: # Checked all lines, save data if target_source in diff_metadata: diff_metadata[target_source] = target_hunk.union(diff_metadata[target_source]) else: diff_metadata[target_source] = target_hunk target_hunk = set() found_hunk = False if target_line_current != target_line_end or source_line_current != source_line_end: raise DiffParseError("Unexpected end of file. Expected hunk with {} target lines, {} source lines".format( target_line_end - target_line_current, source_line_end - source_line_current)) self._refinePaths(diff_metadata, diff_base_dir) return diff_metadata def filterByDiff(self, diff_file, dir_base_dir, fastcov_json, fallback_encodings=[]): diff_metadata = self.parseDiffFile(diff_file, dir_base_dir, fallback_encodings) logging.debug("Include only next files: {}".format(diff_metadata.keys())) excluded_files_count = 0 excluded_lines_count = 0 for source in list(fastcov_json["sources"].keys()): diff_lines = diff_metadata.get(source, None) if not diff_lines: excluded_files_count = excluded_files_count + 1 logging.debug("Exclude {} according to diff file".format(source)) fastcov_json["sources"].pop(source) continue for test_name, report_data in fastcov_json["sources"][source].copy().items(): #No info about functions boundaries, removing all for function in list(report_data["functions"].keys()): report_data["functions"].pop(function, None) for line in list(report_data["lines"].keys()): if line not in diff_lines: excluded_lines_count = excluded_lines_count + 1 report_data["lines"].pop(line) for branch_line in list(report_data["branches"].keys()): if branch_line not in diff_lines: report_data["branches"].pop(branch_line) if len(report_data["lines"]) == 0: fastcov_json["sources"][source].pop(test_name) if len(fastcov_json["sources"][source]) == 0: excluded_files_count = excluded_files_count + 1 logging.debug('Exclude {} file as it has no lines due to diff filter'.format(source)) fastcov_json["sources"].pop(source) logging.info("Excluded {} files and {} lines according to diff file".format(excluded_files_count, excluded_lines_count)) return fastcov_json def chunks(l, n): """Yield successive n-sized chunks from l.""" for i in range(0, len(l), n): yield l[i:i + n] def setExitCode(key): global EXIT_CODE EXIT_CODE = EXIT_CODES[key] def setExitCodeRaw(code): global EXIT_CODE EXIT_CODE = code def incrementCounters(total, skipped): global GCOVS_TOTAL global GCOVS_SKIPPED GCOVS_TOTAL += total GCOVS_SKIPPED += skipped def stopwatch(): """Return number of seconds since last time this was called.""" global START_TIME end_time = time.monotonic() delta = end_time - START_TIME START_TIME = end_time return delta def parseVersionFromLine(version_str): """Given a string containing a dotted integer version, parse out integers and return as tuple.""" version = re.search(r'(\d+\.\d+\.\d+)', version_str) if not version: return (0,0,0) return tuple(map(int, version.group(1).split("."))) def getGcovVersion(gcov): p = subprocess.Popen([gcov, "-v"], stdout=subprocess.PIPE) output = p.communicate()[0].decode('UTF-8') p.wait() return parseVersionFromLine(output.split("\n")[0]) def tryParseNumber(s): try: return int(s) except ValueError: # Log a warning if not hyphen if s != "-": logging.warning("Unsupported numerical value '%s', using 0", s) # Default to 0 if we can't parse the number (e.g. "-", "NaN", etc.) return 0 def removeFiles(files): for file in files: os.remove(file) def processPrefix(path, prefix, prefix_strip): p = Path(path) if p.exists() or not p.is_absolute(): return path if prefix_strip > 0: segments = p.parts if len(segments) < prefix_strip + 1: logging.warning("Couldn't strip %i path levels from %s.", prefix_strip, path) return path segments = segments[prefix_strip+1:] p = Path(segments[0]) segments = segments[1:] for s in segments: p = p.joinpath(s) if len(prefix) > 0: if p.is_absolute(): p = Path(prefix).joinpath(p.relative_to('/')) else: p = Path(prefix).joinpath(p) return str(p) def getFilteredCoverageFiles(coverage_files, exclude): def excludeGcda(gcda): for ex in exclude: if ex in gcda: logging.debug("Omitting %s due to '--exclude-gcda %s'", gcda, ex) return False return True return list(filter(excludeGcda, coverage_files)) def globCoverageFiles(cwd, coverage_type): return glob.glob(os.path.join(os.path.abspath(cwd), "**/*" + coverage_type), recursive=True) def findCoverageFiles(cwd, coverage_files, use_gcno): coverage_type = "user provided" if not coverage_files: # gcov strips off extension of whatever you pass it and searches [extensionless name] + .gcno/.gcda # We should pass either gcno or gcda, but not both - if you pass both it will be processed twice coverage_type = GCOV_GCNO_EXT if use_gcno else GCOV_GCDA_EXT coverage_files = globCoverageFiles(cwd, coverage_type) logging.info("Found {} coverage files ({})".format(len(coverage_files), coverage_type)) logging.debug("Coverage files found:\n %s", "\n ".join(coverage_files)) return coverage_files def gcovWorker(data_q, metrics_q, args, chunk, gcov_filter_options): base_report = {"sources": {}} gcovs_total = 0 gcovs_skipped = 0 error_exit = False gcov_bin = args.gcov gcov_args = ["--json-format", "--stdout"] if args.branchcoverage or args.xbranchcoverage: gcov_args.append("--branch-probabilities") encoding = sys.stdout.encoding if sys.stdout.encoding else 'UTF-8' workdir = args.cdirectory if args.cdirectory else "." p = subprocess.Popen([gcov_bin] + gcov_args + chunk, cwd=workdir, stdout=subprocess.PIPE, stderr=subprocess.DEVNULL) for i, line in enumerate(iter(p.stdout.readline, b'')): try: intermediate_json = json.loads(line.decode(encoding)) except json.decoder.JSONDecodeError as e: logging.error("Could not process chunk file '{}' ({}/{})".format(chunk[i], i+1, len(chunk))) logging.error(str(e)) setExitCode("bad_chunk_file") continue if "current_working_directory" not in intermediate_json: logging.error("Missing 'current_working_directory' for data file: {}".format(intermediate_json)) setExitCode("missing_json_key") continue intermediate_json_files = processGcovs(args.cdirectory, intermediate_json["files"], intermediate_json["current_working_directory"], gcov_filter_options) for f in intermediate_json_files: distillSource(f, base_report["sources"], args.test_name, args.xbranchcoverage) gcovs_total += len(intermediate_json["files"]) gcovs_skipped += len(intermediate_json["files"]) - len(intermediate_json_files) p.wait() data_q.put(base_report) metrics_q.put((gcovs_total, gcovs_skipped)) sys.exit(EXIT_CODE) def processGcdas(args, coverage_files, gcov_filter_options): chunk_size = max(args.minimum_chunk, int(len(coverage_files) / args.jobs) + 1) processes = [] data_q = multiprocessing.Queue() metrics_q = multiprocessing.Queue() for chunk in chunks(coverage_files, chunk_size): p = multiprocessing.Process(target=gcovWorker, args=(data_q, metrics_q, args, chunk, gcov_filter_options)) processes.append(p) p.start() logging.info("Spawned {} gcov processes, each processing at most {} coverage files".format(len(processes), chunk_size)) fastcov_jsons = [] for p in processes: fastcov_jsons.append(data_q.get()) incrementCounters(*metrics_q.get()) for p in processes: p.join() if p.exitcode != 0: setExitCodeRaw(p.exitcode) base_fastcov = fastcov_jsons.pop() for fj in fastcov_jsons: combineReports(base_fastcov, fj) return base_fastcov def shouldFilterSource(source, gcov_filter_options): """Returns true if the provided source file should be filtered due to CLI options, otherwise returns false.""" # If explicit sources were passed, check for match if gcov_filter_options["sources"]: if source not in gcov_filter_options["sources"]: logging.debug("Filtering coverage for '%s' due to option '--source-files'", source) return True # Check exclude filter for ex in gcov_filter_options["exclude"]: if ex in source: logging.debug("Filtering coverage for '%s' due to option '--exclude %s'", source, ex) return True # Check exclude filter for ex_glob in gcov_filter_options["exclude_glob"]: if fnmatch.fnmatch(source, ex_glob): logging.debug("Filtering coverage for '%s' due to option '--exclude-glob %s'", source, ex_glob) return True # Check include filter if gcov_filter_options["include"]: included = False for inc in gcov_filter_options["include"]: if inc in source: included = True break if not included: logging.debug("Filtering coverage for '%s' due to option '--include %s'", source, " ".join(gcov_filter_options["include"])) return True return False def filterFastcov(fastcov_json, args): logging.info("Performing filtering operations (if applicable)") gcov_filter_options = getGcovFilterOptions(args) for source in list(fastcov_json["sources"].keys()): if shouldFilterSource(source, gcov_filter_options): del fastcov_json["sources"][source] def processGcov(cwd, gcov, source_base_dir, files, gcov_filter_options): # Uses cwd if set, else source_base_dir from gcov json. If both are empty, uses "." base_dir = cwd if cwd else source_base_dir base_dir = base_dir if base_dir else "." # Add absolute path gcov["file_abs"] = os.path.abspath(os.path.join(base_dir, gcov["file"])) if shouldFilterSource(gcov["file_abs"], gcov_filter_options): return files.append(gcov) logging.debug("Accepted coverage for '%s'", gcov["file_abs"]) def processGcovs(cwd, gcov_files, source_base_dir, gcov_filter_options): files = [] for gcov in gcov_files: processGcov(cwd, gcov, source_base_dir, files, gcov_filter_options) return files def dumpBranchCoverageToLcovInfo(f, branches): branch_miss = 0 branch_found = 0 brda = [] for line_num, branch_counts in branches.items(): for i, count in enumerate(branch_counts): # Branch (, , , ) brda.append((line_num, int(i/2), i, count)) branch_miss += int(count == 0) branch_found += 1 for v in sorted(brda): f.write("BRDA:{},{},{},{}\n".format(*v)) f.write("BRF:{}\n".format(branch_found)) # Branches Found f.write("BRH:{}\n".format(branch_found - branch_miss)) # Branches Hit def dumpToLcovInfo(fastcov_json, output): with open(output, "w") as f: sources = fastcov_json["sources"] for sf in sorted(sources.keys()): for tn in sorted(sources[sf].keys()): data = sources[sf][tn] f.write("TN:{}\n".format(tn)) #Test Name - used mainly in conjuction with genhtml --show-details f.write("SF:{}\n".format(sf)) #Source File fn_miss = 0 fn = [] fnda = [] for function, fdata in data["functions"].items(): fn.append((fdata["start_line"], function)) # Function Start Line fnda.append((fdata["execution_count"], function)) # Function Hits fn_miss += int(fdata["execution_count"] == 0) # NOTE: lcov sorts FN, but not FNDA. for v in sorted(fn): f.write("FN:{},{}\n".format(*v)) for v in sorted(fnda): f.write("FNDA:{},{}\n".format(*v)) f.write("FNF:{}\n".format(len(data["functions"]))) #Functions Found f.write("FNH:{}\n".format((len(data["functions"]) - fn_miss))) #Functions Hit if data["branches"]: dumpBranchCoverageToLcovInfo(f, data["branches"]) line_miss = 0 da = [] for line_num, count in data["lines"].items(): da.append((line_num, count)) line_miss += int(count == 0) for v in sorted(da): f.write("DA:{},{}\n".format(*v)) # Line f.write("LF:{}\n".format(len(data["lines"]))) #Lines Found f.write("LH:{}\n".format((len(data["lines"]) - line_miss))) #Lines Hit f.write("end_of_record\n") def getSourceLines(source, fallback_encodings=[]): """Return a list of lines from the provided source, trying to decode with fallback encodings if the default fails.""" default_encoding = sys.getdefaultencoding() for encoding in [default_encoding] + fallback_encodings: try: with open(source, encoding=encoding) as f: return f.readlines() except UnicodeDecodeError: pass logging.warning("Could not decode '{}' with {} or fallback encodings ({}); ignoring errors".format(source, default_encoding, ",".join(fallback_encodings))) with open(source, errors="ignore") as f: return f.readlines() def containsMarker(markers, strBody): for marker in markers: if marker in strBody: return True return False # Returns whether source coverage changed or not def exclProcessSource(fastcov_sources, source, exclude_branches_sw, include_branches_sw, exclude_line_marker, fallback_encodings, gcov_prefix, gcov_prefix_strip): source_to_open = processPrefix(source, gcov_prefix, gcov_prefix_strip) # Before doing any work, check if this file even needs to be processed if not exclude_branches_sw and not include_branches_sw: # Ignore unencodable characters with open(source_to_open, errors="ignore") as f: if not containsMarker(exclude_line_marker + ["LCOV_EXCL"], f.read()): return False # If we've made it this far we have to check every line start_line = 0 end_line = 0 # Start enumeration at line 1 because the first line of the file is line 1 not 0 for i, line in enumerate(getSourceLines(source_to_open, fallback_encodings), 1): # Cycle through test names (likely only 1) for test_name in fastcov_sources[source]: fastcov_data = fastcov_sources[source][test_name] # Check if branch coverage should be deleted based on CLI options if (exclude_branches_sw or include_branches_sw) and (i in fastcov_data["branches"]): del_exclude_br = exclude_branches_sw and any(line.lstrip().startswith(e) for e in exclude_branches_sw) del_include_br = include_branches_sw and all(not line.lstrip().startswith(e) for e in include_branches_sw) if del_exclude_br or del_include_br: del fastcov_data["branches"][i] # Skip to next line as soon as possible if not containsMarker(exclude_line_marker + ["LCOV_EXCL"], line): continue # Build line to function dict so can quickly delete by line number line_to_func = {} for f in fastcov_data["functions"].keys(): l = fastcov_data["functions"][f]["start_line"] if l not in line_to_func: line_to_func[l] = set() line_to_func[l].add(f) if any(marker in line for marker in exclude_line_marker): for key in ["lines", "branches"]: if i in fastcov_data[key]: del fastcov_data[key][i] if i in line_to_func: for key in line_to_func[i]: if key in fastcov_data["functions"]: del fastcov_data["functions"][key] elif "LCOV_EXCL_START" in line: start_line = i elif "LCOV_EXCL_STOP" in line: end_line = i if not start_line: end_line = 0 continue for key in ["lines", "branches"]: for line_num in list(fastcov_data[key].keys()): if start_line <= line_num <= end_line: del fastcov_data[key][line_num] for line_num in range(start_line, end_line): if line_num in line_to_func: for key in line_to_func[line_num]: if key in fastcov_data["functions"]: del fastcov_data["functions"][key] start_line = end_line = 0 elif "LCOV_EXCL_BR_LINE" in line: if i in fastcov_data["branches"]: del fastcov_data["branches"][i] # Source coverage changed return True def exclMarkerWorker(data_q, fastcov_sources, chunk, exclude_branches_sw, include_branches_sw, exclude_line_marker, fallback_encodings, gcov_prefix, gcov_prefix_strip): changed_sources = [] for source in chunk: try: if exclProcessSource(fastcov_sources, source, exclude_branches_sw, include_branches_sw, exclude_line_marker, fallback_encodings, gcov_prefix, gcov_prefix_strip): changed_sources.append((source, fastcov_sources[source])) except FileNotFoundError: logging.error("Could not find '%s' to scan for exclusion markers...", source) setExitCode("excl_not_found") # Set exit code because of error # Write out changed sources back to main fastcov file data_q.put(changed_sources) # Exit current process with appropriate code sys.exit(EXIT_CODE) def processExclusionMarkers(fastcov_json, jobs, exclude_branches_sw, include_branches_sw, exclude_line_marker, min_chunk_size, fallback_encodings, gcov_prefix, gcov_prefix_strip): chunk_size = max(min_chunk_size, int(len(fastcov_json["sources"]) / jobs) + 1) processes = [] data_q = multiprocessing.Queue() for chunk in chunks(list(fastcov_json["sources"].keys()), chunk_size): p = multiprocessing.Process(target=exclMarkerWorker, args=(data_q, fastcov_json["sources"], chunk, exclude_branches_sw, include_branches_sw, exclude_line_marker, fallback_encodings, gcov_prefix, gcov_prefix_strip)) processes.append(p) p.start() logging.info("Spawned {} exclusion marker scanning processes, each processing at most {} source files".format(len(processes), chunk_size)) changed_sources = [] for p in processes: changed_sources += data_q.get() for p in processes: p.join() if p.exitcode != 0: setExitCodeRaw(p.exitcode) for changed_source in changed_sources: fastcov_json["sources"][changed_source[0]] = changed_source[1] def validateSources(fastcov_json, gcov_prefix, gcov_prefix_strip): logging.info("Checking if all sources exist") for source in fastcov_json["sources"].keys(): source = processPrefix(source, gcov_prefix, gcov_prefix_strip) if not os.path.exists(source): logging.error("Cannot find '{}'".format(source)) def distillFunction(function_raw, functions): function_name = function_raw["name"] # NOTE: need to explicitly cast all counts coming from gcov to int - this is because gcov's json library # will pass as scientific notation (i.e. 12+e45) start_line = int(function_raw["start_line"]) execution_count = int(function_raw["execution_count"]) if function_name not in functions: functions[function_name] = { "start_line": start_line, "execution_count": execution_count } else: functions[function_name]["execution_count"] += execution_count def emptyBranchSet(branch1, branch2): return (branch1["count"] == 0 and branch2["count"] == 0) def matchingBranchSet(branch1, branch2): return (branch1["count"] == branch2["count"]) def filterExceptionalBranches(branches): filtered_branches = [] exception_branch = False for i in range(0, len(branches), 2): if i+1 >= len(branches): filtered_branches.append(branches[i]) break # Filter exceptional branch noise if branches[i+1]["throw"]: exception_branch = True continue # Filter initializer list noise if exception_branch and emptyBranchSet(branches[i], branches[i+1]) and len(filtered_branches) >= 2 and matchingBranchSet(filtered_branches[-1], filtered_branches[-2]): return [] filtered_branches.append(branches[i]) filtered_branches.append(branches[i+1]) return filtered_branches def distillLine(line_raw, lines, branches, include_exceptional_branches): line_number = int(line_raw["line_number"]) count = int(line_raw["count"]) if count < 0: if "function_name" in line_raw: logging.warning("Ignoring negative count found in '%s'.", line_raw["function_name"]) else: logging.warning("Ignoring negative count.") count = 0 if line_number not in lines: lines[line_number] = count else: lines[line_number] += count # Filter out exceptional branches by default unless requested otherwise if not include_exceptional_branches: line_raw["branches"] = filterExceptionalBranches(line_raw["branches"]) # Increment all branch counts for i, branch in enumerate(line_raw["branches"]): if line_number not in branches: branches[line_number] = [] blen = len(branches[line_number]) glen = len(line_raw["branches"]) if blen < glen: branches[line_number] += [0] * (glen - blen) branches[line_number][i] += int(branch["count"]) def distillSource(source_raw, sources, test_name, include_exceptional_branches): source_name = source_raw["file_abs"] if source_name not in sources: sources[source_name] = { test_name: { "functions": {}, "branches": {}, "lines": {} } } for function in source_raw["functions"]: distillFunction(function, sources[source_name][test_name]["functions"]) for line in source_raw["lines"]: distillLine(line, sources[source_name][test_name]["lines"], sources[source_name][test_name]["branches"], include_exceptional_branches) def dumpToJson(intermediate, output): with open(output, "w") as f: json.dump(intermediate, f) def getGcovFilterOptions(args): return { "sources": set([os.path.abspath(s) for s in args.sources]), #Make paths absolute, use set for fast lookups "include": args.includepost, "exclude": args.excludepost, "exclude_glob":args.excludepost_glob } def addDicts(dict1, dict2): """Add dicts together by value. i.e. addDicts({"a":1,"b":0}, {"a":2}) == {"a":3,"b":0}.""" result = {k:v for k,v in dict1.items()} for k,v in dict2.items(): if k in result: result[k] += v else: result[k] = v return result def addLists(list1, list2): """Add lists together by value. i.e. addLists([1,1], [2,2]) == [3,3].""" # Find big list and small list blist, slist = list(list2), list(list1) if len(list1) > len(list2): blist, slist = slist, blist # Overlay small list onto big list for i, b in enumerate(slist): blist[i] += b return blist def combineReports(base, overlay): for source, scov in overlay["sources"].items(): # Combine Source Coverage if source not in base["sources"]: base["sources"][source] = scov continue for test_name, tcov in scov.items(): # Combine Source Test Name Coverage if test_name not in base["sources"][source]: base["sources"][source][test_name] = tcov continue # Drill down and create convenience variable base_data = base["sources"][source][test_name] # Combine Line Coverage base_data["lines"] = addDicts(base_data["lines"], tcov["lines"]) # Combine Branch Coverage for branch, cov in tcov["branches"].items(): if branch not in base_data["branches"]: base_data["branches"][branch] = cov else: base_data["branches"][branch] = addLists(base_data["branches"][branch], cov) # Combine Function Coverage for function, cov in tcov["functions"].items(): if function not in base_data["functions"]: base_data["functions"][function] = cov else: base_data["functions"][function]["execution_count"] += cov["execution_count"] def parseInfo(path): """Parse an lcov .info file into fastcov json.""" fastcov_json = { "sources": {} } with open(path) as f: current_test_name = "" for line in f: if line.startswith("TN:"): current_test_name = line[3:].strip() elif line.startswith("SF:"): current_sf = line[3:].strip() fastcov_json["sources"].setdefault(current_sf, { current_test_name: { "functions": {}, "branches": {}, "lines": {}, } }) current_data = fastcov_json["sources"][current_sf][current_test_name] elif line.startswith("FN:"): line_nums, function_name = line[3:].strip().rsplit(",", maxsplit=1) line_num_start = line_nums.split(",")[0] current_data["functions"][function_name] = {} current_data["functions"][function_name]["start_line"] = tryParseNumber(line_num_start) elif line.startswith("FNDA:"): count, function_name = line[5:].strip().split(",") current_data["functions"][function_name]["execution_count"] = tryParseNumber(count) elif line.startswith("DA:"): line_num, count = line[3:].strip().split(",") current_data["lines"][line_num] = tryParseNumber(count) elif line.startswith("BRDA:"): branch_tokens = line[5:].strip().split(",") line_num, count = branch_tokens[0], branch_tokens[-1] if line_num not in current_data["branches"]: current_data["branches"][line_num] = [] current_data["branches"][line_num].append(tryParseNumber(count)) return fastcov_json def convertKeysToInt(report): for source in report["sources"].keys(): for test_name in report["sources"][source].keys(): report_data = report["sources"][source][test_name] report_data["lines"] = {int(k):v for k,v in report_data["lines"].items()} report_data["branches"] = {int(k):v for k,v in report_data["branches"].items()} def parseAndCombine(paths): base_report = {} for path in paths: if path.endswith(".json"): with open(path) as f: report = json.load(f) elif path.endswith(".info"): report = parseInfo(path) else: logging.error("Currently only fastcov .json and lcov .info supported for combine operations, aborting due to %s...\n", path) sys.exit(EXIT_CODES["unsupported_coverage_format"]) # In order for sorting to work later when we serialize, # make sure integer keys are int convertKeysToInt(report) if not base_report: base_report = report logging.info("Setting {} as base report".format(path)) else: combineReports(base_report, report) logging.info("Adding {} to base report".format(path)) return base_report def getCombineCoverage(args): logging.info("Performing combine operation") fastcov_json = parseAndCombine(args.combine) filterFastcov(fastcov_json, args) return fastcov_json def getGcovCoverage(args): # Need at least python 3.5 because of use of recursive glob checkPythonVersion(sys.version_info[0:2]) # Need at least gcov 9.0.0 because that's when gcov JSON and stdout streaming was introduced checkGcovVersion(getGcovVersion(args.gcov)) # Get list of gcda files to process coverage_files = findCoverageFiles(args.directory, args.coverage_files, args.use_gcno) # If gcda/gcno filtering is enabled, filter them out now if args.excludepre: coverage_files = getFilteredCoverageFiles(coverage_files, args.excludepre) logging.info("Found {} coverage files after filtering".format(len(coverage_files))) # We "zero" the "counters" by simply deleting all gcda files if args.zerocounters: removeFiles(globCoverageFiles(args.directory, GCOV_GCDA_EXT)) logging.info("Removed {} .gcda files".format(len(coverage_files))) sys.exit() if not coverage_files: logging.error("No coverage files found in directory '%s'", args.directory) setExitCode("no_coverage_files") sys.exit(EXIT_CODE) # Fire up one gcov per cpu and start processing gcdas gcov_filter_options = getGcovFilterOptions(args) fastcov_json = processGcdas(args, coverage_files, gcov_filter_options) # Summarize processing results logging.info("Processed {} .gcov files ({} total, {} skipped)".format(GCOVS_TOTAL - GCOVS_SKIPPED, GCOVS_TOTAL, GCOVS_SKIPPED)) logging.debug("Final report will contain coverage for the following %d source files:\n %s", len(fastcov_json["sources"]), "\n ".join(fastcov_json["sources"])) return fastcov_json def formatCoveredItems(covered, total): coverage = (covered * 100.0) / total if total > 0 else 100.0 coverage = round(coverage, 2) return "{:.2f}%, {}/{}".format(coverage, covered, total) def dumpStatistic(fastcov_json): total_lines = 0 covered_lines = 0 total_functions = 0 covered_functions = 0 total_files = len(fastcov_json["sources"]) covered_files = 0 for source_name, source in fastcov_json["sources"].items(): is_file_covered = False for test_name, test in source.items(): total_lines += len(test["lines"]) for execution_count in test["lines"].values(): covered_lines += 1 if execution_count > 0 else 0 is_file_covered = is_file_covered or execution_count > 0 total_functions += len(test["functions"]) for function in test["functions"].values(): covered_functions += 1 if function['execution_count'] > 0 else 0 is_file_covered = is_file_covered or function['execution_count'] > 0 if is_file_covered: covered_files = covered_files + 1 logging.info("Files Coverage: {}".format(formatCoveredItems(covered_files, total_files))) logging.info("Functions Coverage: {}".format(formatCoveredItems(covered_functions, total_functions))) logging.info("Lines Coverage: {}".format(formatCoveredItems(covered_lines, total_lines))) def dumpFile(fastcov_json, args): if args.lcov: dumpToLcovInfo(fastcov_json, args.output) logging.info("Created lcov info file '{}'".format(args.output)) else: dumpToJson(fastcov_json, args.output) logging.info("Created fastcov json file '{}'".format(args.output)) if args.dump_statistic: dumpStatistic(fastcov_json) def tupleToDotted(tup): return ".".join(map(str, tup)) def parseArgs(): parser = argparse.ArgumentParser(description='A parallel gcov wrapper for fast coverage report generation') parser.add_argument('-z', '--zerocounters', dest='zerocounters', action="store_true", help='Recursively delete all gcda files') # Enable Branch Coverage parser.add_argument('-b', '--branch-coverage', dest='branchcoverage', action="store_true", help='Include only the most useful branches in the coverage report.') parser.add_argument('-B', '--exceptional-branch-coverage', dest='xbranchcoverage', action="store_true", help='Include ALL branches in the coverage report (including potentially noisy exceptional branches).') parser.add_argument('-A', '--exclude-br-lines-starting-with', dest='exclude_branches_sw', nargs="+", metavar='', default=[], help='Exclude branches from lines starting with one of the provided strings (i.e. assert, return, etc.)') parser.add_argument('-a', '--include-br-lines-starting-with', dest='include_branches_sw', nargs="+", metavar='', default=[], help='Include only branches from lines starting with one of the provided strings (i.e. if, else, while, etc.)') parser.add_argument('-X', '--skip-exclusion-markers', dest='skip_exclusion_markers', action="store_true", help='Skip reading source files to search for lcov exclusion markers (such as "LCOV_EXCL_LINE")') parser.add_argument('-x', '--scan-exclusion-markers', dest='scan_exclusion_markers', action="store_true", help='(Combine operations) Force reading source files to search for lcov exclusion markers (such as "LCOV_EXCL_LINE")') # Capture untested file coverage as well via gcno parser.add_argument('-n', '--process-gcno', dest='use_gcno', action="store_true", help='Process both gcno and gcda coverage files. This option is useful for capturing untested files in the coverage report.') # Filtering Options parser.add_argument('-s', '--source-files', dest='sources', nargs="+", metavar='', default=[], help='Filter: Specify exactly which source files should be included in the final report. Paths must be either absolute or relative to current directory.') parser.add_argument('-e', '--exclude', dest='excludepost', nargs="+", metavar='', default=[], help='Filter: Exclude source files from final report if they contain one of the provided substrings (i.e. /usr/include test/, etc.)') parser.add_argument('-eg', '--exclude-glob', dest='excludepost_glob', nargs="+", metavar='', default=[], help='Filter: Exclude source files by glob pattern from final report if they contain one of the provided substrings (i.e. /usr/include test/, etc.)') parser.add_argument('-i', '--include', dest='includepost', nargs="+", metavar='', default=[], help='Filter: Only include source files in final report that contain one of the provided substrings (i.e. src/ etc.)') parser.add_argument('-f', '--gcda-files', dest='coverage_files', nargs="+", metavar='', default=[], help='Filter: Specify exactly which gcda or gcno files should be processed. Note that specifying gcno causes both gcno and gcda to be processed.') parser.add_argument('-E', '--exclude-gcda', dest='excludepre', nargs="+", metavar='', default=[], help='Filter: Exclude gcda or gcno files from being processed via simple find matching (not regex)') parser.add_argument('-u', '--diff-filter', dest='diff_file', default='', help='Unified diff file with changes which will be included into final report') parser.add_argument('-ub', '--diff-base-dir', dest='diff_base_dir', default='', help='Base directory for sources in unified diff file, usually repository dir') parser.add_argument('-ce', '--custom-exclusion-marker', dest='exclude_line_marker', nargs="+", metavar='', default=["LCOV_EXCL_LINE"], help='Filter: Add filter for lines that will be excluded from coverage (same behavior as "LCOV_EXCL_LINE")') parser.add_argument('-g', '--gcov', dest='gcov', default='gcov', help='Which gcov binary to use') parser.add_argument('-d', '--search-directory', dest='directory', default=".", help='Base directory to recursively search for gcda files (default: .)') parser.add_argument('-c', '--compiler-directory', dest='cdirectory', default="", help='Base directory compiler was invoked from (default: . or read from gcov) \ This needs to be set if invoking fastcov from somewhere other than the base compiler directory. No need to set it if gcc version > 9.1') parser.add_argument('-j', '--jobs', dest='jobs', type=int, default=multiprocessing.cpu_count(), help='Number of parallel gcov to spawn (default: {}).'.format(multiprocessing.cpu_count())) parser.add_argument('-m', '--minimum-chunk-size', dest='minimum_chunk', type=int, default=5, help='Minimum number of files a thread should process (default: 5). \ If you have only 4 gcda files but they are monstrously huge, you could change this value to a 1 so that each thread will only process 1 gcda. Otherwise fastcov will spawn only 1 thread to process all of them.') parser.add_argument('-F', '--fallback-encodings', dest='fallback_encodings', nargs="+", metavar='', default=[], help='List of encodings to try if opening a source file with the default fails (i.e. latin1, etc.). This option is not usually needed.') parser.add_argument('-l', '--lcov', dest='lcov', action="store_true", help='Output in lcov info format instead of fastcov json') parser.add_argument('-o', '--output', dest='output', default="", help='Name of output file (default: coverage.json or coverage.info, depends on --lcov option)') parser.add_argument('-q', '--quiet', dest='quiet', action="store_true", help='Suppress output to stdout') parser.add_argument('-t', '--test-name', dest='test_name', default="", help='Specify a test name for the coverage. Equivalent to lcov\'s `-t`.') parser.add_argument('-C', '--add-tracefile', dest='combine', nargs="+", help='Combine multiple coverage files into one. If this flag is specified, fastcov will do a combine operation instead invoking gcov. Equivalent to lcov\'s `-a`.') parser.add_argument('-V', '--verbose', dest="verbose", action="store_true", help="Print more detailed information about what fastcov is doing") parser.add_argument('-w', '--validate-sources', dest="validate_sources", action="store_true", help="Check if every source file exists") parser.add_argument('-p', '--dump-statistic', dest="dump_statistic", action="store_true", help="Dump total statistic at the end") parser.add_argument('-v', '--version', action="version", version='%(prog)s {version}'.format(version=__version__), help="Show program's version number and exit") parser.add_argument('-gps', '--gcov_prefix_strip', dest="gcov_prefix_strip", action="store", default=0, type=int, help="The number of initial directory names to strip off the absolute paths in the object file.") parser.add_argument('-gp', '--gcov_prefix', dest="gcov_prefix", action="store", default="", help="The prefix to add to the paths in the object file.") args = parser.parse_args() if not args.output: args.output = 'coverage.info' if args.lcov else 'coverage.json' return args def checkPythonVersion(version): """Exit if the provided python version is less than the supported version.""" if version < MINIMUM_PYTHON: sys.stderr.write("Minimum python version {} required, found {}\n".format(tupleToDotted(MINIMUM_PYTHON), tupleToDotted(version))) sys.exit(EXIT_CODES["python_version"]) def checkGcovVersion(version): """Exit if the provided gcov version is less than the supported version.""" if version < MINIMUM_GCOV: sys.stderr.write("Minimum gcov version {} required, found {}\n".format(tupleToDotted(MINIMUM_GCOV), tupleToDotted(version))) sys.exit(EXIT_CODES["gcov_version"]) def setupLogging(quiet, verbose): handler = logging.StreamHandler() handler.setFormatter(FastcovFormatter("[%(levelname)s]: %(message)s")) root = logging.getLogger() root.setLevel(logging.INFO) root.addHandler(handler) if not quiet: logging.disable(level=logging.NOTSET) # Re-enable logging if verbose: root.setLevel(logging.DEBUG) def main(): args = parseArgs() # Setup logging setupLogging(args.quiet, args.verbose) if args.gcov_prefix_strip > 0: os.environ["GCOV_PREFIX_STRIP"] = str(args.gcov_prefix_strip) if len(args.gcov_prefix) > 0: os.environ["GCOV_PREFIX"] = args.gcov_prefix # Get report from appropriate source if args.combine: fastcov_json = getCombineCoverage(args) skip_exclusion_markers = not args.scan_exclusion_markers else: fastcov_json = getGcovCoverage(args) skip_exclusion_markers = args.skip_exclusion_markers # Scan for exclusion markers if not skip_exclusion_markers: processExclusionMarkers(fastcov_json, args.jobs, args.exclude_branches_sw, args.include_branches_sw, args.exclude_line_marker, args.minimum_chunk, args.fallback_encodings, args.gcov_prefix, args.gcov_prefix_strip) logging.info("Scanned {} source files for exclusion markers".format(len(fastcov_json["sources"]))) if args.diff_file: logging.info("Filtering according to {} file".format(args.diff_file)) DiffParser().filterByDiff(args.diff_file, args.diff_base_dir, fastcov_json, args.fallback_encodings) if args.validate_sources: validateSources(fastcov_json, args.gcov_prefix, args.gcov_prefix_strip) # Dump to desired file format dumpFile(fastcov_json, args) # If there was an error along the way, but we still completed the pipeline... if EXIT_CODE: sys.exit(EXIT_CODE) # Set package version... it's way down here so that we can call tupleToDotted __version__ = tupleToDotted(FASTCOV_VERSION) if __name__ == '__main__': main() verilator-5.044/nodist/verilator_saif_diff0000755000542200017500000002361515125463617021363 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # pylint: disable=C0114,C0115,C0116,C0301,R0902,R0903,R0912,R0915,W0719,W0718 ###################################################################### # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import argparse import re SUCCESS_CODE = 0 FAILURE_CODE = 1 INSTANCE_TYPE = "INSTANCE" NET_LIST_TYPE = "NET" SIGNAL_TYPE = "SIGNAL" EOF_ERROR = "Unexpected EOF" def saif_assert(expression: bool, message: str) -> None: if not expression: raise Exception(message) def saif_error(message: str) -> None: raise Exception(message) class SAIFSignalBit: name: str high_time: int low_time: int transitions: int def __init__(self, name: str): self.name = name self.high_time = 0 self.low_time = 0 self.transitions = 0 class SAIFInstance: def __init__(self, scope_name: str): self.scope_name = scope_name self.parent_instance = None self.nets = {} self.child_instances = {} class SAIFToken: def __init__(self, token: str): self.token = token self.type = '' self.value = '' class SAIFParser: def __init__(self): self.token_stack = [] # For parsing simplicity self.token_stack.append(SAIFToken('saif_root')) self.current_instance = None self.has_saifile_header = False self.direction = '' self.saif_version = '' self.top_instances = {} self.duration = '' self.divider = '' self.timescale = '' def parse(self, saif_filename: str) -> None: file_contents = '' with open(saif_filename, 'r', encoding="utf8") as saif_file: content = saif_file.readlines() filtered_lines = [line for line in content if not line.strip().startswith('//')] file_contents = ''.join(filtered_lines) tokens = file_contents.replace('(', ' ( ').replace(')', ' ) ').split() num_of_tokens = len(tokens) index = 0 while index < num_of_tokens: token = tokens[index] index += 1 if token == '(': self.token_stack.append(SAIFToken(token)) self.token_stack[-1].type = self.token_stack[-2].type self.token_stack[-1].value = self.token_stack[-2].value continue if token == ')': if self.token_stack[-1].type == INSTANCE_TYPE: self.current_instance = self.current_instance.parent_instance self.token_stack.pop() continue if re.match(r'SAIFILE', token): self.has_saifile_header = True continue if re.match(r'DIRECTION', token): saif_assert(index < num_of_tokens, EOF_ERROR) self.direction = tokens[index].replace('\"', '') index += 1 continue if re.match(r'SAIFVERSION', token): saif_assert(index < num_of_tokens, EOF_ERROR) self.saif_version = tokens[index].replace('\"', '') index += 1 continue if re.match(r'DESIGN|DATE|VENDOR|PROGRAM_NAME|VERSION', token): # NOP, only skip value saif_assert(index < num_of_tokens, EOF_ERROR) index += 1 continue if re.match(r'DIVIDER', token): saif_assert(index < num_of_tokens, EOF_ERROR) self.divider = tokens[index] index += 1 continue if re.match(r'TIMESCALE', token): saif_assert(index < num_of_tokens, EOF_ERROR) self.timescale = tokens[index] index += 1 continue if re.match(r'DURATION', token): saif_assert(index < num_of_tokens, EOF_ERROR) self.duration = tokens[index] index += 1 continue if re.match(r'INSTANCE', token): saif_assert(index < num_of_tokens, EOF_ERROR) instance_name = tokens[index] index += 1 self.token_stack[-1].type = INSTANCE_TYPE self.token_stack[-1].value = instance_name instance = SAIFInstance(instance_name) if self.current_instance is None: self.top_instances[instance_name] = instance else: self.current_instance.child_instances[instance_name] = instance instance.parent_instance = self.current_instance self.current_instance = instance continue if re.match(r'NET', token): self.token_stack[-1].type = NET_LIST_TYPE continue if re.match(r'T1', token): net_name = self.token_stack[-1].value saif_assert(index < num_of_tokens, EOF_ERROR) self.current_instance.nets[net_name].high_time = tokens[index] index += 1 continue if re.match(r'T0', token): net_name = self.token_stack[-1].value saif_assert(index < num_of_tokens, EOF_ERROR) self.current_instance.nets[net_name].low_time = tokens[index] index += 1 continue if re.match(r'TC', token): net_name = self.token_stack[-1].value saif_assert(index < num_of_tokens, EOF_ERROR) self.current_instance.nets[net_name].transitions = tokens[index] index += 1 continue if re.match(r'TZ|TX|TB|TG|IG|IK', token): # NOP, only skip value index += 1 continue if self.token_stack[-2].type == NET_LIST_TYPE: self.token_stack[-1].type = SIGNAL_TYPE self.token_stack[-1].value = token self.current_instance.nets[token] = SAIFSignalBit(token) saif_assert(self.has_saifile_header, "SAIF file doesn't contain a SAIFILE keyword") saif_assert(self.direction == "backward", f"SAIF file doesn't have a valid/compatible direction: {self.direction}") saif_assert(self.saif_version == "2.0", f"SAIF file doesn't have a valid/compatible version: {self.saif_version}") # Only 'saif_root' token should be left saif_assert(len(self.token_stack) == 1, "Incorrect nesting of scopes") def compare_saif_instances(first: SAIFInstance, second: SAIFInstance) -> None: if len(first.nets) != len(second.nets): saif_error(f"Number of nets doesn't match in {first.scope_name}: " f"{len(first.nets)} != {len(second.nets)}") for signal_name, saif_signal in first.nets.items(): if signal_name not in second.nets: saif_error(f"Signal {signal_name} doesn't exist in the second object\n") other_signal = second.nets[signal_name] if (saif_signal.high_time != other_signal.high_time or saif_signal.low_time != other_signal.low_time or saif_signal.transitions != other_signal.transitions): saif_error("Incompatible signal bit parameters in " f"{signal_name}\n") if len(first.child_instances) != len(second.child_instances): saif_error(f"Number of child instances doesn't match in {first.scope_name}: " f"{len(first.child_instances)} != {len(second.child_instances)}") for instance_name, instance in first.child_instances.items(): if instance_name not in second.child_instances: saif_error(f"Instance {instance_name} doesn't exist in the second object\n") compare_saif_instances(instance, second.child_instances[instance_name]) def compare_saif_contents(first_file: str, second_file: str) -> int: """Test if second SAIF file has the same values as the first""" first_saif = SAIFParser() first_saif.parse(first_file) second_saif = SAIFParser() second_saif.parse(second_file) if first_saif.duration != second_saif.duration: saif_error("Duration of trace doesn't match: " f"{first_saif.duration} != {second_saif.duration}") if first_saif.divider != second_saif.divider: saif_error(f"Dividers don't match: {first_saif.divider} != {second_saif.divider}") if first_saif.timescale != second_saif.timescale: saif_error(f"Timescale doesn't match: {first_saif.timescale} != {second_saif.timescale}") if len(first_saif.top_instances) != len(second_saif.top_instances): saif_error("Number of top instances doesn't match: " f"{len(first_saif.top_instances)} != {len(second_saif.top_instances)}") for top_instance_name, top_instance in first_saif.top_instances.items(): if top_instance_name not in second_saif.top_instances: saif_error(f"Top instance {top_instance_name} missing in other SAIF") compare_saif_instances(top_instance, second_saif.top_instances[top_instance_name]) return SUCCESS_CODE parser = argparse.ArgumentParser( allow_abbrev=False, formatter_class=argparse.RawDescriptionHelpFormatter, description= """verilator_saif_diff checks if two SAIF files are logically-identical. It returns first encountered difference as output. Run as: cd $VERILATOR_ROOT nodist/code_coverage --first example.saif --second other.saif""") parser.add_argument('--first', action='store', help='First SAIF file') parser.add_argument('--second', action='store', help='Second SAIF file') parser.set_defaults(stop=True) args = parser.parse_args() try: compare_saif_contents(args.first, args.second) except Exception as error: print(error) verilator-5.044/nodist/lint_py_test_filter0000755000542200017500000000357315125463617021445 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # mypy: disallow-untyped-defs # pylint: disable=C0114,C0116 ###################################################################### import argparse import sys SUPPRESSES = [ "**********", "E0602: Undefined variable 'test' (undefined-variable)", "E0602: Undefined variable 're' (undefined-variable)", "E0602: Undefined variable 'os' (undefined-variable)", "E0602: Undefined variable 'glob' (undefined-variable)", "W0611: Unused import vltest_bootstrap (unused-import)", ] ###################################################################### def process() -> None: anymsg = False for line in sys.stdin: line = line.rstrip() show = True for msg in SUPPRESSES: if msg in line: show = False continue if show: print(line) anymsg = True if anymsg: sys.exit("%Error: See messages above") ####################################################################### ####################################################################### parser = argparse.ArgumentParser( allow_abbrev=False, formatter_class=argparse.RawDescriptionHelpFormatter, description="""lint_py_test_filter is used to filter pylint output for expected errors in Verilator test_regress/*.py tests.""", epilog="""Copyright 2024-2026 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") parser.add_argument('--debug', action='store_true', help='enable debug') Args = parser.parse_args() process() ###################################################################### # Local Variables: # compile-command: "cd .. ; make lint-py-pylint-tests" # End: verilator-5.044/nodist/uvm_pkg_packer0000755000542200017500000000602415125463617020352 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # mypy: disallow-untyped-defs # pylint: disable=C0114,C0116 ###################################################################### import argparse import re import sys ###################################################################### def process() -> None: in_header = True in_backslash = None for line in sys.stdin: line = line.rstrip() line = line.expandtabs(tabsize=8) line = re.sub(r', +', ', ', line) line = re.sub(r'"/[^"]+/src/', '"t/uvm/src/', line) # Replace header if in_header: if re.match(r'^//', line): continue in_header = False print_header() in_header = False # Drop some unneeded items if re.match(r'^`begin_keywords ', line): continue if re.match(r'^`line ', line): continue if re.match(r'^\s*$', line) and not in_backslash: continue if re.match(r'^ *endpackage', line): print(line) break in_backslash = re.search(r'\\$', line) print(line) def print_header() -> None: print("// DESCR" "IPTION: Verilator: Concatenated UVM header for internal testing") print("// SPDX-" "License-Identifier: Apache-2.0") print("//----------------------------------------------------------------------") print("// To recreate:") print("// Using verilator_ext_tests:") print("// " + Args.test_name + " --gold") # Copy the copyright header from original sources with open(Args.uvm_header_filename, 'r', encoding="utf8") as fh: for line in fh: line = line.strip() line = line.expandtabs(tabsize=8) if not re.match(r'^//', line): break print(line) ####################################################################### ####################################################################### parser = argparse.ArgumentParser( allow_abbrev=False, formatter_class=argparse.RawDescriptionHelpFormatter, description="""uvm_pkg_packer is used to create the test_regress uvm_pkg libraries from sources in verilator_ext_test repository's tests.""", epilog="""Copyright 2025-2026 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") parser.add_argument('--debug', action='store_true', help='enable debug') parser.add_argument('--test-name', type=str, required=True, help='name of test to run to recreate') parser.add_argument('--uvm-header-filename', type=str, required=True, help='filename of uvm_pkg.sv') Args = parser.parse_args() process() ###################################################################### # Local Variables: # compile-command: "cd $VE && t/t_uvm_hello_v2017_1_0_nodpi.py" # End: verilator-5.044/nodist/dot_importer0000755000542200017500000000707115125463617020067 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # mypy: disallow-untyped-defs # pylint: disable=C0103,C0114,C0115,C0116,C0209,C0301 ###################################################################### import argparse import re ###################################################################### Header = [] Vertexes = [] Edges = [] ####################################################################### def dotread(filename: str) -> None: with open(filename, "r", encoding="utf8") as fh: header = True vnum = 0 vertex_re = re.compile(r'^\t([a-zA-Z0-9_]+)\t(.*)$') edge_re = re.compile(r'^\t([a-zA-Z0-9_]+)\s+->\s+([a-zA-Z0-9_]+)\s*(.*)$') for line in fh: vertex_match = re.search(vertex_re, line) edge_match = re.search(edge_re, line) if vertex_match: if vertex_match.group(1) != 'nTITLE': header = False Vertexes.append({'num': vnum, 'line': line, 'name': vertex_match.group(1)}) vnum += 1 elif edge_match: fromv = edge_match.group(1) tov = edge_match.group(2) w = re.match(r'weight=(\d+)', line) weight = w.group(1) if w else 1 w = re.match(r'style=(\S+)', line) cutable = w.group(1) if w else None edge = { 'num': vnum, 'line': line, 'weight': weight, 'cutable': cutable, 'from': fromv, 'to': tov } vnum += 1 Edges.append(edge) elif header: Header.append(line) print("IGNORE: " + line) ####################################################################### def cwrite(filename: str) -> None: with open(filename, "w", encoding="utf8") as fh: fh.write("void V3GraphTestImport::dotImport() {\n") fh.write(" auto* gp = &m_graph;\n") for ver in sorted(Vertexes, key=lambda ver: ver['num']): fh.write(" auto* %s = new V3GraphTestVertex{gp, \"%s\"}; if (%s) {}\n" % (ver['name'], ver['name'], ver['name'])) fh.write("\n") for edge in Edges: fh.write( " new V3GraphEdge{gp, %s, %s, %s, %s};\n" % (edge['from'], edge['to'], edge['weight'], "true" if edge['cutable'] else "false")) fh.write("}\n") ###################################################################### # main parser = argparse.ArgumentParser( allow_abbrev=False, formatter_class=argparse.RawDescriptionHelpFormatter, description="""dot_importer takes a graphvis .dot file and converts into .cpp file. This x.cpp file is then manually included in V3GraphTest.cpp to verify various xsub-algorithms.""", epilog="""Copyright 2005-2026 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") parser.add_argument('--debug', action='store_const', const=9, help='enable debug') parser.add_argument('filename', help='input .dot filename to process') Args = parser.parse_args() dotread(Args.filename) cwrite("graph_export.cpp") ###################################################################### # Local Variables: # compile-command: "./dot_importer ../test_regress/obj_vlt/t_EXAMPLE/*orderg_o*.dot && cat graph_export.cpp" # End: verilator-5.044/nodist/log_changes0000755000542200017500000001024615125463617017627 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # mypy: disallow-untyped-defs # pylint: disable=C0114,C0116,C0209,R0911,R0912,R0914,R0915 ###################################################################### import argparse import os import re #from pprint import pprint,pformat ####################################################################### def message_section(msg: str) -> int: """Return sorting-section number for given commit message""" if re.match(r'^Support', msg, flags=re.IGNORECASE): return 10 if re.match(r'^Add', msg, flags=re.IGNORECASE): return 20 if re.match(r'^Improve', msg, flags=re.IGNORECASE): return 30 if re.match(r'^Fix', msg, flags=re.IGNORECASE): return 40 if re.match(r'^(Internals|CI|Tests)', msg, flags=re.IGNORECASE): return -1 if re.match(r'^Bump.* from .* to .*', msg, flags=re.IGNORECASE): # dependabot return -1 return 0 def process() -> None: cmd = "git log" msgs = {} msg_authors = {} with os.popen(cmd) as fh: author = "" lineno = 0 key = None for line in fh: lineno += 1 line = line.rstrip() # print("l %s" % line) if re.match(r'^Date', line): key = None continue if re.match(r'^commit', line): key = None continue if re.search(r'Commentary: Changes update', line): break am = re.match(r'^Author: (.*) <(.*)>', line) dm = re.match(r'^ +(.*)', line) if am: email = am.group(2) author = am.group(1) if re.search(r'antmicro', email): author += ", Antmicro Ltd." if re.search(r'github action', author): author = "" continue elif author != "" and dm: msg = dm.group(1) mid = re.search(r'\(#([0-9][0-9][0-9][0-9]+)', line) if mid: bug_id = mid.group(1) else: bug_id = " %d" % lineno section = message_section(msg) if section >= 0: key = "%06s_%06s_%06d" % (section, bug_id, lineno) msgs[key] = '* ' + msg msg_authors[key] = author # print("i [%s] %s [%s]" % (key, msg, author)) author = "" elif key: m = re.search(r'(fix|fixes) *#\(?([0-9][0-9][0-9][0-9]+)', line, flags=re.IGNORECASE) if m: # print("K %s" % line) msgs[key] += ' (#' + m.group(2) + ')' if not msgs: print("No Changes need to be inserted.") return print() print("Insertion-sort the following lines into 'Changes' file:") print() dedup = {} for key in sorted(msgs.keys()): if msgs[key] not in dedup: dedup[msgs[key]] = True msg = msgs[key] if not re.search(r'\.$', msg): msg += '.' print(msg + ' [' + msg_authors[key] + ']') print() print("You may now want to clean up spelling, and commit:") print(" (make spelling | grep -vi 'writing output')") print(" git ci -am 'Commentary: Changes update'") print() ####################################################################### parser = argparse.ArgumentParser( allow_abbrev=False, prog="log_changes", description="Create example entries for 'Changes' from parsing 'git log'", epilog="""Copyright 2019-2026 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") parser.add_argument('--debug', action='store_true', help='enable debug') Args = parser.parse_args() process() ###################################################################### # Local Variables: # compile-command: "cd .. ; nodist/log_changes" # End: verilator-5.044/nodist/clang_check_attributes0000755000542200017500000013704315125463617022052 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # pylint: disable=C0114,C0115,C0116,C0209,C0302,R0902,R0911,R0912,R0914,R0915,E1101 # # Copyright 2022-2026 by Wilson Snyder. Verilator is free software; you # can redistribute it and/or modify it under the terms of either the GNU Lesser # General Public License Version 3 or the Apache License 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Apache-2.0 import argparse import os import sys import shlex from typing import Callable, Iterable, Optional, Union, TYPE_CHECKING import dataclasses from dataclasses import dataclass import enum from enum import Enum import multiprocessing import re import tempfile import clang.cindex from clang.cindex import ( Index, TranslationUnitSaveError, TranslationUnitLoadError, CompilationDatabase, ) if not TYPE_CHECKING: from clang.cindex import CursorKind else: # Workaround for missing support for members defined out-of-class in Pylance: # https://github.com/microsoft/pylance-release/issues/2365#issuecomment-1035803067 class CursorKindMeta(type): def __getattr__(cls, name: str) -> clang.cindex.CursorKind: return getattr(clang.cindex.CursorKind, name) # pylint: disable-next=invalid-enum-extension class CursorKind(clang.cindex.CursorKind, metaclass=CursorKindMeta): pass def fully_qualified_name(node): if node is None: return [] if node.kind == CursorKind.TRANSLATION_UNIT: return [] res = fully_qualified_name(node.semantic_parent) displayname = node.displayname displayname = [displayname] if displayname else [] if res: return res + displayname return displayname # Returns True, if `class_node` contains node # that matches `member` spelling def check_class_member_exists(class_node, member): for child in class_node.get_children(): if member.spelling == child.spelling: return True return False # Returns Base class (if found) of `class_node` # that is of type `base_type` def get_base_class(class_node, base_type): for child in class_node.get_children(): if child.kind is CursorKind.CXX_BASE_SPECIFIER: base_class = child.type if base_type.spelling == base_class.spelling: return base_class return None @dataclass class VlAnnotations: mt_start: bool = False mt_safe: bool = False stable_tree: bool = False mt_safe_postinit: bool = False mt_unsafe: bool = False mt_disabled: bool = False mt_unsafe_one: bool = False pure: bool = False guarded: bool = False requires: bool = False excludes: bool = False acquire: bool = False release: bool = False def is_mt_safe_context(self): return self.mt_safe and not (self.mt_unsafe or self.mt_unsafe_one) def is_pure_context(self): return self.pure def is_stabe_tree_context(self): # stable tree context requires calls to be marked # as MT_SAFE or MT_STABLE # Functions in MT_START needs to be MT_SAFE or MT_STABLE return self.stable_tree or self.mt_start def is_mt_unsafe_call(self): return self.mt_unsafe or self.mt_unsafe_one or self.mt_disabled def is_mt_safe_call(self): return (not self.is_mt_unsafe_call() and (self.mt_safe or self.mt_safe_postinit or self.pure or self.requires or self.excludes or self.acquire or self.release)) def is_pure_call(self): return self.pure def is_stabe_tree_call(self): return self.stable_tree def __or__(self, other: "VlAnnotations"): result = VlAnnotations() for key, value in dataclasses.asdict(self).items(): setattr(result, key, value | getattr(other, key)) return result def is_empty(self): for value in dataclasses.asdict(self).values(): if value: return False return True def __str__(self): result = [] for field, value in dataclasses.asdict(self).items(): if value: result.append(field) return ", ".join(result) @staticmethod def from_nodes_list(nodes: Iterable): result = VlAnnotations() for node in nodes: if node.kind == CursorKind.ANNOTATE_ATTR: displayname = node.displayname if displayname == "MT_START": result.mt_start = True elif displayname == "MT_SAFE": result.mt_safe = True elif displayname == "MT_STABLE": result.stable_tree = True elif displayname == "MT_SAFE_POSTINIT": result.mt_safe_postinit = True elif displayname == "MT_UNSAFE": result.mt_unsafe = True elif displayname == "MT_UNSAFE_ONE": result.mt_unsafe_one = True elif displayname == "MT_DISABLED": result.mt_disabled = True elif displayname == "PURE": result.pure = True elif displayname in ["ACQUIRE", "ACQUIRE_SHARED"]: result.acquire = True elif displayname in ["RELEASE", "RELEASE_SHARED"]: result.release = True elif displayname == "REQUIRES": result.requires = True elif displayname in ["EXCLUDES", "MT_SAFE_EXCLUDES"]: result.excludes = True elif displayname == "GUARDED_BY": result.guarded = True # Attributes are always at the beginning elif not node.kind.is_attribute(): break return result class FunctionType(Enum): UNKNOWN = enum.auto() FUNCTION = enum.auto() METHOD = enum.auto() STATIC_METHOD = enum.auto() CONSTRUCTOR = enum.auto() @staticmethod def from_node(node: clang.cindex.Cursor): if node is None: return FunctionType.UNKNOWN if node.kind == CursorKind.FUNCTION_DECL: return FunctionType.FUNCTION if node.kind == CursorKind.CXX_METHOD and node.is_static_method(): return FunctionType.STATIC_METHOD if node.kind == CursorKind.CXX_METHOD: return FunctionType.METHOD if node.kind == CursorKind.CONSTRUCTOR: return FunctionType.CONSTRUCTOR return FunctionType.UNKNOWN @dataclass(eq=False) class FunctionInfo: name_parts: list[str] usr: str file: str line: int annotations: VlAnnotations ftype: FunctionType _hash: Optional[int] = dataclasses.field(default=None, init=False, repr=False) @property def name(self): return "::".join(self.name_parts) def __str__(self): return f"[{self.name}@{self.file}:{self.line}]" def __hash__(self): if not self._hash: self._hash = hash(f"{self.usr}:{self.file}:{self.line}") return self._hash def __eq__(self, other): return (self.usr == other.usr and self.file == other.file and self.line == other.line) def copy(self, /, **changes): return dataclasses.replace(self, **changes) @staticmethod def from_decl_file_line_and_refd_node(file: str, line: int, refd: clang.cindex.Cursor, annotations: VlAnnotations): file = os.path.abspath(file) refd = refd.canonical assert refd is not None name_parts = fully_qualified_name(refd) usr = refd.get_usr() ftype = FunctionType.from_node(refd) return FunctionInfo(name_parts, usr, file, line, annotations, ftype) @staticmethod def from_node(node: clang.cindex.Cursor, refd: Optional[clang.cindex.Cursor] = None, annotations: Optional[VlAnnotations] = None): file = os.path.abspath(node.location.file.name) line = node.location.line if annotations is None: annotations = VlAnnotations.from_nodes_list(node.get_children()) if refd is None: refd = node.referenced if refd is not None: refd = refd.canonical assert refd is not None name_parts = fully_qualified_name(refd) usr = refd.get_usr() ftype = FunctionType.from_node(refd) return FunctionInfo(name_parts, usr, file, line, annotations, ftype) class DiagnosticKind(Enum): ANNOTATIONS_DEF_DECL_MISMATCH = enum.auto() NON_PURE_CALL_IN_PURE_CTX = enum.auto() NON_MT_SAFE_CALL_IN_MT_SAFE_CTX = enum.auto() NON_STABLE_TREE_CALL_IN_STABLE_TREE_CTX = enum.auto() MISSING_MT_DISABLED_ANNOTATION = enum.auto() def __lt__(self, other): return self.value < other.value @dataclass class Diagnostic: target: FunctionInfo source: FunctionInfo source_ctx: FunctionInfo kind: DiagnosticKind _hash: Optional[int] = dataclasses.field(default=None, init=False, repr=False) def __hash__(self): if not self._hash: self._hash = hash(hash(self.target) ^ hash(self.source_ctx) ^ hash(self.kind)) return self._hash class CallAnnotationsValidator: def __init__(self, diagnostic_cb: Callable[[Diagnostic], None], is_ignored_top_level: Callable[[clang.cindex.Cursor], bool], is_ignored_def: Callable[[clang.cindex.Cursor, clang.cindex.Cursor], bool], is_ignored_call: Callable[[clang.cindex.Cursor], bool]): self._diagnostic_cb = diagnostic_cb self._is_ignored_top_level = is_ignored_top_level self._is_ignored_call = is_ignored_call self._is_ignored_def = is_ignored_def self._index = Index.create() # Map key represents translation unit initial defines # (from command line and source's lines before any include) self._processed_headers: dict[str, set[str]] = {} self._external_decls: dict[str, set[tuple[str, int]]] = {} # Current context self._main_source_file: str = "" self._defines: dict[str, str] = {} self._call_location: Optional[FunctionInfo] = None self._caller: Optional[FunctionInfo] = None self._base_func_declarations: dict[str, clang.cindex.Cursor] = {} self._constructor_context: list[clang.cindex.Cursor] = [] self._level: int = 0 def is_mt_disabled_code_unit(self): return "VL_MT_DISABLED_CODE_UNIT" in self._defines def is_constructor_context(self): return len(self._constructor_context) > 0 # Parses all lines in a form: `#define KEY VALUE` located before any `#include` line. # The parsing is very simple, there is no support for line breaks, etc. @staticmethod def parse_initial_defines(source_file: str) -> dict[str, str]: defs: dict[str, str] = {} with open(source_file, "r", encoding="utf-8") as file: for line in file: line = line.strip() match = re.fullmatch(r"^#\s*(define\s+(\w+)(?:\s+(.*))?|include\s+.*)$", line) if match: if match.group(1).startswith("define"): key = match.group(2) value = match.groups("1")[2] defs[key] = value elif match.group(1).startswith("include"): break return defs @staticmethod def filter_out_unsupported_compiler_args(args: list[str]) -> tuple[list[str], dict[str, str]]: filtered_args = [] defines = {} args_iter = iter(args) try: while arg := next(args_iter): # Skip positional arguments (input file name). if not arg.startswith("-") and (arg.endswith(".cpp") or arg.endswith(".c") or arg.endswith(".h")): continue # Skipped options with separate value argument. if arg in ["-o", "-T", "-MT", "-MQ", "-MF" "-L"]: next(args_iter) continue # Skipped options without separate value argument. if arg == "-c" or arg.startswith("-W") or arg.startswith("-L"): continue # Preserved options with separate value argument. if arg in [ "-x" "-Xclang", "-I", "-isystem", "-iquote", "-include", "-include-pch" ]: filtered_args += [arg, next(args_iter)] continue kv_str = None d_or_u = None # Preserve define/undefine with separate value argument. if arg in ["-D", "-U"]: filtered_args.append(arg) d_or_u = arg[1] kv_str = next(args_iter) filtered_args.append(kv_str) # Preserve define/undefine without separate value argument. elif arg[0:2] in ["-D", "-U"]: filtered_args.append(arg) kv_str = arg[2:] d_or_u = arg[1] # Preserve everything else. else: filtered_args.append(arg) continue # Keep track of defines for class' internal purposes. key_value = kv_str.split("=", 1) key = key_value[0] val = "1" if len(key_value) == 1 else key_value[1] if d_or_u == "D": defines[key] = val elif d_or_u == "U" and key in defines: del defines[key] except StopIteration: pass return (filtered_args, defines) def compile_and_analyze_file(self, source_file: str, compiler_args: list[str], build_dir: Optional[str]): filename = os.path.abspath(source_file) initial_cwd = "." filtered_args, defines = self.filter_out_unsupported_compiler_args(compiler_args) defines.update(self.parse_initial_defines(source_file)) if build_dir: initial_cwd = os.getcwd() os.chdir(build_dir) try: translation_unit = self._index.parse(filename, filtered_args) except TranslationUnitLoadError: translation_unit = None errors = [] if translation_unit: for diag in translation_unit.diagnostics: if diag.severity >= clang.cindex.Diagnostic.Error: errors.append(str(diag)) if translation_unit and len(errors) == 0: self._defines = defines self._main_source_file = filename self.process_translation_unit(translation_unit) self._main_source_file = "" self._defines = {} elif len(errors) != 0: print(f"%Error: parsing failed: {filename}", file=sys.stderr) for error in errors: print(f" {error}", file=sys.stderr) if build_dir: os.chdir(initial_cwd) def emit_diagnostic(self, target: Union[FunctionInfo, clang.cindex.Cursor], kind: DiagnosticKind): assert self._caller is not None assert self._call_location is not None source = self._caller source_ctx = self._call_location if isinstance(target, FunctionInfo): self._diagnostic_cb(Diagnostic(target, source, source_ctx, kind)) else: self._diagnostic_cb( Diagnostic(FunctionInfo.from_node(target), source, source_ctx, kind)) def iterate_children(self, children: Iterable[clang.cindex.Cursor], handler: Callable[[clang.cindex.Cursor], None]): if children: self._level += 1 for child in children: handler(child) self._level -= 1 @staticmethod def get_referenced_node_info( node: clang.cindex.Cursor ) -> tuple[bool, Optional[clang.cindex.Cursor], VlAnnotations, Iterable[clang.cindex.Cursor]]: if not node.spelling and not node.displayname: return (False, None, VlAnnotations(), []) refd = node.referenced if refd is None: raise ValueError("The node does not specify referenced node.") refd = refd.canonical children = list(refd.get_children()) annotations = VlAnnotations.from_nodes_list(children) return (True, refd, annotations, children) def check_mt_safe_call(self, node: clang.cindex.Cursor, refd: clang.cindex.Cursor, annotations: VlAnnotations): is_mt_safe = False if annotations.is_mt_safe_call(): is_mt_safe = True elif not annotations.is_mt_unsafe_call(): # Check whether the object the method is called on is mt-safe def find_object_ref(node): try: node = next(node.get_children()) if node.kind == CursorKind.DECL_REF_EXPR: # Operator on an argument or local object return node if node.kind != CursorKind.MEMBER_REF_EXPR: return None if node.referenced and node.referenced.kind == CursorKind.FIELD_DECL: # Operator on a member object return node node = next(node.get_children()) if node.kind == CursorKind.UNEXPOSED_EXPR: node = next(node.get_children()) return node except StopIteration: return None refn = find_object_ref(node) if self.is_constructor_context() and not refn: # we are in constructor and no object reference means # we are calling local method. It is MT safe # only if this method is also only calling local methods or # MT-safe methods self.iterate_children(refd.get_children(), self.dispatch_node_inside_definition) is_mt_safe = True # class/struct member elif refn and refn.kind == CursorKind.MEMBER_REF_EXPR and refn.referenced: refn = refn.referenced refna = VlAnnotations.from_nodes_list(refn.get_children()) if refna.guarded: is_mt_safe = True if self.is_constructor_context() and refn.semantic_parent: # we are in constructor, so calling local members is MT_SAFE, # make sure object that we are calling is local to the constructor constructor_class = self._constructor_context[-1].semantic_parent if refn.semantic_parent.spelling == constructor_class.spelling: if check_class_member_exists(constructor_class, refn): is_mt_safe = True else: # check if this class inherits from some base class base_class = get_base_class(constructor_class, refn.semantic_parent) if base_class: if check_class_member_exists(base_class.get_declaration(), refn): is_mt_safe = True # variable elif refn and refn.kind == CursorKind.DECL_REF_EXPR and refn.referenced: if refn.get_definition(): if refn.referenced.semantic_parent: if refn.referenced.semantic_parent.kind in [ CursorKind.FUNCTION_DECL, CursorKind.CXX_METHOD ]: # This is a local or an argument. # Calling methods on local pointers or references is MT-safe, # but on argument pointers or references is not. if "*" not in refn.type.spelling and "&" not in refn.type.spelling: is_mt_safe = True # local variable if refn.referenced.kind == CursorKind.VAR_DECL: is_mt_safe = True else: # Global variable in different translation unit, unsafe pass elif refn and refn.kind == CursorKind.CALL_EXPR: if self.is_constructor_context(): # call to local function from constructor context # safe if this function also calling local methods or # MT-safe methods self.dispatch_call_node(refn) is_mt_safe = True return is_mt_safe # Call handling def process_method_call(self, node: clang.cindex.Cursor, refd: clang.cindex.Cursor, annotations: VlAnnotations): assert self._call_location ctx = self._call_location.annotations # MT-safe context if ctx.is_mt_safe_context(): if not self.check_mt_safe_call(node, refd, annotations): self.emit_diagnostic(FunctionInfo.from_node(refd, refd, annotations), DiagnosticKind.NON_MT_SAFE_CALL_IN_MT_SAFE_CTX) # stable tree context if ctx.is_stabe_tree_context(): if annotations.is_mt_unsafe_call() or not ( annotations.is_stabe_tree_call() or annotations.is_pure_call() or self.check_mt_safe_call(node, refd, annotations)): self.emit_diagnostic(FunctionInfo.from_node(refd, refd, annotations), DiagnosticKind.NON_STABLE_TREE_CALL_IN_STABLE_TREE_CTX) # pure context if ctx.is_pure_context(): if not annotations.is_pure_call(): self.emit_diagnostic(FunctionInfo.from_node(refd, refd, annotations), DiagnosticKind.NON_PURE_CALL_IN_PURE_CTX) def process_function_call(self, refd: clang.cindex.Cursor, annotations: VlAnnotations): assert self._call_location ctx = self._call_location.annotations # MT-safe context if ctx.is_mt_safe_context(): if not annotations.is_mt_safe_call(): self.emit_diagnostic(FunctionInfo.from_node(refd, refd, annotations), DiagnosticKind.NON_MT_SAFE_CALL_IN_MT_SAFE_CTX) # stable tree context if ctx.is_stabe_tree_context(): if annotations.is_mt_unsafe_call() or not (annotations.is_pure_call() or annotations.is_mt_safe_call() or annotations.is_stabe_tree_call()): self.emit_diagnostic(FunctionInfo.from_node(refd, refd, annotations), DiagnosticKind.NON_STABLE_TREE_CALL_IN_STABLE_TREE_CTX) # pure context if ctx.is_pure_context(): if not annotations.is_pure_call(): self.emit_diagnostic(FunctionInfo.from_node(refd, refd, annotations), DiagnosticKind.NON_PURE_CALL_IN_PURE_CTX) def process_constructor_call(self, refd: clang.cindex.Cursor, annotations: VlAnnotations): assert self._call_location ctx = self._call_location.annotations # Constructors are OK in MT-safe context # only if they call local methods or MT-safe functions. if ctx.is_mt_safe_context() or self.is_constructor_context(): self._constructor_context.append(refd) self.iterate_children(refd.get_children(), self.dispatch_node_inside_definition) self._constructor_context.pop() # stable tree context if ctx.is_stabe_tree_context(): self._constructor_context.append(refd) self.iterate_children(refd.get_children(), self.dispatch_node_inside_definition) self._constructor_context.pop() # pure context if ctx.is_pure_context(): if not annotations.is_pure_call() and not refd.is_default_constructor(): self.emit_diagnostic(FunctionInfo.from_node(refd, refd, annotations), DiagnosticKind.NON_PURE_CALL_IN_PURE_CTX) def dispatch_call_node(self, node: clang.cindex.Cursor): [supported, refd, annotations, _] = self.get_referenced_node_info(node) if not supported: self.iterate_children(node.get_children(), self.dispatch_node_inside_definition) return True assert refd is not None if self._is_ignored_call(refd): return True if "std::function" in refd.displayname: # Workaroud for missing support for lambda annotations # in c++11. # If function takes std::function as argument, # assume, that this std::function will be called inside it. self.process_function_definition(node) return False assert self._call_location is not None node_file = os.path.abspath(node.location.file.name) self._call_location = self._call_location.copy(file=node_file, line=node.location.line) # Standalone functions and static class methods if (refd.kind == CursorKind.FUNCTION_DECL or refd.kind == CursorKind.CXX_METHOD and refd.is_static_method()): self.process_function_call(refd, annotations) # Function pointer elif refd.kind in [CursorKind.VAR_DECL, CursorKind.FIELD_DECL, CursorKind.PARM_DECL]: self.process_function_call(refd, annotations) # Non-static class methods elif refd.kind == CursorKind.CXX_METHOD: self.process_method_call(node, refd, annotations) # Conversion method (e.g. `operator int()`) elif refd.kind == CursorKind.CONVERSION_FUNCTION: self.process_method_call(node, refd, annotations) # Constructors elif refd.kind == CursorKind.CONSTRUCTOR: self.process_constructor_call(refd, annotations) else: # Ignore other callables, but report them print("Unknown callable: " f"{refd.location.file.name}:{refd.location.line}: " f"{refd.displayname} {refd.kind}\n" f" from: {node.location.file.name}:{node.location.line}") return True def process_function_declaration(self, node: clang.cindex.Cursor): # Ignore declarations in main .cpp file if node.location.file.name != self._main_source_file: children = list(node.get_children()) annotations = VlAnnotations.from_nodes_list(children) if not annotations.mt_disabled: self._external_decls.setdefault(node.get_usr(), set()).add( (str(node.location.file.name), int(node.location.line))) return self.iterate_children(children, self.dispatch_node) return self.iterate_children(node.get_children(), self.dispatch_node) # Definition handling def dispatch_node_inside_definition(self, node: clang.cindex.Cursor): if node.kind == CursorKind.CALL_EXPR: if self.dispatch_call_node(node) is False: return None elif node.is_definition() and node.kind in [ CursorKind.CXX_METHOD, CursorKind.FUNCTION_DECL, CursorKind.CONSTRUCTOR, CursorKind.CONVERSION_FUNCTION ]: self.process_function_definition(node) return None return self.iterate_children(node.get_children(), self.dispatch_node_inside_definition) def process_function_definition(self, node: clang.cindex.Cursor): [supported, refd, annotations, _] = self.get_referenced_node_info(node) # Fetch virtual annotations from base class. # Set refd to virtual definition if present. signature = node.displayname if signature in self._base_func_declarations: refd = self._base_func_declarations[signature] virtual_annotations = VlAnnotations.from_nodes_list(refd.get_children()) annotations = annotations | virtual_annotations if refd and self._is_ignored_def(node, refd): return None node_children = list(node.get_children()) if not supported: return self.iterate_children(node_children, self.dispatch_node) assert refd is not None def_annotations = VlAnnotations.from_nodes_list(node_children) # Implicitly mark definitions in VL_MT_DISABLED_CODE_UNIT .cpp files as # VL_MT_DISABLED. Existence of the annotation on declarations in .h # files is verified below. # Also sets VL_EXCLUDES, as this annotation is added together with # explicit VL_MT_DISABLED. if self.is_mt_disabled_code_unit(): if node.location.file.name == self._main_source_file: annotations.mt_disabled = True annotations.excludes = True if refd.location.file.name == self._main_source_file: def_annotations.mt_disabled = True def_annotations.excludes = True if def_annotations != annotations: # Use definition's annotations for the diagnostic # source (i.e. the definition) self._caller = FunctionInfo.from_node(node, refd, def_annotations) self._call_location = self._caller self.emit_diagnostic(FunctionInfo.from_node(refd, refd, annotations), DiagnosticKind.ANNOTATIONS_DEF_DECL_MISMATCH) else: # Use concatenation of definition and declaration annotations # for calls validation. self._caller = FunctionInfo.from_node(node, refd, def_annotations | annotations) prev_call_location = self._call_location self._call_location = self._caller if self.is_mt_disabled_code_unit(): # Report declarations of this functions that don't have MT_DISABLED annotation # and are located in headers. if node.location.file.name == self._main_source_file: usr = node.get_usr() declarations = self._external_decls.get(usr, set()) for file, line in declarations: self.emit_diagnostic( FunctionInfo.from_decl_file_line_and_refd_node( file, line, refd, def_annotations), DiagnosticKind.MISSING_MT_DISABLED_ANNOTATION) if declarations: del self._external_decls[usr] self.iterate_children(node_children, self.dispatch_node_inside_definition) self._call_location = prev_call_location self._caller = prev_call_location return None # Nodes not located inside definition def dispatch_node(self, node: clang.cindex.Cursor): kind = node.kind if kind is CursorKind.CXX_BASE_SPECIFIER: # Get referenced virtual declarations from base class. for base in node.get_children(): if base.referenced: for declaration in base.referenced.get_children(): self._base_func_declarations[declaration.displayname] = declaration elif kind in [ CursorKind.CXX_METHOD, CursorKind.FUNCTION_DECL, CursorKind.CONSTRUCTOR, CursorKind.CONVERSION_FUNCTION ]: if node.is_definition(): return self.process_function_definition(node) return self.process_function_declaration(node) result = self.iterate_children(node.get_children(), self.dispatch_node) # Clean declarations if class declaration processing is finished. if kind in [ CursorKind.CLASS_DECL, CursorKind.STRUCT_DECL, CursorKind.UNION_DECL, CursorKind.ENUM_DECL, CursorKind.UNEXPOSED_DECL ]: self._base_func_declarations = {} return result def process_translation_unit(self, translation_unit: clang.cindex.TranslationUnit): self._level += 1 kv_defines = sorted([f"{k}={v}" for k, v in self._defines.items()]) concat_defines = '\n'.join(kv_defines) # List of headers already processed in a TU with specified set of defines. tu_processed_headers = self._processed_headers.setdefault(concat_defines, set()) for child in translation_unit.cursor.get_children(): if self._is_ignored_top_level(child): continue if tu_processed_headers: filename = os.path.abspath(child.location.file.name) if filename in tu_processed_headers: continue self.dispatch_node(child) self._level -= 1 tu_processed_headers.update( [os.path.abspath(str(hdr.source)) for hdr in translation_unit.get_includes()]) @dataclass class CompileCommand: refid: int filename: str args: list[str] directory: str = dataclasses.field(default_factory=os.getcwd) def get_filter_funcs(verilator_root: str): verilator_root = os.path.abspath(verilator_root) + "/" def is_ignored_top_level(node: clang.cindex.Cursor) -> bool: # Anything defined in a header outside Verilator root if not node.location.file: return True filename = os.path.abspath(node.location.file.name) return not filename.startswith(verilator_root) def is_ignored_def(node: clang.cindex.Cursor, refd: clang.cindex.Cursor) -> bool: # __* if str(refd.spelling).startswith("__"): return True # Anything defined in a header outside Verilator root if not node.location.file: return True filename = os.path.abspath(node.location.file.name) if not filename.startswith(verilator_root): return True return False def is_ignored_call(refd: clang.cindex.Cursor) -> bool: # __* if str(refd.spelling).startswith("__"): return True # std::* fqn = fully_qualified_name(refd) if fqn and fqn[0] == "std": return True # Anything declared in a header outside Verilator root if not refd.location.file: return True filename = os.path.abspath(refd.location.file.name) if not filename.startswith(verilator_root): return True return False return (is_ignored_top_level, is_ignored_def, is_ignored_call) def precompile_header(compile_command: CompileCommand, tmp_dir: str) -> str: initial_cwd = os.getcwd() errors = [] try: os.chdir(compile_command.directory) index = Index.create() translation_unit = index.parse(compile_command.filename, compile_command.args) for diag in translation_unit.diagnostics: if diag.severity >= clang.cindex.Diagnostic.Error: errors.append(str(diag)) if len(errors) == 0: pch_file = os.path.join( tmp_dir, f"{compile_command.refid:02}_{os.path.basename(compile_command.filename)}.pch") translation_unit.save(pch_file) if pch_file: return pch_file except (TranslationUnitSaveError, TranslationUnitLoadError, OSError) as exception: print(f"%Warning: {exception}", file=sys.stderr) finally: os.chdir(initial_cwd) print(f"%Warning: Precompilation failed, skipping: {compile_command.filename}", file=sys.stderr) for error in errors: print(f" {error}", file=sys.stderr) return "" # Compile and analyze inputs in a single process. def run_analysis(ccl: Iterable[CompileCommand], pccl: Iterable[CompileCommand], diagnostic_cb: Callable[[Diagnostic], None], verilator_root: str): (is_ignored_top_level, is_ignored_def, is_ignored_call) = get_filter_funcs(verilator_root) prefix = "verilator_clang_check_attributes_" with tempfile.TemporaryDirectory(prefix=prefix) as tmp_dir: extra_args = [] for pcc in pccl: pch_file = precompile_header(pcc, tmp_dir) if pch_file: extra_args += ["-include-pch", pch_file] cav = CallAnnotationsValidator(diagnostic_cb, is_ignored_top_level, is_ignored_def, is_ignored_call) for compile_command in ccl: cav.compile_and_analyze_file(compile_command.filename, extra_args + compile_command.args, compile_command.directory) @dataclass class ParallelAnalysisProcess: cav: Optional[CallAnnotationsValidator] = None diags: set[Diagnostic] = dataclasses.field(default_factory=set) tmp_dir: str = "" @staticmethod def init_data(verilator_root: str, tmp_dir: str): (is_ignored_top_level, is_ignored_def, is_ignored_call) = get_filter_funcs(verilator_root) ParallelAnalysisProcess.cav = CallAnnotationsValidator( ParallelAnalysisProcess._diagnostic_handler, is_ignored_top_level, is_ignored_def, is_ignored_call) ParallelAnalysisProcess.tmp_dir = tmp_dir @staticmethod def _diagnostic_handler(diag: Diagnostic): ParallelAnalysisProcess.diags.add(diag) @staticmethod def analyze_cpp_file(compile_command: CompileCommand) -> set[Diagnostic]: ParallelAnalysisProcess.diags = set() assert ParallelAnalysisProcess.cav is not None ParallelAnalysisProcess.cav.compile_and_analyze_file(compile_command.filename, compile_command.args, compile_command.directory) return ParallelAnalysisProcess.diags @staticmethod def precompile_header(compile_command: CompileCommand) -> str: return precompile_header(compile_command, ParallelAnalysisProcess.tmp_dir) # Compile and analyze inputs in multiple processes. def run_parallel_analysis(ccl: Iterable[CompileCommand], pccl: Iterable[CompileCommand], diagnostic_cb: Callable[[Diagnostic], None], jobs_count: int, verilator_root: str): prefix = "verilator_clang_check_attributes_" with tempfile.TemporaryDirectory(prefix=prefix) as tmp_dir: with multiprocessing.Pool(processes=jobs_count, initializer=ParallelAnalysisProcess.init_data, initargs=[verilator_root, tmp_dir]) as pool: extra_args = [] for pch_file in pool.imap_unordered(ParallelAnalysisProcess.precompile_header, pccl): if pch_file: extra_args += ["-include-pch", pch_file] if extra_args: for compile_command in ccl: compile_command.args = compile_command.args + extra_args for diags in pool.imap_unordered(ParallelAnalysisProcess.analyze_cpp_file, ccl, 1): for diag in diags: diagnostic_cb(diag) class TopDownSummaryPrinter(): @dataclass class FunctionCallees: info: FunctionInfo calees: set[FunctionInfo] mismatch: Optional[FunctionInfo] = None reason: Optional[DiagnosticKind] = None def __init__(self): self._is_first_group = True self._funcs: dict[str, TopDownSummaryPrinter.FunctionCallees] = {} self._unsafe_in_safe: set[str] = set() def begin_group(self, label): if not self._is_first_group: print() print(f"%Error: {label}") self._is_first_group = False def handle_diagnostic(self, diag: Diagnostic): usr = diag.source.usr func = self._funcs.get(usr, None) if func is None: func = TopDownSummaryPrinter.FunctionCallees(diag.source, set()) self._funcs[usr] = func func.reason = diag.kind if diag.kind == DiagnosticKind.ANNOTATIONS_DEF_DECL_MISMATCH: func.mismatch = diag.target else: func.calees.add(diag.target) self._unsafe_in_safe.add(diag.target.usr) def print_summary(self, root_dir: str): row_groups: dict[str, list[list[str]]] = {} column_widths = [0, 0] for func in sorted(self._funcs.values(), key=lambda func: (func.info.file, func.info.line, func.info.usr)): func_info = func.info relfile = os.path.relpath(func_info.file, root_dir) row_group = [] name = f"\"{func_info.name}\" " if func.reason == DiagnosticKind.ANNOTATIONS_DEF_DECL_MISMATCH: name += "declaration does not match definition" elif func.reason == DiagnosticKind.NON_MT_SAFE_CALL_IN_MT_SAFE_CTX: name += "is mtsafe but calls non-mtsafe function(s)" elif func.reason == DiagnosticKind.NON_PURE_CALL_IN_PURE_CTX: name += "is pure but calls non-pure function(s)" elif func.reason == DiagnosticKind.NON_STABLE_TREE_CALL_IN_STABLE_TREE_CTX: name += "is stable_tree but calls non-stable_tree or non-mtsafe" elif func.reason == DiagnosticKind.MISSING_MT_DISABLED_ANNOTATION: name += ("defined in a file marked as " + "VL_MT_DISABLED_CODE_UNIT has declaration(s) " + "without VL_MT_DISABLED annotation") else: name += "for unknown reason (please add description)" if func.mismatch: mrelfile = os.path.relpath(func.mismatch.file, root_dir) row_group.append([ f"{mrelfile}:{func.mismatch.line}:", f"[{func.mismatch.annotations}]", func.mismatch.name + " [declaration]" ]) row_group.append( [f"{relfile}:{func_info.line}:", f"[{func_info.annotations}]", func_info.name]) for callee in sorted(func.calees, key=lambda func: (func.file, func.line, func.usr)): crelfile = os.path.relpath(callee.file, root_dir) row_group.append( [f"{crelfile}:{callee.line}:", f"[{callee.annotations}]", " " + callee.name]) row_groups[name] = row_group for row in row_group: for row_id, value in enumerate(row[0:-1]): column_widths[row_id] = max(column_widths[row_id], len(value)) for label, rows in sorted(row_groups.items(), key=lambda kv: kv[0]): self.begin_group(label) for row in rows: print(f"{row[0]:<{column_widths[0]}} " f"{row[1]:<{column_widths[1]}} " f"{row[2]}") print(f"Number of functions reported unsafe: {len(self._unsafe_in_safe)}") def get_cpu_count(): try: return len(os.sched_getaffinity(0)) except AttributeError: return multiprocessing.cpu_count() def main(): default_verilator_root = os.path.abspath(os.path.join(os.path.dirname(__file__), "..")) parser = argparse.ArgumentParser( allow_abbrev=False, formatter_class=argparse.RawDescriptionHelpFormatter, description="""Check function annotations for correctness""", epilog="""Copyright 2022-2026 by Wilson Snyder. Verilator is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Apache License 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Apache-2.0""") parser.add_argument("--verilator-root", type=str, default=default_verilator_root, help="Path to Verilator sources root directory.") parser.add_argument("--jobs", "-j", type=int, default=0, help="Number of parallel jobs to use.") parser.add_argument("--compile-commands-dir", type=str, default=None, help="Path to directory containing compile_commands.json.") parser.add_argument("--cxxflags", type=str, default=None, help="Extra flags passed to clang++.") parser.add_argument("--compilation-root", type=str, default=os.getcwd(), help="Directory used as CWD when compiling source files.") parser.add_argument("-c", "--precompile", action="append", help="Header file to be precompiled and cached at the start.") parser.add_argument("file", type=str, nargs="+", help="Source file to analyze.") cmdline = parser.parse_args() if cmdline.jobs == 0: cmdline.jobs = max(1, get_cpu_count()) if not cmdline.compilation_root: cmdline.compilation_root = cmdline.verilator_root verilator_root = os.path.abspath(cmdline.verilator_root) default_compilation_root = os.path.abspath(cmdline.compilation_root) compdb: Optional[CompilationDatabase] = None if cmdline.compile_commands_dir: compdb = CompilationDatabase.fromDirectory(cmdline.compile_commands_dir) if cmdline.cxxflags is not None: common_cxxflags = shlex.split(cmdline.cxxflags) else: common_cxxflags = [] precompile_commands_list = [] if cmdline.precompile: hdr_cxxflags = ['-xc++-header'] + common_cxxflags for refid, file in enumerate(cmdline.precompile): filename = os.path.abspath(file) compile_command = CompileCommand(refid, filename, hdr_cxxflags, default_compilation_root) precompile_commands_list.append(compile_command) compile_commands_list = [] for refid, file in enumerate(cmdline.file): filename = os.path.abspath(file) root = default_compilation_root cxxflags = common_cxxflags[:] if compdb: entry = compdb.getCompileCommands(filename) if entry is None: print(f"%Error: reading compile commands failed: {filename}", file=sys.stderr) entry_list = [] else: entry_list = list(entry) # Compilation database can contain multiple entries for single file, # e.g. when it has been updated by appending new entries. # Use last entry for the file, if it exists, as it is the newest one. if len(entry_list) > 0: last_entry = entry_list[-1] root = last_entry.directory entry_args = list(last_entry.arguments) # First argument in compile_commands.json arguments list is # compiler executable name/path. CIndex (libclang) always # implicitly prepends executable name, so it shouldn't be passed # here. cxxflags.extend(entry_args[1:]) compile_command = CompileCommand(refid, filename, cxxflags, root) compile_commands_list.append(compile_command) summary_printer = TopDownSummaryPrinter() if cmdline.jobs == 1: run_analysis(compile_commands_list, precompile_commands_list, summary_printer.handle_diagnostic, verilator_root) else: run_parallel_analysis(compile_commands_list, precompile_commands_list, summary_printer.handle_diagnostic, cmdline.jobs, verilator_root) summary_printer.print_summary(verilator_root) if __name__ == '__main__': main() verilator-5.044/nodist/install_test0000755000542200017500000001216015125463617020060 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # mypy: disallow-untyped-defs # pylint: disable=C0103,C0114,C0115,C0116,C0209,R0801,R0915 ###################################################################### import argparse import multiprocessing import os import shutil import subprocess import sys ###################################################################### def test() -> None: if not os.path.exists("nodist/install_test"): sys.exit("%Error: Run from the top of the verilator kit") cleanenv() if os.path.exists("Makefile"): run("make distclean") # Try building from a scratch area srcdir = os.getcwd() blddir = srcdir + "/test_regress/obj_dir/install_test_bld" prefix = srcdir + "/test_regress/obj_dir/install_test_prefix" testdirp = srcdir + "/test_regress/obj_dir/install_test_testp" testdirn = srcdir + "/test_regress/obj_dir/install_test_testn" if Args.stage <= 0: print("== stage 0") run("/bin/rm -rf " + blddir) run("/bin/mkdir -p " + blddir) # Matches Ubuntu's e.g. /usr/share/pkgconfig/verilator.pc run("cd " + blddir + " && " + srcdir + "/configure --prefix " + prefix + " --exec-prefix " + prefix + " --datarootdir " + prefix + "/share" + " --includedir " + prefix + "/share/verilator/include") run("cd " + blddir + " && make -j " + str(calc_jobs())) # Install it under the prefix if Args.stage <= 1: print("== stage 1") run("/bin/rm -rf " + prefix) run("/bin/mkdir -p " + prefix) run("cd " + blddir + " && make install") run("test -e " + prefix + "/share/man/man1/verilator.1") run("test -e " + prefix + "/share/verilator/examples/make_tracing_c/Makefile") run("test -e " + prefix + "/share/verilator/include/verilated.h") run("test -e " + prefix + "/bin/verilator") run("test -e " + prefix + "/bin/verilator_bin") run("test -e " + prefix + "/bin/verilator_bin_dbg") run("test -e " + prefix + "/bin/verilator_gantt") run("test -e " + prefix + "/bin/verilator_profcfunc") # run a test using just the path if Args.stage <= 2: print("== stage 2") odir = testdirp run("/bin/rm -rf " + odir) run("/bin/mkdir -p " + odir) path = prefix + "/bin" + ":" + prefix + "/share/bin" write_verilog(odir) run("cd " + odir + " && PATH=" + path + ":$PATH verilator --cc top.v --exe sim_main.cpp") run("cd " + odir + "/obj_dir && PATH=" + path + ":$PATH make -f Vtop.mk") run("cd " + odir + " && PATH=" + path + ":$PATH obj_dir/Vtop") # run a test using exact path to binary if Args.stage <= 3: print("== stage 3") odir = testdirn run("/bin/rm -rf " + odir) run("/bin/mkdir -p " + odir) write_verilog(odir) bin1 = prefix + "/bin" run("cd " + odir + " && " + bin1 + "/verilator --cc top.v --exe sim_main.cpp") run("cd " + odir + "/obj_dir && make -f Vtop.mk") run("cd " + odir + "/obj_dir && ./Vtop") if Args.stage <= 9: print("*-* All Finished *-*") def write_verilog(odir: str) -> None: shutil.copy2("examples/make_hello_c/top.v", odir + "/top.v") shutil.copy2("examples/make_hello_c/sim_main.cpp", odir + "/sim_main.cpp") def cleanenv() -> None: for var in os.environ: if var in ('VERILATOR_ROOT', 'VERILATOR_INCLUDE', 'VERILATOR_NO_OPT_BUILD'): print("unset %s # Was '%s'" % (var, os.environ[var])) del os.environ[var] def get_cpu_count() -> int: try: return len(os.sched_getaffinity(0)) except AttributeError: return multiprocessing.cpu_count() def calc_jobs() -> int: return get_cpu_count() + 1 def run(command: str) -> None: # run a system command, check errors print("\t%s" % command) os.system(command) status = subprocess.call(command, shell=True) if status < 0: raise RuntimeError("%Error: Command failed " + command + ", stopped") ####################################################################### ####################################################################### parser = argparse.ArgumentParser( allow_abbrev=False, formatter_class=argparse.RawDescriptionHelpFormatter, description="""install_test performs several make-and-install iterations to verify the Verilator kit. It isn't part of the normal "make test" due to the number of builds required.""", epilog="""Copyright 2009-2026 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") parser.add_argument('--debug', action='store_const', const=9, help='enable debug') parser.add_argument('--stage', type=int, default=0, help='run a specific test stage (see the script)') Args = parser.parse_args() test() ###################################################################### # Local Variables: # compile-command: "cd .. ; nodist/install_test" # End: verilator-5.044/.clang-format0000644000542200017500000000722515125463617016506 0ustar mahmoudyfreeshell--- Language: Cpp # BasedOnStyle: LLVM AccessModifierOffset: -4 AlignAfterOpenBracket: Align AlignConsecutiveAssignments: false AlignConsecutiveDeclarations: false AlignEscapedNewlines: DontAlign AlignOperands: true AlignTrailingComments: false AllowAllParametersOfDeclarationOnNextLine: true AllowShortBlocksOnASingleLine: true AllowShortCaseLabelsOnASingleLine: true AllowShortFunctionsOnASingleLine: All AllowShortIfStatementsOnASingleLine: true AllowShortLoopsOnASingleLine: true AlwaysBreakAfterDefinitionReturnType: None AlwaysBreakAfterReturnType: None AlwaysBreakBeforeMultilineStrings: false AlwaysBreakTemplateDeclarations: true BinPackArguments: true BinPackParameters: true BraceWrapping: AfterClass: false AfterControlStatement: false AfterEnum: false AfterFunction: false AfterNamespace: false AfterObjCDeclaration: false AfterStruct: false AfterUnion: false AfterExternBlock: false BeforeCatch: false BeforeElse: false IndentBraces: false SplitEmptyFunction: true SplitEmptyRecord: true SplitEmptyNamespace: true BreakBeforeBinaryOperators: All BreakBeforeBraces: Attach BreakBeforeInheritanceComma: false BreakBeforeTernaryOperators: true BreakConstructorInitializersBeforeComma: false BreakConstructorInitializers: BeforeComma BreakAfterJavaFieldAnnotations: false BreakStringLiterals: true ColumnLimit: 99 CommentPragmas: '^ IWYU pragma:' CompactNamespaces: false ConstructorInitializerAllOnOneLineOrOnePerLine: false ConstructorInitializerIndentWidth: 4 ContinuationIndentWidth: 4 Cpp11BracedListStyle: true DerivePointerAlignment: false DisableFormat: false ExperimentalAutoDetectBinPacking: false FixNamespaceComments: true ForEachMacros: - Q_FOREACH - BOOST_FOREACH # Include grouping/sorting SortIncludes: true IncludeBlocks: Regroup IncludeCategories: - Regex: '"V3Pch.*\.h"' Priority: -2 # Precompiled headers - Regex: '"(config_build|verilated_config|verilatedos)\.h"' Priority: -1 # Sepecials before main header - Regex: '(<|")verilated.*' Priority: 1 # Runtime headers - Regex: '"V3.*__gen.*\.h"' Priority: 3 # Generated internal headers separately - Regex: '"V3.*"' Priority: 2 # Internal header - Regex: '".*"' Priority: 4 # Other non-system headers - Regex: '<[[:alnum:]_.]+>' Priority: 5 # Simple system headers next - Regex: '<.*>' Priority: 6 # Other system headers next IncludeIsMainRegex: '$' IndentCaseLabels: false IndentPPDirectives: None IndentWidth: 4 IndentWrappedFunctionNames: false JavaScriptQuotes: Leave JavaScriptWrapImports: true KeepEmptyLinesAtTheStartOfBlocks: true MacroBlockBegin: '' MacroBlockEnd: '' MaxEmptyLinesToKeep: 1 NamespaceIndentation: None ObjCBlockIndentWidth: 2 ObjCSpaceAfterProperty: false ObjCSpaceBeforeProtocolList: true PenaltyBreakAssignment: 2 PenaltyBreakBeforeFirstCallParameter: 19 PenaltyBreakComment: 300 PenaltyBreakFirstLessLess: 120 PenaltyBreakString: 1000 PenaltyExcessCharacter: 1000000 PenaltyReturnTypeOnItsOwnLine: 60 PointerAlignment: Left ReflowComments: true SortUsingDeclarations: true SpaceAfterCStyleCast: false SpaceAfterTemplateKeyword: true SpaceBeforeAssignmentOperators: true SpaceBeforeParens: ControlStatements SpaceInEmptyParentheses: false SpacesBeforeTrailingComments: 2 SpacesInAngles: false SpacesInContainerLiterals: true SpacesInCStyleCastParentheses: false SpacesInLineCommentPrefix: Minimum: 0 Maximum: -1 SpacesInParentheses: false SpacesInSquareBrackets: false Standard: Cpp11 TabWidth: 8 UseTab: Never ... verilator-5.044/.gitignore0000644000542200017500000000113715125463617016117 0ustar mahmoudyfreeshell\#* .#* .gdb_history .nfs* *~ *.tidy *.old *.gz *.gz.uu *.html *.info *.log *.1 .*.swp *.tmp *.tex *.pdf /Makefile /.ccache /.venv/ /artifact/ README TAGS autom4te.cache compile_commands.json config.cache config.status configure dddrun* doxygen-doc gdbrun* gmon.out internals.txt ncverilog.history nohup.out verilator-config-version.cmake verilator-config.cmake verilator.pc verilator.txt verilator_bin* verilator_coverage_bin* **/__pycache__/* **/_build/* **/obj_dir/* /.vscode/ /.idea/ /cmake-build-*/ /obj_coverage/ /test_regress/snapshot/ xmverilog.* xrun.history # Normal CMake build directory /build verilator-5.044/test_regress/0000755000542200017500000000000015125463617016636 5ustar mahmoudyfreeshellverilator-5.044/test_regress/Makefile_obj0000644000542200017500000000276115125463617021136 0ustar mahmoudyfreeshell# -*- Makefile -*- #***************************************************************************** # # DESCRIPTION: Verilator Example: Makefile for inside object directory # # This is executed in the object directory, and called by ../Makefile # # Copyright 2003-2026 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # #***************************************************************************** default: $(VM_PREFIX) include $(VM_PREFIX).mk # So t/t_foobar.cpp is found (due to test_regress using -Mdir) VPATH += ../.. ####################################################################### # Debugging CPPFLAGS += -DVL_DEBUG=1 # Assertions disabled as SystemC libraries are not clean #CPPFLAGS += -D_GLIBCXX_DEBUG # Needed by tracing routines CPPFLAGS += -DTEST_OBJ_DIR=$(TEST_OBJ_DIR) CPPFLAGS += -DVM_PREFIX=$(VM_PREFIX) CPPFLAGS += -DVM_PREFIX_INCLUDE="<$(VM_PREFIX).h>" CPPFLAGS += -DVM_PREFIX_ROOT_INCLUDE="<$(VM_PREFIX)___024root.h>" CPPFLAGS += $(CPPFLAGS_DRIVER) CPPFLAGS += $(CPPFLAGS_DRIVER2) CPPFLAGS += $(CPPFLAGS_ADD) # Reduce spin count for faster testing CPPFLAGS += -DVL_LOCK_SPINS=10000 ifeq ($(CFG_WITH_LONGTESTS),yes) ifeq ($(DRIVER_STD),newest) CPPFLAGS += $(CFG_CXXFLAGS_STD) endif endif ####################################################################### verilator-5.044/test_regress/.gdbinit0000644000542200017500000000002715125463617020256 0ustar mahmoudyfreeshellsource ../src/.gdbinit verilator-5.044/test_regress/t/0000755000542200017500000000000015125463617017101 5ustar mahmoudyfreeshellverilator-5.044/test_regress/t/t_class_imp2.v0000644000542200017500000000211315125463617021644 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; interface class Courier; pure virtual function void deliver(); endclass class Person implements Courier; virtual function void deliver(); $display("slow delivery"); endfunction endclass interface class Seats; pure virtual function int seats(); endclass class Vehicle; endclass class Car extends Vehicle implements Courier, Seats; virtual function void deliver(); $display("fast delivery"); endfunction virtual function int seats(); return 4; endfunction endclass class MetaCar extends Car; endclass function void do_delivery(Courier courier); courier.deliver(); endfunction initial begin MetaCar car; car = new(); do_delivery(car); if (car.seats() != 4) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_force_bad_rw.out0000644000542200017500000000046515125463617022576 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_force_bad_rw.v:14:20: Unsupported: Signals used via read-write reference cannot be forced 14 | foreach (ass[index]) begin | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.044/test_regress/t/t_param_array8.py0000755000542200017500000000073415125463617022373 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_opt_const_cond_redundant.v0000644000542200017500000000205715125463617024676 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug3806 module t ( input clk ); reg [65:0] idx /*verilator public*/; initial idx = 1; wire unlikely = idx > 200; typedef enum logic { UP, DOWN } dir_t; dir_t direction; always_comb direction = idx % 2 == 0 ? UP : DOWN; int ups; // Make computable always @(posedge clk) begin if (idx > 100) begin `ifdef TEST_VERBOSE $write("ups = %0d\n", ups); `endif if (ups != 50049) $stop; $write("*-* All Finished *-*\n"); $finish; end if (direction == UP)++ups; else if (direction == UP)++ups; else ups += 1000; case (direction) DOWN: idx = idx + 3; UP: idx = idx - 1; default: begin // This if just gets rid of branch pred on default^ if (unlikely == '1) begin $write("never\n"); end end endcase end endmodule verilator-5.044/test_regress/t/t_clocking_bad2.v0000644000542200017500000000076415125463617022303 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; logic in, out; clocking cb @(posedge clk); default input #1 output #1step; // Now allowed default input #2 output #2; output #1step out; // Now allowed output out; endclocking endmodule verilator-5.044/test_regress/t/t_order.v0000644000542200017500000000677515125463617020745 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); // surefire lint_off ASWEBB // surefire lint_off ASWEMB // surefire lint_off STMINI // surefire lint_off CSEBEQ input clk; reg [7:0] a_to_clk_levm3; reg [7:0] b_to_clk_levm1; reg [7:0] c_com_levs10; reg [7:0] d_to_clk_levm2; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [7:0] m_from_clk_lev1_r; // From a of t_order_a.v wire [7:0] n_from_clk_lev2; // From a of t_order_a.v wire [7:0] o_from_com_levs11; // From a of t_order_a.v wire [7:0] o_from_comandclk_levs12;// From a of t_order_a.v wire [7:0] o_subfrom_clk_lev2; // From b of t_order_b.v // End of automatics reg [7:0] cyc; initial cyc = 0; t_order_a a ( .one (8'h1), /*AUTOINST*/ // Outputs .m_from_clk_lev1_r (m_from_clk_lev1_r[7:0]), .n_from_clk_lev2 (n_from_clk_lev2[7:0]), .o_from_com_levs11 (o_from_com_levs11[7:0]), .o_from_comandclk_levs12(o_from_comandclk_levs12[7:0]), // Inputs .clk (clk), .a_to_clk_levm3 (a_to_clk_levm3[7:0]), .b_to_clk_levm1 (b_to_clk_levm1[7:0]), .c_com_levs10 (c_com_levs10[7:0]), .d_to_clk_levm2 (d_to_clk_levm2[7:0])); t_order_b b ( /*AUTOINST*/ // Outputs .o_subfrom_clk_lev2 (o_subfrom_clk_lev2[7:0]), // Inputs .m_from_clk_lev1_r (m_from_clk_lev1_r[7:0])); reg [7:0] o_from_com_levs12; reg [7:0] o_from_com_levs13; always @ (/*AS*/o_from_com_levs11) begin o_from_com_levs12 = o_from_com_levs11 + 8'h1; o_from_com_levs12 = o_from_com_levs12 + 8'h1; // Test we can add to self and optimize o_from_com_levs13 = o_from_com_levs12; end reg sepassign_in; wire [3:0] sepassign; // verilator lint_off UNOPT assign #0.1 sepassign[0] = 0, sepassign[1] = sepassign[2], sepassign[2] = sepassign[3], sepassign[3] = sepassign_in; wire [7:0] o_subfrom_clk_lev3 = o_subfrom_clk_lev2; // verilator lint_on UNOPT always @ (posedge clk) begin cyc <= cyc+8'd1; sepassign_in <= 0; if (cyc == 8'd1) begin a_to_clk_levm3 <= 0; d_to_clk_levm2 <= 1; b_to_clk_levm1 <= 1; c_com_levs10 <= 2; sepassign_in <= 1; end if (cyc == 8'd2) begin if (sepassign !== 4'b1110) $stop; end if (cyc == 8'd3) begin $display("%d %d %d %d", m_from_clk_lev1_r, n_from_clk_lev2, o_from_com_levs11, o_from_comandclk_levs12); if (m_from_clk_lev1_r !== 8'h2) $stop; if (o_subfrom_clk_lev3 !== 8'h2) $stop; if (n_from_clk_lev2 !== 8'h2) $stop; if (o_from_com_levs11 !== 8'h3) $stop; if (o_from_com_levs13 !== 8'h5) $stop; if (o_from_comandclk_levs12 !== 8'h5) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.044/test_regress/t/t_display_time.py0000755000542200017500000000100015125463617022453 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_func_dotted.v0000644000542200017500000001047015125463617022113 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); // verilator lint_off MULTIDRIVEN ma ma0 (); initial t.ma0.u_b[0].f(1); initial t.ma0.u_b[0].f(clk); global_mod #(32'hf00d) global_cell (); global_mod #(32'hf22d) global_cell2 (); input clk; integer cyc=1; function [31:0] getName; input fake; getName = "t "; endfunction always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==2) begin if (global_cell. getGlob(1'b0) !== 32'hf00d) $stop; if (global_cell2.getGlob(1'b0) !== 32'hf22d) $stop; end if (cyc==3) begin if (ma0. getName(1'b0) !== "ma ") $stop; if (ma0.mb0. getName(1'b0) !== "mb ") $stop; if (ma0.mb0.mc0.getName(1'b0) !== "mc ") $stop; end if (cyc==4) begin if (ma0.mb0. getP2(1'b0) !== 32'h0) $stop; if (ma0.mb0.mc0.getP3(1'b0) !== 32'h0) $stop; if (ma0.mb0.mc1.getP3(1'b0) !== 32'h1) $stop; end if (cyc==5) begin ma0. checkName(ma0. getName(1'b0)); ma0.mb0. checkName(ma0.mb0. getName(1'b0)); ma0.mb0.mc0.checkName(ma0.mb0.mc0.getName(1'b0)); end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule `ifdef ATTRIBUTES `ifdef USE_INLINE_MID `define INLINE_MODULE /*verilator inline_module*/ `define INLINE_MID_MODULE /*verilator no_inline_module*/ `else `ifdef USE_INLINE `define INLINE_MODULE /*verilator inline_module*/ `define INLINE_MID_MODULE /*verilator inline_module*/ `else `define INLINE_MODULE /*verilator public_module*/ `define INLINE_MID_MODULE /*verilator public_module*/ `endif `endif `else `define INLINE_MODULE `define INLINE_MID_MODULE `endif module global_mod; `INLINE_MODULE parameter INITVAL = 0; integer globali; initial globali = INITVAL; function [31:0] getName; input fake; getName = "gmod"; endfunction function [31:0] getGlob; input fake; getGlob = globali; endfunction endmodule module ma (); `INLINE_MODULE mb #(0) mb0 (); reg [31:0] gName; initial gName = "ma "; function [31:0] getName; input fake; getName = "ma "; endfunction task checkName; input [31:0] name; if (name !== "ma ") $stop; endtask initial begin if (ma.getName(1'b0) !== "ma ") $stop; if (mb0.getName(1'b0) !== "mb ") $stop; if (mb0.mc0.getName(1'b0) !== "mc ") $stop; end endmodule module mb (); `INLINE_MID_MODULE parameter P2 = 0; mc #(P2,0) mc0 (); mc #(P2,1) mc1 (); global_mod #(32'hf33d) global_cell2 (); reg [31:0] gName; initial gName = "mb "; function [31:0] getName; input fake; getName = "mb "; endfunction function [31:0] getP2 ; input fake; getP2 = P2; endfunction task checkName; input [31:0] name; if (name !== "mb ") $stop; endtask initial begin `ifndef verilator #1; `endif if (ma. getName(1'b0) !== "ma ") $stop; if ( getName(1'b0) !== "mb ") $stop; if (mc1.getName(1'b0) !== "mc ") $stop; ma. checkName (ma. gName); /**/checkName ( gName); mc1.checkName (mc1.gName); ma. checkName (ma. getName(1'b0)); /**/checkName ( getName(1'b0)); mc1.checkName (mc1.getName(1'b0)); end endmodule module mc (); `INLINE_MODULE parameter P2 = 0; parameter P3 = 0; reg [31:0] gName; initial gName = "mc "; function [31:0] getName; input fake; getName = "mc "; endfunction function [31:0] getP3 ; input fake; getP3 = P3; endfunction task checkName; input [31:0] name; if (name !== "mc ") $stop; endtask initial begin `ifndef verilator #1; `endif if (ma.getName(1'b0) !== "ma ") $stop; if (mb.getName(1'b0) !== "mb ") $stop; if (mc.getName(1'b0) !== "mc ") $stop; ma.checkName (ma.gName); mb.checkName (mb.gName); mc.checkName (mc.gName); ma.checkName (ma.getName(1'b0)); mb.checkName (mb.getName(1'b0)); mc.checkName (mc.getName(1'b0)); end endmodule module b; function void f(bit v); $display("%m"); endfunction : f; endmodule : b bind ma b u_b[0:1](); verilator-5.044/test_regress/t/t_func_inout_bit_sel.py0000755000542200017500000000073415125463617023657 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_tri_struct.v0000644000542200017500000000105515125463617022016 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 typedef struct { bit x; } u_struct_t; module u_mh (inout u_struct_t u_i, inout u_struct_t u_o); assign u_o.x = u_i.x; endmodule module t; u_struct_t u_i, u_o; u_mh u_mh(u_i, u_o); initial begin u_i.x = 1; #1; if (u_o.x != 1'b1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_flag_topmodule_bad.out0000644000542200017500000000133615125463617023767 0ustar mahmoudyfreeshell%Warning-MULTITOP: t/t_flag_topmodule.v:15:8: Multiple top level modules : ... Suggest see manual; fix the duplicates, or use --top-module to select top. ... For warning description see https://verilator.org/warn/MULTITOP?v=latest ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message. : ... Top module 'a' 7 | module a; | ^ : ... Top module 'a2' 15 | module a2; | ^~ : ... Top module 'b' 22 | module b; | ^ %Error: Exiting due to verilator-5.044/test_regress/t/t_covergroup_unsup_ign2.py0000755000542200017500000000113415125463617024344 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_covergroup_unsup.v" test.lint(verilator_flags2=[ '--assert --coverage --Wwarn-UNSUPPORTED -Wno-fatal +define+T_COVERGROUP_UNSUP_IGN' ]) test.passes() verilator-5.044/test_regress/t/t_assoc_method_bad.py0000755000542200017500000000076315125463617023265 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_x_assign_0.py0000755000542200017500000000124115125463617022031 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_x_assign.cpp" test.top_filename = "t/t_x_assign.v" test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--x-assign 0 --exe", test.pli_filename]) test.execute() test.passes() verilator-5.044/test_regress/t/t_randomize_rand_mode_bad.py0000755000542200017500000000076315125463617024615 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_dpi_if_cond_c.cpp0000644000542200017500000000231315125463617022666 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2024 by Antmicro. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include #include // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" //====================================================================== // clang-format off #if defined(VERILATOR) # include "Vt_dpi_if_cond__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(NC) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif // clang-format on #ifdef NEED_EXTERNS extern "C" { // If get ncsim: *F,NOFDPI: Function {foo} not found in default libdpi. // Then probably forgot to list a function here. extern int dpii_increment(int* counter); } #endif int dpii_increment(int* counter) { ++(*counter); return 0; } verilator-5.044/test_regress/t/t_specparam.py0000755000542200017500000000076315125463617021762 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.044/test_regress/t/t_case_auto1.v0000644000542200017500000000543015125463617021641 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; localparam // synopsys enum En_State EP_State_IDLE = {3'b000,5'd00}, EP_State_CMDSHIFT0 = {3'b001,5'd00}, EP_State_CMDSHIFT13 = {3'b001,5'd13}, EP_State_CMDSHIFT14 = {3'b001,5'd14}, EP_State_CMDSHIFT15 = {3'b001,5'd15}, EP_State_CMDSHIFT16 = {3'b001,5'd16}, EP_State_DWAIT = {3'b010,5'd00}, EP_State_DSHIFT0 = {3'b100,5'd00}, EP_State_DSHIFT1 = {3'b100,5'd01}, EP_State_DSHIFT15 = {3'b100,5'd15}; reg [7:0] /* synopsys enum En_State */ m_state_xr; // Last command, for debugging /*AUTOASCIIENUM("m_state_xr", "m_stateAscii_xr", "EP_State_")*/ // Beginning of automatic ASCII enum decoding reg [79:0] m_stateAscii_xr; // Decode of m_state_xr always @(m_state_xr) begin case ({m_state_xr}) EP_State_IDLE: m_stateAscii_xr = "idle "; EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 "; EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13"; EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14"; EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15"; EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16"; EP_State_DWAIT: m_stateAscii_xr = "dwait "; EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 "; EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 "; EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 "; default: m_stateAscii_xr = "%Error "; endcase end // End of automatics integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; //$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b); if (cyc==1) begin m_state_xr <= EP_State_IDLE; end if (cyc==2) begin if (m_stateAscii_xr != "idle ") $stop; m_state_xr <= EP_State_CMDSHIFT13; end if (cyc==3) begin if (m_stateAscii_xr != "cmdshift13") $stop; m_state_xr <= EP_State_CMDSHIFT16; end if (cyc==4) begin if (m_stateAscii_xr != "cmdshift16") $stop; m_state_xr <= EP_State_DWAIT; end if (cyc==9) begin if (m_stateAscii_xr != "dwait ") $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.044/test_regress/t/t_split_var_issue.v0000644000542200017500000000177415125463617023037 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module other_sub ( input wire clk, input wire foo, output logic [5:0] bar ); always_comb bar[0] = foo; `ifndef NO_ASSERT assert property (@(posedge clk) (foo == bar[0])); `endif always_ff @(posedge clk) bar[5:1] <= bar[4:0]; endmodule interface intf (input wire clk); endinterface module sub ( input logic clk ); for (genvar k = 0; k < 4; k++) begin logic [5:0] bar; other_sub the_other_sub ( .clk, .foo ('1), .bar ); end endmodule module t ( input clk ); int cyc = 0; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 9) begin $write("*-* All Finished *-*\n"); $finish; end end sub the_sub (.*); endmodule verilator-5.044/test_regress/t/t_gen_defparam_multi.out0000644000542200017500000000205115125463617023775 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_gen_defparam_multi.v:14:17: Unsupported: defparam with no dot 14 | defparam PAR = 5; | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_gen_defparam_multi.v:39:24: Unsupported: defparam with more than one dot 39 | defparam m2.m3.PAR3 = 80; | ^ %Error: t/t_gen_defparam_multi.v:39:25: syntax error, unexpected IDENTIFIER, expecting ',' or ';' 39 | defparam m2.m3.PAR3 = 80; | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error-UNSUPPORTED: t/t_gen_defparam_multi.v:44:24: Unsupported: defparam with more than one dot 44 | defparam m2.m3.PAR3 = 40; | ^ %Error: t/t_gen_defparam_multi.v:44:25: syntax error, unexpected IDENTIFIER, expecting ',' or ';' 44 | defparam m2.m3.PAR3 = 40; | ^~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_clocking_sched.out0000644000542200017500000000113315125463617023112 0ustar mahmoudyfreeshell0 | posedge 0 | cb.y=0 0 | b=0 0 | x<=0 0 | y=0 0 | c<=0 0 | c<=1 0 | cb.a=1 0 | cb.b=1 0 | posedge 0 | x<=1 0 | y=1 0 | c<=0 0 | cb.a=0 0 | cb.b=1 0 | cb.y=1 0 | b=1 0 | x<=0 0 | y=0 0 | 0 1 0 0 0 0 20 | posedge 20 | c<=1 20 | cb.a=1 20 | cb.b=1 20 | cb.y=0 20 | b=0 20 | posedge 20 | x<=1 20 | y=1 20 | c<=0 20 | cb.a=0 20 | cb.b=1 20 | cb.y=1 20 | b=1 20 | x<=0 20 | y=0 20 | 0 1 0 0 0 0 30 | posedge 30 | c<=1 30 | cb.a=1 30 | cb.b=1 30 | cb.y=0 30 | b=0 30 | posedge 30 | x<=1 30 | y=1 30 | c<=0 30 | cb.a=0 30 | cb.b=1 30 | cb.y=1 30 | b=1 30 | x<=0 30 | y=0 30 | 0 1 0 0 0 0 *-* All Finished *-* verilator-5.044/test_regress/t/t_interface_param_genblk.v0000644000542200017500000000246315125463617024262 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Anthony Donlon. // SPDX-License-Identifier: CC0-1.0 // See #4664 interface intf #( parameter A = 10 ); localparam B = A / A + 1; // 2 logic [A/10-1:0] sig; endinterface module t; intf #( .A(100) ) intf(); sub i_sub ( .intf ); endmodule module sub ( intf intf // Having this named same "intf intf" important for V3LinkDot coverage ); if (intf.A == 10) begin $error("incorrect"); end else if (intf.A / intf.B == 50) begin // end else if (intf.A / $bits(intf.sig) == 10) begin // TODO: support this $info("correct"); end else begin $error("incorrect"); end for (genvar i = intf.A - 2; i < intf.A + 1; i += intf.B) begin for (genvar j = intf.B; j > intf.A - 100; j--) begin if (i < intf.A - 2) $error("error"); if (i > intf.A) $error("error"); $info("i = %0d, j = %0d", i, j); end end case (intf.A) 10, intf.A - 10: $error("incorrect"); intf.B * 50: $info("correct"); 30: $error("incorrect"); default: $error("incorrect"); endcase endmodule verilator-5.044/test_regress/t/t_dist_cppstyle.py0000755000542200017500000000663715125463617022703 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Primitive C++ style checker # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') def get_source_files(): git_files = test.run_capture("cd " + test.root + " && git ls-files") if test.verbose: print("MF " + git_files) files = {} for filename in git_files.split(): if filename == '': continue files[filename] = True return files def check_pattern(filename, contents, pattern, not_pattern, message): # Pattern uses match, so must include skipping leading whitespace if necessary lineno = 0 buffer_lineno = 0 buffer = "\n" for line in contents.splitlines(): lineno += 1 if buffer == "\n": buffer_lineno = lineno if line != "": # Don't do whole file at once - see issue #4085 # Build a buffer until a newline so we check a block at a time. buffer += line + "\n" continue m = re.search(r"\n" + pattern, buffer) if m: if not not_pattern or not re.search(not_pattern, buffer): test.error_keep_going(filename + ":" + str(buffer_lineno) + ": " + message + m.group(0)) buffer = "\n" if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") files = get_source_files() for filename in sorted(files.keys()): filename = os.path.join(test.root, filename) if not os.path.exists(filename): # git file might be deleted but not yet staged continue if not re.search(r'\.(h|c|cpp)(\.in)?$', filename): continue if '/gtkwave/' in filename: continue contents = test.file_contents(filename) + "\n\n" check_pattern(filename, contents, r"[^\']*virtual[^{};\n]+override[^\n]*", None, "'virtual' keyword is redundant on 'override' method") check_pattern(filename, contents, r' \s*(\w+ )*\s*(inline) [^;]+?\([^;]*?\)[^;]+?(?:{|:|=\s*default[^\n]*)', None, "'inline' keyword is redundant on method definitions inside classes") check_pattern( filename, contents, r'\s*inline \S+ [^;:(]+::[^;:(]+\([^;]*\)[^;]+{[^\n]*', r'template', "Use 'inline' only on declaration inside classes" " (except for template specializations)") check_pattern( filename, contents, r'.*[( ]new [a-zA-Z0-9]+\([^\n]*', # Ignore common ok narrowing conversions, on int vs uint32_t arguments r'(Need \(\)|new AstArraySel|new AstConst|new AstRange)', "Use brace instead of parenthesis-style new constructors e.g. 'new ...{...}'") check_pattern( filename, contents, r'.*(\n *[:,]|,\n) +m_[a-zA-Z0-9]+\(', # Ignore common m_e enum constructors r'.*(Need \(\)|: m_e\()|V3OPTION_PARSER_DEF', "Use brace instead of parenthesis-style constructors e.g. ': m_...{...}'") if re.search(r'\.(c|cpp)', filename): check_pattern(filename, contents, r'(\w+\s+)*(\binline\b)[^\n]*', None, "'inline' keyword is on functions defined in .cpp files") test.passes() verilator-5.044/test_regress/t/t_let_stmt_bad.v0000644000542200017500000000062015125463617022252 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; wire clk; let letf(x) = (x << 1); always @(posedge clk) begin case (0) 0: letf(0); // Bad, need a statement endcase end endmodule verilator-5.044/test_regress/t/t_class_imp2.py0000755000542200017500000000073415125463617022041 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_trace_array_saif.py0000755000542200017500000000136115125463617023300 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_trace_array.v" test.golden_filename = "t/t_trace_array_saif.out" test.compile(verilator_flags2=['--cc --trace-saif --trace-structs --trace-max-width 0']) test.execute() # saif_identical is very slow, so require exact match test.files_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_constraint_dist_randc_bad.v0000644000542200017500000000053715125463617025004 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls1; randc int rc; constraint c_bad { rc dist {3 := 0, 10 := 5}; } // Bad, no dist on randc endclass module t; endmodule verilator-5.044/test_regress/t/t_inst_dtree_inlad.py0000755000542200017500000000111615125463617023307 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_inst_dtree.v" test.compile(v_flags2=['+define+INLINE_A +define+INLINE_D'], verilator_flags2=['-trace']) test.execute() test.passes() verilator-5.044/test_regress/t/t_timing_pong.v0000644000542200017500000000130215125463617022121 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; event ping; event pong; int cnt = 0; initial forever @ping begin `ifdef TEST_VERBOSE $write("ping\n"); `endif cnt++; ->pong; end initial forever @pong begin `ifdef TEST_VERBOSE $write("pong\n"); `endif if (cnt < 10) ->ping; end initial #1 ->ping; initial #2 if (cnt == 10) begin $write("*-* All Finished *-*\n"); $finish; end else $stop; initial #3 $stop; // timeout endmodule verilator-5.044/test_regress/t/t_hier_block_type_param_typedef.v0000644000542200017500000000157615125463617025666 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t( clk ); input clk; logic [21:0] in1; logic [21:0] out1; assign in1 = 0; typedef logic[21:0] PARAM_T; Test #(.TYPE_t(PARAM_T)) test(.out (out1), .in (in1)); logic [63:0] in2; logic [63:0] out2; assign in2 = 0; typedef logic[63:0] PARAM2_T; Test #(.TYPE_t(PARAM2_T)) test2(.out (out2), .in (in2)); always @ (posedge clk) begin if (out1 !== ~in1) $stop; if (out2 !== ~in2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module Test #(parameter type TYPE_t = logic [4:0]) ( output TYPE_t out, input TYPE_t in ); /*verilator hier_block*/ assign out = ~ in; endmodule verilator-5.044/test_regress/t/t_sys_file_basic_uz.v0000644000542200017500000000752015125463617023313 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2030 by Stephen Henry. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) // verilog_format: on module t; int fdin_bin, fdout_txt, fdout_bin; `define STRINGIFY(x) `"x`" // // task automatic test1; begin for (int i = 0; i < 256; i++) begin byte actual, expected; expected = i[7:0]; $fscanf(fdin_bin, "%u", actual); `checkh(actual, expected); $fdisplay(fdout_txt, "%h", actual); $fwrite(fdout_bin, "%u", actual); end for (int i = 0; i < 256; i++) begin shortint actual, expected; for (int j = 0; j < 2; j++) expected[(8 * j)+:8] = i[7:0] + j[7:0]; $fscanf(fdin_bin, "%u", actual); `checkh(actual, expected); $fdisplay(fdout_txt, "%h", actual); $fwrite(fdout_bin, "%u", actual); end for (int i = 0; i < 256; i++) begin int actual, expected; for (int j = 0; j < 4; j++) expected[(8 * j)+:8] = i[7:0] + j[7:0]; $fscanf(fdin_bin, "%u", actual); `checkh(actual, expected); $fdisplay(fdout_txt, "%h", actual); $fwrite(fdout_bin, "%u", actual); end for (int i = 0; i < 256; i++) begin longint actual, expected; for (int j = 0; j < 8; j++) expected[(8 * j)+:8] = i[7:0] + j[7:0]; $fscanf(fdin_bin, "%u", actual); `checkh(actual, expected); $fdisplay(fdout_txt, "%h", actual); $fwrite(fdout_bin, "%u", actual); end end endtask // // task automatic test2; begin for (int i = 0; i < 256; i++) begin byte actual, expected; expected = i[7:0]; $fscanf(fdin_bin, "%z", actual); `checkh(actual, expected); $fdisplay(fdout_txt, "%h", actual); $fwrite(fdout_bin, "%z", actual); end for (int i = 0; i < 256; i++) begin shortint actual, expected; for (int j = 0; j < 2; j++) expected[(8 * j)+:8] = i[7:0] + j[7:0]; $fscanf(fdin_bin, "%z", actual); `checkh(actual, expected); $fdisplay(fdout_txt, "%h", actual); $fwrite(fdout_bin, "%z", actual); end for (int i = 0; i < 256; i++) begin int actual, expected; for (int j = 0; j < 4; j++) expected[(8 * j)+:8] = i[7:0] + j[7:0]; $fscanf(fdin_bin, "%z", actual); `checkh(actual, expected); $fdisplay(fdout_txt, "%h", actual); $fwrite(fdout_bin, "%z", actual); end for (int i = 0; i < 256; i++) begin longint actual, expected; for (int j = 0; j < 8; j++) expected[(8 * j)+:8] = i[7:0] + j[7:0]; $fscanf(fdin_bin, "%z", actual); `checkh(actual, expected); $fdisplay(fdout_txt, "%h", actual); $fwrite(fdout_bin, "%z", actual); end end endtask initial begin : main_PROC string filename; filename = "t/t_sys_file_basic_uz.dat"; fdin_bin = $fopen(filename, "rb"); `ifdef IVERILOG filename = $sformatf("%s/t_sys_file_basic_uz_test.log","obj_iv/t_sys_file_basic_uz"); `else filename = $sformatf("%s/t_sys_file_basic_uz_test.log",`STRINGIFY(`TEST_OBJ_DIR)); `endif fdout_txt = $fopen(filename, "w"); `ifdef IVERILOG filename = $sformatf("%s/t_sys_file_basic_uz_test.bin","obj_iv/t_sys_file_basic_uz"); `else filename = $sformatf("%s/t_sys_file_basic_uz_test.bin",`STRINGIFY(`TEST_OBJ_DIR)); `endif $display(filename); fdout_bin = $fopen(filename, "wb"); test1; test2; $fclose(fdin_bin); $fclose(fdout_txt); $write("*-* All Finished *-*\n"); $finish(0); // Test arguments to finish end // block: main_PROC `undef STRINGIFY endmodule // t verilator-5.044/test_regress/t/t_flag_prefix_bad.out0000644000542200017500000000030115125463617023243 0ustar mahmoudyfreeshell%Error: --prefix argument must be a legal C++ identifier: 'bad/name' ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_vpi_multidim.py0000755000542200017500000000131315125463617022501 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(make_top_shell=False, make_main=False, make_pli=True, v_flags2=["+define+USE_VPI_NOT_DPI"], verilator_flags2=["--exe --vpi --no-l2name --public-flat-rw", test.pli_filename]) test.execute(use_libvpi=True) test.passes() verilator-5.044/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg2.py0000755000542200017500000000077115125463617027762 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_assoc_wildcard.v0000644000542200017500000000327215125463617022600 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; integer i; always @ (posedge clk) begin cyc <= cyc + 1; begin // Wildcard typedef string dict_t [*]; static string a [*] = '{default: "nope", "BBBBB": "fooing", 23'h434343: "baring"}; static dict_t b = '{default: "nope", "BBBBB": "fooing", 23'h434343: "baring"}; int k; string v; v = b["CCC"]; `checks(v, "baring"); v = b["BBBBB"]; `checks(v, "fooing"); v = a["CCC"]; `checks(v, "baring"); v = a["BBBBB"]; `checks(v, "fooing"); a[32'd1234] = "fooed"; a[4'd3] = "bared"; a[79'h4141] = "bazed"; i = a.num(); `checkh(i, 5); i = a.size(); `checkh(i, 5); v = a[39'd1234]; `checks(v, "fooed"); v = a["AA"]; `checks(v, "bazed"); v = a[4'd3]; `checks(v, "bared"); i = a.exists("baz"); `checkh(i, 0); i = a.exists(4'd3); `checkh(i, 1); a.delete(4'd3); i = a.size(); `checkh(i, 4); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_func_types.v0000644000542200017500000000407715125463617022002 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; function int int123(); int123 = 32'h123; endfunction function bit f_bit ; input bit i; f_bit = ~i; endfunction function int f_int ; input int i; f_int = ~i; endfunction function byte f_byte ; input byte i; f_byte = ~i; endfunction function shortint f_shortint; input shortint i; f_shortint = ~i; endfunction function longint f_longint ; input longint i; f_longint = ~i; endfunction function chandle f_chandle ; input chandle i; f_chandle = i; endfunction // Note there's no "input" here vvvv, it's the default function bit g_bit (bit i); g_bit = ~i; endfunction function int g_int (int i); g_int = ~i; endfunction function byte g_byte (byte i); g_byte = ~i; endfunction function shortint g_shortint(shortint i); g_shortint = ~i; endfunction function longint g_longint (longint i); g_longint = ~i; endfunction function chandle g_chandle (chandle i); g_chandle = i; endfunction chandle c; initial begin if (int123() !== 32'h123) $stop; if (f_bit(1'h1) !== 1'h0) $stop; if (f_bit(1'h0) !== 1'h1) $stop; if (f_int(32'h1) !== 32'hfffffffe) $stop; if (f_byte(8'h1) !== 8'hfe) $stop; if (f_shortint(16'h1) !== 16'hfffe) $stop; if (f_longint(64'h1) !== 64'hfffffffffffffffe) $stop; if (f_chandle(c) !== c) $stop; if (g_bit(1'h1) !== 1'h0) $stop; if (g_bit(1'h0) !== 1'h1) $stop; if (g_int(32'h1) !== 32'hfffffffe) $stop; if (g_byte(8'h1) !== 8'hfe) $stop; if (g_shortint(16'h1) !== 16'hfffe) $stop; if (g_longint(64'h1) !== 64'hfffffffffffffffe) $stop; if (g_chandle(c) !== c) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_interface1_noinl.py0000755000542200017500000000103315125463617023216 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface1.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_dpi_string.v0000644000542200017500000000126315125463617021757 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); import "DPI-C" function int dpii_string(input string DSM_NAME); generate begin : DSM string SOME_STRING; end endgenerate initial begin $sformat(DSM.SOME_STRING, "%m"); if (dpii_string(DSM.SOME_STRING) != 5) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_flag_relinc_dir/0000755000542200017500000000000015125463617022527 5ustar mahmoudyfreeshellverilator-5.044/test_regress/t/t_flag_relinc_dir/chip/0000755000542200017500000000000015125463617023452 5ustar mahmoudyfreeshellverilator-5.044/test_regress/t/t_flag_relinc_dir/chip/t_flag_relinc_sub.v0000644000542200017500000000074115125463617027304 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `include "../include/t_flag_relinc.vh" module t_flag_relinc_sub (); initial begin `all_finished; $finish; end endmodule verilator-5.044/test_regress/t/t_flag_relinc_dir/include/0000755000542200017500000000000015125463617024152 5ustar mahmoudyfreeshellverilator-5.044/test_regress/t/t_flag_relinc_dir/include/t_flag_relinc.vh0000644000542200017500000000061415125463617027302 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `define all_finished $write("*-* All Finished *-*\n") verilator-5.044/test_regress/t/t_alias_var_bad.py0000755000542200017500000000076315125463617022556 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_dfg_regularize_circular.v0000644000542200017500000000056215125463617024473 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module A ( output [2:0] Y ); endmodule module B; wire [2:0] w1; wire w2; A A ( .Y({ w1[2], w1[0], w2 }) ); assign w1[1] = w1[2]; endmodule verilator-5.044/test_regress/t/t_covergroup_with_sample_args_too_many_bad.v0000644000542200017500000000075115125463617030134 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ module t; covergroup cg_with_sample(int init) with function sample (int addr, bit is_read = 1'b0); endgroup cg_with_sample cov1 = new(7); function void run(); cov1.sample(5, 1'b0, 42); // Too many arguments endfunction endmodule verilator-5.044/test_regress/t/t_interface_nest.py0000755000542200017500000000073415125463617022776 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_class_new_scoped_bad.py0000755000542200017500000000076615125463617024133 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_vlcov_data_a.dat0000644000542200017500000000026715125463617022545 0ustar mahmoudyfreeshell# SystemC::Coverage-3 C 'CoverPoint0ffile1.sphl159' 0 C 'CoverPoint1ffile1.sphl159' 1 C 'CoverPoint2ffile1.sphl159' 10 C 'CoverPoint3ffile1.sphl159' 0 verilator-5.044/test_regress/t/t_alw_combdly.py0000755000542200017500000000073415125463617022301 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_case_reducer.v0000644000542200017500000002610415125463617022242 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [7:0] operand_a = crc[7:0]; wire [7:0] operand_b = crc[15:8]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [6:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[6:0]), // Inputs .clk (clk), .operand_a (operand_a[7:0]), .operand_b (operand_b[7:0])); // Aggregate outputs into a single result vector wire [63:0] result = {57'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h8a78c2ec4946ac38 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( // Inputs input wire clk, input wire [7:0] operand_a, // operand a input wire [7:0] operand_b, // operand b // Outputs output wire [6:0] out ); wire [6:0] clz_a; wire [6:0] clz_b; clz u_clz_a ( // Inputs .data_i (operand_a), .out (clz_a)); clz u_clz_b ( // Inputs .data_i (operand_b), .out (clz_b)); assign out = clz_a - clz_b; `ifdef TEST_VERBOSE always @(posedge clk) $display("Out(%x) = clz_a(%x) - clz_b(%x)", out, clz_a, clz_b); `endif endmodule `define def_0000_001x 8'b0000_0010, 8'b0000_0011 `define def_0000_01xx 8'b0000_0100, 8'b0000_0101, 8'b0000_0110, 8'b0000_0111 `define def_0000_10xx 8'b0000_1000, 8'b0000_1001, 8'b0000_1010, 8'b0000_1011 `define def_0000_11xx 8'b0000_1100, 8'b0000_1101, 8'b0000_1110, 8'b0000_1111 `define def_0000_1xxx `def_0000_10xx, `def_0000_11xx `define def_0001_00xx 8'b0001_0000, 8'b0001_0001, 8'b0001_0010, 8'b0001_0011 `define def_0001_01xx 8'b0001_0100, 8'b0001_0101, 8'b0001_0110, 8'b0001_0111 `define def_0001_10xx 8'b0001_1000, 8'b0001_1001, 8'b0001_1010, 8'b0001_1011 `define def_0001_11xx 8'b0001_1100, 8'b0001_1101, 8'b0001_1110, 8'b0001_1111 `define def_0010_00xx 8'b0010_0000, 8'b0010_0001, 8'b0010_0010, 8'b0010_0011 `define def_0010_01xx 8'b0010_0100, 8'b0010_0101, 8'b0010_0110, 8'b0010_0111 `define def_0010_10xx 8'b0010_1000, 8'b0010_1001, 8'b0010_1010, 8'b0010_1011 `define def_0010_11xx 8'b0010_1100, 8'b0010_1101, 8'b0010_1110, 8'b0010_1111 `define def_0011_00xx 8'b0011_0000, 8'b0011_0001, 8'b0011_0010, 8'b0011_0011 `define def_0011_01xx 8'b0011_0100, 8'b0011_0101, 8'b0011_0110, 8'b0011_0111 `define def_0011_10xx 8'b0011_1000, 8'b0011_1001, 8'b0011_1010, 8'b0011_1011 `define def_0011_11xx 8'b0011_1100, 8'b0011_1101, 8'b0011_1110, 8'b0011_1111 `define def_0100_00xx 8'b0100_0000, 8'b0100_0001, 8'b0100_0010, 8'b0100_0011 `define def_0100_01xx 8'b0100_0100, 8'b0100_0101, 8'b0100_0110, 8'b0100_0111 `define def_0100_10xx 8'b0100_1000, 8'b0100_1001, 8'b0100_1010, 8'b0100_1011 `define def_0100_11xx 8'b0100_1100, 8'b0100_1101, 8'b0100_1110, 8'b0100_1111 `define def_0101_00xx 8'b0101_0000, 8'b0101_0001, 8'b0101_0010, 8'b0101_0011 `define def_0101_01xx 8'b0101_0100, 8'b0101_0101, 8'b0101_0110, 8'b0101_0111 `define def_0101_10xx 8'b0101_1000, 8'b0101_1001, 8'b0101_1010, 8'b0101_1011 `define def_0101_11xx 8'b0101_1100, 8'b0101_1101, 8'b0101_1110, 8'b0101_1111 `define def_0110_00xx 8'b0110_0000, 8'b0110_0001, 8'b0110_0010, 8'b0110_0011 `define def_0110_01xx 8'b0110_0100, 8'b0110_0101, 8'b0110_0110, 8'b0110_0111 `define def_0110_10xx 8'b0110_1000, 8'b0110_1001, 8'b0110_1010, 8'b0110_1011 `define def_0110_11xx 8'b0110_1100, 8'b0110_1101, 8'b0110_1110, 8'b0110_1111 `define def_0111_00xx 8'b0111_0000, 8'b0111_0001, 8'b0111_0010, 8'b0111_0011 `define def_0111_01xx 8'b0111_0100, 8'b0111_0101, 8'b0111_0110, 8'b0111_0111 `define def_0111_10xx 8'b0111_1000, 8'b0111_1001, 8'b0111_1010, 8'b0111_1011 `define def_0111_11xx 8'b0111_1100, 8'b0111_1101, 8'b0111_1110, 8'b0111_1111 `define def_1000_00xx 8'b1000_0000, 8'b1000_0001, 8'b1000_0010, 8'b1000_0011 `define def_1000_01xx 8'b1000_0100, 8'b1000_0101, 8'b1000_0110, 8'b1000_0111 `define def_1000_10xx 8'b1000_1000, 8'b1000_1001, 8'b1000_1010, 8'b1000_1011 `define def_1000_11xx 8'b1000_1100, 8'b1000_1101, 8'b1000_1110, 8'b1000_1111 `define def_1001_00xx 8'b1001_0000, 8'b1001_0001, 8'b1001_0010, 8'b1001_0011 `define def_1001_01xx 8'b1001_0100, 8'b1001_0101, 8'b1001_0110, 8'b1001_0111 `define def_1001_10xx 8'b1001_1000, 8'b1001_1001, 8'b1001_1010, 8'b1001_1011 `define def_1001_11xx 8'b1001_1100, 8'b1001_1101, 8'b1001_1110, 8'b1001_1111 `define def_1010_00xx 8'b1010_0000, 8'b1010_0001, 8'b1010_0010, 8'b1010_0011 `define def_1010_01xx 8'b1010_0100, 8'b1010_0101, 8'b1010_0110, 8'b1010_0111 `define def_1010_10xx 8'b1010_1000, 8'b1010_1001, 8'b1010_1010, 8'b1010_1011 `define def_1010_11xx 8'b1010_1100, 8'b1010_1101, 8'b1010_1110, 8'b1010_1111 `define def_1011_00xx 8'b1011_0000, 8'b1011_0001, 8'b1011_0010, 8'b1011_0011 `define def_1011_01xx 8'b1011_0100, 8'b1011_0101, 8'b1011_0110, 8'b1011_0111 `define def_1011_10xx 8'b1011_1000, 8'b1011_1001, 8'b1011_1010, 8'b1011_1011 `define def_1011_11xx 8'b1011_1100, 8'b1011_1101, 8'b1011_1110, 8'b1011_1111 `define def_1100_00xx 8'b1100_0000, 8'b1100_0001, 8'b1100_0010, 8'b1100_0011 `define def_1100_01xx 8'b1100_0100, 8'b1100_0101, 8'b1100_0110, 8'b1100_0111 `define def_1100_10xx 8'b1100_1000, 8'b1100_1001, 8'b1100_1010, 8'b1100_1011 `define def_1100_11xx 8'b1100_1100, 8'b1100_1101, 8'b1100_1110, 8'b1100_1111 `define def_1101_00xx 8'b1101_0000, 8'b1101_0001, 8'b1101_0010, 8'b1101_0011 `define def_1101_01xx 8'b1101_0100, 8'b1101_0101, 8'b1101_0110, 8'b1101_0111 `define def_1101_10xx 8'b1101_1000, 8'b1101_1001, 8'b1101_1010, 8'b1101_1011 `define def_1101_11xx 8'b1101_1100, 8'b1101_1101, 8'b1101_1110, 8'b1101_1111 `define def_1110_00xx 8'b1110_0000, 8'b1110_0001, 8'b1110_0010, 8'b1110_0011 `define def_1110_01xx 8'b1110_0100, 8'b1110_0101, 8'b1110_0110, 8'b1110_0111 `define def_1110_10xx 8'b1110_1000, 8'b1110_1001, 8'b1110_1010, 8'b1110_1011 `define def_1110_11xx 8'b1110_1100, 8'b1110_1101, 8'b1110_1110, 8'b1110_1111 `define def_1111_00xx 8'b1111_0000, 8'b1111_0001, 8'b1111_0010, 8'b1111_0011 `define def_1111_01xx 8'b1111_0100, 8'b1111_0101, 8'b1111_0110, 8'b1111_0111 `define def_1111_10xx 8'b1111_1000, 8'b1111_1001, 8'b1111_1010, 8'b1111_1011 `define def_1111_11xx 8'b1111_1100, 8'b1111_1101, 8'b1111_1110, 8'b1111_1111 `define def_0001_xxxx `def_0001_00xx, `def_0001_01xx, `def_0001_10xx, `def_0001_11xx `define def_0010_xxxx `def_0010_00xx, `def_0010_01xx, `def_0010_10xx, `def_0010_11xx `define def_0011_xxxx `def_0011_00xx, `def_0011_01xx, `def_0011_10xx, `def_0011_11xx `define def_0100_xxxx `def_0100_00xx, `def_0100_01xx, `def_0100_10xx, `def_0100_11xx `define def_0101_xxxx `def_0101_00xx, `def_0101_01xx, `def_0101_10xx, `def_0101_11xx `define def_0110_xxxx `def_0110_00xx, `def_0110_01xx, `def_0110_10xx, `def_0110_11xx `define def_0111_xxxx `def_0111_00xx, `def_0111_01xx, `def_0111_10xx, `def_0111_11xx `define def_1000_xxxx `def_1000_00xx, `def_1000_01xx, `def_1000_10xx, `def_1000_11xx `define def_1001_xxxx `def_1001_00xx, `def_1001_01xx, `def_1001_10xx, `def_1001_11xx `define def_1010_xxxx `def_1010_00xx, `def_1010_01xx, `def_1010_10xx, `def_1010_11xx `define def_1011_xxxx `def_1011_00xx, `def_1011_01xx, `def_1011_10xx, `def_1011_11xx `define def_1100_xxxx `def_1100_00xx, `def_1100_01xx, `def_1100_10xx, `def_1100_11xx `define def_1101_xxxx `def_1101_00xx, `def_1101_01xx, `def_1101_10xx, `def_1101_11xx `define def_1110_xxxx `def_1110_00xx, `def_1110_01xx, `def_1110_10xx, `def_1110_11xx `define def_1111_xxxx `def_1111_00xx, `def_1111_01xx, `def_1111_10xx, `def_1111_11xx `define def_1xxx_xxxx `def_1000_xxxx, `def_1001_xxxx, `def_1010_xxxx, `def_1011_xxxx, \ `def_1100_xxxx, `def_1101_xxxx, `def_1110_xxxx, `def_1111_xxxx `define def_01xx_xxxx `def_0100_xxxx, `def_0101_xxxx, `def_0110_xxxx, `def_0111_xxxx `define def_001x_xxxx `def_0010_xxxx, `def_0011_xxxx module clz( input wire [7:0] data_i, output wire [6:0] out ); // ----------------------------- // Reg declarations // ----------------------------- reg [2:0] clz_byte0; reg [2:0] clz_byte1; reg [2:0] clz_byte2; reg [2:0] clz_byte3; always @* case (data_i) `def_1xxx_xxxx : clz_byte0 = 3'b000; `def_01xx_xxxx : clz_byte0 = 3'b001; `def_001x_xxxx : clz_byte0 = 3'b010; `def_0001_xxxx : clz_byte0 = 3'b011; `def_0000_1xxx : clz_byte0 = 3'b100; `def_0000_01xx : clz_byte0 = 3'b101; `def_0000_001x : clz_byte0 = 3'b110; 8'b0000_0001 : clz_byte0 = 3'b111; 8'b0000_0000 : clz_byte0 = 3'b111; default : clz_byte0 = 3'bxxx; endcase always @* case (data_i) `def_1xxx_xxxx : clz_byte1 = 3'b000; `def_01xx_xxxx : clz_byte1 = 3'b001; `def_001x_xxxx : clz_byte1 = 3'b010; `def_0001_xxxx : clz_byte1 = 3'b011; `def_0000_1xxx : clz_byte1 = 3'b100; `def_0000_01xx : clz_byte1 = 3'b101; `def_0000_001x : clz_byte1 = 3'b110; 8'b0000_0001 : clz_byte1 = 3'b111; 8'b0000_0000 : clz_byte1 = 3'b111; default : clz_byte1 = 3'bxxx; endcase always @* case (data_i) `def_1xxx_xxxx : clz_byte2 = 3'b000; `def_01xx_xxxx : clz_byte2 = 3'b001; `def_001x_xxxx : clz_byte2 = 3'b010; `def_0001_xxxx : clz_byte2 = 3'b011; `def_0000_1xxx : clz_byte2 = 3'b100; `def_0000_01xx : clz_byte2 = 3'b101; `def_0000_001x : clz_byte2 = 3'b110; 8'b0000_0001 : clz_byte2 = 3'b111; 8'b0000_0000 : clz_byte2 = 3'b111; default : clz_byte2 = 3'bxxx; endcase always @* case (data_i) `def_1xxx_xxxx : clz_byte3 = 3'b000; `def_01xx_xxxx : clz_byte3 = 3'b001; `def_001x_xxxx : clz_byte3 = 3'b010; `def_0001_xxxx : clz_byte3 = 3'b011; `def_0000_1xxx : clz_byte3 = 3'b100; `def_0000_01xx : clz_byte3 = 3'b101; `def_0000_001x : clz_byte3 = 3'b110; 8'b0000_0001 : clz_byte3 = 3'b111; 8'b0000_0000 : clz_byte3 = 3'b111; default : clz_byte3 = 3'bxxx; endcase assign out = {4'b0000, clz_byte1}; endmodule // clz verilator-5.044/test_regress/t/t_math_wide_bad.out0000644000542200017500000000312315125463617022723 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_math_wide_bad.v:34:19: Unsupported: operator ISTORD operator of 64 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h 34 | assign r = real'(a); | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_math_wide_bad.v:28:18: Unsupported: operator POWSS operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h 28 | assign z2 = a ** 3; | ^~ %Error-UNSUPPORTED: t/t_math_wide_bad.v:27:17: Unsupported: operator MULS operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h 27 | assign z = a * b; | ^ %Error-UNSUPPORTED: t/t_math_wide_bad.v:29:18: Unsupported: operator DIVS operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h 29 | assign z3 = a / b; | ^ %Error-UNSUPPORTED: t/t_math_wide_bad.v:30:18: Unsupported: operator MODDIVS operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h 30 | assign z4 = a % b; | ^ %Error-UNSUPPORTED: t/t_math_wide_bad.v:31:19: Unsupported: operator DIV operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h 31 | assign z5 = ua / ub; | ^ %Error-UNSUPPORTED: t/t_math_wide_bad.v:32:19: Unsupported: operator MODDIV operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h 32 | assign z6 = ua % ub; | ^ %Error: Exiting due to verilator-5.044/test_regress/t/t_fork_jumpblock.v0000644000542200017500000000072215125463617022623 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class bar; task foo(logic r); int a, b; if (r) return; fork a = #1 b; join_none endtask endclass module t; bar b = new; initial begin b.foo(0); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_cover_lib_c.cpp0000644000542200017500000000710115125463617022375 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "verilated_cov.h" #include "svdpi.h" #include #include #include // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" #include VM_PREFIX_INCLUDE //====================================================================== double sc_time_stamp() { return 0; } int errors = 0; //====================================================================== const char* name() { return "main"; } void hier_insert(VerilatedCovContext* covContextp, uint64_t* countp, const char* hierp, const char* peri) { // This needs to be a function at one line number so all of the // line numbers for coverage are constant, otherwise instances won't combine. VL_COVER_INSERT(covContextp, name(), countp, "hier", hierp, "per_instance", peri); } int main() { uint32_t covers[1]; uint64_t coverw[6]; VerilatedCovContext* covContextp = Verilated::defaultContextp()->coveragep(); VL_COVER_INSERT(covContextp, name(), &covers[0], "comment", "kept_one"); VL_COVER_INSERT(covContextp, name(), &coverw[0], "comment", "kept_two"); VL_COVER_INSERT(covContextp, name(), &coverw[1], "comment", "lost_three"); hier_insert(covContextp, &coverw[2], "top.a0.pi", "0"); hier_insert(covContextp, &coverw[3], "top.a1.pi", "0"); hier_insert(covContextp, &coverw[4], "top.a0.npi", "1"); hier_insert(covContextp, &coverw[5], "top.a1.npi", "1"); covers[0] = 100; coverw[0] = 210; coverw[1] = 220; coverw[2] = 200; coverw[3] = 300; coverw[4] = 200; coverw[5] = 300; #ifdef T_COVER_LIB TEST_CHECK_EQ(covContextp->defaultFilename(), "coverage.dat"); covContextp->write(VL_STRINGIFY(TEST_OBJ_DIR) "/coverage1.dat"); covContextp->forcePerInstance(true); covContextp->write(VL_STRINGIFY(TEST_OBJ_DIR) "/coverage1_per_instance.dat"); covContextp->forcePerInstance(false); covContextp->clearNonMatch("kept_"); covContextp->write(VL_STRINGIFY(TEST_OBJ_DIR) "/coverage2.dat"); covContextp->zero(); covContextp->write(VL_STRINGIFY(TEST_OBJ_DIR) "/coverage3.dat"); covContextp->clear(); Verilated::defaultContextp()->coverageFilename(VL_STRINGIFY(TEST_OBJ_DIR) "/coverage4.dat"); TEST_CHECK_EQ(covContextp->defaultFilename(), VL_STRINGIFY(TEST_OBJ_DIR) "/coverage4.dat"); covContextp->write(); // Uses defaultFilename() #elif defined(T_COVER_LIB_LEGACY) TEST_CHECK_EQ(VerilatedCov::defaultFilename(), "coverage.dat"); VerilatedCov::write(VL_STRINGIFY(TEST_OBJ_DIR) "/coverage1.dat"); VerilatedCov::clearNonMatch("kept_"); VerilatedCov::write(VL_STRINGIFY(TEST_OBJ_DIR) "/coverage2.dat"); VerilatedCov::zero(); VerilatedCov::write(VL_STRINGIFY(TEST_OBJ_DIR) "/coverage3.dat"); VerilatedCov::clear(); Verilated::defaultContextp()->coverageFilename(VL_STRINGIFY(TEST_OBJ_DIR) "/coverage4.dat"); TEST_CHECK_EQ(VerilatedCov::defaultFilename(), VL_STRINGIFY(TEST_OBJ_DIR) "/coverage4.dat"); VerilatedCov::write(); // Uses defaultFilename() #else #error #endif printf("*-* All Finished *-*\n"); return (errors ? 10 : 0); } verilator-5.044/test_regress/t/t_pp_underline_bad.py0000755000542200017500000000076315125463617023301 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_order_blkloopinit_bad.py0000755000542200017500000000076315125463617024336 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_var_static.py0000755000542200017500000000104415125463617022137 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['-Wno-IMPLICITSTATIC']) test.execute(all_run_flags=['+plusarg=value']) test.passes() verilator-5.044/test_regress/t/t_order_wireloop.py0000755000542200017500000000156215125463617023040 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(fails=test.vlt_all, verilator_flags2=["-fno-dfg"]) # Used to be %Error: t/t_order_wireloop.v:\d+: Wire inputs its own output, creating circular logic .wire x=x. # However we no longer gate optimize this # Can't use expect_filename here as unstable output test.file_grep( test.compile_log_filename, r"%Warning-UNOPTFLAT: t/t_order_wireloop.v:\d+:\d+: Signal unoptimizable: Circular combinational logic: \'t.foo\'" ) test.passes() verilator-5.044/test_regress/t/t_sys_file_basic_mcd_test2_1.dat0000644000542200017500000000020215125463617025252 0ustar mahmoudyfreeshellScotland is the greatest country. All other countries are inferior. Woe betide those to stand against the mighty Scottish nation. verilator-5.044/test_regress/t/t_implements_not_nested.v0000644000542200017500000000143315125463617024213 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package ipkg; typedef interface class iclass; interface class iclass; pure virtual function void doit(); endclass endpackage package epkg; interface class cclass2 extends ipkg::iclass; pure virtual function void doit2(); endclass class cclass implements cclass2; virtual function void doit(); $display("doit"); endfunction virtual function void doit2(); $display("doit2"); endfunction endclass endpackage module top; import epkg::*; initial begin automatic cclass c = new(); c.doit(); $finish; end endmodule verilator-5.044/test_regress/t/t_sequence_first_match_unsup.py0000755000542200017500000000107715125463617025433 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert --error-limit 1000'], fails=True) test.passes() verilator-5.044/test_regress/t/t_array_rev.py0000755000542200017500000000073415125463617021777 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_enum_overlap_bad.v0000644000542200017500000000053615125463617023121 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; enum { e0, e1, e2, e1b=1 } BAD1; initial begin $stop; end endmodule verilator-5.044/test_regress/t/t_trace_param_fst.py0000755000542200017500000000103215125463617023127 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_trace_param.v" test.compile(v_flags2=["--trace-fst"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_lint_literal_bad.v0000644000542200017500000000040515125463617023102 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module t ( ); localparam the_localparam = 8'd256; endmodule verilator-5.044/test_regress/t/t_array_in_struct.py0000755000542200017500000000073415125463617023215 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_interface_generic_bad2.v0000644000542200017500000000106015125463617024134 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class inf; int v; endclass module GenericModule (interface a); initial begin #1; if (a.v != 7) $stop; if (b.k != 9) $stop; end endmodule module t; inf inf_inst(); GenericModule genericModule (inf_inst); initial begin inf_inst.v = 7; inf_inst2.k = 9; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_mod_dot.py0000755000542200017500000000135215125463617021427 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') # This doesn't use the general compile rule as we want to make sure we form # prefix properly using post-escaped identifiers test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator", "--binary", "--Mdir " + test.obj_dir + "/t_mod_dot", 't/t_mod_dot.v', ], verilator_run=True) test.passes() verilator-5.044/test_regress/t/t_randomize_prepost.py0000755000542200017500000000104615125463617023546 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_checker_unsup.py0000755000542200017500000000111015125463617022630 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=['--assert'], expect_filename=test.golden_filename, fails=test.vlt_all) #test.execute() test.passes() verilator-5.044/test_regress/t/t_trace_depth.v0000644000542200017500000000134415125463617022077 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input clk ); int cyc; wire integer value_at_top = cyc; // Magic name checked in .py file sub1 sub1a (.*); sub1 sub1b (.*); always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub1 ( input int cyc ); sub2 sub2a (.*); sub2 sub2b (.*); sub2 sub2c (.*); endmodule module sub2 ( input int cyc ); wire integer value_in_sub = cyc; // Magic name checked in .py file endmodule verilator-5.044/test_regress/t/t_array_packed_sysfunct.py0000755000542200017500000000073415125463617024370 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_json_only_begin_hier.py0000755000542200017500000000135415125463617024171 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums'], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.files_identical(out_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_timing_trace_saif.out0000644000542200017500000001145715125463617023634 0ustar mahmoudyfreeshell// Generated by verilated_saif (SAIFILE (SAIFVERSION "2.0") (DIRECTION "backward") (PROGRAM_NAME "Verilator") (DIVIDER / ) (TIMESCALE 1ps) (DURATION 100) (INSTANCE t (NET (CLK_PERIOD\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[1\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1)) (CLK_PERIOD\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[3\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1)) (CLK_PERIOD\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[0\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1)) (CLK_HALF_PERIOD\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[2\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1)) (CLK_HALF_PERIOD\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (rst (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1)) (clk (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 20)) (a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 2)) (c (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10)) (d (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ev (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) verilator-5.044/test_regress/t/t_dpi_open_oob_bad_c.cpp0000644000542200017500000001165615125463617023705 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include #include #include // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" //====================================================================== // clang-format off #if defined(VERILATOR) # include "Vt_dpi_open_oob_bad__Dpi.h" #else # error "Unknown simulator for DPI test" #endif // clang-format on //====================================================================== int errors = 0; void dpii_nullptr() { printf("%s:\n", __func__); // These cause fatal errors, so each would need a separate run // svOpenArrayHandle h = nullptr; // svBitVecVal bit_vec_val[2]; // svLogicVecVal logic_vec_val[2]; // svDimensions(h); // svGetArrayPtr(h); // svHigh(h, 0); // svIncrement(h, 0); // svLeft(h, 0); // svLow(h, 0); // svRight(h, 0); // svSize(h, 0); // svSizeOfArray(h); // // svGetArrElemPtr(h, 0); // svGetArrElemPtr1(h, 0); // svGetArrElemPtr2(h, 0, 0); // svGetArrElemPtr3(h, 0, 0, 0); // svGetBitArrElem(h, 0); // svGetBitArrElem1(h, 0); // svGetBitArrElem1VecVal(bit_vec_val, h, 0); // svGetBitArrElem2(h, 0, 0); // svGetBitArrElem2VecVal(bit_vec_val, h, 0, 0); // svGetBitArrElem3(h, 0, 0, 0); // svGetBitArrElem3VecVal(bit_vec_val, h, 0, 0, 0); // svGetBitArrElemVecVal(bit_vec_val, h, 0); // svGetLogicArrElem(h, 0); // svGetLogicArrElem1(h, 0); // svGetLogicArrElem1VecVal(logic_vec_val, h, 0); // svGetLogicArrElem2(h, 0, 0); // svGetLogicArrElem2VecVal(logic_vec_val, h, 0, 0); // svGetLogicArrElem3(h, 0, 0, 0); // svGetLogicArrElem3VecVal(logic_vec_val, h, 0, 0, 0); // svGetLogicArrElemVecVal(logic_vec_val, h, 0); // svPutBitArrElem(h, 0, 0); // svPutBitArrElem1(h, 0, 0); // svPutBitArrElem1VecVal(h, bit_vec_val, 0); // svPutBitArrElem2(h, 0, 0, 0); // svPutBitArrElem2VecVal(h, bit_vec_val, 0, 0); // svPutBitArrElem3(h, 0, 0, 0, 0); // svPutBitArrElem3VecVal(h, bit_vec_val, 0, 0, 0); // svPutBitArrElemVecVal(h, bit_vec_val, 0); // svPutLogicArrElem(h, 0, 0); // svPutLogicArrElem1(h, 0, 0); // svPutLogicArrElem1VecVal(h, logic_vec_val, 0); // svPutLogicArrElem2(h, 0, 0, 0); // svPutLogicArrElem2VecVal(h, logic_vec_val, 0, 0); // svPutLogicArrElem3(h, 0, 0, 0, 0); // svPutLogicArrElem3VecVal(h, logic_vec_val, 0, 0, 0); // svPutLogicArrElemVecVal(h, logic_vec_val, 0); } void dpii_int_u3(const svOpenArrayHandle i) { printf("%s:\n", __func__); // Correct usage intptr_t ip = (intptr_t)svGetArrElemPtr3(i, 1, 2, 3); TEST_CHECK_HEX_NE(ip, 0); // Out of bounds ip = (intptr_t)svGetArrElemPtr3(i, 1, 2, 30); TEST_CHECK_HEX_EQ(ip, 0); ip = (intptr_t)svGetArrElemPtr3(i, 1, 20, 3); TEST_CHECK_HEX_EQ(ip, 0); ip = (intptr_t)svGetArrElemPtr3(i, 10, 2, 3); TEST_CHECK_HEX_EQ(ip, 0); ip = (intptr_t)svGetArrElemPtr1(i, 30); TEST_CHECK_HEX_EQ(ip, 0); } void dpii_real_u1(const svOpenArrayHandle i) { printf("%s:\n", __func__); svBitVecVal bit_vec_val[4]; svLogicVecVal logic_vec_val[4]; svGetBitArrElem(i, 0); svGetBitArrElem1(i, 0); svGetBitArrElem1VecVal(bit_vec_val, i, 0); svGetBitArrElemVecVal(bit_vec_val, i, 0); svGetLogicArrElem(i, 0); svGetLogicArrElem1(i, 0); svGetLogicArrElem1VecVal(logic_vec_val, i, 0); svGetLogicArrElemVecVal(logic_vec_val, i, 0); svPutBitArrElem(i, 0, 0); svPutBitArrElem1(i, 0, 0); svPutBitArrElem1VecVal(i, bit_vec_val, 0); svPutBitArrElemVecVal(i, bit_vec_val, 0); svPutLogicArrElem(i, 0, 0); svPutLogicArrElem1(i, 0, 0); svPutLogicArrElem1VecVal(i, logic_vec_val, 0); svPutLogicArrElemVecVal(i, logic_vec_val, 0); } void dpii_bit_u6(const svOpenArrayHandle i) { printf("%s:\n", __func__); svBitVecVal bit_vec_val[4]; svLogicVecVal logic_vec_val[4]; svGetBitArrElem(i, 0, 0, 0, 0, 0, 0); svGetBitArrElemVecVal(bit_vec_val, i, 0, 0, 0, 0, 0, 0); svGetLogicArrElem(i, 0, 0, 0, 0, 0, 0); svGetLogicArrElemVecVal(logic_vec_val, i, 0, 0, 0, 0, 0, 0); svPutBitArrElem(i, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); svPutBitArrElemVecVal(i, bit_vec_val, 0, 0, 0, 0, 0, 0); svPutLogicArrElem(i, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); svPutLogicArrElemVecVal(i, logic_vec_val, 0, 0, 0, 0, 0, 0); } void dpii_real_u6(const svOpenArrayHandle i) { printf("%s:\n", __func__); svGetArrElemPtr(i, 0, 0, 0, 0, 0, 0); } verilator-5.044/test_regress/t/t_interface_typedef_bad.out0000644000542200017500000000140115125463617024437 0ustar mahmoudyfreeshell%Error: t/t_interface_typedef_bad.v:15:11: Can't find definition of scope/variable: 'not_found' 15 | typedef not_found.choice_t choice1_t; | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_interface_typedef_bad.v:15:20: Expecting a data type, not a constant: 0 15 | typedef not_found.choice_t choice1_t; | ^ %Error: t/t_interface_typedef_bad.v:16:12: Expecting a data type, not DOT: '' 16 | typedef i.not_found_t choice2_t; | ^ %Error: t/t_interface_typedef_bad.v:17:19: Expecting a data type, not MEMBERSEL: 'x_t' 17 | typedef not_ifc.x_t choice3_t; | ^~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_c_width_bad.py0000755000542200017500000000076615125463617022241 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_var_pins_sc_uint_bool_nomain.py0000755000542200017500000000107415125463617025724 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_a1_first_cc.v" test.compile(verilator_flags2=["-sc --trace-vcd --pins-sc-uint-bool"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_order_dpi_export_8.cpp0000644000542200017500000000112315125463617023724 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2022 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include void call_set_x(svBit val) { set_x(val); } verilator-5.044/test_regress/t/t_opt_table_string.py0000755000542200017500000000130215125463617023334 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--stats"]) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 1) test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 1) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_timing_initial_edge.v0000644000542200017500000000046715125463617023606 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; initial begin #10; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_multitop_sig.cpp0000644000542200017500000000232215125463617022646 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include VM_PREFIX_INCLUDE #include // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" double sc_time_stamp() { return 0; } int errors = 0; int main(int argc, char* argv[]) { Verilated::debug(0); Verilated::commandArgs(argc, argv); VM_PREFIX* topp = new VM_PREFIX{""}; { topp->a__02Ein = 0; topp->b__02Ein = 0; topp->uniq_in = 0; topp->eval(); TEST_CHECK_EQ(topp->a__02Eout, 1); TEST_CHECK_EQ(topp->b__02Eout, 0); TEST_CHECK_EQ(topp->uniq_out, 1); topp->a__02Ein = 1; topp->b__02Ein = 1; topp->uniq_in = 1; topp->eval(); TEST_CHECK_EQ(topp->a__02Eout, 0); TEST_CHECK_EQ(topp->b__02Eout, 1); TEST_CHECK_EQ(topp->uniq_out, 0); } topp->final(); VL_DO_DANGLING(delete topp, topp); printf("*-* All Finished *-*\n"); return errors ? 10 : 0; } verilator-5.044/test_regress/t/t_timing_strobe.py0000755000542200017500000000103515125463617022645 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_class_method.v0000644000542200017500000000163215125463617022262 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef class Cls; class Cls; int imembera; function int get_methoda; return imembera; endfunction task set_methoda(input int val); imembera = val; endtask function void setv_methoda(input int val); imembera = val; endfunction endclass : Cls module t; initial begin int tmp_i; Cls c; if (c != null) $stop; c = new; c.imembera = 10; if (c.get_methoda() != 10) $stop; c.set_methoda(20); if (c.get_methoda() != 20) $stop; c.setv_methoda(30); if (c.get_methoda() != 30) $stop; c.setv_methoda(300); tmp_i = c.get_methoda; if (tmp_i != 300) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_time_print.py0000755000542200017500000000100015125463617022142 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_dpi_display_c.cpp0000644000542200017500000000225215125463617022734 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include //====================================================================== // clang-format off #if defined(VERILATOR) # include "Vt_dpi_display__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif // clang-format on #ifdef NEED_EXTERNS extern "C" { extern void dpii_display_call(const char* c); } #endif // clang-format off #ifndef VL_PRINTF # define VL_PRINTF printf #endif // clang-format on //====================================================================== void dpii_display_call(const char* c) { VL_PRINTF("dpii_display_call: '%s'\n", c); } verilator-5.044/test_regress/t/t_dfg_regularize_clk.py0000755000542200017500000000100415125463617023616 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--hierarchical", "--trace"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_select_bad_range6.py0000755000542200017500000000077615125463617023342 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_select_width.py0000755000542200017500000000070615125463617022462 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.044/test_regress/t/t_constraint_inheritance_with.v0000644000542200017500000000307215125463617025405 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 `define check_rand(cl, field, constr, cond) \ begin \ longint prev_result; \ int ok = 0; \ if (!bit'(cl.randomize() with { constr; })) $stop; \ prev_result = longint'(field); \ if (!(cond)) $stop; \ repeat(9) begin \ longint result; \ if (!bit'(cl.randomize() with { constr; })) $stop; \ result = longint'(field); \ if (!(cond)) $stop; \ if (result != prev_result) ok = 1; \ prev_result = result; \ end \ if (ok != 1) $stop; \ end typedef class C; class D extends C; rand int z; constraint x_lt_y { x < y; } endclass class A; rand int x; endclass class B extends A; constraint x_gt_0 { x > 0; } endclass class C extends B; rand int y; endclass class E extends C; constraint x_gt_y { x > y; } endclass module t; initial begin B b = new; C c = new; D d = new; E e = new; A a = b; `check_rand(a, a.x, x < 10, a.x > 0 && a.x < 10); `check_rand(c, c.x, x < 100, c.x > 0 && c.x < 100); `check_rand(c, c.y, x == 5, c.x == 5); `check_rand(d, d.x, z > x && z < y, d.x > 0 && d.x < d.y); `check_rand(d, d.y, z > x && z < y, d.x > 0 && d.x < d.y); `check_rand(e, e.x, x inside {[10:20]}, e.x inside {[10:20]} && e.x > e.y); `check_rand(e, e.y, x inside {[10:20]}, e.x inside {[10:20]} && e.x > e.y); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_inst_recurse2_bad.v0000644000542200017500000000046015125463617023210 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; looped looped (); endmodule module looped; looped looped (); endmodule verilator-5.044/test_regress/t/t_class_param_circ_bad.py0000755000542200017500000000076615125463617024105 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_mailbox_notiming.v0000644000542200017500000000154215125463617023154 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Methods defined by IEEE: // class mailbox #(type T = dynamic_singular_type) ; // function new(int bound = 0); // function int num(); // task put( T message); // function int try_put( T message); // task get( ref T message ); // function int try_get( ref T message ); // task peek( ref T message ); // function int try_peek( ref T message ); // endclass `ifndef MAILBOX_T `define MAILBOX_T mailbox `endif // verilator lint_off DECLFILENAME module t; `MAILBOX_T #(int) m; initial begin m = new(4); if (m.num() != 0) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_param_array4.v0000644000542200017500000000236015125463617022176 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; parameter int SIZES [3:1] = '{10,20,30}; parameter int SUMS3 = SIZES[3]; parameter int SUMS2 = SIZES[2]; parameter int SUMS1 = SIZES[1]; parameter int LE_SIZES [1:3] = '{10,20,30}; parameter int LE_SUMS3 = LE_SIZES[3]; parameter int LE_SUMS2 = LE_SIZES[2]; parameter int LE_SUMS1 = LE_SIZES[1]; function int from_array(int index); if (index != 0); return SIZES[index]; endfunction function int from_array_le(int index); if (index != 0); return LE_SIZES[index]; endfunction initial begin if (SUMS1 != 30) $stop; if (SUMS2 != 20) $stop; if (SUMS3 != 10) $stop; if (LE_SUMS1 != 10) $stop; if (LE_SUMS2 != 20) $stop; if (LE_SUMS3 != 30) $stop; if (from_array(1) != 30) $stop; if (from_array(2) != 20) $stop; if (from_array(3) != 10) $stop; if (from_array_le(1) != 10) $stop; if (from_array_le(2) != 20) $stop; if (from_array_le(3) != 30) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_std_identifier.v0000644000542200017500000000056215125463617022612 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 package foo; `ifdef TEST_DECLARE_STD class std; static int bar; endclass `endif endpackage module t; int baz = foo::std::bar; endmodule verilator-5.044/test_regress/t/t_assert_disable_bad.out0000644000542200017500000000064015125463617023747 0ustar mahmoudyfreeshell%Error: t/t_assert_disable_bad.v:27:38: disable iff expression before property call and in its body is not legal : ... note: In instance 't' 27 | assert property (disable iff (val == 0) check(1, 1)); | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_generate_fatal_bad.out0000644000542200017500000000171315125463617023726 0ustar mahmoudyfreeshell%Warning-USERFATAL: "boom" ... For warning description see https://verilator.org/warn/USERFATAL?v=latest ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' : ... note: In instance 't.nested_loop[10].foo2_inst.foo2_loop[1].foo_in_foo2_inst' t/t_generate_fatal_bad.v:9:4: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_generate_fatal_bad.v:13:29: ... Called from 'get_baz()' with parameters: bar = ?32?h0 13 | localparam integer BAZ = get_baz(BAR); | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_randcase_fork.v0000644000542200017500000000112115125463617022407 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module randcase_tb; int count; initial begin for (int i = 0; i < 100; i++) begin fork randcase 1: count++; 5: count--; 3: ; endcase join_none end #1; if (count > 30) $stop; // Realistically won't happen (10^25) though not impossible $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_class_param_bad1.py0000755000542200017500000000076615125463617023166 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_dynarray_method.py0000755000542200017500000000073415125463617023176 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_const_number_bad.v0000644000542200017500000000115615125463617023122 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test of select from constant // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; parameter integer FOO2 = 32'd-6; // Minus doesn't go here parameter integer FOO3 = 32'd; parameter integer FOO4 = 32'h; parameter integer FOO5 = 32'b2; parameter integer FOO6 = 32'o8; // See bug2432, this is questionable, some simulators take this, others do not parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; // bug2432 - intentionally no spaces near ? endmodule verilator-5.044/test_regress/t/t_lint_syncasyncnet_bad.v0000644000542200017500000000255315125463617024175 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk, rst_both_l, rst_sync_l, rst_async_l, d ); /*AUTOINPUT*/ input clk; input rst_both_l; input rst_sync_l; input rst_async_l; input d; reg q1; reg q2; always @(posedge clk) begin if (~rst_sync_l) begin /*AUTORESET*/ // Beginning of autoreset for uninitialized flops q1 <= 1'h0; // End of automatics end else begin q1 <= d; end end always @(posedge clk) begin q2 <= (rst_both_l) ? d : 1'b0; if (0 && q1 && q2) ; end reg q3; always @(posedge clk or negedge rst_async_l) begin if (~rst_async_l) begin /*AUTORESET*/ // Beginning of autoreset for uninitialized flops q3 <= 1'h0; // End of automatics end else begin q3 <= d; end end reg q4; always @(posedge clk or negedge rst_both_l) begin q4 <= (~rst_both_l) ? 1'b0 : d; end // Make there be more async uses than sync uses reg q5; always @(posedge clk or negedge rst_both_l) begin q5 <= (~rst_both_l) ? 1'b0 : d; if (0 && q3 && q4 && q5) ; end endmodule verilator-5.044/test_regress/t/t_constraint_global_nested_member.v0000755000542200017500000000331715125463617026217 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by PlanV GmbH. // SPDX-License-Identifier: CC0-1.0 // Test case 1 class uvm_reg_field; rand int m_value; endclass class reg_class; rand int m_value; rand uvm_reg_field _dummy; constraint _dummy_is_reg {_dummy.m_value == m_value;} function new(); _dummy = new; endfunction endclass class block_class; rand reg_class m_r; function new(); m_r = new; endfunction endclass class tb_test; virtual task run_phase(int phase); block_class regmodel; regmodel = new; // verilator lint_off IGNOREDRETURN void'(regmodel.randomize() with {m_r.m_value == 32'hA5;}); // verilator lint_on IGNOREDRETURN if (regmodel.m_r.m_value != 32'hA5) $stop; endtask endclass // Test case 2 class axi_agent_config; rand bit r_ready_delays; constraint r_ready_delays_c { r_ready_delays == 0; } endclass class axi_env_config; rand axi_agent_config axim_agt_cfg; function new(); axim_agt_cfg = new; endfunction endclass class axi_base_test; axi_env_config axi_env_cfg; virtual function void build_phase(); configure_axi_env(); endfunction function void configure_axi_env(); axi_env_cfg = new; endfunction endclass class axi_wrap_test extends axi_base_test; function void configure_axi_env(); void'(axi_env_cfg.randomize()); endfunction endclass module t_constraint_global_nested_member; initial begin tb_test tb; axi_wrap_test axi_t; tb = new; tb.run_phase(0); axi_t = new(); axi_t.build_phase(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_math_pow6.py0000755000542200017500000000073415125463617021711 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_class_package.py0000755000542200017500000000073415125463617022565 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_trace_open_wrong_order_bad.v0000644000542200017500000000037215125463617025151 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog dummy test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Yu-Sheng Lin. // SPDX-License-Identifier: CC0-1.0 module t(input clk); endmodule verilator-5.044/test_regress/t/t_flag_parameter.v0000644000542200017500000000777315125463617022602 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // // Special cases of "string parameters" : // This table compares obtain results from big-3 simulators to Verilator // expected behavior. Base specified integer literals are also included as // string detection may impact results for such cases. // // | Option/Param file | simulator 1 | simulator 2 | simulator 3 | verilator | // |---------------------|-------------|-------------|-------------|-------------| // | -gC0='"AB CD"' | AB CD | UNSUPPORTED | AB CD | AB CD | // | -gC1=\"AB\ CD\" | AB CD | UNSUPPORTED | UNSUPPORTED | AB CD | // | -gC2="\"AB CD\"" | AB CD | AB CD | AB CD | AB CD | // | -gC3="\"AB\ CD\"" | AB CD | AB\\ CD | AB CD | AB CD | // | -gC4=32'h600D600D | UNSUPPORTED | 32'h600D600D| 32'h600D600D| 32'h600D600D| // | -gC5=32\'h600D600D | 32'h600D600D| UNSUPPORTED | UNSUPPORTED | 32'h600D600D| // | -gC6="32'h600D600D" | 32'h600D600D| 32'h600D600D| UNSUPPORTED | 32'h600D600D| // | -gC7='AB CD' | AB CD | UNSUPPORTED | UNSUPPORTED | UNSUPPORTED | `define stop $stop `define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: Wrong parameter value", `__FILE__,`__LINE__); `stop; end while(0); typedef enum logic [1:0] { enum_val_0 = 2'd0, enum_val_1 = 2'd1, enum_val_2 = 2'd2, enum_val_3 = 2'd3 } enum_t; module t; parameter string1 = "Original String"; parameter string2 = "Original String"; parameter string11 = "Original String"; parameter string12 = "Original String"; parameter string21 = "Original String"; parameter string22 = "Original String"; parameter real11 = 0.1; parameter real12 = 0.1; parameter real21 = 0.1; parameter real22 = 0.1; parameter real31 = 0.1; parameter real32 = 0.1; parameter real41 = 0.1; parameter real42 = 0.1; parameter real51 = 0.1; parameter real52 = 0.1; parameter int11 = 1; parameter int12 = 1; parameter int21 = 1; parameter int22 = 1; parameter int31 = 1; parameter int32 = 1; parameter int41 = 1; parameter int42 = 1; parameter int51 = 1; parameter int52 = 1; parameter int61 = 1; parameter int62 = 1; parameter int71 = 1; parameter int72 = 1; parameter bit bit0to0 = 0; parameter bit bit1to1 = 1; parameter bit bit0to1 = 0; parameter bit bit1to0 = 1; parameter enum_t enum11 = enum_val_1; parameter enum_t enum12 = enum_val_1; parameter enum_t enum21 = enum_val_1; parameter enum_t enum22 = enum_val_1; initial begin `check(string1,"New String"); `check(string2,"New String"); `check(string11,"New String"); `check(string12,"New String"); `check(string21,"New String"); `check(string22,"New String"); `check(real11,0.2); `check(real12,0.2); `check(real21,400); `check(real22,400); `check(real31,20); `check(real32,20); `check(real41,582.5); `check(real42,582.5); `check(real51,145.5); `check(real52,145.5); `check(int11,16); `check(int12,16); `check(int21,16); `check(int22,16); `check(int31,123); `check(int32,123); `check(int41,32'hdeadbeef); `check(int42,32'hdeadbeef); `check(int51,32'hdeadbeef); `check(int52,32'hdeadbeef); `check(int61,32'hdeadbeef); `check(int62,32'hdeadbeef); `check(int71,-1000); `check(int72,-1000); `check(bit0to0, 1'b0); `check(bit1to1, 1'b1); `check(bit0to1, 1'b1); `check(bit1to0, 1'b0); `check(enum11, enum_val_2); `check(enum12, enum_val_2); `check(enum21, enum_val_3); `check(enum22, enum_val_3); // Check parameter assigned simple integer literal is signed if ((int11 << 27) >>> 31 != -1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_config_include_bad.v0000644000542200017500000000041515125463617023371 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 include "meant_to_tick_include.v" module t; endmodule verilator-5.044/test_regress/t/t_preproc_strify_join.py0000755000542200017500000000137515125463617024100 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") test.compile(verilator_flags2=['-E -P'], verilator_make_gmake=False, make_top_shell=False, make_main=False, stdout_filename=stdout_filename) test.files_identical(stdout_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_display_type_bad.v0000644000542200017500000000057615125463617023137 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; string s = "a string"; initial begin $display("%d %x %f %t", s, s, s, s); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_time_sc_bad.py0000755000542200017500000000130515125463617022231 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_time_sc.v" test.sc_time_resolution = 'SC_NS' test.compile(verilator_flags2=[ '-sc', '-timescale 1ps/1ps', # Mismatch w/sc_time_resolution '+define+TEST_EXPECT=2us' ]) test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_class_extends_default.py0000755000542200017500000000077615125463617024356 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_enum_type_nomethod_bad.v0000644000542200017500000000062115125463617024322 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; typedef enum [3:0] { E01 = 1 } my_t; my_t e; initial begin e.bad_no_such_method(); $stop; end endmodule verilator-5.044/test_regress/t/t_bitsel_struct.py0000755000542200017500000000073415125463617022673 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_assoc.py0000755000542200017500000000073415125463617021115 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_dpi_name_bad.py0000755000542200017500000000077615125463617022375 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_enum_base.v0000644000542200017500000000060715125463617021554 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; typedef int int_t; typedef enum int_t {INTT_VAL = 1} intt_e; intt_e intte; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_array_backw_index_bad.v0000644000542200017500000000164615125463617024104 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; logic [31:0] array_assign [3:0]; logic [31:0] larray_assign [0:3]; logic [31:0] array_assign2 [6:3]; logic [31:0] larray_assign2 [3:6]; initial begin array_assign[1:3] = '{32'd4, 32'd3, 32'd2}; larray_assign[3:1] = '{32'd4, 32'd3, 32'd2}; array_assign2[4:6] = '{32'd4, 32'd3, 32'd2}; larray_assign2[6:4] = '{32'd4, 32'd3, 32'd2}; array_assign[4:3] = '{32'd4, 32'd3}; array_assign[1:-1] = '{32'd4, 32'd3}; array_assign[1:1] = '{32'd4}; // Ok larray_assign[1:1] = '{32'd4}; // Ok array_assign2[4:4] = '{32'd4}; // Ok larray_assign2[4:4] = '{32'd4}; // Ok $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_sys_delta_monitor.v0000644000542200017500000000115515125463617023353 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; logic [31:0] tmp; logic [31:0] tmp2; logic [31:0] tmp3; initial begin tmp = 0; $monitor("[%0t] monitor0 %h", $time, tmp); while (tmp < 32) begin tmp = tmp + 1; if ((tmp % 5) == 1) begin tmp = tmp + 2; tmp = tmp + 1; end #1; end $write("*-* All Finished *-*\n"); $finish(); end endmodule verilator-5.044/test_regress/t/t_alw_split.v0000644000542200017500000000513415125463617021614 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [15:0] m_din; // We expect all these blocks should split; // blocks that don't split should go in t_alw_nosplit.v reg [15:0] a_split_1, a_split_2; always @ (/*AS*/m_din) begin a_split_1 = m_din; a_split_2 = m_din; end reg [15:0] d_split_1, d_split_2; always @ (posedge clk) begin d_split_1 <= m_din; d_split_2 <= d_split_1; d_split_1 <= ~m_din; end reg [15:0] h_split_1; reg [15:0] h_split_2; always @ (posedge clk) begin // $write(" cyc = %x m_din = %x\n", cyc, m_din); if (cyc > 2) begin if (m_din == 16'h0) begin h_split_1 <= 16'h0; h_split_2 <= 16'h0; end else begin h_split_1 <= m_din; h_split_2 <= ~m_din; end end else begin h_split_1 <= 16'h0; h_split_2 <= 16'h0; end end reg [15:0] l_split_1, l_split_2; always @ (posedge clk) begin l_split_2 <= l_split_1; l_split_1 <= l_split_2 | m_din; end // (The checker block is an exception, it won't split.) always @ (posedge clk) begin if (cyc!=0) begin cyc<=cyc+1; if (cyc==1) begin m_din <= 16'hfeed; end if (cyc==3) begin end if (cyc==4) begin m_din <= 16'he11e; //$write(" A %x %x\n", a_split_1, a_split_2); if (!(a_split_1==16'hfeed && a_split_2==16'hfeed)) $stop; if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; if (!(h_split_1==16'hfeed && h_split_2==16'h0112)) $stop; end if (cyc==5) begin m_din <= 16'he22e; if (!(a_split_1==16'he11e && a_split_2==16'he11e)) $stop; if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; if (!(h_split_1==16'hfeed && h_split_2==16'h0112)) $stop; end if (cyc==6) begin m_din <= 16'he33e; if (!(a_split_1==16'he22e && a_split_2==16'he22e)) $stop; if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop; if (!(h_split_1==16'he11e && h_split_2==16'h1ee1)) $stop; end if (cyc==7) begin $write("*-* All Finished *-*\n"); $finish; end end end // always @ (posedge clk) endmodule verilator-5.044/test_regress/t/t_param_named_2.py0000755000542200017500000000073415125463617022472 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_process_redecl.v0000644000542200017500000000067615125463617022620 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( ); // Overrides standard class class process; endclass class mailbox; endclass class semaphore; endclass initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_udp_param_bad.out0000644000542200017500000000054615125463617022740 0ustar mahmoudyfreeshell%Error: t/t_udp_param_bad.v:12:15: syntax error, unexpected '#', expecting ';' 12 | primitive udp #( | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_udp_param_bad.v:14:1: syntax error, unexpected ')', expecting ';' 14 | ) (o, a); | ^ %Error: Exiting due to verilator-5.044/test_regress/t/t_x_rand_stability_trace.out0000644000542200017500000000105615125463617024674 0ustar mahmoudyfreeshelluninitialized = 0xf5bbcbc0 x_assigned (initial) = 0x00000000 uninitialized2 = 0xa979eb54 big = 0xa20c93ac50d8c57d4c80949aa68e82775da6af98ce08f75dc6ccfad97b059a33 random_init = 0x952aaa76 top.t.the_sub_yes_inline_1 no_init 0x4a544f7798b83fc8 top.t.the_sub_yes_inline_2 no_init 0x19b7000ee0472c9 top.t.the_sub_no_inline_1 no_init 0x38121a34978975dd top.t.the_sub_no_inline_2 no_init 0x9022c84ae0fa3cf6 rand = 0xe3e54aaa rand = 0xe85acf2d rand = 0x15e12c6a rand = 0x0f7f28c0 rand = 0xe189c52a x_assigned = 0x486aeb2d Last rand = 0xf0700dbf *-* All Finished *-* verilator-5.044/test_regress/t/t_unpacked_slice.py0000755000542200017500000000073415125463617022756 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_var_tieout.py0000755000542200017500000000073415125463617022166 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_udp_bad_comb_trigger.out0000644000542200017500000000054415125463617024301 0ustar mahmoudyfreeshell%Error: t/t_udp_bad_comb_trigger.v:14:10: There should not be a edge trigger for combinational UDP table line : ... note: In instance 'top' 14 | (01) 1 0 : 0; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_tri_gate_pmos_pins_inout.py0000755000542200017500000000140615125463617025105 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" test.compile(make_top_shell=False, make_main=False, v_flags2=['+define+T_PMOS'], make_flags=['CPPFLAGS_ADD=-DT_PMOS'], verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) test.execute() test.passes() verilator-5.044/test_regress/t/t_var_outoforder.py0000755000542200017500000000073415125463617023045 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_lib_prot_exe_bad.out0000644000542200017500000000031015125463617023430 0ustar mahmoudyfreeshell%Error: --exe cannot be used together with --lib-create. Suggest see manual ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_initial_assign_sformatf_debug.py0000755000542200017500000000105415125463617026045 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_initial_assign_sformatf.v" test.compile(verilator_flags2=['--debug']) test.execute() test.passes() verilator-5.044/test_regress/t/t_interface_gen12_noinl.py0000755000542200017500000000104015125463617024127 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_gen12.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_lint_width_genfor_bad.py0000755000542200017500000000076615125463617024325 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_var_dotted1_inl2.py0000755000542200017500000000104715125463617023143 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_var_dotted1.v" test.compile(v_flags2=['+define+USE_INLINE_MID']) test.execute() test.passes() verilator-5.044/test_regress/t/t_class_extends1.py0000755000542200017500000000073415125463617022725 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_randomize_inline_var_ctl_unsup_1.v0000644000542200017500000000103115125463617026320 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Foo; int x; static function Foo get; Foo foo = new; return foo; endfunction endclass module t; initial begin Foo foo = Foo::get(); Foo foos[] = new[1]; void'(foo.randomize(Foo::get().x)); void'(foo.randomize(foos[0].x)); void'(foo.randomize(null)); end endmodule verilator-5.044/test_regress/t/t_gate_inline_wide_noexclude_small_wide.v0000644000542200017500000000106615125463617027352 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 localparam N = 65; // Wide but narrower than expand limit module t( input wire [N-1:0] i, output wire [N-1:0] o ); // Do not exclude from inlining wides small enough to be handled by // V3Expand. wire [65:0] wide_small = N << i * i / N; for (genvar n = 0; n < N; ++n) begin assign o[n] = i[n] ^ wide_small[n]; end endmodule verilator-5.044/test_regress/t/t_var_overwidth_bad.out0000644000542200017500000000016315125463617023646 0ustar mahmoudyfreeshell%Error: unknown:0: Testbench C set input 'clk' to value that overflows what the signal's width can fit Aborting... verilator-5.044/test_regress/t/t_hier_block_import_cmake.py0000755000542200017500000000234315125463617024636 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.priority(30) test.scenarios('vlt_all') # CMake build executes from a different directory than the Make one. test.top_filename = os.path.abspath("t/t_hier_block_import.v") # stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. test.clean_objs() test.setenv('TEST_ROOT', test.t_dir + "/t_hier_block_import") test.compile(verilator_make_cmake=True, verilator_make_gmake=False, verilator_flags2=[ '$TEST_ROOT/t_hier_block_import_def.vh', '-f $TEST_ROOT/t_hier_block_import_args.vc', '-I$TEST_ROOT' ], threads=(6 if test.vltmt else 1)) test.execute() test.file_grep(test.obj_dir + "/VsubA/subA.sv", r'^module\s+(\S+)\s+', "subA") test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 2) test.passes() verilator-5.044/test_regress/t/t_lint_latch_1.v0000644000542200017500000000057515125463617022163 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for issue #1609 // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Julien Margetts. // SPDX-License-Identifier: Unlicense module t (/*AUTOARG*/ a, b, o); input a; input b; output reg o; // verilator lint_off LATCH always @(a or b) if (a) o <= b; endmodule verilator-5.044/test_regress/t/t_var_bad_hide2.py0000755000542200017500000000107115125463617022451 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["-Wwarn-VARHIDDEN"], fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_debug_fatalsrc_bt_bad.py0000755000542200017500000000156615125463617024251 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') if 'VERILATOR_TEST_NO_GDB' in os.environ: test.skip("Skipping due to VERILATOR_TEST_NO_GDB") if not test.have_gdb: test.skip("No gdb installed") test.lint(verilator_flags2=["--debug --gdbbt --debug-fatalsrc"], fails='any') test.file_grep(test.compile_log_filename, r'%Error: Internal Error: .*: --debug-fatal-src') test.file_grep(test.compile_log_filename, r'See the manual') test.file_grep(test.compile_log_filename, r'in V3Options::') test.passes() verilator-5.044/test_regress/t/t_clocking_bad1.v0000644000542200017500000000060415125463617022273 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; default clocking @(posedge clk); endclocking default clocking @(posedge clk); endclocking endmodule verilator-5.044/test_regress/t/t_sys_readmem_h.mem0000644000542200017500000000104715125463617022745 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @4 4004_37654321_27654321_17654321_07654321_abcdef10 @a 400a_37654321_27654321_17654321_07654321_abcdef11 400b_37654321_27654321_17654321_07654321_abcdef12 400c_37654321_27654321_17654321_07654321_abcdef13 verilator-5.044/test_regress/t/t_package_using_dollar_unit.py0000755000542200017500000000073415125463617025201 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_constraint_struct.py0000755000542200017500000000104615125463617023572 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_extend_c_class_c.h0000644000542200017500000000103315125463617023052 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006-2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class t_extend_c_class_c { public: // CONSTRUCTORS t_extend_c_class_c() = default; ~t_extend_c_class_c() = default; // METHODS // This function will be called from an instance created in Verilog uint32_t my_math(uint32_t in) { return in + 1; } }; verilator-5.044/test_regress/t/t_trace_no_top_name2.cpp0000644000542200017500000000272615125463617023675 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #if VM_TRACE_FST #include #define TRACE_FILE_NAME "simx.fst" #define TRACE_CLASS VerilatedFstC #elif VM_TRACE_VCD #include #define TRACE_FILE_NAME "simx.vcd" #define TRACE_CLASS VerilatedVcdC #elif VM_TRACE_SAIF #include #define TRACE_FILE_NAME "simx.saif" #define TRACE_CLASS VerilatedSaifC #endif #include #include VM_PREFIX_INCLUDE unsigned long long main_time = 0; double sc_time_stamp() { return (double)main_time; } int main(int argc, char** argv) { Verilated::debug(0); Verilated::traceEverOn(true); Verilated::commandArgs(argc, argv); // This test is to specifically check "" as the below upper model name std::unique_ptr top{new VM_PREFIX{""}}; std::unique_ptr tfp{new TRACE_CLASS}; top->trace(tfp.get(), 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/" TRACE_FILE_NAME); top->clk = 0; while (main_time <= 20) { top->eval(); tfp->dump((unsigned int)(main_time)); ++main_time; top->clk = !top->clk; } tfp->close(); top->final(); tfp.reset(); top.reset(); printf("*-* All Finished *-*\n"); return 0; } verilator-5.044/test_regress/t/t_mod_dup_bad_lib.py0000755000542200017500000000102415125463617023061 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flag2=["--work liba"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_udp_bad_multi_output.out0000644000542200017500000000053715125463617024412 0ustar mahmoudyfreeshell%Error: t/t_udp_bad_multi_output.v:8:15: 2 output ports for UDP table, there must be one output port : ... note: In instance 'top' 8 | output dout1, dout2; | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_uvm_dpi_v2020_3_1.out0000644000542200017500000000464215125463617023121 0ustar mahmoudyfreeshellUVM Report t/t_uvm_dpi.v:54: id message uvm_dpi_get_tool_name_c() = Verilator = uvm_re = uvm_hdl_check_path = uvm_hdl_read simple variable = uvm_hdl_deposit simple variable = uvm_hdl_read single bit = uvm_hdl_deposit single bit = uvm_hdl_read multi-bit = uvm_hdl_deposit multi-bit = uvm_hdl_deposit bad ranges === UVM Report expected on next line: UVM Report ../../t/uvm/v2020_3_1/dpi/uvm_hdl_verilator.c:54: UVM/DPI/HDL_SET set: unable to locate hdl path (t.exposed[10:3]) Either the name is incorrect, or you may not have PLI/ACC visibility to that name === UVM Report expected on next line: UVM Report ../../t/uvm/v2020_3_1/dpi/uvm_hdl_verilator.c:54: UVM/DPI/HDL_SET set: unable to locate hdl path (t.exposed[99:15]) Either the name is incorrect, or you may not have PLI/ACC visibility to that name = uvm_hdl_deposit not found (bad) === UVM Report expected on next line: UVM Report ../../t/uvm/v2020_3_1/dpi/uvm_hdl_verilator.c:54: UVM/DPI/HDL_SET set: unable to locate hdl path (t.__DEPOSIT_NOT_FOUND) Either the name is incorrect, or you may not have PLI/ACC visibility to that name = uvm_hdl_deposit to not exposed (bad) === UVM Report expected on next line: UVM Report ../../t/uvm/v2020_3_1/dpi/uvm_hdl_verilator.c:54: UVM/DPI/HDL_SET set: unable to locate hdl path (t.not_exposed) Either the name is incorrect, or you may not have PLI/ACC visibility to that name = uvm_hdl_force === UVM Report expected on next line: UVM Report ../../t/uvm/v2020_3_1/dpi/uvm_hdl_verilator.c:54: UVM/DPI/VLOG_GET Unsupported: uvh_hdl_force/uvm_hdl_release on hdl path 't.exposed' = uvm_hdl_release === UVM Report expected on next line: UVM Report ../../t/uvm/v2020_3_1/dpi/uvm_hdl_verilator.c:54: UVM/DPI/VLOG_GET Unsupported: uvh_hdl_force/uvm_hdl_release on hdl path 't.exposed' = uvm_hdl_release_and_read === UVM Report expected on next line: UVM Report ../../t/uvm/v2020_3_1/dpi/uvm_hdl_verilator.c:54: UVM/DPI/VLOG_GET Unsupported: uvh_hdl_force/uvm_hdl_release on hdl path 't.exposed' = uvm_hdl_force to not exposed (bad) === UVM Report expected on next line: UVM Report ../../t/uvm/v2020_3_1/dpi/uvm_hdl_verilator.c:54: UVM/DPI/VLOG_GET Unsupported: uvh_hdl_force/uvm_hdl_release on hdl path 't.not_exposed' = uvm_hdl_force to not forcable (bad) === UVM Report expected on next line: UVM Report ../../t/uvm/v2020_3_1/dpi/uvm_hdl_verilator.c:54: UVM/DPI/VLOG_GET Unsupported: uvh_hdl_force/uvm_hdl_release on hdl path 't.exposed_not_forceable' *-* All Finished *-* verilator-5.044/test_regress/t/t_disable_fork2.py0000755000542200017500000000077115125463617022514 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_vlcov_debugi.py0000755000542200017500000000137115125463617022453 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') for basename in [ "t_vlcov_data_a.dat", "t_vlcov_data_b.dat", "t_vlcov_data_c.dat", "t_vlcov_data_d.dat" ]: test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "t/" + basename, "--debug", "--debugi 9" ], tee=test.verbose, verilator_run=True) test.passes() verilator-5.044/test_regress/t/t_nba_commit_queue_suspenable.v0000644000542200017500000000337415125463617025357 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test of select from constant // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t; reg clk = 0; always #50 clk = ~clk; initial begin #1000; $write("*-* All Finished *-*\n"); $finish; end int cyc = 0; always @(posedge clk) cyc <= cyc + 1; localparam SIZE = 65536; // Case 1: Array NBA inside suspendable int array1 [SIZE]; always @ (posedge clk) begin #1; for (int i=0; i 1) begin for (int i=0; i extern "C" { #include } // Avoid C++11 in this file as not all simulators allow it //====================================================================== class TestVpiHandle { /// For testing, etc, wrap vpiHandle in an auto-releasing class vpiHandle m_handle; // No = as no C++11 bool m_freeit; // No = as no C++11 public: TestVpiHandle() : m_handle(NULL) // Need (), not C++11 , m_freeit(true) {} // Need (), not C++11 TestVpiHandle(vpiHandle h) : m_handle(h) // Need (), not C++11 , m_freeit(true) {} // Need (), not C++11 ~TestVpiHandle() { release(); } operator vpiHandle() const { return m_handle; } TestVpiHandle& operator=(vpiHandle h) { release(); m_handle = h; m_freeit = true; return *this; } void release() { if (m_handle && m_freeit) { // Below not VL_DO_DANGLING so is portable #ifdef IVERILOG vpi_free_object(m_handle); #else vpi_release_handle(m_handle); #endif m_handle = NULL; } } // Freed by another action e.g. vpi_scan; so empty and don't free again void freed() { m_handle = NULL; m_freeit = false; } }; //====================================================================== // VerilatedVpiError Methods const char* strFromVpiVal(PLI_INT32 vpiVal) { // clang-format off static const char* const names[] = { "*undefined*", "vpiBinStrVal", "vpiOctStrVal", "vpiDecStrVal", "vpiHexStrVal", "vpiScalarVal", "vpiIntVal", "vpiRealVal", "vpiStringVal", "vpiVectorVal", "vpiStrengthVal", "vpiTimeVal", "vpiObjTypeVal", "vpiSuppressVal", "vpiShortIntVal", "vpiLongIntVal", "vpiShortRealVal", "vpiRawTwoStateVal", "vpiRawFourStateVal", }; // clang-format on if ((vpiVal < 0)) return names[0]; return names[(vpiVal <= vpiRawFourStateVal) ? vpiVal : 0]; } const char* strFromVpiObjType(PLI_INT32 vpiVal) { // clang-format off static const char* const names[] = { "*undefined*", "vpiAlways", "vpiAssignStmt", "vpiAssignment", "vpiBegin", "vpiCase", "vpiCaseItem", "vpiConstant", "vpiContAssign", "vpiDeassign", "vpiDefParam", "vpiDelayControl", "vpiDisable", "vpiEventControl", "vpiEventStmt", "vpiFor", "vpiForce", "vpiForever", "vpiFork", "vpiFuncCall", "vpiFunction", "vpiGate", "vpiIf", "vpiIfElse", "vpiInitial", "vpiIntegerVar", "vpiInterModPath", "vpiIterator", "vpiIODecl", "vpiMemory", "vpiMemoryWord", "vpiModPath", "vpiModule", "vpiNamedBegin", "vpiNamedEvent", "vpiNamedFork", "vpiNet", "vpiNetBit", "vpiNullStmt", "vpiOperation", "vpiParamAssign", "vpiParameter", "vpiPartSelect", "vpiPathTerm", "vpiPort", "vpiPortBit", "vpiPrimTerm", "vpiRealVar", "vpiReg", "vpiRegBit", "vpiRelease", "vpiRepeat", "vpiRepeatControl", "vpiSchedEvent", "vpiSpecParam", "vpiSwitch", "vpiSysFuncCall", "vpiSysTaskCall", "vpiTableEntry", "vpiTask", "vpiTaskCall", "vpiTchk", "vpiTchkTerm", "vpiTimeVar", "vpiTimeQueue", "vpiUdp", "vpiUdpDefn", "vpiUserSystf", "vpiVarSelect", "vpiWait", "vpiWhile", "vpiCondition", "vpiDelay", "vpiElseStmt", "vpiForIncStmt", "vpiForInitStmt", "vpiHighConn", "vpiLhs", "vpiIndex", "vpiLeftRange", "vpiLowConn", "vpiParent", "vpiRhs", "vpiRightRange", "vpiScope", "vpiSysTfCall", "vpiTchkDataTerm", "vpiTchkNotifier", "vpiTchkRefTerm", "vpiArgument", "vpiBit", "vpiDriver", "vpiInternalScope", "vpiLoad", "vpiModDataPathIn", "vpiModPathIn", "vpiModPathOut", "vpiOperand", "vpiPortInst", "vpiProcess", "vpiVariables", "vpiUse", "vpiExpr", "vpiPrimitive", "vpiStmt", "vpiAttribute", "vpiBitSelect", "vpiCallback", "vpiDelayTerm", "vpiDelayDevice", "vpiFrame", "vpiGateArray", "vpiModuleArray", "vpiPrimitiveArray", "vpiNetArray", "vpiRange", "vpiRegArray", "vpiSwitchArray", "vpiUdpArray", "vpiActiveTimeFormat", "vpiInTerm", "vpiInstanceArray", "vpiLocalDriver", "vpiLocalLoad", "vpiOutTerm", "vpiPorts", "vpiSimNet", "vpiTaskFunc", "vpiContAssignBit", "vpiNamedEventArray", "vpiIndexedPartSelect", "vpiBaseExpr", "vpiWidthExpr", "vpiGenScopeArray", "vpiGenScope", "vpiGenVar", "vpiAutomatics" }; static const char* const sv_names1[] = { "vpiPackage", "vpiInterface", "vpiProgram", "vpiInterfaceArray", "vpiProgramArray", "vpiTypespec", "vpiModport", "vpiInterfaceTfDecl", "vpiRefObj", "vpiTypeParameter", "vpiLongIntVar", "vpiShortIntVar", "vpiIntVar", "vpiShortRealVar", "vpiByteVar", "vpiClassVar", "vpiStringVar", "vpiEnumVar", "vpiStructVar", "vpiUnionVar", "vpiBitVar", "vpiClassObj", "vpiChandleVar", "vpiPackedArrayVar", "*undefined*", // 624 is not defined for object types "vpiLongIntTypespec", "vpiShortRealTypespec", "vpiByteTypespec", "vpiShortIntTypespec", "vpiIntTypespec", "vpiClassTypespec", "vpiStringTypespec", "vpiChandleTypespec", "vpiEnumTypespec", "vpiEnumConst", "vpiIntegerTypespec", "vpiTimeTypespec", "vpiRealTypespec", "vpiStructTypespec", "vpiUnionTypespec", "vpiBitTypespec", "vpiLogicTypespec", "vpiArrayTypespec", "vpiVoidTypespec", "vpiTypespecMember", "vpiDistItem", "vpiAliasStmt", "vpiThread", "vpiMethodFuncCall", "vpiMethodTaskCall", "vpiClockingBlock", "vpiClockingIODecl", "vpiClassDefn", "vpiConstraint", "vpiConstraintOrdering", "vpiPropertyDecl", "vpiPropertySpec", "vpiPropertyExpr", "vpiMulticlockSequenceExpr", "vpiClockedSeq", "vpiPropertyInst", "vpiSequenceDecl", "vpiCaseProperty", "*undefined*", // 663 is not defined for object types "vpiSequenceInst", "vpiImmediateAssert", "vpiReturn", "vpiAnyPattern", "vpiTaggedPattern", "vpiStructPattern", "vpiDoWhile", "vpiOrderedWait", "vpiWaitFork", "vpiDisableFork", "vpiExpectStmt", "vpiForeachStmt", "vpiFinal", "vpiExtends", "vpiDistribution", "vpiSeqFormalDecl", "vpiEnumNet", "vpiIntegerNet", "vpiTimeNet", "vpiStructNet", "vpiBreak", "vpiContinue", "vpiAssert", "vpiAssume", "vpiCover", "vpiDisableCondition", "vpiClockingEvent", "vpiReturnStmt", "vpiPackedArrayTypespec", "vpiPackedArrayNet", "vpiImmediateAssume", "vpiImmediateCover", "vpiSequenceTypespec", "vpiPropertyTypespec", "vpiEventTypespec", "vpiPropFormalDecl", }; // clang-format on if (vpiVal < 0) return names[0]; else if (vpiVal <= vpiAutomatics) return names[vpiVal]; else if (vpiVal >= vpiPackage && vpiVal <= vpiPropFormalDecl) return sv_names1[(vpiVal - vpiPackage)]; else return names[0]; } const char* strFromVpiMethod(PLI_INT32 vpiVal) { // clang-format off static const char* const names[] = { "vpiCondition", "vpiDelay", "vpiElseStmt", "vpiForIncStmt", "vpiForInitStmt", "vpiHighConn", "vpiLhs", "vpiIndex", "vpiLeftRange", "vpiLowConn", "vpiParent", "vpiRhs", "vpiRightRange", "vpiScope", "vpiSysTfCall", "vpiTchkDataTerm", "vpiTchkNotifier", "vpiTchkRefTerm", "vpiArgument", "vpiBit", "vpiDriver", "vpiInternalScope", "vpiLoad", "vpiModDataPathIn", "vpiModPathIn", "vpiModPathOut", "vpiOperand", "vpiPortInst", "vpiProcess", "vpiVariables", "vpiUse", "vpiExpr", "vpiPrimitive", "vpiStmt" }; // clang-format on if (vpiVal > vpiStmt || vpiVal < vpiCondition) return "*undefined*"; return names[vpiVal - vpiCondition]; } const char* strFromVpiCallbackReason(PLI_INT32 vpiVal) { // clang-format off static const char* const names[] = { "*undefined*", "cbValueChange", "cbStmt", "cbForce", "cbRelease", "cbAtStartOfSimTime", "cbReadWriteSynch", "cbReadOnlySynch", "cbNextSimTime", "cbAfterDelay", "cbEndOfCompile", "cbStartOfSimulation", "cbEndOfSimulation", "cbError", "cbTchkViolation", "cbStartOfSave", "cbEndOfSave", "cbStartOfRestart", "cbEndOfRestart", "cbStartOfReset", "cbEndOfReset", "cbEnterInteractive", "cbExitInteractive", "cbInteractiveScopeChange", "cbUnresolvedSystf", "cbAssign", "cbDeassign", "cbDisable", "cbPLIError", "cbSignal", "cbNBASynch", "cbAtEndOfSimTime" }; // clang-format on if (vpiVal < 0) return names[0]; return names[(vpiVal <= cbAtEndOfSimTime) ? vpiVal : 0]; } const char* strFromVpiProp(PLI_INT32 vpiVal) { // clang-format off static const char* const names[] = { "*undefined or other*", "vpiType", "vpiName", "vpiFullName", "vpiSize", "vpiFile", "vpiLineNo", "vpiTopModule", "vpiCellInstance", "vpiDefName", "vpiProtected", "vpiTimeUnit", "vpiTimePrecision", "vpiDefNetType", "vpiUnconnDrive", "vpiDefFile", "vpiDefLineNo", "vpiScalar", "vpiVector", "vpiExplicitName", "vpiDirection", "vpiConnByName", "vpiNetType", "vpiExplicitScalared", "vpiExplicitVectored", "vpiExpanded", "vpiImplicitDecl", "vpiChargeStrength", "vpiArray", "vpiPortIndex", "vpiTermIndex", "vpiStrength0", "vpiStrength1", "vpiPrimType", "vpiPolarity", "vpiDataPolarity", "vpiEdge", "vpiPathType", "vpiTchkType", "vpiOpType", "vpiConstType", "vpiBlocking", "vpiCaseType", "vpiFuncType", "vpiNetDeclAssign", "vpiUserDefn", "vpiScheduled", "*undefined*", "*undefined*", "vpiActive", "vpiAutomatic", "vpiCell", "vpiConfig", "vpiConstantSelect", "vpiDecompile", "vpiDefAttribute", "vpiDelayType", "vpiIteratorType", "vpiLibrary", "*undefined*", "vpiOffset", "vpiResolvedNetType", "vpiSaveRestartID", "vpiSaveRestartLocation", "vpiValid", "vpiSigned", "vpiStop", "vpiFinish", "vpiReset", "vpiSetInteractiveScope", "vpiLocalParam", "vpiModPathHasIfNone", "vpiIndexedPartSelectType", "vpiIsMemory", "vpiIsProtected" }; // clang-format on if (vpiVal == vpiUndefined) return "vpiUndefined"; return names[(vpiVal <= vpiIsProtected) ? vpiVal : 0]; } const char* strFromVpiConstType(PLI_INT32 constType) { // clang-format off static const char* const names[] = { "*undefined*", "vpiDecConst", "vpiRealConst", "vpiBinaryConst", "vpiOctConst", "vpiHexConst", "vpiStringConst", "vpiIntConst", "vpiTimeConst", }; // clang-format on if (constType < 0) return names[0]; return names[(constType <= vpiTimeConst) ? constType : 0]; } #define FILENM basename(strdup(__FILE__)) #define CHECK_RESULT_VH(got, exp) \ if ((got) != (exp)) { \ printf("%%Error: %s:%d: GOT = %p EXP = %p\n", FILENM, __LINE__, (got), (exp)); \ return __LINE__; \ } #define CHECK_RESULT_NZ(got) \ if (!(got)) { \ printf("%%Error: %s:%d: GOT = NULL EXP = !NULL\n", FILENM, __LINE__); \ return __LINE__; \ } #define CHECK_RESULT_Z(got) \ if (got) { \ printf("%%Error: %s:%d: GOT = !NULL EXP = NULL\n", FILENM, __LINE__); \ return __LINE__; \ } // Use cout to avoid issues with %d/%lx etc #define CHECK_RESULT(got, exp) \ if ((got) != (exp)) { \ std::cout << std::dec << "%Error: " << FILENM << ":" << __LINE__ << ": GOT = " << (got) \ << " EXP = " << (exp) << std::endl; \ return __LINE__; \ } #define CHECK_RESULT_HEX(got, exp) \ if ((got) != (exp)) { \ std::cout << std::dec << "%Error: " << FILENM << ":" << __LINE__ << std::hex \ << ": GOT = " << (got) << " EXP = " << (exp) << std::endl; \ return __LINE__; \ } #define CHECK_RESULT_CSTR(got, exp) \ if (std::strcmp((got), (exp))) { \ printf("%%Error: %s:%d: GOT = '%s' EXP = '%s'\n", FILENM, __LINE__, \ (got) ? (got) : "", (exp) ? (exp) : ""); \ return __LINE__; \ } #define CHECK_RESULT_CSTR_STRIP(got, exp) CHECK_RESULT_CSTR(got + strspn(got, " "), exp) verilator-5.044/test_regress/t/t_always_chg_first.v0000644000542200017500000000354515125463617023152 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk, fastclk ); input clk; input fastclk; // surefire lint_off_line UDDIXN integer _mode; initial _mode=0; reg [31:0] ord1; initial ord1 = 32'h1111; wire [31:0] ord2; reg [31:0] ord3; wire [31:0] ord4; wire [31:0] ord5; wire [31:0] ord6; wire [31:0] ord7; // verilator lint_off UNOPT t_chg_a a ( .a(ord1), .a_p1(ord2), .b(ord4), .b_p1(ord5), .c(ord3), .c_p1(ord4), .d(ord6), .d_p1(ord7) ); // surefire lint_off ASWEMB assign ord6 = ord5 + 1; // verilator lint_on UNOPT always @ (/*AS*/ord2) ord3 = ord2 + 1; always @ (fastclk) begin // surefire lint_off_line ALWLTR ALWMTR if (_mode==1) begin //$write("[%0t] t_chg: %d: Values: %x %x %x %x %x %x %x\n", $time,fastclk,ord1,ord2,ord3,ord4,ord5,ord6,ord7); //if (ord2 == 2 && ord7 != 7) $stop; end end always @ (posedge clk) begin if (_mode==0) begin $write("[%0t] t_chg: Running\n", $time); _mode<=1; ord1 <= 1; end else if (_mode==1) begin _mode<=2; if (ord7 !== 7) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module t_chg_a (/*AUTOARG*/ // Outputs a_p1, b_p1, c_p1, d_p1, // Inputs a, b, c, d ); input [31:0] a; output [31:0] a_p1; wire [31:0] a_p1 = a + 1; input [31:0] b; output [31:0] b_p1; wire [31:0] b_p1 = b + 1; input [31:0] c; output [31:0] c_p1; wire [31:0] c_p1 = c + 1; input [31:0] d; output [31:0] d_p1; wire [31:0] d_p1 = d + 1; endmodule verilator-5.044/test_regress/t/t_expect.v0000644000542200017500000000113515125463617021103 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg a; reg b; initial begin #10; expect (@(posedge clk) a ##1 b) a = 110; #10; expect (@(posedge clk) a ##1 b) else a = 299; #10; expect (@(posedge clk) a ##1 b) a = 300; else a = 399; end // TODO set a/b appropriately - this is just a parsing test currently endmodule verilator-5.044/test_regress/t/t_dpi_inline_new.cpp0000644000542200017500000000134015125463617023111 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: DPI stub for t_dpi_inline_new // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Include the Verilator-generated DPI header so the C prototype matches // the SystemVerilog import expectations. #include "Vt_dpi_inline_new__Dpi.h" #ifdef __cplusplus extern "C" { #endif // Stub implementation for _pyhdl_if_PyTuple_GetItem used by pyhdl_if package. // Returns a null pointer; the SystemVerilog test only checks that the call // compiles and links. void* _pyhdl_if_PyTuple_GetItem(void* p0, unsigned long long idx) { (void)p0; (void)idx; return 0; } #ifdef __cplusplus } #endif verilator-5.044/test_regress/t/t_lint_input_eq_good.py0000755000542200017500000000070315125463617023663 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint() test.passes() verilator-5.044/test_regress/t/t_unroll_delay.py0000755000542200017500000000105115125463617022467 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary --trace-vcd']) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_func_wide_out.v0000644000542200017500000000730115125463617022446 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); typedef bit signed [11:0] s12_t; typedef bit unsigned [11:0] u12_t; typedef bit signed [69:0] s70_t; typedef bit unsigned [69:0] u70_t; import "DPI-C" context function void dpii_inv_s12(input s12_t in, output s12_t out); import "DPI-C" context function void dpii_inv_u12(input u12_t in, output u12_t out); import "DPI-C" context function void dpii_inv_s70(input s70_t in, output s70_t out); import "DPI-C" context function void dpii_inv_u70(input s70_t in, output u70_t out); class Cls #(type T = bit); static function void get(inout T value); `ifdef TEST_NOINLINE // verilator no_inline_task `endif value = ~value; endfunction endclass module t; parameter MSG_PORT_WIDTH = 4350; localparam PAYLOAD_MAX_BITS = 4352; reg [MSG_PORT_WIDTH-1:0] msg; function void func (output bit [PAYLOAD_MAX_BITS-1:0] data); `ifdef TEST_NOINLINE // verilator no_inline_task `endif data = {PAYLOAD_MAX_BITS{1'b1}}; endfunction s12_t ds12; u12_t du12; s70_t ds70; u70_t du70; s12_t qs12; u12_t qu12; s70_t qs70; u70_t qu70; initial begin // Operator TASKREF 'func' expects 4352 bits on the Function Argument, but Function Argument's VARREF 'msg' generates 4350 bits. // verilator lint_off WIDTHEXPAND func(msg); if (msg !== {MSG_PORT_WIDTH{1'b1}}) $stop; begin // narrow connect to wide ds12 = 12'h234; Cls#(s70_t)::get(ds12); `checkh(ds12, 12'hdcb); ds12 = 12'he34; // negative if signed Cls#(s70_t)::get(ds12); `checkh(ds12, 12'h1cb); du12 = 12'h244; Cls#(u70_t)::get(du12); `checkh(du12, 12'hdbb); du12 = 12'he34; // negative if signed Cls#(u70_t)::get(du12); `checkh(du12, 12'h1cb); // wie connect to narrow ds70 = 12'h254; Cls#(s12_t)::get(ds70); `checkh(ds70, 70'h3ffffffffffffffdab); ds70 = 12'he34; // negative if signed Cls#(s12_t)::get(ds70); `checkh(ds70, 70'h0000000000000001cb); du70 = 12'h264; Cls#(u12_t)::get(du70); `checkh(du70, 70'h000000000000000d9b); du70 = 12'he34; // negative if signed Cls#(u12_t)::get(du70); `checkh(du70, 70'h0000000000000001cb); end begin // narrow connect to wide ds12 = 12'h234; dpii_inv_s70(ds12, qs12); `checkh(qs12, 12'hdcb); ds12 = 12'he34; // negative if signed dpii_inv_s70(ds12, qs12); `checkh(qs12, 12'h1cb); du12 = 12'h244; dpii_inv_u70(du12, qu12); `checkh(qu12, 12'hdbb); du12 = 12'he34; // negative if signed dpii_inv_u70(ds12, qs12); `checkh(qs12, 12'h1cb); // wie connect to narrow ds70 = 12'h254; dpii_inv_s12(ds70, qs70); `checkh(qs70, 70'h3ffffffffffffffdab); ds70 = 12'he34; // negative if signed dpii_inv_s12(ds70, qs70); `checkh(qs70, 70'h0000000000000001cb); du70 = 12'h264; dpii_inv_u12(du70, qu70); `checkh(qu70, 70'h000000000000000d9b); du70 = 12'he34; // negative if signed dpii_inv_u12(du70, qu70); `checkh(qu70, 70'h0000000000000001cb); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_interface_localparam.v0000644000542200017500000000254115125463617023750 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Justin Thiel. // SPDX-License-Identifier: CC0-1.0 interface SimpleIntf #( parameter int VAL = 28 ) (); // This value is calculated incorrectly for other instances of // this interface when it is accessed via the HDL for any other // instance of this interface localparam int valDiv2 = VAL/2; localparam int valDiv4 = valDiv2/2; localparam bit mismatch2 = (VAL != (2*valDiv2) ); localparam bit mismatch4 = (VAL != (4*valDiv4) ); initial begin $write("%m: VAL %0d, valDiv2 %0d, mismatch2 %0d\n", VAL, valDiv2, mismatch2); $write("%m: VAL %0d, valDiv4 %0d, mismatch4 %0d\n", VAL, valDiv4, mismatch2); if (mismatch2) $stop; if (mismatch4) $stop; end endinterface module Core( SimpleIntf intf ); // this will constify and valDiv2 will have the default value localparam valDiv4Upper = intf.valDiv2; SimpleIntf #(.VAL(68)) core_intf (); initial begin if (intf.valDiv2 != valDiv4Upper) begin $display("%%Error: param = %0d", intf.valDiv2); end end endmodule module t(); SimpleIntf intf(); Core theCore (.intf); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_sys_file_basic_mcd.py0000755000542200017500000000217115125463617023603 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.unlink_ok(test.obj_dir + "/t_sys_file_basic_mcd.log") test.compile() test.execute(expect_filename=test.golden_filename) test.files_identical(test.obj_dir + "/t_sys_file_basic_mcd_test2_0.dat", test.t_dir + "/t_sys_file_basic_mcd_test2_0.dat") test.files_identical(test.obj_dir + "/t_sys_file_basic_mcd_test2_1.dat", test.t_dir + "/t_sys_file_basic_mcd_test2_1.dat") test.files_identical(test.obj_dir + "/t_sys_file_basic_mcd_test2_2.dat", test.t_dir + "/t_sys_file_basic_mcd_test2_2.dat") test.files_identical(test.obj_dir + "/t_sys_file_basic_mcd_test5.dat", test.t_dir + "/t_sys_file_basic_mcd_test5.dat") test.passes() verilator-5.044/test_regress/t/t_cover_line_cc_vlt.py0000755000542200017500000000176615125463617023472 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_cover_line.v" test.golden_filename = "t/t_cover_line.out" test.compile(verilator_flags2=['--cc', '--coverage-line', "t/t_cover_line.vlt"]) test.execute() # Read the input .v file and do any CHECK_COVER requests test.inline_checks() test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--annotate-points", "--annotate", test.obj_dir + "/annotated", test.obj_dir + "/coverage.dat", ], verilator_run=True) test.files_identical(test.obj_dir + "/annotated/t_cover_line.v", test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_opt_balance_cats.py0000755000542200017500000000131415125463617023261 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile( verilator_flags2=["--stats", "--build", "--gate-stmts", "10000", "--expand-limit", "128"]) test.file_grep(test.stats, r'Optimizations, FuncOpt concat trees balanced\s+(\d+)', 1) test.file_grep(test.stats, r'Optimizations, FuncOpt concat splits\s+(\d+)', 62) test.passes() verilator-5.044/test_regress/t/t_package_alone_bad.v0000644000542200017500000000033315125463617023171 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 export pkg::something; verilator-5.044/test_regress/t/t_preproc_persist_inc.v0000644000542200017500000000043415125463617023670 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifndef COMMON_GUARD `define COMMON_GUARD 1 Inside `__FILE__. `endif verilator-5.044/test_regress/t/t_assert_inside_cond_bad.py0000755000542200017500000000117715125463617024454 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_assert_inside_cond.v" test.compile(verilator_flags2=["-x-assign 0 --assert +define+T_ASSERT_INSIDE_COND_BAD"]) test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_class_to_basic_assignment_bad.py0000755000542200017500000000076615125463617026020 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_covergroup_option_bad.v0000644000542200017500000000111315125463617024200 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Verilator lint_off COVERIGN module t; covergroup cg_opt; type_option.weight = 1; // ok option.name = "the_name"; // pk bad_cg_non_option.name = "xx"; // <--- Bad endgroup covergroup cg_cross3; cross a, b{ option.comment = "cross"; // ok bad_cross_non_option.name = "xx"; // <--- Bad } endgroup initial $stop; endmodule verilator-5.044/test_regress/t/t_assert_future.py0000755000542200017500000000077115125463617022701 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert']) test.execute() test.passes() verilator-5.044/test_regress/t/t_with_suggest_bad.out0000644000542200017500000000120415125463617023474 0ustar mahmoudyfreeshell%Error: t/t_with_suggest_bad.v:16:25: Can't find definition of variable: 'itemm' : ... Suggested alternative: 'item' 16 | qv = q.find with (itemm == 2); | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_with_suggest_bad.v:18:37: Can't find definition of variable: 'misspelledd' : ... Suggested alternative: 'misspelled' 18 | qv = q.find(misspelled) with (misspelledd == 2); | ^~~~~~~~~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_array_pattern_bad.v0000644000542200017500000000075015125463617023276 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug1364 module t (/*AUTOARG*/ // Inputs clk, res ); input clk; input res; typedef struct packed { logic [3:0] port_num; } info_t; info_t myinfo; always_comb myinfo = '{default: '0, valids: '1}; endmodule verilator-5.044/test_regress/t/t_func_purification.v0000644000542200017500000000076715125463617023334 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; initial begin if (0 & func(1)) $stop; $write("*-* All Finished *-*\n"); $finish; end function bit func(bit x); if (x) begin if (x) begin return 1; end else begin $c(""); end return 0; end endfunction endmodule verilator-5.044/test_regress/t/t_split_var_3_wreal.py0000755000542200017500000000130015125463617023412 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--stats', "-fno-dfg"]) test.execute() test.file_grep(test.stats, r'SplitVar,\s+packed variables split due to attribute\s+(\d+)', 0) test.file_grep(test.stats, r'SplitVar,\s+unpacked arrays split due to attribute\s+(\d+)', 3) test.passes() verilator-5.044/test_regress/t/t_cast_size_bad.v0000644000542200017500000000051015125463617022401 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; int a; reg [3:0] b; initial begin a = 1; b = (-1)'(a); // Bad end endmodule verilator-5.044/test_regress/t/t_sys_readmem_bad_addr2.mem0000644000542200017500000000054215125463617024317 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @10x 10x verilator-5.044/test_regress/t/t_func_nansi_dup_bad.out0000644000542200017500000000122715125463617023760 0ustar mahmoudyfreeshell%Error: t/t_func_nansi_dup_bad.v:14:9: Duplicate declaration of signal: 'bad4' 14 | reg bad4; | ^~~~ t/t_func_nansi_dup_bad.v:12:17: ... Location of original declaration 12 | input [7:0] bad4; | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_func_nansi_dup_bad.v:19:17: Duplicate declaration of signal: 'bad5' 19 | input [7:0] bad5; | ^~~~ t/t_func_nansi_dup_bad.v:18:17: ... Location of original declaration 18 | input [7:0] bad5; | ^~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_parse_delay_timing.py0000755000542200017500000000102115125463617023632 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_parse_delay.v" test.compile(verilator_flags2=['--binary']) test.passes() verilator-5.044/test_regress/t/t_func_tie_bad.v0000644000542200017500000000066215125463617022221 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin // verilator lint_off IGNOREDRETURN func(0, 1'b1); end function automatic int func ( input int a, output bit b ); return 0; endfunction endmodule verilator-5.044/test_regress/t/t_trace_dumpvars_dyn.v0000644000542200017500000000150015125463617023500 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc; sub1 #(10) sub1a (.*); sub1 #(20) sub1b (.*); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub1 #(parameter int ADD) (input int cyc); int value; always_comb value = cyc + ADD; sub2 #(ADD + 1) sub2a(.*); sub2 #(ADD + 2) sub2b(.*); sub2 #(ADD + 3) sub2c(.*); endmodule module sub2 #(parameter int ADD) (input int cyc); int value; always_comb value = cyc + ADD; endmodule verilator-5.044/test_regress/t/t_assert_ctl_arg.dat.out0000644000542200017500000005176415125463617023735 0ustar mahmoudyfreeshell# SystemC::Coverage-3 C 'ft/t_assert_ctl_arg.vl100n32tuserpagev_user/tocover_simple_immediate_100htop.t.cover_simple_immediate_100' 1 C 'ft/t_assert_ctl_arg.vl100n37tuserpagev_user/tocover_simple_immediate_stmt_100htop.t.cover_simple_immediate_stmt_100' 1 C 'ft/t_assert_ctl_arg.vl100n40tuserpagev_user/tocover_final_deferred_immediate_100htop.t.cover_final_deferred_immediate_100' 1 C 'ft/t_assert_ctl_arg.vl100n43tuserpagev_user/tocover_observed_deferred_immediate_100htop.t.cover_observed_deferred_immediate_100' 1 C 'ft/t_assert_ctl_arg.vl100n45tuserpagev_user/tocover_final_deferred_immediate_stmt_100htop.t.cover_final_deferred_immediate_stmt_100' 1 C 'ft/t_assert_ctl_arg.vl100n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_100htop.t.cover_observed_deferred_immediate_stmt_100' 1 C 'ft/t_assert_ctl_arg.vl103n32tuserpagev_user/tocover_simple_immediate_103htop.t.cover_simple_immediate_103' 0 C 'ft/t_assert_ctl_arg.vl103n37tuserpagev_user/tocover_simple_immediate_stmt_103htop.t.cover_simple_immediate_stmt_103' 0 C 'ft/t_assert_ctl_arg.vl103n40tuserpagev_user/tocover_final_deferred_immediate_103htop.t.cover_final_deferred_immediate_103' 0 C 'ft/t_assert_ctl_arg.vl103n43tuserpagev_user/tocover_observed_deferred_immediate_103htop.t.cover_observed_deferred_immediate_103' 0 C 'ft/t_assert_ctl_arg.vl103n45tuserpagev_user/tocover_final_deferred_immediate_stmt_103htop.t.cover_final_deferred_immediate_stmt_103' 0 C 'ft/t_assert_ctl_arg.vl103n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_103htop.t.cover_observed_deferred_immediate_stmt_103' 0 C 'ft/t_assert_ctl_arg.vl106n32tuserpagev_user/tocover_simple_immediate_106htop.t.cover_simple_immediate_106' 1 C 'ft/t_assert_ctl_arg.vl106n37tuserpagev_user/tocover_simple_immediate_stmt_106htop.t.cover_simple_immediate_stmt_106' 1 C 'ft/t_assert_ctl_arg.vl106n40tuserpagev_user/tocover_final_deferred_immediate_106htop.t.cover_final_deferred_immediate_106' 1 C 'ft/t_assert_ctl_arg.vl106n43tuserpagev_user/tocover_observed_deferred_immediate_106htop.t.cover_observed_deferred_immediate_106' 1 C 'ft/t_assert_ctl_arg.vl106n45tuserpagev_user/tocover_final_deferred_immediate_stmt_106htop.t.cover_final_deferred_immediate_stmt_106' 1 C 'ft/t_assert_ctl_arg.vl106n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_106htop.t.cover_observed_deferred_immediate_stmt_106' 1 C 'ft/t_assert_ctl_arg.vl108n32tuserpagev_user/tocover_simple_immediate_108htop.t.cover_simple_immediate_108' 1 C 'ft/t_assert_ctl_arg.vl108n37tuserpagev_user/tocover_simple_immediate_stmt_108htop.t.cover_simple_immediate_stmt_108' 1 C 'ft/t_assert_ctl_arg.vl108n40tuserpagev_user/tocover_final_deferred_immediate_108htop.t.cover_final_deferred_immediate_108' 1 C 'ft/t_assert_ctl_arg.vl108n43tuserpagev_user/tocover_observed_deferred_immediate_108htop.t.cover_observed_deferred_immediate_108' 1 C 'ft/t_assert_ctl_arg.vl108n45tuserpagev_user/tocover_final_deferred_immediate_stmt_108htop.t.cover_final_deferred_immediate_stmt_108' 1 C 'ft/t_assert_ctl_arg.vl108n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_108htop.t.cover_observed_deferred_immediate_stmt_108' 1 C 'ft/t_assert_ctl_arg.vl110n32tuserpagev_user/tocover_simple_immediate_110htop.t.cover_simple_immediate_110' 0 C 'ft/t_assert_ctl_arg.vl110n37tuserpagev_user/tocover_simple_immediate_stmt_110htop.t.cover_simple_immediate_stmt_110' 0 C 'ft/t_assert_ctl_arg.vl110n40tuserpagev_user/tocover_final_deferred_immediate_110htop.t.cover_final_deferred_immediate_110' 0 C 'ft/t_assert_ctl_arg.vl110n43tuserpagev_user/tocover_observed_deferred_immediate_110htop.t.cover_observed_deferred_immediate_110' 0 C 'ft/t_assert_ctl_arg.vl110n45tuserpagev_user/tocover_final_deferred_immediate_stmt_110htop.t.cover_final_deferred_immediate_stmt_110' 0 C 'ft/t_assert_ctl_arg.vl110n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_110htop.t.cover_observed_deferred_immediate_stmt_110' 0 C 'ft/t_assert_ctl_arg.vl112n32tuserpagev_user/tocover_simple_immediate_112htop.t.cover_simple_immediate_112' 1 C 'ft/t_assert_ctl_arg.vl112n37tuserpagev_user/tocover_simple_immediate_stmt_112htop.t.cover_simple_immediate_stmt_112' 1 C 'ft/t_assert_ctl_arg.vl112n40tuserpagev_user/tocover_final_deferred_immediate_112htop.t.cover_final_deferred_immediate_112' 1 C 'ft/t_assert_ctl_arg.vl112n43tuserpagev_user/tocover_observed_deferred_immediate_112htop.t.cover_observed_deferred_immediate_112' 0 C 'ft/t_assert_ctl_arg.vl112n45tuserpagev_user/tocover_final_deferred_immediate_stmt_112htop.t.cover_final_deferred_immediate_stmt_112' 1 C 'ft/t_assert_ctl_arg.vl112n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_112htop.t.cover_observed_deferred_immediate_stmt_112' 0 C 'ft/t_assert_ctl_arg.vl192n22tuserpagev_user/concurrentocover_concurrenthtop.t.concurrent.cover_concurrent' 0 C 'ft/t_assert_ctl_arg.vl193n27tuserpagev_user/concurrentocover_concurrent_stmthtop.t.concurrent.cover_concurrent_stmt' 0 C 'ft/t_assert_ctl_arg.vl49n31tuserpagev_user/tocover_simple_immediate_49htop.t.cover_simple_immediate_49' 1 C 'ft/t_assert_ctl_arg.vl49n36tuserpagev_user/tocover_simple_immediate_stmt_49htop.t.cover_simple_immediate_stmt_49' 1 C 'ft/t_assert_ctl_arg.vl49n39tuserpagev_user/tocover_final_deferred_immediate_49htop.t.cover_final_deferred_immediate_49' 0 C 'ft/t_assert_ctl_arg.vl49n42tuserpagev_user/tocover_observed_deferred_immediate_49htop.t.cover_observed_deferred_immediate_49' 0 C 'ft/t_assert_ctl_arg.vl49n44tuserpagev_user/tocover_final_deferred_immediate_stmt_49htop.t.cover_final_deferred_immediate_stmt_49' 0 C 'ft/t_assert_ctl_arg.vl49n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_49htop.t.cover_observed_deferred_immediate_stmt_49' 0 C 'ft/t_assert_ctl_arg.vl51n31tuserpagev_user/tocover_simple_immediate_51htop.t.cover_simple_immediate_51' 0 C 'ft/t_assert_ctl_arg.vl51n36tuserpagev_user/tocover_simple_immediate_stmt_51htop.t.cover_simple_immediate_stmt_51' 0 C 'ft/t_assert_ctl_arg.vl51n39tuserpagev_user/tocover_final_deferred_immediate_51htop.t.cover_final_deferred_immediate_51' 0 C 'ft/t_assert_ctl_arg.vl51n42tuserpagev_user/tocover_observed_deferred_immediate_51htop.t.cover_observed_deferred_immediate_51' 0 C 'ft/t_assert_ctl_arg.vl51n44tuserpagev_user/tocover_final_deferred_immediate_stmt_51htop.t.cover_final_deferred_immediate_stmt_51' 0 C 'ft/t_assert_ctl_arg.vl51n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_51htop.t.cover_observed_deferred_immediate_stmt_51' 0 C 'ft/t_assert_ctl_arg.vl56n31tuserpagev_user/tocover_simple_immediate_56htop.t.cover_simple_immediate_56' 0 C 'ft/t_assert_ctl_arg.vl56n36tuserpagev_user/tocover_simple_immediate_stmt_56htop.t.cover_simple_immediate_stmt_56' 0 C 'ft/t_assert_ctl_arg.vl56n39tuserpagev_user/tocover_final_deferred_immediate_56htop.t.cover_final_deferred_immediate_56' 0 C 'ft/t_assert_ctl_arg.vl56n42tuserpagev_user/tocover_observed_deferred_immediate_56htop.t.cover_observed_deferred_immediate_56' 1 C 'ft/t_assert_ctl_arg.vl56n44tuserpagev_user/tocover_final_deferred_immediate_stmt_56htop.t.cover_final_deferred_immediate_stmt_56' 0 C 'ft/t_assert_ctl_arg.vl56n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_56htop.t.cover_observed_deferred_immediate_stmt_56' 1 C 'ft/t_assert_ctl_arg.vl58n31tuserpagev_user/tocover_simple_immediate_58htop.t.cover_simple_immediate_58' 0 C 'ft/t_assert_ctl_arg.vl58n36tuserpagev_user/tocover_simple_immediate_stmt_58htop.t.cover_simple_immediate_stmt_58' 0 C 'ft/t_assert_ctl_arg.vl58n39tuserpagev_user/tocover_final_deferred_immediate_58htop.t.cover_final_deferred_immediate_58' 0 C 'ft/t_assert_ctl_arg.vl58n42tuserpagev_user/tocover_observed_deferred_immediate_58htop.t.cover_observed_deferred_immediate_58' 0 C 'ft/t_assert_ctl_arg.vl58n44tuserpagev_user/tocover_final_deferred_immediate_stmt_58htop.t.cover_final_deferred_immediate_stmt_58' 0 C 'ft/t_assert_ctl_arg.vl58n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_58htop.t.cover_observed_deferred_immediate_stmt_58' 0 C 'ft/t_assert_ctl_arg.vl63n31tuserpagev_user/tocover_simple_immediate_63htop.t.cover_simple_immediate_63' 0 C 'ft/t_assert_ctl_arg.vl63n36tuserpagev_user/tocover_simple_immediate_stmt_63htop.t.cover_simple_immediate_stmt_63' 0 C 'ft/t_assert_ctl_arg.vl63n39tuserpagev_user/tocover_final_deferred_immediate_63htop.t.cover_final_deferred_immediate_63' 1 C 'ft/t_assert_ctl_arg.vl63n42tuserpagev_user/tocover_observed_deferred_immediate_63htop.t.cover_observed_deferred_immediate_63' 0 C 'ft/t_assert_ctl_arg.vl63n44tuserpagev_user/tocover_final_deferred_immediate_stmt_63htop.t.cover_final_deferred_immediate_stmt_63' 1 C 'ft/t_assert_ctl_arg.vl63n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_63htop.t.cover_observed_deferred_immediate_stmt_63' 0 C 'ft/t_assert_ctl_arg.vl65n31tuserpagev_user/tocover_simple_immediate_65htop.t.cover_simple_immediate_65' 0 C 'ft/t_assert_ctl_arg.vl65n36tuserpagev_user/tocover_simple_immediate_stmt_65htop.t.cover_simple_immediate_stmt_65' 0 C 'ft/t_assert_ctl_arg.vl65n39tuserpagev_user/tocover_final_deferred_immediate_65htop.t.cover_final_deferred_immediate_65' 0 C 'ft/t_assert_ctl_arg.vl65n42tuserpagev_user/tocover_observed_deferred_immediate_65htop.t.cover_observed_deferred_immediate_65' 0 C 'ft/t_assert_ctl_arg.vl65n44tuserpagev_user/tocover_final_deferred_immediate_stmt_65htop.t.cover_final_deferred_immediate_stmt_65' 0 C 'ft/t_assert_ctl_arg.vl65n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_65htop.t.cover_observed_deferred_immediate_stmt_65' 0 C 'ft/t_assert_ctl_arg.vl69n31tuserpagev_user/tocover_simple_immediate_69htop.t.cover_simple_immediate_69' 0 C 'ft/t_assert_ctl_arg.vl69n36tuserpagev_user/tocover_simple_immediate_stmt_69htop.t.cover_simple_immediate_stmt_69' 0 C 'ft/t_assert_ctl_arg.vl69n39tuserpagev_user/tocover_final_deferred_immediate_69htop.t.cover_final_deferred_immediate_69' 0 C 'ft/t_assert_ctl_arg.vl69n42tuserpagev_user/tocover_observed_deferred_immediate_69htop.t.cover_observed_deferred_immediate_69' 0 C 'ft/t_assert_ctl_arg.vl69n44tuserpagev_user/tocover_final_deferred_immediate_stmt_69htop.t.cover_final_deferred_immediate_stmt_69' 0 C 'ft/t_assert_ctl_arg.vl69n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_69htop.t.cover_observed_deferred_immediate_stmt_69' 0 C 'ft/t_assert_ctl_arg.vl71n31tuserpagev_user/tocover_simple_immediate_71htop.t.cover_simple_immediate_71' 1 C 'ft/t_assert_ctl_arg.vl71n36tuserpagev_user/tocover_simple_immediate_stmt_71htop.t.cover_simple_immediate_stmt_71' 1 C 'ft/t_assert_ctl_arg.vl71n39tuserpagev_user/tocover_final_deferred_immediate_71htop.t.cover_final_deferred_immediate_71' 1 C 'ft/t_assert_ctl_arg.vl71n42tuserpagev_user/tocover_observed_deferred_immediate_71htop.t.cover_observed_deferred_immediate_71' 1 C 'ft/t_assert_ctl_arg.vl71n44tuserpagev_user/tocover_final_deferred_immediate_stmt_71htop.t.cover_final_deferred_immediate_stmt_71' 1 C 'ft/t_assert_ctl_arg.vl71n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_71htop.t.cover_observed_deferred_immediate_stmt_71' 1 C 'ft/t_assert_ctl_arg.vl73n31tuserpagev_user/tocover_simple_immediate_73htop.t.cover_simple_immediate_73' 0 C 'ft/t_assert_ctl_arg.vl73n36tuserpagev_user/tocover_simple_immediate_stmt_73htop.t.cover_simple_immediate_stmt_73' 0 C 'ft/t_assert_ctl_arg.vl73n39tuserpagev_user/tocover_final_deferred_immediate_73htop.t.cover_final_deferred_immediate_73' 0 C 'ft/t_assert_ctl_arg.vl73n42tuserpagev_user/tocover_observed_deferred_immediate_73htop.t.cover_observed_deferred_immediate_73' 0 C 'ft/t_assert_ctl_arg.vl73n44tuserpagev_user/tocover_final_deferred_immediate_stmt_73htop.t.cover_final_deferred_immediate_stmt_73' 0 C 'ft/t_assert_ctl_arg.vl73n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_73htop.t.cover_observed_deferred_immediate_stmt_73' 0 C 'ft/t_assert_ctl_arg.vl76n31tuserpagev_user/tocover_simple_immediate_76htop.t.cover_simple_immediate_76' 1 C 'ft/t_assert_ctl_arg.vl76n36tuserpagev_user/tocover_simple_immediate_stmt_76htop.t.cover_simple_immediate_stmt_76' 1 C 'ft/t_assert_ctl_arg.vl76n39tuserpagev_user/tocover_final_deferred_immediate_76htop.t.cover_final_deferred_immediate_76' 0 C 'ft/t_assert_ctl_arg.vl76n42tuserpagev_user/tocover_observed_deferred_immediate_76htop.t.cover_observed_deferred_immediate_76' 1 C 'ft/t_assert_ctl_arg.vl76n44tuserpagev_user/tocover_final_deferred_immediate_stmt_76htop.t.cover_final_deferred_immediate_stmt_76' 0 C 'ft/t_assert_ctl_arg.vl76n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_76htop.t.cover_observed_deferred_immediate_stmt_76' 1 C 'ft/t_assert_ctl_arg.vl78n31tuserpagev_user/tocover_simple_immediate_78htop.t.cover_simple_immediate_78' 1 C 'ft/t_assert_ctl_arg.vl78n36tuserpagev_user/tocover_simple_immediate_stmt_78htop.t.cover_simple_immediate_stmt_78' 1 C 'ft/t_assert_ctl_arg.vl78n39tuserpagev_user/tocover_final_deferred_immediate_78htop.t.cover_final_deferred_immediate_78' 1 C 'ft/t_assert_ctl_arg.vl78n42tuserpagev_user/tocover_observed_deferred_immediate_78htop.t.cover_observed_deferred_immediate_78' 1 C 'ft/t_assert_ctl_arg.vl78n44tuserpagev_user/tocover_final_deferred_immediate_stmt_78htop.t.cover_final_deferred_immediate_stmt_78' 1 C 'ft/t_assert_ctl_arg.vl78n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_78htop.t.cover_observed_deferred_immediate_stmt_78' 1 C 'ft/t_assert_ctl_arg.vl80n31tuserpagev_user/tocover_simple_immediate_80htop.t.cover_simple_immediate_80' 1 C 'ft/t_assert_ctl_arg.vl80n36tuserpagev_user/tocover_simple_immediate_stmt_80htop.t.cover_simple_immediate_stmt_80' 1 C 'ft/t_assert_ctl_arg.vl80n39tuserpagev_user/tocover_final_deferred_immediate_80htop.t.cover_final_deferred_immediate_80' 0 C 'ft/t_assert_ctl_arg.vl80n42tuserpagev_user/tocover_observed_deferred_immediate_80htop.t.cover_observed_deferred_immediate_80' 0 C 'ft/t_assert_ctl_arg.vl80n44tuserpagev_user/tocover_final_deferred_immediate_stmt_80htop.t.cover_final_deferred_immediate_stmt_80' 0 C 'ft/t_assert_ctl_arg.vl80n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_80htop.t.cover_observed_deferred_immediate_stmt_80' 0 C 'ft/t_assert_ctl_arg.vl82n31tuserpagev_user/tocover_simple_immediate_82htop.t.cover_simple_immediate_82' 1 C 'ft/t_assert_ctl_arg.vl82n36tuserpagev_user/tocover_simple_immediate_stmt_82htop.t.cover_simple_immediate_stmt_82' 1 C 'ft/t_assert_ctl_arg.vl82n39tuserpagev_user/tocover_final_deferred_immediate_82htop.t.cover_final_deferred_immediate_82' 0 C 'ft/t_assert_ctl_arg.vl82n42tuserpagev_user/tocover_observed_deferred_immediate_82htop.t.cover_observed_deferred_immediate_82' 0 C 'ft/t_assert_ctl_arg.vl82n44tuserpagev_user/tocover_final_deferred_immediate_stmt_82htop.t.cover_final_deferred_immediate_stmt_82' 0 C 'ft/t_assert_ctl_arg.vl82n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_82htop.t.cover_observed_deferred_immediate_stmt_82' 0 C 'ft/t_assert_ctl_arg.vl84n31tuserpagev_user/tocover_simple_immediate_84htop.t.cover_simple_immediate_84' 0 C 'ft/t_assert_ctl_arg.vl84n36tuserpagev_user/tocover_simple_immediate_stmt_84htop.t.cover_simple_immediate_stmt_84' 0 C 'ft/t_assert_ctl_arg.vl84n39tuserpagev_user/tocover_final_deferred_immediate_84htop.t.cover_final_deferred_immediate_84' 0 C 'ft/t_assert_ctl_arg.vl84n42tuserpagev_user/tocover_observed_deferred_immediate_84htop.t.cover_observed_deferred_immediate_84' 0 C 'ft/t_assert_ctl_arg.vl84n44tuserpagev_user/tocover_final_deferred_immediate_stmt_84htop.t.cover_final_deferred_immediate_stmt_84' 0 C 'ft/t_assert_ctl_arg.vl84n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_84htop.t.cover_observed_deferred_immediate_stmt_84' 0 C 'ft/t_assert_ctl_arg.vl86n31tuserpagev_user/tocover_simple_immediate_86htop.t.cover_simple_immediate_86' 1 C 'ft/t_assert_ctl_arg.vl86n36tuserpagev_user/tocover_simple_immediate_stmt_86htop.t.cover_simple_immediate_stmt_86' 1 C 'ft/t_assert_ctl_arg.vl86n39tuserpagev_user/tocover_final_deferred_immediate_86htop.t.cover_final_deferred_immediate_86' 0 C 'ft/t_assert_ctl_arg.vl86n42tuserpagev_user/tocover_observed_deferred_immediate_86htop.t.cover_observed_deferred_immediate_86' 0 C 'ft/t_assert_ctl_arg.vl86n44tuserpagev_user/tocover_final_deferred_immediate_stmt_86htop.t.cover_final_deferred_immediate_stmt_86' 0 C 'ft/t_assert_ctl_arg.vl86n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_86htop.t.cover_observed_deferred_immediate_stmt_86' 0 C 'ft/t_assert_ctl_arg.vl88n31tuserpagev_user/tocover_simple_immediate_88htop.t.cover_simple_immediate_88' 0 C 'ft/t_assert_ctl_arg.vl88n36tuserpagev_user/tocover_simple_immediate_stmt_88htop.t.cover_simple_immediate_stmt_88' 0 C 'ft/t_assert_ctl_arg.vl88n39tuserpagev_user/tocover_final_deferred_immediate_88htop.t.cover_final_deferred_immediate_88' 0 C 'ft/t_assert_ctl_arg.vl88n42tuserpagev_user/tocover_observed_deferred_immediate_88htop.t.cover_observed_deferred_immediate_88' 0 C 'ft/t_assert_ctl_arg.vl88n44tuserpagev_user/tocover_final_deferred_immediate_stmt_88htop.t.cover_final_deferred_immediate_stmt_88' 0 C 'ft/t_assert_ctl_arg.vl88n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_88htop.t.cover_observed_deferred_immediate_stmt_88' 0 C 'ft/t_assert_ctl_arg.vl90n31tuserpagev_user/tocover_simple_immediate_90htop.t.cover_simple_immediate_90' 1 C 'ft/t_assert_ctl_arg.vl90n36tuserpagev_user/tocover_simple_immediate_stmt_90htop.t.cover_simple_immediate_stmt_90' 1 C 'ft/t_assert_ctl_arg.vl90n39tuserpagev_user/tocover_final_deferred_immediate_90htop.t.cover_final_deferred_immediate_90' 1 C 'ft/t_assert_ctl_arg.vl90n42tuserpagev_user/tocover_observed_deferred_immediate_90htop.t.cover_observed_deferred_immediate_90' 1 C 'ft/t_assert_ctl_arg.vl90n44tuserpagev_user/tocover_final_deferred_immediate_stmt_90htop.t.cover_final_deferred_immediate_stmt_90' 1 C 'ft/t_assert_ctl_arg.vl90n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_90htop.t.cover_observed_deferred_immediate_stmt_90' 1 C 'ft/t_assert_ctl_arg.vl92n31tuserpagev_user/tocover_simple_immediate_92htop.t.cover_simple_immediate_92' 0 C 'ft/t_assert_ctl_arg.vl92n36tuserpagev_user/tocover_simple_immediate_stmt_92htop.t.cover_simple_immediate_stmt_92' 0 C 'ft/t_assert_ctl_arg.vl92n39tuserpagev_user/tocover_final_deferred_immediate_92htop.t.cover_final_deferred_immediate_92' 0 C 'ft/t_assert_ctl_arg.vl92n42tuserpagev_user/tocover_observed_deferred_immediate_92htop.t.cover_observed_deferred_immediate_92' 0 C 'ft/t_assert_ctl_arg.vl92n44tuserpagev_user/tocover_final_deferred_immediate_stmt_92htop.t.cover_final_deferred_immediate_stmt_92' 0 C 'ft/t_assert_ctl_arg.vl92n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_92htop.t.cover_observed_deferred_immediate_stmt_92' 0 C 'ft/t_assert_ctl_arg.vl97n31tuserpagev_user/tocover_simple_immediate_97htop.t.cover_simple_immediate_97' 0 C 'ft/t_assert_ctl_arg.vl97n36tuserpagev_user/tocover_simple_immediate_stmt_97htop.t.cover_simple_immediate_stmt_97' 0 C 'ft/t_assert_ctl_arg.vl97n39tuserpagev_user/tocover_final_deferred_immediate_97htop.t.cover_final_deferred_immediate_97' 0 C 'ft/t_assert_ctl_arg.vl97n42tuserpagev_user/tocover_observed_deferred_immediate_97htop.t.cover_observed_deferred_immediate_97' 0 C 'ft/t_assert_ctl_arg.vl97n44tuserpagev_user/tocover_final_deferred_immediate_stmt_97htop.t.cover_final_deferred_immediate_stmt_97' 0 C 'ft/t_assert_ctl_arg.vl97n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_97htop.t.cover_observed_deferred_immediate_stmt_97' 0 verilator-5.044/test_regress/t/t_assert_disable_iff.v0000644000542200017500000000231415125463617023423 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Peter Monsson. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc; Test test (/*AUTOINST*/ // Inputs .clk (clk)); always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( input clk ); `ifdef FAIL_ASSERT_1 assert property (@(posedge clk) disable iff (0) 0) else $display("wrong disable"); `endif assert property (@(posedge clk) disable iff (1) 0) $stop; else $stop; assert property (@(posedge clk) disable iff (1) 1) $stop; else $stop; assert property (@(posedge clk) disable iff (0) 1); // // Cover properties behave differently // cover property (@(posedge clk) disable iff (1) 1) $stop; cover property (@(posedge clk) disable iff (1) 0) $stop; cover property (@(posedge clk) disable iff (0) 1) $display("*COVER: ok"); cover property (@(posedge clk) disable iff (0) 0) $stop; endmodule verilator-5.044/test_regress/t/t_flag_f__3.v0000644000542200017500000000002315125463617021405 0ustar mahmoudyfreeshell`define GOT_DEF3 1 verilator-5.044/test_regress/t/t_flag_runtime_timeout_bad.py0000755000542200017500000000134615125463617025035 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') # TODO if make this general purpose, consider an e.g. VERILATOR_RUNTIME_FLAGS # envvar so can set for test suites. Make sure runtime-debug prints such options. test.compile(verilator_flags2=['--binary', '--debug-runtime-timeout 1']) test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_fork_repeat.v0000644000542200017500000000122015125463617022107 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; bit clk; // Gen Clock always #10 clk = ~clk; initial begin fork begin forever @(posedge clk); end begin repeat(10) @(posedge clk); end begin for(int i=0; i < 6; ++i) @(posedge clk); end join_any $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_sys_file_basic_mcd.v0000644000542200017500000000767715125463617023435 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; `define STR(__s) `"__s`" task automatic fail(string s); $display({"FAIL! Reason: ", s}); $stop; endtask task automatic test1; int fd[30], fd_fail, fd_success, fd_close, tmp; for (int i = 0; i < 30; i++) begin // Attempt to allocate 30 MCD descriptors; returned descriptors // should fall within correct range: [1, 30]. tmp = $fopen($sformatf("%s/some_file%0d.dat", `STR(`TEST_OBJ_DIR), i)); fd[i] = tmp; if ((fd[i] == 0) || !$onehot(fd[i])) fail($sformatf("MCD descriptor out of range %d", fd[i])); end // Attempt to allocate another MCD descriptor when all should // be used. We expect this operation to fail and return the // invalid descriptor (0). fd_fail = $fopen($sformatf("%s/another_file.dat", `STR(`TEST_OBJ_DIR))); if (fd_fail != 0) fail("Able to allocate MCD descriptor when fully utilized."); // Return descriptor back to pool fd_close = fd[0]; $fclose(fd_close); // Re-attempt MCD allocation; should pass at this point. fd_success = $fopen($sformatf("%s/yet_another_file.dat", `STR(`TEST_OBJ_DIR))); if (fd_success == 0) fail("Expect to have free descriptors at this point."); // Returned descriptor should have a value matching that which // had previously just been returned back to the pool. if (fd_success != fd[0]) fail("Descriptor has incorrect value."); // Return all descriptors back to the pool. for (int i = 1; i < 30; i++) begin fd_close = fd[i]; $fclose(fd_close); end endtask task automatic test2; // Validate basic MCD functionality. integer fd[3], fd_all, tmp; for (int i = 0; i < 3; i++) begin tmp = $fopen($sformatf("%s/t_sys_file_basic_mcd_test2_%0d.dat", `STR(`TEST_OBJ_DIR), i)); fd[i] = tmp; end fd_all = 0; for (int i = 0; i < 3; i++) fd_all |= fd[i]; $fwrite(fd_all, "Scotland is the greatest country.\n"); $fwrite(fd_all, "All other countries are inferior.\n"); $fwrite(fd_all, "Woe betide those to stand against the mighty Scottish nation.\n"); $fclose(fd_all); endtask task automatic test3; int result; // Write some things to standard output. $fwrite(32'h8000_0001, "Sean Connery was the best Bond.\n"); $fwrite(32'h8000_0001); $fstrobe(32'h8000_0001); result = $fseek(32'hffffffff, 0, 0); `checkd(result, -1); result = $ftell(32'hffffffff); `checkd(result, -1); result = $rewind(32'hffffffff); `checkd(result, -1); result = $feof(0); `checkd(result, 1); endtask task automatic test4; int fd; // Wide filename fd = $fopen({`STR(`TEST_OBJ_DIR), "/some_very_large_filename_that_no_one_would_ever_use_", "except_to_purposefully_break_my_beautiful_code.dat"}); if (fd == 0) fail("Long filename could not be opened."); $fclose(fd); endtask task automatic test5; int fd_all; fd_all = $fopen({`STR(`TEST_OBJ_DIR), "/t_sys_file_basic_mcd_test5.dat"}); if (fd_all == 0) fail("could not be opened."); fd_all |= 1; $fdisplay(fd_all, "To file and to stdout"); $fclose(fd_all); endtask initial begin // Test1: Validate file descriptor region. test1; // Test2: Validate basic MCD functionality. test2; // Test3: Validate explicit descriptor ID test3; // Test4: Validate filename lengths test4; // Test5: OR with stdout test5; $write("*-* All Finished *-*\n"); $finish(0); // Test arguments to finish end // initial begin `undef STR endmodule // t verilator-5.044/test_regress/t/t_preproc_kwd.v0000644000542200017500000000306615125463617022137 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; v95 v95 (); v01nc v01nc (); v01c v01c (); v05 v05 (); s05 s05 (); s09 s09 (); s12 s12 (); s17 s17 (); s23 s23 (); a23 a23 (); initial begin $finish; end endmodule `begin_keywords "1364-1995" module v95; integer signed; initial signed = 1; endmodule `end_keywords `begin_keywords "1364-2001-noconfig" module v01nc; localparam g = 0; integer instance; initial instance = 1; endmodule `end_keywords `begin_keywords "1364-2001" module v01c; localparam g = 0; integer bit; initial bit = 1; endmodule `end_keywords `begin_keywords "1364-2005" module v05; uwire w; integer final; initial final = 1; endmodule `end_keywords `begin_keywords "1800-2005" module s05; bit b; integer global; initial global = 1; endmodule `end_keywords `begin_keywords "1800-2009" module s09; bit b; integer soft; initial soft = 1; endmodule `end_keywords `begin_keywords "1800-2012" module s12; final begin $write("*-* All Finished *-*\n"); end endmodule `end_keywords `begin_keywords "1800-2017" module s17; final begin $write("*-* All Finished *-*\n"); end endmodule `end_keywords `begin_keywords "1800-2023" module s23; final begin $write("*-* All Finished *-*\n"); end endmodule `end_keywords `begin_keywords "VAMS-2.3" module a23; real foo; initial foo = sqrt(2.0); endmodule `end_keywords verilator-5.044/test_regress/t/t_interface_virtual_controlflow.v0000644000542200017500000000345415125463617025757 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 interface Bus1; logic [15:0] data; endinterface interface Bus2; logic [15:0] data; endinterface interface Bus3; logic [15:0] data; endinterface module t_controlflow; logic clk = 0; integer cyc = 0; Bus1 intf1(); Bus2 intf2(); Bus3 intf3(), intf4(); virtual Bus1 vif1 = intf1; virtual Bus2 vif2 = intf2; virtual Bus3 vif3 = intf3, vif4 = intf4; // Finish on negedge so that $finish is last always @(negedge clk) begin if (cyc >= 10) begin $write("*-* All Finished *-*\n"); $finish; end end function void assign_to_intf3(); intf3.data = 'hcafe; endfunction always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 1 || cyc == 3 || cyc == 5) intf1.data = 'hdead; else vif2.data = 'hbeef; if (cyc == 1 || cyc == 3 || cyc == 5) begin if (cyc < 3) intf3.data = 'hfafa; intf4.data = 'hface; end if (cyc == 7) begin intf4.data = 'hcafe; end if (cyc == 9) begin assign_to_intf3; intf4.data = 'hdeaf; end end always @(vif1.data) begin $write("[%0t] vif1.data==%h\n", $time, vif1.data); end always @(intf2.data) begin $write("[%0t] intf2.data==%h\n", $time, intf2.data); end always @(vif3.data) begin $write("[%0t] vif3.data==%h\n", $time, vif3.data); end always @(intf4.data) begin $write("[%0t] intf4.data==%h\n", $time, intf4.data); end initial begin repeat (20) #5ns clk = ~clk; end endmodule verilator-5.044/test_regress/t/t_flag_output_groups.v0000644000542200017500000000164615125463617023552 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 virtual class Base; pure virtual function int get_param; endclass class Foo#(int N = 17) extends Base; function int get_param; return N; endfunction endclass module t (/*AUTOARG*/ // Inputs clk ); input clk; localparam MAX = 128; Base q[$]; generate // should result in many C++ files genvar i; for (i = 0; i < MAX; i++) initial begin Foo#(i) item = new; q.push_back(item); end endgenerate always @(posedge clk) begin static int sum = 0; foreach (q[i]) sum += q[i].get_param(); if (sum != MAX * (MAX - 1) / 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_tri_array.py0000755000542200017500000000106015125463617021772 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) if not test.vlt_all: test.execute() test.passes() verilator-5.044/test_regress/t/t_implements_noninterface_bad.out0000644000542200017500000000103315125463617025670 0ustar mahmoudyfreeshell%Error: t/t_implements_noninterface_bad.v:10:26: Attempting to implement from non-interface class 'NotIcls' ... Suggest use 'extends' 10 | class ClsBad1 implements NotIcls; | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_implements_noninterface_bad.v:16:23: Attempting to extend from interface class 'Icls' ... Suggest use 'implements' 16 | class ClsBad2 extends Icls; | ^~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_assigndly_dynamic_notiming_bad.out0000644000542200017500000000060215125463617026366 0ustar mahmoudyfreeshell%Error-NOTIMING: t/t_assigndly_dynamic_notiming_bad.v:10:11: Delayed assignment in a non-inlined function/task requires --timing : ... note: In instance '$unit::Cls' 10 | qux <= '1; | ^~ ... For error description see https://verilator.org/warn/NOTIMING?v=latest %Error: Exiting due to verilator-5.044/test_regress/t/t_lint_pragma_protected_bad.py0000755000542200017500000000102715125463617025155 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, verilator_flags2=['-Wpedantic'], expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_randomize_this.v0000644000542200017500000000163715125463617022641 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Member; rand int m_val; endclass class Cls; rand int m_val; rand Member m_member; function void test; automatic int rand_result; logic ok1 = 0, ok2 = 0; m_val = 256; m_member.m_val = 65535; for (int i = 0; i < 20; i++) begin rand_result = randomize(); if (rand_result != 1) $stop; if (m_val != 256) ok1 = 1; if (m_member.m_val != 65535) ok2 = 1; end if (!ok1) $stop; if (!ok2) $stop; endfunction function new; m_member = new; endfunction endclass module t; initial begin Cls c; c = new; c.test; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_sys_writemem_b.gold5.mem0000644000542200017500000000162015125463617024164 0ustar mahmoudyfreeshell00000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000 11011100101110101001100001110110010101000000000000000100 00000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000 11011100101110101001100001110110010101000000000000001010 11011100101110101001100001110110010101000000000000001011 11011100101110101001100001110110010101000000000000001100 00000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000 verilator-5.044/test_regress/t/t_assign_slice_overflow.py0000755000542200017500000000073415125463617024373 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_disable_bad.v0000644000542200017500000000042115125463617022021 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; initial begin disable abcd; end endmodule : t verilator-5.044/test_regress/t/t_threads_crazy.v0000644000542200017500000000077015125463617022461 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc!=0) begin if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.044/test_regress/t/t_uniqueif_else.py0000755000542200017500000000077415125463617022646 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.044/test_regress/t/t_covergroup_in_class_duplicate_bad.py0000755000542200017500000000077115125463617026714 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_mod_mod.out0000644000542200017500000000142115125463617021571 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_mod_mod.v:10:3: Unsupported: module decls within module decls 10 | program p_in_m(); | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_mod_mod.v:12:3: Unsupported: program decls within module decls 12 | interface i_in_m(); | ^~~~~~~~~ %Error-UNSUPPORTED: t/t_mod_mod.v:14:1: Unsupported: interface decls within module decls 14 | endmodule | ^~~~~~~~~ %Error-UNSUPPORTED: t/t_mod_mod.v:19:3: Unsupported: interface decls within interface decls 19 | program p_in_i(); | ^~~~~~~ %Error-UNSUPPORTED: t/t_mod_mod.v:21:1: Unsupported: program decls within interface decls 21 | endinterface | ^~~~~~~~~~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_lint_latch_casei_bad.v0000644000542200017500000000061415125463617023707 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for Issue#1609 // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input a, output reg o ); always_comb begin // verilator lint_off CASEINCOMPLETE case (a) 1'b0: o = 1; endcase end endmodule verilator-5.044/test_regress/t/t_assert_ctl_type_bad.py0000755000542200017500000000102515125463617024011 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--assert'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_typedef_iface_typedef.py0000755000542200017500000000077115125463617024315 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_func_impure_bad.out0000644000542200017500000000130115125463617023272 0ustar mahmoudyfreeshell%Error-IMPURE: t/t_func_impure_bad.v:11:9: Unsupported: External variable referenced by non-inlined function/task: 't.foo' 11 | task foo; | ^~~ t/t_func_impure_bad.v:13:7: ... Location of the external reference: 't.sig' 13 | sig = '1; | ^~~ ... For error description see https://verilator.org/warn/IMPURE?v=latest %Error-IMPURE: t/t_func_impure_bad.v:20:9: Unsupported: External variable referenced by non-inlined function/task: 't.baz' 20 | task baz; | ^~~ t/t_func_impure_bad.v:17:7: ... Location of the external reference: 't.sig' 17 | sig = '1; | ^~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_lint_width_bad.py0000755000542200017500000000076315125463617022762 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_module_input_default_value_1_bad.v0000644000542200017500000000221115125463617026241 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Andrew Ranck // SPDX-License-Identifier: CC0-1.0 // Test for Issue#5358: Support default value on module input. // This test *is* expected to not compile, and must match .out file. module dut_should_fail_compile1 ( input logic i = 1'b1, output logic o ); assign i = 1'b0; // bad, should fail post link in V3Width assign o = i; endmodule module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc = 0; // 1800-2009, a few flavors to test: // We should have some DUT instances that fail to compile, // if you tried having a default value on port output. logic dut_should_fail_o; dut_should_fail_compile1 u_dut_should_fail_compile1 (.i(1'b0), .o(dut_should_fail_o) ); always @(posedge clk) begin : main cyc <= cyc + 1; if (cyc == 10) begin // done checking various DUTs and finish $display("%t %m: cyc=%0d", $time, cyc); $write("*-* All Finished *-*\n"); $finish(); end end endmodule : t verilator-5.044/test_regress/t/t_clocking_concat.v0000644000542200017500000000163215125463617022735 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; logic[3:0] D1, D2, Q1, Q2; always @(posedge clk) begin {Q1, Q2} <= {D1, D2}; end always @(posedge clk) $display("[%0t] posedge clk", $time); clocking cb @(posedge clk); input #0 Q = {Q1, Q2}; output #0 D = {D1, D2}; endclocking initial $monitor("[%0t] --> D=%x\t\tQ=%x\t\tcb.Q=%x", $time, {D1,D2}, {Q1,Q2}, cb.Q); int cyc = 0; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc > 1 && cb.Q != {D1 - 4'd1, D2 - 4'd1}) $stop; cb.D <= {D1 + 4'd1, D2 + 4'd1}; if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.044/test_regress/t/t_leak.cpp0000644000542200017500000000513415125463617021047 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test driver/expect definition // // Copyright 2003-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 #include #include #include #include VM_PREFIX_INCLUDE unsigned int main_time = 0; double sc_time_stamp() { return main_time; } long long get_memory_usage() { // Return memory usage. Return 0 if the system doesn't look quite right. #if 0 // BSD only. struct rusage usage; getrusage(RUSAGE_SELF, &usage); return usage.ru_ixrss + usage.ru_idrss + usage.ru_isrss; #endif FILE* fp = fopen("/proc/self/stat", "r"); if (!fp) return 0; int ps_ign; uint64_t ps_vsize, ps_rss; int items = fscanf(fp, ("%d (%*[^) ]) %*1s %d %*d %*d %*d %*d %u" " %u %u %u %u %d %d %d %d" " %*d %*d %*u %*u %d %" PRIu64 " %" PRIu64 " "), &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_vsize, &ps_rss); fclose(fp); if (items >= 14) { return ps_vsize; } else { return 0; } } void make_and_destroy() { VerilatedContext* contextp = new VerilatedContext; contextp->debug(0); VM_PREFIX* topp = new VM_PREFIX{contextp}; topp->eval(); topp->clk = true; while (!contextp->gotFinish()) { contextp->timeInc(5); topp->clk = !topp->clk; topp->eval(); } VL_DO_DANGLING(delete topp, topp); VL_DO_DANGLING(delete contextp, contextp); } int main(int argc, char* argv[]) { uint64_t firstUsage = get_memory_usage(); // Warmup phase for (int i = 0; i < 10; i++) { // make_and_destroy(); } firstUsage = get_memory_usage(); printf("Memory size %" PRId64 " bytes\n", firstUsage); int loops = 10; for (int left = loops; left > 0;) { for (int j = 0; j < 1; ++j, --left) { // make_and_destroy(); } } uint64_t leaked = get_memory_usage() - firstUsage; if (leaked > 64 * 1024) { // Have to allow some slop for this code. printf("Leaked %" PRId64 " bytes, or ~ %" PRId64 " bytes/construt\n", // leaked, leaked / loops); vl_fatal(__FILE__, __LINE__, "top", "Leaked memory\n"); } printf("*-* All Finished *-*\n"); } verilator-5.044/test_regress/t/t_time_passed.v0000644000542200017500000000240015125463617022104 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `timescale 1ns / 1ps module t ( /*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; time in; // verilator lint_off REALCVT initial in = 5432109876.543210ns; // Will round to time units // verilator lint_on REALCVT // This shows time changes when passed between modules with different units // See also discussion in uvm_tlm2_time.svh ps ps (.*); ns ns (.*); always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 60) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule `timescale 1ps / 1ps module ps ( input clk, input integer cyc, input time in ); always @(posedge clk) begin if (cyc == 10) begin $timeformat(-9, 6, "ns", 16); $write("%m: Input time %t %d\n", in, in); end end endmodule `timescale 1ns / 1ps module ns ( input clk, input integer cyc, input time in ); always @(posedge clk) begin if (cyc == 20) begin $timeformat(-9, 6, "ns", 16); $write("%m: Input time %t %d\n", in, in); end end endmodule verilator-5.044/test_regress/t/t_math_shiftrs.py0000755000542200017500000000073415125463617022500 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_struct_nest_uarray.py0000755000542200017500000000073415125463617023745 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_select_bad_range3.out0000644000542200017500000000076115125463617023505 0ustar mahmoudyfreeshell%Warning-SELRANGE: t/t_select_bad_range3.v:19:33: Selection index out of range: 13 outside 12:10 : ... note: In instance 't' 19 | assign outwires[12] = inwires[13]; | ^ ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.044/test_regress/t/t_randomize_inline_var_ctl_bad.py0000755000542200017500000000077615125463617025661 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_unroll_genf.v0000644000542200017500000000110215125463617022117 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //bug830 module sub(); endmodule function integer cdiv(input integer x); begin cdiv = 10; end endfunction module t; genvar j; generate for (j = 0; j < cdiv(10); j=j+1) sub #() sub (); // #() for code coverage in verilog.y endgenerate initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_flag_language.v0000644000542200017500000000057415125463617022375 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // See also t_preproc_kwd.v integer bit; initial bit = 1; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_dynarray_param.v0000644000542200017500000000303215125463617022622 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Noam Gallmann. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t; localparam int SIZES [3:0] = '{1,2,3,4}; typedef int calc_sums_t [3:0]; localparam int SUMS_ARRAY [3:0] = calc_sums_array(SIZES, 4); function automatic calc_sums_t calc_sums_array(int s[3:0], int n); int sum = 0; for (int ii = 0; ii < n; ++ii) begin sum = sum + s[ii]; calc_sums_array[ii] = sum; end endfunction `ifndef VERILATOR localparam int SUMS_DYN [3:0] = calc_sums_dyn(SIZES, 4); `endif function automatic calc_sums_t calc_sums_dyn(int s[], int n); int sum = 0; for (int ii = 0; ii < n; ++ii) begin sum = sum + s[ii]; calc_sums_dyn[ii] = sum; end endfunction initial begin `checkh(SIZES[0], 4); `checkh(SIZES[1], 3); `checkh(SIZES[2], 2); `checkh(SIZES[3], 1); `checkh(SUMS_ARRAY[0], 4); `checkh(SUMS_ARRAY[1], 7); `checkh(SUMS_ARRAY[2], 9); `checkh(SUMS_ARRAY[3], 10); `ifndef VERILATOR `checkh(SUMS_DYN[0], 1); `checkh(SUMS_DYN[1], 3); `checkh(SUMS_DYN[2], 6); `checkh(SUMS_DYN[3], 10); `endif $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_vams_kwd_bad.v0000644000542200017500000000254515125463617022242 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Driss Hafdi. // SPDX-License-Identifier: CC0-1.0 `begin_keywords "VAMS-2.3" module t; // Just get errors on bad keywords (for code coverage) int above; int abs; int absdelay; int abstol; int ac_stim; int access; int acos; int acosh; int aliasparam; int analog; int analysis; int assert; int branch; int connect; int connectmodule; int connectrules; int continuous; int cross; int ddt; int ddt_nature; int ddx; int discipline; int discrete; int domain; int driver_update; int endconnectrules; int enddiscipline; int endnature; int endparamset; int exclude; int final_step; int flicker_noise; int flow; int from; int ground; int idt; int idt_nature; int idtmod; int inf; int initial_step; int laplace_nd; int laplace_np; int laplace_zd; int laplace_zp; int last_crossing; int limexp; int max; int merged; int min; int nature; int net_resolution; int noise_table; int paramset; int potential; int resolveto; int slew; int split; int timer; int transition; int units; int white_noise; int zi_nd; int zi_np; int zi_zd; int zi_zp; endmodule verilator-5.044/test_regress/t/t_flag_main_top_name.v0000644000542200017500000000126315125463617023414 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2023 by Don Williamson and Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module top; string scope; initial begin scope = $sformatf("%m"); $write("[%0t] In %s\n", $time, scope); `ifdef MAIN_TOP_NAME_EMPTY if (scope != "top") $stop; `else if (scope != "ALTOP.top") $stop; `endif $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_const_op_red_scope.py0000755000542200017500000000073415125463617023654 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_class_defaultparam_import.py0000755000542200017500000000070615125463617025230 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.044/test_regress/t/t_lint_always_comb_bad.out0000644000542200017500000000260315125463617024312 0ustar mahmoudyfreeshell%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:29:9: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'temp1' : ... note: In instance 't' 29 | temp1 = 'h0; | ^~~~~ ... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest %Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:31:9: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'temp1' : ... note: In instance 't' 31 | temp1 = (temp1_d1r - 'h1); | ^~~~~ %Warning-ALWCOMBORDER: t/t_lint_always_comb_bad.v:32:7: Always_comb variable driven after use: 'mid' : ... note: In instance 't' 32 | mid = (temp1_d1r == 'h0); | ^~~ ... For warning description see https://verilator.org/warn/ALWCOMBORDER?v=latest ... Use "/* verilator lint_off ALWCOMBORDER */" and lint_on around source to disable this message. %Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:46:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'temp1_d1r' : ... note: In instance 't' 46 | temp1_d1r <= temp1; | ^~~~~~~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_timing_zerodly_unsup.py0000755000542200017500000000106615125463617024275 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--exe --main --timing"]) test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_opt_merge_cond_no_motion.py0000755000542200017500000000164515125463617025054 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_opt_merge_cond.v" test.compile(verilator_flags2=["-unroll-count 64", "--stats", "-fno-merge-cond-motion"]) test.execute() if test.vlt: # Note, with vltmt this might be split differently, so only checking vlt test.file_grep(test.stats, r'Optimizations, MergeCond merges\s+(\d+)', 10) test.file_grep(test.stats, r'Optimizations, MergeCond merged items\s+(\d+)', 580) test.file_grep(test.stats, r'Optimizations, MergeCond longest merge\s+(\d+)', 64) test.passes() verilator-5.044/test_regress/t/t_covergroup_in_class_colliding.v0000644000542200017500000000116415125463617025707 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ class myClass; covergroup embeddedCg; endgroup function new(); real r; embeddedCg = new(); embeddedCg.sample(); r = embeddedCg.get_coverage(); endfunction endclass class secondClass; covergroup embeddedCg; endgroup function new(); real r; embeddedCg = new(); embeddedCg.sample(); r = embeddedCg.get_coverage(); endfunction endclass verilator-5.044/test_regress/t/t_gen_class.v0000644000542200017500000000371515125463617021557 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on module Child; int ch_value; endmodule module Parent; for (genvar i = 0; i < 10; i++) begin : gen_child Child child(); end endmodule module t; Parent parent(); virtual class ChildAgentBase; pure virtual task preload(int value); pure virtual function string name(); endclass ChildAgentBase child_agents[10]; for (genvar i = 0; i < 10; i++) begin : gfor class ChildAgent extends ChildAgentBase; task automatic preload(int value); parent.gen_child[i].child.ch_value = value; endtask function string name(); return $sformatf("%m"); endfunction endclass ChildAgent agent = new(); initial child_agents[i] = agent; end task automatic preload_children; for (int i = 0; i < 10; i++) begin child_agents[i].preload(i); end endtask string s; initial begin #1; // Ensure all class instances are initialized preload_children(); `checkh(parent.gen_child[3].child.ch_value, 3); `checkh(parent.gen_child[8].child.ch_value, 8); `ifdef VERILATOR // Some legal examples "t.gfor[4].\ChildAgent::name", "t.gfor[4].ChildAgent.name" `checks(child_agents[4].name(), "t.gfor[4].ChildAgent.name"); `endif $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_lib_prot_clk_gated.py0000755000542200017500000000367515125463617023623 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt', 'xsim') test.top_filename = "t/t_lib_prot.v" if test.benchmark: test.sim_time = test.benchmark * 100 trace_opt = "" secret_prefix = "secret" secret_dir = test.obj_dir + "/" + secret_prefix test.mkdir_ok(secret_dir) # Always compile the secret file with Verilator no matter what simulator # we are testing with test.run( logfile=secret_dir + "/vlt_compile.log", cmd=["perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", '--no-timing', trace_opt, "--prefix", "Vt_lib_prot_secret", "-cc", "-Mdir", secret_dir, "-GGATED_CLK=1", "--protect-lib", secret_prefix, "--protect-key", "secret-key", "t/t_lib_prot_secret.v"], verilator_run=True) # yapf:disable test.run(logfile=secret_dir + "/secret_gcc.log", cmd=[os.environ["MAKE"], "-C", secret_dir, "-f", "Vt_lib_prot_secret.mk"]) test.compile(verilator_flags2=['--no-timing', trace_opt, "-GGATED_CLK=1", "-LDFLAGS", secret_prefix + "/libsecret.a", secret_dir + "/secret.sv"], xsim_flags2=[secret_dir + "/secret.sv"]) # yapf:disable test.execute(xsim_run_flags2=["--sv_lib", secret_dir + "/libsecret", "--dpi_absolute"]) if test.vlt and test.trace: # We can see the ports of the secret module test.file_grep(test.trace_filename, r'accum_in') # but we can't see what's inside test.file_grep_not(test.trace_filename, r'secret_') test.passes() verilator-5.044/test_regress/t/t_timing_finish2.py0000755000542200017500000000077115125463617022717 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.044/test_regress/t/t_concat_string.v0000644000542200017500000000167115125463617022455 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 typedef enum {efgh} en; module t; initial begin en e; string s; s = {"a", "b"}; if (s != "ab") $stop; e = efgh; s = {"abcd", e.name(), "ijkl"}; if (s != "abcdefghijkl") $stop; // hang V3Width if complexity grows exponential (2**52 should suffice) s = {"a", "b", "c", "d", "e", "f", "g", "h", "i", "j", "k", "l", "m", "n", "o", "p", "q", "r", "s", "t", "u", "v", "w", "x", "y", "z", "a", "b", "c", "d", "e", "f", "g", "h", "i", "j", "k", "l", "m", "n", "o", "p", "q", "r", "s", "t", "u", "v", "w", "x", "y", "z"}; if (s != "abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz") $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_clocked_release_combo.py0000755000542200017500000000073415125463617024270 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_udp_nonsequential_x.py0000755000542200017500000000073215125463617024067 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_json_only_flat_no_inline_mod.out0000644000542200017500000001366415125463617026100 0ustar mahmoudyfreeshell{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"(E)", "modulesp": [ {"type":"MODULE","name":"$root","addr":"(F)","loc":"d,11:8,11:11","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"i_clk","addr":"(G)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"top.i_clk","addr":"(I)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"top.f.i_clk","addr":"(J)","loc":"d,7:24,7:29","dtypep":"(H)","origName":"i_clk","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"TOPSCOPE","name":"","addr":"(E)","loc":"d,11:8,11:11","senTreesp": [], "scopep": [ {"type":"SCOPE","name":"TOP","addr":"(K)","loc":"d,11:8,11:11","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(F)", "varsp": [ {"type":"VARSCOPE","name":"i_clk","addr":"(L)","loc":"d,11:24,11:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(G)"}, {"type":"VARSCOPE","name":"top.i_clk","addr":"(M)","loc":"d,11:24,11:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(I)"}, {"type":"ALWAYS","name":"","addr":"(N)","loc":"d,11:24,11:29","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(O)","loc":"d,11:24,11:29","dtypep":"(H)", "rhsp": [ {"type":"VARREF","name":"i_clk","addr":"(P)","loc":"d,11:24,11:29","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(L)","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"top.i_clk","addr":"(Q)","loc":"d,11:24,11:29","dtypep":"(H)","access":"WR","varp":"(I)","varScopep":"(M)","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"VARSCOPE","name":"top.f.i_clk","addr":"(R)","loc":"d,7:24,7:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(J)"}, {"type":"ALWAYS","name":"","addr":"(S)","loc":"d,7:24,7:29","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(T)","loc":"d,7:24,7:29","dtypep":"(H)", "rhsp": [ {"type":"VARREF","name":"i_clk","addr":"(U)","loc":"d,7:24,7:29","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(L)","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"top.f.i_clk","addr":"(V)","loc":"d,7:24,7:29","dtypep":"(H)","access":"WR","varp":"(J)","varScopep":"(R)","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]} ],"blocksp": [],"inlinesp": []} ]} ]} ],"filesp": [], "miscsp": [ {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"UNLINKED", "typesp": [ {"type":"BASICDTYPE","name":"logic","addr":"(H)","loc":"d,11:18,11:23","dtypep":"(H)","keyword":"logic","generic":true,"rangep": []} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ {"type":"MODULE","name":"@CONST-POOL@","addr":"(W)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(X)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(W)","varsp": [],"blocksp": [],"inlinesp": []} ]} ]} ]} verilator-5.044/test_regress/t/t_interface_and_struct_pattern.py0000755000542200017500000000073415125463617025730 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_trace_ascendingrange.py0000755000542200017500000000161415125463617024131 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') # CI environment offers 2 VCPUs, 2 thread setting causes the following warning. # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. # Strangely, asking for more threads makes it go away. test.compile(verilator_flags2=['--cc --trace-vcd --trace-params -Wno-ASCRANGE'], threads=(6 if test.vltmt else 1)) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_lint_pindup_bad.v0000644000542200017500000000115715125463617022752 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( output wire o, input wire i, input wire i2 ); sub #(.NEXIST(1), // Not found .P(2), .P(3)) // Dup sub (.o(o), .i(i), .i(i2), // Dup .nexist(i2) // Not found ); endmodule module sub #(parameter P=1, parameter EXIST=9) ( output wire o, input wire i, input wire exists ); assign o = ~i; endmodule verilator-5.044/test_regress/t/t_inst_tree_inl1_pub0.py0000755000542200017500000000235515125463617023653 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_inst_tree.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(v_flags2=[ "--no-json-edit-nums", "-fno-dfg-post-inline", "-fno-dfg-scoped", test.t_dir + "/t_inst_tree_inl1_pub0.vlt" ]) if test.vlt_all: test.file_grep( out_filename, r'{"type":"VAR","name":"t.u.u0.u0.z1",.*"loc":"\w,70:[^"]*",.*"origName":"z1",.*"dtypeName":"logic"' ) test.file_grep( out_filename, r'{"type":"VAR","name":"t.u.u0.u1.z1",.*"loc":"\w,70:[^"]*",.*"origName":"z1",.*"dtypeName":"logic"' ) test.file_grep( out_filename, r'{"type":"VAR","name":"t.u.u1.u0.z0",.*"loc":"\w,70:[^"]*",.*"origName":"z0",.*"dtypeName":"logic"' ) test.execute() test.file_grep(test.run_log_filename, r"\] (%m|.*t\.ps): Clocked") test.passes() verilator-5.044/test_regress/t/t_randomize_member_select.py0000755000542200017500000000104615125463617024660 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_implements_missing_bad.out0000644000542200017500000000074215125463617024674 0ustar mahmoudyfreeshell%Error: t/t_implements_missing_bad.v:12:1: Class 'Cls' implements 'Icls1' but is missing implementation for 'icf2' (IEEE 1800-2023 8.26) 12 | class Cls implements Icls1; | ^~~~~ t/t_implements_missing_bad.v:9:30: ... Location of interface class's function 9 | pure virtual function int icf2; | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_struct_packed_sysfunct.v0000644000542200017500000000312215125463617024402 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // packed structures struct packed { logic e0; logic [1:0] e1; logic [3:0] e2; logic [7:0] e3; } struct_dsc; // descendng range structure /* verilator lint_off ASCRANGE */ struct packed { logic e0; logic [0:1] e1; logic [0:3] e2; logic [0:7] e3; } struct_asc; // ascending range structure /* verilator lint_on ASCRANGE */ integer cnt = 0; // event counter always @ (posedge clk) begin cnt <= cnt + 1; end // finish report always @ (posedge clk) if (cnt==2) begin $write("*-* All Finished *-*\n"); $finish; end always @ (posedge clk) if (cnt==1) begin // descending range if ($bits (struct_dsc ) != 15) $stop; if ($bits (struct_dsc.e0) != 1) $stop; if ($bits (struct_dsc.e1) != 2) $stop; if ($bits (struct_dsc.e2) != 4) $stop; if ($bits (struct_dsc.e3) != 8) $stop; if ($increment (struct_dsc, 1) != 1) $stop; // ascending range if ($bits (struct_asc ) != 15) $stop; if ($bits (struct_asc.e0) != 1) $stop; if ($bits (struct_asc.e1) != 2) $stop; if ($bits (struct_asc.e2) != 4) $stop; if ($bits (struct_asc.e3) != 8) $stop; if ($increment (struct_asc, 1) != 1) $stop; // Structure itself always big numbered end endmodule verilator-5.044/test_regress/t/t_interface_generic_modport2.py0000755000542200017500000000101315125463617025256 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(timing_loop=True, verilator_flags2=['--timing']) test.execute() test.passes() verilator-5.044/test_regress/t/t_wait_order.py0000755000542200017500000000107515125463617022143 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(expect_filename=test.golden_filename, verilator_flags2=['--binary'], fails=test.vlt_all) test.passes() verilator-5.044/test_regress/t/t_class_field_name.v0000644000542200017500000000066615125463617023073 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Cls; int queue; endclass module t; initial begin Cls cls = new; cls.queue = 1; if (cls.queue == 1) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.044/test_regress/t/t_timescale_lint2.py0000755000542200017500000000103115125463617023052 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_timescale_lint.v" test.lint(verilator_flags2=["--timescale 1ns/1ns"]) test.passes() verilator-5.044/test_regress/t/t_mailbox_concurrent.v0000644000542200017500000000201515125463617023506 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Liam Braun. // SPDX-License-Identifier: CC0-1.0 module t(); mailbox #(int) m; task automatic test_get; int v; m.get(v); // Only one thread should be here at a time (mailbox empty) $display("mailbox read %0t", $time); #1; m.put(v); endtask task automatic test_put; int v; m.put(42); // Only one thread should be here at a time (mailbox full) $display("mailbox write %0t", $time); #1; m.get(v); endtask initial begin m = new(1); m.put(42); fork test_get(); test_get(); test_get(); join m = new(1); fork test_put(); test_put(); test_put(); join $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_langext_3_bad.out0000644000542200017500000000035015125463617022645 0ustar mahmoudyfreeshell%Error: t/t_langext_3.v:20:4: Can't find typedef/interface: 'uwire' 20 | uwire w; | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_func_outp.v0000644000542200017500000000352415125463617021621 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; reg [7:0] a,b; wire [7:0] z; mytop u0 ( a, b, clk, z ); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; //$write("%d %x\n", cyc, z); if (cyc==1) begin a <= 8'h07; b <= 8'h20; end if (cyc==2) begin a <= 8'h8a; b <= 8'h12; end if (cyc==3) begin if (z !== 8'hdf) $stop; a <= 8'h71; b <= 8'hb2; end if (cyc==4) begin if (z !== 8'hed) $stop; end if (cyc==5) begin if (z !== 8'h4d) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule // mytop module inv( input [ 7:0 ] a, output wire [ 7:0 ] z ); assign z = ~a; endmodule module ftest( input [ 7:0 ] a, b, // Test legal syntax input clk, output reg [ 7:0 ] z ); wire [7:0] zi; inv u1 (.a(myadd(a,b)), .z(zi)); always @ ( posedge clk ) begin z <= myadd( a, zi ); end function [ 7:0 ] myadd; input [7:0] ina; input [7:0] inb; begin myadd = ina + inb; end endfunction // myadd endmodule // ftest module mytop ( input [ 7:0 ] a, b, input clk, output [ 7:0 ] z ); ftest u0( a, b, clk, z ); endmodule // mytop verilator-5.044/test_regress/t/t_opt_merge_cond.py0000755000542200017500000000154015125463617022765 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(verilator_flags2=["-unroll-count 64", "--stats"]) test.execute() if test.vlt: # Note, with vltmt this might be split differently, so only checking vlt test.file_grep(test.stats, r'Optimizations, MergeCond merges\s+(\d+)', 9) test.file_grep(test.stats, r'Optimizations, MergeCond merged items\s+(\d+)', 580) test.file_grep(test.stats, r'Optimizations, MergeCond longest merge\s+(\d+)', 128) test.passes() verilator-5.044/test_regress/t/t_randomize_unpacked_wide.v0000644000542200017500000000144415125463617024470 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Foo; rand bit [65:0] m_wideUnpacked[3]; constraint int_queue_c { m_wideUnpacked[0] == 0; m_wideUnpacked[1] == 1; m_wideUnpacked[2] == 2; } function void self_check(); if (m_wideUnpacked[0] != 0) $stop; if (m_wideUnpacked[1] != 1) $stop; if (m_wideUnpacked[2] != 2) $stop; endfunction endclass module t; int success; initial begin Foo foo = new; success = foo.randomize(); if (success != 1) $stop; foo.self_check(); $display("Unpacked: %p", foo.m_wideUnpacked); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_select_bad_range5.out0000644000542200017500000000375615125463617023516 0ustar mahmoudyfreeshell%Error: t/t_select_bad_range5.v:16:19: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' : ... note: In instance 't' 16 | assign mi = unk[3:2]; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Warning-SELRANGE: t/t_select_bad_range5.v:16:19: Extracting 2 bits from only 1 bit number : ... note: In instance 't' 16 | assign mi = unk[3:2]; | ^ ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Warning-SELRANGE: t/t_select_bad_range5.v:16:19: Selection index out of range: 3:2 outside 1:0 : ... note: In instance 't' 16 | assign mi = unk[3:2]; | ^ %Warning-WIDTHEXPAND: t/t_select_bad_range5.v:16:19: Bit extraction of var[3:0] requires 2 bit index, not 1 bits. : ... note: In instance 't' 16 | assign mi = unk[3:2]; | ^ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. %Warning-WIDTHTRUNC: t/t_select_bad_range5.v:16:14: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's SEL generates 2 bits. : ... note: In instance 't' 16 | assign mi = unk[3:2]; | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.044/test_regress/t/t_debug_graph_test.py0000755000542200017500000000125415125463617023311 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') if 'VERILATOR_TEST_NO_GDB' in os.environ: test.skip("Skipping due to VERILATOR_TEST_NO_GDB") test.lint( # Check we can call dump() on graph, and other things v_flags=["--lint-only --debug --debugi-V3GraphTest 9 --debug-self-test"]) test.passes() verilator-5.044/test_regress/t/t_math_repl_bad.v0000644000542200017500000000062415125463617022376 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; logic [31:0] o; initial begin o = {0 {1'b1}}; // Bad 0 rep o = {$test$plusargs("NON-CONSTANT") {1'b1}}; // Bad non-constant rep $stop; end endmodule verilator-5.044/test_regress/t/t_timing_fork_nba.py0000755000542200017500000000075715125463617023142 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--exe --timing"]) test.passes() verilator-5.044/test_regress/t/t_struct_unpacked.py0000755000542200017500000000073415125463617023203 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_display_cwide_bad.py0000755000542200017500000000076315125463617023435 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_debug_width.py0000755000542200017500000000107515125463617022271 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_opt_const.v" test.lint(verilator_flags2=["--debug-width"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_implements_nested_bad.v0000644000542200017500000000054415125463617024143 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; interface class inte; interface class bad_cannot_nest; endclass endclass endclass module t; Cls c; endmodule verilator-5.044/test_regress/t/t_alias_tristate_unsup.out0000644000542200017500000000053615125463617024423 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_alias_tristate_unsup.v:17:9: Unsupported: Tristate variable referenced in alias: 'a' : ... note: In instance 't' 17 | alias a = b; | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.044/test_regress/t/t_tri_struct_packed.py0000755000542200017500000000106115125463617023510 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary']) test.execute(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_initial_dlyass_bad.out0000644000542200017500000000133515125463617023775 0ustar mahmoudyfreeshell%Warning-INITIALDLY: t/t_initial_dlyass.v:18:9: Non-blocking assignment '<=' in initial/final block : ... This will be executed as a blocking assignment '='! 18 | a <= 22; | ^~ ... For warning description see https://verilator.org/warn/INITIALDLY?v=latest ... Use "/* verilator lint_off INITIALDLY */" and lint_on around source to disable this message. %Warning-INITIALDLY: t/t_initial_dlyass.v:19:9: Non-blocking assignment '<=' in initial/final block : ... This will be executed as a blocking assignment '='! 19 | b <= 33; | ^~ %Error: Exiting due to verilator-5.044/test_regress/t/t_constraint_pure_nonabs_bad.v0000644000542200017500000000050515125463617025200 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class NonAsbstract; pure constraint raintBad; // Bad: Not in abstract class endclass module t; endmodule verilator-5.044/test_regress/t/t_dpi_type_bad.py0000755000542200017500000000077615125463617022436 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_udp_bad_comb_trigger.v0000755000542200017500000000103515125463617023736 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 primitive t_gate(dout, a, b, c); output dout; input a, b, c; table x 0 1 : 1; 0 ? 1 : 1; (01) 1 0 : 0; 1 1 ? : 1; 1 0 0 : 0; 0 0 0 : 1; endtable endprimitive module top (o, a, b, c); output o; input a, b, c; t_gate(o, a, b, c); endmodule verilator-5.044/test_regress/t/t_udp_bad_first_input.v0000755000542200017500000000103215125463617023636 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 primitive t_gate(a, b, c, dout); input a, b, c; output dout; table x 0 1 : 1; 0 ? 1 : 1; 0 1 0 : 0; 1 1 ? : 1; 1 0 0 : 0; 0 0 0 : 1; endtable endprimitive module top (a, b, c, o); input a, b, c; output o; t_gate(a, b, c, o); endmodule verilator-5.044/test_regress/t/t_opt_dead_noassigns.v0000644000542200017500000000102315125463617023452 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs in ); input int in; int ass_keptdead; initial begin if (in != 0) begin ass_keptdead = 1 | in; $display("Avoid gate removing"); ass_keptdead = 2 | in; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_gen_for0.py0000755000542200017500000000073415125463617021504 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_sys_fread.v0000644000542200017500000000671115125463617021577 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define STRINGIFY(x) `"x`" `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on //====================================================================== module t; integer file; integer r_i; byte r_upb[20:10]; byte r_dnb[10:20]; reg [13:0] r_ups[20:10]; reg [13:0] r_dns[10:20]; reg [30:0] r_upi[20:10]; reg [30:0] r_dni[10:20]; reg [61:0] r_upq[20:10]; reg [61:0] r_dnq[10:20]; reg [71:0] r_upw[20:10]; reg [71:0] r_dnw[10:20]; task clear; // Initialize memories to zero, // avoid differences between 2-state and 4-state. r_i = ~0; foreach (r_upb[i]) r_upb[i] = ~0; foreach (r_dnb[i]) r_dnb[i] = ~0; foreach (r_ups[i]) r_ups[i] = ~0; foreach (r_dns[i]) r_dns[i] = ~0; foreach (r_upi[i]) r_upi[i] = ~0; foreach (r_dni[i]) r_dni[i] = ~0; foreach (r_upq[i]) r_upq[i] = ~0; foreach (r_dnq[i]) r_dnq[i] = ~0; foreach (r_upw[i]) r_upw[i] = ~0; foreach (r_dnw[i]) r_dnw[i] = ~0; // Open file $fclose(file); file = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/t_sys_fread.mem"}, "r"); if ($feof(file)) $stop; endtask task dump; // verilog_format: off $write("Dump:"); $write("\n r_i:"); $write(" %x",r_i); $write("\n r_upb:"); foreach (r_upb[i]) $write(" %x", r_upb[i]); $write("\n r_dnb:"); foreach (r_dnb[i]) $write(" %x", r_dnb[i]); $write("\n r_ups:"); foreach (r_ups[i]) $write(" %x", r_ups[i]); $write("\n r_dns:"); foreach (r_dns[i]) $write(" %x", r_dns[i]); $write("\n r_upi:"); foreach (r_upi[i]) $write(" %x", r_upi[i]); $write("\n r_dni:"); foreach (r_dni[i]) $write(" %x", r_dni[i]); $write("\n r_upq:"); foreach (r_upq[i]) $write(" %x", r_upq[i]); $write("\n r_dnq:"); foreach (r_dnq[i]) $write(" %x", r_dnq[i]); $write("\n r_upw:"); foreach (r_upw[i]) $write(" %x", r_upw[i]); $write("\n r_dnw:"); foreach (r_dnw[i]) $write(" %x", r_dnw[i]); $write("\n\n"); // verilog_format: on endtask integer code; initial begin // verilog_format: off clear; code = $fread(r_i, file); `checkd(code, 4); code = $fread(r_upb, file); `checkd(code, 11); code = $fread(r_dnb, file); `checkd(code, 11); code = $fread(r_ups, file); `checkd(code, 22); code = $fread(r_dns, file); `checkd(code, 22); code = $fread(r_upi, file); `checkd(code, 44); code = $fread(r_dni, file); `checkd(code, 44); code = $fread(r_upq, file); `checkd(code, 88); code = $fread(r_dnq, file); `checkd(code, 88); code = $fread(r_upw, file); `checkd(code, 99); code = $fread(r_dnw, file); `checkd(code, 99); dump; clear; code = $fread(r_upb, file, 15); `checkd(code, 6); code = $fread(r_dnb, file, 15); `checkd(code, 6); code = $fread(r_upb, file, , 1); `checkd(code, 1); code = $fread(r_dnb, file, , 1); `checkd(code, 1); code = $fread(r_upb, file, 13, 1); `checkd(code, 1); code = $fread(r_dnb, file, 13, 1); `checkd(code, 1); // verilog_format: on // Bug where fread in if() broke. if ($fread(r_ups, file, 15, 2) != 4) $stop; dump; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_flag_prefix.v0000644000542200017500000000210715125463617022101 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 module t; sub sub(); endmodule module sub; // no_inline_module, so it goes into separate file /* verilator no_inline_module */ // Goes into const pool which is separate file wire logic [255:0] C = {32'h1111_1111, 32'h2222_2222, 32'h3333_3333, 32'h4444_4444, 32'h5555_5555, 32'h6666_6666, 32'h7777_7777, 32'h8888_8888}; int i; initial begin // Note: Base index via $c to prevent optimization i = $c(0*32); $display("0x%32x", C[i+:32]); i = $c(1*32); $display("0x%32x", C[i+:32]); i = $c(2*32); $display("0x%32x", C[i+:32]); i = $c(3*32); $display("0x%32x", C[i+:32]); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_array_packed_write_read.py0000755000542200017500000000073415125463617024637 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_exprstmt_on_lhs_of_nba.v0000644000542200017500000000550115125463617024350 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Outputs data_o, // Inputs clk, rst_i, write_valid_i, write_front_i, read_valid_i, data_i ); localparam NR_ELEMENTS = 16; localparam DATAW = 32; input clk; input rst_i; input write_valid_i; input write_front_i; input read_valid_i; input [31:0] data_i; output [31:0] data_o; reg [31:0] FIFOContent [NR_ELEMENTS-1:0]; typedef logic [$clog2(NR_ELEMENTS)-1:0] FIFOPointer_t; // verilator lint_off WIDTH localparam FIFOPointer_t MAX_PTR_VAL = NR_ELEMENTS-1; // verilator lint_on WIDTH localparam FIFOPointer_t MIN_PTR_VAL = 0; localparam FIFOPointer_t PTR_INC = 1; FIFOPointer_t write_pointer; FIFOPointer_t read_pointer; function FIFOPointer_t nextPointer(input FIFOPointer_t val); if ($clog2(NR_ELEMENTS) == $clog2(NR_ELEMENTS+1) && val == MAX_PTR_VAL) nextPointer = MIN_PTR_VAL; // explicit wrap if NR_ELEMENTS is not a power of 2 else nextPointer = val + PTR_INC; endfunction function FIFOPointer_t prevPointer(input FIFOPointer_t val); if ($clog2(NR_ELEMENTS) == $clog2(NR_ELEMENTS+1) && val == MIN_PTR_VAL) prevPointer = MAX_PTR_VAL; // explicit wrap if NR_ELEMENTS is not a power of 2 else prevPointer = val - PTR_INC; endfunction reg [$clog2(NR_ELEMENTS)-1:0] level; reg is_empty; always @(posedge clk) begin if (write_valid_i) FIFOContent[write_front_i ? (read_valid_i ? read_pointer : prevPointer(read_pointer)) : write_pointer] <= data_i; end assign data_o = FIFOContent[read_pointer]; always @(posedge clk) begin if (rst_i) begin is_empty <= 1; end else if (write_valid_i) begin is_empty <= 0; end else if (read_valid_i && write_pointer == nextPointer(read_pointer)) begin is_empty <= 1; end end always @(posedge clk) begin if (rst_i) begin level <= 0; end else begin level <= level + (write_valid_i ? 1 : 0) - (read_valid_i ? 1 : 0); end end always @(posedge clk) begin if (rst_i) begin write_pointer <= 0; end else if (write_valid_i && !write_front_i) begin write_pointer <= nextPointer(write_pointer); end end always @(posedge clk) begin if (rst_i) begin read_pointer <= 0; end else if (read_valid_i) begin if (!(write_valid_i && write_front_i))read_pointer <= nextPointer(read_pointer); end else if (write_valid_i && write_front_i) begin read_pointer <= prevPointer(read_pointer); end end endmodule verilator-5.044/test_regress/t/t_vlprocess_missing.py0000755000542200017500000000437615125463617023564 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = test.obj_dir + "/t_vlprocess_missing.v" # Number of tests to generate NUM_TESTS = 200 # Testbench header template HEADER = """\ module Testbench; logic clk; logic reset; // Clock driver initial begin clk = 0; forever begin #5 clk = ~clk; end end task automatic advance_clock(int n = 1); repeat (n) @(posedge clk); endtask """ # Test task template TEST_TASK_TEMPLATE = """ task automatic test_{num}(); int counter = 0; int expected_value = {num}; // Timeout wait fork begin advance_clock(10000); $error("Timeout"); end join_none wait (counter == expected_value); disable fork; while (counter < expected_value) begin advance_clock(); counter++; end endtask """ # Testbench footer template FOOTER = " initial begin" # Call template for invoking each test task CALL_TEMPLATE = " test_{num}();\n" # Footer end FOOTER_END = """ $finish; end endmodule """ def gen(filename, num_tests): """ Generates a SystemVerilog testbench with the specified number of tests. Args: filename (str): The output file name for the generated testbench. num_tests (int): The number of test tasks to generate. """ with open(filename, 'w', encoding="utf-8") as fh: fh.write("// Generated by t_vlprocess_missing.py\n") # Write the header fh.write(HEADER) # Generate the test tasks for i in range(1, num_tests + 1): fh.write(TEST_TASK_TEMPLATE.format(num=i)) # Write the initial block with test calls fh.write(FOOTER) for i in range(1, num_tests + 1): fh.write(CALL_TEMPLATE.format(num=i)) fh.write(FOOTER_END) gen(test.top_filename, NUM_TESTS) test.compile(verilator_flags2=["--binary"]) test.passes() verilator-5.044/test_regress/t/t_inside_queue_elem.v0000644000542200017500000000064315125463617023277 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; initial begin int q[$] = {1, 2}; if (!(1 inside {q[0], q[1]})) $stop; if (3 inside {q[0], q[1]}) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_order_dpi_export_3.cpp0000644000542200017500000000223015125463617023717 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2021 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include void toggle_other_clk(svBit val) { set_other_clk(val); } void toggle_third_clk(svBit val) { set_third_clk(val); } int main(int argc, char* argv[]) { VM_PREFIX* const tb = new VM_PREFIX; tb->contextp()->commandArgs(argc, argv); bool clk = true; while (!tb->contextp()->gotFinish()) { // Timeout if (tb->contextp()->time() > 100000) break; // Toggle and set main clock clk = !clk; tb->clk = clk; // Eval tb->eval(); // Advance time tb->contextp()->timeInc(500); } delete tb; return 0; } verilator-5.044/test_regress/t/t_mod_nomod.py0000755000542200017500000000071215125463617021754 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile() test.passes() verilator-5.044/test_regress/t/t_fork.out0000644000542200017500000000043715125463617021122 0ustar mahmoudyfreeshell%Error-NOTIMING: t/t_fork.v:10:7: Fork statements require --timing : ... note: In instance 't' 10 | fork : fblk | ^~~~ ... For error description see https://verilator.org/warn/NOTIMING?v=latest %Error: Exiting due to verilator-5.044/test_regress/t/t_expr_incr_unsup.v0000644000542200017500000000066515125463617023045 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 Krzysztof Boronski. // SPDX-License-Identifier: CC0-1.0 int i = 0; function int postincrement_i; return i++; endfunction module t; initial begin int arr [1:0] = {0, 0}; i = 0; $display("Value: %d", arr[postincrement_i()]++); end endmodule verilator-5.044/test_regress/t/t_constraint_dist_randc_bad.out0000644000542200017500000000101515125463617025336 0ustar mahmoudyfreeshell%Error: t/t_constraint_dist_randc_bad.v:10:23: Randc variables not allowed in 'constraint dist' (IEEE 1800-2023 18.5.3) 10 | constraint c_bad { rc dist {3 := 0, 10 := 5}; } | ^~ t/t_constraint_dist_randc_bad.v:10:26: ... Location of restricting expression 10 | constraint c_bad { rc dist {3 := 0, 10 := 5}; } | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_force_complex_sel_unsup.py0000755000542200017500000000077115125463617024730 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_struct_packed_init_bad.out0000644000542200017500000000057115125463617024644 0ustar mahmoudyfreeshell%Error: t/t_struct_packed_init_bad.v:12:17: Initial values not allowed in packed struct/union (IEEE 1800-2023 7.2.2) : ... note: In instance 't' 12 | bit [3:0] m_lo = P; | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_func_const_packed_struct_bad2.out0000644000542200017500000000233115125463617026120 0ustar mahmoudyfreeshell%Warning-USERFATAL: "f_add = 15" ... For warning description see https://verilator.org/warn/USERFATAL?v=latest ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_func_const_packed_struct_bad2.v:20:21: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' : ... note: In instance 't' t/t_func_const_packed_struct_bad2.v:31:9: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_func_const_packed_struct_bad2.v:43:16: ... Called from 'f_add()' with parameters: params = [0 = '{a: 32'h7, foo: 6'hb, sub_params: '{b: 32'h37, bar: 8'h6f}}, 1 = '{a: 32'h3039, foo: 6'hc, sub_params: '{b: 32'h8, bar: 8'h70}}] t/t_func_const_packed_struct_bad2.v:20:21: ... Called from 'f_add2()' with parameters: a = ?32?h7 b = ?32?h8 c = ?32?h9 20 | localparam P24 = f_add2(7, 8, 9); | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_lparam_assign_iface_typedef.v0000644000542200017500000000230015125463617025275 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // // assign localparam from interface typedef, single level nesting // verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0h exp=%0h\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on interface x_if #( parameter int p_awidth = 4, parameter int p_dwidth = 7 )(); typedef struct packed { logic [p_awidth-1:0] addr; logic [p_dwidth-1:0] data; } rq_t; typedef struct packed { logic [p_dwidth-1:0] data; } rs_t; endinterface module top(); x_if #( .p_awidth(16), .p_dwidth(8) ) if0(); localparam p0_rq_t = if0.rq_t; localparam p0_rs_t = if0.rs_t; p0_rq_t rq; p0_rs_t rs; always_comb begin rq.addr = 'h1234; rq.data = 'h37; rs.data = 'h5a; end initial begin #1; `checkh(rq.addr, 16'h1234); `checkh(rq.data, 8'h37); `checkh(rs.data, 8'h5a); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_class_override_bad.v0000644000542200017500000001106115125463617023424 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Function names correspond to how the function is declared in the base class, // then the extend class, with letters: // Does-not-exist(x), Nothing(n), :initial(i), :extends(e), :final(f) class Base; // _X = non-existant // _n = None function int get_n; return 1; endfunction function int get_n_n; return 1; endfunction function int get_n_e; return 1; endfunction function int get_n_ef; return 1; endfunction function int get_n_i; return 1; endfunction function int get_n_if; return 1; endfunction function int get_n_f; return 1; endfunction // _e = :extends function :extends int get_e; return 1; endfunction // Bad // _ef = :extends :final function :extends :final int get_ef; return 1; endfunction // Bad // _i = :initial function :initial int get_i; return 1; endfunction function :initial int get_i_n; return 1; endfunction function :initial int get_i_e; return 1; endfunction function :initial int get_i_ef; return 1; endfunction function :initial int get_i_i; return 1; endfunction function :initial int get_i_if; return 1; endfunction function :initial int get_i_f; return 1; endfunction // _if = :initial :final function :initial :final int get_if; return 1; endfunction function :initial :final int get_if_n; return 1; endfunction function :initial :final int get_if_e; return 1; endfunction function :initial :final int get_if_ef; return 1; endfunction function :initial :final int get_if_i; return 1; endfunction function :initial :final int get_if_if; return 1; endfunction function :initial :final int get_if_f; return 1; endfunction // _f = :final function :final int get_f; return 1; endfunction function :final int get_f_n; return 1; endfunction function :final int get_f_e; return 1; endfunction function :final int get_f_ef; return 1; endfunction function :final int get_f_i; return 1; endfunction function :final int get_f_if; return 1; endfunction function :final int get_f_f; return 1; endfunction endclass class Cls extends Base; // _X = non-existant function int get_x_n; return 1; endfunction function :extends int get_x_e; return 1; endfunction // Bad function :extends :final int get_x_ef; return 1; endfunction // Bad function :initial int get_x_i; return 1; endfunction function :initial :final int get_x_if; return 1; endfunction function :final int get_x_f; return 1; endfunction // _n = None function int get_n_n; return 1; endfunction function :extends int get_n_e; return 1; endfunction function :extends :final int get_n_ef; return 1; endfunction function :initial int get_n_i; return 1; endfunction // Bad function :initial :final int get_n_if; return 1; endfunction // Bad function :final int get_n_f; return 1; endfunction // _e = :extends // _ef = :extends :final // _i = :initial function int get_i_n; return 1; endfunction function :extends int get_i_e; return 1; endfunction function :extends :final int get_i_ef; return 1; endfunction function :initial int get_i_i; return 1; endfunction // Bad function :initial :final int get_i_if; return 1; endfunction // Bad function :final int get_i_f; return 1; endfunction // _if = :initial :final function int get_if_n; return 1; endfunction // Bad function :extends int get_if_e; return 1; endfunction // Bad function :extends :final int get_if_ef; return 1; endfunction // Bad function :initial int get_if_i; return 1; endfunction // Bad function :initial :final int get_if_if; return 1; endfunction // Bad function :final int get_if_f; return 1; endfunction // Bad // _f = :final function int get_f_n; return 1; endfunction // Bad function :extends int get_f_e; return 1; endfunction // Bad function :extends :final int get_f_ef; return 1; endfunction // Bad function :initial int get_f_i; return 1; endfunction // Bad function :initial :final int get_f_if; return 1; endfunction // Bad function :final int get_f_f; return 1; endfunction // Bad endclass class CBase; endclass class CClsN extends CBase; endclass class :final CClsF extends CBase; endclass class :final CClsBadExtendsFinal extends CClsF; endclass module t; initial begin Cls c; CClsF cc; if (c != null) $stop; c = new; cc = new; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_select_loop.v0000644000542200017500000000275715125463617022136 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [255:0] a; reg [255:0] q; reg [63:0] qq; integer i; always @* begin for (i=0; i<256; i=i+1) begin q[255-i] = a[i]; end q[27:16] = 12'hfed; for (i=0; i<64; i=i+1) begin qq[63-i] = a[i]; end qq[27:16] = 12'hfed; end always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $write("%x/%x %x\n", q, qq, a); `endif if (cyc==1) begin a = 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26; end if (cyc==2) begin a = 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8; if (q != 256'h64fe7e285bcf892eca128d426ed707a20eebc824d5d9127bacbc21362fed1cb7) $stop; if (qq != 64'h64fe7e285fed892e) $stop; end if (cyc==3) begin if (q != 256'h1da9cf939c0712504b5bdbbbbfbb6c47c316bd471362641958a7fabcffede870) $stop; if (qq != 64'h1da9cf939fed1250) $stop; end if (cyc==4) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.044/test_regress/t/t_interface_modportlist.py0000755000542200017500000000101515125463617024376 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_make_gmake=False, make_top_shell=False, make_main=False) test.passes() verilator-5.044/test_regress/t/t_dump_inputs_rerun.py0000755000542200017500000000525415125463617023571 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') def fixup(path): lines = [] removeBeginKeywords = True with open(path, "r", encoding="utf-8") as rfd: for line in rfd: # Remove "all arguments" line, which can differ if line.startswith("// Arguments:"): lines.append("// Arguments: ") # Remove first `begin_keywords, which will be re-inserted on reruns elif removeBeginKeywords and line.startswith("`begin_keywords"): removeBeginKeywords = False lines.append("// " + line) else: lines.append(line) with open(path, "w", encoding="utf-8") as wfd: for line in lines: wfd.write(line) obj_dir_1 = test.obj_dir + "/obj_dir_1" test.mkdir_ok(obj_dir_1) dump_1 = obj_dir_1 + "/Vprefix__inputs.vpp" test.run( logfile=obj_dir_1 + "/vlt_compile.log", cmd=[ "perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", "-cc", "-Mdir", obj_dir_1, "--prefix", "Vprefix", "--top-module", "lpm_divide", "--no-timing", "-CFLAGS", "'-O3 --foo'", # Argument with whitespace "-CFLAGS", "'-DDQUOTE=\"'", # Argument with quote "--dump-inputs", "t/t_altera_lpm.v", "t/t_math_cond_huge.v" ]) fixup(dump_1) obj_dir_2 = test.obj_dir + "/obj_dir_2" test.mkdir_ok(obj_dir_2) dump_2 = obj_dir_2 + "/Vprefix__inputs.vpp" test.run( logfile=obj_dir_2 + "/vlt_compile.log", cmd=[ "perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", "-Mdir", obj_dir_2, "-f", dump_1, dump_1, "--debug", # --debug also dumps the same way "--debugi", "1" ]) fixup(dump_2) obj_dir_3 = test.obj_dir + "/obj_dir_3" test.mkdir_ok(obj_dir_3) dump_3 = obj_dir_3 + "/Vprefix__inputs.vpp" test.run(logfile=obj_dir_3 + "/vlt_compile.log", cmd=[ "perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", "-Mdir", obj_dir_3, "-f", dump_2, dump_2, "--dump-inputs", ]) fixup(dump_3) test.files_identical(dump_1, dump_2) test.files_identical(dump_1, dump_3) test.passes() verilator-5.044/test_regress/t/t_class_new.v0000644000542200017500000000367715125463617021606 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class ClsNoArg; const int imembera; // Ok for new() to assign to a const function new(); int other = other_func(); imembera = 5; if (other != 6) $stop; endfunction : new class InnerNoArg; const int imembera; function new(); int other = other_func(); imembera = 5; if (other != 6) $stop; endfunction function int other_func(); return 6; endfunction endclass function int other_func(); return 6; endfunction endclass class ClsArg; int imembera; function new(int i); imembera = i + 1; endfunction function int geta; return imembera; endfunction static function ClsArg create6; ClsArg obj; obj = new(6 - 1); return obj; endfunction endclass class Cls2Arg; int imembera; int imemberb; function new(int i, int j); imembera = i + 1; imemberb = j + 2; endfunction function Cls2Arg clone(); Cls2Arg ret; ret = new(imembera, imemberb); return ret; endfunction endclass module t; initial begin ClsNoArg c1; ClsArg c2; Cls2Arg c3; Cls2Arg c4; ClsNoArg::InnerNoArg c5 = new; c1 = new; if (c1.imembera != 5) $stop; c2 = new(3 - 1); if (c2.imembera != 3) $stop; if (c2.geta() != 3) $stop; c2 = ClsArg::create6(); if (c2.imembera != 6) $stop; if (c2.geta() != 6) $stop; c3 = new(4, 5); if (c3.imembera != 5) $stop; if (c3.imemberb != 7) $stop; c4 = c3.clone(); if (c4.imembera != 6) $stop; if (c4.imemberb != 9) $stop; c5 = new; if (c5.imembera != 5) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_covergroup_unsup.py0000755000542200017500000000107115125463617023425 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert --error-limit 1000'], fails=True) test.passes() verilator-5.044/test_regress/t/t_display_real_noopt.py0000755000542200017500000000115715125463617023674 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_display_real.v" test.golden_filename = "t/t_display_real.out" test.compile(verilator_flags2=["-O0"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_clk_scope_bad.v0000644000542200017500000000133315125463617022363 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs out, // Inputs clk, in ); input clk; input [2:0] in; output [2:0] out; logic [2:0] r_in; always_ff @ (posedge clk) r_in <= in; flop p0 (.clk(clk), .d(r_in[0]), .q(out[0])); flop p2 (.clk(r_in[1]), .d(clk), .q(out[1])); flop p1 (.clk(clk), .d(r_in[2]), .q(out[2])); endmodule module flop ( input d, input clk, output logic q); // verilator no_inline_module always_ff @ (posedge clk) begin q <= d; end endmodule verilator-5.044/test_regress/t/t_timing_wait1.v0000644000542200017500000000374615125463617022221 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `ifdef TEST_VERBOSE `define WRITE_VERBOSE(msg) $write(msg) `else `define WRITE_VERBOSE(msg) `endif module t; int a = 0; int b = 0; int c = 0; int q[$]; initial begin `WRITE_VERBOSE("start with a==0, b==0, c==0\n"); #2 a = 1; `WRITE_VERBOSE("assign 1 to a\n"); #1 a = 2; `WRITE_VERBOSE("assign 2 to a\n"); // a==2 #1 a = 0; `WRITE_VERBOSE("assign 0 to a\n"); #1 a = 2; `WRITE_VERBOSE("assign 2 to a\n"); // 1a #1 c = 3; `WRITE_VERBOSE("assign 3 to c\n"); #1 c = 4; `WRITE_VERBOSE("assign 4 to c\n"); // a+bc b = 5; `WRITE_VERBOSE("push_back b to q\n"); q.push_back(b); end initial begin #1 `WRITE_VERBOSE("waiting for a==2\n"); wait(a == 2) if (a != 2) $stop; `WRITE_VERBOSE("waiting for a<2\n"); wait(a < 2) if (a >= 2) $stop; `WRITE_VERBOSE("waiting for a==0\n"); wait(a == 0) if (a != 0) $stop; `WRITE_VERBOSE("waiting for 1 1 && a < 3) if (a <= 1 || a >= 3) $stop; `WRITE_VERBOSE("waiting for b>a\n"); wait(b > a) if (b <= a) $stop; `WRITE_VERBOSE("waiting for a+b= c) $stop; `WRITE_VERBOSE("waiting for ac\n"); wait(a < b && b > c) if (a >= b || b <= c) $stop; `WRITE_VERBOSE("waiting for q.size() > 0\n"); wait(q.size() > 0) if (q.size() <= 0) $stop; wait(1); wait(0 < 1) $write("*-* All Finished *-*\n"); $finish; end initial wait(0) $stop; // Note this doesn't give WAITCONST initial wait(1 == 0) $stop; initial #12 $stop; // timeout endmodule verilator-5.044/test_regress/t/t_mailbox_array.v0000644000542200017500000000104715125463617022446 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; localparam DWIDTH = 6; typedef int my_type_t [2**DWIDTH]; mailbox #(my_type_t) m_mbx; function new(); this.m_mbx = new(1); endfunction endclass module tb_top(); Cls c; initial begin c = new(); $display("%p", c); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_typedef_iface_typedef6.py0000755000542200017500000000077115125463617024403 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_var_port2_bad.py0000755000542200017500000000076615125463617022536 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_typedef_param_class.v0000644000542200017500000000101215125463617023612 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Class1 #( type T ); typedef T::Some_type2 Some_type1; endclass class Class2; typedef int Some_type2; endclass module t; initial begin int value0 = 7; Class1#(Class2)::Some_type1 value1 = value0; int value2 = value1; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_vpi_unimpl.cpp0000644000542200017500000001160615125463617022316 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "verilated.h" #include "verilated_vcd_c.h" #include "Vt_vpi_unimpl.h" #include "Vt_vpi_unimpl__Dpi.h" #include "svdpi.h" // No verilated_vpi.h, make sure can link without it #include // These require the above. Comment prevents clang-format moving them #include "TestVpi.h" unsigned int callback_count = 0; //====================================================================== int _mon_check_unimpl(p_cb_data cb_data) { static TestVpiHandle cb, clk_h; vpiHandle handle; const char* cp = nullptr; if (cb_data) { // this is the callback s_vpi_error_info info; vpi_chk_error(&info); callback_count++; printf("%%Info: got pli message %s\n", info.message); } else { // setup and install static t_cb_data cb_data; clk_h = vpi_handle_by_name((PLI_BYTE8*)"t.clk", NULL); cb_data.reason = cbPLIError; cb_data.cb_rtn = _mon_check_unimpl; // this function cb = vpi_register_cb(&cb_data); CHECK_RESULT_NZ(cb); // now exercise unimplemented fns vpi_get_cb_info(cb, NULL); CHECK_RESULT(callback_count, 1); vpi_register_systf(NULL); vpi_get_systf_info(NULL, NULL); vpi_handle_multi(0, NULL, NULL); vpi_get64(0, NULL); vpi_get_delays(NULL, NULL); vpi_put_delays(NULL, NULL); vpi_get_time(NULL, NULL); vpi_mcd_name(0); vpi_compare_objects(NULL, NULL); vpi_get_data(0, NULL, 0); vpi_put_data(0, NULL, 0); vpi_get_userdata(NULL); vpi_put_userdata(NULL, NULL); vpi_handle_by_multi_index(NULL, 0, NULL); vpi_control(0); s_vpi_time time_s; time_s.type = 0; vpi_get_time(NULL, &time_s); handle = vpi_put_value(NULL, NULL, NULL, 0); CHECK_RESULT(handle, 0); handle = vpi_handle(0, NULL); CHECK_RESULT(handle, 0); vpi_iterate(0, NULL); handle = vpi_register_cb(NULL); CHECK_RESULT(handle, 0); s_cb_data cb_data_s; cb_data_s.reason = 0; // Bad handle = vpi_register_cb(&cb_data_s); CHECK_RESULT(handle, 0); (void)vpi_get_str(vpiRange, clk_h); // Bad type // Supported but illegal tests: // Various checks that guarded passing NULL handles handle = vpi_scan(NULL); CHECK_RESULT(handle, 0); (void)vpi_get(vpiType, NULL); (void)vpi_get(vpiDirection, NULL); (void)vpi_get(vpiVector, NULL); cp = vpi_get_str(vpiType, NULL); CHECK_RESULT_Z(cp); vpi_release_handle(NULL); printf("End of main test\n"); } return 0; // Ok } extern "C" int mon_check() { // Callback from initial block in monitor if (int status = _mon_check_unimpl(NULL)) return status; return 0; // Ok } //====================================================================== int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; uint64_t sim_time = 1100; contextp->commandArgs(argc, argv); // contextp->debug(9); // We're going to be checking for these errors so don't crash out contextp->fatalOnVpiError(0); const std::unique_ptr topp{new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; #ifdef VERILATOR #ifdef TEST_VERBOSE contextp->scopesDump(); #endif #endif #if VM_TRACE contextp->traceEverOn(true); VL_PRINTF("Enabling waves...\n"); VerilatedVcdC* tfp = new VerilatedVcdC; topp->trace(tfp, 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); #endif topp->eval(); topp->clk = 0; contextp->timeInc(10); while (contextp->time() < sim_time && !contextp->gotFinish()) { contextp->timeInc(1); topp->eval(); // VerilatedVpi::callValueCbs(); // Make sure can link without verilated_vpi.h included topp->clk = !topp->clk; // mon_do(); #if VM_TRACE if (tfp) tfp->dump(contextp->time()); #endif } if (!callback_count) vl_fatal(FILENM, __LINE__, "main", "%Error: never got callbacks"); if (!contextp->gotFinish()) { vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); #if VM_TRACE if (tfp) tfp->close(); #endif return 0; } verilator-5.044/test_regress/t/t_force_input_assign_bad.out0000644000542200017500000000140315125463617024642 0ustar mahmoudyfreeshell%Error-ASSIGNIN: t/t_force_input_assign_bad.v:18:10: Assigning to input/const variable: 'i' : ... note: In instance 't' 18 | s1.i = 2; | ^ ... For error description see https://verilator.org/warn/ASSIGNIN?v=latest %Error-ASSIGNIN: t/t_force_input_assign_bad.v:21:10: Assigning to input/const variable: 'i' : ... note: In instance 't' 21 | s2.i = 2; | ^ %Error-ASSIGNIN: t/t_force_input_assign_bad.v:25:17: Assigning to input/const variable: 'i' : ... note: In instance 't' 25 | assign s3.i = 2; | ^ %Error: Exiting due to verilator-5.044/test_regress/t/t_strength_strongest_non_tristate.v0000644000542200017500000000171315125463617026354 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (clk1, clk2); input wire clk1; input wire clk2; wire (weak0, weak1) a = 0; assign (strong0, supply1) a = clk1; assign (pull0, pull1) a = 1; wire b; xor (strong0, strong1) (b, clk1, clk2); and (weak0, pull1) (b, clk1, clk2); wire [7:0] c; assign (supply0, strong1) c = clk1 ? '1 : '0; assign (weak0, supply1) c = '0; assign (weak0, pull1) c = 'z; always begin if (a === clk1 && b === clk1 ^ clk2 && c[0] === clk1) begin $write("*-* All Finished *-*\n"); $finish; end else begin $write("Error: a = %b, b = %b, c[0] = %b, ", a, b, c[0]); $write("expected: a = %b, b = %b, c[0] = %b\n", clk1, clk1 ^ clk2, clk1); $stop; end end endmodule verilator-5.044/test_regress/t/t_trace_depth.py0000755000542200017500000000116215125463617022263 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(v_flags2=["--trace-vcd --trace-depth 1"]) test.execute() test.file_grep(test.trace_filename, r'value_at_top') test.file_grep_not(test.trace_filename, r' value_in_sub') test.passes() verilator-5.044/test_regress/t/t_dpi_arg_input_unpack.py0000755000542200017500000000237515125463617024175 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if test.nc: # For NC, compile twice, first just to generate DPI headers test.compile(nc_flags2=[ "+ncdpiheader+" + test.obj_dir + "/dpi-exp.h", "+ncdpiimpheader+" + test.obj_dir + "/dpi-imp.h" ]) test.compile( v_flags2=["t/" + test.name + ".cpp"], # --no-decoration so .out file doesn't comment on source lines verilator_flags2=["-Wall -Wno-DECLFILENAME --no-decoration"], # NC: Gdd the obj_dir to the C include path nc_flags2=["+ncscargs+-I" + test.obj_dir], # ModelSim: Generate DPI header, add obj_dir to the C include path ms_flags2=["-dpiheader " + test.obj_dir + "/dpi.h", "-ccflags -I" + test.obj_dir]) if test.vlt_all: test.files_identical(test.obj_dir + "/" + test.vm_prefix + "__Dpi.h", "t/" + test.name + "__Dpi.out") test.execute() test.passes() verilator-5.044/test_regress/t/t_lint_width_arraydecl.py0000755000542200017500000000070315125463617024174 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint() test.passes() verilator-5.044/test_regress/t/t_unroll_nested.v0000644000542200017500000000243115125463617022470 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifndef VERILATOR `define PRAGMA `elsif TEST_DISABLE `define PRAGMA /*verilator unroll_disable*/ `elsif TEST_FULL `define PRAGMA /*verilator unroll_full*/ `endif module t; int a, b; int pos; initial begin for (int exit_a = 0; exit_a < 2; ++exit_a) begin `PRAGMA for (int exit_b = 0; exit_b < 3; ++exit_b) begin `PRAGMA b = 0; $write("exit_a %0d %0d", exit_a, exit_b); for (a = 0; a < 3; ++a) begin : a_loop `PRAGMA $write(" A%0d", a * 10 + b); for (b = 0; b < 3; ++b) begin : b_loop `PRAGMA $write(" B%0d", a * 10 + b); if (exit_b == 1 && b == 1) disable b_loop; $write(" C%0d", a * 10 + b); if (exit_b == 2 && a == 1) disable a_loop; $write(" D%0d", a * 10 + b); end $write(" Y%0d", a * 10 + b); if (exit_a == 1 && a == 1) disable a_loop; $write(" Z%0d", a * 10 + b); end $display; end end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_var_dotted_dup_bad.py0000755000542200017500000000076315125463617023620 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_program.py0000755000542200017500000000073415125463617021454 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_xml_flat_vlvbound.v0000644000542200017500000000117015125463617023337 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module vlvbound_test ( input logic [15:0] i_a, input logic [15:0] i_b, output logic [6:0] o_a, output logic [6:0] o_b ); function automatic logic [6:0] foo(input logic [15:0] val); logic [6:0] ret; integer i; for (i=0 ; i < 7; i++) begin ret[i] = (val[i*2 +: 2] == 2'b00); end return ret; endfunction assign o_a = foo(i_a); assign o_b = foo(i_b); endmodule verilator-5.044/test_regress/t/t_func_purification.py0000755000542200017500000000073415125463617023514 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_pgo_threads_hier.py0000755000542200017500000000325015125463617023307 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vltmt') test.top_filename = "t/t_hier_block_perf.v" cycles = 100 test.sim_time = cycles * 10 + 1000 threads = 2 config_file = test.t_dir + "/" + test.name + ".vlt" flags = [config_file, "--hierarchical", "-Wno-UNOPTFLAT", "-DSIM_CYCLES=" + str(cycles)] test.compile(v_flags2=["--prof-pgo"] + flags, threads=threads) test.execute(all_run_flags=[ "+verilator+prof+exec+start+0", " +verilator+prof+exec+file+/dev/null", " +verilator+prof+vlt+file+" + test.obj_dir + "/profile.vlt"]) # yapf:disable test.file_grep(test.obj_dir + "/profile.vlt", r'profile_data -model "VTest"') test.file_grep(test.obj_dir + "/profile.vlt", r'profile_data -model "VCheck"') test.file_grep(test.obj_dir + "/profile.vlt", r'profile_data -model "VCoreHier"') test.file_grep(test.obj_dir + "/profile.vlt", r'profile_data -model "V' + test.name + '"') # Check for cost rollovers test.file_grep_not(test.obj_dir + "/profile.vlt", r'.*cost 64\'d\d{18}.*') # Differentiate results test.name = test.name + "_optimized" test.compile( # Intentionally no --prof-pgo here to make sure profile data can be read in # without it (that is: --prof-pgo has no effect on profile_data hash names) v_flags2=[test.obj_dir + "/profile.vlt"] + flags, threads=threads) test.execute() test.passes() verilator-5.044/test_regress/t/t_var_in_assign.v0000644000542200017500000000302715125463617022437 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; integer v; reg i; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire oa; // From a of a.v wire oz; // From z of z.v // End of automatics a a (.*); z z (.*); always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d i=%x oa=%x oz=%x\n", $time, cyc, i, oa, oz); `endif cyc <= cyc + 1; i <= cyc[0]; if (cyc==0) begin v = 3; if (v !== 3) $stop; if (assignin(v) !== 2) $stop; if (v !== 3) $stop; // Make sure V didn't get changed end else if (cyc<10) begin if (cyc==11 && oz!==1'b0) $stop; if (cyc==12 && oz!==1'b1) $stop; if (cyc==12 && oa!==1'b1) $stop; end else if (cyc<90) begin end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end function integer assignin(input integer i); i = 2; assignin = i; endfunction endmodule module a (input i, output oa); // verilator lint_off ASSIGNIN assign i = 1'b1; assign oa = i; endmodule module z (input i, output oz); assign oz = i; endmodule verilator-5.044/test_regress/t/t_param_store_bad.out0000644000542200017500000000051015125463617023273 0ustar mahmoudyfreeshell%Error: t/t_param_store_bad.v:12:31: Storing to parameter variable 'S' in a context that is determined only at runtime 12 | $value$plusargs("S=%s", S); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_func_complex.v0000644000542200017500000000223715125463617022301 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(); typedef integer q_t[$]; function void queue_set(ref q_t q); `ifdef TEST_NOINLINE // verilator no_inline_task `endif q.push_back(42); if (q.size() != 1) $stop; endfunction function void queue_check_nref(q_t q); `ifdef TEST_NOINLINE // verilator no_inline_task `endif q[0] = 11; if (q[0] != 11) $stop; endfunction function void queue_check_ref(const ref q_t q); `ifdef TEST_NOINLINE // verilator no_inline_task `endif if (q[0] != 42) $stop; endfunction function q_t queue_ret(); `ifdef TEST_NOINLINE // verilator no_inline_task `endif queue_ret = '{101}; endfunction initial begin q_t iq; queue_set(iq); if (iq.size() != 1) $stop; queue_check_ref(iq); iq[0] = 44; queue_check_nref(iq); if (iq[0] != 44) $stop; iq = queue_ret(); if (iq[0] != 101) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_vpi_public_depth.v0000644000542200017500000000446615125463617023145 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifndef IVERILOG import "DPI-C" context function int mon_check(); `endif package somepackage; int someint; endpackage module t (/*AUTOARG*/ // Inputs clk ); `ifdef USE_DOLLAR_C32 `systemc_header extern "C" int mon_check(); `verilog `endif input clk; integer status; wire a, b, x; A \mod.a (/*AUTOINST*/ // Outputs .x (x), // Inputs .clk (clk), .a (a), .b (b)); // Test loop initial begin `ifdef IVERILOG status = $mon_check(); `elsif USE_DOLLAR_C32 status = $c32("mon_check()"); `else status = mon_check(); `endif if (status!=0) begin $write("%%Error: t_vpi_module.cpp:%0d: C Test failed\n", status); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule : t module A(/*AUTOARG*/ // Outputs x, // Inputs clk, a, b ); // this comment should get ignored for public-ignore input clk /* verilator public_flat_rw */; input a, b; output x; wire y, c; B \mod_b$ (/*AUTOINST*/ // Outputs .y (y), // Inputs .b (b), .c (c)); C \mod\c$ (/*AUTOINST*/ // Outputs .x (x), // Inputs .clk (clk), .a (a), .y (y)); endmodule : A module B(/*AUTOARG*/ // Outputs y, // Inputs b, c ); input b, c; output reg y; always @(*) begin : myproc y = b ^ c; end endmodule module C(/*AUTOARG*/ // Outputs x, // Inputs clk, a, y ); input clk; input a, y; output reg x; always @(posedge clk) begin x <= a & y; end endmodule verilator-5.044/test_regress/t/t_flag_modprefix_bad.out0000644000542200017500000000030515125463617023747 0ustar mahmoudyfreeshell%Error: --mod-prefix argument must be a legal C++ identifier: 'bad/name' ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_inst_array.v0000644000542200017500000000270015125463617021765 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; parameter ONE = 1; wire [17:10] bitout; reg [7:0] allbits; reg [15:0] onebit; sub sub [7:0] (allbits, onebit, bitout); integer x; always @ (posedge clk) begin //$write("%x\n", bitout); if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin allbits <= 8'hac; onebit <= 16'hc01a; end if (cyc==2) begin if (bitout !== 8'h07) $stop; allbits <= 8'hca; onebit <= 16'h1f01; end if (cyc==3) begin if (bitout !== 8'h41) $stop; if (sub[0].bitout !== 1'b1) $stop; if (sub[1].bitout !== 1'b0) $stop; `ifndef verilator // Hacky array subscripting if (sub[ONE].bitout !== 1'b0) $stop; `endif $write("*-* All Finished *-*\n"); $finish; end end end endmodule `ifdef USE_INLINE `define INLINE_MODULE /*verilator inline_module*/ `else `define INLINE_MODULE /*verilator public_module*/ `endif module sub (input [7:0] allbits, input [1:0] onebit, output bitout); `INLINE_MODULE assign bitout = (^ onebit) ^ (^ allbits); endmodule verilator-5.044/test_regress/t/t_unpacked_to_queue.py0000755000542200017500000000073415125463617023505 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_altera_lpm_mult.py0000755000542200017500000000111115125463617023154 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module]) test.passes() verilator-5.044/test_regress/t/t_timing_sched.py0000755000542200017500000000077115125463617022443 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_hier_block_vlt.py0000755000542200017500000000321615125463617022771 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_hier_block.v" # stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. test.clean_objs() # CI environment offers 2 VCPUs, 2 thread setting causes the following warning. # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. # So use 6 threads here though it's not optimal in performance, but ok. test.compile(v_flags2=['t/t_hier_block.cpp'], verilator_flags2=[ '--stats', '--hierarchical', '+define+SHOW_TIMESCALE', '+define+USE_VLT', 't/t_hier_block_vlt.vlt', '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"' ], threads=(6 if test.vltmt else 1)) test.execute() test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^\s+timeprecision\s+(\d+)ps;', 1) test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") test.file_grep(test.obj_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") test.file_grep(test.obj_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14) test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") test.passes() verilator-5.044/test_regress/t/t_dpi_lib_c.cpp0000644000542200017500000001375115125463617022043 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include #include #include // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" //====================================================================== // clang-format off #if defined(VERILATOR) # include "Vt_dpi_lib__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(NC) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif // clang-format on #ifdef NEED_EXTERNS extern "C" { // If get ncsim: *F,NOFDPI: Function {foo} not found in default libdpi. // Then probably forgot to list a function here. extern int dpii_failure(); extern void dpii_check(); } #endif //====================================================================== int errors = 0; int dpii_failure() { return errors; } //====================================================================== void dpii_lib_bit_check() { svBitVecVal bv[3]; bv[0] = 0xa3a2a1a0; // 31..0 bv[1] = 0xa7a6a5a4; // 63..32 bv[2] = 0xabaaa9a8; // 95..64 TEST_CHECK_HEX_EQ((int)svGetBitselBit(bv, 32), 0); TEST_CHECK_HEX_EQ((int)svGetBitselBit(bv, 33), 0); TEST_CHECK_HEX_EQ((int)svGetBitselBit(bv, 34), 1); TEST_CHECK_HEX_EQ((int)svGetBitselBit(bv, 35), 0); TEST_CHECK_HEX_EQ((int)svGetBitselBit(bv, 36), 0); TEST_CHECK_HEX_EQ((int)svGetBitselBit(bv, 37), 1); TEST_CHECK_HEX_EQ((int)svGetBitselBit(bv, 38), 0); TEST_CHECK_HEX_EQ((int)svGetBitselBit(bv, 39), 1); svPutBitselBit(bv, 32, 1); svPutBitselBit(bv, 33, 0); svPutBitselBit(bv, 34, 1); svPutBitselBit(bv, 35, 1); TEST_CHECK_HEX_EQ(bv[0], 0xa3a2a1a0); TEST_CHECK_HEX_EQ(bv[1], 0xa7a6a5ad); TEST_CHECK_HEX_EQ(bv[2], 0xabaaa9a8); svBitVecVal btmp[2]; svGetPartselBit(btmp, bv, 40, 8); TEST_CHECK_HEX_EQ(btmp[0], 0xa5); svGetPartselBit(btmp, bv, 32, 32); TEST_CHECK_HEX_EQ(btmp[0], 0xa7a6a5ad); svGetPartselBit(btmp, bv, 48, 40); TEST_CHECK_HEX_EQ(btmp[0], 0xa9a8a7a6); TEST_CHECK_HEX_EQ(btmp[1], 0xaa); btmp[0] = 0xa5; svPutPartselBit(bv, btmp[0], 48, 8); TEST_CHECK_HEX_EQ(bv[0], 0xa3a2a1a0); TEST_CHECK_HEX_EQ(bv[1], 0xa7a5a5ad); TEST_CHECK_HEX_EQ(bv[2], 0xabaaa9a8); btmp[0] = 0x11223344; svPutPartselBit(bv, btmp[0], 32, 32); TEST_CHECK_HEX_EQ(bv[0], 0xa3a2a1a0); TEST_CHECK_HEX_EQ(bv[1], 0x11223344); TEST_CHECK_HEX_EQ(bv[2], 0xabaaa9a8); btmp[0] = 0x99887766; svPutPartselBit(bv, btmp[0], 24, 24); TEST_CHECK_HEX_EQ(bv[0], 0x66a2a1a0); TEST_CHECK_HEX_EQ(bv[1], 0x11228877); TEST_CHECK_HEX_EQ(bv[2], 0xabaaa9a8); } void dpii_lib_logic_check() { svLogicVecVal lv[3]; lv[0].aval = 0xb3b2b1b0; // 31..0 lv[1].aval = 0xb7b6b5b4; // 63..32 lv[2].aval = 0xbbbab9b8; // 95..64 lv[0].bval = 0xc3c2c1c0; // 31..0 lv[1].bval = 0xc7c6c5c4; // 63..32 lv[2].bval = 0xcbcac9c8; // 95..64 TEST_CHECK_HEX_EQ((int)svGetBitselLogic(lv, 32), 0); TEST_CHECK_HEX_EQ((int)svGetBitselLogic(lv, 33), 0); TEST_CHECK_HEX_EQ((int)svGetBitselLogic(lv, 34), 3); TEST_CHECK_HEX_EQ((int)svGetBitselLogic(lv, 35), 0); TEST_CHECK_HEX_EQ((int)svGetBitselLogic(lv, 36), 1); TEST_CHECK_HEX_EQ((int)svGetBitselLogic(lv, 37), 1); TEST_CHECK_HEX_EQ((int)svGetBitselLogic(lv, 38), 2); TEST_CHECK_HEX_EQ((int)svGetBitselLogic(lv, 39), 3); svPutBitselLogic(lv, 32, 1); svPutBitselLogic(lv, 33, 0); svPutBitselLogic(lv, 34, 1); svPutBitselLogic(lv, 35, 3); TEST_CHECK_HEX_EQ(lv[0].aval, 0xb3b2b1b0); TEST_CHECK_HEX_EQ(lv[1].aval, 0xb7b6b5bd); TEST_CHECK_HEX_EQ(lv[2].aval, 0xbbbab9b8); TEST_CHECK_HEX_EQ(lv[0].bval, 0xc3c2c1c0); TEST_CHECK_HEX_EQ(lv[1].bval, 0xc7c6c5c8); TEST_CHECK_HEX_EQ(lv[2].bval, 0xcbcac9c8); svLogicVecVal ltmp[2]; svGetPartselLogic(ltmp, lv, 40, 8); TEST_CHECK_HEX_EQ(ltmp[0].aval, 0xb5); TEST_CHECK_HEX_EQ(ltmp[0].bval, 0xc5); svGetPartselLogic(ltmp, lv, 32, 32); TEST_CHECK_HEX_EQ(ltmp[0].aval, 0xb7b6b5bd); TEST_CHECK_HEX_EQ(ltmp[0].bval, 0xc7c6c5c8); svGetPartselLogic(ltmp, lv, 48, 40); TEST_CHECK_HEX_EQ(ltmp[0].aval, 0xb9b8b7b6); TEST_CHECK_HEX_EQ(ltmp[0].bval, 0xc9c8c7c6); TEST_CHECK_HEX_EQ(ltmp[1].aval, 0xba); TEST_CHECK_HEX_EQ(ltmp[1].bval, 0xca); ltmp[0].aval = 0xb5; ltmp[0].bval = 0xc5; svPutPartselLogic(lv, ltmp[0], 48, 8); TEST_CHECK_HEX_EQ(lv[0].aval, 0xb3b2b1b0); TEST_CHECK_HEX_EQ(lv[1].aval, 0xb7b5b5bd); TEST_CHECK_HEX_EQ(lv[2].aval, 0xbbbab9b8); TEST_CHECK_HEX_EQ(lv[0].bval, 0xc3c2c1c0); TEST_CHECK_HEX_EQ(lv[1].bval, 0xc7c5c5c8); TEST_CHECK_HEX_EQ(lv[2].bval, 0xcbcac9c8); ltmp[0].aval = 0x11223344; ltmp[0].bval = 0x81828384; svPutPartselLogic(lv, ltmp[0], 32, 32); TEST_CHECK_HEX_EQ(lv[0].aval, 0xb3b2b1b0); TEST_CHECK_HEX_EQ(lv[1].aval, 0x11223344); TEST_CHECK_HEX_EQ(lv[2].aval, 0xbbbab9b8); TEST_CHECK_HEX_EQ(lv[0].bval, 0xc3c2c1c0); TEST_CHECK_HEX_EQ(lv[1].bval, 0x81828384); TEST_CHECK_HEX_EQ(lv[2].bval, 0xcbcac9c8); ltmp[0].aval = 0x99887766; ltmp[0].bval = 0x89888786; svPutPartselLogic(lv, ltmp[0], 24, 24); TEST_CHECK_HEX_EQ(lv[0].aval, 0x66b2b1b0); TEST_CHECK_HEX_EQ(lv[1].aval, 0x11228877); TEST_CHECK_HEX_EQ(lv[2].aval, 0xbbbab9b8); TEST_CHECK_HEX_EQ(lv[0].bval, 0x86c2c1c0); TEST_CHECK_HEX_EQ(lv[1].bval, 0x81828887); TEST_CHECK_HEX_EQ(lv[2].bval, 0xcbcac9c8); } //====================================================================== void dpii_check() { dpii_lib_bit_check(); dpii_lib_logic_check(); } verilator-5.044/test_regress/t/t_flag_f_bad_cmt.v0000644000542200017500000000150115125463617022477 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include "t_flag_f_tsub_inc.v" module t; initial begin `ifndef GOT_DEF1 $write("%%Error: NO GOT_DEF1\n"); $stop; `endif `ifndef GOT_DEF2 $write("%%Error: NO GOT_DEF2\n"); $stop; `endif `ifndef GOT_DEF3 $write("%%Error: NO GOT_DEF3\n"); $stop; `endif `ifndef GOT_DEF4 $write("%%Error: NO GOT_DEF4\n"); $stop; `endif `ifndef GOT_DEF5 $write("%%Error: NO GOT_DEF5\n"); $stop; `endif `ifndef GOT_DEF6 $write("%%Error: NO GOT_DEF6\n"); $stop; `endif `ifdef NON_DEF $write("%%Error: NON_DEF\n"); $stop; `endif $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_dynarray_concat.py0000755000542200017500000000073415125463617023165 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_assert_question.v0000644000542200017500000000146515125463617023051 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs dout, // Inputs clk, sel, a, c ); input clk; input bit [3:0] sel; input bit [3:0] a; input bit c; output bit dout; localparam logic DC = 1'b?; always_ff @(posedge clk) begin unique casez(sel) 4'b0000: dout <= a[0]; 4'b001?: dout <= a[1]; {1'b0, 1'b1, 1'b?, 1'b?}: dout <= a[2]; {1'b1, 1'b?, 1'b?, DC}: dout <= a[3]; default: dout <= '0; endcase $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_class_copy2.v0000644000542200017500000000142415125463617022035 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); class Cls; bit x = 1; endclass module t; Cls obj1; Cls obj2; initial begin obj1 = new; `checkh(obj1.x, 1); obj1.x = 0; obj2 = new obj1; `checkh(obj2.x, 0); obj2.x = 1; `checkh(obj1.x, 0); `checkh(obj2.x, 1); obj2.x = 0; `checkh(obj2.x, 0); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_enum_public.v0000644000542200017500000000166715125463617022127 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package p3; typedef enum logic [2:0] { ZERO = 3'b0, ONE = 3'b1 } e3_t /*verilator public*/; typedef enum logic [2:0] { TWO = 3'd2, XES = 3'b?1? } has_x_t /*verilator public*/; endpackage package p62; typedef enum logic [62:0] { ZERO = '0, ALLONE = '1 } e62_t /*verilator public*/; endpackage package pw; typedef enum logic [99:0] { // Too wide for public WIDE = 100'h123} ewide_t /*verilator public*/; endpackage module t; enum integer { EI_A, EI_B, EI_C } m_state; initial begin m_state = EI_A; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_timing_fork_nba.v0000644000542200017500000000062115125463617022742 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg b = 0, c = 1; always @(posedge clk) begin fork b <= c; c <= b; join end endmodule verilator-5.044/test_regress/t/t_detectarray_1.py0000755000542200017500000000101315125463617022523 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-Wno-UNOPTFLAT", "-fno-dfg"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_lint_eofnewline.out0000644000542200017500000000017515125463617023341 0ustar mahmoudyfreeshell`line 1 "obj_vlt/t_lint_eofnewline/t_lint_eofnewline_bad.v" 1 `line 2 "obj_vlt/t_lint_eofnewline/t_lint_eofnewline_bad.v" 0 verilator-5.044/test_regress/t/t_timing_delay_callstack.v0000644000542200017500000000304315125463617024301 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; int counter = 0; // As Verilator doesn't support recursive calls, let's use macros to // generate tasks for a deep call stack `ifdef TEST_VERBOSE `define DEEP_STACK_DELAY_END(i) \ task delay``i; \ counter++; \ $write("[%0t] at depth %0d\n", $time, i); \ counter++; \ endtask `define DEEP_STACK_DELAY(i, j) \ task delay``i; \ $write("[%0t] entering depth %0d\n", $time, i); \ #1 delay``j; \ counter++; \ #1 $write("[%0t] leaving depth %0d\n", $time, i); \ counter++; \ endtask `else `define DEEP_STACK_DELAY_END(i) \ task delay``i; \ counter += 2; \ endtask `define DEEP_STACK_DELAY(i, j) \ task delay``i; \ #1 delay``j; \ counter++; \ #1; \ counter++; \ endtask `endif `DEEP_STACK_DELAY_END(10); `DEEP_STACK_DELAY(9, 10); `DEEP_STACK_DELAY(8, 9); `DEEP_STACK_DELAY(7, 8); `DEEP_STACK_DELAY(6, 7); `DEEP_STACK_DELAY(5, 6); `DEEP_STACK_DELAY(4, 5); `DEEP_STACK_DELAY(3, 4); `DEEP_STACK_DELAY(2, 3); `DEEP_STACK_DELAY(1, 2); initial begin delay1; if ($time != 9*2) $stop; if (counter != 10*2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_case_reducer.py0000755000542200017500000000073415125463617022431 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_wrapper_context__top1.dat.out0000644000542200017500000003470615125463617025264 0ustar mahmoudyfreeshell# SystemC::Coverage-3 C 'ft/t_wrapper_context.vl14n22ttogglepagev_toggle/topoclk:0->1htop1.top' 6 C 'ft/t_wrapper_context.vl14n22ttogglepagev_toggle/topoclk:1->0htop1.top' 5 C 'ft/t_wrapper_context.vl15n22ttogglepagev_toggle/toporst:0->1htop1.top' 1 C 'ft/t_wrapper_context.vl15n22ttogglepagev_toggle/toporst:1->0htop1.top' 1 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[0]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[0]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[10]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[10]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[11]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[11]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[12]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[12]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[13]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[13]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[14]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[14]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[15]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[15]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[16]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[16]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[17]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[17]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[18]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[18]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[19]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[19]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[1]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[1]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[20]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[20]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[21]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[21]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[22]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[22]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[23]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[23]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[24]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[24]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[25]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[25]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[26]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[26]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[27]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[27]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[28]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[28]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[29]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[29]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[2]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[2]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[30]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[30]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[31]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[31]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[3]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[3]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[4]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[4]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[5]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[5]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[6]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[6]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[7]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[7]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[8]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[8]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[9]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[9]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl17n22ttogglepagev_toggle/topostop:0->1htop1.top' 1 C 'ft/t_wrapper_context.vl17n22ttogglepagev_toggle/topostop:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[0]:0->1htop1.top' 3 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[0]:1->0htop1.top' 2 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[10]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[10]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[11]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[11]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[12]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[12]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[13]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[13]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[14]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[14]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[15]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[15]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[16]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[16]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[17]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[17]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[18]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[18]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[19]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[19]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[1]:0->1htop1.top' 1 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[1]:1->0htop1.top' 1 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[20]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[20]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[21]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[21]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[22]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[22]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[23]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[23]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[24]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[24]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[25]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[25]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[26]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[26]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[27]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[27]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[28]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[28]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[29]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[29]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[2]:0->1htop1.top' 1 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[2]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[30]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[30]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[31]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[31]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[3]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[3]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[4]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[4]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[5]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[5]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[6]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[6]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[7]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[7]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[8]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[8]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[9]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[9]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl19n22ttogglepagev_toggle/topodone_o:0->1htop1.top' 1 C 'ft/t_wrapper_context.vl19n22ttogglepagev_toggle/topodone_o:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl22n4tlinepagev_line/topoblockS22,25,29,31-33htop1.top' 1 C 'ft/t_wrapper_context.vl36n4tlinepagev_line/topoblockS36htop1.top' 6 C 'ft/t_wrapper_context.vl37n7tbranchpagev_branch/topoifS37-38htop1.top' 1 C 'ft/t_wrapper_context.vl37n8tbranchpagev_branch/topoelseS40htop1.top' 5 C 'ft/t_wrapper_context.vl42n4tlinepagev_line/topoblockS42-43htop1.top' 19 C 'ft/t_wrapper_context.vl44n7tbranchpagev_branch/topoifS44htop1.top' 19 C 'ft/t_wrapper_context.vl44n8tbranchpagev_branch/topoelseS50htop1.top' 0 C 'ft/t_wrapper_context.vl45n11tlinepagev_line/topoelsehtop1.top' 18 C 'ft/t_wrapper_context.vl45n27texprpagev_expr/topo((counter >= 32'sh5)==0) => 0htop1.top' 18 C 'ft/t_wrapper_context.vl45n27texprpagev_expr/topo((counter >= 32'sh5)==1 && stop==1) => 1htop1.top' 1 C 'ft/t_wrapper_context.vl45n27texprpagev_expr/topo(stop==0) => 0htop1.top' 0 C 'ft/t_wrapper_context.vl51n10tbranchpagev_branch/topoifS51-53htop1.top' 0 C 'ft/t_wrapper_context.vl51n11tbranchpagev_branch/topoelsehtop1.top' 0 verilator-5.044/test_regress/t/t_class_class.v0000644000542200017500000000170015125463617022103 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Note UVM internals do not require classes-in-classes package P; class Cls #(type STORE_T=string); STORE_T imembera; STORE_T imemberb; class SubCls; STORE_T smembera; STORE_T smemberb; // TODO put extern function here or in t_class_extern.v to check link endclass : SubCls SubCls sc; endclass : Cls endpackage : P module t; P::Cls#(int) c; initial begin c = new; c.imembera = 10; c.imemberb = 20; c.sc = new; c.sc.smembera = 30; c.sc.smemberb = 40; if (c.imembera != 10) $stop; if (c.imemberb != 20) $stop; if (c.sc.smembera != 30) $stop; if (c.sc.smemberb != 40) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_threads_crazy_context.py0000755000542200017500000000145515125463617024414 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_threads_crazy.v" test.compile(verilator_flags2=['--cc'], threads=(2 if test.vltmt else 1), context_threads=1024) test.execute() if test.vltmt: test.file_grep( test.run_log_filename, r'Process has \d+ hardware threads available, but simulation thread count set to 1024\. This will likely cause significant slowdown\.' ) test.passes() verilator-5.044/test_regress/t/t_class_static_method.py0000755000542200017500000000073415125463617024021 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_sys_sformat.py0000755000542200017500000000073415125463617022356 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_display_qqq.py0000755000542200017500000000077215125463617022336 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_force_readwrite_unsup.v0000644000542200017500000000124415125463617024212 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Cls; task take_ref(ref logic s); endtask endclass module t; logic a; logic b = 1; Cls cls = new; initial begin force a = b; cls.take_ref(a); cls.take_ref(b); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_config_rules.py0000755000542200017500000000125415125463617022462 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=[ "--binary", "--top cfg", "--work liba t/t_config_rules_sub.v", "--work libb t/t_config_rules_sub.v", "--work libc t/t_config_rules_sub.v", "--work libd t/t_config_rules_sub.v" ]) test.execute() test.passes() verilator-5.044/test_regress/t/t_class_new_supernfirst_bad.py0000755000542200017500000000145315125463617025234 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.extract(in_filename=test.top_filename, out_filename=test.root + "/docs/gen/ex_SUPERNFIRST_faulty.rst", lines="18-20") test.extract(in_filename=test.golden_filename, out_filename=test.root + "/docs/gen/ex_SUPERNFIRST_msg.rst", regexp=r'SUPERNFIRST:') test.passes() verilator-5.044/test_regress/t/t_wrapper_context__top0.dat.out0000644000542200017500000003471115125463617025257 0ustar mahmoudyfreeshell# SystemC::Coverage-3 C 'ft/t_wrapper_context.vl14n22ttogglepagev_toggle/topoclk:0->1htop0.top' 11 C 'ft/t_wrapper_context.vl14n22ttogglepagev_toggle/topoclk:1->0htop0.top' 10 C 'ft/t_wrapper_context.vl15n22ttogglepagev_toggle/toporst:0->1htop0.top' 1 C 'ft/t_wrapper_context.vl15n22ttogglepagev_toggle/toporst:1->0htop0.top' 1 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[0]:0->1htop0.top' 1 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[0]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[10]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[10]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[11]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[11]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[12]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[12]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[13]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[13]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[14]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[14]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[15]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[15]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[16]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[16]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[17]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[17]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[18]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[18]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[19]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[19]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[1]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[1]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[20]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[20]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[21]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[21]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[22]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[22]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[23]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[23]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[24]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[24]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[25]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[25]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[26]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[26]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[27]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[27]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[28]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[28]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[29]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[29]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[2]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[2]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[30]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[30]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[31]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[31]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[3]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[3]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[4]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[4]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[5]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[5]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[6]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[6]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[7]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[7]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[8]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[8]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[9]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[9]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl17n22ttogglepagev_toggle/topostop:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl17n22ttogglepagev_toggle/topostop:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[0]:0->1htop0.top' 5 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[0]:1->0htop0.top' 5 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[10]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[10]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[11]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[11]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[12]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[12]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[13]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[13]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[14]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[14]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[15]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[15]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[16]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[16]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[17]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[17]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[18]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[18]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[19]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[19]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[1]:0->1htop0.top' 3 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[1]:1->0htop0.top' 2 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[20]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[20]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[21]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[21]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[22]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[22]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[23]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[23]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[24]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[24]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[25]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[25]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[26]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[26]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[27]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[27]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[28]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[28]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[29]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[29]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[2]:0->1htop0.top' 1 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[2]:1->0htop0.top' 1 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[30]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[30]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[31]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[31]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[3]:0->1htop0.top' 1 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[3]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[4]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[4]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[5]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[5]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[6]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[6]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[7]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[7]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[8]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[8]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[9]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[9]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl19n22ttogglepagev_toggle/topodone_o:0->1htop0.top' 1 C 'ft/t_wrapper_context.vl19n22ttogglepagev_toggle/topodone_o:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl22n4tlinepagev_line/topoblockS22,25,29,31-33htop0.top' 1 C 'ft/t_wrapper_context.vl36n4tlinepagev_line/topoblockS36htop0.top' 11 C 'ft/t_wrapper_context.vl37n7tbranchpagev_branch/topoifS37-38htop0.top' 1 C 'ft/t_wrapper_context.vl37n8tbranchpagev_branch/topoelseS40htop0.top' 10 C 'ft/t_wrapper_context.vl42n4tlinepagev_line/topoblockS42-43htop0.top' 34 C 'ft/t_wrapper_context.vl44n7tbranchpagev_branch/topoifS44htop0.top' 0 C 'ft/t_wrapper_context.vl44n8tbranchpagev_branch/topoelseS50htop0.top' 34 C 'ft/t_wrapper_context.vl45n11tlinepagev_line/topoelsehtop0.top' 0 C 'ft/t_wrapper_context.vl45n27texprpagev_expr/topo((counter >= 32'sh5)==0) => 0htop0.top' 0 C 'ft/t_wrapper_context.vl45n27texprpagev_expr/topo((counter >= 32'sh5)==1 && stop==1) => 1htop0.top' 0 C 'ft/t_wrapper_context.vl45n27texprpagev_expr/topo(stop==0) => 0htop0.top' 0 C 'ft/t_wrapper_context.vl51n10tbranchpagev_branch/topoifS51-53htop0.top' 1 C 'ft/t_wrapper_context.vl51n11tbranchpagev_branch/topoelsehtop0.top' 33 verilator-5.044/test_regress/t/t_lint_iface_array_topmodule3.py0000755000542200017500000000070615125463617025452 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.044/test_regress/t/t_case_inside.v0000644000542200017500000000340715125463617022065 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc = 0; reg [63:0] crc; reg [63:0] sum; reg out1; reg [4:0] out2; sub sub (.in(crc[23:0]), .out1(out1), .out2(out2)); always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x sum=%x in[3:0]=%x out=%x,%x\n", $time, cyc, crc, sum, crc[3:0], out1,out2); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2}; if (cyc==0) begin // Setup crc <= 64'h00000000_00000097; sum <= 64'h0; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); `define EXPECTED_SUM 64'h10204fa5567c8a4b if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub (/*AUTOARG*/ // Outputs out1, out2, // Inputs in ); input [23:0] in; output reg out1; output reg [4:0] out2; always @* begin case (in[3:0]) inside default {out1,out2} = {1'b0,5'h0F}; // Note not last item, no : to cover parser 4'h1, 4'h2, 4'h3: {out1,out2} = {1'b1,5'h01}; 4'h4: {out1,out2} = {1'b1,5'h04}; [4'h6:4'h5]: {out1,out2} = {1'b1,5'h05}; // order backwards, will not match 4'b100?:/*8,9*/ {out1,out2} = {1'b1,5'h08}; [4'hc:4'hf]: {out1,out2} = {1'b1,5'h0C}; endcase end endmodule verilator-5.044/test_regress/t/t_lint_modport_dir_bad.v0000644000542200017500000000154515125463617023776 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface dummy_if (); logic signal; modport slave (output signal); modport master (input signal); endinterface: dummy_if module sub ( input wire signal_i, output wire signal_o, dummy_if.master dummy_in, dummy_if.slave dummy_out ); assign dummy_in.signal = signal_i; assign signal_o = dummy_out.signal; endmodule module t (/*AUTOARG*/ // Outputs signal_o, // Inputs signal_i ); input signal_i; output signal_o; dummy_if dummy_if (); sub sub ( .signal_i(signal_i), .signal_o(signal_o), .dummy_in(dummy_if), .dummy_out(dummy_if) ); endmodule verilator-5.044/test_regress/t/t_lint_defparam_bad.py0000755000542200017500000000114615125463617023416 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_lint_defparam.v" test.lint(verilator_flags2=["-Wwarn-style -Wno-DECLFILENAME"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_interface_ar2a.v0000644000542200017500000000077515125463617022471 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: SystemVerilog interface test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Thierry Tambe. // SPDX-License-Identifier: CC0-1.0 module t (); ahb_slave_intf AHB_S[1](); AHB_MEM uMEM(.S(AHB_S[0].source)); // AHB_MEM V_MEM(.S(AHB_S[0])); endmodule module AHB_MEM ( ahb_slave_intf.source S ); endmodule interface ahb_slave_intf (); logic [31:0] HADDR; modport source (input HADDR); endinterface verilator-5.044/test_regress/t/t_timing_wait3.py0000755000542200017500000000077115125463617022404 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_class_extends_arg.py0000755000542200017500000000073415125463617023475 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_udp_param_bad.py0000755000542200017500000000076615125463617022570 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_sequence_first_match_unsup.out0000644000542200017500000000273515125463617025611 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:47:40: Unsupported: or (in sequence expression) 47 | initial p0: assert property ((##1 1) or (##2 1) |-> x==1); | ^~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:50:52: Unsupported: or (in sequence expression) 50 | initial p1: assert property (first_match((##1 1) or (##2 1)) |-> x==1); | ^~ %Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:50:32: Unsupported: first_match (in sequence expression) 50 | initial p1: assert property (first_match((##1 1) or (##2 1)) |-> x==1); | ^~~~~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:53:34: Unsupported: or (in sequence expression) 53 | initial p2: assert property (1 or ##1 1 |-> x==0); | ^~ %Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:56:46: Unsupported: or (in sequence expression) 56 | initial p3: assert property (first_match(1 or ##1 1) |-> x==0); | ^~ %Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:56:32: Unsupported: first_match (in sequence expression) 56 | initial p3: assert property (first_match(1 or ##1 1) |-> x==0); | ^~~~~~~~~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_gantt_io_arm.out0000644000542200017500000000266315125463617022627 0ustar mahmoudyfreeshellVerilator Gantt report Argument settings: +verilator+prof+exec+start+1 +verilator+prof+exec+window+2 Summary: Total elapsed time = 300000 rdtsc ticks Parallelized code = 80.49% of elapsed time Waiting time = 0.67% of elapsed time Total threads = 2 Total CPUs used = 2 Total mtasks = 5 Total yields = 51 NUMA assignment: NUMA status = 0,2;1,3 Parallelized code, measured: Thread utilization = 42.50% Speedup = 0.85x Parallelized code, predicted during static scheduling: Thread utilization = 82.44% Speedup = 1.65x All code, measured: Thread utilization = 43.96% Speedup = 0.879x All code, measured, scaled by predicted speedup: Thread utilization = 72.06% Speedup = 1.44x MTask statistics: Longest mtask id = 79 Longest mtask time = 57.05% of time elapsed in parallelized code min log(p2e) = -1.054 from mtask 79 (predict 48001, elapsed 137754) max log(p2e) = 3.641 from mtask 87 (predict 33809, elapsed 887) mean = 1.656 stddev = 2.104 e ^ stddev = 8.200 CPU info: Id | Time spent executing MTask | Socket | Core | Model | % of elapsed ticks / ticks | | | ====|============================|========|======|====== 2 | 67.44% / 202323 | | | Phytium,FT-2500/128 3 | 0.97% / 2914 | | | Phytium,FT-2500/128 Writing profile_exec.vcd verilator-5.044/test_regress/t/t_tri_gate_nmos_pins_inout.py0000755000542200017500000000140615125463617025103 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" test.compile(make_top_shell=False, make_main=False, v_flags2=['+define+T_NMOS'], make_flags=['CPPFLAGS_ADD=-DT_NMOS'], verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) test.execute() test.passes() verilator-5.044/test_regress/t/t_class_new_ref_bad.out0000644000542200017500000000150615125463617023577 0ustar mahmoudyfreeshell%Error: t/t_class_new_ref_bad.v:16:24: new() assignment not legal to non-class data type 'int' : ... note: In instance 't' 16 | txn_type_t txn = new; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_class_new_ref_bad.v:17:25: new() cannot copy from non-class data type 'int' : ... note: In instance 't' 17 | txn_type_t copy = new txn; | ^~~ %Error: t/t_class_new_ref_bad.v:26:21: Assign RHS expects a CLASSREFDTYPE 'Base', got BASICDTYPE 'int' : ... note: In instance 't' 26 | Base b = Cls::generate_txn(); | ^~~~~~~~~~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_display_wide_bad.out0000644000542200017500000000054515125463617023444 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_display_wide_bad.v:25:10: Unsupported: Exceeded limit of 8192 bits for any $display-like arguments 25 | $write("[%0t] cyc==%0d crc=%d\n", $time, cyc, {crc, crc, crc, crc}); | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.044/test_regress/t/t_pgo_profoutofdate_bad.out0000644000542200017500000000074715125463617024521 0ustar mahmoudyfreeshell%Warning-PROFOUTOFDATE: t/t_pgo_profoutofdate_bad.v:27:1: Profile data for mtasks may be out of date. 3 of 3 mtasks had no data 27 | profile_data -model "x" -mtask "h7baded98__0" -cost 64'd12345678901234567890 | ^~~~~~~~~~~~ ... For warning description see https://verilator.org/warn/PROFOUTOFDATE?v=latest ... Use "/* verilator lint_off PROFOUTOFDATE */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.044/test_regress/t/t_tagged.out0000644000542200017500000000427015125463617021413 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_tagged.v:9:18: Unsupported: tagged union 9 | typedef union tagged { | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_tagged.v:10:6: Unsupported: void (for tagged unions) 10 | void m_invalid; | ^~~~ %Error: t/t_tagged.v:19:14: syntax error, unexpected tagged, expecting IDENTIFIER-for-type 19 | u = tagged m_invalid; | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error-UNSUPPORTED: t/t_tagged.v:24:16: Unsupported: matches (for tagged union) 24 | case (u) matches | ^~~~~~~ %Error: t/t_tagged.v:29:9: syntax error, unexpected tagged, expecting IDENTIFIER-for-type 29 | tagged m_invalid: ; | ^~~~~~ %Error-UNSUPPORTED: t/t_tagged.v:34:34: Unsupported: '{} tagged patterns 34 | if (u matches tagged m_int .n) $stop; | ^ %Error-UNSUPPORTED: t/t_tagged.v:34:21: Unsupported: '{} tagged patterns 34 | if (u matches tagged m_int .n) $stop; | ^~~~~~ %Error-UNSUPPORTED: t/t_tagged.v:34:13: Unsupported: matches operator 34 | if (u matches tagged m_int .n) $stop; | ^~~~~~~ %Error: t/t_tagged.v:36:11: syntax error, unexpected tagged, expecting IDENTIFIER-for-type 36 | u = tagged m_int (123); | ^~~~~~ %Error: t/t_tagged.v:40:9: syntax error, unexpected tagged, expecting IDENTIFIER-for-type 40 | tagged m_invalid: $stop; | ^~~~~~ %Error-UNSUPPORTED: t/t_tagged.v:45:34: Unsupported: '{} tagged patterns 45 | if (u matches tagged m_int .n) if (n != 123) $stop; | ^ %Error-UNSUPPORTED: t/t_tagged.v:45:21: Unsupported: '{} tagged patterns 45 | if (u matches tagged m_int .n) if (n != 123) $stop; | ^~~~~~ %Error-UNSUPPORTED: t/t_tagged.v:45:13: Unsupported: matches operator 45 | if (u matches tagged m_int .n) if (n != 123) $stop; | ^~~~~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_alias_cyclic_bad.out0000644000542200017500000000166415125463617023411 0ustar mahmoudyfreeshell%Error: t/t_alias_cyclic_bad.v:18:13: Alias is specified more than once (IEEE 1800-2023 10.11): 'a' : ... note: In instance 't' 18 | alias a = a; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_alias_cyclic_bad.v:19:9: Alias is specified more than once (IEEE 1800-2023 10.11): 'a' : ... note: In instance 't' 19 | alias a = b; | ^ %Error: t/t_alias_cyclic_bad.v:20:9: Alias is specified more than once (IEEE 1800-2023 10.11): 'b' : ... note: In instance 't' 20 | alias b = a; | ^ %Error: t/t_alias_cyclic_bad.v:20:13: Alias is specified more than once (IEEE 1800-2023 10.11): 'a' : ... note: In instance 't' 20 | alias b = a; | ^ %Error: Exiting due to verilator-5.044/test_regress/t/t_disable_fork1.v0000644000542200017500000000200215125463617022312 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define N 3 class Cls; task runforks(integer n); for (integer i = 0; i < n; i++) fork #1 $stop; join_none endtask endclass module t; Cls cls = new; initial begin // run forks for (integer i = 0; i < `N; i++) fork #1 $stop; join_none // run forks inside a method cls.runforks(`N); // run forks in forks for (integer i = 0; i < `N; i++) fork for (integer j = 0; j < `N; j++) fork #1 $stop; join_none join_none for (integer i = 0; i < `N; i++) fork cls.runforks(`N); join_none // kill them all disable fork; // check if we can still fork fork #2 $write("*-* All Finished *-*\n"); #3 $finish; join_none end endmodule verilator-5.044/test_regress/t/t_class2.py0000755000542200017500000000073415125463617021174 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_class_extends_colon.py0000755000542200017500000000101315125463617024025 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(make_flags=['VM_PARALLEL_BUILDS=1']) # bug2775) test.execute() test.passes() verilator-5.044/test_regress/t/t_class_param_static.py0000755000542200017500000000073415125463617023641 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_interface_dearray_bad.out0000644000542200017500000000346115125463617024436 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_interface_dearray_bad.v:23:9: Unexpected target of interface assignment ['IFACEREFDTYPE$[0:5]'] : ... note: In instance 'tb_top' 23 | a = f; | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_interface_dearray_bad.v:26:13: Array size mismatch in interface assignment : ... note: In instance 'tb_top' 26 | c.vif = b; | ^ %Error: t/t_interface_dearray_bad.v:31:23: Expecting expression to be constant, but variable isn't const: 'i' : ... note: In instance 'tb_top' 31 | d.vif[i] = a[i]; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error-UNSUPPORTED: t/t_interface_dearray_bad.v:31:23: Non-constant index in RHS interface array selection : ... note: In instance 'tb_top' 31 | d.vif[i] = a[i]; | ^ %Error-UNSUPPORTED: t/t_interface_dearray_bad.v:35:16: Interface slices unsupported : ... note: In instance 'tb_top' 35 | e.vif = b[0:5]; | ^ %Error: Internal Error: t/t_interface_dearray_bad.v:23:11: ../V3Broken.cpp:#: Broken link in node (or something without maybePointedTo): 'm_varp && !m_varp->brokeExists()' @ ./V3Ast__gen_impl.h:# : ... note: In instance 'tb_top' 23 | a = f; | ^ ... This fatal error may be caused by the earlier error(s); resolve those first. verilator-5.044/test_regress/t/t_disable_bad.out0000644000542200017500000000073215125463617022370 0ustar mahmoudyfreeshell%Error: t/t_disable_bad.v:9:13: Can't find definition of block/task: 'abcd' 9 | disable abcd; | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Internal Error: t/t_disable_bad.v:9:5: ../V3LinkJump.cpp:#: Unlinked disable statement 9 | disable abcd; | ^~~~~~~ ... This fatal error may be caused by the earlier error(s); resolve those first. verilator-5.044/test_regress/t/t_package_enum.py0000755000542200017500000000073415125463617022424 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_time_passed.py0000755000542200017500000000100015125463617022265 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_mailbox_bad.v0000644000542200017500000000061015125463617022051 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; mailbox #(int) m; initial begin m = new(4); if (m.bad_method() != 0) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_func_paramed.v0000644000542200017500000000363115125463617022242 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [11:0] in_a; reg [31:0] sel; wire [2:0] out_x; extractor #(4,3) extractor ( // Outputs .out (out_x), // Inputs .in (in_a), .sel (sel)); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; //$write("%d %x %x %x\n", cyc, in_a, sel, out_x); if (cyc==1) begin in_a <= 12'b001_101_111_010; sel <= 32'd0; end if (cyc==2) begin sel <= 32'd1; if (out_x != 3'b010) $stop; end if (cyc==3) begin sel <= 32'd2; if (out_x != 3'b111) $stop; end if (cyc==4) begin sel <= 32'd3; if (out_x != 3'b101) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module extractor (/*AUTOARG*/ // Outputs out, // Inputs in, sel ); parameter IN_WIDTH=8; parameter OUT_WIDTH=2; input [IN_WIDTH*OUT_WIDTH-1:0] in; output [OUT_WIDTH-1:0] out; input [31:0] sel; wire [OUT_WIDTH-1:0] out = selector(in,sel); function [OUT_WIDTH-1:0] selector; input [IN_WIDTH*OUT_WIDTH-1:0] inv; input [31:0] selv; integer i; begin selector = 0; for (i=0; i>{4'hd}}); `checkh(bit_q[0], 1'b1); `checkh(bit_q[1], 1'b1); `checkh(bit_q[2], 1'b0); `checkh(bit_q[3], 1'b1); bit_q = bit_q_t'({<<{4'hc}}); `checkh(bit_q[0], 1'b0); `checkh(bit_q[1], 1'b0); `checkh(bit_q[2], 1'b1); `checkh(bit_q[3], 1'b1); bit_q = {>>{bit_q_t'(4'he)}}; `checkh(bit_q[0], 1'b1); `checkh(bit_q[1], 1'b1); `checkh(bit_q[2], 1'b1); `checkh(bit_q[3], 1'b0); bit_q = {<<{bit_q_t'(4'hd)}}; `checkh(bit_q[0], 1'b1); `checkh(bit_q[1], 1'b0); `checkh(bit_q[2], 1'b1); `checkh(bit_q[3], 1'b1); bit_qq = {>>{bit_q}}; `checkh(bit_qq[0], 1'b1); `checkh(bit_qq[1], 1'b0); `checkh(bit_qq[2], 1'b1); `checkh(bit_qq[3], 1'b1); bit_qq = {<<{bit_q}}; `checkh(bit_qq[0], 1'b1); `checkh(bit_qq[1], 1'b1); `checkh(bit_qq[2], 1'b0); `checkh(bit_qq[3], 1'b1); bit_q = bit_q_t'({>>{4'hd}}); `checkh(bit_q[0], 1'b1); `checkh(bit_q[1], 1'b1); `checkh(bit_q[2], 1'b0); `checkh(bit_q[3], 1'b1); bit_q = bit_q_t'({>>2{4'hd}}); `checkh(bit_q[0], 1'b1); `checkh(bit_q[1], 1'b1); `checkh(bit_q[2], 1'b0); `checkh(bit_q[3], 1'b1); bit_qq = bit_q_t'({>>{bit_q}}); `checkh(bit_qq[0], 1'b1); `checkh(bit_qq[1], 1'b1); `checkh(bit_qq[2], 1'b0); `checkh(bit_qq[3], 1'b1); bit_qq = bit_q_t'({>>2{bit_q}}); `checkh(bit_qq[0], 1'b1); `checkh(bit_qq[1], 1'b1); `checkh(bit_qq[2], 1'b0); `checkh(bit_qq[3], 1'b1); bit_qq = bit_q_t'({<<{bit_q}}); `checkh(bit_qq[0], 1'b1); `checkh(bit_qq[1], 1'b0); `checkh(bit_qq[2], 1'b1); `checkh(bit_qq[3], 1'b1); bit_qq = {<<2{bit_qq}}; `checkh(bit_qq[0], 1'b1); `checkh(bit_qq[1], 1'b1); `checkh(bit_qq[2], 1'b1); `checkh(bit_qq[3], 1'b0); bit_qq = {<<2{bit_q_t'({<<{bit_q}})}}; `checkh(bit_qq[0], 1'b1); `checkh(bit_qq[1], 1'b1); `checkh(bit_qq[2], 1'b1); `checkh(bit_qq[3], 1'b0); end begin cdata_q_t cdata_q, cdata_qq; cdata_q = cdata_q_t'(32'hdeadbeef); `checkh(cdata_q[0], 8'hde); `checkh(cdata_q[1], 8'had); `checkh(cdata_q[2], 8'hbe); `checkh(cdata_q[3], 8'hef); cdata_qq = cdata_q_t'({<<{cdata_q}}); `checkh(cdata_qq[0], 8'hf7); `checkh(cdata_qq[1], 8'h7d); `checkh(cdata_qq[2], 8'hb5); `checkh(cdata_qq[3], 8'h7b); cdata_qq = {<<2{cdata_q}}; `checkh(cdata_qq[0], 8'hfb); `checkh(cdata_qq[1], 8'hbe); `checkh(cdata_qq[2], 8'h7a); `checkh(cdata_qq[3], 8'hb7); end begin sdata_logic_q_t sdata_q, sdata_qq; sdata_q = sdata_logic_q_t'(64'hfeedface_deadbeef); `checkh(sdata_q[0], 16'hfeed); `checkh(sdata_q[1], 16'hface); `checkh(sdata_q[2], 16'hdead); `checkh(sdata_q[3], 16'hbeef); sdata_qq = sdata_logic_q_t'({<<{sdata_q}}); `checkh(sdata_qq[0], 16'hf77d); `checkh(sdata_qq[1], 16'hb57b); `checkh(sdata_qq[2], 16'h735f); `checkh(sdata_qq[3], 16'hb77f); sdata_qq = {<<2{sdata_q}}; `checkh(sdata_qq[0], 16'hfbbe); `checkh(sdata_qq[1], 16'h7ab7); `checkh(sdata_qq[2], 16'hb3af); `checkh(sdata_qq[3], 16'h7bbf); end begin idata_logic_q_t idata_q, idata_qq; idata_q = idata_logic_q_t'(64'h12345678_9abcdef0); `checkh(idata_q[0], 32'h12345678); `checkh(idata_q[1], 32'h9abcdef0); idata_qq = idata_logic_q_t'({<<{idata_q}}); `checkh(idata_qq[0], 32'h0f7b3d59); `checkh(idata_qq[1], 32'h1e6a2c48); idata_q = idata_logic_q_t'(128'hfeedface_deadbeef_cafebabe_12345678); `checkh(idata_q[0], 32'hfeedface); `checkh(idata_q[1], 32'hdeadbeef); `checkh(idata_q[2], 32'hcafebabe); `checkh(idata_q[3], 32'h12345678); idata_qq = {<<2{idata_logic_q_t'({<<{idata_q}})}}; `checkh(idata_qq[0], 32'hfddef5cd); `checkh(idata_qq[1], 32'hed5e7ddf); `checkh(idata_qq[2], 32'hc5fd757d); `checkh(idata_qq[3], 32'h2138a9b4); end begin qdata_logic_q_t qdata_q, qdata_qq; qdata_q.push_back(64'hdeadbeef_cafebabe); qdata_q.push_back(64'hfeedface_12345678); `checkh(qdata_q[0], 64'hdeadbeef_cafebabe); `checkh(qdata_q[1], 64'hfeedface_12345678); qdata_qq = qdata_logic_q_t'({<<{qdata_q}}); `checkh(qdata_qq[0], 64'h1e6a2c48735fb77f); `checkh(qdata_qq[1], 64'h7d5d7f53f77db57b); qdata_q.push_back(64'h1111222233334444); qdata_q.push_back(64'h5555666677778888); qdata_qq = {<<2{qdata_q}}; `checkh(qdata_qq[0], 64'h2222dddd99995555); `checkh(qdata_qq[1], 64'h1111cccc88884444); `checkh(qdata_qq[2], 64'h2d951c84b3af7bbf); `checkh(qdata_qq[3], 64'hbeaebfa3fbbe7ab7); end begin wide_q_t wide_q, wide_qq; wide_q.push_back(128'hdeadbeef_cafebabe_feedface_12345678); wide_q.push_back(128'h11112222_33334444_55556666_77778888); `checkh(wide_q[0], 128'hdeadbeef_cafebabe_feedface_12345678); `checkh(wide_q[1], 128'h11112222_33334444_55556666_77778888); wide_qq = wide_q_t'({<<{wide_q}}); `checkh(wide_qq[0], 128'h1111eeee6666aaaa2222cccc44448888); `checkh(wide_qq[1], 128'h1e6a2c48735fb77f7d5d7f53f77db57b); wide_q.push_back(128'haaaabbbb_ccccdddd_eeeeffff_00001111); wide_q.push_back(128'h22223333_44445555_66667777_88889999); wide_qq = wide_q_t'({<<{wide_q}}); wide_qq = {<<2{wide_q}}; `checkh(wide_qq[0], 128'h66662222dddd999955551111cccc8888); `checkh(wide_qq[1], 128'h44440000ffffbbbb77773333eeeeaaaa); `checkh(wide_qq[2], 128'h2222dddd999955551111cccc88884444); `checkh(wide_qq[3], 128'h2d951c84b3af7bbfbeaebfa3fbbe7ab7); end begin byte_q_t bytq_init; byte_q_t bytq; bit_q_t bitq; bytq_init.push_back(8'h84); bytq_init.push_back(8'haa); `checkh(bytq_init[0], 8'h84); `checkh(bytq_init[1], 8'haa); s = $sformatf("bytq_init=%p", bytq_init); `checks(s, "bytq_init='{'h84, 'haa}"); bytq = bytq_init; bitq = {<<8{bit_q_t'({<<{bytq}})}}; bytq = {<<8{bit_q_t'({<<{bitq}})}}; s = $sformatf("bitq=%p", bitq); `checks(s, "bitq='{'h0, 'h0, 'h1, 'h0, 'h0, 'h0, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1}"); s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'h84, 'haa}"); /* Generalized block-reversal semantics for the outer left-stream when blockSize > 1. This seemingly complicated approach is what is required to match commercial simulators, otherwise the straggler bit [1] in the padded byte might end up as 0x01 instead of 0x80. Starting with result of inner {<<{bitq}}: [1,1,0,1,0,1,0,1,0,1,0,0,0,0,1,0,0] (17 bits), apply outer {<<8{...}} using generalized block-reversal like this: - Reverse all bits: [0,0,1,0,0,0,0,1,0,1,0,1,0,1,0,1,1] - Split into 8-bit blocks from left and pad incomplete blocks on the left: - Block 0: [0,0,1,0,0,0,0,1] (complete) - Block 1: [0,1,0,1,0,1,0,1] (complete) - Block 2: [1] -> pad on left -> [0,0,0,0,0,0,0,1] - Reverse bits within each 8-bit block: - Block 0: [0,0,1,0,0,0,0,1] -> [1,0,0,0,0,1,0,0] = 0x84 - Block 1: [0,1,0,1,0,1,0,1] -> [1,0,1,0,1,0,1,0] = 0xaa - Block 2: [0,0,0,0,0,0,0,1] -> [1,0,0,0,0,0,0,0] = 0x80 */ bytq = bytq_init; bitq = {<<8{bit_q_t'({<<{bytq}})}}; bitq.push_back(1'b1); bytq = {<<8{bit_q_t'({<<{bitq}})}}; s = $sformatf("bitq=%p", bitq); `checks(s, "bitq='{'h0, 'h0, 'h1, 'h0, 'h0, 'h0, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h1}"); `checkh(bytq[0], 8'h84); `checkh(bytq[1], 8'haa); `checkh(bytq[2], 8'h80); s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'h84, 'haa, 'h80}"); bytq = bytq_init; bitq = {<<8{bit_q_t'({<<{bytq}})}}; bitq.push_back(1'b1); bitq.push_back(1'b1); bytq = {<<8{bit_q_t'({<<{bitq}})}}; s = $sformatf("bitq=%p", bitq); `checks(s, "bitq='{'h0, 'h0, 'h1, 'h0, 'h0, 'h0, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h1, 'h1}"); s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'h84, 'haa, 'hc0}"); bytq = bytq_init; bitq = {<<8{bit_q_t'({<<{bytq}})}}; bitq.push_back(1'b1); bitq.push_back(1'b1); bitq.push_back(1'b1); bytq = {<<8{bit_q_t'({<<{bitq}})}}; s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'h84, 'haa, 'he0}"); bytq = bytq_init; bitq = {<<8{bit_q_t'({<<{bytq}})}}; bitq.push_back(1'b1); bitq.push_back(1'b1); bitq.push_back(1'b1); bitq.push_back(1'b0); bytq = {<<8{bit_q_t'({<<{bitq}})}}; s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'h84, 'haa, 'h70}"); bytq = bytq_init; bitq = {<<8{bit_q_t'({<<{bytq}})}}; bitq.push_back(1'b1); bitq.push_back(1'b1); bitq.push_back(1'b1); bitq.push_back(1'b0); bitq.push_back(1'b1); bytq = {<<8{bit_q_t'({<<{bitq}})}}; s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'h84, 'haa, 'hb8}"); bytq = bytq_init; bitq = {<<8{bit_q_t'({<<{bytq}})}}; bitq.push_back(1'b1); bitq.push_back(1'b1); bitq.push_back(1'b1); bitq.push_back(1'b0); bitq.push_back(1'b1); bitq.push_back(1'b0); bytq = {<<8{bit_q_t'({<<{bitq}})}}; s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'h84, 'haa, 'h5c}"); bytq = bytq_init; bitq = {<<8{bit_q_t'({<<{bytq}})}}; bitq.push_back(1'b1); bitq.push_back(1'b1); bitq.push_back(1'b1); bitq.push_back(1'b0); bitq.push_back(1'b1); bitq.push_back(1'b0); bitq.push_back(1'b0); bytq = {<<8{bit_q_t'({<<{bitq}})}}; s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'h84, 'haa, 'h2e}"); bytq = bytq_init; bitq = {<<8{bit_q_t'({<<{bytq}})}}; bitq.push_back(1'b1); bitq.push_back(1'b1); bitq.push_back(1'b1); bitq.push_back(1'b0); bitq.push_back(1'b1); bitq.push_back(1'b0); bitq.push_back(1'b0); bitq.push_back(1'b1); bytq = {<<8{bit_q_t'({<<{bitq}})}}; s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'h84, 'haa, 'h97}"); bytq = bytq_init; bitq = {<<8{bit_q_t'({<<{bytq}})}}; bitq.push_back(1'b1); bitq.push_back(1'b1); bitq.push_back(1'b1); bitq.push_back(1'b0); bitq.push_back(1'b1); bitq.push_back(1'b0); bitq.push_back(1'b0); bitq.push_back(1'b1); bitq.push_back(1'b1); bytq = {<<8{bit_q_t'({<<{bitq}})}}; s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'h84, 'haa, 'h97, 'h80}"); end // Test StreamR (>>) operations - fairly simple since this should maintain left-to-right order. begin bit_q_t bitq; byte_q_t bytq; bitq = {1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0}; bitq = {>>4{bit_q_t'({<<{bitq}})}}; s = $sformatf("bitq=%p", bitq); `checks(s, "bitq='{'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1}"); bytq = {8'h84, 8'haa}; bitq = {>>{bit_q_t'({<<{bytq}})}}; s = $sformatf("bitq=%p", bitq); `checks(s, "bitq='{'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h0, 'h1, 'h0, 'h0, 'h0, 'h0, 'h1}"); bitq = { 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 }; bytq = {>>2{byte_q_t'({<<{bitq}})}}; s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'h43, 'h55}"); bytq = {8'h12, 8'h34, 8'h56}; bytq = {>>{byte_q_t'({<<{bytq}})}}; s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'h6a, 'h2c, 'h48}"); bitq = {1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0}; bitq = {>>6{bit_q_t'({>>{bitq}})}}; s = $sformatf("bitq=%p", bitq); `checks(s, "bitq='{'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0}"); bytq = {8'h84, 8'haa}; bitq = {>>{bit_q_t'({>>{bytq}})}}; s = $sformatf("bitq=%p", bitq); `checks(s, "bitq='{'h1, 'h0, 'h0, 'h0, 'h0, 'h1, 'h0, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0}"); bitq = { 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 }; bytq = {>>8{byte_q_t'({>>{bitq}})}}; s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'haa, 'hc2}"); bytq = {8'h12, 8'h34, 8'h56}; bytq = {>>{byte_q_t'({>>{bytq}})}}; s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'h12, 'h34, 'h56}"); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_param_type_bad.out0000644000542200017500000000042415125463617023124 0ustar mahmoudyfreeshell%Error: t/t_param_type_bad.v:9:27: Expecting a data type, not a constant: 2 9 | localparam type bad2 = 2; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_gen_for_overlap.py0000755000542200017500000000073415125463617023154 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_trace_fst_cmake.out0000644000542200017500000002554515125463617023302 0ustar mahmoudyfreeshell$date Sat Apr 5 13:56:26 2025 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $var wire 1 ! clk $end $var wire 5 " state [4:0] $end $scope module t $end $var wire 1 ! clk $end $var int 32 # cyc [31:0] $end $var logic 1 $ rstn $end $var wire 5 " state [4:0] $end $var real_parameter 64 % fst_gparam_real $end $var real_parameter 64 & fst_lparam_real $end $var real 64 % fst_real $end $var integer 32 ' fst_integer [31:0] $end $var bit 1 ( fst_bit $end $var logic 1 ) fst_logic $end $var int 32 * fst_int [31:0] $end $var shortint 16 + fst_shortint [15:0] $end $var longint 64 , fst_longint [63:0] $end $var byte 8 - fst_byte [7:0] $end $var parameter 32 . fst_parameter [31:0] $end $var parameter 32 / fst_lparam [31:0] $end $var supply0 1 0 fst_supply0 $end $var supply1 1 1 fst_supply1 $end $var tri0 1 0 fst_tri0 $end $var tri1 1 1 fst_tri1 $end $var tri 1 2 fst_tri $end $var wire 1 3 fst_wire $end $scope module test $end $var wire 1 ! clk $end $var wire 1 $ rstn $end $var wire 5 " state [4:0] $end $var logic 5 4 state_w [4:0] $end $var logic 5 5 state_array[0] [4:0] $end $var logic 5 6 state_array[1] [4:0] $end $var logic 5 7 state_array[2] [4:0] $end $scope module unnamedblk1 $end $var int 32 8 i [31:0] $end $upscope $end $scope module unnamedblk2 $end $var int 32 9 i [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b00000000000000000000000000000000 9 b00000000000000000000000000000000 8 b00000 7 b00000 6 b00000 5 b00000 4 03 02 11 00 b00000000000000000000000111001000 / b00000000000000000000000001111011 . b00000000 - b0000000000000000000000000000000000000000000000000000000000000000 , b0000000000000000 + b00000000000000000000000000000000 * 0) 0( b00000000000000000000000000000000 ' r4.56 & r1.23 % 0$ b00000000000000000000000000000000 # b00000 " 0! $end #10 1! b00001 " b00000000000000000000000000000001 # b10100 4 b00001 5 b00001 6 b00001 7 b00000000000000000000000000000011 8 #15 0! #20 1! b00000000000000000000000000000010 # #25 0! #30 1! b00000000000000000000000000000011 # #35 0! #40 1! b00000000000000000000000000000100 # #45 0! #50 1! b00000000000000000000000000000101 # #55 0! #60 1! b00000000000000000000000000000110 # #65 0! #70 1! b00000000000000000000000000000111 # #75 0! #80 1! b00000000000000000000000000001000 # #85 0! #90 1! b00000000000000000000000000001001 # #95 0! #100 1! b00000000000000000000000000001010 # #105 0! #110 1! b00000000000000000000000000001011 # 1$ #115 0! #120 1! b00000000000000000000000000001100 # b10100 7 b01010 4 b00000000000000000000000000000010 9 #125 0! #130 1! b00101 4 b01010 7 b00000000000000000000000000001101 # b10100 6 #135 0! #140 1! b01010 6 b00000000000000000000000000001110 # b00101 7 b10110 4 b10100 5 b10100 " #145 0! #150 1! b01010 " b01010 5 b01011 4 b10110 7 b00000000000000000000000000001111 # b00101 6 #155 0! #160 1! b10110 6 b00000000000000000000000000010000 # b01011 7 b10001 4 b00101 5 b00101 " #165 0! #170 1! b10110 " b10110 5 b11100 4 b10001 7 b00000000000000000000000000010001 # b01011 6 #175 0! #180 1! b10001 6 b00000000000000000000000000010010 # b11100 7 b01110 4 b01011 5 b01011 " #185 0! #190 1! b10001 " b10001 5 b00111 4 b01110 7 b00000000000000000000000000010011 # b11100 6 #195 0! #200 1! b01110 6 b00000000000000000000000000010100 # b00111 7 b10111 4 b11100 5 b11100 " #205 0! #210 1! b01110 " b01110 5 b11111 4 b10111 7 b00000000000000000000000000010101 # b00111 6 #215 0! #220 1! b10111 6 b00000000000000000000000000010110 # b11111 7 b11011 4 b00111 5 b00111 " #225 0! #230 1! b10111 " b10111 5 b11001 4 b11011 7 b00000000000000000000000000010111 # b11111 6 #235 0! #240 1! b11011 6 b00000000000000000000000000011000 # b11001 7 b11000 4 b11111 5 b11111 " #245 0! #250 1! b11011 " b11011 5 b01100 4 b11000 7 b00000000000000000000000000011001 # b11001 6 #255 0! #260 1! b11000 6 b00000000000000000000000000011010 # b01100 7 b00110 4 b11001 5 b11001 " #265 0! #270 1! b11000 " b11000 5 b00011 4 b00110 7 b00000000000000000000000000011011 # b01100 6 #275 0! #280 1! b00110 6 b00000000000000000000000000011100 # b00011 7 b10101 4 b01100 5 b01100 " #285 0! #290 1! b00110 " b00110 5 b11110 4 b10101 7 b00000000000000000000000000011101 # b00011 6 #295 0! #300 1! b10101 6 b00000000000000000000000000011110 # b11110 7 b01111 4 b00011 5 b00011 " #305 0! #310 1! b10101 " b10101 5 b10011 4 b01111 7 b00000000000000000000000000011111 # b11110 6 #315 0! #320 1! b01111 6 b00000000000000000000000000100000 # b10011 7 b11101 4 b11110 5 b11110 " #325 0! #330 1! b01111 " b01111 5 b11010 4 b11101 7 b00000000000000000000000000100001 # b10011 6 #335 0! #340 1! b11101 6 b00000000000000000000000000100010 # b11010 7 b01101 4 b10011 5 b10011 " #345 0! #350 1! b11101 " b11101 5 b10010 4 b01101 7 b00000000000000000000000000100011 # b11010 6 #355 0! #360 1! b01101 6 b00000000000000000000000000100100 # b10010 7 b01001 4 b11010 5 b11010 " #365 0! #370 1! b01101 " b01101 5 b10000 4 b01001 7 b00000000000000000000000000100101 # b10010 6 #375 0! #380 1! b01001 6 b00000000000000000000000000100110 # b10000 7 b01000 4 b10010 5 b10010 " #385 0! #390 1! b01001 " b01001 5 b00100 4 b01000 7 b00000000000000000000000000100111 # b10000 6 #395 0! #400 1! b01000 6 b00000000000000000000000000101000 # b00100 7 b00010 4 b10000 5 b10000 " #405 0! #410 1! b01000 " b01000 5 b00001 4 b00010 7 b00000000000000000000000000101001 # b00100 6 #415 0! #420 1! b00010 6 b00000000000000000000000000101010 # b00001 7 b10100 4 b00100 5 b00100 " #425 0! #430 1! b00010 " b00010 5 b01010 4 b10100 7 b00000000000000000000000000101011 # b00001 6 #435 0! #440 1! b10100 6 b00000000000000000000000000101100 # b01010 7 b00101 4 b00001 5 b00001 " #445 0! #450 1! b10100 " b10100 5 b10110 4 b00101 7 b00000000000000000000000000101101 # b01010 6 #455 0! #460 1! b00101 6 b00000000000000000000000000101110 # b10110 7 b01011 4 b01010 5 b01010 " #465 0! #470 1! b00101 " b00101 5 b10001 4 b01011 7 b00000000000000000000000000101111 # b10110 6 #475 0! #480 1! b01011 6 b00000000000000000000000000110000 # b10001 7 b11100 4 b10110 5 b10110 " #485 0! #490 1! b01011 " b01011 5 b01110 4 b11100 7 b00000000000000000000000000110001 # b10001 6 #495 0! #500 1! b11100 6 b00000000000000000000000000110010 # b01110 7 b00111 4 b10001 5 b10001 " #505 0! #510 1! b11100 " b11100 5 b10111 4 b00111 7 b00000000000000000000000000110011 # b01110 6 #515 0! #520 1! b00111 6 b00000000000000000000000000110100 # b10111 7 b11111 4 b01110 5 b01110 " #525 0! #530 1! b00111 " b00111 5 b11011 4 b11111 7 b00000000000000000000000000110101 # b10111 6 #535 0! #540 1! b11111 6 b00000000000000000000000000110110 # b11011 7 b11001 4 b10111 5 b10111 " #545 0! #550 1! b11111 " b11111 5 b11000 4 b11001 7 b00000000000000000000000000110111 # b11011 6 #555 0! #560 1! b11001 6 b00000000000000000000000000111000 # b11000 7 b01100 4 b11011 5 b11011 " #565 0! #570 1! b11001 " b11001 5 b00110 4 b01100 7 b00000000000000000000000000111001 # b11000 6 #575 0! #580 1! b01100 6 b00000000000000000000000000111010 # b00110 7 b00011 4 b11000 5 b11000 " #585 0! #590 1! b01100 " b01100 5 b10101 4 b00011 7 b00000000000000000000000000111011 # b00110 6 #595 0! #600 1! b00011 6 b00000000000000000000000000111100 # b10101 7 b11110 4 b00110 5 b00110 " #605 0! #610 1! b00011 " b00011 5 b01111 4 b11110 7 b00000000000000000000000000111101 # b10101 6 #615 0! #620 1! b11110 6 b00000000000000000000000000111110 # b01111 7 b10011 4 b10101 5 b10101 " #625 0! #630 1! b11110 " b11110 5 b11101 4 b10011 7 b00000000000000000000000000111111 # b01111 6 #635 0! #640 1! b10011 6 b00000000000000000000000001000000 # b11101 7 b11010 4 b01111 5 b01111 " #645 0! #650 1! b10011 " b10011 5 b01101 4 b11010 7 b00000000000000000000000001000001 # b11101 6 #655 0! #660 1! b11010 6 b00000000000000000000000001000010 # b01101 7 b10010 4 b11101 5 b11101 " #665 0! #670 1! b11010 " b11010 5 b01001 4 b10010 7 b00000000000000000000000001000011 # b01101 6 #675 0! #680 1! b10010 6 b00000000000000000000000001000100 # b01001 7 b10000 4 b01101 5 b01101 " #685 0! #690 1! b10010 " b10010 5 b01000 4 b10000 7 b00000000000000000000000001000101 # b01001 6 #695 0! #700 1! b10000 6 b00000000000000000000000001000110 # b01000 7 b00100 4 b01001 5 b01001 " #705 0! #710 1! b10000 " b10000 5 b00010 4 b00100 7 b00000000000000000000000001000111 # b01000 6 #715 0! #720 1! b00100 6 b00000000000000000000000001001000 # b00010 7 b00001 4 b01000 5 b01000 " #725 0! #730 1! b00100 " b00100 5 b10100 4 b00001 7 b00000000000000000000000001001001 # b00010 6 #735 0! #740 1! b00001 6 b00000000000000000000000001001010 # b10100 7 b01010 4 b00010 5 b00010 " #745 0! #750 1! b00001 " b00001 5 b00101 4 b01010 7 b00000000000000000000000001001011 # b10100 6 #755 0! #760 1! b01010 6 b00000000000000000000000001001100 # b00101 7 b10110 4 b10100 5 b10100 " #765 0! #770 1! b01010 " b01010 5 b01011 4 b10110 7 b00000000000000000000000001001101 # b00101 6 #775 0! #780 1! b10110 6 b00000000000000000000000001001110 # b01011 7 b10001 4 b00101 5 b00101 " #785 0! #790 1! b10110 " b10110 5 b11100 4 b10001 7 b00000000000000000000000001001111 # b01011 6 #795 0! #800 1! b10001 6 b00000000000000000000000001010000 # b11100 7 b01110 4 b01011 5 b01011 " #805 0! #810 1! b10001 " b10001 5 b00111 4 b01110 7 b00000000000000000000000001010001 # b11100 6 #815 0! #820 1! b01110 6 b00000000000000000000000001010010 # b00111 7 b10111 4 b11100 5 b11100 " #825 0! #830 1! b01110 " b01110 5 b11111 4 b10111 7 b00000000000000000000000001010011 # b00111 6 #835 0! #840 1! b10111 6 b00000000000000000000000001010100 # b11111 7 b11011 4 b00111 5 b00111 " #845 0! #850 1! b10111 " b10111 5 b11001 4 b11011 7 b00000000000000000000000001010101 # b11111 6 #855 0! #860 1! b11011 6 b00000000000000000000000001010110 # b11001 7 b11000 4 b11111 5 b11111 " #865 0! #870 1! b11011 " b11011 5 b01100 4 b11000 7 b00000000000000000000000001010111 # b11001 6 #875 0! #880 1! b11000 6 b00000000000000000000000001011000 # b01100 7 b00110 4 b11001 5 b11001 " #885 0! #890 1! b11000 " b11000 5 b00011 4 b00110 7 b00000000000000000000000001011001 # b01100 6 #895 0! #900 1! b00110 6 b00000000000000000000000001011010 # b00011 7 b10101 4 b01100 5 b01100 " #905 0! #910 1! b00110 " b00110 5 b11110 4 b10101 7 b00000000000000000000000001011011 # b00011 6 #915 0! #920 1! b10101 6 b00000000000000000000000001011100 # b11110 7 b01111 4 b00011 5 b00011 " #925 0! #930 1! b10101 " b10101 5 b10011 4 b01111 7 b00000000000000000000000001011101 # b11110 6 #935 0! #940 1! b01111 6 b00000000000000000000000001011110 # b10011 7 b11101 4 b11110 5 b11110 " #945 0! #950 1! b01111 " b01111 5 b11010 4 b11101 7 b00000000000000000000000001011111 # b10011 6 #955 0! #960 1! b11101 6 b00000000000000000000000001100000 # b11010 7 b01101 4 b10011 5 b10011 " #965 0! #970 1! b11101 " b11101 5 b10010 4 b01101 7 b00000000000000000000000001100001 # b11010 6 #975 0! #980 1! b01101 6 b00000000000000000000000001100010 # b10010 7 b01001 4 b11010 5 b11010 " #985 0! #990 1! b01101 " b01101 5 b10000 4 b01001 7 b00000000000000000000000001100011 # b10010 6 #995 0! #1000 1! b01001 6 b00000000000000000000000001100100 # b10000 7 b01000 4 b10010 5 b10010 " verilator-5.044/test_regress/t/t_select_sideeffect.py0000755000542200017500000000073415125463617023445 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_assert_ctl_immediate.out0000644000542200017500000000105615125463617024340 0ustar mahmoudyfreeshell[0] %Error: t_assert_ctl_immediate.v:47: Assertion failed in top.t.module_with_assertctl: 'assert' failed. -Info: t/t_assert_ctl_immediate.v:47: Verilog $stop, ignored due to +verilator+error+limit [0] %Error: t_assert_ctl_immediate.v:53: Assertion failed in top.t.module_with_assertctl: 'assert' failed. [0] %Error: t_assert_ctl_immediate.v:41: Assertion failed in top.t.module_with_assertctl.f_assert: 'assert' failed. [0] %Error: t_assert_ctl_immediate.v:41: Assertion failed in top.t.module_with_assertctl.f_assert: 'assert' failed. *-* All Finished *-* verilator-5.044/test_regress/t/t_fuzz_eqne_bad.v0000644000542200017500000000045715125463617022435 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //bug1587 module t; reg a[0]; reg b; reg c; initial c = (a != &b); endmodule verilator-5.044/test_regress/t/t_tagged.py0000755000542200017500000000100415125463617021227 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_fuzz_always_bad.out0000644000542200017500000000063615125463617023346 0ustar mahmoudyfreeshell%Error: t/t_fuzz_always_bad.v:10:15: Can't find definition of 'a' in dotted variable/method: 'c.a' 10 | always @ c.a c:h; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_fuzz_always_bad.v:10:19: Can't find definition of task/function: 'h' 10 | always @ c.a c:h; | ^ %Error: Exiting due to verilator-5.044/test_regress/t/t_math_repl.v0000644000542200017500000000702515125463617021572 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [63:0] rf; reg [63:0] rf2; reg [63:0] biu; reg b; always @* begin rf[63:32] = biu[63:32] & {32{b}}; rf[31:0] = {32{b}}; rf2 = rf; rf2[31:0] = ~{32{b}}; end reg [31:0] src1, src0, sr, mask; wire [31:0] dualasr = ((| src1[31:4]) ? {{16{src0[31]}}, {16{src0[15]}}} : ( ( sr & {2{mask[31:16]}}) | ( {{16{src0[31]}}, {16{src0[15]}}} & {2{~mask[31:16]}}))); wire [31:0] sl_mask = (32'hffffffff << src1[4:0]); wire [31:0] sr_mask = {sl_mask[0], sl_mask[1], sl_mask[2], sl_mask[3], sl_mask[4], sl_mask[5], sl_mask[6], sl_mask[7], sl_mask[8], sl_mask[9], sl_mask[10], sl_mask[11], sl_mask[12], sl_mask[13], sl_mask[14], sl_mask[15], sl_mask[16], sl_mask[17], sl_mask[18], sl_mask[19], sl_mask[20], sl_mask[21], sl_mask[22], sl_mask[23], sl_mask[24], sl_mask[25], sl_mask[26], sl_mask[27], sl_mask[28], sl_mask[29], sl_mask[30], sl_mask[31]}; wire [95:0] widerep = {2{({2{({2{ {b,b}, {b,{2{b}}}, {{2{b}},b}, {2{({2{b}})}} }})}})}}; wire [1:0] w = {2{b}}; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $write("cyc=%0d d=%x %x %x %x %x %x %x\n", cyc, b, rf, rf2, dualasr, sl_mask, sr_mask, widerep); `endif if (cyc==1) begin biu <= 64'h12451282_abadee00; b <= 1'b0; src1 <= 32'h00000001; src0 <= 32'h9a4f1235; sr <= 32'h0f19f567; mask <= 32'h7af07ab4; end if (cyc==2) begin biu <= 64'h12453382_abad8801; b <= 1'b1; if (rf != 64'h0) $stop; if (rf2 != 64'h00000000ffffffff) $stop; src1 <= 32'h0010000f; src0 <= 32'h028aa336; sr <= 32'h42ad0377; mask <= 32'h1ab3b906; if (dualasr != 32'h8f1f7060) $stop; if (sl_mask != 32'hfffffffe) $stop; if (sr_mask != 32'h7fffffff) $stop; if (widerep != '0) $stop; end if (cyc==3) begin biu <= 64'h12422382_77ad8802; b <= 1'b1; if (rf != 64'h12453382ffffffff) $stop; if (rf2 != 64'h1245338200000000) $stop; src1 <= 32'h0000000f; src0 <= 32'h5c158f71; sr <= 32'h7076c40a; mask <= 32'h33eb3d44; if (dualasr != 32'h0000ffff) $stop; if (sl_mask != 32'hffff8000) $stop; if (sr_mask != 32'h0001ffff) $stop; if (widerep != '1) $stop; end if (cyc==4) begin if (rf != 64'h12422382ffffffff) $stop; if (rf2 != 64'h1242238200000000) $stop; if (dualasr != 32'h3062cc1e) $stop; if (sl_mask != 32'hffff8000) $stop; if (sr_mask != 32'h0001ffff) $stop; $write("*-* All Finished *-*\n"); if (widerep != '1) $stop; $finish; end end end endmodule verilator-5.044/test_regress/t/t_lint_assigneqexpr.v0000644000542200017500000000142415125463617023353 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input logic a2_i, a1_i, a0_i, input logic b_i, output logic d_o ); // verilator lint_off PINMISSING Sub sub ( .a_i({a2_i, a1_i, a0_i}), .b_i, .d_o ); // verilator lint_on PINMISSING endmodule module Sub ( input logic [2:0] a_i, input logic b_i, output logic c_o, output logic d_o ); assign c_o = (a_i != 0) ? 1 : 0; assign d_o = // Note = not == below ( c_o = 1 // <--- Warning: ASSIGNEQEXPR ) ? 1 : ( c_o = 0 // <--- Warning: ASSIGNEQEXPR ) ? b_i : 0; endmodule verilator-5.044/test_regress/t/t_foreach_type_bad.v0000644000542200017500000000077215125463617023077 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; endclass module t; real r; bit b[2]; Cls c; initial begin foreach (c[i]); // bad type foreach (r[i]); // no loop var foreach (b[i, j, k]); // extra loop var foreach (r[, i]); // no loop var and extra $stop; end endmodule verilator-5.044/test_regress/t/t_assert_ctl_type_bad.v0000755000542200017500000000046015125463617023630 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $assertcontrol(0); $assertcontrol(100); end endmodule verilator-5.044/test_regress/t/t_flag_f_bad_cmt.vc0000644000542200017500000000004215125463617022641 0ustar mahmoudyfreeshell/* Multiline unterminated comment verilator-5.044/test_regress/t/t_preproc_elsif_bad.py0000755000542200017500000000105615125463617023445 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint( fails=True, # The .vh file has the error, not the .v file expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_inst_missing_dot_bad.v0000644000542200017500000000053115125463617023774 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $display("a=", missing.a); end missing missing(); // Intentionally missing endmodule verilator-5.044/test_regress/t/t_c_width_bad.v0000644000542200017500000000044415125463617022044 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test of select from constant // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; bit [99:0] wide = $c100("0"); initial $display("%d", wide); endmodule verilator-5.044/test_regress/t/t_alias_transitive.py0000755000542200017500000000073415125463617023346 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_func_ref_arg.py0000755000542200017500000000073415125463617022425 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_randomize_rand_mode_unsup.py0000755000542200017500000000076315125463617025241 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_foreach_array.v0000755000542200017500000001163415125463617022430 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by PlanV GmbH. // SPDX-License-Identifier: CC0-1.0 module t_foreach_array; // Define various structures to test foreach behavior int dyn_arr[][]; int queue[$][$]; int unpacked_arr [3:1][9:8]; int associative_array_3d[string][string][string]; int queue_unp[$][3]; // Outer dynamic queue with fixed-size inner arrays int unp_queue[3][$]; // Fixed-size outer array with dynamic inner queues int dyn_queue[][]; // Fully dynamic 2D array int queue_dyn[$][]; // Outer dynamic queue with dynamic inner queues int dyn_unp[][3]; // Dynamic outer array with fixed-size inner arrays int unp_dyn[3][]; // Fixed-size outer array with dynamic inner arrays // Define counter for various structures of array int count_que, exp_count_que; int count_dyn, exp_count_dyn; int count_unp, exp_count_unp; int count_assoc; int count_queue_unp, exp_count_queue_unp; int count_unp_queue, exp_count_unp_queue; int count_dyn_queue, exp_count_dyn_queue; int count_queue_dyn, exp_count_queue_dyn; int count_dyn_unp, exp_count_dyn_unp; int count_unp_dyn, exp_count_unp_dyn; string k1, k2, k3; initial begin // Initialize queue = '{'{1, 2, 3}, '{4, 5}, '{6}}; dyn_arr = '{'{1, 2, 3}, '{4, 5, 6, 0, 10}, '{6, 7, 8, 9}}; associative_array_3d["key1"]["subkey1"]["subsubkey1"] = 1; associative_array_3d["key1"]["subkey1"]["subsubkey2"] = 2; associative_array_3d["key1"]["subkey2"]["subsubkey1"] = 3; associative_array_3d["key1"]["subkey3"]["subsubkey1"] = 4; associative_array_3d["key1"]["subkey3"]["subsubkey2"] = 5; associative_array_3d["key1"]["subkey3"]["subsubkey3"] = 6; associative_array_3d["key2"]["subkey1"]["subsubkey1"] = 7; associative_array_3d["key2"]["subkey1"]["subsubkey2"] = 8; associative_array_3d["key2"]["subkey3"]["subsubkey1"] = 9; queue_unp = '{'{1, 2, 3}, '{4, 5, 6}, '{7, 8, 9}}; unp_queue[0] = '{10, 11}; unp_queue[1] = '{12, 13, 14}; unp_queue[2] = '{15}; dyn_queue = '{'{16, 17}, '{18, 19, 20}}; queue_dyn = '{'{21, 22}, '{23, 24, 25}}; dyn_unp = '{'{26, 27, 28}, '{29, 30, 31}}; unp_dyn[0] = '{32, 33}; unp_dyn[1] = '{34, 35, 36}; unp_dyn[2] = '{37}; // Perform foreach loop counting and expected value calculation count_que = 0; foreach(queue[i, j]) count_que++; exp_count_que = 0; foreach(queue[i]) foreach(queue[i][j]) exp_count_que++; count_dyn = 0; foreach(dyn_arr[i, j]) count_dyn++; exp_count_dyn = 0; foreach(dyn_arr[i]) foreach(dyn_arr[i][j]) exp_count_dyn++; count_unp = 0; foreach(unpacked_arr[i, j]) count_unp++; exp_count_unp = 0; foreach(unpacked_arr[i]) foreach(unpacked_arr[i][j]) exp_count_unp++; count_assoc = 0; foreach(associative_array_3d[k1, k2, k3]) count_assoc++; count_queue_unp = 0; foreach (queue_unp[i, j]) count_queue_unp++; exp_count_queue_unp = 0; foreach (queue_unp[i]) foreach (queue_unp[i][j]) exp_count_queue_unp++; count_unp_queue = 0; foreach (unp_queue[i, j]) count_unp_queue++; exp_count_unp_queue = 0; foreach (unp_queue[i]) foreach (unp_queue[i][j]) exp_count_unp_queue++; count_dyn_queue = 0; foreach (dyn_queue[i, j]) count_dyn_queue++; exp_count_dyn_queue = 0; foreach (dyn_queue[i]) foreach (dyn_queue[i][j]) exp_count_dyn_queue++; count_queue_dyn = 0; foreach (queue_dyn[i, j]) count_queue_dyn++; exp_count_queue_dyn = 0; foreach (queue_dyn[i]) foreach (queue_dyn[i][j]) exp_count_queue_dyn++; count_dyn_unp = 0; foreach (dyn_unp[i, j]) count_dyn_unp++; exp_count_dyn_unp = 0; foreach (dyn_unp[i]) foreach (dyn_unp[i][j]) exp_count_dyn_unp++; count_unp_dyn = 0; foreach (unp_dyn[i, j]) count_unp_dyn++; exp_count_unp_dyn = 0; foreach (unp_dyn[i]) foreach (unp_dyn[i][j]) exp_count_unp_dyn++; // Verification checks if (count_que != 6 || count_que != exp_count_que) $stop; if (count_dyn != 12 || count_dyn != exp_count_dyn) $stop; if (count_unp != 6 || count_unp != exp_count_unp) $stop; if (count_assoc != 9) $stop; if (count_queue_unp != exp_count_queue_unp) $stop; if (count_unp_queue != exp_count_unp_queue) $stop; if (count_dyn_queue != exp_count_dyn_queue) $stop; if (count_queue_dyn != exp_count_queue_dyn) $stop; if (count_dyn_unp != exp_count_dyn_unp) $stop; if (count_unp_dyn != exp_count_unp_dyn) $stop; $write("*-* All Finished *-*\\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_alias_ports_unsup.py0000755000542200017500000000077615125463617023565 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_lint_range_negative_bad.py0000755000542200017500000000076615125463617024624 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_dpi_arg_input_type.py0000755000542200017500000000244115125463617023667 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if test.nc: # For NC, compile twice, first just to generate DPI headers test.compile(nc_flags2=[ "+ncdpiheader+" + test.obj_dir + "/dpi-exp.h", "+ncdpiimpheader+" + test.obj_dir + "/dpi-imp.h" ]) test.compile( v_flags2=["t/" + test.name + ".cpp"], # --no-decoration so .out file doesn't comment on source lines verilator_flags2=["-Wall -Wno-DECLFILENAME --no-decoration"], # NC: Gdd the obj_dir to the C include path nc_flags2=["+ncscargs+-I" + test.obj_dir], # ModelSim: Generate DPI header, add obj_dir to the C include path ms_flags2=["-dpiheader " + test.obj_dir + "/dpi.h", "-ccflags -I" + test.obj_dir]) if test.vlt_all: test.files_identical(test.obj_dir + "/" + test.vm_prefix + "__Dpi.h", "t/" + test.name + "__Dpi.out") test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_randomize_method_with_bad.v0000644000542200017500000000075315125463617025011 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Foo; rand int unsigned v; endclass module t_randomize_method_with_bad(); function automatic int unsigned in_mod_function(); return 5; endfunction initial begin Foo foo = new; int res = foo.randomize() with { v < in_mod_function(); }; end endmodule verilator-5.044/test_regress/t/t_var_ref_bad3.out0000644000542200017500000000050115125463617022466 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_var_ref_bad3.v:10:18: Unsupported: ref/const ref as primary input/output: 'bad_primary_ref' 10 | module t(ref int bad_primary_ref); | ^~~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.044/test_regress/t/t_mod_interface_array0.v0000644000542200017500000000260315125463617023671 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Johan Bjork. // SPDX-License-Identifier: CC0-1.0 parameter N = 4; interface a_if #(parameter PARAM = 0) (); logic long_name; modport source (output long_name); modport sink (input long_name); endinterface module intf_source ( input logic [N-1:0] intf_input, a_if.source i_intf_source[N-1:0] ); generate for (genvar i=0; i < N;i++) begin assign i_intf_source[i].long_name = intf_input[i]; end endgenerate endmodule module intf_sink ( output [N-1:0] a_out, a_if.sink i_intf_sink[N-1:0] ); generate for (genvar i=0; i < N;i++) begin assign a_out[i] = i_intf_sink[i].long_name; end endgenerate endmodule module t ( clk ); input clk; logic [N-1:0] a_in; logic [N-1:0] a_out; logic [N-1:0] ack_out; a_if #(.PARAM(1)) tl_intf [N-1:0] (); intf_source source(a_in, tl_intf); intf_sink sink(a_out, tl_intf); initial a_in = '0; initial ack_out = '0; always @(posedge clk) begin a_in <= a_in + { {N-1 {1'b0}}, 1'b1 }; ack_out <= ack_out + { {N-1 {1'b0}}, 1'b1 }; if (ack_out != a_out) begin $stop; end if (& a_in) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.044/test_regress/t/t_nba_struct_array.py0000755000542200017500000000075715125463617023354 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(check_finished=True) test.passes() verilator-5.044/test_regress/t/t_covergroup_args.py0000755000542200017500000000070615125463617023213 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.044/test_regress/t/t_param_default_override.v0000644000542200017500000000301315125463617024313 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Josse Van Delm. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off WIDTH module m2 #(parameter int N = 4) (input [N-1:0] i0, i1, input s, output [N-1:0] y); assign y = s ? i1 : i0; endmodule module m4 #(parameter int N = 4) (input [N-1:0] i0, i1, i2, i3, input [1:0] S, output [N-1:0] y); wire [N-1:0] o_low, o_high; // See issue #4920 - use of m4 without parameter overrides // caused the other use of m4(#(6)) to irop the #(N) below m2 #(N) lowm( .i0(i0), .i1(i1), .s(S[0]), .y(o_low)); m2 #(N) highm( .i0(i2), .i1(i3), .s(S[0]), .y(o_high)); m2 #(N) finalm( .i0(o_low), .i1(o_high), .s(S[1]), .y(y)); endmodule module m8 #(parameter int N = 4) (input [N-1:0] i0, i1, i2, i3, i4, i5, i6, i7, input [2:0] S, output [N-1:0] y); wire [N-1:0] o_low, o_high; m4 #(N) lowm(.i0(i0), .i1(i1), .i2(i2), .i3(i3), .S(S[1:0]), .y(o_low)); m4 #(N) highm(.i0(i4), .i1(i5), .i2(i6), .i3(i7), .S(S[1:0]), .y(o_high)); m2 #(N) finalm(.i0(o_low), .i1(o_high), .s(S[2]), .y(y)); endmodule module t (); reg [5:0] i0, i1, i2, i3; reg [1:0] S; wire [5:0] Y; m4 #(6) iut(.i0(i0), .i1(i1), .i2(i2), .i3(i3), .S(S), .y(Y)); initial begin i0 = 6'b000000; i1 = 6'b000001; i2 = 6'b000010; i3 = 6'b000100; S = 2'b00; #10; S = 2'b01; #10; $write("*-* All Finished *-*\n"); end endmodule verilator-5.044/test_regress/t/t_typedef_iface_typedef2.py0000755000542200017500000000077115125463617024377 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_queue.v0000644000542200017500000001743315125463617020747 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; integer i; typedef int q_t[$]; function void set_val(ref int lhs, input int rhs); lhs = rhs; endfunction initial begin q_t iq; iq.push_back(42); // Resize via [] set_val(iq[0], 9000); `checkh(iq.size(), 1); `checks(iq[0], 9000); iq[1]++; `checkh(iq.size(), 2); `checks(iq[1], 1); iq[1000] = 1000; `checkh(iq.size(), 2); `checks(iq[1000], 0); end always @ (posedge clk) begin cyc <= cyc + 1; begin // Very simple test using bit bit q[$]; bit x; `checkh($left(q), 0); `checkh($right(q), -1); `checkh($increment(q), -1); `checkh($low(q), 0); `checkh($high(q), -1); `checkh($size(q), 0); `checkh($dimensions(q), 1); // $bits is unsupported in several other simulators, see bug1646 // Unsup: `checkh($bits(q), 0); q.push_back(1'b1); `checkh($left(q), 0); `checkh($right(q), 0); `checkh($increment(q), -1); `checkh($low(q), 0); `checkh($high(q), 0); `checkh($size(q), 1); `checkh($dimensions(q), 1); // Unsup: `checkh($bits(q), 2); `checkh(q.size(), 1); q.push_back(1'b1); q.push_back(1'b0); q.push_back(1'b1); `checkh($left(q), 0); `checkh($right(q), 3); `checkh($low(q), 0); `checkh($high(q), 3); `checkh($size(q), 4); // Unsup: `checkh($bits(q), 4); `checkh(q.size(), 4); x = q.pop_back(); `checkh(x, 1'b1); `checkh($left(q), 0); `checkh($right(q), 2); `checkh($low(q), 0); `checkh($high(q), 2); `checkh($size(q), 3); // sure those are working now.. x = q.pop_front(); `checkh(x, 1'b1); x = q.pop_front(); `checkh(x, 1'b1); x = q.pop_front(); `checkh(x, 1'b0); `checkh(q.size(), 0); end begin // Simple test using integer typedef bit [3:0] nibble_t; nibble_t q[$]; nibble_t v; `checkh($left(q), 0); `checkh($right(q), -1); `checkh($increment(q), -1); `checkh($low(q), 0); `checkh($high(q), -1); `checkh($size(q), 0); `checkh($dimensions(q), 2); i = q.size(); `checkh(i, 0); q.push_back(4'd1); // 1 q.push_front(4'd2); // 2 1 q.push_back(4'd3); // 2 1 3 i = q.size; `checkh(i, 3); // Also checks no parens end begin // Strings string q[$]; string p[$:3]; string v; int j; // Empty queue checks `checkh($left(q), 0); `checkh($right(q), -1); `checkh($increment(q), -1); `checkh($low(q), 0); `checkh($high(q), -1); `checkh($size(q), 0); `checkh($dimensions(q), 2); //Unsup: `checkh($bits(q), 0); q.push_front("f1"); //Unsup: `checkh($bits(q), 16); q.push_back("b1"); q.push_front("f2"); q.push_back("b2"); i = q.size(); `checkh(i, 4); v = q[0]; `checks(v, "f2"); v = q[1]; `checks(v, "f1"); v = q[2]; `checks(v, "b1"); v = q[3]; `checks(v, "b2"); v = q[4]; `checks(v, ""); //Unsup: `checkh(q[$], "b2"); `checkp(q, "'{\"f2\", \"f1\", \"b1\", \"b2\"}"); `checkp(p, "'{}"); //Unsup: q.delete(1); //Unsup: v = q[1]; `checks(v, "b1"); //Unsup: q.insert(0, "ins0"); //Unsup: q.insert(3, "ins3"); //v = q[0]; `checks(v, "ins0"); //v = q[3]; `checks(v, "ins3"); j = 0; foreach (q[i]) begin j++; v = q[i]; if (i == 0) `checks(v, "f2"); if (i == 1) `checks(v, "f1"); if (i == 2) `checks(v, "b1"); if (i == 3) `checks(v, "b2"); end `checkh(j,4); q.pop_front(); v = q.pop_front(); `checks(v, "f1"); v = q.pop_back(); `checks(v, "b2"); v = q.pop_back(); `checks(v, "b1"); i = q.size(); `checkh(i, 0); // Empty queue, this should be 0 foreach (q[i]) begin j++; end `checkh(j,4); q.push_front("non-empty"); i = q.size(); `checkh(i, 1); q.delete(); i = q.size(); `checkh(i, 0); v = q.pop_front(); `checks(v, ""); // Was empty, optional warning v = q.pop_back(); `checks(v, ""); // Was empty, optional warning // Conversion of insert/delete with zero to operator q.push_front("front"); q.insert(0, "newfront"); i = q.size(); `checkh(i, 2); q.delete(0); i = q.size(); `checkh(i, 1); `checks(q[0], "front"); //Unsup: `checks(q[$], "front"); // Resize via [] q[0] = "long"; `checkh(q.size(), 1); `checks(q[0], "long"); end // Append to queue of queues using [] begin int q[$][$]; q[0][0] = 1; `checkh(q.size(), 1); `checkh(q[0].size(), 1); `checks(q[0][0], 1); end // Do not append with [] if used as index begin int p[$]; int q[$]; q[p[0]] = 1; `checkh(p.size(), 0); `checkh(q.size(), 1); `checks(q[0], 1); end begin typedef struct packed { bit [7:0] opcode; bit [23:0] addr; } instruction; // named structure type instruction q[$]; `checkh($dimensions(q), 2); //Unsup: `checkh($bits(q), 0); end // testing a wide queue begin typedef struct packed { bit [7:0] opcode; bit [23:0] addr; bit [127:0] data; } instructionW; // named structure type instructionW inst_push; instructionW inst_pop; instructionW q[$]; `checkh($dimensions(q), 2); `checkh(q[0].opcode, 0); `checkh(q[0].addr, 0); `checkh(q[0].data, 0); inst_push.opcode = 1; inst_push.addr = 42; inst_push.data = {4{32'hdeadbeef}}; q.push_back(inst_push); `checkh(q[0].opcode, 1); `checkh(q[0].addr, 42); `checkh(q[0].data, {4{32'hdeadbeef}}); inst_pop = q.pop_front(); `checkh(inst_pop.opcode, 1); `checkh(inst_pop.addr, 42); `checkh(inst_pop.data, {4{32'hdeadbeef}}); `checkh(q.size(), 0); `checkh(q[0].opcode, 0); `checkh(q[0].addr, 0); `checkh(q[0].data, 0); end /* Unsup: begin int q[4][$]; q[0].push_back(0); q[0].push_back(1); q[1].push_back(2); q[2].push_back(3); end */ // See t_queue_unsup_bad for more unsupported stuff $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_assert_ctl_immediate_noinl.py0000755000542200017500000000130015125463617025353 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t_assert_ctl_immediate.v" test.golden_filename = "t/t_assert_ctl_immediate.out" test.compile(verilator_flags2=['--assert --timing --fno-inline']) test.execute(all_run_flags=["+verilator+error+limit+100"], expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_gate_inline_wide_exclude_multiple.v0000644000542200017500000000137515125463617026533 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 localparam N = 256; // Wider than expand limit. module t( input wire [N-1:0] i, output logic [N-1:0] o_multiple1, output logic [N-1:0] o_multiple2, output wire [N-1:0] o ); // Exclude from inline wide expressions referenced multiple times. wire [N-1:0] wide_multiple_assigns = N >> i; wire [N-1:0] wide = N << i; for (genvar n = 0; n < N - 1; ++n) begin assign o[n] = i[N-1-n] | wide[N-1-n]; end assign o_multiple1 = wide_multiple_assigns | i + 1; assign o_multiple2 = wide_multiple_assigns | i + 2; endmodule verilator-5.044/test_regress/t/t_dpi_context.py0000755000542200017500000000103215125463617022315 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["t/t_dpi_context_c.cpp", "--debug", "-no-dump-tree"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_class_param_extends3.py0000755000542200017500000000073415125463617024107 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_pp_recursedef_bad.py0000755000542200017500000000076315125463617023443 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_enum_bad_value.v0000644000542200017500000000100715125463617022557 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(); enum bit signed [3:0] {OK1 = -1} ok1_t; // As is signed, loss of 1 bits is ok per IEEE enum bit signed [3:0] {OK2 = 3} ok2_t; typedef enum [2:0] { VALUE_BAD1 = 8 } enum_t; enum bit [4:0] {BAD2[4] = 100} bad2; enum logic [3:0] {BAD3 = 5'bxxxxx} bad3; initial $stop; endmodule verilator-5.044/test_regress/t/t_interface_gen7.v0000644000542200017500000000330115125463617022470 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 // bug998 interface intf #(parameter PARAM = 0) (); /* verilator lint_off MULTIDRIVEN */ logic val; /* verilator lint_on MULTIDRIVEN */ function integer func (); return 5; endfunction endinterface module t1(intf mod_intf); initial begin $display("%m %d", mod_intf.val); end endmodule module t(); intf #(.PARAM(1)) my_intf [1:0] (); generate genvar the_genvar; begin : ia for (the_genvar = 0; the_genvar < 2; the_genvar++) begin : TestIf begin assign my_intf[the_genvar].val = '1; t1 t (.mod_intf(my_intf[the_genvar])); end end end endgenerate generate genvar the_second_genvar; begin : ib intf #(.PARAM(1)) my_intf [1:0] (); for (the_second_genvar = 0; the_second_genvar < 2; the_second_genvar++) begin : TestIf begin assign my_intf[the_second_genvar].val = '1; t1 t (.mod_intf(my_intf[the_second_genvar])); end end end endgenerate generate genvar the_third_genvar; begin : ic for (the_third_genvar = 0; the_third_genvar < 2; the_third_genvar++) begin : TestIf begin intf #(.PARAM(1)) my_intf [1:0] (); assign my_intf[the_third_genvar].val = '1; t1 t (.mod_intf(my_intf[the_third_genvar])); end end end endgenerate initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_struct_unpacked_array.v0000644000542200017500000000153415125463617024212 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef struct { logic a; } Data_t; module t (/*AUTOARG*/ clk ); input clk; int cyc = 0; localparam int SIZE = 20; reg[$clog2(SIZE)-1 : 0] ptr; Data_t buffer[SIZE]; Data_t out; reg out1; always_ff @( posedge clk ) begin int i; cyc <= cyc + 1; if (cyc == 0) begin for (i=0;i= 0); | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.044/test_regress/t/t_randomize_rand_mode.py0000755000542200017500000000073415125463617024005 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_param_type_cmp.v0000644000542200017500000000214415125463617022614 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (); logic [2:0] a; logic [2:0] b; logic signed_out; logic unsigned_out; cmp #(.element_type(logic signed [2:0])) signed_cmp (.a(a), .b(b), .c(signed_out)); cmp #(.element_type(logic [2:0])) unsigned_cmp (.a(a), .b(b), .c(unsigned_out)); initial a = 3'b001; initial b = 3'b111; initial begin #1; if (signed_out !== 1'b0) begin $display("%%Error: bad signed comparison %b < %b: got=%d exp=%d", a, b, signed_out, 1'b0); $stop; end if (unsigned_out !== 1'b1) begin $display("%%Error: bad unsigned comparison %b < %b: got=%d exp=%d", a, b, unsigned_out, 1'b1); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule module cmp #( parameter type element_type = logic ) ( input element_type a, input element_type b, output logic c ); assign c = a < b; endmodule verilator-5.044/test_regress/t/t_lint_blkseq_bad.py0000755000542200017500000000107515125463617023121 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["-Wwarn-BLKSEQ -Wwarn-COMBDLY"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_real_out_of_bounds.v0000644000542200017500000000160715125463617023467 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on module t; class Cls; function void m_uvm_execute_field_op(); real sa_real[3]; string s; // 5 doesn't match array size of 3 for (int i = 0; i < 5; ++i) begin s = $sformatf("%g", sa_real[i]); `checks(s, "0"); s = $sformatf("%p", sa_real[i]); `checks(s, "0"); end endfunction endclass initial begin Cls c; c = new; c.m_uvm_execute_field_op(); $finish; end endmodule verilator-5.044/test_regress/t/t_sdf_annotate_unsup.py0000755000542200017500000000077615125463617023712 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_math_vgen.py0000755000542200017500000000073415125463617021755 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_tri_pull2_bad.v0000644000542200017500000000064515125463617022342 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2010 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; wire A; pullup p1(A); child child(/*AUTOINST*/ // Inouts .A (A)); endmodule module child(inout A); pulldown p2(A); endmodule verilator-5.044/test_regress/t/t_const_bad.v0000644000542200017500000000110615125463617021545 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin if (32'hxxxxxxxx !== 'hx) $stop; if (32'hzzzzzzzz !== 'hz) $stop; if (32'h???????? !== 'h?) $stop; if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop; if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop; if (68'h?_????????_???????? !== 'd?) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_langext_2_bad.py0000755000542200017500000000116115125463617022471 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_langext_2.v" test.leak_check_disable() # This is a lint only test. test.lint(v_flags2=["+1364-1995ext+v"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_mem_slot.py0000755000542200017500000000112715125463617021621 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename, "--no-timing"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_vlt_timing.v0000644000542200017500000000140315125463617021765 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; event e1; event e2; initial begin int x; // verilator timing_off #1 fork @e1; @e2; join @e1 wait(x == 4) x = #1 8; // verilator timing_on if (x != 8) $stop; if ($time != 0) $stop; @e2; @e1; if ((e1.triggered && e2.triggered) || (!e1.triggered && !e2.triggered)) $stop; if ($time != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end initial #2 ->e1; initial #2 ->e2; initial #3 $stop; // timeout initial #1 @(e1, e2) #1 $stop; // timeout endmodule verilator-5.044/test_regress/t/t_exprstmt_on_lhs_of_nba.py0000755000542200017500000000070615125463617024540 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.044/test_regress/t/t_tri_gate_pmos.py0000755000542200017500000000136115125463617022636 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" test.compile(make_top_shell=False, make_main=False, v_flags2=['+define+T_PMOS'], make_flags=['CPPFLAGS_ADD=-DT_PMOS'], verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.044/test_regress/t/t_inst_recurse2_bad.py0000755000542200017500000000076615125463617023407 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_interface_generic_modport_bad2.out0000755000542200017500000000053115125463617026247 0ustar mahmoudyfreeshell%Error: t/t_interface_generic_modport_bad2.v:17:7: Attempt to drive input-only modport: 'v' : ... note: In instance 't.genericModule' 17 | a.v = 10; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_semaphore_class.v0000644000542200017500000000152115125463617022762 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class semaphore_cls; // Test an implementation similar to what Verilator will do internally int m_keys; function new(int keyCount = 0); m_keys = keyCount; endfunction function void put(int keyCount = 1); m_keys += keyCount; endfunction task get(int keyCount = 1); wait (m_keys >= keyCount); m_keys -= keyCount; endtask function int try_get(int keyCount = 1); if (m_keys >= keyCount) begin m_keys -= keyCount; return 1; end else begin return 0; end endfunction endclass `define SEMAPHORE_T semaphore_cls `include "t_semaphore.v" verilator-5.044/test_regress/t/t_unpacked_concat_bad2.out0000644000542200017500000000147315125463617024173 0ustar mahmoudyfreeshell%Error: t/t_unpacked_concat_bad2.v:20:15: Array initialization has too many elements. 2 elements are expected, but at least 5 elements exist. 20 | s1 = {s0, s2}; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_unpacked_concat_bad2.v:21:23: Array initialization has too many elements. 4 elements are expected, but at least 5 elements exist. 21 | s2 = {s1, s0, s0, s0}; | ^ %Error: t/t_unpacked_concat_bad2.v:23:17: Item is incompatible with the array type. 23 | s2 = {s0, s3}; | ^~ %Error: t/t_unpacked_concat_bad2.v:25:19: Item is incompatible with the array type. 25 | A9_logic = {A3, 4, 5, A3, 6}; | ^~ %Error: Exiting due to verilator-5.044/test_regress/t/t_savable_open_bad.out0000644000542200017500000000037315125463617023424 0ustar mahmoudyfreeshellModel width = 10 Restoring model from 'obj_vlt/t_savable_open_bad/saved.vltsv' %Error: obj_vlt/t_savable_open_bad/saved.vltsv:0: Can't deserialize; file has wrong header signature, or file not found: obj_vlt/t_savable_open_bad/saved.vltsv Aborting... verilator-5.044/test_regress/t/t_config_libmap.v0000644000542200017500000000057715125463617022415 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; m1 u_1(); m2 u_2(); m3 u_3(); x4 u_4(); m5 u_5(); other u_o(); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_net_dtype_bad.v0000644000542200017500000000143415125463617022416 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; endclass module t; typedef real real_t; typedef struct packed { bit m_bit; } bad_t; typedef struct { logic m_bit; } ok_unpk_t; typedef struct packed { logic m_bit; } ok_t; wire real_t bad_real; // <--- Error - bad net type wire Cls bad_class; // <--- Error - bad net type wire string bad_string; // <--- Error - bad net type wire bit bad_bit; // <--- Error - bad net type wire bad_t bad_struct; // <--- Error - bad net type wire ok_unpk_t ok_unpk_struct; wire ok_t ok_struct; // Ok initial $stop; endmodule verilator-5.044/test_regress/t/t_timing_sched_nba.v0000644000542200017500000000243015125463617023067 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; bit clk1 = 0; assign #3 clk1 = ~clk1; bit clk2 = 0; assign #11 clk2 = ~clk2; int a1 = 0; int b1 = 0; always @(posedge clk1) #4 a1 <= a1 + 1; always @(posedge clk1) @(posedge clk2) b1 <= b1 + 1; int a2 = 0; always_comb begin // verilator lint_off MULTIDRIVEN a2 = a1 << 1; // verilator lint_on MULTIDRIVEN `ifdef TEST_VERBOSE $display("[%0t] a2 = %0d", $time, a2); `endif end int b2 = 0; always_comb begin // verilator lint_off MULTIDRIVEN b2 = b1 << 2; // verilator lint_on MULTIDRIVEN `ifdef TEST_VERBOSE $display("[%0t] b2 = %0d", $time, b2); `endif end always @(posedge clk1) #5 if (a2 != a1 << 1) $stop; always @(posedge clk2) #1 if (b2 != b1 << 2) $stop; initial #78 begin `ifdef TEST_VERBOSE $display("a1=%0d, b1=%0d, a2=%0d, b2=%0d", a1, b1, a2, b2); `endif if (a1 != 12) $stop; if (b1 != 4) $stop; if (a2 != a1 << 1) $stop; if (b2 != b1 << 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_runflag_errorlimit_bad.out0000644000542200017500000000057615125463617024701 0ustar mahmoudyfreeshell[0] %Error: t_runflag_errorlimit_bad.v:9: Assertion failed in top.t: One -Info: t/t_runflag_errorlimit_bad.v:9: Verilog $stop, ignored due to +verilator+error+limit [0] %Error: t_runflag_errorlimit_bad.v:10: Assertion failed in top.t: Two [0] %Error: t_runflag_errorlimit_bad.v:11: Assertion failed in top.t: Three %Error: t/t_runflag_errorlimit_bad.v:11: Verilog $stop Aborting... verilator-5.044/test_regress/t/t_vlcov_opt_user.py0000755000542200017500000000133615125463617023055 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--write-info", test.obj_dir + "/coverage.info", "--filter-type user", "t/t_vlcov_data_f.dat" ], verilator_run=True) test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") test.passes() verilator-5.044/test_regress/t/t_timing_func_fork.py0000755000542200017500000000077015125463617023330 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary -Wno-UNOPTFLAT"]) test.passes() verilator-5.044/test_regress/t/t_flag_names.py0000755000542200017500000000104115125463617022071 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--mod-prefix modPrefix --top-module t --l2-name l2Name"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_lparam_assign_iface_array_typedef.py0000755000542200017500000000077115125463617026673 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_process_always.py0000755000542200017500000000077115125463617023044 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_wrapper_context__trace1.vcd.out0000644000542200017500000000215015125463617025550 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top0 $end $var wire 1 # clk $end $var wire 1 $ rst $end $var wire 32 % trace_number [31:0] $end $var wire 1 & stop $end $var wire 32 ' counter [31:0] $end $var wire 1 ( done_o $end $scope module top $end $var wire 1 # clk $end $var wire 1 $ rst $end $var wire 32 % trace_number [31:0] $end $var wire 1 & stop $end $var wire 32 ' counter [31:0] $end $var wire 1 ( done_o $end $upscope $end $upscope $end $enddefinitions $end #0 0# 1$ b00000000000000000000000000000001 % 0& b00000000000000000000000000000000 ' 0( #1 1# #2 0# 0$ #3 1# b00000000000000000000000000000001 ' #4 0# #5 1# b00000000000000000000000000000010 ' #6 0# #7 1# b00000000000000000000000000000011 ' #8 0# #9 1# b00000000000000000000000000000100 ' #10 0# #11 1# b00000000000000000000000000000101 ' #12 0# #13 1# b00000000000000000000000000000110 ' #14 0# #15 1# b00000000000000000000000000000111 ' #16 0# #17 1# b00000000000000000000000000001000 ' #18 0# #19 1# b00000000000000000000000000001001 ' #20 0# #21 1# b00000000000000000000000000001010 ' 1( verilator-5.044/test_regress/t/t_xml_tag.py0000755000542200017500000000133615125463617021437 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') out_filename = test.obj_dir + "/V" + test.name + ".xml" test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only'], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.files_identical(out_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_vpi_module_empty.py0000755000542200017500000000124515125463617023364 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile( make_top_shell=False, make_main=False, make_pli=True, iv_flags2=["-g2005-sv"], verilator_flags2=["+define+USE_DOLLAR_C32 --exe --vpi --no-l2name", test.pli_filename]) test.execute(use_libvpi=True) test.passes() verilator-5.044/test_regress/t/t_runflag_errorlimit_fatal_bad.v0000644000542200017500000000066415125463617025504 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $error("One"); $fatal; $error("Two"); $error("Three"); $error("Four"); $error("Five"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_lint_latch_bad.py0000755000542200017500000000107415125463617022732 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["-Wwarn-style -Wno-DECLFILENAME"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_inside_assoc_unsup.py0000755000542200017500000000076615125463617023707 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_emit_constw.py0000755000542200017500000000077515125463617022345 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--fno-expand']) test.execute() test.passes() verilator-5.044/test_regress/t/t_case_unique_many.py0000755000542200017500000000077115125463617023333 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--assert"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_randomize_method_with_bad.out0000644000542200017500000000055515125463617025353 0ustar mahmoudyfreeshell%Error: t/t_randomize_method_with_bad.v:18:42: Can't find definition of task/function: 'in_mod_function' 18 | int res = foo.randomize() with { v < in_mod_function(); }; | ^~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_order_blkloopinit_bad.v0000644000542200017500000000122215125463617024137 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test of select from constant // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off MULTIDRIVEN module t (/*AUTOARG*/ // Outputs o, // Inputs clk ); input clk; output int o; localparam SIZE = 65536; // Unsupported case 1: Array NBA to compund type class C; endclass C array2[SIZE]; always @ (negedge clk) begin o <= int'(array2[1] == null); for (int i=0; i b) ? a : b; endfunction function automatic integer log2; input integer value; value = value >> 1; for (log2 = 0; value > 0; log2 = log2 + 1) value = value >> 1; endfunction function automatic integer ceil_log2; input integer value; value = value - 1; for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1) value = value >> 1; endfunction endpackage module sub(); import defs::*; parameter RAND_NUM_MAX = ""; localparam DATA_RANGE = RAND_NUM_MAX + 1; localparam DATA_WIDTH = ceil_log2(DATA_RANGE); localparam WIDTH = max(4, ceil_log2(DATA_RANGE + 1)); endmodule module t; import defs::*; parameter WHICH = 0; parameter MAX_COUNT = 10; localparam MAX_EXPONENT = log2(MAX_COUNT); localparam EXPONENT_WIDTH = ceil_log2(MAX_EXPONENT + 1); generate if (WHICH == 1) begin : which_true sub sub_true(); defparam sub_true.RAND_NUM_MAX = MAX_EXPONENT; end else begin : which_false sub sub_false(); defparam sub_false.RAND_NUM_MAX = MAX_COUNT; end endgenerate endmodule verilator-5.044/test_regress/t/t_case_nest.v0000644000542200017500000001056415125463617021565 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc = 0; reg [63:0] crc; reg [63:0] sum; reg out1; sub sub (.in(crc[23:0]), .out1(out1)); always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x sum=%x out=%x\n", $time, cyc, crc, sum, out1); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {63'h0,out1}; if (cyc==1) begin // Setup crc <= 64'h00000000_00000097; sum <= 64'h0; end else if (cyc==90) begin if (sum !== 64'h2e5cb972eb02b8a0) $stop; end else if (cyc==91) begin end else if (cyc==92) begin end else if (cyc==93) begin end else if (cyc==94) begin end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub (/*AUTOARG*/ // Outputs out1, // Inputs in ); input [23:0] in; output reg [0:0] out1; // Note this tests a vector of 1 bit, which is different from a non-arrayed signal parameter [1023:0] RANDOM = 1024'b101011010100011011100111101001000000101000001111111111100110000110011011010110011101000100110000110101111101000111100100010111001001110001010101000111000100010000010011100001100011110110110000101100011111000110111110010110011000011111111010101110001101010010001111110111100000110111101100110101110001110110000010000110101110111001111001100001101110001011100111001001110101001010000110101010100101111000010000010110100101110100110000110110101000100011101111100011000110011001100010010011001101100100101110010100110101001110011111110010000111001111000010001101100101101110111110001000010110010011100101001011111110011010110111110000110010011110001110110011010011010110011011111001110100010110100011100001011000101111000010011111010111001110110011101110101011111001100011000101000001000100111110010100111011101010101011001101000100000101111110010011010011010001111010001110000110010100011110110011001010000011001010010110111101010010011111111010001000101100010100100010011001100110000111111000001000000001001111101110000100101; always @* begin casez (in[17:16]) 2'b00: casez (in[2:0]) 3'h0: out1[0] = in[0]^RANDOM[0]; 3'h1: out1[0] = in[0]^RANDOM[1]; 3'h2: out1[0] = in[0]^RANDOM[2]; 3'h3: out1[0] = in[0]^RANDOM[3]; 3'h4: out1[0] = in[0]^RANDOM[4]; 3'h5: out1[0] = in[0]^RANDOM[5]; 3'h6: out1[0] = in[0]^RANDOM[6]; 3'h7: out1[0] = in[0]^RANDOM[7]; endcase 2'b01: casez (in[2:0]) 3'h0: out1[0] = RANDOM[10]; 3'h1: out1[0] = RANDOM[11]; 3'h2: out1[0] = RANDOM[12]; 3'h3: out1[0] = RANDOM[13]; 3'h4: out1[0] = RANDOM[14]; 3'h5: out1[0] = RANDOM[15]; 3'h6: out1[0] = RANDOM[16]; 3'h7: out1[0] = RANDOM[17]; endcase 2'b1?: casez (in[4]) 1'b1: casez (in[2:0]) 3'h0: out1[0] = RANDOM[20]; 3'h1: out1[0] = RANDOM[21]; 3'h2: out1[0] = RANDOM[22]; 3'h3: out1[0] = RANDOM[23]; 3'h4: out1[0] = RANDOM[24]; 3'h5: out1[0] = RANDOM[25]; 3'h6: out1[0] = RANDOM[26]; 3'h7: out1[0] = RANDOM[27]; endcase 1'b0: casez (in[2:0]) 3'h0: out1[0] = RANDOM[30]; 3'h1: out1[0] = RANDOM[31]; 3'h2: out1[0] = RANDOM[32]; 3'h3: out1[0] = RANDOM[33]; 3'h4: out1[0] = RANDOM[34]; 3'h5: out1[0] = RANDOM[35]; 3'h6: out1[0] = RANDOM[36]; 3'h7: out1[0] = RANDOM[37]; endcase endcase endcase end endmodule verilator-5.044/test_regress/t/t_lparam_assign_iface_typedef_nested_modules2.py0000755000542200017500000000077115125463617030651 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_math_shortcircuit_assocsel.py0000755000542200017500000000073415125463617025434 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_inst_tree_inl0_pub0.py0000755000542200017500000000272315125463617023651 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_inst_tree.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(v_flags2=["--no-json-edit-nums", test.t_dir + "/" + test.name + ".vlt"]) if test.vlt_all: test.file_grep(out_filename, r'{"type":"MODULE","name":"l1",.*"loc":"\w,56:[^"]*",.*"origName":"l1"') test.file_grep(out_filename, r'{"type":"MODULE","name":"l2",.*"loc":"\w,62:[^"]*",.*"origName":"l2"') test.file_grep(out_filename, r'{"type":"MODULE","name":"l3",.*"loc":"\w,69:[^"]*",.*"origName":"l3"') test.file_grep(out_filename, r'{"type":"MODULE","name":"l4",.*"loc":"\w,76:[^"]*",.*"origName":"l4"') test.file_grep(out_filename, r'{"type":"MODULE","name":"l5__P1",.*"loc":"\w,83:[^"]*",.*"origName":"l5"') test.file_grep(out_filename, r'{"type":"MODULE","name":"l5__P2",.*"loc":"\w,83:[^"]*",.*"origName":"l5"') test.execute() test.file_grep(test.run_log_filename, r"\] (%m|.*t\.ps): Clocked") test.passes() verilator-5.044/test_regress/t/t_stream_dynamic.v0000644000542200017500000001410415125463617022612 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); typedef enum bit [5:0] { A = 6'b111000, B = 6,b111111 } enum_t; module t; task test1; bit arr[]; bit [1:0] arr2[$]; bit [5:0] arr6[$]; bit [5:0] bit6; bit [5:0] ans; bit [3:0] arr4[]; bit [7:0] arr8[]; bit [63:0] arr64[]; bit [159:0] arr160[]; bit [63:0] bit64; bit [99:0] bit100; bit [319:0] bit320; enum_t ans_enum; bit6 = 6'b111000; arr4 = '{25{4'b1000}}; arr8 = '{8{8'b00110011}}; arr64 = '{5{64'h0123456789abcdef}}; arr160 = '{2{160'h0123456789abcdef0123456789abcdef01234567}}; { >> bit {arr}} = bit6; `checkp(arr, "'{'h1, 'h1, 'h1, 'h0, 'h0, 'h0}"); ans = { >> bit {arr} }; `checkh(ans, bit6); ans_enum = enum_t'({ >> bit {arr} }); `checkh(ans_enum, bit6); { << bit {arr}} = bit6; `checkp(arr, "'{'h0, 'h0, 'h0, 'h1, 'h1, 'h1}"); ans = { << bit {arr} }; `checkh(ans, bit6); ans_enum = enum_t'({ << bit {arr} }); `checkh(ans_enum, bit6); `ifdef VERILATOR // This set flags errors on other simulators { >> bit[1:0] {arr2}} = bit6; `checkp(arr2, "'{'h3, 'h2, 'h0}"); ans = { >> bit[1:0] {arr2} }; `checkh(ans, bit6); ans_enum = enum_t'({ >> bit[1:0] {arr2} }); `checkh(ans_enum, bit6); { << bit[1:0] {arr2}} = bit6; `checkp(arr2, "'{'h0, 'h2, 'h3}"); ans = { << bit[1:0] {arr2} }; `checkh(ans, bit6); ans_enum = enum_t'({ << bit[1:0] {arr2} }); `checkh(ans_enum, bit6); { >> bit [5:0] {arr6} } = bit6; `checkp(arr6, "'{'h38}"); ans = { >> bit[5:0] {arr6} }; `checkh(ans, bit6); ans_enum = enum_t'({ >> bit[5:0] {arr6} }); `checkh(ans_enum, bit6); { << bit [5:0] {arr6} } = bit6; `checkp(arr6, "'{'h38}"); ans = { << bit[5:0] {arr6} }; `checkh(ans, bit6); ans_enum = enum_t'({ << bit[5:0] {arr6} }); `checkh(ans_enum, bit6); `endif bit64 = { >> bit {arr8} }; `checkh(bit64[7:0], 8'b00110011); bit64 = { << bit {arr8} }; `checkh(bit64[7:0], 8'b11001100); { >> bit {arr8} } = bit64; `checkh(arr8[0], 8'b11001100); { << bit {arr8} } = bit64; `checkh(arr8[0], 8'b00110011); bit100 = { >> bit {arr4} }; `checkh(bit100[3:0], 4'b1000); bit100 = { << bit {arr4} }; `checkh(bit100[3:0], 4'b0001); { >> bit {arr4} } = bit100; `checkh(arr4[0], 4'b0001); { << bit {arr4} } = bit100; `checkh(arr4[0], 4'b1000); bit320 = { >> byte {arr64} }; `checkh(bit320[63:0], 64'h0123456789abcdef); bit320 = { << byte {arr64} }; `checkh(bit320[63:0], 64'hefcdab8967452301); { >> byte {arr64} } = bit320; `checkh(arr64[0], 64'hefcdab8967452301); { << byte {arr64} } = bit320; `checkh(arr64[0], 64'h0123456789abcdef); { >> bit {arr64} } = bit64; `checkh(arr64[0], 64'hcccccccccccccccc); { << bit {arr64} } = bit64; `checkh(arr64[0], 64'h3333333333333333); bit64 = { >> bit {arr64} }; `checkh(bit64, 64'h3333333333333333); bit64 = { << bit {arr64} }; `checkh(bit64, 64'hcccccccccccccccc); bit320 = { >> byte {arr160} }; `checkh(bit320[159:0], 160'h0123456789abcdef0123456789abcdef01234567); bit320 = { << byte {arr160} }; `checkh(bit320[159:0], 160'h67452301efcdab8967452301efcdab8967452301); { >> byte {arr160} } = bit320; `checkh(arr160[0], 160'h67452301efcdab8967452301efcdab8967452301); { << byte {arr160} } = bit320; `checkh(arr160[0], 160'h0123456789abcdef0123456789abcdef01234567); endtask task test2; byte unpack [8]; // [0] is left-most for purposes of streaming bit [63:0] bits; // [63] is left-most for purposes of streaming longint word; // [63] is left-most for purposes of streaming // Using packed bits $display("Test2"); bits = {8'hfa, 8'hde, 8'hca, 8'hfe, 8'hde, 8'had, 8'hbe, 8'hef}; word = {>>{bits}}; `checkh(word, 64'hfadecafedeadbeef); word = {<<8{bits}}; `checkh(word, 64'hefbeaddefecadefa); // Using byte unpacked array unpack = '{8'hfa, 8'hde, 8'hca, 8'hfe, 8'hde, 8'had, 8'hbe, 8'hef}; `checkh(unpack[0], 8'hfa); `checkh(unpack[7], 8'hef); word = {>>{unpack}}; `checkh(word, 64'hfadecafedeadbeef); word = {<<8{unpack}}; `checkh(word, 64'hefbeaddefecadefa); endtask task test3; byte dyn8 []; // [0] is left-most for purposes of streaming longint word; // [63] is left-most for purposes of streaming // verilator lint_off ASCRANGE bit [0:63] rbits; // [63] is still left-most for purposes of streaming // verilator lint_on ASCRANGE // Using byte dynamic array dyn8 = new[8]('{8'hfa, 8'hde, 8'hca, 8'hfe, 8'hde, 8'had, 8'hbe, 8'hef}); `checkh(dyn8[0], 8'hfa); `checkh(dyn8[7], 8'hef); word = {>>{dyn8}}; `checkh(word, 64'hfadecafedeadbeef); word = {<<1{dyn8}}; `checkh(word, 64'hf77db57b7f537b5f); word = {<<8{dyn8}}; `checkh(word, 64'hefbeaddefecadefa); rbits = {>>{dyn8}}; `checkh(rbits, 64'hfadecafedeadbeef); rbits = {<<1{dyn8}}; `checkh(rbits, 64'hf77db57b7f537b5f); rbits = {<<8{dyn8}}; `checkh(rbits, 64'hefbeaddefecadefa); endtask initial begin test1(); test2(); test3(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_preproc_ifexpr.v0000644000542200017500000000363515125463617022651 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `begin_keywords "1800-2023" `define ONE `undef ZERO `ifdef ( ONE ) "ok ( ONE )" `endif // Test no spaces around () `ifdef (ZERO) `error "( ZERO )" `endif `ifndef ( ! ONE ) "ok ( ! ONE )" `endif // Test no spaces around () `ifndef (!ZERO) `error "( ! ZERO )" `endif `ifdef ( ! ZERO ) "ok ( ! ZERO )" `endif `ifdef ( ! ONE ) `error "( ! ONE )" `endif `ifdef ( ZERO || ZERO || ONE ) "ok ( ZERO || ZERO || ONE )" `endif `ifdef ( ZERO || ZERO || ZERO ) `error "( ZERO || ZERO || ZERO )" `endif `ifdef ( ONE && ONE && ONE ) "ok ( ONE && ONE && ONE )" `endif `ifdef ( ONE && ONE && ZERO ) `error "( ONE && ONE && ZERO )" `endif // Precedence of && is under || `ifdef ( ZERO && ZERO || ONE ) "ok ( ZERO && ZERO || ONE )" `endif `ifdef ( ONE || ZERO && ZERO ) "ok ( ONE || ZERO && ZERO )" `endif `ifdef ZERO `elsif ( ONE && !( ZERO && ONE ) ) "ok ( ONE && !( ZERO && ONE ) )" `endif `ifdef ( ZERO -> ZERO) "ok ( ZERO -> ZERO)" `endif // Text extra newlines `ifdef ( ZERO -> ONE) "ok ( ZERO -> ONE)" `endif // Text comments `ifdef ( ZERO // Zero -> // Operator ONE) // One "ok ( ZERO -> ONE)" `endif `ifdef ( /*val*/ ZERO /*op*/ -> /*val*/ ONE) "ok ( ZERO -> ONE)" `endif `ifndef ( ONE -> ZERO) "ok ( ONE -> ZERO)" `endif `ifdef ( ONE -> ONE) "ok ( ONE -> ONE)" `endif `ifdef ( ZERO <-> ZERO) "ok ( ZERO <-> ZERO)" `endif `ifndef ( ZERO <-> ONE) "ok ( ZERO <-> ONE)" `endif `ifndef ( ONE <-> ZERO) "ok ( ONE <-> ZERO)" `endif `ifdef ( ONE <-> ONE) "ok ( ONE <-> ONE)" `endif `ifdef (ZERO) "bad" `elsif (ZERO) "bad" `elsif (ONE) "ok " `elsif (ONE) "bad" `endif // Did we end up right? Line: `__LINE__ verilator-5.044/test_regress/t/t_lib_prot_secret.v0000644000542200017500000000661215125463617022777 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module secret #(parameter GATED_CLK = 0) ( input [31:0] accum_in, output wire [31:0] accum_out, input accum_bypass, output [31:0] accum_bypass_out, input s1_in, output logic s1_out, input s1up_in[2], output logic s1up_out[2], input [1:0] s2_in, output logic [1:0] s2_out, input [7:0] s8_in, output logic [7:0] s8_out, input [32:0] s33_in, output logic [32:0] s33_out, input [63:0] s64_in, output logic [63:0] s64_out, input [64:0] s65_in, output logic [64:0] s65_out, input [128:0] s129_in, output logic [128:0] s129_out, input [3:0] [31:0] s4x32_in, output logic [3:0] [31:0] s4x32_out, /*verilator lint_off ASCRANGE*/ input [0:15] s6x16up_in[0:1][2:0], output logic [0:15] s6x16up_out[0:1][2:0], /*verilator lint_on ASCRANGE*/ input [15:0] s8x16up_in[1:0][0:3], output logic [15:0] s8x16up_out[1:0][0:3], input [15:0] s8x16up_3d_in[1:0][0:1][0:1], output logic [15:0] s8x16up_3d_out[1:0][0:1][0:1], input clk_en, input clk); logic [31:0] secret_accum_q = 0; logic [31:0] secret_value = 7; initial $display("created %m"); logic the_clk; generate if (GATED_CLK != 0) begin: yes_gated_clock logic clk_en_latch; /* verilator lint_off COMBDLY */ /* verilator lint_off LATCH */ always_comb if (clk == '0) clk_en_latch <= clk_en; /* verilator lint_on LATCH */ /* verilator lint_on COMBDLY */ assign the_clk = clk & clk_en_latch; end else begin: no_gated_clock assign the_clk = clk; end endgenerate always @(posedge the_clk) begin secret_accum_q <= secret_accum_q + accum_in + secret_value; end // Test combinatorial paths of different sizes always @(*) begin s1_out = s1_in; s1up_out = s1up_in; s2_out = s2_in; s8_out = s8_in; s64_out = s64_in; s65_out = s65_in; s129_out = s129_in; s4x32_out = s4x32_in; end for (genvar i = 0; i < 3; ++i) begin assign s6x16up_out[0][i] = s6x16up_in[0][i]; assign s6x16up_out[1][i] = s6x16up_in[1][i]; end for (genvar i = 0; i < 4; ++i) begin assign s8x16up_out[0][i] = s8x16up_in[0][i]; assign s8x16up_out[1][i] = s8x16up_in[1][i]; end for (genvar i = 0; i < 8; ++i) begin assign s8x16up_3d_out[i[2]][i[1]][i[0]] = s8x16up_3d_in[i[2]][i[1]][i[0]]; end sub sub (.sub_in(s33_in), .sub_out(s33_out)); // Test sequential path assign accum_out = secret_accum_q; // Test mixed combinatorial/sequential path assign accum_bypass_out = accum_bypass ? accum_in : secret_accum_q; final $display("destroying %m"); endmodule module sub ( input [32:0] sub_in, output [32:0] sub_out); /*verilator no_inline_module*/ assign sub_out = sub_in; endmodule verilator-5.044/test_regress/t/t_time_literals.v0000644000542200017500000000170115125463617022447 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `timescale 1ns/1ps module t; time t; // realtime value scaled to timeunit, rounded to timeprecision initial begin // verilator lint_off REALCVT t = 1s; `checkd(t, 64'd1000000000); t = 2ms; `checkd(t, 2000000); t = 1ms; `checkd(t, 1000000); t = 1us; `checkd(t, 1000); t = 1ns; `checkd(t, 1); t = 1ps; `checkd(t, 0); // Below precision t = 1fs; `checkd(t, 0); t = 2.3ps; `checkd(t, 0); t = 2.4us; `checkd(t, 2400); // verilator lint_on REALCVT $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_profcfunc.py0000755000542200017500000000131515125463617021766 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') test.run(cmd=[ "cd " + test.obj_dir + " && " + os.environ["VERILATOR_ROOT"] + "/bin/verilator_profcfunc", test.t_dir + "/t_profcfunc.gprof > profcfuncs.log" ], check_finished=False) test.files_identical(test.obj_dir + "/profcfuncs.log", test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_unopt_combo_isolate.vlt0000644000542200017500000000070715125463617024223 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config isolate_assignments -module "file" -var "b" isolate_assignments -module "file" -task "set_b_d" -var "t_c*" isolate_assignments -module "file" -function "get_31_16" -var "t_crc" isolate_assignments -module "file" -function "get_31_16" verilator-5.044/test_regress/t/t_inst_missing.v0000644000542200017500000000117115125463617022321 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; wire ok = 1'b0; // verilator lint_off UNDRIVEN wire nc; // verilator lint_on UNDRIVEN // verilator lint_off PINNOCONNECT // verilator lint_off PINCONNECTEMPTY sub sub (ok, , nc); // verilator lint_on PINCONNECTEMPTY // verilator lint_on PINNOCONNECT endmodule module sub (input ok, input none, input nc); initial if (ok && none && nc) begin end // No unused warning endmodule verilator-5.044/test_regress/t/t_assert_procedural_clk_bad.py0000755000542200017500000000076315125463617025167 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(expect_filename=test.golden_filename, fails=True) test.passes() verilator-5.044/test_regress/t/t_covergroup_with_sample_zeroargs.v0000644000542200017500000000060615125463617026320 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ module t; covergroup cg0 with function sample (); endgroup cg0 cov = new(); function void run(); cov.sample(); endfunction endmodule verilator-5.044/test_regress/t/t_param_noval_bad.out0000644000542200017500000000402715125463617023265 0ustar mahmoudyfreeshell%Error: t/t_param_noval_bad.v:7:22: Parameter without default value is never given value (IEEE 1800-2023 6.20.1): 'P' : ... note: In instance 't' 7 | module t #(parameter P, parameter type T); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_param_noval_bad.v:7:40: Parameter type without default value is never given value (IEEE 1800-2023 6.20.1): 'T' : ... note: In instance 't' 7 | module t #(parameter P, parameter type T); | ^ %Warning-WIDTHTRUNC: t/t_param_noval_bad.v:10:7: Logical operator GENFOR expects 1 bit on the For Test Condition, but For Test Condition's VARREF 'P' generates 32 bits. : ... note: In instance 't' 10 | for (j=0; P; j++) | ^~~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: t/t_param_noval_bad.v:10:7: Non-genvar used in generate for: 'j' : ... note: In instance 't' 10 | for (j=0; P; j++) | ^~~ %Error: t/t_param_noval_bad.v:10:7: Loop unrolling failed. : ... note: In instance 't' 10 | for (j=0; P; j++) | ^~~ %Error-UNSUPPORTED: t/t_param_noval_bad.v:10:7: Unsupported: Can't unroll generate for; Unable to unroll loop : ... note: In instance 't' 10 | for (j=0; P; j++) | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: t/t_param_noval_bad.v:10:7: For loop doesn't have genvar index, or is malformed : ... note: In instance 't' 10 | for (j=0; P; j++) | ^~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_split_var_issue.py0000755000542200017500000000106615125463617023217 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios("simulator_st") test.compile(verilator_flags2=["--assert", "-fno-localize"]) test.execute(all_run_flags=["+verilator+rand+reset+2"]) test.passes() verilator-5.044/test_regress/t/t_class_const.v0000644000542200017500000000074515125463617022134 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; const int aconst = 10; static const int astatic = 20; endclass module t; initial begin Cls c = new; if (c.aconst !== 10) $stop; if (Cls::astatic !== 20) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_case_call_count.v0000644000542200017500000000212615125463617022732 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Cls; int callCount = 0; int callCount2 = 0; int value = 6; bit[5:0] value2 = 6; function int get(); callCount += 1; return value; endfunction function bit[5:0] get2(); callCount2 += 1; return value2; endfunction function int getPure(); return callCount2; endfunction endclass module t; Cls c; initial begin bit called = 0; c = new; case (c.get()) 4: $stop; 5: $stop; 6: called = 1; 7: $stop; default: $stop; endcase if (!called) $stop; if (c.callCount != 1) $stop; called = 0; case (c.get2()) 4: $stop; 5: $stop; 6: called = 1; 7: $stop; default: $stop; endcase case (c.getPure()) 1:; default: $stop; endcase if (!called) $stop; if (c.callCount2 != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_config_hier.out0000644000542200017500000000133515125463617022433 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_config_hier.v:36:18: Unsupported: hierarchical config rule 36 | instance t.u_1 use work.cfg2 :config; | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_config_hier.v:41:18: Unsupported: hierarchical config rule 41 | instance t.u_1 use cfg2 :config; | ^~~ %Error-UNSUPPORTED: t/t_config_hier.v:46:16: Unsupported: hierarchical config rule 46 | cell work.m1 use work.cfg2 :config; | ^~~ %Error-UNSUPPORTED: t/t_config_hier.v:51:11: Unsupported: hierarchical config rule 51 | cell m1 use cfg2 :config; | ^~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_interface_generic_bad2.out0000755000542200017500000000251515125463617024507 0ustar mahmoudyfreeshell%Error: t/t_interface_generic_bad2.v:15:9: Can't find definition of scope/variable: 'b' 15 | if (b.k != 9) $stop; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_interface_generic_bad2.v:20:3: Cannot find file containing interface: 'inf' 20 | inf inf_inst(); | ^~~ %Error: t/t_interface_generic_bad2.v:21:32: Found definition of 'inf_inst' as a CELL but expected a variable 21 | GenericModule genericModule (inf_inst); | ^~~~~~~~ %Error: t/t_interface_generic_bad2.v:21:32: Expected an interface but 'inf_inst' is not an interface 21 | GenericModule genericModule (inf_inst); | ^~~~~~~~ %Error: t/t_interface_generic_bad2.v:23:5: Dotted reference to instance that refers to missing module/interface: 'inf' 23 | inf_inst.v = 7; | ^~~~~~~~ %Error: t/t_interface_generic_bad2.v:23:14: Can't find definition of 'v' in dotted variable/method: 'inf_inst.v' 23 | inf_inst.v = 7; | ^ %Error: t/t_interface_generic_bad2.v:24:5: Can't find definition of scope/variable: 'inf_inst2' : ... Suggested alternative: 'inf_inst' 24 | inf_inst2.k = 9; | ^~~~~~~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_dpi_imp_gen_c.cpp0000644000542200017500000000221715125463617022706 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 //************************************************************************* #include "svdpi.h" #include #include //====================================================================== // clang-format off #if defined(VERILATOR) # include "Vt_dpi_imp_gen__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif // clang-format on #ifdef NEED_EXTERNS extern "C" { extern void dpi_genvarTest(); } #endif //====================================================================== // Called from our Verilog code to run the tests void dpi_genvarTest() { const char* scopeName = svGetNameFromScope(svGetScope()); printf("scope name : %s\n", scopeName); } verilator-5.044/test_regress/t/t_bitsel_over32.v0000644000542200017500000000207515125463617022301 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(aw_addr, orig_aw_size); typedef logic [63:0] addr_t; typedef logic [7:0][7:0] mst_data_t; logic [127:0] slv_req_i_w_data; input addr_t aw_addr; mst_data_t w_data; input logic [2:0] orig_aw_size; always_comb begin // verilator lint_off WIDTHEXPAND automatic addr_t mst_port_offset = aw_addr[2:0]; automatic addr_t slv_port_offset = aw_addr[3:0]; w_data = '0; for (int b=0; b<16; b++) begin if ((b >= slv_port_offset) && (b - slv_port_offset < (1 << orig_aw_size)) && (b + mst_port_offset - slv_port_offset < 8)) begin automatic addr_t index = b + mst_port_offset - slv_port_offset; // verilator lint_on WIDTHEXPAND // [#][7:0] = [ +: 8] w_data[index] = slv_req_i_w_data[8*b +: 8]; end end end endmodule verilator-5.044/test_regress/t/t_probdist.v0000644000542200017500000000550015125463617021441 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; integer seed; integer r; integer sum; initial begin //======= seed = 1234; r = $dist_chi_square(seed, 5); `checkd(seed, 923940542); `checkd(r, 8); sum = 1; repeat(20) sum += $dist_chi_square(seed, 5); `checkd(sum, 130); sum = 1; repeat(20) sum += $dist_chi_square(seed, -5); `checkd(sum, 1); sum = 1; repeat(20) sum += $dist_chi_square(seed, 2); `checkd(sum, 30); //======= seed = 1234; r = $dist_erlang(seed, 5, 10); `checkd(seed, 1025211431); `checkd(r, 19); sum = 1; repeat(20) sum += $dist_erlang(seed, 5, 10); `checkd(sum, 173); sum = 1; repeat(20) sum += $dist_erlang(seed, 5, -10); `checkd(sum, -241); //======= seed = 1234; r = $dist_exponential(seed, 5); `checkd(seed, 85231147); `checkd(r, 20); sum = 1; repeat(20) sum += $dist_exponential(seed, 5); `checkd(sum, 104); //======= seed = 1234; r = $dist_normal(seed, 5, 10); `checkd(seed, -1570070672); `checkd(r, 4); sum = 1; repeat(20) sum += $dist_normal(seed, 5, 10); `checkd(sum, 114); //======= seed = 1234; r = $dist_poisson(seed, 5); `checkd(seed, 418012337); `checkd(r, 2); sum = 1; repeat(20) sum += $dist_poisson(seed, 5); `checkd(sum, 111); //======= seed = 1234; r = $dist_t(seed, 5); `checkd(seed, -797481412); `checkd(r, 0); sum = 1; repeat(20) sum += $dist_t(seed, 5); `checkd(sum, -2); //======= seed = 1234; r = $dist_uniform(seed, 5, 10); `checkd(seed, 85231147); `checkd(r, 5); sum = 1; repeat(20) sum += $dist_uniform(seed, 5, 10); `checkd(sum, 147); seed = 1234; r = $dist_uniform(seed, 10, 5); `checkd(r, 10); sum = 1; repeat(20) sum += $dist_uniform(seed, -2147483648, -20); `checkd(sum, 1768955681); sum = 1; repeat(20) sum += $dist_uniform(seed, 20, 2147483647); `checkd(sum, 1534326415); sum = 1; repeat(20) sum += $dist_uniform(seed, -2147483648, 2147483647); `checkd(sum, 1394525852); seed = 0; sum = 1; repeat(20) sum += $dist_uniform(seed, -10, 100); `checkd(seed, 1003647461); `checkd(sum, 896); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_lint_sideeffect_bad.v0000644000542200017500000000075715125463617023561 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 Krzysztof Boronski. // SPDX-License-Identifier: CC0-1.0 int i = 0; function int postincrement_i; return i++; endfunction module t; initial begin int arr [3][3] = {{1, 2, 3}, {4, 5, 6}, {7, 8, 9}}; i = 0; arr[postincrement_i()][postincrement_i()]++; $display("Value: %d", i); end endmodule verilator-5.044/test_regress/t/t_func_regfirst.py0000755000542200017500000000073415125463617022645 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_dpi_result_type.py0000755000542200017500000000244115125463617023215 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if test.nc: # For NC, compile twice, first just to generate DPI headers test.compile(nc_flags2=[ "+ncdpiheader+" + test.obj_dir + "/dpi-exp.h", "+ncdpiimpheader+" + test.obj_dir + "/dpi-imp.h" ]) test.compile( v_flags2=["t/" + test.name + ".cpp"], # --no-decoration so .out file doesn't comment on source lines verilator_flags2=["-Wall -Wno-DECLFILENAME --no-decoration"], # NC: Gdd the obj_dir to the C include path nc_flags2=["+ncscargs+-I" + test.obj_dir], # ModelSim: Generate DPI header, add obj_dir to the C include path ms_flags2=["-dpiheader " + test.obj_dir + "/dpi.h", "-ccflags -I" + test.obj_dir]) if test.vlt_all: test.files_identical(test.obj_dir + "/" + test.vm_prefix + "__Dpi.h", "t/" + test.name + "__Dpi.out") test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_initial_edge.py0000755000542200017500000000100115125463617022406 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--x-initial-edge"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_assert_disable_bad.v0000644000542200017500000000130115125463617023400 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc = 0; logic val = 0; always @(posedge clk) begin cyc <= cyc + 1; val = ~val; end property check(int cyc_mod_2, logic expected); @(posedge clk) disable iff (cyc == 0) cyc % 2 == cyc_mod_2 |=> val == expected; endproperty // Test should fail due to duplicated disable iff statements // (IEEE 1800-2012 16.12.1). assert property (disable iff (val == 0) check(1, 1)); endmodule verilator-5.044/test_regress/t/t_parse_sync_bad2.out0000644000542200017500000000234015125463617023212 0ustar mahmoudyfreeshell%Error: t/t_parse_sync_bad2.v:9:15: Can't find typedef/interface: 'unknown' 9 | typedef unknown defu; | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_parse_sync_bad2.v:17:7: Can't find typedef/interface: 'Invalid1' 17 | Invalid1 invalid1; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_parse_sync_bad2.v:18:12: Unsupported: Multiple '::' package/class reference 18 | pkg::cls::defi valid1; | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: t/t_parse_sync_bad2.v:18:17: Can't find typedef/interface: 'defi' 18 | pkg::cls::defi valid1; | ^~~~ %Error-UNSUPPORTED: t/t_parse_sync_bad2.v:19:12: Unsupported: Multiple '::' package/class reference 19 | pkg::cls::defu valid2; | ^~~ %Error: t/t_parse_sync_bad2.v:19:17: Can't find typedef/interface: 'defu' 19 | pkg::cls::defu valid2; | ^~~~ %Error: t/t_parse_sync_bad2.v:20:7: Can't find typedef/interface: 'Invalid2' 20 | Invalid2 invalid2; | ^~~~~~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_func_under.py0000755000542200017500000000073415125463617022135 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_queue_slice.v0000644000542200017500000000740515125463617022124 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); module t; initial begin typedef string q_t[$]; q_t q; string v; int i; int qi[$:5]; int ri[$]; q.push_front("non-empty"); i = q.size(); `checkh(i, 1); `checkp(q, "'{\"non-empty\"}"); q = '{}; i = q.size(); `checkh(i, 0); q = '{"q"}; `checkp(q, "'{\"q\"}"); q = {}; i = q.size(); `checkh(i, 0); q = '{"q", "b", "c", "d", "e", "f"}; if (q[0] !== "q") $stop; `checkp(q, "'{\"q\", \"b\", \"c\", \"d\", \"e\", \"f\"}"); q = {"q", "b", "c", "d", "e", "f"}; `checkp(q, "'{\"q\", \"b\", \"c\", \"d\", \"e\", \"f\"}"); q.delete(1); v = q[1]; `checks(v, "c"); `checkp(q, "'{\"q\", \"c\", \"d\", \"e\", \"f\"}"); q.insert(0, "ins0"); q.insert(2, "ins2"); v = q[0]; `checks(v, "ins0"); v = q[2]; `checks(v, "ins2"); `checkp(q, "'{\"ins0\", \"q\", \"ins2\", \"c\", \"d\", \"e\", \"f\"}"); // Slicing q = '{"q", "b", "c", "d", "e", "f"}; q = q[-1:0]; `checkp(q, "'{\"q\"}"); q = '{"q", "b", "c", "d", "e", "f"}; q = q[2:3]; `checkp(q, "'{\"c\", \"d\"}"); q = '{"q", "b", "c", "d", "e", "f"}; q = q[3:$]; `checkp(q, "'{\"d\", \"e\", \"f\"}"); q = q[$:$]; `checkp(q, "'{\"f\"}"); // Similar using implied notation q = '{"f"}; q = {q, "f1"}; // push_front q = {q, "f2"}; // push_front q = {"b1", q}; // push_back q = {"b2", q}; // push_back `checkp(q, "'{\"b2\", \"b1\", \"f\", \"f1\", \"f2\"}"); q = {q[0], q[2:$]}; // delete element 1 `checkp(q, "'{\"b2\", \"f\", \"f1\", \"f2\"}"); q = {"a", "b"}; q = {q, q}; `checkp(q, "'{\"a\", \"b\", \"a\", \"b\"}"); begin string ai[$] = '{ "Foo", "Bar" }; q = ai; // Copy i = q.size(); `checkh(i, 2); v = q.pop_front(); `checks(v, "Foo"); v = q.pop_front(); `checks(v, "Bar"); q = '{ "BB", "CC" }; // Note '{} not {} v = q.pop_front(); `checks(v, "BB"); v = q.pop_front(); `checks(v, "CC"); q = { "BB", "CC" }; // Note {} not '{} v = q.pop_front(); `checks(v, "BB"); v = q.pop_front(); `checks(v, "CC"); end begin qi.push_back(0); qi.push_back(1); qi.push_back(2); qi.push_back(3); qi.push_back(4); qi.push_back(5); // Assignment to unsized queue from sized queue ri = qi[ 2 : 4 ]; `checkh(ri.size, 3); ri = qi[ 4 : 2 ]; `checkh(ri.size, 0); ri = qi[ 2 : 2 ]; `checkh(ri.size, 1); ri = qi[ -2 : 2 ]; // 2 - 0 + 1 = 3 `checkh(ri.size, 3); ri = qi[ 2 : 10 ]; // 5 - 2 + 1 = 4 `checkh(ri.size, 4); // Assignment from unsized to sized ri = '{1,2,3,4,5,6,7,8,9}; qi = ri; `checkh(qi.size, 5); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_constraint_global_random_simple.v0000644000542200017500000000571315125463617026236 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by PlanV GmbH. // SPDX-License-Identifier: CC0-1.0 // Simple test for global constraints with 2-level nesting: Top -> Mid -> Inner class Inner; rand int m_val; rand int m_rand_in_val; rand int m_only_topConstrained_val; constraint c_inner { m_val inside {[1:5]}; } function new(); m_val = 0; m_rand_in_val = 0; m_only_topConstrained_val = 0; endfunction endclass class Mid; int m_limit; rand int m_x; rand Inner m_inner; rand int m_rand_mid_val; constraint c_mid { m_x == m_limit; } function new(int lim); m_limit = lim; m_x = 0; m_rand_mid_val = 0; m_inner = new(); endfunction endclass class Top; rand Mid m_mid; rand int m_y; constraint c_top { m_y < m_mid.m_x; // 1-level reference m_mid.m_inner.m_val < m_y; // 2-level reference m_mid.m_inner.m_only_topConstrained_val == 5; // Only constrained at top level } function new(); m_mid = new(10); m_y = 0; endfunction endclass module t_constraint_global_random_simple; int success; Top t; initial begin t = new(); // Test: Regular randomize() with global constraints success = t.randomize(); if (success != 1) $stop; $display("After randomization:"); $display(" t.m_y = %0d", t.m_y); $display(" t.m_mid.m_x = %0d", t.m_mid.m_x); $display(" t.m_mid.m_inner.m_val = %0d", t.m_mid.m_inner.m_val); $display(" t.m_mid.m_inner.m_only_topConstrained_val = %0d", t.m_mid.m_inner.m_only_topConstrained_val); $display(" t.m_mid.m_rand_mid_val = %0d", t.m_mid.m_rand_mid_val); $display(" t.m_mid.m_inner.m_rand_in_val = %0d", t.m_mid.m_inner.m_rand_in_val); // Verify constraints // 1. c_mid: m_x == m_limit if (t.m_mid.m_x != 10) begin $display("ERROR: m_mid.m_x should be 10, got %0d", t.m_mid.m_x); $stop; end // 2. c_inner: m_val in [1:5] if (t.m_mid.m_inner.m_val < 1 || t.m_mid.m_inner.m_val > 5) begin $display("ERROR: m_inner.m_val should be in [1:5], got %0d", t.m_mid.m_inner.m_val); $stop; end // 3. c_top: m_y < m_mid.m_x (m_y < 10) if (t.m_y >= t.m_mid.m_x) begin $display("ERROR: m_y should be < m_mid.m_x, got m_y=%0d, m_x=%0d", t.m_y, t.m_mid.m_x); $stop; end // 4. c_top: m_mid.m_inner.m_val < m_y if (t.m_mid.m_inner.m_val >= t.m_y) begin $display("ERROR: m_inner.m_val should be < m_y, got m_val=%0d, m_y=%0d", t.m_mid.m_inner.m_val, t.m_y); $stop; end // 5. c_top: m_mid.m_inner.m_only_topConstrained_val == 5 if (t.m_mid.m_inner.m_only_topConstrained_val != 5) begin $display("ERROR: m_only_topConstrained_val should be 5, got %0d", t.m_mid.m_inner.m_only_topConstrained_val); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_func_sel.v0000644000542200017500000000306215125463617021412 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // The code as shown applies a random vector to the Test // module, then calculates a CRC on the Test module's outputs. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; parameter W = 104; integer cyc = 0; reg [63:0] crc; reg [127:0] sum; wire [127:0] result; wire [103:0] in; reg [103:0] out; assign in = {crc[39:0], crc[63:0]}; always @(posedge clk) begin out <= reverse(in); end assign result = {24'h0, out }; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x in=%x out=%x\n", $time, cyc, crc, result, in, out); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= {sum[127:1], 1'b0} + result; if (cyc < 10) begin crc <= 1; sum <= '0; end else if (cyc >= 90) begin $display("SUM = %x_%x_%x_%x", sum[127:96], sum[95:64], sum[63:32], sum[31:0]); `define EXPECTED_SUM 128'h00002d36_42d1a346_8d1a5936_42d1a319 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end function [W-1:0] reverse(input [W-1:0] val); integer i; // Bug workaround: reverse = '0; for (i = 0; i < W; i = i + 1) reverse[W-1-i] = val[i]; endfunction endmodule verilator-5.044/test_regress/t/t_lint_restore_prag_bad.py0000755000542200017500000000076315125463617024337 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_display_format_wide_decimal.py0000755000542200017500000000105415125463617025504 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-Wall -Wno-DECLFILENAME"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_alias_tristate_unsup.py0000755000542200017500000000077615125463617024255 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_func_noinl.v0000644000542200017500000000566415125463617021760 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; wire [31:0] inp = crc[31:0]; wire reset = (cyc < 5); /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] outp; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .outp (outp[31:0]), // Inputs .reset (reset), .clk (clk), .inp (inp[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, outp}; // What checksum will we end up with `define EXPECTED_SUM 64'ha7f0a34f9cf56ccb // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs outp, // Inputs reset, clk, inp ); input reset; input clk; input [31:0] inp; output [31:0] outp; function automatic [31:0] no_inline_function; input [31:0] var1; input [31:0] var2; /*verilator no_inline_task*/ reg [31*2:0] product1 ; reg [31*2:0] product2 ; integer i; reg [31:0] tmp; begin product2 = {(31*2+1){1'b0}}; for (i = 0; i < 32; i = i + 1) if (var2[i]) begin product1 = { {31*2+1-32{1'b0}}, var1} << i; product2 = product2 ^ product1; end no_inline_function = 0; for (i= 0; i < 31; i = i + 1 ) no_inline_function[i+1] = no_inline_function[i] ^ product2[i] ^ var1[i]; end endfunction reg [31:0] outp; reg [31:0] inp_d; always @( posedge clk ) begin if( reset ) begin outp <= 0; end else begin inp_d <= inp; outp <= no_inline_function(inp, inp_d); end end endmodule verilator-5.044/test_regress/t/t_preproc_persist.out0000644000542200017500000000014515125463617023400 0ustar mahmoudyfreeshellInside "t/t_preproc_persist.v". Inside "t/t_preproc_persist_inc.v". Inside "t/t_preproc_persist2.v". verilator-5.044/test_regress/t/t_uniqueif.py0000755000542200017500000000102015125463617021617 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert'], nc_flags2=['+assert']) test.execute() test.passes() verilator-5.044/test_regress/t/t_flag_bboxsys.v0000644000542200017500000000074515125463617022303 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg a; initial begin $unknown_sys_task_call_to_be_bbox("blah"); $unkown_sys_task_call_noarg; a = $unknown_sys_func_call(23); a = $unknown_sys_func_call_noarg; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_dist_attributes_src.py0000755000542200017500000000374615125463617024073 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.priority(30) test.scenarios('dist') test.rerunnable = False def have_clang_check(): cmd = 'python3 -c "from clang.cindex import Index; index = Index.create(); print(\\"Clang imported\\")";' if test.verbose: print("\t" + cmd) nout = test.run_capture(cmd, check=False) if not nout or not re.search(r'Clang imported', nout): return False return True if 'VERILATOR_TEST_NO_ATTRIBUTES' in os.environ: test.skip("Skipping due to VERILATOR_TEST_NO_ATTRIBUTES") if not os.path.exists(test.root + "/src/obj_dbg/compile_commands.json"): test.skip("compile_commands.json not found. Please install 'bear > 3.0' and rebuild Verilator") if not have_clang_check(): test.skip("No libclang installed") # some of the files are only used in Verilation # and are only in "include" folder srcfiles = test.glob_some(test.root + "/src/*.cpp") + test.glob_some(test.root + "/src/obj_dbg/V3Const__gen.cpp") srcfiles = [f for f in srcfiles if re.search(r'\/(V3Const|Vlc\w*|\w*_test|\w*_sc|\w*.yy).cpp$', f)] srcfiles_str = " ".join(srcfiles) test.run(logfile=test.run_log_filename, tee=True, cmd=["python3", test.root + "/nodist/clang_check_attributes", "--verilator-root=" + test.root, "--compilation-root=" + test.root + "/src/obj_dbg", "--compile-commands-dir=" + test.root + "/src/obj_dbg", srcfiles_str]) # yapf:disable test.file_grep(test.run_log_filename, r'Number of functions reported unsafe: +(\d+)', 0) test.passes() verilator-5.044/test_regress/t/t_class_extends_aliased_real_bad.out0000644000542200017500000000054015125463617026306 0ustar mahmoudyfreeshell%Error: t/t_class_extends_aliased_real_bad.v:14:10: Attempting to extend using non-class : ... note: In instance 't' 14 | bar #(real_t) bar_real_t; | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_param_up_bad.out0000644000542200017500000000041615125463617022570 0ustar mahmoudyfreeshell%Error: t/t_param_up_bad.v:16:19: Can't find definition of scope/variable: 'bar' 16 | assign a_bad = bar.foo; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_trace_cat_renew.out0000644000542200017500000001745015125463617023311 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $date Sat Feb 23 20:18:07 2013 $end $timescale 1ps $end $scope module top $end $var wire 1 $ clk $end $scope module t $end $var wire 1 $ clk $end $var wire 32 # cyc [31:0] $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000001 # 1$ #1 0$ #2 b00000000000000000000000000000010 # 1$ #3 0$ #4 b00000000000000000000000000000011 # 1$ #5 0$ #6 b00000000000000000000000000000100 # 1$ #7 0$ #8 b00000000000000000000000000000101 # 1$ #9 0$ #10 b00000000000000000000000000000110 # 1$ #11 0$ #12 b00000000000000000000000000000111 # 1$ #13 0$ #14 b00000000000000000000000000001000 # 1$ #15 0$ #16 b00000000000000000000000000001001 # 1$ #17 0$ #18 b00000000000000000000000000001010 # 1$ #19 0$ #20 b00000000000000000000000000001011 # 1$ #21 0$ #22 b00000000000000000000000000001100 # 1$ #23 0$ #24 b00000000000000000000000000001101 # 1$ #25 0$ #26 b00000000000000000000000000001110 # 1$ #27 0$ #28 b00000000000000000000000000001111 # 1$ #29 0$ #30 b00000000000000000000000000010000 # 1$ #31 0$ #32 b00000000000000000000000000010001 # 1$ #33 0$ #34 b00000000000000000000000000010010 # 1$ #35 0$ #36 b00000000000000000000000000010011 # 1$ #37 0$ #38 b00000000000000000000000000010100 # 1$ #39 0$ #40 b00000000000000000000000000010101 # 1$ #41 0$ #42 b00000000000000000000000000010110 # 1$ #43 0$ #44 b00000000000000000000000000010111 # 1$ #45 0$ #46 b00000000000000000000000000011000 # 1$ #47 0$ #48 b00000000000000000000000000011001 # 1$ #49 0$ #50 b00000000000000000000000000011010 # 1$ #51 0$ #52 b00000000000000000000000000011011 # 1$ #53 0$ #54 b00000000000000000000000000011100 # 1$ #55 0$ #56 b00000000000000000000000000011101 # 1$ #57 0$ #58 b00000000000000000000000000011110 # 1$ #59 0$ #60 b00000000000000000000000000011111 # 1$ #61 0$ #62 b00000000000000000000000000100000 # 1$ #63 0$ #64 b00000000000000000000000000100001 # 1$ #65 0$ #66 b00000000000000000000000000100010 # 1$ #67 0$ #68 b00000000000000000000000000100011 # 1$ #69 0$ #70 b00000000000000000000000000100100 # 1$ #71 0$ #72 b00000000000000000000000000100101 # 1$ #73 0$ #74 b00000000000000000000000000100110 # 1$ #75 0$ #76 b00000000000000000000000000100111 # 1$ #77 0$ #78 b00000000000000000000000000101000 # 1$ #79 0$ #80 b00000000000000000000000000101001 # 1$ #81 0$ #82 b00000000000000000000000000101010 # 1$ #83 0$ #84 b00000000000000000000000000101011 # 1$ #85 0$ #86 b00000000000000000000000000101100 # 1$ #87 0$ #88 b00000000000000000000000000101101 # 1$ #89 0$ #90 b00000000000000000000000000101110 # 1$ #91 0$ #92 b00000000000000000000000000101111 # 1$ #93 0$ #94 b00000000000000000000000000110000 # 1$ #95 0$ #96 b00000000000000000000000000110001 # 1$ #97 0$ #98 b00000000000000000000000000110010 # 1$ #99 0$ #100 b00000000000000000000000000110011 # 1$ #101 0$ #102 b00000000000000000000000000110100 # 1$ #103 0$ #104 b00000000000000000000000000110101 # 1$ #105 0$ #106 b00000000000000000000000000110110 # 1$ #107 0$ #108 b00000000000000000000000000110111 # 1$ #109 0$ #110 b00000000000000000000000000111000 # 1$ #111 0$ #112 b00000000000000000000000000111001 # 1$ #113 0$ #114 b00000000000000000000000000111010 # 1$ #115 0$ #116 b00000000000000000000000000111011 # 1$ #117 0$ #118 b00000000000000000000000000111100 # 1$ #119 0$ #120 b00000000000000000000000000111101 # 1$ #121 0$ #122 b00000000000000000000000000111110 # 1$ #123 0$ #124 b00000000000000000000000000111111 # 1$ #125 0$ #126 b00000000000000000000000001000000 # 1$ #127 0$ #128 b00000000000000000000000001000001 # 1$ #129 0$ #130 b00000000000000000000000001000010 # 1$ #131 0$ #132 b00000000000000000000000001000011 # 1$ #133 0$ #134 b00000000000000000000000001000100 # 1$ #135 0$ #136 b00000000000000000000000001000101 # 1$ #137 0$ #138 b00000000000000000000000001000110 # 1$ #139 0$ #140 b00000000000000000000000001000111 # 1$ #141 0$ #142 b00000000000000000000000001001000 # 1$ #143 0$ #144 b00000000000000000000000001001001 # 1$ #145 0$ #146 b00000000000000000000000001001010 # 1$ #147 0$ #148 b00000000000000000000000001001011 # 1$ #149 0$ #150 b00000000000000000000000001001100 # 1$ #151 0$ #152 b00000000000000000000000001001101 # 1$ #153 0$ #154 b00000000000000000000000001001110 # 1$ #155 0$ #156 b00000000000000000000000001001111 # 1$ #157 0$ #158 b00000000000000000000000001010000 # 1$ #159 0$ #160 b00000000000000000000000001010001 # 1$ #161 0$ #162 b00000000000000000000000001010010 # 1$ #163 0$ #164 b00000000000000000000000001010011 # 1$ #165 0$ #166 b00000000000000000000000001010100 # 1$ #167 0$ #168 b00000000000000000000000001010101 # 1$ #169 0$ #170 b00000000000000000000000001010110 # 1$ #171 0$ #172 b00000000000000000000000001010111 # 1$ #173 0$ #174 b00000000000000000000000001011000 # 1$ #175 0$ #176 b00000000000000000000000001011001 # 1$ #177 0$ #178 b00000000000000000000000001011010 # 1$ #179 0$ #180 b00000000000000000000000001011011 # 1$ #181 0$ #182 b00000000000000000000000001011100 # 1$ #183 0$ #184 b00000000000000000000000001011101 # 1$ #185 0$ #186 b00000000000000000000000001011110 # 1$ #187 0$ #188 b00000000000000000000000001011111 # 1$ #189 0$ #190 b00000000000000000000000001100000 # 1$ #191 0$ #192 b00000000000000000000000001100001 # 1$ #193 0$ #194 b00000000000000000000000001100010 # 1$ #195 0$ #196 b00000000000000000000000001100011 # 1$ #197 0$ #198 b00000000000000000000000001100100 # 1$ #199 0$ #200 b00000000000000000000000001100101 # 1$ #201 0$ #202 b00000000000000000000000001100110 # 1$ #203 0$ #204 b00000000000000000000000001100111 # 1$ #205 0$ #206 b00000000000000000000000001101000 # 1$ #207 0$ #208 b00000000000000000000000001101001 # 1$ #209 0$ #210 b00000000000000000000000001101010 # 1$ #211 0$ #212 b00000000000000000000000001101011 # 1$ #213 0$ #214 b00000000000000000000000001101100 # 1$ #215 0$ #216 b00000000000000000000000001101101 # 1$ #217 0$ #218 b00000000000000000000000001101110 # 1$ #219 0$ #220 b00000000000000000000000001101111 # 1$ #221 0$ #222 b00000000000000000000000001110000 # 1$ #223 0$ #224 b00000000000000000000000001110001 # 1$ #225 0$ #226 b00000000000000000000000001110010 # 1$ #227 0$ #228 b00000000000000000000000001110011 # 1$ #229 0$ #230 b00000000000000000000000001110100 # 1$ #231 0$ #232 b00000000000000000000000001110101 # 1$ #233 0$ #234 b00000000000000000000000001110110 # 1$ #235 0$ #236 b00000000000000000000000001110111 # 1$ #237 0$ #238 b00000000000000000000000001111000 # 1$ #239 0$ #240 b00000000000000000000000001111001 # 1$ #241 0$ #242 b00000000000000000000000001111010 # 1$ #243 0$ #244 b00000000000000000000000001111011 # 1$ #245 0$ #246 b00000000000000000000000001111100 # 1$ #247 0$ #248 b00000000000000000000000001111101 # 1$ #249 0$ #250 b00000000000000000000000001111110 # 1$ #251 0$ #252 b00000000000000000000000001111111 # 1$ #253 0$ #254 b00000000000000000000000010000000 # 1$ #255 0$ #256 b00000000000000000000000010000001 # 1$ #257 0$ #258 b00000000000000000000000010000010 # 1$ #259 0$ #260 b00000000000000000000000010000011 # 1$ #261 0$ #262 b00000000000000000000000010000100 # 1$ #263 0$ #264 b00000000000000000000000010000101 # 1$ #265 0$ #266 b00000000000000000000000010000110 # 1$ #267 0$ #268 b00000000000000000000000010000111 # 1$ #269 0$ #270 b00000000000000000000000010001000 # 1$ #271 0$ #272 b00000000000000000000000010001001 # 1$ #273 0$ #274 b00000000000000000000000010001010 # 1$ #275 0$ #276 b00000000000000000000000010001011 # 1$ #277 0$ #278 b00000000000000000000000010001100 # 1$ #279 0$ #280 b00000000000000000000000010001101 # 1$ #281 0$ #282 b00000000000000000000000010001110 # 1$ #283 0$ #284 b00000000000000000000000010001111 # 1$ #285 0$ #286 b00000000000000000000000010010000 # 1$ #287 0$ #288 b00000000000000000000000010010001 # 1$ #289 0$ #290 b00000000000000000000000010010010 # 1$ #291 0$ #292 b00000000000000000000000010010011 # 1$ #293 0$ #294 b00000000000000000000000010010100 # 1$ #295 0$ #296 b00000000000000000000000010010101 # 1$ #297 0$ #298 b00000000000000000000000010010110 # 1$ #299 0$ verilator-5.044/test_regress/t/t_clocking_xref.v0000644000542200017500000000202515125463617022427 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module mod; bit clk = 1'b0; bit inp = 1'b0; clocking cb @(posedge clk); input #3 inp; endclocking always @(posedge clk) inp <= 1'b1; always #1 clk = ~clk; endmodule module main; bit clk = 1'b0; bit inp = 1'b0; always begin #2 if (t.mod1.cb.inp != 1'b0) $stop; if (t.main1.cbb.inp != 1'b0) $stop; if (t.main2.cbb.inp != 1'b0) $stop; #4; if (t.mod1.cb.inp != 1'b1) $stop; if (t.main1.cbb.inp != 1'b1) $stop; if (t.main2.cbb.inp != 1'b1) $stop; end clocking cbb @(posedge clk); input #3 inp; endclocking always @(posedge clk) inp <= 1'b1; always #1 clk = ~clk; endmodule module t; main main1(); mod mod1(); main main2(); initial begin #7; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_pp_lib.v0000644000542200017500000000046615125463617021066 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include "t_pp_lib_inc.vh" module t(); wire [`WIDTH-1:0] a; library_cell n1(a); endmodule verilator-5.044/test_regress/t/t_order_dpi_export_6.cpp0000644000542200017500000000213615125463617023727 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2022 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include void toggle_other_clk(svBit val) { set_other_clk(val); } int main(int argc, char* argv[]) { VM_PREFIX* const tb = new VM_PREFIX; tb->contextp()->commandArgs(argc, argv); bool clk = true; while (!tb->contextp()->gotFinish()) { // Timeout if (tb->contextp()->time() > 100000) break; // Toggle and set main clock clk = !clk; tb->clk = clk; // Eval tb->eval(); // Advance time tb->contextp()->timeInc(500); } delete tb; return 0; } verilator-5.044/test_regress/t/t_class_extends_rec_bad.v0000644000542200017500000000051315125463617024110 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class RecursiveExtCls extends RecursiveExtCls; int i; endclass module t; RecursiveExtCls cls = new; endmodule verilator-5.044/test_regress/t/t_opt_table_enum.out0000644000542200017500000000027515125463617023156 0ustar mahmoudyfreeshellcyle 0 = 0 cyle 1 = 1 cyle 2 = 2 cyle 3 = 99 cyle 4 = 4 cyle 5 = 5 cyle 6 = 99 cyle 7 = 99 *-* All Finished *-* verilator-5.044/test_regress/t/t_property_untyped.py0000755000542200017500000000077115125463617023442 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert']) test.execute() test.passes() verilator-5.044/test_regress/t/t_slice_cond.py0000755000542200017500000000071415125463617022105 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.044/test_regress/t/t_sys_file_zero.py0000755000542200017500000000073415125463617022661 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_param_pattern.v0000644000542200017500000000250215125463617022447 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2021 by Krzysztof Bieganski. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); package config_pkg; typedef struct packed { int UPPER0; int UPPER2; int USE_QUAD0; int USE_QUAD1; int USE_QUAD2; } config_struct_t; endpackage module t; import config_pkg::*; struct_submodule #(.MY_CONFIG('{ UPPER0: 10, UPPER2: 20, USE_QUAD0: 4, USE_QUAD1: 5, USE_QUAD2: 6 })) a_submodule_I (); endmodule module struct_submodule import config_pkg::*; #(parameter config_struct_t MY_CONFIG = '0); initial begin `checkd(MY_CONFIG.UPPER0, 10); `checkd(MY_CONFIG.USE_QUAD0, 4); `checkd(MY_CONFIG.USE_QUAD1, 5); `checkd(MY_CONFIG.USE_QUAD2, 6); `checkd(MY_CONFIG.UPPER2, 20); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_std_process_self.v0000644000542200017500000000075115125463617023157 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Foo; static task do_something(); `ifdef USE_STD_PREFIX std::process p; `else process p; `endif p = process::self(); endtask endclass module t(); initial begin Foo::do_something(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_struct_port.v0000644000542200017500000000413215125463617022203 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef struct packed { bit b9; byte b1; bit b0; } pack_t; module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs pack_t in; always @* in = crc[9:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) pack_t out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out), // Inputs .in (in)); // Aggregate outputs into a single result vector wire [63:0] result = {54'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x in=%x result=%x\n", $time, cyc, crc, in, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h99c434d9b08c2a8a if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( input pack_t in, output pack_t out); always @* begin out = in; out.b1 = in.b1 + 1; out.b0 = 1'b1; end endmodule // Local Variables: // verilog-typedef-regexp: "_t$" // End: verilator-5.044/test_regress/t/t_lint_didnotconverge_bad.out0000644000542200017500000000025315125463617025023 0ustar mahmoudyfreeshell-V{t#,#} 'stl' region trigger index 0 is active: @([hybrid] a) %Error: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge after 100 tries Aborting... verilator-5.044/test_regress/t/t_pp_pragmas.py0000755000542200017500000000072615125463617022137 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_wire_self_bad.v0000644000542200017500000000050715125463617022402 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' // // Simple bi-directional alias test. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; wire myself = myself; endmodule verilator-5.044/test_regress/t/t_mem_twoedge.py0000755000542200017500000000073415125463617022301 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_clocking_react.v0000644000542200017500000000256015125463617022565 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 interface axi_if; logic clk; wire rlast; wire rvalid; clocking cb @(posedge clk); inout rlast, rvalid; endclocking endinterface module t; axi_if axi_vi(); initial begin axi_vi.clk = 1'b0; #1 axi_vi.clk = 1'b1; // triggers line 26 #1 axi_vi.clk = 1'b0; // triggers line 29 (shouldn't happen) #1 axi_vi.clk = 1'b1; // triggers line 18 (shouldn't happen) end initial begin @(negedge axi_vi.rvalid); $display("[%0t] rvalid==%b", $time, axi_vi.rvalid); $display("[%0t] rlast is 1: ", $time, axi_vi.rlast === 1); if (axi_vi.rlast === 1) $stop; $write("*-* All Finished *-*\n"); $finish; end initial begin $display("[%0t] rvalid <= 1", $time); axi_vi.cb.rvalid <= 1'b1; // assigned on first clk posedge (line 13) @(posedge axi_vi.rvalid); $display("[%0t] rvalid <= 0", $time); axi_vi.cb.rvalid <= 1'b0; // assigned on second clk posedge (line 15), but should be on first @(negedge axi_vi.clk); $display("[%0t] rlast <= 1", $time); axi_vi.cb.rlast <= 1'b1; // assigned on second clk posedge (line 15), shouldn't happen end endmodule verilator-5.044/test_regress/t/t_flag_build_jobs_bad.out0000644000542200017500000000030615125463617024067 0ustar mahmoudyfreeshell%Error: --build-jobs requires a non-negative integer, but '-1' was passed ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_queue_output_func.v0000644000542200017500000000075515125463617023401 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Cls; int x = 1; endclass task init_set_2 (output Cls c); c = new; c.x = 2; endtask module t; initial begin Cls cls_q[$]; init_set_2(cls_q[0]); if (cls_q[0].x != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_stream_unpack.v0000644000542200017500000001743515125463617022461 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); typedef enum bit [5:0] { A = 6'b111000, B = 6,b111111 } enum_t; module t; initial begin typedef bit [5:0] bit6_t; typedef bit bit6_unpacked_t[6]; bit6_unpacked_t arr; bit [1:0] arr2[3]; bit6_t arr6[1]; bit6_t [0:0] parr6; bit6_t bit6 = 6'b111000; bit [5:0] ans; bit [2:0][1:0] ans_packed; enum_t ans_enum; logic [1:0] a [3] = {1, 0, 3}; logic [1:0] b [3] = {1, 2, 0}; logic c [4] = {1, 1, 0, 0}; logic [15:0] d; logic [3:0] e [2]; logic f [8]; logic [1:0][7:0] g; logic [1:0][1:0][3:0] h; byte i []; longint j; int k; int l []; logic [127:0] m; longint n []; logic [255:0] o; logic [127:0] p[]; { >> bit {arr}} = bit6; `checkp(arr, "'{'h1, 'h1, 'h1, 'h0, 'h0, 'h0}"); arr = { >> bit {bit6}}; `checkp(arr, "'{'h1, 'h1, 'h1, 'h0, 'h0, 'h0}"); ans = { >> bit {arr} }; `checkh(ans, bit6); { >> bit {ans}} = arr; `checkh(ans, bit6); ans_packed = { >> bit {arr} }; `checkh(ans_packed, bit6); { >> bit {ans_packed}} = arr; `checkh(ans_packed, bit6); ans_enum = enum_t'({ >> bit {arr} }); `checkh(ans_enum, bit6); { << bit {arr}} = bit6; `checkp(arr, "'{'h0, 'h0, 'h0, 'h1, 'h1, 'h1}"); arr = { << bit {bit6}}; `checkp(arr, "'{'h0, 'h0, 'h0, 'h1, 'h1, 'h1}"); ans = { << bit {arr} }; `checkh(ans, bit6); { << bit {ans} } = arr; `checkh(ans, bit6); ans_packed = { << bit {arr} }; `checkh(ans_packed, bit6); { << bit {ans_packed} } = arr; `checkh(ans_packed, bit6); ans_enum = enum_t'({ << bit {arr} }); `checkh(ans_enum, bit6); { >> bit[1:0] {arr2}} = bit6; `checkp(arr2, "'{'h3, 'h2, 'h0}"); arr2 = { >> bit[1:0] {bit6}}; `checkp(arr2, "'{'h3, 'h2, 'h0}"); ans = { >> bit[1:0] {arr2} }; `checkh(ans, bit6); { >> bit[1:0] {ans} } = arr2; `checkh(ans, bit6); ans_packed = { >> bit[1:0] {arr2} }; `checkh(ans_packed, bit6); { >> bit[1:0] {ans_packed} } = arr2; `checkh(ans_packed, bit6); ans_enum = enum_t'({ >> bit[1:0] {arr2} }); `checkh(ans_enum, bit6); { << bit[1:0] {arr2}} = bit6; `checkp(arr2, "'{'h0, 'h2, 'h3}"); ans = { << bit[1:0] {arr2} }; `checkh(ans, bit6); { << bit[1:0] {ans} } = arr2; `checkh(ans, bit6); ans_packed = { << bit[1:0] {arr2} }; `checkh(ans_packed, bit6); { << bit[1:0] {ans_packed} } = arr2; `checkh(ans_packed, bit6); ans_enum = enum_t'({ << bit[1:0] {arr2} }); `checkh(ans_enum, bit6); { >> bit [5:0] {arr6} } = bit6; `checkp(arr6, "'{'h38}"); arr6 = { >> bit [5:0] {bit6}}; `checkp(arr6, "'{'h38}"); ans = { >> bit[5:0] {arr6} }; `checkh(ans, bit6); { >> bit[5:0] {ans} } = arr6; `checkh(ans, bit6); ans_packed = { >> bit[5:0] {arr6} }; `checkh(ans_packed, bit6); { >> bit[5:0] {ans_packed} } = arr6; `checkh(ans_packed, bit6); ans_enum = enum_t'({ >> bit[5:0] {arr6} }); `checkh(ans_enum, bit6); { << bit [5:0] {arr6} } = bit6; `checkp(arr6, "'{'h38}"); arr6 = { << bit [5:0] {bit6}}; `checkp(arr6, "'{'h38}"); ans = { << bit[5:0] {arr6} }; `checkh(ans, bit6); { << bit[5:0] {ans} } = arr6; `checkh(ans, bit6); ans_packed = { << bit[5:0] {arr6} }; `checkh(ans_packed, bit6); { << bit[5:0] {ans_packed} } = arr6; `checkh(ans_packed, bit6); ans_enum = enum_t'({ << bit[5:0] {arr6} }); `checkh(ans_enum, bit6); { >> bit [5:0] {parr6} } = bit6; `checkh(parr6, bit6); parr6 = { >> bit [5:0] {bit6}}; `checkh(parr6, bit6); ans = { >> bit[5:0] {parr6} }; `checkh(ans, bit6); { >> bit[5:0] {ans} } = parr6; `checkh(ans, bit6); ans_packed = { >> bit[5:0] {parr6} }; `checkh(ans_packed, bit6); { >> bit[5:0] {ans_packed} } = parr6; `checkh(ans_packed, bit6); ans_enum = enum_t'({ >> bit[5:0] {parr6} }); `checkh(ans_enum, bit6); { << bit [5:0] {parr6} } = bit6; `checkh(parr6, bit6); parr6 = { << bit [5:0] {bit6}}; `checkh(parr6, bit6); ans = { << bit[5:0] {parr6} }; `checkh(ans, bit6); { << bit[5:0] {ans} } = parr6; `checkh(ans, bit6); ans_packed = { << bit[5:0] {parr6} }; `checkh(ans_packed, bit6); { << bit[5:0] {ans_packed} } = parr6; `checkh(ans_packed, bit6); ans_enum = enum_t'({ << bit[5:0] {parr6} }); `checkh(ans_enum, bit6); d = { >> {a, b, c}}; `checkh(d, 16'b0100110110001100); { >> {e, f}} = d; `checkp(e, "'{'h4, 'hd}"); `checkp(f, "'{'h1, 'h0, 'h0, 'h0, 'h1, 'h1, 'h0, 'h0}"); d = { << 4 {a, b, c}}; `checkh(d, 16'b1100100011010100); { << 2 {e, f}} = d; `checkp(e, "'{'h1, 'h7}"); `checkp(f, "'{'h0, 'h0, 'h1, 'h0, 'h0, 'h0, 'h1, 'h1}"); g = { << 8 {16'hABCD}}; `checkh(g, 16'hCDAB); h = { << 8 {16'hABCD}}; `checkh(h, 16'hCDAB); i = new[8]('{8'hfa, 8'hde, 8'hca, 8'hfe, 8'hde, 8'had, 8'hbe, 8'hef}); `checkh(i[0], 8'hfa); `checkh(i[7], 8'hef); j = {>>{i}}; `checkh(j, 64'hfadecafedeadbeef); j = {<<8{i}}; `checkh(j, 64'hefbeaddefecadefa); i = new[4]('{8'hba, 8'hbe, 8'hfa, 8'hce}); k = {>>{i}}; `checkh(k, 32'hbabeface); k = {<<8{i}}; `checkh(k, 32'hcefabeba); i = new[8]('{8'hba, 8'hbe, 8'hfa, 8'hce, 8'hde, 8'had, 8'hbe, 8'hef}); j = {>>{i}}; `checkh(j, 64'hbabefacedeadbeef); j = {<<8{i}}; `checkh(j, 64'hefbeaddecefabeba); i = new[16]('{8'hba, 8'hbe, 8'hfa, 8'hce, 8'hde, 8'had, 8'hbe, 8'hef, 8'hde, 8'had, 8'hbe, 8'hef, 8'hde, 8'had, 8'hbe, 8'hef}); m = {>>{i}}; `checkh(m, 128'hbabefacedeadbeefdeadbeefdeadbeef); m = {<<8{i}}; `checkh(m, 128'hefbeaddeefbeaddeefbeaddecefabeba); l = new[2]('{32'hbabeface, 32'hdeadbeef}); j = {>>{l}}; `checkh(j, 64'hbabefacedeadbeef); j = {<<8{l}}; `checkh(j, 64'hefbeaddecefabeba); l = new[4]('{32'hbabeface, 32'hdeadbeef, 32'hdeadbeef, 32'hdeadbeef}); m = {>>{l}}; `checkh(m, 128'hbabefacedeadbeefdeadbeefdeadbeef); m = {<<8{l}}; `checkh(m, 128'hefbeaddeefbeaddeefbeaddecefabeba); n = new[2]('{64'hfadecafedeadbeef, 64'habcd0123456789ab}); m = {>>{n}}; `checkh(m, 128'hfadecafedeadbeefabcd0123456789ab); m = {<<64{n}}; `checkh(m, 128'habcd0123456789abfadecafedeadbeef); p = new[2]('{128'hfadecafedeadbeefabcd0123456789ab, 128'habcd0123456789abfadecafedeadbeef}); o = {>>{p}}; `checkh(o, 256'hfadecafedeadbeefabcd0123456789ababcd0123456789abfadecafedeadbeef); o = {<<128{p}}; `checkh(o, 256'habcd0123456789abfadecafedeadbeeffadecafedeadbeefabcd0123456789ab); {>>{p}} = o; `checkh(p[0], 128'habcd0123456789abfadecafedeadbeef); `checkh(p[1], 128'hfadecafedeadbeefabcd0123456789ab); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_timescale_default.out0000644000542200017500000000006215125463617023625 0ustar mahmoudyfreeshellTime scale of t is 1ps / 1ps *-* All Finished *-* verilator-5.044/test_regress/t/t_display_concat2.out0000644000542200017500000000013515125463617023232 0ustar mahmoudyfreeshell00005678 00001234 00005679 00001234 0000567a 00001234 0000567b 00001234 *-* All Finished *-* verilator-5.044/test_regress/t/t_split_var_5.py0000755000542200017500000000135015125463617022227 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_split_var_4.v" test.compile(verilator_flags2=['--stats', "-fno-dfg"]) test.execute() test.file_grep(test.stats, r'SplitVar,\s+packed variables split due to attribute\s+(\d+)', 0) test.file_grep(test.stats, r'SplitVar,\s+unpacked arrays split due to attribute\s+(\d+)', 0) test.passes() verilator-5.044/test_regress/t/t_math_wide_inc.py0000755000542200017500000000073415125463617022577 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_flag_runtime_timeout_bad.out0000644000542200017500000000013615125463617025205 0ustar mahmoudyfreeshellSleeping.... %Error: Alarm signal received, '--debug-runtime-timeout 1' exceeded Aborting... verilator-5.044/test_regress/t/t_typedef_consistency_0.py0000755000542200017500000000073415125463617024305 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_unpacked_slice_range.v0000644000542200017500000000401315125463617023736 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Yutetsu TAKATSUKASA // SPDX-License-Identifier: Unlicense module t ( clk ); input clk; int c = 0; t2 #(0) i_0(.*); t2 #(-1) i_1(.*); // lo is -1, hi is 5 t2 #(-4) i_2(.*); // lo is -4, hi is 1 t2 #(-10) i_3(.*); // lo is -10, hi is -4 t2 #(+1) i_4(.*); // lo is 1, hi is 7 t2 #(+4) i_5(.*); // lo is 4, hi is 10 t2 #(+10) i_6(.*); // lo is 10, hi is 16 always @(posedge clk) begin c <= c + 1; if (c == 5) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module t2 #(parameter ORIGIN = 0) (input wire clk, input int c); localparam WIDTH = 7; localparam OFFSET = 3; localparam FULL_LO = ORIGIN; localparam FULL_HI = ORIGIN + WIDTH - 1; localparam PART_LO = FULL_LO + OFFSET; localparam PART_HI = FULL_HI; bit unpack_sig0 [FULL_LO:FULL_HI]; bit unpack_sig1 [PART_LO:PART_HI]; bit unpack_sig2 [FULL_HI:FULL_LO]; bit unpack_sig3 [PART_HI:PART_LO]; initial $display("%m ORIGIN:%d [%d:%d] [%d:%d]", ORIGIN, FULL_LO, FULL_HI, PART_LO, PART_HI); always @(posedge clk) begin unpack_sig0[PART_LO] <= 1'b1; unpack_sig1[PART_LO] <= 1'b1; unpack_sig0 [PART_LO+1:FULL_HI] <= unpack_sig0[PART_LO:FULL_HI-1]; unpack_sig1 [PART_LO+1:PART_HI] <= unpack_sig1[PART_LO:PART_HI-1]; unpack_sig2[PART_LO] <= 1'b1; unpack_sig3[PART_LO] <= 1'b1; unpack_sig2 [FULL_HI:PART_LO+1] <= unpack_sig2[FULL_HI-1:PART_LO]; unpack_sig3 [PART_HI:PART_LO+1] <= unpack_sig3[PART_HI-1:PART_LO]; end always @(posedge clk) begin if (c >= 4) begin if (!unpack_sig0[FULL_HI] || !unpack_sig1[PART_HI]) $stop; if (!unpack_sig2[FULL_HI] || !unpack_sig3[PART_HI]) $stop; end else begin if (unpack_sig0[FULL_HI] || unpack_sig1[PART_HI]) $stop; if (unpack_sig2[FULL_HI] || unpack_sig3[PART_HI]) $stop; end end endmodule verilator-5.044/test_regress/t/t_interface_modport_expr.out0000644000542200017500000000451215125463617024721 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_interface_modport_expr.v:15:22: Unsupported: Modport expressions (IEEE 1800-2023 25.5.4) 15 | modport mp1(input .a(sig_a), output .b(sig_b)); | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: t/t_interface_modport_expr.v:15:22: Modport item not found: 'a' 15 | modport mp1(input .a(sig_a), output .b(sig_b)); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error-UNSUPPORTED: t/t_interface_modport_expr.v:15:40: Unsupported: Modport expressions (IEEE 1800-2023 25.5.4) 15 | modport mp1(input .a(sig_a), output .b(sig_b)); | ^ %Error: t/t_interface_modport_expr.v:15:40: Modport item not found: 'b' 15 | modport mp1(input .a(sig_a), output .b(sig_b)); | ^ %Error-UNSUPPORTED: t/t_interface_modport_expr.v:16:22: Unsupported: Modport expressions (IEEE 1800-2023 25.5.4) 16 | modport mp2(input .a(sig_c), output .b(sig_d)); | ^ %Error: t/t_interface_modport_expr.v:16:22: Modport item not found: 'a' 16 | modport mp2(input .a(sig_c), output .b(sig_d)); | ^ %Error-UNSUPPORTED: t/t_interface_modport_expr.v:16:40: Unsupported: Modport expressions (IEEE 1800-2023 25.5.4) 16 | modport mp2(input .a(sig_c), output .b(sig_d)); | ^ %Error: t/t_interface_modport_expr.v:16:40: Modport item not found: 'b' 16 | modport mp2(input .a(sig_c), output .b(sig_d)); | ^ %Error: t/t_interface_modport_expr.v:28:18: Can't find definition of 'a' in dotted variable/method: 'i.a' 28 | assign i.b = i.a; | ^ %Error: t/t_interface_modport_expr.v:28:12: Can't find definition of 'b' in dotted variable/method: 'i.b' 28 | assign i.b = i.a; | ^ %Error: t/t_interface_modport_expr.v:22:18: Can't find definition of 'a' in dotted variable/method: 'i.a' 22 | assign i.b = i.a; | ^ %Error: t/t_interface_modport_expr.v:22:12: Can't find definition of 'b' in dotted variable/method: 'i.b' 22 | assign i.b = i.a; | ^ %Error: Exiting due to verilator-5.044/test_regress/t/t_interface_inl.py0000755000542200017500000000115715125463617022607 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface.v" test.compile( # Avoid inlining so we find bugs in the non-inliner connection code verilator_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_trace_two_dumpfst_cc.py0000755000542200017500000000243115125463617024177 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test tracing with two models instanced import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t_trace_two_a.v" test.pli_filename = "t/t_trace_two_cc.cpp" test.compile(make_main=False, verilator_make_gmake=False, top_filename='t_trace_two_b.v', vm_prefix='Vt_trace_two_b', verilator_flags2=['--trace-fst --trace-threads 1 -DTEST_FST']) test.run(logfile=test.obj_dir + "/make_first_ALL.log", cmd=[ os.environ["MAKE"], "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp" ]) test.compile( make_main=False, top_filename='t_trace_two_a.v', verilator_flags2=['-exe', '--trace-fst --trace-threads 1', '-DTEST_FST', test.pli_filename], v_flags2=['+define+TEST_DUMP']) test.execute() if test.vlt_all: test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_lint_style_bad.v0000644000542200017500000000060115125463617022604 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; integer top; task x; output top; begin end endtask initial begin begin: lower integer top; end end endmodule verilator-5.044/test_regress/t/t_clk_dsp.py0000755000542200017500000000073415125463617021424 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_package_export.py0000755000542200017500000000100115125463617022765 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=['+define+T_PACKAGE_EXPORT']) test.execute() test.passes() verilator-5.044/test_regress/t/t_program_anonymous.v0000644000542200017500000000110615125463617023370 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 program; task atask; endtask function int afunc(input int i); return i+1; endfunction class acls; static int i = 10; endclass endprogram program t; int i; initial begin atask(); i = afunc(2); if (i != 3) $stop; if (acls::i != 10) $stop; $write("*-* All Finished *-*\n"); $finish; end endprogram verilator-5.044/test_regress/t/t_gen_defparam_nfound_bad.v0000644000542200017500000000047315125463617024406 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; a a (); defparam z.W = 3; // Bad endmodule module a; parameter W = 0; endmodule verilator-5.044/test_regress/t/t_rand_stability_class.v0000644000542200017500000000160715125463617024014 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; class Cls; task test_srandom; int i, j, k; // $urandom is per-process thread, not affected by object stability/this.srandom(seed) // "Each object maintains its own internal RNG, which is used exclusively by its randomize() method." // THis was moved to t_rand_stability_class.v this.srandom(1234); i = $urandom; this.srandom(1234); j = $urandom; this.srandom(1234); k = $urandom; if (i == j && i == k) $stop; // Small chance randomly i == j, or j == k endtask endclass Cls c1; initial begin c1 = new; c1.test_srandom; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_lint_implicit_type_bad.py0000755000542200017500000000122315125463617024506 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') # --debug-check adds extra internal message, otherwise golden log would vary test.lint(verilator_flags2=["--no-debug-check -Wall -Wno-DECLFILENAME"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_force_multi.v0000644000542200017500000000203115125463617022117 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) // verilog_format: on module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; logic [3:0] busa; logic [3:0] busb; // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 0) begin busa <= 4'b0101; busb <= 4'b0111; end else if (cyc == 1) begin force {busa, busb} = 8'b1111_1101; end else if (cyc == 2) begin `checkh(busa, 4'b1111); `checkh(busb, 4'b1101); end // else if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.044/test_regress/t/t_flag_xinitial_unique.py0000755000542200017500000000121015125463617024173 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios("vlt_all") test.compile(verilator_flags2=["--x-initial unique"]) test.execute() files = glob.glob(test.obj_dir + "/" + test.vm_prefix + "___024root__*__Slow.cpp") test.file_grep_any(files, r"VL_SCOPED_RAND_RESET") test.passes() verilator-5.044/test_regress/t/t_opt_table_signed.py0000755000542200017500000000130215125463617023277 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--stats"]) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 1) test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 1) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_sys_readmem_bad_end.mem0000644000542200017500000000057515125463617024077 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 00 01 10 // Missing additional data verilator-5.044/test_regress/t/t_display.py0000755000542200017500000000100015125463617021435 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_genvar_misuse_bad.out0000644000542200017500000000112115125463617023625 0ustar mahmoudyfreeshell%Error: t/t_genvar_misuse_bad.v:15:19: Genvar 'i' used outside generate for loop (IEEE 1800-2023 27.4) 15 | assign q[i] = d[i]; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_genvar_misuse_bad.v:15:12: Genvar 'i' used outside generate for loop (IEEE 1800-2023 27.4) 15 | assign q[i] = d[i]; | ^ %Error: t/t_genvar_misuse_bad.v:22:11: Genvar 'c' used outside generate for loop (IEEE 1800-2023 27.4) 22 | if (c); | ^ %Error: Exiting due to verilator-5.044/test_regress/t/t_flag_trace_threads_bad.out0000644000542200017500000000021615125463617024563 0ustar mahmoudyfreeshell%Error: --trace-threads must be >= 1: -1 ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. verilator-5.044/test_regress/t/t_compiler_include_dpi.h0000644000542200017500000000122115125463617023742 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2024 by Antmicro. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // no header guards to check if included once in pch file extern "C" int dpii_add_check(int actual, int expected); extern "C" void dpii_add(int a, int b, int* out); verilator-5.044/test_regress/t/t_sys_readmem_bad_addr2.py0000755000542200017500000000102415125463617024170 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_var_extern_method_lifetime.py0000755000542200017500000000077115125463617025401 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_timing_at_class.v0000644000542200017500000000354215125463617022757 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on module t; class apb_item; int addr; int data; endclass class any_monitor #( type REQ = int, RSP = REQ ); REQ req; RSP rsp; int req_changes; int rsp_changes; task run_phase(); $display("[%0t] run_phase", $time); fork forever begin @req; ++req_changes; $display("[%0t] req change #%0d", $time, req_changes); end forever begin @rsp; ++rsp_changes; $display("[%0t] rsp change #%0d", $time, rsp_changes); end join_none endtask endclass typedef int int_t; any_monitor #(int_t, int_t) imon; apb_item creq_item, crsp_item; any_monitor #(apb_item, apb_item) cmon; initial begin $display("Integer-based test"); imon = new; #1; imon.run_phase(); #1; imon.req = 1; // Change imon.rsp = 2; // Change #1; imon.req++; // Change #1; `checkd(imon.req_changes, 2); `checkd(imon.rsp_changes, 1); $display("Class-based test"); creq_item = new; crsp_item = new; cmon = new; #1; cmon.run_phase(); #1; cmon.req = creq_item; // Change cmon.rsp = crsp_item; // Change #1; creq_item.addr++; // Not a change #1; cmon.rsp = null; // Change #1; `checkd(cmon.req_changes, 1); `checkd(cmon.rsp_changes, 2); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_udp_delay.v0000644000542200017500000000066415125463617021567 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 primitive not_u(out, in); output out; input in; table 0 : 1; 1 : 0; endtable endprimitive module t (out, in); input in; output wire out; real v = 0.34; not_u #(1.145, v) dut_u (out, in); endmodule verilator-5.044/test_regress/t/t_implements_missing_bad.py0000755000542200017500000000076615125463617024526 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_alw_sen_compare.v0000644000542200017500000000067015125463617022754 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module top; sub inst ( .a({128{1'b1}}), .b({128{1'b1}}) ); endmodule module sub ( a, b ); input [127:0] a; input [127:0] b; always @(a or b) begin $display("doesn't matter"); end endmodule verilator-5.044/test_regress/t/t_sc_names.py0000755000542200017500000000113215125463617021566 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_sc: test.skip("No SystemC installed") test.compile(make_main=False, verilator_flags2=["-sc --exe", test.pli_filename]) test.execute() test.passes() verilator-5.044/test_regress/t/t_dist_docs_style.py0000755000542200017500000000764515125463617023210 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Primitive C++ style checker # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') def get_source_files(): git_files = test.run_capture("cd " + test.root + " && git ls-files") if test.verbose: print("MF " + git_files) files = {} for filename in git_files.split(): if filename == '': continue files[filename] = True return files def check_pattern(filename, contents, pattern, message): lineno = 1 buf = contents while True: m = re.match(r'^(.*?^(' + pattern + '))(.*)', buf) if not m: break lineno += m.group(1).count("\n") buf = m.group(3) test.error_keep_going(filename + ":" + str(lineno) + ": " + message) def check_sorted(filename, contents): re_option = re.compile(r'^\.\. option:: (.*)') re_other = re.compile(r'^[^ ]') # .. t_dist_docs_style ignore string # Ignore the given string, as a prefix match re_ignore = re.compile(r' *\.\. t_dist_docs_style ignore (.*)') # .. t_dist_docs_style restart_sort # Restart the sort as if it's a new list, for forcing specific ordering re_restart = re.compile(r' *\.\. t_dist_docs_style restart_sort') contents += "__EOF__\n" lineno = 0 options = [] ignores = [] for line in contents.split("\n"): lineno += 1 if re.match(r'^($|\.\. _)', line): continue match_option = re_option.match(line) match_ignore = re_ignore.match(line) if match_option: arg = match_option.group(1) # print("-option %s" % line) hit = False for ignore in ignores: if arg[:len(ignore)] == ignore: hit = True if not hit: options.append([lineno, arg]) elif match_ignore: arg = match_ignore.group(1) ignores.append(arg) elif (options and re_other.match(line)) or re_restart.match(line): # print("-end-list %d %s" % (len(options), line)) check_sorted_options(filename, options) ignores = [] options = [] def check_sorted_options(filename, options): last_opt = None for opt_data in options: (lineno, opt) = opt_data if last_opt and _option_sort_key(last_opt) > _option_sort_key(opt): test.error_keep_going(filename + ":" + str(lineno) + ": Option '%s' should be in sorted order before '%s'" % (opt, last_opt)) last_opt = opt def _option_sort_key(opt): opt = re.sub(r'^<', ' <', opt) # before -option opt = re.sub(r'^\+', '-', opt) # +options sort with -options opt = re.sub(r'^--', '-', opt) # -- sorts with - opt = re.sub(r'^-no-', '-', opt) # -no- sorts with non-no opt = opt.lower() return opt ##### if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") ### Must trim output before and after our file list files = get_source_files() for filename in sorted(files.keys()): filename = os.path.join(test.root, filename) if not os.path.exists(filename): # git file might be deleted but not yet staged continue if not re.search(r'\.rst$', filename): continue contents = test.file_contents(filename) check_pattern(filename, contents, r'.*[a-z](?= 0: -2 ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. verilator-5.044/test_regress/t/t_cover_toggle_underscore.py0000755000542200017500000000120715125463617024711 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = 't/t_cover_toggle.v' test.compile(verilator_flags2=['--cc --coverage-toggle --coverage-underscore']) test.execute() test.file_grep(test.obj_dir + "/coverage.dat", "_under_toggle") test.passes() verilator-5.044/test_regress/t/t_opt_merge_cond_blowup.py0000755000542200017500000000200715125463617024354 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') # TODO: This takes excessively long on vltmt, this should be fixed test.compile(verilator_flags2=["--unroll-count 1000000000", "--output-split 0", "--stats"]) test.execute() if test.vlt: # Note, with vltmt this might be split differently, so only checking vlt test.file_grep(test.stats, r'Optimizations, MergeCond merges\s+(\d+)', 500) # V3MergeCond.cpp MAX_DISTANCE test.file_grep(test.stats, r'Optimizations, MergeCond merged items\s+(\d+)', 1000) # V3MergeCond.cpp MAX_DISTANCE *2 test.file_grep(test.stats, r'Optimizations, MergeCond longest merge\s+(\d+)', 2) test.passes() verilator-5.044/test_regress/t/t_gen_missing.v0000644000542200017500000000255015125463617022117 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // verilator lint_off PINMISSING `ifdef T_GEN_MISSING_BAD foobar #(.FOO_TYPE(1)) foobar(); // This means we should instatiate missing module `elsif T_GEN_MISSING foobar #(.FOO_TYPE(0)) foobar(); // This means we should instatiate foo0 `else `error "Bad Test" `endif endmodule module foobar #( parameter FOO_START = 0, FOO_NUM = 2, FOO_TYPE = 1 ) ( input wire[FOO_NUM-1:0] foo, output wire[FOO_NUM-1:0] bar); generate begin: g genvar j; for (j = FOO_START; j < FOO_NUM+FOO_START; j = j + 1) begin: foo_inst; if (FOO_TYPE == 0) begin: foo_0 // instatiate foo0 foo0 i_foo(.x(foo[j]), .y(bar[j])); end if (FOO_TYPE == 1) begin: foo_1 // instatiate foo1 foo_not_needed i_foo(.x(foo[j]), .y(bar[j])); end end end endgenerate endmodule module foo0(input wire x, output wire y); assign y = ~x; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_vpi_dump_missing_scopes.out0000644000542200017500000000210515125463617025103 0ustar mahmoudyfreeshellt (vpiModule) t vpiDefName=t vpiReg: vpiParameter: vpiInternalScope: top_wrap_1 (vpiModule) t.top_wrap_1 vpiDefName=gen_wrapper vpiReg: vpiParameter: vpiInternalScope: gen_loop[0] (vpiGenScope) t.top_wrap_1.gen_loop[0] vpiReg: vpiParameter: vpiInternalScope: after_gen_loop (vpiModule) t.top_wrap_1.gen_loop[0].after_gen_loop vpiDefName=sub vpiReg: subsig1 (vpiReg) t.top_wrap_1.gen_loop[0].after_gen_loop.subsig1 vpiParameter: top_wrap_2 (vpiModule) t.top_wrap_2 vpiDefName=gen_wrapper vpiReg: vpiParameter: vpiInternalScope: gen_loop[0] (vpiGenScope) t.top_wrap_2.gen_loop[0] vpiReg: vpiParameter: vpiInternalScope: after_gen_loop (vpiModule) t.top_wrap_2.gen_loop[0].after_gen_loop vpiDefName=sub vpiReg: subsig1 (vpiReg) t.top_wrap_2.gen_loop[0].after_gen_loop.subsig1 vpiParameter: *-* All Finished *-* verilator-5.044/test_regress/t/t_lib_nolib.py0000755000542200017500000000213715125463617021735 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all', 'xsim') test.top_filename = "t/t_lib_prot.v" if test.benchmark: test.sim_time = test.benchmark * 100 trace_opt = ("" if re.search(r'--no-trace', ' '.join(test.driver_verilator_flags)) else "-trace") # Tests the same code as t_lib_prot.py but without --protect-lib test.compile(verilator_flags2=['--no-timing', trace_opt, "t/t_lib_prot_secret.v"], xsim_flags2=["t/t_lib_prot_secret.v"]) test.execute() if test.vlt and test.trace: # We can see the ports of the secret module test.file_grep(test.trace_filename, r'accum_in') # and we can see what's inside (because we didn't use --protect-lib) test.file_grep(test.trace_filename, r'secret_') test.passes() verilator-5.044/test_regress/t/t_eq_wild_unsup.v0000644000542200017500000000066015125463617022473 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 function logic get_x_or_0(logic get_x); return get_x ? 1'bx : 1'b0; endfunction module t; initial begin if (1 ==? get_x_or_0(0)) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_lint_width_genfor_bad.out0000644000542200017500000000323015125463617024466 0ustar mahmoudyfreeshell%Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:25:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?sh10' generates 32 or 5 bits. : ... note: In instance 't' 25 | rg = g; | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:26:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'P' generates 32 or 5 bits. : ... note: In instance 't' 26 | rp = P; | ^ %Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:27:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'w' generates 5 bits. : ... note: In instance 't' 27 | rw = w; | ^ %Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:28:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits. : ... note: In instance 't' 28 | rc = 64'h1; | ^ %Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:33:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'i' generates 32 bits. : ... note: In instance 't' 33 | ri = i; | ^ %Error: Exiting due to verilator-5.044/test_regress/t/t_randc_extends.py0000755000542200017500000000073415125463617022626 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_trace_enum_fst.out0000644000542200017500000000121715125463617023154 0ustar mahmoudyfreeshell$date Sat Apr 5 13:56:28 2025 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $attrbegin misc 07 $unit::state_t 4 VAL_A VAL_B VAL_C VAL_D 00 01 10 11 1 $end $attrbegin misc 07 t.other_state_t 3 VAL_X VAL_Y VAL_Z 00 01 10 2 $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end $scope interface sink $end $attrbegin misc 07 "" 1 $end $var logic 2 " state [1:0] $end $upscope $end $attrbegin misc 07 "" 1 $end $var logic 2 # v_enumed [1:0] $end $attrbegin misc 07 "" 2 $end $var logic 2 $ v_other_enumed [1:0] $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b00 $ b00 # b00 " 0! $end #10 1! verilator-5.044/test_regress/t/t_pipe_filter.v0000644000542200017500000000073615125463617022123 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //=========================================================================== // Includes example line 10; example line 11; `include "t_pipe_filter_inc.vh" // Twice to check caching of includes `include "t_pipe_filter_inc.vh" example line 15; example line 16; verilator-5.044/test_regress/t/t_lint_iface_array_topmodule_bad.out0000644000542200017500000000062315125463617026347 0ustar mahmoudyfreeshell%Error: t/t_lint_iface_array_topmodule_bad.v:8:24: Parameter without default value is never given value (IEEE 1800-2023 6.20.1): 'DW' : ... note: In instance 't' 8 | parameter integer DW | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_display_esc_bad.out0000644000542200017500000000040115125463617023255 0ustar mahmoudyfreeshell%Error: t/t_display_esc_bad.v:9:16: Unknown escape sequence: \x 9 | $display("\x\y\z"); | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_if_same_bad.v0000644000542200017500000000212215125463617022021 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug3806 module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [3:0] in; tri [3:0] bus = in; int never_driven; int never_forced; task force_bus; force bus[1:0] = 2'b10; endtask task release_bus; release bus; endtask // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 0) begin in <= 4'b0101; end else if (cyc == 10) begin $display("10"); end else if (cyc == 11) begin $display("11"); end // // bus else if (cyc == 10) begin // Should warn $display("10b"); end else if (cyc == 11) begin // Should warn $display("11b"); end // else if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.044/test_regress/t/t_mod_interface_array2.py0000755000542200017500000000073415125463617024064 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_force_select_bad.py0000755000542200017500000000076615125463617023255 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_typedef_iface_typedef4.py0000755000542200017500000000077115125463617024401 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_waiveroutput_roundtrip.v0000644000542200017500000000147315125463617024504 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs out, out2, // Inputs clk, a0, d0, d1 ); input clk; input [1:0] a0; input [7:0] d0; input [7:0] d1; output reg [31:0] out; output reg [15:0] out2; reg [7:0] mem [4]; always @(posedge clk) begin mem[a0] <= d0; // <--- Warning end always @(negedge clk) begin mem[a0] <= d1; // <--- Warning end assign out = {mem[3],mem[2],mem[1],mem[0]}; always @(posedge clk) begin out2[7:0] <= d0; // <--- Warning end always @(negedge clk) begin out2[15:8] <= d0; // <--- Warning end endmodule verilator-5.044/test_regress/t/t_uniqueif_fail1.py0000755000542200017500000000131415125463617022701 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_uniqueif.v" test.compile(v_flags2=['+define+FAILING_ASSERTION1'], verilator_flags2=['--assert'], nc_flags2=['+assert'], fails=test.nc) test.execute(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_class_param_noinit.py0000755000542200017500000000073415125463617023652 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_class_extends_param_unused.py0000755000542200017500000000073415125463617025407 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_class_method_struct.v0000644000542200017500000000126715125463617023672 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 typedef struct packed { int x; int y; int z; } my_struct; class Cls; function my_struct get_struct; my_struct s; s.x = 1; s.y = 2; s.z = 3; return s; endfunction endclass : Cls module t; initial begin Cls c = new; my_struct s = c.get_struct; if (s.x != 1) $stop; if (s.y != 2) $stop; if (s.z != 3) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_xml_debugcheck.out0000644000542200017500000031037215125463617023127 0ustar mahmoudyfreeshell verilator-5.044/test_regress/t/t_stream_unpack_narrower.v0000644000542200017500000000076315125463617024374 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 module t; logic [30:0] packed_data; logic [60:0] packed_data2; logic [7:0] stream[4]; initial begin packed_data = 31'h12345678; {>>{stream}} = packed_data; packed_data = {>>{stream}}; stream = {>>{packed_data2}}; {>>{packed_data2}} = stream; end endmodule verilator-5.044/test_regress/t/t_opt_table_real.v0000644000542200017500000000127015125463617022567 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024. // SPDX-License-Identifier: CC0-1.0 module t ( // Inputs clk ); input clk; reg [2:0] cyc; real x; initial cyc = 0; always @(posedge clk) cyc <= cyc + 1; always @(cyc) begin case (cyc) 3'd0: x = 1.0; 3'd1: x = 2.0; 3'd2: x = 3.0; 3'd4: x = 5.0; 3'd5: x = 6.0; default: x = 0.0; endcase end always @(posedge clk) begin $display("cyle %d = %.1f", cyc, x); if (cyc == 7) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule ; verilator-5.044/test_regress/t/t_langext_4_bad.py0000755000542200017500000000116115125463617022473 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_langext_2.v" test.leak_check_disable() # This is a lint only test. test.lint(v_flags2=["+1800-2005ext+v"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_flag_compiler_clang.py0000755000542200017500000000105315125463617023747 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_flag_compiler.v" test.compile(verilator_flags2=["--compiler clang"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_trace_jumps_do_while_saif.out0000644000542200017500000000214315125463617025345 0ustar mahmoudyfreeshell// Generated by verilated_saif (SAIFILE (SAIFVERSION "2.0") (DIRECTION "backward") (PROGRAM_NAME "Verilator") (DIVIDER / ) (TIMESCALE 1ps) (DURATION 10) (INSTANCE top (NET (clk (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) ) (INSTANCE t (NET (clk (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) ) (INSTANCE unnamedblk1 (NET (results\[0\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) (results\[1\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) (results\[2\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) (results\[3\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) (results\[4\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) (results\[5\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) (results\[6\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) (results\[7\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) (results\[8\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) (results\[9\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) (results\[10\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) (results\[11\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) ) ) ) ) ) verilator-5.044/test_regress/t/t_vpi_finish.py0000755000542200017500000000103115125463617022132 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["t/t_vpi_finish_c.cpp"], verilator_flags2=["--vpi"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_stream.py0000755000542200017500000000073415125463617021300 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_interface_array_nocolon.v0000644000542200017500000000324015125463617024477 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Functionally demonstrate an array of interfaces // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Mike Popoloski. // SPDX-License-Identifier: CC0-1.0 interface foo_intf ( input x ); endinterface module foo_subm ( input x ); endmodule module t (); localparam N = 3; wire [2:0] X = 3'b110; // Should not cause ASCRANGE warning, as no harm in array selections. // verilator lint_on ASCRANGE foo_intf foo1 [N] (.x(1'b1)); foo_subm sub1 [N] (.x(1'b1)); // Will cause ASCRANGE warning? // verilator lint_off ASCRANGE foo_intf foos [N] (.x(X)); foo_intf fool [1:3] (.x(X)); foo_intf foom [3:1] (.x(X)); foo_subm subs [N] (.x(X)); foo_subm subl [1:3] (.x(X)); foo_subm subm [3:1] (.x(X)); initial begin // Check numbering with 0 first // NC has a bug here if (foos[0].x !== 1'b1) $stop; if (foos[1].x !== 1'b1) $stop; if (foos[2].x !== 1'b0) $stop; // if (fool[1].x !== 1'b1) $stop; if (fool[2].x !== 1'b1) $stop; if (fool[3].x !== 1'b0) $stop; // if (foom[1].x !== 1'b0) $stop; if (foom[2].x !== 1'b1) $stop; if (foom[3].x !== 1'b1) $stop; // if (subs[0].x !== 1'b1) $stop; if (subs[1].x !== 1'b1) $stop; if (subs[2].x !== 1'b0) $stop; // if (subl[1].x !== 1'b1) $stop; if (subl[2].x !== 1'b1) $stop; if (subl[3].x !== 1'b0) $stop; // if (subm[1].x !== 1'b0) $stop; if (subm[2].x !== 1'b1) $stop; if (subm[3].x !== 1'b1) $stop; // $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_trace_dumpvars_dyn_vcd_0.py0000755000542200017500000000130315125463617024742 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_trace_dumpvars_dyn.cpp" test.top_filename = "t/t_trace_dumpvars_dyn.v" test.compile(make_main=False, verilator_flags2=["--trace-vcd --exe", test.pli_filename]) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_clk_condflop.v0000644000542200017500000000540215125463617022251 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; reg [0:0] d1; reg [2:0] d3; reg [7:0] d8; wire [0:0] q1; wire [2:0] q3; wire [7:0] q8; reg ena; condff #(12) condff (.clk(clk), .sen(1'b0), .ena(ena), .d({d8,d3,d1}), .q({q8,q3,q1})); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin //$write("%x %x %x %x\n", cyc, q8, q3, q1); cyc <= cyc + 1; if (cyc==1) begin d1 <= 1'b1; d3<=3'h1; d8<=8'h11; ena <= 1'b1; end if (cyc==2) begin d1 <= 1'b0; d3<=3'h2; d8<=8'h33; ena <= 1'b0; end if (cyc==3) begin d1 <= 1'b1; d3<=3'h3; d8<=8'h44; ena <= 1'b1; if (q8 != 8'h11) $stop; end if (cyc==4) begin d1 <= 1'b1; d3<=3'h4; d8<=8'h77; ena <= 1'b1; if (q8 != 8'h11) $stop; end if (cyc==5) begin d1 <= 1'b1; d3<=3'h0; d8<=8'h88; ena <= 1'b1; if (q8 != 8'h44) $stop; end if (cyc==6) begin if (q8 != 8'h77) $stop; end if (cyc==7) begin if (q8 != 8'h88) $stop; end // if (cyc==20) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module condff (clk, sen, ena, d, q); parameter WIDTH = 1; input clk; input sen; input ena; input [WIDTH-1:0] d; output [WIDTH-1:0] q; condffimp #(.WIDTH(WIDTH)) imp (.clk(clk), .sen(sen), .ena(ena), .d(d), .q(q)); endmodule module condffimp (clk, sen, ena, d, q); parameter WIDTH = 1; input clk; input sen; input ena; input [WIDTH-1:0] d; output reg [WIDTH-1:0] q; wire gatedclk; clockgate clockgate (.clk(clk), .sen(sen), .ena(ena), .gatedclk(gatedclk)); always @(posedge gatedclk) begin if (gatedclk === 1'bX) begin q <= {WIDTH{1'bX}}; end else begin q <= d; end end endmodule module clockgate (clk, sen, ena, gatedclk); input clk; input sen; input ena; output gatedclk; reg ena_b; wire gatedclk = clk & ena_b; // verilator lint_off COMBDLY // verilator lint_off LATCH always @(clk or ena or sen) begin if (~clk) begin ena_b <= ena | sen; end else begin if ((clk^sen)===1'bX) ena_b <= 1'bX; end end // verilator lint_on LATCH // verilator lint_on COMBDLY endmodule verilator-5.044/test_regress/t/t_trace_multi_bad.v0000644000542200017500000000037515125463617022736 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial $finish; endmodule verilator-5.044/test_regress/t/t_class_compare.py0000755000542200017500000000073415125463617022620 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_class_split.v0000644000542200017500000000115415125463617022134 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Iru Cai. // SPDX-License-Identifier: CC0-1.0 class Cls1; int ctr; task run(); $display("%d", ctr); ctr = ctr + 1; endtask: run endclass; class Cls2 extends Cls1; task runtask(); run(); run(); run(); run(); run(); run(); endtask: runtask endclass module top; Cls2 o; initial begin o = new; o.runtask(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_randomize_inline_var_ctl_bad.out0000644000542200017500000000373715125463617026035 0ustar mahmoudyfreeshell%Error: t/t_randomize_inline_var_ctl_bad.v:12:23: 'randomize()' argument must be a variable contained in 'Foo' : ... note: In instance 't' 12 | void'(randomize(y)); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_randomize_inline_var_ctl_bad.v:26:46: 'randomize()' argument must be a variable contained in 'foo' : ... note: In instance 't' 26 | void'(foo.randomize(x, foo.x, null, qux.x, bar.y, 0 + 1, x ** 2)); | ^ %Error: t/t_randomize_inline_var_ctl_bad.v:26:53: 'randomize()' argument must be a variable contained in 'foo' : ... note: In instance 't' 26 | void'(foo.randomize(x, foo.x, null, qux.x, bar.y, 0 + 1, x ** 2)); | ^ %Error: t/t_randomize_inline_var_ctl_bad.v:26:59: 'randomize()' argument must be a variable contained in 'foo' : ... note: In instance 't' 26 | void'(foo.randomize(x, foo.x, null, qux.x, bar.y, 0 + 1, x ** 2)); | ^ %Error: t/t_randomize_inline_var_ctl_bad.v:26:66: 'randomize()' argument must be a variable contained in 'foo' : ... note: In instance 't' 26 | void'(foo.randomize(x, foo.x, null, qux.x, bar.y, 0 + 1, x ** 2)); | ^~ %Error: t/t_randomize_inline_var_ctl_bad.v:26:37: Cannot pass more arguments to 'randomize(null)' : ... note: In instance 't' 26 | void'(foo.randomize(x, foo.x, null, qux.x, bar.y, 0 + 1, x ** 2)); | ^~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_class_local_nested_bad.v0000644000542200017500000000077715125463617024255 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class NodeList; class Node; static local string name; endclass string name; function new(); name = Node::name; endfunction endclass module t; initial begin NodeList n = new; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_gate_width_bad.v0000644000542200017500000000111615125463617022537 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [1:0] in; wire [2:0] out; // verilator lint_off WIDTH buf buf1 (out[0], 1); // <--- BAD wrong connection width buf buf2[0:0] (out[1], 2'b01); // <--- BAD wrong connection width buf buf3[0:0] (out[2], in[1:0]); // <--- BAD wrong connection width buf buf4[3:0] (out[2], in[1:0]); // <--- BAD wrong connection width initial $stop; endmodule verilator-5.044/test_regress/t/t_force_release.py0000755000542200017500000000102715125463617022577 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--binary"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_preproc_eof_qqq_bad.py0000755000542200017500000000076615125463617024005 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_property_named.py0000755000542200017500000000077115125463617023036 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert']) test.execute() test.passes() verilator-5.044/test_regress/t/t_queue_class.v0000644000542200017500000000160015125463617022121 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; class Cls; int que[$]; task push_data(int val); que.push_back(val); endtask function logic ok; return '1; endfunction endclass initial begin Cls c2 [1:0]; Cls cq[$]; c2[0] = new(); c2[0].push_data(20); // Works if (c2[0].que.size() != 1) $stop; c2[0].que.push_back(10); // Unsupported if (c2[0].que.size() != 2) $stop; // Test there's no side effect warning on iteration foreach (cq[i]) case (cq[i].ok()) '0: $stop; '1: $stop; endcase $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_hier_block1_bad.v0000644000542200017500000000204515125463617022604 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Yutetsu TAKATSUKASA // SPDX-License-Identifier: Unlicense `define HIER_BLOCK /*verilator hier_block*/ interface byte_ifs(input clk); logic [7:0] data; modport sender(input clk, output data); modport receiver(input clk, input data); endinterface; module t (/*AUTOARG*/ // Inputs clk ); `HIER_BLOCK // Top module can not be a hierarchy block input wire clk; wire [7:0] out0; int count = 0; byte_ifs in_ifs(.clk(clk)); byte_ifs out_ifs(.clk(clk)); assign in_ifs.data = out0; sub0 i_sub0(.clk(clk), .in(count), .out(out0)); sub1 i_sub1(.in(in_ifs), .out(out_ifs)); endmodule module sub0 ( input wire clk, input wire [7:0] in, output wire [7:0] out); `HIER_BLOCK logic [7:0] ff; always_ff @(posedge clk) ff <= in; assign out = ff; endmodule module sub1 (byte_ifs.receiver in, byte_ifs.sender out); `HIER_BLOCK assign out.data = in.data; endmodule verilator-5.044/test_regress/t/t_unopt_converge_initial.v0000644000542200017500000000074215125463617024364 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs x, // Inputs clk ); `ifdef ALLOW_UNOPT /*verilator lint_off UNOPTFLAT*/ `endif input clk; output [31:0] x; // Avoid eliminating x reg [31:0] x; always @* begin x = x ^ $random; end endmodule verilator-5.044/test_regress/t/t_xml_flat_no_inline_mod.v0000644000542200017500000000062615125463617024316 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module foo(input logic i_clk); /* verilator no_inline_module */ endmodule // --flatten forces inlining of 'no_inline_module' module foo. module top(input logic i_clk); foo f(.*); endmodule verilator-5.044/test_regress/t/t_trace_dumpvars_dyn_fst_1.py0000755000542200017500000000130315125463617024763 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_trace_dumpvars_dyn.cpp" test.top_filename = "t/t_trace_dumpvars_dyn.v" test.compile(make_main=False, verilator_flags2=["--trace-fst --exe", test.pli_filename]) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_semaphore_bad.out0000644000542200017500000000054215125463617022747 0ustar mahmoudyfreeshell%Error: t/t_semaphore_bad.v:12:13: Class method 'bad_method' not found in class 'semaphore' : ... note: In instance 't' 12 | if (s.bad_method() != 0) $stop; | ^~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_mod_param_class_typedef7.py0000755000542200017500000000077115125463617024741 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_cover_expr_dyn_array_class.v0000644000542200017500000000114415125463617025224 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Class1; int value0 = 7; endclass module t; initial begin int i = 0; Class1 q[] = new [15]; for (int j = 0; j < 15; j = j + 1) begin Class1 x = new; q[j] = x; end while (i < 15) begin if ((q[i].value0 > 8) || (q[i].value0 < 5)) $stop; i += 1; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_std_randomize_bad1.out0000644000542200017500000000122415125463617023705 0ustar mahmoudyfreeshell%Error: t/t_std_randomize_bad1.v:12:36: Non-variable arguments for 'std::randomize()'. : ... note: In instance 't_std_randomize_bad1' 12 | success = std::randomize(a + 1); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_std_randomize_bad1.v:19:30: 'std::randomize()' does not accept 'null' as arguments. : ... note: In instance 't_std_randomize_bad1' 19 | void'(std::randomize(null)); | ^~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_xml_first.out0000644000542200017500000001112115125463617022160 0ustar mahmoudyfreeshell verilator-5.044/test_regress/t/t_flag_noop_bad.out0000644000542200017500000000032615125463617022730 0ustar mahmoudyfreeshell%Error: verilator: Need --binary, --cc, --sc, --dpi-hdr-only, --lint-only, --xml-only, --json-only or --E option ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. verilator-5.044/test_regress/t/t_case_inside_call_count.py0000755000542200017500000000107315125463617024453 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--stats']) test.execute() test.file_grep(test.stats, r'Impure case expressions\s+(\d+)', 2) test.passes() verilator-5.044/test_regress/t/t_json_only_tag.out0000644000542200017500000003515015125463617023026 0ustar mahmoudyfreeshell{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED", "modulesp": [ {"type":"MODULE","name":"m","addr":"(E)","loc":"d,12:8,12:9","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"m","level":1,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"clk_ip","addr":"(F)","loc":"d,14:11,14:17","dtypep":"(G)","origName":"clk_ip","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"rst_ip","addr":"(H)","loc":"d,15:11,15:17","dtypep":"(G)","origName":"rst_ip","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"foo_op","addr":"(I)","loc":"d,16:11,16:17","dtypep":"(G)","origName":"foo_op","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"TYPEDEF","name":"my_struct","addr":"(J)","loc":"d,25:6,25:15","dtypep":"(K)","attrPublic":false,"isUnderClass":false,"childDTypep": [],"attrsp": []}, {"type":"CELL","name":"itop","addr":"(L)","loc":"d,29:8,29:12","origName":"itop","recursive":false,"modp":"(M)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []}, {"type":"VAR","name":"itop","addr":"(N)","loc":"d,29:8,29:12","dtypep":"(O)","origName":"itop__Viftop","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"IFACEREF","dtypeName":"","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"this_struct","addr":"(P)","loc":"d,31:14,31:25","dtypep":"(Q)","origName":"this_struct","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"dotted","addr":"(R)","loc":"d,33:16,33:22","dtypep":"(S)","origName":"dotted","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"ALWAYS","name":"","addr":"(T)","loc":"d,33:23,33:24","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(U)","loc":"d,33:23,33:24","dtypep":"(S)", "rhsp": [ {"type":"VARXREF","name":"value","addr":"(V)","loc":"d,33:30,33:35","dtypep":"(W)","containsGenBlock":false,"dotted":"itop","inlinedDots":"","access":"RD","varp":"(X)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"dotted","addr":"(Y)","loc":"d,33:16,33:22","dtypep":"(S)","access":"WR","varp":"(R)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"TASK","name":"f","addr":"(Z)","loc":"d,35:18,35:19","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"f","fvarp": [],"classOrPackagep": [], "stmtsp": [ {"type":"VAR","name":"m","addr":"(AB)","loc":"d,35:33,35:34","dtypep":"(BB)","origName":"m","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":true,"isStdRandomizeArg":false,"lifetime":"VAUTOMI","varType":"PORT","dtypeName":"string","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"DISPLAY","name":"","addr":"(CB)","loc":"d,36:7,36:15", "fmtp": [ {"type":"SFORMATF","name":"%@","addr":"(DB)","loc":"d,36:7,36:15","dtypep":"(BB)", "exprsp": [ {"type":"VARREF","name":"m","addr":"(EB)","loc":"d,36:22,36:23","dtypep":"(BB)","access":"RD","varp":"(AB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"scopeNamep": []} ],"filep": []} ],"scopeNamep": []}, {"type":"INITIAL","name":"","addr":"(FB)","loc":"d,39:4,39:11","isSuspendable":false,"needProcess":false, "stmtsp": [ {"type":"BEGIN","name":"","addr":"(GB)","loc":"d,39:12,39:17","implied":false,"needProcess":false,"unnamed":true,"declsp": [], "stmtsp": [ {"type":"STMTEXPR","name":"","addr":"(HB)","loc":"d,41:7,41:8", "exprp": [ {"type":"TASKREF","name":"f","addr":"(IB)","loc":"d,41:7,41:8","dtypep":"(JB)","dotted":"","taskp":"(Z)","classOrPackagep":"UNLINKED","namep": [], "pinsp": [ {"type":"ARG","name":"","addr":"(KB)","loc":"d,41:9,41:736", "exprp": [ {"type":"CONST","name":"\\\"\\001\\002\\003\\004\\005\\006\\007\\010\\t\\n\\013\\014\\r\\016\\017\\020\\021\\022\\023\\024\\025\\026\\027\\030\\031\\032\\033\\034\\035\\036\\037 !\\\"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\\\]^_`abcdefghijklmnopqrstuvwxyz{|}~\\177\\200\\201\\202\\203\\204\\205\\206\\207\\210\\211\\212\\213\\214\\215\\216\\217\\220\\221\\222\\223\\224\\225\\226\\227\\230\\231\\232\\233\\234\\235\\236\\237\\240\\241\\242\\243\\244\\245\\246\\247\\250\\251\\252\\253\\254\\255\\256\\257\\260\\261\\262\\263\\264\\265\\266\\267\\270\\271\\272\\273\\274\\275\\276\\277\\300\\301\\302\\303\\304\\305\\306\\307\\310\\311\\312\\313\\314\\315\\316\\317\\320\\321\\322\\323\\324\\325\\326\\327\\330\\331\\332\\333\\334\\335\\336\\337\\340\\341\\342\\343\\344\\345\\346\\347\\350\\351\\352\\353\\354\\355\\356\\357\\360\\361\\362\\363\\364\\365\\366\\367\\370\\371\\372\\373\\374\\375\\376\\377\\\"","addr":"(LB)","loc":"d,41:9,41:736","dtypep":"(BB)"} ]} ],"scopeNamep": []} ]} ]} ]} ]}, {"type":"IFACE","name":"ifc","addr":"(M)","loc":"d,7:11,7:14","origName":"ifc","level":2,"modPublic":false,"inLibrary":true,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"value","addr":"(X)","loc":"d,8:12,8:17","dtypep":"(W)","origName":"value","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"MODPORT","name":"out_modport","addr":"(MB)","loc":"d,9:12,9:23", "varsp": [ {"type":"MODPORTVARREF","name":"value","addr":"(NB)","loc":"d,9:32,9:37","direction":"OUTPUT","varp":"(X)","exprp": []} ]} ]} ],"filesp": [], "miscsp": [ {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(JB)", "typesp": [ {"type":"VOIDDTYPE","name":"","addr":"(JB)","loc":"d,41:7,41:8","dtypep":"(JB)","generic":false}, {"type":"BASICDTYPE","name":"integer","addr":"(W)","loc":"d,8:4,8:11","dtypep":"(W)","keyword":"integer","range":"31:0","generic":true,"signed":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(G)","loc":"d,14:11,14:17","dtypep":"(G)","keyword":"logic","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(OB)","loc":"d,21:7,21:12","dtypep":"(OB)","keyword":"logic","generic":false,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(PB)","loc":"d,22:7,22:12","dtypep":"(PB)","keyword":"logic","generic":false,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(QB)","loc":"d,23:7,23:12","dtypep":"(QB)","keyword":"logic","generic":false,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(RB)","loc":"d,24:7,24:12","dtypep":"(RB)","keyword":"logic","generic":false,"rangep": []}, {"type":"STRUCTDTYPE","name":"m.my_struct","addr":"(K)","loc":"d,20:12,20:18","dtypep":"(K)","packed":true,"isFourstate":true,"generic":false,"classOrPackagep":"UNLINKED", "membersp": [ {"type":"MEMBERDTYPE","name":"clk","addr":"(SB)","loc":"d,21:19,21:22","dtypep":"(OB)","isConstrainedRand":false,"name":"clk","tag":"this is clk","generic":false,"refDTypep":"(OB)","childDTypep": [],"valuep": []}, {"type":"MEMBERDTYPE","name":"k","addr":"(TB)","loc":"d,22:19,22:20","dtypep":"(PB)","isConstrainedRand":false,"name":"k","tag":"","generic":false,"refDTypep":"(PB)","childDTypep": [],"valuep": []}, {"type":"MEMBERDTYPE","name":"enable","addr":"(UB)","loc":"d,23:19,23:25","dtypep":"(QB)","isConstrainedRand":false,"name":"enable","tag":"enable","generic":false,"refDTypep":"(QB)","childDTypep": [],"valuep": []}, {"type":"MEMBERDTYPE","name":"data","addr":"(VB)","loc":"d,24:19,24:23","dtypep":"(RB)","isConstrainedRand":false,"name":"data","tag":"data","generic":false,"refDTypep":"(RB)","childDTypep": [],"valuep": []} ]}, {"type":"IFACEREFDTYPE","name":"","addr":"(O)","loc":"d,29:8,29:12","dtypep":"(O)","isPortDecl":false,"isVirtual":false,"cellName":"itop","ifaceName":"ifc","modportName":"","generic":false,"ifacep":"UNLINKED","cellp":"(L)","modportp":"UNLINKED","paramsp": []}, {"type":"BASICDTYPE","name":"logic","addr":"(S)","loc":"d,31:27,31:28","dtypep":"(S)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, {"type":"REFDTYPE","name":"my_struct","addr":"(WB)","loc":"d,31:4,31:13","dtypep":"(K)","generic":false,"typedefp":"UNLINKED","refDTypep":"(K)","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []}, {"type":"UNPACKARRAYDTYPE","name":"","addr":"(Q)","loc":"d,31:26,31:27","dtypep":"(Q)","isCompound":false,"declRange":"[0:1]","generic":false,"refDTypep":"(WB)","childDTypep": [], "rangep": [ {"type":"RANGE","name":"","addr":"(XB)","loc":"d,31:26,31:27","ascending":true,"fromBracket":true, "leftp": [ {"type":"CONST","name":"32'h0","addr":"(YB)","loc":"d,31:27,31:28","dtypep":"(S)"} ], "rightp": [ {"type":"CONST","name":"32'h1","addr":"(ZB)","loc":"d,31:27,31:28","dtypep":"(S)"} ]} ]}, {"type":"BASICDTYPE","name":"string","addr":"(BB)","loc":"d,35:26,35:32","dtypep":"(BB)","keyword":"string","generic":true,"rangep": []} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ {"type":"MODULE","name":"@CONST-POOL@","addr":"(AC)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(BC)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(AC)","varsp": [],"blocksp": [],"inlinesp": []} ]} ]} ]} verilator-5.044/test_regress/t/t_tri_pull_bad.py0000755000542200017500000000077615125463617022453 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_lint_blkseq_bad.out0000644000542200017500000000416115125463617023274 0ustar mahmoudyfreeshell%Warning-BLKSEQ: t/t_lint_blkseq_bad.v:22:14: Blocking assignment '=' in sequential logic process : ... note: In instance 't' : ... Suggest using delayed assignment '<=' 22 | sync_blk = 1'b1; | ^ ... For warning description see https://verilator.org/warn/BLKSEQ?v=latest ... Use "/* verilator lint_off BLKSEQ */" and lint_on around source to disable this message. %Warning-BLKSEQ: t/t_lint_blkseq_bad.v:23:15: Blocking assignment '=' in sequential logic process : ... note: In instance 't' : ... Suggest using delayed assignment '<=' 23 | sync_blk2 = 1'b1; | ^ %Warning-BLKSEQ: t/t_lint_blkseq_bad.v:66:29: Blocking assignment '=' in sequential logic process : ... note: In instance 't.a' : ... Suggest using delayed assignment '<=' 66 | always @(posedge clk) out = 1; | ^ %Warning-BLKSEQ: t/t_lint_blkseq_bad.v:75:29: Blocking assignment '=' in sequential logic process : ... note: In instance 't.b' : ... Suggest using delayed assignment '<=' 75 | always @(posedge clk) out = 1; | ^ %Warning-COMBDLY: t/t_lint_blkseq_bad.v:29:16: Non-blocking assignment '<=' in combinational logic process : ... This will be executed as a blocking assignment '='! 29 | combo_nblk <= 1'b1; | ^~ ... For warning description see https://verilator.org/warn/COMBDLY?v=latest ... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message. *** See https://verilator.org/warn/COMBDLY?v=latest before disabling this, else you may end up with different sim results. %Error: Exiting due to verilator-5.044/test_regress/t/t_func_check.v0000644000542200017500000000323515125463617021706 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off WIDTH // verilator lint_off VARHIDDEN module t ( clk ); input clk; integer cyc = 0; reg [63:0] crc; initial crc = 64'h1; chk chk (.clk (clk), .rst_l (1'b1), .expr (|crc) ); always @ (posedge clk) begin cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; if (cyc==0) begin crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<90) begin end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module chk (input clk, input rst_l, input expr); int errors; task printerr; input [8*64:1] msg; begin errors = errors + 1; $write("%%Error: %0s\n", msg); $stop; end endtask always @(posedge clk) begin if (rst_l) begin if (expr == 1'b0) begin printerr("expr not asserted"); end end end wire noxs = ((expr ^ expr) == 1'b0); // TODO: this test is dodgy, noxs can be proven constant, so this block // should never relly trigger... reg hasx; always @ (noxs) begin if (noxs) begin hasx = 1'b0; end else begin hasx = 1'b1; end end always @(posedge clk) begin if (rst_l) begin if (hasx) begin printerr("expr has unknowns"); end end end endmodule verilator-5.044/test_regress/t/t_bitsel_slice.v0000644000542200017500000000404415125463617022256 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; logic [2:0] [1:0] in; always @* in = crc[5:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) logic [1:0] [1:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out/*[1:0][1:0]*/), // Inputs .clk (clk), .in (in/*[2:0][1:0]*/)); // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, out[1],out[0]}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hdc21e42d85441511 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs clk, in ); //bug717 input clk; input logic [2:0][1:0] in; output logic [1:0][1:0] out; always @(posedge clk) begin out <= in[2 -: 2]; end endmodule verilator-5.044/test_regress/t/t_foreach_bad.py0000755000542200017500000000076615125463617022227 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_setuphold.v0000644000542200017500000000466015125463617021630 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk, d, t_in ); input clk; input d; input t_in; wire delayed_CLK; wire delayed_D; reg notifier; wire [1:0] BL_X = 2'b11; wire [5:0] BL_X2; wire BL_0; wire [3:0] BL_1 = 4'b1100; wire fake_CLK; wire fake_D; logic[3:0] sh1 = 1; logic[3:0] sh2 = 2; logic[3:0] sh3 = 3; logic[3:0] sh4 = 4; logic[3:0] sh5 = 5; logic[3:0] sh6 = 6; int cyc = 0; specify $setuphold (posedge clk, negedge d, 0, 0, notifier, (0:0:0), 0, delayed_CLK, delayed_D); $setuphold (posedge sh1, negedge sh3, 0, 0, notifier,,, sh2, sh4); $setuphold (posedge sh5, negedge d, 0, 0, notifier,,, sh6); $setuphold (posedge clk, negedge d, 0, 0, notifier, (1:2:3), (0:0:0)); $setuphold (posedge clk, negedge d, 0, 0, notifier, (1:2:3)); $setuphold (posedge clk, negedge d, 0, 0, notifier); $setuphold (posedge clk, negedge d, 0, 0); $setuphold (posedge clk, negedge d, 0, 0); $setuphold (posedge clk, negedge d, (0:0:0), (0:0:0)); $setuphold (posedge clk, negedge d, 0:0:0, 0:0:0); $setuphold (posedge clk, negedge d, 0, 0,,,,,); $setuphold (posedge clk &&& sh1, BL_X[0], 0, 0, ,,,delayed_CLK, BL_0); $setuphold (posedge clk &&& sh1, BL_1, 0, 0, ,,,delayed_CLK, BL_X2[4:1]); $setuphold (fake_CLK, fake_D &&& sh1, 0, 0); $setuphold (posedge fake_CLK, posedge fake_D &&& sh1, 0, 0); $setuphold (negedge fake_CLK, negedge fake_D &&& sh1, 0, 0); $setuphold (edge fake_CLK, edge fake_D &&& sh1, 0, 0); $setuphold (edge [0Z, z1, 10] fake_CLK, edge [01, x0, 0X] fake_CLK &&& sh1, 0, 0); $setuphold (posedge clk, negedge d, 0, 0, notifier, (0:0:0), 0, t_in); endspecify initial begin if (sh1 != sh2 || sh3 != sh4) begin $stop; end if (sh5 != sh6) begin $stop; end if (BL_0 != BL_X[0] || BL_1 != BL_X2[4:1]) begin $stop; end end always @(posedge clk) begin cyc <= cyc + 1; $display("%d %d", clk, delayed_CLK); if (delayed_CLK != clk || delayed_D != d) begin $stop; end if (cyc == 10) begin $display("*-* All Finished *-*"); $finish; end end endmodule verilator-5.044/test_regress/t/t_trace_public_sig.py0000755000542200017500000000155515125463617023305 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_trace_public.v" test.golden_filename = "t/t_trace_public.out" test.compile(make_top_shell=False, make_main=False, v_flags2=["-DATTRIBUTES --trace-vcd --exe", test.pli_filename]) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) # vcd_identical doesn't detect "$var a.b;" vs "$scope module a; $var b;" test.file_grep(test.trace_filename, r'module glbl') test.passes() verilator-5.044/test_regress/t/t_bitsel_enum.py0000755000542200017500000000073415125463617022313 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_event_control_timing.py0000755000542200017500000000110715125463617024230 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_event_control.v" test.compile(verilator_flags2=["--timing"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_embed1_c.cpp0000644000542200017500000001071015125463617021566 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2011-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "../t_embed1_child/Vt_embed1_child.h" #include "svdpi.h" #include //====================================================================== // clang-format off #if defined(VERILATOR) # include "Vt_embed1__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif // clang-format on #include "verilated.h" #ifdef NEED_EXTERNS extern "C" { extern void t_embed_child_initial(); extern void t_embed_child_final(); extern void t_embed_child_eval(); extern void t_embed_child_io_eval(); // TODO real function params here } #endif //====================================================================== extern int T_Embed_Child_Unique; int T_Embed_Child_Unique = 0; // Address used for uniqueness Vt_embed1_child* __get_modelp() { svScope scope = svGetScope(); if (!scope) { vl_fatal(__FILE__, __LINE__, __FILE__, "svGetScope failed"); return nullptr; } void* __modelp = svGetUserData(scope, &T_Embed_Child_Unique); if (!__modelp) { // Create the model const char* scopenamep = svGetNameFromScope(scope); if (!scopenamep) vl_fatal(__FILE__, __LINE__, __FILE__, "svGetNameFromScope failed"); __modelp = new Vt_embed1_child{scopenamep}; if (svPutUserData(scope, &T_Embed_Child_Unique, __modelp)) { vl_fatal(__FILE__, __LINE__, __FILE__, "svPutUserData failed"); } } return reinterpret_cast(__modelp); } void __delete_modelp() { svScope scope = svGetScope(); if (!scope) { vl_fatal(__FILE__, __LINE__, __FILE__, "svGetScope failed"); return; } void* __modelp = svGetUserData(scope, &T_Embed_Child_Unique); if (__modelp) { delete reinterpret_cast(__modelp); __modelp = nullptr; if (svPutUserData(scope, &T_Embed_Child_Unique, __modelp)) { vl_fatal(__FILE__, __LINE__, __FILE__, "svPutUserData failed"); } } } void t_embed_child_initial() { VL_DEBUG_IF(VL_PRINTF(" t_embed1_child_initial\n");); Vt_embed1_child* __modelp = __get_modelp(); __modelp->eval(); } void t_embed_child_final() { VL_DEBUG_IF(VL_PRINTF(" t_embed1_child_final\n");); Vt_embed1_child* __modelp = __get_modelp(); __modelp->final(); __delete_modelp(); } void t_embed_child_eval() { VL_DEBUG_IF(VL_PRINTF(" t_embed1_child_eval\n");); Vt_embed1_child* __modelp = __get_modelp(); __modelp->eval(); } void t_embed_child_io_eval(unsigned char clk, unsigned char bit_in, const svBitVecVal* vec_in, const svBitVecVal* wide_in, unsigned char is_ref, unsigned char* bit_out, svBitVecVal* vec_out, svBitVecVal* wide_out, unsigned char* did_init_out) { VL_DEBUG_IF(VL_PRINTF(" t_embed1_child_io_eval\n");); Vt_embed1_child* __modelp = __get_modelp(); VL_DEBUG_IF(VL_PRINTF("[%0ld] in clk=%x b=%x V=%x R=%x\n", // (long int)(VL_TIME_Q()), clk, bit_in, vec_in[0], is_ref);); __modelp->clk = clk; __modelp->bit_in = bit_in; __modelp->vec_in = vec_in[0]; __modelp->wide_in[0] = wide_in[0]; __modelp->wide_in[1] = wide_in[1]; __modelp->wide_in[2] = wide_in[2]; __modelp->wide_in[3] = wide_in[3]; __modelp->is_ref = is_ref; // __modelp->eval(); // TODO maybe we should look at a "change detect" to know if we need to copy // out the variables; can return this value to the caller verilog code too // *bit_out = __modelp->bit_out; vec_out[0] = __modelp->vec_out; wide_out[0] = __modelp->wide_out[0]; wide_out[1] = __modelp->wide_out[1]; wide_out[2] = __modelp->wide_out[2]; wide_out[3] = __modelp->wide_out[3]; *did_init_out = __modelp->did_init_out; VL_DEBUG_IF(VL_PRINTF("[%0ld] out b=%x V=%x DI=%x\n", // (long int)(VL_TIME_Q()), *bit_out, *vec_out, *did_init_out);); } verilator-5.044/test_regress/t/t_case_string.py0000755000542200017500000000073415125463617022306 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_strength_bufif1.py0000755000542200017500000000077315125463617023102 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_randomize_this.py0000755000542200017500000000073415125463617023024 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_param_type_id_bad.py0000755000542200017500000000077615125463617023436 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_runflag_bad.py0000755000542200017500000000226415125463617022251 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile() test.execute(all_run_flags=["+verilator+bad+flag+testing"], fails=True, expect_filename="t/" + test.name + "__a.out") test.execute(all_run_flags=["+verilator+rand+reset+-1"], fails=True, expect_filename="t/" + test.name + "__b.out") test.execute(all_run_flags=["+verilator+rand+reset+3"], fails=True, expect_filename="t/" + test.name + "__c.out") test.execute(all_run_flags=["+verilator+prof+exec+window+0"], fails=True, expect_filename="t/" + test.name + "__d.out") test.execute(all_run_flags=["+verilator+prof+exec+window+1000000000000000000000000"], fails=True, expect_filename="t/" + test.name + "__e.out") test.passes() verilator-5.044/test_regress/t/t_opt_merge_cond_no_merge.py0000755000542200017500000000163515125463617024645 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_opt_merge_cond.v" test.compile(verilator_flags2=["-unroll-count 64", "--stats", "-fno-merge-cond"]) test.execute() if test.vlt: # Note, with vltmt this might be split differently, so only checking vlt test.file_grep_not(test.stats, r'Optimizations, MergeCond merges\s+(\d+)') test.file_grep_not(test.stats, r'Optimizations, MergeCond merged items\s+(\d+)') test.file_grep_not(test.stats, r'Optimizations, MergeCond longest merge\s+(\d+)') test.passes() verilator-5.044/test_regress/t/t_attr_parenstar.v0000644000542200017500000000143615125463617022650 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; always @(*) begin if (clk) begin end end always @(* ) begin if (clk) begin end end // Not legal in some simulators, legal in others // always @(* /*cmt*/ ) begin // if (clk) begin end // end // Not legal in some simulators, legal in others // always @(* // cmt // ) begin // if (clk) begin end // end always @ (* ) begin if (clk) begin end end initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_interface_virtual_unused.v0000644000542200017500000000062515125463617024707 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Arkadiusz Kozdra. // SPDX-License-Identifier: CC0-1.0 // See also t_interface_virtual.v interface QBus(); endinterface module t; virtual QBus q8; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_param_passed_to_port.v0000644000542200017500000000115415125463617024021 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 parameter int HwDataAttr[1] = '{1}; module flash_mp_data_region_sel ( input int region_attrs_i[1] ); initial begin int o = 0; for (int i = 0; i < 1; i++) begin o = region_attrs_i[i]; end if (o != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module t; flash_mp_data_region_sel u_hw_sel (.region_attrs_i(HwDataAttr)); endmodule verilator-5.044/test_regress/t/t_preproc_cmtend_bad.out0000644000542200017500000000030415125463617023764 0ustar mahmoudyfreeshell%Error: t/t_preproc_cmtend_bad.v:10:1: EOF in '/* ... */' block comment ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_gen_index.py0000755000542200017500000000071415125463617021743 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.044/test_regress/t/t_preproc_inc3.vh0000644000542200017500000000120615125463617022350 0ustar mahmoudyfreeshell// DESCRIPTION: Verilog::Preproc: Example source code // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2000-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifndef _EXAMPLE_INC2_V_ `define _EXAMPLE_INC2_V_ 1 `define _EMPTY // FOO At file `__FILE__ line `__LINE__ `line `__LINE__ "inc3_a_filename_from_line_directive_with_LINE" 0 At file `__FILE__ line `__LINE__ `line 100 "inc3_a_filename_from_line_directive" 0 At file `__FILE__ line `__LINE__ `else `error "INC2 File already included once" `endif // guard `ifdef not_defined `include "NotToBeInced.vh" `endif verilator-5.044/test_regress/t/t_flag_wfatal.py0000755000542200017500000000106015125463617022245 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_flag_wfatal.v" test.lint(verilator_flags2=["-Wno-fatal"], expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_opt_table_sparse_output_split.py0000755000542200017500000000234015125463617026161 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_opt_table_sparse.v" test.golden_filename = "t/t_opt_table_sparse.out" def check_splits(expected): n = 0 for filename in test.glob_some(test.obj_dir + "/*.cpp"): if re.search(r'__ConstPool_', filename): n += 1 if n != expected: test.error("__ConstPool*.cpp not split: " + str(n)) test.compile(verilator_flags2=["--stats", "--output-split 1"]) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 1) test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 2) # Splitting should set VM_PARALLEL_BUILDS to 1 by default test.file_grep(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", r'VM_PARALLEL_BUILDS\s*=\s*1') check_splits(2) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_pp_misdef_bad.v0000644000542200017500000000061615125463617022372 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; `define DEFINED // NDEFINED isn't defined here: `NDEFINED // Botched directive (`timescale) `imescale initial $stop; // Should have failed endmodule verilator-5.044/test_regress/t/t_interface_dearray.py0000755000542200017500000000073415125463617023454 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_mod_mod.v0000644000542200017500000000066215125463617021235 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module m(); module m_in_m; endmodule program p_in_m(); endprogram interface i_in_m(); endinterface endmodule interface i(); interface i_in_i(); endinterface program p_in_i(); endprogram endinterface verilator-5.044/test_regress/t/t_lint_blkseq_loop.py0000755000542200017500000000076415125463617023350 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["-Wwarn-BLKSEQ -Wwarn-COMBDLY"]) test.passes() verilator-5.044/test_regress/t/t_virtual_interface_member_trigger.v0000755000542200017500000000353115125463617026400 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by PlanV GmbH. // SPDX-License-Identifier: CC0-1.0 `timescale 1ns/1ps interface INTF; logic x; logic y; logic z; logic [7:0] data; endinterface class Dummy; virtual INTF vif; function new(virtual INTF vif); this.vif = vif; endfunction task write_data(logic [7:0] d); vif.data = d; endtask endclass module t_virtual_interface_member_trigger(); // === Part 1: logic trigger false loop test === logic s1, s2, src_val; INTF intf_loop(); virtual INTF vif_loop; assign intf_loop.x = s1; assign intf_loop.y = src_val; assign intf_loop.z = !intf_loop.y; assign s2 = intf_loop.z; assign s1 = s2; // === Part 2: data transfer chain test === logic [7:0] data; INTF intf_read(); INTF intf_write(); assign intf_read.data = data; assign data = intf_write.data; virtual INTF vif_read, vif_write; Dummy cl_1, cl_2; initial begin // Test 1: no false loop with member-level trigger #1ns; vif_loop = intf_loop; cl_1 = new(vif_loop); #1ns; src_val = 0; #1ns; if (!(cl_1.vif.x == 1 && cl_1.vif.y == 0 && cl_1.vif.z == 1 && s1 == 1 && s2 == 1)) $stop; // Test 2: write from module #1ns; vif_read = intf_read; vif_write = intf_write; #1ns; vif_write.data = 8'hA5; #1ns; if (vif_read.data !== 8'hA5) $stop; // Test 3: write from class #1ns; cl_2 = new(vif_write); #1ns; cl_2.write_data(8'hB7); #1ns; if (vif_read.data !== 8'hB7) $stop; #5ns; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_covergroup_extends_newfirst.py0000755000542200017500000000070615125463617025652 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.044/test_regress/t/t_lib_prot.v0000644000542200017500000001504115125463617021426 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 `define DRIVE(sig) \ /* Just throw a bunch of bits at the input */ \ /* verilator lint_off WIDTH */ \ sig``_in <= {8{crc}}; \ /* verilator lint_on WIDTH */ `define CHECK(sig) \ if (cyc > 0 && sig``_in != sig``_out) begin \ $display(`"%%Error (%m) sig``_in (0x%0x) != sig``_out (0x%0x)`", \ sig``_in, sig``_out); \ $stop; \ end module t #(parameter GATED_CLK = 0) (/*AUTOARG*/ // Inputs clk ); input clk; localparam last_cyc = `ifdef TEST_BENCHMARK `TEST_BENCHMARK; `else 10; `endif genvar x; generate for (x = 0; x < 2; x = x + 1) begin: gen_loop integer cyc = 0; reg [63:0] crc = 64'h5aef0c8d_d70a4497; logic [31:0] accum_in; logic [31:0] accum_out; logic accum_bypass; logic [31:0] accum_bypass_out; logic [31:0] accum_out_expect; logic [31:0] accum_bypass_out_expect; logic s1_in; logic s1_out; logic s1up_in[2]; logic s1up_out[2]; logic [1:0] s2_in; logic [1:0] s2_out; logic [7:0] s8_in; logic [7:0] s8_out; logic [32:0] s33_in; logic [32:0] s33_out; logic [63:0] s64_in; logic [63:0] s64_out; logic [64:0] s65_in; logic [64:0] s65_out; logic [128:0] s129_in; logic [128:0] s129_out; logic [3:0] [31:0] s4x32_in; logic [3:0] [31:0] s4x32_out; /*verilator lint_off ASCRANGE*/ logic [0:15] s6x16up_in[0:1][2:0]; logic [0:15] s6x16up_out[0:1][2:0]; /*verilator lint_on ASCRANGE*/ logic [15:0] s8x16up_in[1:0][0:3]; logic [15:0] s8x16up_out[1:0][0:3]; logic [15:0] s8x16up_3d_in[1:0][0:1][0:1]; logic [15:0] s8x16up_3d_out[1:0][0:1][0:1]; wire clk_en = crc[0]; secret secret ( .accum_in, .accum_out, .accum_bypass, .accum_bypass_out, .s1_in, .s1_out, .s1up_in, .s1up_out, .s2_in, .s2_out, .s8_in, .s8_out, .s33_in, .s33_out, .s64_in, .s64_out, .s65_in, .s65_out, .s129_in, .s129_out, .s4x32_in, .s4x32_out, .s6x16up_in, .s6x16up_out, .s8x16up_in, .s8x16up_out, .s8x16up_3d_in, .s8x16up_3d_out, .clk_en, .clk); always @(posedge clk) begin `ifdef TEST_VERBOSE $display("[%0t] x=%0d, cyc=%0d accum_in=%0d accum_out=%0d accum_bypass_out=%0d", $time, x, cyc, accum_in, accum_out, accum_bypass_out); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; accum_in <= accum_in + 5; `DRIVE(s1) `DRIVE(s2) `DRIVE(s8) `DRIVE(s33) `DRIVE(s64) `DRIVE(s65) `DRIVE(s129) `DRIVE(s4x32) {s1up_in[1], s1up_in[0]} <= {^crc, ~(^crc)}; {s6x16up_in[0][0], s6x16up_in[0][1], s6x16up_in[0][2]} <= crc[47:0]; {s6x16up_in[1][0], s6x16up_in[1][1], s6x16up_in[1][2]} <= ~crc[63:16]; {s8x16up_in[0][0], s8x16up_in[0][1], s8x16up_in[0][2], s8x16up_in[0][3]} <= crc; {s8x16up_in[1][0], s8x16up_in[1][1], s8x16up_in[1][2], s8x16up_in[1][3]} <= ~crc; {s8x16up_3d_in[0][0][0], s8x16up_3d_in[0][0][1]} <= ~crc[31:0]; {s8x16up_3d_in[0][1][0], s8x16up_3d_in[0][1][1]} <= ~crc[63:32]; {s8x16up_3d_in[1][0][0], s8x16up_3d_in[1][0][1]} <= crc[31:0]; {s8x16up_3d_in[1][1][0], s8x16up_3d_in[1][1][1]} <= crc[63:32]; if (cyc == 0) begin accum_in <= x*100; accum_bypass <= '0; end else if (cyc > 0) begin if (accum_out_expect != accum_out) begin $display("%%Error: (%m) accum_out expected %0d got %0d", accum_out_expect, accum_out); $stop; end if (accum_bypass_out_expect != accum_bypass_out) begin $display("%%Error: (%m) accum_bypass_out expected %0d got %0d", accum_bypass_out_expect, accum_bypass_out); $stop; end end if (cyc == 5) accum_bypass <= '1; if (x == 0 && cyc == last_cyc) begin $display("final cycle = %0d", cyc); $write("*-* All Finished *-*\n"); $finish; end end logic possibly_gated_clk; if (GATED_CLK != 0) begin: yes_gated_clock logic clk_en_latch; // verilator lint_off COMBDLY,LATCH always_comb if (clk == '0) clk_en_latch <= clk_en; // verilator lint_on COMBDLY,LATCH assign possibly_gated_clk = clk & clk_en_latch; end else begin: no_gated_clock assign possibly_gated_clk = clk; end always @(posedge possibly_gated_clk) begin // 7 is the secret_value inside the secret module accum_out_expect <= accum_in + accum_out_expect + 7; end always @(*) begin // XSim (and maybe all event simulators?) sees the moment where // s1_in has not yet propagated to s1_out, however, they do always // both change at the same time /* verilator lint_off STMTDLY */ #1; /* verilator lint_on STMTDLY */ `CHECK(s1) `CHECK(s1up) `CHECK(s2) `CHECK(s8) `CHECK(s33) `CHECK(s64) `CHECK(s65) `CHECK(s129) `CHECK(s4x32) `CHECK(s6x16up) `CHECK(s8x16up) `CHECK(s8x16up_3d) end assign accum_bypass_out_expect = accum_bypass ? accum_in : accum_out_expect; end endgenerate endmodule verilator-5.044/test_regress/t/t_disable_outside.py0000755000542200017500000000101315125463617023133 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(timing_loop=True, verilator_flags2=["--timing"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_pgo_profoutofdate_bad.py0000755000542200017500000000100315125463617024327 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vltmt') test.compile(threads=2, fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_force_chained.v0000644000542200017500000000205015125463617022361 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop // TODO `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) // verilog_format: on module t; reg [1:0] a; wire [1:0] b = 1; bit [1:0] c; initial begin #1 a = 0; force b = a; force c = b; `checkh(a, 0); `checkh(b, 0); `checkh(c, 0); a = 1; #1; `checkh(a, 1); `checkh(b, 1); // TODO implement inter-dependency resolution between force statements `checkh(c, 1); a = 2; #1; `checkh(a, 2); `checkh(b, 2); `checkh(c, 2); a = 3; c = 3; #1; `checkh(a, 3); `checkh(b, 3); `checkh(c, 3); release b; release c; `checkh(a, 3); `checkh(b, 1); `checkh(c, 3); #1 $finish; end endmodule verilator-5.044/test_regress/t/t_flag_unroll_limit_stmt.v0000644000542200017500000000075715125463617024375 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin // verilator unroll_full for (int i = 0; i < 4; ++i) begin $display("Should unroll: %0d", i); end // verilator unroll_full for (int i = 0; i < 5; ++i) begin $display("Should NOT unroll: %0d", i); end end endmodule verilator-5.044/test_regress/t/t_vpi_unimpl.v0000644000542200017500000000206115125463617021774 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VERILATOR //We call it via $c so we can verify DPI isn't required - see bug572 `else import "DPI-C" context function int mon_check(); `endif module t (/*AUTOARG*/ // Inputs clk ); `ifdef VERILATOR `systemc_header extern "C" int mon_check(); `verilog `endif input clk; reg onebit /*verilator public_flat_rw @(posedge clk) */; integer status; // Test loop initial begin `ifdef VERILATOR status = $c32("mon_check()"); `else status = mon_check(); `endif if (status != 0) begin $write("%%Error: t_vpi_unimpl.cpp:%0d: C Test failed\n", status); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule : t verilator-5.044/test_regress/t/t_math_signed_noexpand.py0000755000542200017500000000103615125463617024157 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_math_signed.v" test.compile(verilator_flags2=['-fno-expand']) test.execute() test.passes() verilator-5.044/test_regress/t/t_constraint_dyn_queue_basic.v0000755000542200017500000000630715125463617025227 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by PlanV GmbH. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); class ConstrainedDynamicQueueArray; rand int queue_1d[$]; rand int queue[$][$]; rand int dyn[][]; rand int queue_dyn[$][]; rand int dyn_queue[][$]; rand int queue_unp[$][3]; rand int unp_queue[3][$]; rand int \array_w[ith_es]cape [3][2]; // Constraints for the queues and dynamic arrays constraint queue_constraints { foreach (queue_1d[i]) queue_1d[i] == i + 2; foreach (queue[i, j]) queue[i][j] == (2 * i) + j; } constraint dyn_constraints { dyn[0][0] == 10; dyn[1][0] inside {20, 30, 40}; dyn[1][1] > 50; dyn[0][1] < 100; dyn[0][2] inside {5, 15, 25}; } constraint queue_dyn_constraints { foreach (queue_dyn[i, j]) queue_dyn[i][j] == i + j + 3; } constraint dyn_queue_constraints { foreach (dyn_queue[i, j]) dyn_queue[i][j] == (3 * i) + j + 2; } constraint unp_queue_constraints { foreach (unp_queue[i, j]) unp_queue[i][j] == (i * 5) + j + 1; } constraint array_with_escape_constraints { \array_w[ith_es]cape [0][0] == 6; } // Constructor function new(); queue_1d = {1, 2, 3, 4}; queue = '{ '{1, 2}, '{3, 4, 5}, '{6}}; dyn = new[2]; dyn[0] = new[3]; dyn[1] = new[4]; queue_dyn = {}; queue_dyn[0] = new[3]; queue_dyn[1] = new[4]; dyn_queue = new[2]; dyn_queue[0] = {7, 8, 9}; dyn_queue[1] = {10}; queue_unp = {}; unp_queue[0] = {17, 18}; unp_queue[1] = {19}; unp_queue[2] = {20}; endfunction // Self-check function function void check(); foreach (queue_1d[i]) `checkh(queue_1d[i], i + 2) foreach (queue[i, j]) `checkh(queue[i][j], (2 * i) + j) `checkh(dyn[0][0], 10) `checkh(dyn[1][0] inside {20, 30, 40}, 1'b1) `checkh(dyn[1][1] > 50, 1'b1) `checkh(dyn[0][1] < 100, 1'b1) `checkh(dyn[0][2] inside {5, 15, 25}, 1'b1) foreach (queue_dyn[i, j]) `checkh(queue_dyn[i][j], i + j + 3) foreach (dyn_queue[i, j]) `checkh(dyn_queue[i][j], (3 * i) + j + 2) `checkh(unp_queue[0][0], (0 * 5) + 0 + 1) `checkh(unp_queue[0][1], (0 * 5) + 1 + 1) `checkh(unp_queue[1][0], (1 * 5) + 0 + 1) `checkh(unp_queue[2][0], (2 * 5) + 0 + 1) `checkh(\array_w[ith_es]cape [0][0], 6) endfunction endclass module t_constraint_dyn_queue_basic; ConstrainedDynamicQueueArray array_test; int success; initial begin $display("Test: Randomization for dynamic and mixed queues and arrays:"); array_test = new(); repeat(2) begin success = array_test.randomize(); `checkh(success, 1) array_test.check(); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_difftree.py0000755000542200017500000000161015125463617021567 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') if not os.path.exists(os.environ["VERILATOR_ROOT"] + "/bin/verilator_difftree"): test.skip("No verilator_difftree available") test.run(cmd=[ "cd " + test.obj_dir + " && " + os.environ["VERILATOR_ROOT"] + "/bin/verilator_difftree", test.t_dir + "/t_difftree.a.tree", test.t_dir + "/t_difftree.b.tree > diff.log" ], fails=1) # Testing mismatch, so exit code 1 test.files_identical(test.obj_dir + "/diff.log", test.golden_filename, 'logfile') test.passes() verilator-5.044/test_regress/t/t_mod_interface_array4.v0000644000542200017500000000331015125463617023671 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) interface intf (); integer index; endinterface module t ( clk ); input clk; intf ifa1_intf[2:1](); intf ifa2_intf[2:1](); intf ifb1_intf[1:2](); intf ifb2_intf[1:2](); int cyc; sub sub ( .clk, .cyc, .alh(ifa1_intf), .ahl(ifa2_intf), .blh(ifb1_intf), .bhl(ifb2_intf) ); always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 1) begin ifa1_intf[1].index = 'h101; ifa1_intf[2].index = 'h102; ifa2_intf[1].index = 'h201; ifa2_intf[2].index = 'h202; ifb1_intf[1].index = 'h301; ifb1_intf[2].index = 'h302; ifb2_intf[1].index = 'h401; ifb2_intf[2].index = 'h402; end end endmodule module sub ( input logic clk, input int cyc, intf alh[1:2], intf ahl[2:1], intf blh[1:2], intf bhl[2:1] ); always @(posedge clk) begin if (cyc == 5) begin `checkh(alh[1].index, 'h102); `checkh(alh[2].index, 'h101); `checkh(ahl[1].index, 'h201); `checkh(ahl[2].index, 'h202); `checkh(blh[1].index, 'h301); `checkh(blh[2].index, 'h302); `checkh(bhl[1].index, 'h402); `checkh(bhl[2].index, 'h401); $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.044/test_regress/t/t_flag_unroll_limit_stmt.out0000644000542200017500000000057315125463617024733 0ustar mahmoudyfreeshell%Error: t/t_flag_unroll_limit_stmt.v:16:5: Unrolling procedural loop with '/* verilator unroll_full */' took too long; probably this is an infinite loop, otherwise set '--unroll-limit' above 4 16 | for (int i = 0; i < 5; ++i) begin | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_udp_param_bad.v0000644000542200017500000000064215125463617022373 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Anthony Donlon. // SPDX-License-Identifier: CC0-1.0 module t; wire a, b; udp i_udp (a, b); endmodule primitive udp #( parameter A = 1 ) (o, a); output o; input a; table //o a 0 : 1; 1 : 0; endtable endprimitive verilator-5.044/test_regress/t/t_class_diamond.py0000755000542200017500000000073415125463617022605 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_incorrect_multi_driven.v0000644000542200017500000000222315125463617024363 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Adrien Le Masle. // SPDX-License-Identifier: CC0-1.0 interface test_if #(parameter int AA = 2, BB=5); logic [AA-1 : 0] a; logic [BB-1 : 0] b; logic c; logic d; modport slave (input a, input b, input c, input d); modport master (output a, output b, output c, output d); endinterface : test_if module test (input logic [28:0] a, output logic [28:0] b); always_comb begin b = a; end endmodule module multi_driven ( input logic [20-1 : 0] data_in, output logic [20-1 : 0] data_out, test_if.slave test_if_in, test_if.master test_if_out ); test test_inst ( .a({data_in, test_if_in.a, test_if_in.b, test_if_in.c, test_if_in.d}), .b({data_out, test_if_out.a, test_if_out.b, test_if_out.c, test_if_out.d})); endmodule; verilator-5.044/test_regress/t/t_protect_ids_debug.py0000755000542200017500000000126115125463617023466 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_protect_ids.v" test.compile(verilator_flags2=[ "--protect-ids", "--protect-key SECRET_KEY", "--trace-vcd", "--debug-protect", "--coverage", "-Wno-INSECURE", ], verilator_make_gmake=False) test.passes() verilator-5.044/test_regress/t/t_class_virtual_bad.py0000755000542200017500000000076315125463617023470 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_case_itemwidth.v0000644000542200017500000000561315125463617022611 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // Some inputs we'll set to random values reg [6:0] addr; reg [6:0] e0; reg [5:0] e1; reg [5:0] e2; wire [7:0] data; reg [2:0] wrapcheck_a; reg [2:0] wrapcheck_b; test test (/*AUTOINST*/ // Outputs .data (data[7:0]), // Inputs .addr (addr[6:0]), .e0 (e0[6:0]), .e1 (e1[5:0]), .e2 (e2[5:0])); always @(/*AS*/addr) begin case(addr[2:0]) 3'd0+3'd0: wrapcheck_a = 3'h0; 3'd0+3'd1: wrapcheck_a = 3'h1; 3'd0+3'd2: wrapcheck_a = 3'h2; 3'd0+3'd3: wrapcheck_a = 3'h3; default: wrapcheck_a = 3'h4; endcase case(addr[2:0]) 3'd0+0: wrapcheck_b = 3'h0; 3'd1+1: wrapcheck_b = 3'h1; 3'd2+2: wrapcheck_b = 3'h2; 3'd3+3: wrapcheck_b = 3'h3; default: wrapcheck_b = 3'h4; endcase end integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; //$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b); if (cyc==1) begin addr <= 7'h28; e0 <= 7'h11; e1 <= 6'h02; e2 <= 6'h03; end if (cyc==2) begin addr <= 7'h2b; if (data != 8'h11) $stop; end if (cyc==3) begin addr <= 7'h2c; if (data != 8'h03) $stop; if (wrapcheck_a != 3'h3) $stop; if (wrapcheck_b != 3'h4) $stop; end if (cyc==4) begin addr <= 7'h0; if (data != 8'h00) $stop; if (wrapcheck_a != 3'h4) $stop; if (wrapcheck_b != 3'h2) $stop; end if (cyc==5) begin if (data != 8'h00) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule /* verilator lint_off WIDTH */ `define AI 7'h28 module test (/*AUTOARG*/ // Outputs data, // Inputs addr, e0, e1, e2 ); output [7:0] data; input [6:0] addr; input [6:0] e0; input [5:0] e1, e2; reg [7:0] data; always @(/*AS*/addr or e0 or e1 or e2) begin case (addr) `AI: data = {e0[6], 1'b0, e0[5:0]}; `AI+1: data = e1; `AI+2, `AI+3: data = e2; default: data = 0; endcase end endmodule // Local Variables: // eval:(verilog-read-defines) // verilog-auto-sense-defines-constant: t // End: verilator-5.044/test_regress/t/t_time_vpi.v0000644000542200017500000000342315125463617021431 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `timescale `time_scale_units / `time_scale_prec import "DPI-C" function void dpii_check(); module t ( input clk ); integer cyc = 0; // verilator lint_off REALCVT time digits = 5432109876.543210ns; // Will round to time units realtime rdigits = 5432109876.543210ns; // Will round to time precision time high_acc = 64'd12345678901234567890; // Would lose accuracy if calculated in double // verilator lint_on REALCVT always @ (posedge clk) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $write("- [%0t] tick\n", $time); `endif if ($time >= 60) begin $write(":: In %m\n"); $printtimescale; $write("[%0t] time%%0d=%0d 123%%0t=%0t\n", $time, $time, 123); $write(" dig%%0t=%0t dig%%0d=%0d\n", digits, digits); $write(" rdig%%0t=%0t rdig%%0f=%0f\n", rdigits, rdigits); $write(" acc%%0t=%0t acc%%0d=%0d\n", high_acc, high_acc); $timeformat(-9, 6, "ns", 16); $write("[%0t] time%%0d=%0d 123%%0t=%0t\n", $time, $time, 123); $write(" dig%%0t=%0t dig%%0d=%0d\n", digits, digits); $write(" rdig%%0t=%0t rdig%%0f=%0f\n", rdigits, rdigits); $write(" acc%%0t=%0t acc%%0d=%0d\n", high_acc, high_acc); $write("[%0t] stime%%0t=%0t stime%%0d=%0d stime%%0f=%0f\n", $time, $stime, $stime, $stime); // verilator lint_off REALCVT $write("[%0t] rtime%%0t=%0t rtime%%0d=%0d rtime%%0f=%0f\n", $time, $realtime, $realtime, $realtime); // verilator lint_on REALCVT dpii_check(); $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.044/test_regress/t/t_concat_link_bad.py0000755000542200017500000000076615125463617023104 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_param_up_bad.py0000755000542200017500000000076615125463617022424 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_debug_sigsegv_bt_bad.py0000755000542200017500000000145215125463617024113 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') if 'VERILATOR_TEST_NO_GDB' in os.environ: test.skip("Skipping due to VERILATOR_TEST_NO_GDB") if not test.have_gdb: test.skip("No gdb installed") test.lint(verilator_flags2=["--debug --gdbbt --debug-sigsegv"], fails='any') test.file_grep(test.compile_log_filename, r'Program received signal SIGSEGV') test.file_grep(test.compile_log_filename, r'in V3Options::') test.passes() verilator-5.044/test_regress/t/t_config_work__libb.v0000644000542200017500000000062615125463617023255 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module m2; m3 u_23 (); initial $display("libb:m2 %%m=%m %%l=%l"); endmodule module m3; // Module name duplicated between libraries initial $display("libb:m3 %%m=%m %%l=%l"); endmodule verilator-5.044/test_regress/t/t_randomize_method_with.py0000755000542200017500000000151115125463617024362 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile( # Ensure we test captures of static variables verilator_flags2=["--fno-inline"]) test.execute() for filename in test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*Baz*.cpp"): # Check that "Baz" has no constrained random generator test.file_grep_not(filename, "this->__PVT__constraint") test.passes() verilator-5.044/test_regress/t/t_trace_ub_misaligned_address.v0000644000542200017500000000325315125463617025303 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // When compiled using -fsanitize=address,undefined this triggered: // // verilated_trace_imp.h:875:5: runtime error: store to misaligned address ... // verilated_trace.h:450:31: runtime error: load of misaligned address ... // // due to 32 bit aligned addresses being used for types which require // stricter alignment. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by John Wehle. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" module t; wire [2:0] out; reg in; reg [39:0] p; reg rst; reg clk; initial begin $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); $dumpvars(0, test); clk = 0; rst = 0; for (int i = 0; i < 2; i++) begin #10 rst = 1; #10 rst = 0; p = 40'b0000000000111111111111111111110000000000; in = i[0]; for (int k = 0; k < 31; k++) begin in = p[39 - k] ^ i[0]; #1; end end #30 $write("*-* All Finished *-*\n"); $finish; end always begin #10 clk <= !clk; end Test test(.out(out), .in(in), .clk(clk), .rst(rst)); endmodule module Test(/*AUTOARG*/ // Outputs out, // Inputs clk, in, rst ); input clk; input in; input rst; output wire [2:0] out; reg [2:0] s; reg sin; assign out = s; always @(posedge clk, posedge rst) begin s[0] <= s[2]; s[2] <= in; s[1] <= sin; end always @(negedge clk, posedge rst) if (rst) sin <= 1'b0; else sin <= in; endmodule verilator-5.044/test_regress/t/t_trace_two_hdr_cc.py0000755000542200017500000000246515125463617023301 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test tracing with two models instanced import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t_trace_two_a.v" test.pli_filename = "t/t_trace_two_cc.cpp" test.compile(make_main=False, verilator_make_gmake=False, top_filename='t_trace_two_b.v', vm_prefix='Vt_trace_two_b', verilator_flags2=['-trace']) test.run(logfile=test.obj_dir + "/make_first_ALL.log", cmd=[ os.environ["MAKE"], "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp" ]) test.compile(make_main=False, top_filename='t_trace_two_a.v', make_flags=['CPPFLAGS_ADD=-DTEST_HDR_TRACE=1'], verilator_flags2=['-exe', '-trace', test.pli_filename]) test.execute() if test.vlt_all: test.file_grep(test.trace_filename, r'\$enddefinitions') test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_typedef_param.py0000755000542200017500000000073415125463617022625 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_class_member_bad2.py0000755000542200017500000000076615125463617023336 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_randomize_complex_dynamic_arrays.v0000644000542200017500000000252715125463617026425 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class SubClass; rand bit [2:0] field; function new(); field = 0; endfunction endclass class MyClass; SubClass sc_inst2[]; function new(); sc_inst2 = new[7]; sc_inst2[1] = new; endfunction endclass ; class Deep; MyClass sc_inst1; function new(); sc_inst1 = new; endfunction endclass ; class WeNeedToGoDeeper; Deep sc_inst; function new(); sc_inst = new; endfunction endclass ; module t; initial begin WeNeedToGoDeeper cl_inst[]; MyClass cl_inst2[]; cl_inst = new[3]; cl_inst2 = new[5]; cl_inst[1] = new; cl_inst2[0] = new; if (cl_inst[1].sc_inst.sc_inst1.sc_inst2[1].randomize() with { field inside {1, 2, 3}; } == 0) begin $stop; end if (cl_inst[1].sc_inst.sc_inst1.sc_inst2[1].field < 1 || cl_inst[1].sc_inst.sc_inst1.sc_inst2[1].field > 3) begin $stop; end if (cl_inst2[0].sc_inst2[1].randomize() with {field inside {1, 2, 3};} == 0) begin $stop; end if (cl_inst2[0].sc_inst2[1].field < 1 || cl_inst2[0].sc_inst2[1].field > 3) begin $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_param_array6.v0000644000542200017500000000322115125463617022175 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Anderson Ignacio da Silva. // SPDX-License-Identifier: CC0-1.0 package test_pkg; localparam [31:0] test_arr [4][4:0] = '{ '{'h0000, 'h1000, 'h2000, 'h3000, 'h4000}, '{'h0FFF, 'h1FFF, 'h2FFF, 'h3FFF, 'h4FFF}, '{ 'd0, 'd0, 'd0, 'd0, 'd0}, '{ 'd0, 'd1, 'd2, 'd3, 'd4} }; typedef struct packed{ logic [7:0] val_1; logic [7:0] val_2; } test_ret_t; endpackage module t import test_pkg::*; (clk); input clk; function automatic test_ret_t test_f(logic [31:0] val); test_ret_t temp; temp = test_ret_t'(0); for (int i=0; i<5; i++) begin if (val >= test_arr[0][i] && val <= test_arr[1][i]) begin temp.val_1 = test_arr[2][i][7:0]; temp.val_2 = test_arr[3][i][7:0]; end end return temp; endfunction test_ret_t temp; logic [31:0] random; int cyc; bit [63:0] sum; always @ (posedge clk) begin cyc <= cyc + 1; random <= {17'b0, cyc[3:0], 11'b0}; temp <= test_f(random); `ifdef TEST_VERBOSE $display("rand: %h / Values -> val_1: %d / val_2: %d", random, temp.val_1, temp.val_2); `endif if (cyc > 10 && cyc < 90) begin sum <= {48'h0, temp} ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; end else if (cyc == 99) begin $displayh(sum); if (sum != 64'h74d34ea7a775f994) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.044/test_regress/t/t_order_dpi_export_1.cpp0000644000542200017500000000212715125463617023722 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2021 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include int main(int argc, char* argv[]) { VM_PREFIX* const tb = new VM_PREFIX; tb->contextp()->commandArgs(argc, argv); bool clk = true; while (!tb->contextp()->gotFinish()) { // Timeout if (tb->contextp()->time() > 100000) break; // Toggle and set clock svSetScope(svGetScopeFromName("TOP.testbench")); clk = !clk; set_clk(clk); // Eval tb->eval(); // Advance time tb->contextp()->timeInc(500); } delete tb; return 0; } verilator-5.044/test_regress/t/t_do_while_continue_bad.py0000755000542200017500000000102215125463617024300 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) test.passes() verilator-5.044/test_regress/t/t_fork_block_item_declaration.v0000644000542200017500000000140415125463617025310 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 static int counts[10]; class Foo; static task do_something(); for (int i = 0; i < 10; i++) frk : fork int ii = i; #(10 + i) begin $display("i: %d, ii: %d", i, ii); if (counts[ii]++ != 0) $stop; end join_none : frk #1; endtask endclass module t(); initial begin int desired_counts[10] = '{10{1}}; counts = '{10{0}}; Foo::do_something(); #20; if (counts != desired_counts) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_trace_ena_sc.py0000755000542200017500000000142015125463617022404 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_ena.v" if not test.have_sc: test.skip("No SystemC installed") test.compile(verilator_flags2=['-trace -sc']) test.execute() if test.vlt_all: # Note more checks in _cc.py test.file_grep(test.trace_filename, r'\$enddefinitions') test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_altera_lpm_ff.py0000755000542200017500000000111115125463617022566 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module]) test.passes() verilator-5.044/test_regress/t/t_genvar_misuse_bad.py0000755000542200017500000000076615125463617023467 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_lint_implicit_port.py0000755000542200017500000000075015125463617023707 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["-Wno-IMPLICIT"]) test.passes() verilator-5.044/test_regress/t/t_mod_param_class_typedef3.py0000755000542200017500000000077115125463617024735 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_event_control_scope_var.v0000644000542200017500000000230015125463617024530 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module test_mod(input reg clk, input reg reset, output integer result); always @(reset) begin result <= 1; end endmodule module Dut(input clk); int num; integer result1; integer result2; reg reset1; reg reset2; initial begin reset1 = $random; reset2 = $random; end always @(posedge clk) begin num <= num + 1; if (num == 5) begin reset1 <= 1'b1; end if (num == 10) begin // display to prevent optimalization $display("result1: %d", result1); $display("result2: %d", result2); $write("*-* All Finished *-*\n"); $finish; end end always @(reset1) begin reset2 <= t.reset; end test_mod t ( .clk(clk), .reset(reset1), .result(result1) ); test_mod t2 ( .clk(clk), .reset(reset2), .result(result2)); endmodule module Dut_wrapper(input clk); Dut d(.clk(clk)); Dut d2(.clk(clk)); endmodule module t (/*AUTOARG*/ clk); input clk; Dut_wrapper d_w(.clk(clk)); endmodule verilator-5.044/test_regress/t/t_tri_top_en_out.py0000755000542200017500000000114115125463617023027 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe --timing --pins-inout-enables", test.pli_filename]) test.execute() test.passes() verilator-5.044/test_regress/t/t_var_overwidth_bad.py0000755000542200017500000000111215125463617023465 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(make_main=False, verilator_flags2=["--exe", test.pli_filename]) test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_class_param_bad1.v0000644000542200017500000000056015125463617022770 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls #(parameter PARAMB = 12); endclass module t; Cls #(.PARAMBAD(1)) c; // Bad param name Cls #(13, 1) cd; // Bad param number endmodule verilator-5.044/test_regress/t/t_vlt_legacy.py0000755000542200017500000000077315125463617022141 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=[test.t_dir + "/" + test.name + ".vlt"]) test.passes() verilator-5.044/test_regress/t/t_force_readwrite_unsup.py0000755000542200017500000000077115125463617024404 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_interface_wire_bad_param.v0000644000542200017500000000056415125463617024574 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface Ifc; endinterface module Sub #(parameter P); Ifc a(); endmodule module t; Sub #(0) sub(); // Issue #5649 wire wbad = sub.a; endmodule verilator-5.044/test_regress/t/t_class_param_subtype2.v0000644000542200017500000000110715125463617023734 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Class1 #(type T); static function int get(); return T::Helper::getter(); endfunction endclass class Class2; typedef Class2 Helper; static function int getter(); return 13; endfunction endclass module t; initial begin if (Class1#(Class2)::get() != 13) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_class_short_circuit.v0000644000542200017500000000135015125463617023660 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Cls; int x; function new; x = 10; endfunction function bit set_x(int a); x = a; return 1; endfunction function int get_x; return x; endfunction endclass module t; initial begin Cls cls; if (cls != null && cls.x == 10) $stop; if (cls != null && cls.get_x() == 10) $stop; cls = new; if (!cls.set_x(1) || cls.x != 1) $stop; if (!cls.set_x(2) || cls.get_x() != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_vpi_get_value_array.v0000644000542200017500000000610515125463617023644 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2024 by Diego Roux. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VERILATOR_COMMENTS `define PUBLIC_FLAT_RD /*verilator public_flat_rd*/ `define PUBLIC_FLAT_RW /*verilator public_flat_rw*/ `else `define PUBLIC_FLAT_RD `define PUBLIC_FLAT_RW `endif module test (); `ifdef VERILATOR `systemc_header extern "C" int mon_check(); `verilog `endif reg [7:0] read_bytes [0:3] `PUBLIC_FLAT_RD; reg [7:0] read_bytes_nonzero_index [1:4] `PUBLIC_FLAT_RD; reg [7:0] read_bytes_rl [3:0] `PUBLIC_FLAT_RD; reg [15:0] read_shorts [0:3] `PUBLIC_FLAT_RD; reg [31:0] read_words [0:3] `PUBLIC_FLAT_RD; reg [31:0] read_words_rl [3:0] `PUBLIC_FLAT_RD; reg [63:0] read_longs [0:3] `PUBLIC_FLAT_RD; integer read_integers [0:3] `PUBLIC_FLAT_RD; reg [68:0] read_customs [0:3] `PUBLIC_FLAT_RD; reg [68:0] read_customs_nonzero_index_rl [4:1] `PUBLIC_FLAT_RD; reg [7:0] read_scalar `PUBLIC_FLAT_RD; reg [7:0] read_bounds [1:3] `PUBLIC_FLAT_RD; integer status; initial begin read_bytes[0] = 8'had; read_bytes[1] = 8'hde; read_bytes[2] = 8'hef; read_bytes[3] = 8'hbe; read_bytes_rl[3] = 8'had; read_bytes_rl[2] = 8'hde; read_bytes_rl[1] = 8'hef; read_bytes_rl[0] = 8'hbe; read_bytes_nonzero_index[1] = 8'had; read_bytes_nonzero_index[2] = 8'hde; read_bytes_nonzero_index[3] = 8'hef; read_bytes_nonzero_index[4] = 8'hbe; read_shorts[0] = 16'hdead; read_shorts[1] = 16'hbeef; read_shorts[2] = 16'hcafe; read_shorts[3] = 16'hf00d; read_words[0] = 32'hdeadbeef; read_words[1] = 32'hcafef00d; read_words[2] = 32'h00010203; read_words[3] = 32'h04050607; read_integers[0] = 32'hdeadbeef; read_integers[1] = 32'hcafef00d; read_integers[2] = 32'h00010203; read_integers[3] = 32'h04050607; read_longs[0] = 64'hdeadbeefcafef00d; read_longs[1] = 64'h0001020304050607; read_longs[2] = 64'h08090a0b0c0d0e0f; read_longs[3] = 64'h1011121314151617; read_customs[0] = 69'hFAdeadbeefcafef00d; //0x001F'FFFF'FFFF'FFFF'FFFF read_customs[1] = 69'hF50001020304050607; read_customs[2] = 69'h0A08090a0b0c0d0e0f; read_customs[3] = 69'h051011121314151617; read_customs_nonzero_index_rl[4] = 69'hFAdeadbeefcafef00d; //0x001F'FFFF'FFFF'FFFF'FFFF read_customs_nonzero_index_rl[3] = 69'hF50001020304050607; read_customs_nonzero_index_rl[2] = 69'h0A08090a0b0c0d0e0f; read_customs_nonzero_index_rl[1] = 69'h051011121314151617; `ifdef IVERILOG status = $mon_check; `endif `ifdef VERILATOR status = $c32("mon_check()"); `endif if (status != 0) begin $write("%%Error: t_vpi_get_value_array.cpp:%0d: C Test failed\n", status); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_sys_readmem_bad_notfound.out0000644000542200017500000000013315125463617025204 0ustar mahmoudyfreeshell%Warning: t/t_sys_readmem_bad_NOTFOUND.mem:0: $readmem file not found *-* All Finished *-* verilator-5.044/test_regress/t/t_package_twodeep.v0000644000542200017500000000102115125463617022727 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 // See issue #591 package pkg2; parameter PARAM2 = 16; endpackage // pkg2 package pkg1; import pkg2::*; parameter PARAM1 = 8; endpackage // pkg1 module t import pkg1::*; // Test SV 2012 import format ; reg [PARAM1:0] bus1; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_savable_open_bad.py0000755000542200017500000000116215125463617023245 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_savable.v" test.compile(v_flags2=["--savable"], save_time=500) test.execute(all_run_flags=['+save_restore=1'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_foreach_nindex_bad.py0000755000542200017500000000076615125463617023574 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_clocking_unsup1.out0000644000542200017500000000111215125463617023254 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_clocking_unsup1.v:14:15: Unsupported: clocking event edge override 14 | output posedge #1 a; | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_clocking_unsup1.v:15:15: Unsupported: clocking event edge override 15 | output negedge #1 b; | ^~~~~~~ %Error-UNSUPPORTED: t/t_clocking_unsup1.v:16:15: Unsupported: clocking event edge override 16 | output edge #1 b; | ^~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_interface_noinl.py0000755000542200017500000000103215125463617023134 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_vlt_var_spec_bad.out0000644000542200017500000000063015125463617023451 0ustar mahmoudyfreeshell%Error: t/t_vlt_var_spec_bad.vlt:9:1: 'VAR_SC_BV' attribute does not accept -param/-port 9 | sc_bv -module "top" -param "*" | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_vlt_var_spec_bad.vlt:10:1: 'VAR_SC_BV' attribute does not accept -param/-port 10 | sc_bv -module "top" -port "*" | ^~~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_wrapper_reuse_context_bad.v0000644000542200017500000000040015125463617025042 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module top; initial $finish; endmodule verilator-5.044/test_regress/t/t_func_while.v0000644000542200017500000000144115125463617021736 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2018 by Julien Margetts. // SPDX-License-Identifier: CC0-1.0 module t #(parameter SZ = 4096) ( input wire clk, output reg [tdw(SZ)-1:0] data ); // bug1330 function integer clog2(input integer value); integer tmp; tmp = value-1; clog2 = 0; for (clog2=0; (tmp>0) && (clog2<32); clog2=clog2+1) tmp = tmp>>1; endfunction function integer tdw(input integer SZ); tdw = clog2(SZ); endfunction integer b; always @(posedge clk) for (b=0; b #include #include #include #include void rngUpdate(uint64_t& x) { x ^= x << 13; x ^= x >> 7; x ^= x << 17; } int main(int, char**) { // Create contexts VerilatedContext ctx; // Create models Vref ref{&ctx}; Vopt opt{&ctx}; uint64_t rand_a = 0x5aef0c8dd70a4497; uint64_t rand_b = 0xf0c0a8dd75ae4497; uint64_t srand_a = 0x000fa8dcc7ae4957; uint64_t srand_b = 0x00fa8dc7ae3c9574; uint64_t arand_a = 0x758c168d16c93a0f; uint64_t arand_b = 0xbe01de017d87355d; for (size_t n = 0; n < 200000; ++n) { // Update rngs rngUpdate(rand_a); rngUpdate(rand_b); rngUpdate(srand_a); rngUpdate(srand_b); rngUpdate(arand_a); rngUpdate(arand_b); // Assign inputs ref.rand_a = opt.rand_a = rand_a; ref.rand_b = opt.rand_b = rand_b; ref.srand_a = opt.srand_a = srand_a; ref.srand_b = opt.srand_b = srand_b; ref.arand_a = opt.arand_a = arand_a; ref.arand_b = opt.arand_b = arand_b; // Evaluate both models ref.eval(); opt.eval(); // Check equivalence #include "checks.h" // increment time ctx.timeInc(1); } std::cout << "*-* All Finished *-*\n"; } verilator-5.044/test_regress/t/t_langext_4.py0000755000542200017500000000105515125463617021667 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_langext_2.v" # This is a compile only test. test.compile(v_flags2=["+1800-2009ext+v"]) test.passes() verilator-5.044/test_regress/t/t_struct_circ_bad.out0000644000542200017500000000047515125463617023315 0ustar mahmoudyfreeshell%Error: t/t_struct_circ_bad.v:11:11: Struct's type is circular: t.t2_t : ... note: In instance 't' 11 | typedef struct packed { | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_param_array4.py0000755000542200017500000000073415125463617022367 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_assoc_compare.v0000644000542200017500000000402515125463617022432 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Check == and != operations performed on associative arrays // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Ilya Barkov. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define check_comp(lhs, rhs, op, exp) if ((exp) != ((lhs) op (rhs))) begin $write("%%Error: %s:%0d: op comparison shall return 'b%x\n", `__FILE__, `__LINE__, (exp)); `stop; end // Two checks because == and != may not be derived from each other `define check_eq(lhs, rhs) `check_comp(lhs, rhs, ==, 1'b1) `check_comp(lhs, rhs, !=, 1'b0) `define check_ne(lhs, rhs) `check_comp(lhs, rhs, ==, 1'b0) `check_comp(lhs, rhs, !=, 1'b1) class Cls; int i; endclass module t; initial begin begin // simple case int assoc1[int]; int assoc2[int]; // Empty are equal `check_eq(assoc1, assoc2) // Make different assoc1[10] = 15; assoc2[-1] = 365; `check_ne(assoc1, assoc2) // Make same assoc1[-1] = 365; assoc2[10] = 15; `check_eq(assoc1, assoc2) // Don't actually change assoc1[-1] = 365; `check_eq(assoc1, assoc2) // Compare different sizes assoc1[3] = 0; `check_ne(assoc1, assoc2) end begin // check that a class as key is fine int assoc1[Cls]; int assoc2[Cls]; Cls a = new; Cls b = new; int t; assoc1[a] = 0; `check_ne(assoc1, assoc2) assoc2[a] = 0; `check_eq(assoc1, assoc2) assoc2.delete(a); assoc2[b] = 0; `check_ne(assoc1, assoc2) end begin // check that a class as value is fine Cls assoc1[int]; Cls assoc2[int]; Cls a = new; Cls b = new; assoc1[1] = a; assoc2[1] = b; `check_ne(assoc1, assoc2) assoc2[1] = a; `check_eq(assoc1, assoc2) end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_dpi_arg_output_type.py0000755000542200017500000000244115125463617024070 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if test.nc: # For NC, compile twice, first just to generate DPI headers test.compile(nc_flags2=[ "+ncdpiheader+" + test.obj_dir + "/dpi-exp.h", "+ncdpiimpheader+" + test.obj_dir + "/dpi-imp.h" ]) test.compile( v_flags2=["t/" + test.name + ".cpp"], # --no-decoration so .out file doesn't comment on source lines verilator_flags2=["-Wall -Wno-DECLFILENAME --no-decoration"], # NC: Gdd the obj_dir to the C include path nc_flags2=["+ncscargs+-I" + test.obj_dir], # ModelSim: Generate DPI header, add obj_dir to the C include path ms_flags2=["-dpiheader " + test.obj_dir + "/dpi.h", "-ccflags -I" + test.obj_dir]) if test.vlt_all: test.files_identical(test.obj_dir + "/" + test.vm_prefix + "__Dpi.h", "t/" + test.name + "__Dpi.out") test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_tri_pullvec_bad.out0000644000542200017500000000147315125463617023320 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_tri_pullvec_bad.v:13:13: Unsupported: Conflicting pull directions. : ... note: In instance 't' 13 | pulldown p1 (w[1]); | ^~ t/t_tri_pullvec_bad.v:12:11: ... Location of conflicting pull. 12 | pullup p0 (w[0]); | ^~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_tri_pullvec_bad.v:14:13: Unsupported: Conflicting pull directions. : ... note: In instance 't' 14 | pulldown p2 (w[2]); | ^~ t/t_tri_pullvec_bad.v:12:11: ... Location of conflicting pull. 12 | pullup p0 (w[0]); | ^~ %Error: Exiting due to verilator-5.044/test_regress/t/t_trace_complex_saif_threads_2.py0000755000542200017500000000126215125463617025564 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_complex.v" test.golden_filename = "t/t_trace_complex_saif.out" test.compile(verilator_flags2=['--cc --trace-saif --trace-threads 2']) test.execute() test.saif_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_pp_misdef_bad.py0000755000542200017500000000076315125463617022563 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_struct_init_bad.py0000755000542200017500000000110615125463617023154 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_struct_init.v" test.lint(v_flags2=['+define+T_STRUCT_INIT_BAD'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_trace_packed_struct_fst_sc.out0000644000542200017500000000153315125463617025531 0ustar mahmoudyfreeshell$date Sat Apr 5 13:56:26 2025 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $scope module t $end $var wire 1 ! clk $end $var int 32 " cnt [31:0] $end $var parameter 96 # v[0] [95:0] $end $var parameter 96 $ v[1] [95:0] $end $var parameter 96 % v[2] [95:0] $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b000100000000000000000000000000100001000000000000000000000000000100010000000000000000000000000000 % b001000000000000000000000000000100010000000000000000000000000000100100000000000000000000000000000 $ b001100000000000000000000000000100011000000000000000000000000000100110000000000000000000000000000 # b00000000000000000000000000000000 " 0! $end #10 1! b00000000000000000000000000000001 " #15 0! #20 1! b00000000000000000000000000000010 " #25 0! #30 1! b00000000000000000000000000000011 " #35 0! #40 1! #44 verilator-5.044/test_regress/t/t_dos.v0000644000542200017500000000075415125463617020406 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // This file has DOS carrage returns in it! module t (/*AUTOARG*/ // Inputs clk ); input clk; always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule // This file has DOS carrage returns in it! verilator-5.044/test_regress/t/t_inst_pin_realnreal.out0000644000542200017500000000065015125463617024026 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_inst_pin_realnreal.v:51:32: Unsupported: Output port connection 'out' connects real to non-real : ... note: In instance 't.netlist' 51 | pga_model pga0(.in, .gain, .out(pga_out)); | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.044/test_regress/t/t_var_ref_noinline.py0000755000542200017500000000104015125463617023313 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 test.top_filename = "t/t_var_ref.v" import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=['+define+T_NOINLINE']) test.execute() test.passes() verilator-5.044/test_regress/t/t_vlt_warn.py0000755000542200017500000000075615125463617021645 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["-Wall t/t_vlt_warn.vlt"]) test.passes() verilator-5.044/test_regress/t/t_param_unreachable.py0000755000542200017500000000073415125463617023436 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_class_split.py0000755000542200017500000000100215125463617022312 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--output-split 10']) test.execute() test.passes() verilator-5.044/test_regress/t/t_forceable_var_cmt_trace.py0000755000542200017500000000146215125463617024617 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.pli_filename = "t/t_forceable_var.cpp" test.top_filename = "t/t_forceable_var.v" test.golden_filename = "t/t_forceable_var_trace.vcd.out" test.compile(make_top_shell=False, make_main=False, verilator_flags2=['-DCMT=1', '--exe', '--trace-vcd', test.pli_filename]) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_struct_packed_init_bad.v0000644000542200017500000000064715125463617024306 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; parameter P = 4'h5; struct packed { bit [3:0] m_lo = P; // Bad bit [3:0] m_hi; } s; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_scheduling_2.v0000644000542200017500000000217415125463617022165 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2022 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VERILATOR // The '$c1(1)' is there to prevent inlining of the signal by V3Gate `define IMPURE_ONE $c(1); `else // Use standard $random (chaces of getting 2 consecutive zeroes is zero). `define IMPURE_ONE |($random | $random); `endif module top( clk ); input clk; reg clk_half = 0; reg [31:0] cyc = 0; reg [31:0] a, b, c; always @(posedge clk) begin $display("tick %d: a: %d, b: %d, c: %d", cyc, a, b, c); // Check invariant if (a !== cyc + 1) $stop; if (b !== cyc + 2) $stop; if (c !== cyc + 2) $stop; // End of test if (cyc == 100) begin $write("*-* All Finished *-*\n"); $finish; end cyc <= cyc + 1; end always @(clk) a = cyc + `IMPURE_ONE; always @(a) b = a + `IMPURE_ONE; assign c = a + `IMPURE_ONE; endmodule verilator-5.044/test_regress/t/t_inside_dyn.py0000755000542200017500000000073415125463617022132 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_interface_array_nocolon_bad.v0000644000542200017500000000123015125463617025302 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Functionally demonstrate an array of interfaces // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Mike Popoloski. // SPDX-License-Identifier: CC0-1.0 interface foo_intf ( input x ); endinterface module foo_subm ( input x ); endmodule module t (); localparam N = 3; wire [2:0] X = 3'b110; // Will cause ASCRANGE warning? foo_intf foos [N] (.x(X)); // bad foo_intf fool [1:3] (.x(X)); // bad foo_intf foom [3:1] (.x(X)); // ok foo_subm subs [N] (.x(X)); // bad foo_subm subl [1:3] (.x(X)); // bad foo_subm subm [3:1] (.x(X)); // ok endmodule verilator-5.044/test_regress/t/t_clk_first.py0000755000542200017500000000100515125463617021755 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["+define+ATTRIBUTES=1"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_interface_generic_bad3.v0000644000542200017500000000105515125463617024141 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; int v; endinterface module GenericModule (interface a); initial begin #1; if (a.v != 7) $stop; if (b.k != 9) $stop; end endmodule module t; inf inf_inst(); GenericModule genericModule (inf_inst, inf_inst); initial begin inf_inst.v = 7; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_inst_nansi_param.py0000755000542200017500000000071115125463617023325 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.compile() test.passes() verilator-5.044/test_regress/t/t_gate_inline_wide_exclude_multiple.py0000755000542200017500000000122715125463617026715 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=['--stats', '--expand-limit 5']) test.file_grep(test.stats, r'Optimizations, Gate excluded wide expressions\s+(\d+)', 2) test.file_grep(test.stats, r'Optimizations, Gate sigs deleted\s+(\d+)', 0) test.passes() verilator-5.044/test_regress/t/t_strength_2_uneq_assign.py0000755000542200017500000000076615125463617024465 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_interface_modport_expr_partsel.v0000644000542200017500000000205315125463617026107 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); // verilog_format: on interface my_if; logic [15:0] a; logic [7:0] b, c; modport mp1(input .in(a[7:0]), output .out(b)); modport mp2(input .in(a[15:8]), output .out(c)); endinterface module mod1 ( my_if.mp1 i ); assign i.out = i.in; endmodule module mod2 ( my_if.mp2 i ); assign i.out = ~i.in; endmodule module top (); my_if myIf (); assign myIf.a = 16'habcd; mod1 mod1Instance (myIf); mod2 mod2Instance (myIf); initial begin #1; `checkh(myIf.b, myIf.a[7:0]); `checkh(myIf.c, ~myIf.a[15:8]); #1; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_func_default_warn.py0000755000542200017500000000077315125463617023476 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-Wno-WIDTH"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_preproc_nodef_bad.v0000644000542200017500000000037015125463617023246 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `not_defined module t; endmodule verilator-5.044/test_regress/t/t_mem_bound_bad.v0000644000542200017500000000104315125463617022364 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jie Xu // SPDX-License-Identifier: CC0-1.0 module t; logic [1:0][31:0] tt; logic [31:0] a; logic [31:0] b; logic [31:0] c; initial begin a = 1; b = 2; c = 3; tt[0] = a; tt[1] = b; tt[2] = c; // Out of bounds if (tt[0]!=a) $stop; if (tt[1]!=b) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_trace_packed_struct_saif.py0000755000542200017500000000114515125463617025015 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_packed_struct.v" test.compile(v_flags2=["--trace-saif"]) test.execute() test.saif_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_opt_0.py0000755000542200017500000000074415125463617021027 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['-O0']) test.passes() verilator-5.044/test_regress/t/t_inst_array_inl1.py0000755000542200017500000000104215125463617023074 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_inst_array.v" test.compile(v_flags2=['+define+USE_INLINE']) test.execute() test.passes() verilator-5.044/test_regress/t/t_selextract_in_paramextends.py0000755000542200017500000000077115125463617025425 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_dfg_multidriver_dfg_bad.out0000644000542200017500000002014215125463617024770 0ustar mahmoudyfreeshell%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:45:18: Bit [1] of signal 'y' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' t/t_dfg_multidriver_dfg_bad.v:48:24: ... Location of offending driver 48 | {y[1:0], y[2:1]} = i[3:0] + 4'd5; | ^ t/t_dfg_multidriver_dfg_bad.v:48:24: ... Location of offending driver 48 | {y[1:0], y[2:1]} = i[3:0] + 4'd5; | ^ ... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest ... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message. %Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:16:18: Bits [3:1] of signal 'a' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' t/t_dfg_multidriver_dfg_bad.v:17:19: ... Location of offending driver 17 | assign a[3:0] = i[3:0]; | ^ t/t_dfg_multidriver_dfg_bad.v:18:19: ... Location of offending driver 18 | assign a[4:1] = ~i[4:1]; | ^ %Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:16:18: Bit [3] of signal 'a' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' t/t_dfg_multidriver_dfg_bad.v:17:19: ... Location of offending driver 17 | assign a[3:0] = i[3:0]; | ^ t/t_dfg_multidriver_dfg_bad.v:19:17: ... Location of offending driver 19 | assign a[3] = ~i[3]; | ^ %Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:16:18: Bits [7:6] of signal 'a' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' t/t_dfg_multidriver_dfg_bad.v:20:19: ... Location of offending driver 20 | assign a[8:5] = i[8:5]; | ^ t/t_dfg_multidriver_dfg_bad.v:21:19: ... Location of offending driver 21 | assign a[7:6] = ~i[7:6]; | ^ %Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:16:18: Bit [9] of signal 'a' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' t/t_dfg_multidriver_dfg_bad.v:22:17: ... Location of offending driver 22 | assign a[9] = i[9]; | ^ t/t_dfg_multidriver_dfg_bad.v:23:17: ... Location of offending driver 23 | assign a[9] = ~i[9]; | ^ %Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:26:18: Elements [3:0] of signal 'u' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' t/t_dfg_multidriver_dfg_bad.v:27:14: ... Location of offending driver 27 | assign u = j; | ^ t/t_dfg_multidriver_dfg_bad.v:28:14: ... Location of offending driver 28 | assign u = k; | ^ %Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:30:18: Element [1] of signal 'v' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' t/t_dfg_multidriver_dfg_bad.v:31:14: ... Location of offending driver 31 | assign v = j; | ^ t/t_dfg_multidriver_dfg_bad.v:32:13: ... Location of offending driver 32 | assign v[1] = i; | ^ %Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:34:18: Element [0] of signal 'w' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' t/t_dfg_multidriver_dfg_bad.v:35:13: ... Location of offending driver 35 | assign w[0] = i; | ^ t/t_dfg_multidriver_dfg_bad.v:36:14: ... Location of offending driver 36 | assign w = j; | ^ %Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:38:18: Bits [3:2] of signal 'x[3]' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' t/t_dfg_multidriver_dfg_bad.v:39:17: ... Location of offending driver 39 | assign x[3] = i; | ^ t/t_dfg_multidriver_dfg_bad.v:40:22: ... Location of offending driver 40 | assign x[3][3:2] = ~i[1:0]; | ^ %Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:51:18: Bits [2:1] of signal 'z' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' t/t_dfg_multidriver_dfg_bad.v:53:14: ... Location of offending driver 53 | z[2:0] = i[2:0]; | ^ t/t_dfg_multidriver_dfg_bad.v:58:17: ... Location of offending driver 58 | z[3:1] = i[3:1]; | ^ %Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:51:18: Bits [6:5] of signal 'z' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' t/t_dfg_multidriver_dfg_bad.v:57:14: ... Location of offending driver 57 | z[6:4] = i[6:4]; | ^ t/t_dfg_multidriver_dfg_bad.v:54:14: ... Location of offending driver 54 | z[7:5] = i[7:5]; | ^ %Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:51:18: Bit [7] of signal 'z' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' t/t_dfg_multidriver_dfg_bad.v:54:14: ... Location of offending driver 54 | z[7:5] = i[7:5]; | ^ t/t_dfg_multidriver_dfg_bad.v:60:20: ... Location of offending driver 60 | assign z[10:7] = i[10:7]; | ^ %Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:74:18: Bits [5:2] of signal 't.sub_1.a' have multiple combinational drivers. This can cause performance degradation. t/t_dfg_multidriver_dfg_bad.v:63:20: ... Location of offending driver 63 | assign sub_1.a = i; | ^ t/t_dfg_multidriver_dfg_bad.v:75:19: ... Location of offending driver 75 | assign a[5:2] = i[5:2]; | ^ %Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:74:18: Bits [3:2] of signal 't.sub_2.a' have multiple combinational drivers. This can cause performance degradation. t/t_dfg_multidriver_dfg_bad.v:67:25: ... Location of offending driver 67 | assign sub_2.a[3:0] = i[3:0]; | ^ t/t_dfg_multidriver_dfg_bad.v:75:19: ... Location of offending driver 75 | assign a[5:2] = i[5:2]; | ^ %Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:74:18: Bit [5] of signal 't.sub_2.a' have multiple combinational drivers. This can cause performance degradation. t/t_dfg_multidriver_dfg_bad.v:75:19: ... Location of offending driver 75 | assign a[5:2] = i[5:2]; | ^ t/t_dfg_multidriver_dfg_bad.v:66:26: ... Location of offending driver 66 | assign sub_2.a[10:5] = i[10:5]; | ^ %Error: Exiting due to verilator-5.044/test_regress/t/t_array_pattern_scalar_bad.py0000755000542200017500000000076615125463617025020 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_dpi_argtype_bad.v0000644000542200017500000000076015125463617022733 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2021 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; typedef struct { string a; string b; } foo_t; import "DPI-C" task dpix_twice(foo_t arg); initial begin $stop; end endmodule verilator-5.044/test_regress/t/t_randomize_method_constraints.py0000755000542200017500000000104615125463617025761 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_lib_prot_inout_bad.v0000644000542200017500000000061115125463617023447 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module secret_impl ( input a, input oe, inout z, output y); assign z = oe ? a : 1'bz; assign y = z; endmodule verilator-5.044/test_regress/t/t_func_ref_bad.out0000644000542200017500000000042215125463617022550 0ustar mahmoudyfreeshell%Error: t/t_func_ref_bad.v:19:22: Function/task ref argument is not of allowed type 19 | b = cls.get_x(a[1]); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_dpi_context_c.cpp0000644000542200017500000001024515125463617022754 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include //====================================================================== // clang-format off #if defined(VERILATOR) # ifdef T_DPI_CONTEXT_NOOPT # include "Vt_dpi_context_noopt__Dpi.h" # else # include "Vt_dpi_context__Dpi.h" # endif #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif #ifdef VERILATOR # include "verilated.h" #endif // clang-format on #ifdef NEED_EXTERNS extern "C" { extern int dpic_line(); extern int dpic_save(int value); extern int dpic_restore(); extern unsigned dpic_getcontext(); extern unsigned dpic_get1(); } #endif //====================================================================== int dpic_line() { svScope scope = svGetScope(); if (!scope) { printf("%%Warning: svGetScope failed\n"); return 0; } #ifdef VERILATOR static int didDump = 0; if (didDump++ == 0) Verilated::scopesDump(); #endif const char* scopenamep = svGetNameFromScope(scope); if (!scopenamep) { printf("%%Warning: svGetNameFromScope failed\n"); return 0; } if (scope != svGetScopeFromName(scopenamep)) { printf("%%Warning: svGetScopeFromName repeat failed\n"); return 0; } const char* filenamep = ""; int lineno = 0; if (svGetCallerInfo(&filenamep, &lineno)) { printf("Call from %s:%d:%s\n", filenamep, lineno, scopenamep); } else { printf("%%Warning: svGetCallerInfo failed\n"); return 0; } (void)svGetCallerInfo(nullptr, nullptr); // Check doesn't segflt return lineno; } extern int Dpic_Unique; int Dpic_Unique = 0; // Address used for uniqueness extern int Dpic_Value; int Dpic_Value = 0; // Address used for testing int dpic_save(int value) { svScope scope = svGetScope(); if (!scope) { printf("%%Warning: svGetScope failed\n"); return 0; } // Use union to avoid cast to different size pointer warnings union valpack { void* ptr; int i; } vp; // Load the value here, and below, to test we can reinsert correctly if (svPutUserData(scope, &Dpic_Unique, &Dpic_Value)) { printf("%%Warning: svPutUserData failed (initial)\n"); return 0; } if (void* userp = svGetUserData(scope, &Dpic_Unique)) { if (userp != &Dpic_Value) { printf("%%Warning: svGetUserData failed (initial wrong data)\n"); return 0; } } else { printf("%%Warning: svGetUserData failed (initial)\n"); return 0; } vp.i = value; (void)vp.i; if (svPutUserData(scope, &Dpic_Unique, vp.ptr)) { printf("%%Warning: svPutUserData failed\n"); return 0; } return 1; } int dpic_restore() { svScope scope = svGetScope(); if (!scope) { printf("%%Warning: svGetScope failed\n"); return 0; } if (void* userp = svGetUserData(scope, (void*)&Dpic_Unique)) { // Use union to avoid cast to different size pointer warnings union valpack { void* ptr; int i; } vp; vp.ptr = userp; return vp.i; } else { printf("%%Warning: svGetUserData failed\n"); return 0; } } unsigned dpic_getcontext() { svScope scope = svGetScope(); printf("%%Info: svGetScope returned scope (%p) with name %s\n", // scope, svGetNameFromScope(scope)); return (unsigned)(uintptr_t)scope; } unsigned dpic_get1() { return 1; } void dpic_final() { static int s_once = 0; if (s_once++) return; printf("%s:\n", __func__); #ifdef VERILATOR // Cover VerilatedImp::userDump Verilated::internalsDump(); #endif } verilator-5.044/test_regress/t/t_dpi_accessors_inc.vh0000644000542200017500000000332615125463617023441 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Accessor definitions for test of DPI accessors // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by Jeremy Bennett and Jie Xu // See t_dpi_accessors.v for details of the test. This file should be included // by the top level module to define all the accessors needed. // Use the macros to provide the desire access to our data. First simple // access to the registers, array elements and wires. For consistency with // simulators, we do not attempt to write wires. `RW_ACCESS([0:0], a, {t.i_test_sub.a}); `RW_ACCESS([7:0], b, {t.i_test_sub.b}); `RW_ACCESS([7:0], mem32, {t.i_test_sub.mem[32]}); `R_ACCESS ([0:0], c, {t.i_test_sub.c}); `R_ACCESS ([7:0], d, {t.i_test_sub.d}); `RW_ACCESS([7:0], e, {t.i_test_sub.e}); `RW_ACCESS([7:0], f, {t.i_test_sub.f}); // Slices of vectors and array elements. For consistency with simulators, // we do not attempt to write wire slices. `RW_ACCESS([3:0], b_slice, {t.i_test_sub.b[3:0]}); `RW_ACCESS([4:0], mem32_slice, {t.i_test_sub.mem[32][7:6], t.i_test_sub.mem[32][2:0]}); `R_ACCESS([5:0], d_slice, {t.i_test_sub.d[6:1]}); // Complex registers, one with distinct read and write. We avoid use of // wires for consistency with simulators. `RW_ACCESS([14:0], l1, {t.i_test_sub.b[3:0], t.i_test_sub.mem[32][7:6], t.i_test_sub.e[6:1], t.i_test_sub.mem[32][2:0]}); `R_ACCESS([7:0], l2, {t.i_test_sub.e[7:4], t.i_test_sub.f[3:0]}); `W_ACCESS([7:0], l2, {t.i_test_sub.e[5:2], t.i_test_sub.f[5:2]}); verilator-5.044/test_regress/t/t_func_const3_bad.py0000755000542200017500000000076315125463617023041 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_unroll_forfor.v0000644000542200017500000000164115125463617022505 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This files is used to generated the following error: // %Error: Internal Error: t/t_unroll_forfor.v:27: ../V3Simulate.h:177: No value found for node. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2016 by Jan Egil Ruud. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk, in ); input clk; input [71:0] in; reg [71:0] in_tmp; localparam [71:0] TEST_PARAM = {72{1'b0}}; // Test loop always @* begin: testmap byte i, j; // bug1044 for ( i = 0; i < 9; i = i + 1 ) // verilator lint_off WIDTH for ( j=0; j<(TEST_PARAM[i*8+:8]); j=j+1) begin in_tmp[TEST_PARAM[i*8+:8]+j] = in[TEST_PARAM[i*8+:8]+j]; end // verilator lint_on WIDTH $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_interface_down_inlc.py0000755000542200017500000000110115125463617023766 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_down.v" test.compile(v_flags2=['+define+INLINE_C'], verilator_flags2=['-trace']) test.execute() test.passes() verilator-5.044/test_regress/t/t_order_dpi_export_3.v0000644000542200017500000000267215125463617023414 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2021 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module testbench( /*AUTOARG*/ // Inputs clk ); input clk; // Top level input clock bit other_clk; // Dependent clock set via DPI bit third_clk; // Additional dependent clock set via DPI export "DPI-C" function set_other_clk; function void set_other_clk(bit val); other_clk = val; endfunction; export "DPI-C" function set_third_clk; function void set_third_clk(bit val); third_clk = val; endfunction; bit even_other = 1; import "DPI-C" context function void toggle_other_clk(bit val); always @(posedge clk) begin even_other <= ~even_other; toggle_other_clk(even_other); end bit even_third = 1; import "DPI-C" context function void toggle_third_clk(bit val); always @(posedge other_clk) begin even_third <= ~even_third; toggle_third_clk(even_third); end int n = 0; always @(posedge third_clk) begin $display("[%0t] n=%0d", $time, n); if ($time != (8*n+1) * 500) $stop; if (n == 20) begin $write("*-* All Finished *-*\n"); $finish; end n += 1; end endmodule verilator-5.044/test_regress/t/t_mailbox_array.py0000755000542200017500000000105115125463617022627 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--fno-slice']) # TODO remove -fno-slice, issue #5632/#5644 test.execute() test.passes() verilator-5.044/test_regress/t/t_inst_2star_bad.v0000644000542200017500000000057215125463617022515 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; wire foo; wire bar; sub sub (.*, .*); sub sub (foo, .*); sub sub (foo, .bar); endmodule module sub (input foo, input bar); endmodule verilator-5.044/test_regress/t/t_func_lib_sub.py0000755000542200017500000000077315125463617022442 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(verilator_flags2=['--no-timing']) #test.execute() test.passes() verilator-5.044/test_regress/t/t_sys_sscanf.py0000755000542200017500000000073415125463617022160 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_trace_complex_params_saif.out0000644000542200017500000012230715125463617025354 0ustar mahmoudyfreeshell// Generated by verilated_saif (SAIFILE (SAIFVERSION "2.0") (DIRECTION "backward") (PROGRAM_NAME "Verilator") (DIVIDER / ) (TIMESCALE 1ps) (DURATION 60) (INSTANCE top (NET (clk (T0 35) (T1 25) (TZ 0) (TX 0) (TB 0) (TC 11)) ) (INSTANCE $unit (NET (global_bit (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) ) ) (INSTANCE t (NET (clk (T0 35) (T1 25) (TZ 0) (TX 0) (TB 0) (TC 11)) (cyc\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (cyc\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) (cyc\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_strp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_strp_strp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_strp_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_strp_strp\[2\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_strp_strp\[3\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_unip_strp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_unip_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp_arrp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp_arrp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp_arrp\[2\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp_arrp\[3\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp_strp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp_strp\[2\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp_strp\[3\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arru[1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arru[2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arru_arru[3][1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arru_arru[3][2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arru_arru[4][1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arru_arru[4][2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arru_arrp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arru_arrp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arru_arrp[4]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arru_arrp[4]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arru_strp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arru_strp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arru_strp[4]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arru_strp[4]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_real\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[32\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[33\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[34\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[35\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[37\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[38\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[39\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[40\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[41\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[42\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[43\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[44\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[45\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[46\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[47\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[48\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[49\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[50\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[51\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[52\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[53\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[54\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[55\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[56\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[57\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[58\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[59\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[60\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[61\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[62\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[63\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[32\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[33\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[34\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[35\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[37\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[38\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[39\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[40\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[41\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[42\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[43\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[44\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[45\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[46\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[47\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[48\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[49\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[50\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[51\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[52\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[53\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[54\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[55\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[56\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[57\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[58\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[59\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[60\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[61\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[62\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[63\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[32\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[33\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[34\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[35\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[37\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[38\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[39\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[40\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[41\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[42\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[43\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[44\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[45\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[46\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[47\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[48\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[49\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[50\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[51\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[52\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[53\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[54\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[55\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[56\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[57\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[58\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[59\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[60\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[61\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[62\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[63\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[32\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[33\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[34\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[35\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[37\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[38\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[39\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[40\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[41\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[42\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[43\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[44\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[45\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[46\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[47\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[48\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[49\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[50\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[51\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[52\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[53\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[54\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[55\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[56\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[57\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[58\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[59\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[60\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[61\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[62\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[63\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 7)) (v_str32x2\[1\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4)) (v_str32x2\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_str32x2\[3\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_str32x2\[4\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_str32x2\[5\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_str32x2\[6\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_str32x2\[7\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_str32x2\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[32\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_str32x2\[33\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) (v_str32x2\[34\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_str32x2\[35\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[37\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[38\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[39\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[40\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[41\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[42\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[43\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[44\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[45\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[46\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[47\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[48\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[49\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[50\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[51\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[52\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[53\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[54\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[55\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[56\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[57\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[58\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[59\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[60\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[61\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[62\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[63\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_enumed\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) (v_enumed\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_enumed\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_enumed2\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) (v_enumed2\[3\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_enumed2\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumb\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_enumb\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 3)) (v_enumb\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_enumb2_str\[0\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 5)) (v_enumb2_str\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) (v_enumb2_str\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_enumb2_str\[3\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 5)) (v_enumb2_str\[4\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) (v_enumb2_str\[5\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2)) (unpacked_array[-2]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-2]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-2]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-2]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-2]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-2]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-2]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-2]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed (NET (PARAM\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[2\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (PARAM\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE p2 (NET (PARAM\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[1\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (PARAM\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE p3 (NET (PARAM\[0\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (PARAM\[1\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (PARAM\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE unnamedblk1 (NET (b\[0\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (b\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[2\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (b\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk2 (NET (a\[0\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (a\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[2\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (a\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) ) verilator-5.044/test_regress/t/t_concat_large.py0000755000542200017500000000073415125463617022426 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_savable_format1_bad.out0000644000542200017500000000040315125463617024026 0ustar mahmoudyfreeshellModel width = 40 Restoring model from 'obj_vlt/t_savable_format1_bad/saved.vltsv' %Error: obj_vlt/t_savable_format1_bad/saved.vltsv:0: Can't deserialize save-restore file as was made from different model: obj_vlt/t_savable_format1_bad/saved.vltsv Aborting... verilator-5.044/test_regress/t/t_func_no_lifetime_bad.out0000644000542200017500000000406415125463617024274 0ustar mahmoudyfreeshell%Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:26:17: Function/task's lifetime implicitly set to static : ... Suggest use 'function automatic' or 'function static' 26 | function int f_implicit_static(); | ^~~~~~~~~~~~~~~~~ t/t_func_no_lifetime_bad.v:27:11: ... Location of implicit static variable : ... The initializer value will only be set once 27 | int cnt = 0; | ^~~ ... For warning description see https://verilator.org/warn/IMPLICITSTATIC?v=latest ... Use "/* verilator lint_off IMPLICITSTATIC */" and lint_on around source to disable this message. %Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:31:9: Function/task's lifetime implicitly set to static : ... Suggest use 'task automatic' or 'task static' 31 | task t_implicit_static(); | ^~~~~~~~~~~~~~~~~ t/t_func_no_lifetime_bad.v:32:11: ... Location of implicit static variable : ... The initializer value will only be set once 32 | int cnt = 0; | ^~~ %Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:9:8: Variable's lifetime implicitly set to static : ... The initializer value will only be set once : ... Suggest use 'static' before variable declaration' 9 | int cnt = 0; | ^~~ %Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:15:8: Variable's lifetime implicitly set to static : ... The initializer value will only be set once : ... Suggest use 'static' before variable declaration' 15 | int cnt = 0; | ^~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_hier_bynum.py0000755000542200017500000000110415125463617022136 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(v_flags2=['t/t_hier_block.cpp'], verilator_flags2=['--hierarchical'], verilator_make_gmake=False) test.passes() verilator-5.044/test_regress/t/t_struct_init_trace.py0000755000542200017500000000105115125463617023523 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_struct_init.v" test.compile(verilator_flags2=['--cc --trace-vcd']) test.execute() test.passes() verilator-5.044/test_regress/t/t_class_virtual_pure_bad.py0000755000542200017500000000076315125463617024523 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_unpacked_slice_range.py0000755000542200017500000000073415125463617024132 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_vpi_escape.vlt0000644000542200017500000000077115125463617022276 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `verilator_config public_flat_rd -module "*" -var "double__underscore__vlt" public_flat_rd -module "sub_with_very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very_long_name" -var "subsig2" verilator-5.044/test_regress/t/t_timing_class.v0000644000542200017500000001512315125463617022271 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `ifdef TEST_VERBOSE `define WRITE_VERBOSE(args) $write args `else `define WRITE_VERBOSE(args) `endif class BaseClass; virtual task sleep; endtask virtual task await; endtask endclass module t; // ============================================= // EVENTS class EventClass extends BaseClass; event e; int trig_count; function new; trig_count = 0; endfunction task inc_trig_count; trig_count++; endtask; task sleep; @e inc_trig_count; `WRITE_VERBOSE(("Event in class triggered at time %0t!\n", $time)); endtask task wake; ->e; endtask endclass class WaitClass extends BaseClass; int a; int b; logic ok; function new; a = 0; b = 0; ok = 0; endfunction task await; wait(a == 4 && b > 16) if (a != 4 || b <= 16) $stop; ok = 1; `WRITE_VERBOSE(("Condition in object met at time %0t!\n", $time)); endtask endclass class LocalWaitClass extends BaseClass; logic ok; function new; ok = 0; endfunction task await; int a = 0; int b = 100; fork wait(a == 42 || b != 100) if (a != 42 && b == 100) $stop; #10 a = 42; join ok = 1; `WRITE_VERBOSE(("Condition with local variables met at time %0t!\n", $time)); endtask endclass class ClkClass; logic clk; int count; function new; clk = 0; count = 0; endfunction task flip; clk = ~clk; endtask; task count_5; @(posedge clk) count++; @(posedge clk) count++; @(posedge clk) count++; @(posedge clk) count++; @(posedge clk) count++; endtask endclass EventClass ec = new; WaitClass wc = new; LocalWaitClass lc = new; ClkClass cc = new; initial begin @ec.e; ec.sleep; if (wc.ok) $stop; wc.await; if (lc.ok) $stop; lc.await; end initial #20 ec.wake; initial #40 ->ec.e; initial begin wc.a = #50 4; wc.b = #10 32; end always @ec.e begin ec.inc_trig_count; `WRITE_VERBOSE(("Event in class triggered at time %0t!\n", $time)); end always #5 cc.flip; initial cc.count_5; initial begin #80 if (cc.count != 5) $stop; if (ec.trig_count != 3) $stop; if (!wc.ok) $stop; if (!lc.ok) $stop; end // ============================================= // DELAYS virtual class DelayClass; pure virtual task do_delay; pure virtual task do_sth_else; endclass `ifdef TEST_VERBOSE `define DELAY_CLASS(dt) \ class Delay``dt extends DelayClass; \ virtual task do_delay; \ $write("Starting a #%0d delay\n", dt); \ #dt \ $write("Ended a #%0d delay\n", dt); \ endtask \ virtual task do_sth_else; \ $write("Task with no delay (in Delay%0d)\n", dt); \ endtask \ endclass `else `define DELAY_CLASS(dt) \ class Delay``dt extends DelayClass; \ virtual task do_delay; \ #dt; \ endtask \ virtual task do_sth_else; \ endtask \ endclass `endif `DELAY_CLASS(10); `DELAY_CLASS(20); `DELAY_CLASS(40); class NoDelay extends DelayClass; virtual task do_delay; `WRITE_VERBOSE(("Task with no delay\n")); endtask virtual task do_sth_else; `WRITE_VERBOSE(("Task with no delay (in NoDelay)\n")); endtask endclass class AssignDelayClass; logic x; logic y; task do_assign; y = #10 x; `WRITE_VERBOSE(("Did assignment with delay\n")); endtask endclass initial begin DelayClass dc; Delay10 d10 = new; Delay20 d20 = new; Delay40 d40 = new; NoDelay dNo = new; AssignDelayClass dAsgn = new; `WRITE_VERBOSE(("I'm at time %0t\n", $time)); dc = d10; dc.do_delay; dc.do_sth_else; `WRITE_VERBOSE(("I'm at time %0t\n", $time)); if ($time != 10) $stop; dc = d20; dc.do_delay; dc.do_sth_else; `WRITE_VERBOSE(("I'm at time %0t\n", $time)); if ($time != 30) $stop; dc = d40; dc.do_delay; dc.do_sth_else; `WRITE_VERBOSE(("I'm at time %0t\n", $time)); if ($time != 70) $stop; dc = dNo; dc.do_delay; dc.do_sth_else; `WRITE_VERBOSE(("I'm at time %0t\n", $time)); dAsgn.x = 1; dAsgn.y = 0; fork #5 dAsgn.x = 0; join_none dAsgn.do_assign; if ($time != 80) $stop; if (dAsgn.y != 1) $stop; // Test if the object is deleted before do_assign finishes: fork dAsgn.do_assign; join_none #5 dAsgn = null; #15 $write("*-* All Finished *-*\n"); $finish; end // ============================================= // FORKS class ForkDelayClass; task do_delay; #40; endtask endclass class ForkClass; int done = 0; task do_fork(); ForkDelayClass d; fork begin #10 done++; `WRITE_VERBOSE(("Forked process %0d ending at time %0t\n", done, $time)); end fork begin #20 done++; `WRITE_VERBOSE(("Forked process %0d ending at time %0t\n", done, $time)); d = new; end begin #30 d.do_delay; done++; `WRITE_VERBOSE(("Forked process %0d ending at time %0t\n", done, $time)); end join join done++; `WRITE_VERBOSE(("All forked processes ended at time %0t\n", $time)); endtask endclass initial begin ForkClass fc = new; fc.do_fork; if (fc.done != 4 || $time != 70) $stop; end initial #101 $stop; // timeout endmodule verilator-5.044/test_regress/t/t_assert_ctl_concurrent.py0000755000542200017500000000077415125463617024416 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--binary --assert"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_typedef_iface_typedef7.py0000755000542200017500000000077115125463617024404 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_array_packed_write_read.v0000644000542200017500000002373415125463617024456 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // parameters for array sizes localparam WA = 8; // address dimension size localparam WB = 8; // bit dimension size localparam NO = 10; // number of access events // 2D packed arrays logic [WA-1:0] [WB-1:0] array_dsc; // descending range array /* verilator lint_off ASCRANGE */ logic [0:WA-1] [0:WB-1] array_asc; // ascending range array /* verilator lint_on ASCRANGE */ integer cnt = 0; // msg926 logic [3:0][31:0] packedArray; initial packedArray = '0; // event counter always @ (posedge clk) begin cnt <= cnt + 1; end // finish report always @ (posedge clk) if ((cnt[30:2]==NO) && (cnt[1:0]==2'd0)) begin $write("*-* All Finished *-*\n"); $finish; end // descending range always @ (posedge clk) if (cnt[1:0]==2'd0) begin // initialize to defaaults (all bits to 0) if (cnt[30:2]==0) array_dsc <= '0; else if (cnt[30:2]==1) array_dsc <= '0; else if (cnt[30:2]==2) array_dsc <= '0; else if (cnt[30:2]==3) array_dsc <= '0; else if (cnt[30:2]==4) array_dsc <= '0; else if (cnt[30:2]==5) array_dsc <= '0; else if (cnt[30:2]==6) array_dsc <= '0; else if (cnt[30:2]==7) array_dsc <= '0; else if (cnt[30:2]==8) array_dsc <= '0; else if (cnt[30:2]==9) array_dsc <= '0; end else if (cnt[1:0]==2'd1) begin // write value to array if (cnt[30:2]==0) begin end else if (cnt[30:2]==1) array_dsc <= {WA *WB +0{1'b1}}; else if (cnt[30:2]==2) array_dsc [WA/2-1:0 ] <= {WA/2*WB +0{1'b1}}; else if (cnt[30:2]==3) array_dsc [WA -1:WA/2] <= {WA/2*WB +0{1'b1}}; else if (cnt[30:2]==4) array_dsc [ 0 ] <= {1 *WB +0{1'b1}}; else if (cnt[30:2]==5) array_dsc [WA -1 ] <= {1 *WB +0{1'b1}}; else if (cnt[30:2]==6) array_dsc [ 0 ][WB/2-1:0 ] <= {1 *WB/2+0{1'b1}}; else if (cnt[30:2]==7) array_dsc [WA -1 ][WB -1:WB/2] <= {1 *WB/2+0{1'b1}}; else if (cnt[30:2]==8) array_dsc [ 0 ][ 0 ] <= {1 *1 +0{1'b1}}; else if (cnt[30:2]==9) array_dsc [WA -1 ][WB -1 ] <= {1 *1 +0{1'b1}}; end else if (cnt[1:0]==2'd2) begin // check array value if (cnt[30:2]==0) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2]==1) begin if (array_dsc !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2]==2) begin if (array_dsc !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2]==3) begin if (array_dsc !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2]==4) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2]==5) begin if (array_dsc !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2]==6) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2]==7) begin if (array_dsc !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2]==8) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2]==9) begin if (array_dsc !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end end else if (cnt[1:0]==2'd3) begin // read value from array (not a very good test for now) if (cnt[30:2]==0) begin if (array_dsc !== {WA *WB {1'b0}}) $stop(); end else if (cnt[30:2]==1) begin if (array_dsc !== {WA *WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==2) begin if (array_dsc [WA/2-1:0 ] !== {WA/2*WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==3) begin if (array_dsc [WA -1:WA/2] !== {WA/2*WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==4) begin if (array_dsc [ 0 ] !== {1 *WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==5) begin if (array_dsc [WA -1 ] !== {1 *WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==6) begin if (array_dsc [ 0 ][WB/2-1:0 ] !== {1 *WB/2+0{1'b1}}) $stop(); end else if (cnt[30:2]==7) begin if (array_dsc [WA -1 ][WB -1:WB/2] !== {1 *WB/2+0{1'b1}}) $stop(); end else if (cnt[30:2]==8) begin if (array_dsc [ 0 ][ 0 ] !== {1 *1 +0{1'b1}}) $stop(); end else if (cnt[30:2]==9) begin if (array_dsc [WA -1 ][WB -1 ] !== {1 *1 +0{1'b1}}) $stop(); end end // ascending range always @ (posedge clk) if (cnt[1:0]==2'd0) begin // initialize to defaaults (all bits to 0) if (cnt[30:2]==0) array_asc <= '0; else if (cnt[30:2]==1) array_asc <= '0; else if (cnt[30:2]==2) array_asc <= '0; else if (cnt[30:2]==3) array_asc <= '0; else if (cnt[30:2]==4) array_asc <= '0; else if (cnt[30:2]==5) array_asc <= '0; else if (cnt[30:2]==6) array_asc <= '0; else if (cnt[30:2]==7) array_asc <= '0; else if (cnt[30:2]==8) array_asc <= '0; else if (cnt[30:2]==9) array_asc <= '0; end else if (cnt[1:0]==2'd1) begin // write value to array if (cnt[30:2]==0) begin end else if (cnt[30:2]==1) array_asc <= {WA *WB +0{1'b1}}; else if (cnt[30:2]==2) array_asc [0 :WA/2-1] <= {WA/2*WB +0{1'b1}}; else if (cnt[30:2]==3) array_asc [WA/2:WA -1] <= {WA/2*WB +0{1'b1}}; else if (cnt[30:2]==4) array_asc [0 ] <= {1 *WB +0{1'b1}}; else if (cnt[30:2]==5) array_asc [ WA -1] <= {1 *WB +0{1'b1}}; else if (cnt[30:2]==6) array_asc [0 ][0 :WB/2-1] <= {1 *WB/2+0{1'b1}}; else if (cnt[30:2]==7) array_asc [ WA -1][WB/2:WB -1] <= {1 *WB/2+0{1'b1}}; else if (cnt[30:2]==8) array_asc [0 ][0 ] <= {1 *1 +0{1'b1}}; else if (cnt[30:2]==9) array_asc [ WA -1][ WB -1] <= {1 *1 +0{1'b1}}; end else if (cnt[1:0]==2'd2) begin // check array value if (cnt[30:2]==0) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2]==1) begin if (array_asc !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2]==2) begin if (array_asc !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2]==3) begin if (array_asc !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2]==4) begin if (array_asc !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2]==5) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2]==6) begin if (array_asc !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2]==7) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2]==8) begin if (array_asc !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2]==9) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_asc); $stop(); end end end else if (cnt[1:0]==2'd3) begin // read value from array (not a very good test for now) if (cnt[30:2]==0) begin if (array_asc !== {WA *WB {1'b0}}) $stop(); end else if (cnt[30:2]==1) begin if (array_asc !== {WA *WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==2) begin if (array_asc [0 :WA/2-1] !== {WA/2*WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==3) begin if (array_asc [WA/2:WA -1] !== {WA/2*WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==4) begin if (array_asc [0 ] !== {1 *WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==5) begin if (array_asc [ WA -1] !== {1 *WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==6) begin if (array_asc [0 ][0 :WB/2-1] !== {1 *WB/2+0{1'b1}}) $stop(); end else if (cnt[30:2]==7) begin if (array_asc [ WA -1][WB/2:WB -1] !== {1 *WB/2+0{1'b1}}) $stop(); end else if (cnt[30:2]==8) begin if (array_asc [0 ][0 ] !== {1 *1 +0{1'b1}}) $stop(); end else if (cnt[30:2]==9) begin if (array_asc [ WA -1][ WB -1] !== {1 *1 +0{1'b1}}) $stop(); end end endmodule verilator-5.044/test_regress/t/t_case_x.v0000644000542200017500000000270415125463617021060 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [3:0] value; reg [3:0] valuex; // verilator lint_off CASEOVERLAP // verilator lint_off CASEWITHX // verilator lint_off CASEX // Note for Verilator Xs must become zeros, or the Xs may match. initial begin value = 4'b1001; valuex = 4'b1xxx; case (value) 4'b1xxx: $stop; 4'b1???: $stop; 4'b1001: ; default: $stop; endcase case (valuex) 4'b1???: $stop; 4'b1xxx: ; 4'b1001: ; 4'b1000: ; // 1xxx is mapped to this by Verilator -x-assign 0 default: $stop; endcase // casex (value) 4'b100x: ; default: $stop; endcase casex (value) 4'b100?: ; default: $stop; endcase casex (valuex) 4'b100x: ; default: $stop; endcase casex (valuex) 4'b100?: ; default: $stop; endcase // casez (value) 4'bxxxx: $stop; 4'b100?: ; default: $stop; endcase casez (valuex) 4'b1xx?: ; 4'b100?: ; // 1xxx is mapped to this by Verilator -x-assign 0 default: $stop; endcase $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_constraint_struct_complex.py0000755000542200017500000000104615125463617025321 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_scheduling_many_clocks.py0000755000542200017500000000143115125463617024507 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.sim_time = 100000 test.scenarios('simulator') test.compile(verilator_flags2=["--stats"]) if test.vlt or test.vltmt: test.file_grep(test.stats, r"Scheduling, 'act' extra triggers\s+(\d+)", 1) test.file_grep(test.stats, r"Scheduling, 'act' pre triggers\s+(\d+)", 1) test.file_grep(test.stats, r"Scheduling, 'act' sense triggers\s+(\d+)", 228) test.execute() test.passes() verilator-5.044/test_regress/t/t_type_param.py0000755000542200017500000000073415125463617022146 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_math_repl2_bad.py0000755000542200017500000000076615125463617022655 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_select_bad_msb.py0000755000542200017500000000076315125463617022735 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_math_shift_extend.py0000755000542200017500000000073415125463617023502 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_wire_trireg_unsup.v0000644000542200017500000000061515125463617023371 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' // // Simple bi-directional alias test. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; trireg unsup; trireg (small) unsup_s; trireg (medium) unsup_m; trireg (large) unsup_l; endmodule verilator-5.044/test_regress/t/t_param_while.py0000755000542200017500000000073415125463617022275 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_hier_block_type_param_notfound_bad.py0000755000542200017500000000120615125463617027044 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_hier_block_type_param.v" test.compile(verilator_flags2=["--hierarchical-params-file", "/does-not-exist"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_packed_concat_bad.v0000644000542200017500000000122315125463617023175 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Driss Hafdi // SPDX-License-Identifier: CC0-1.0 module t; typedef logic [15:0] count_t; typedef bit [31:0] bit_int_t; localparam bit_int_t [1:0] count_bits = {2{$bits(count_t)}}; localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)}; initial begin if (count_bits[0] != 16) $stop; if (count_bits[1] != 16) $stop; if (count_bitsc[0] != 16) $stop; if (count_bitsc[1] != 16) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_class_extends_pkg_bad.py0000755000542200017500000000076615125463617024320 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_cover_line_trace.out0000644000542200017500000011367115125463617023471 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 >! clk $end $scope module t $end $var wire 1 >! clk $end $var wire 1 = toggle $end $var wire 32 # vlCoverageLineTrace_t_cover_line__15_block [31:0] $end $var wire 32 > cyc [31:0] $end $var wire 32 $ vlCoverageLineTrace_t_cover_line__18_block [31:0] $end $var wire 8 ? cyc_copy [7:0] $end $scope module b1 $end $var wire 1 >! clk $end $var wire 1 = toggle $end $var wire 32 2! vlCoverageLineTrace_t_cover_line__164_block [31:0] $end $var wire 32 3! vlCoverageLineTrace_t_cover_line__166_else [31:0] $end $var wire 32 T! vlCoverageLineTrace_t_cover_line__166_if [31:0] $end $var wire 32 4! vlCoverageLineTrace_t_cover_line__170_else [31:0] $end $var wire 32 5! vlCoverageLineTrace_t_cover_line__170_if [31:0] $end $var wire 32 6! vlCoverageLineTrace_t_cover_line__174_else [31:0] $end $upscope $end $scope module b2 $end $var wire 1 >! clk $end $var wire 1 = toggle $end $var wire 32 7! vlCoverageLineTrace_t_cover_line__164_block [31:0] $end $var wire 32 8! vlCoverageLineTrace_t_cover_line__166_else [31:0] $end $var wire 32 U! vlCoverageLineTrace_t_cover_line__166_if [31:0] $end $var wire 32 9! vlCoverageLineTrace_t_cover_line__170_else [31:0] $end $var wire 32 :! vlCoverageLineTrace_t_cover_line__170_if [31:0] $end $var wire 32 ;! vlCoverageLineTrace_t_cover_line__174_else [31:0] $end $upscope $end $scope module t1 $end $var wire 1 >! clk $end $var wire 1 = toggle $end $var wire 32 ! clk $end $var wire 1 = toggle $end $var wire 32 X vlCoverageLineTrace_t_cover_line__140_block [31:0] $end $var wire 32 Y vlCoverageLineTrace_t_cover_line__141_else [31:0] $end $var wire 32 Z vlCoverageLineTrace_t_cover_line__141_if [31:0] $end $var wire 32 [ vlCoverageLineTrace_t_cover_line__145_else [31:0] $end $upscope $end $scope module a2 $end $var wire 1 >! clk $end $var wire 1 = toggle $end $var wire 32 \ vlCoverageLineTrace_t_cover_line__140_block [31:0] $end $var wire 32 ] vlCoverageLineTrace_t_cover_line__141_else [31:0] $end $var wire 32 ^ vlCoverageLineTrace_t_cover_line__141_if [31:0] $end $var wire 32 _ vlCoverageLineTrace_t_cover_line__145_else [31:0] $end $upscope $end $scope module cond1 $end $var wire 1 >! clk $end $var wire 32 > cyc [31:0] $end $var wire 1 2 a $end $var wire 1 3 b $end $var wire 1 * c $end $var wire 1 ` d $end $var wire 1 4 e $end $var wire 1 a f $end $var wire 1 + g $end $var wire 1 b h $end $var wire 1 c k $end $var wire 1 I! l $end $var wire 1 @! m $end $var wire 6 , tab [5:0] $end $var wire 8 d data[0][0] [7:0] $end $var wire 8 e data[0][1] [7:0] $end $var wire 8 f data[1][0] [7:0] $end $var wire 8 g data[1][1] [7:0] $end $var wire 32 % vlCoverageLineTrace_t_cover_line__315_block [31:0] $end $var wire 32 h pstruct [31:0] $end $var wire 32 - vlCoverageLineTrace_t_cover_line__323_block [31:0] $end $var wire 32 i vlCoverageLineTrace_t_cover_line__328_block [31:0] $end $var wire 8 J! get_arr__Vstatic__arr[0] [7:0] $end $var wire 8 K! get_arr__Vstatic__arr[1] [7:0] $end $var wire 32 5 vlCoverageLineTrace_t_cover_line__333_cond_else [31:0] $end $var wire 32 6 vlCoverageLineTrace_t_cover_line__333_cond_then [31:0] $end $var wire 32 7 vlCoverageLineTrace_t_cover_line__334_cond_else [31:0] $end $var wire 32 8 vlCoverageLineTrace_t_cover_line__334_cond_then [31:0] $end $var wire 32 . vlCoverageLineTrace_t_cover_line__335_cond_else [31:0] $end $var wire 32 / vlCoverageLineTrace_t_cover_line__335_cond_then [31:0] $end $var wire 32 j vlCoverageLineTrace_t_cover_line__336_block [31:0] $end $var wire 32 k vlCoverageLineTrace_t_cover_line__337_cond_else [31:0] $end $var wire 32 l vlCoverageLineTrace_t_cover_line__337_cond_then [31:0] $end $var wire 32 m vlCoverageLineTrace_t_cover_line__338_cond_else [31:0] $end $var wire 32 n vlCoverageLineTrace_t_cover_line__338_cond_then [31:0] $end $var wire 32 9 vlCoverageLineTrace_t_cover_line__340_cond_else_1 [31:0] $end $var wire 32 : vlCoverageLineTrace_t_cover_line__340_cond_then_1 [31:0] $end $var wire 32 ; vlCoverageLineTrace_t_cover_line__340_cond_else [31:0] $end $var wire 32 < vlCoverageLineTrace_t_cover_line__340_cond_then [31:0] $end $var wire 32 o vlCoverageLineTrace_t_cover_line__343_cond_else [31:0] $end $var wire 32 p vlCoverageLineTrace_t_cover_line__343_cond_then [31:0] $end $var wire 32 L! vlCoverageLineTrace_t_cover_line__349_cond_else [31:0] $end $var wire 32 0 vlCoverageLineTrace_t_cover_line__349_cond_else_1 [31:0] $end $var wire 32 M! vlCoverageLineTrace_t_cover_line__349_cond_then [31:0] $end $var wire 32 1 vlCoverageLineTrace_t_cover_line__349_cond_then_1 [31:0] $end $var wire 32 & vlCoverageLineTrace_t_cover_line__352_block [31:0] $end $var wire 32 q vlCoverageLineTrace_t_cover_line__353_else [31:0] $end $var wire 32 r vlCoverageLineTrace_t_cover_line__353_if [31:0] $end $var wire 32 s vlCoverageLineTrace_t_cover_line__353_cond_else [31:0] $end $var wire 32 t vlCoverageLineTrace_t_cover_line__353_cond_then [31:0] $end $var wire 32 u vlCoverageLineTrace_t_cover_line__356_cond_else [31:0] $end $var wire 32 v vlCoverageLineTrace_t_cover_line__356_cond_then [31:0] $end $var wire 32 ' vlCoverageLineTrace_t_cover_line__359_block [31:0] $end $var wire 32 w vlCoverageLineTrace_t_cover_line__362_block [31:0] $end $var wire 32 x vlCoverageLineTrace_t_cover_line__362_cond_else [31:0] $end $var wire 32 y vlCoverageLineTrace_t_cover_line__362_cond_then [31:0] $end $var wire 32 z vlCoverageLineTrace_t_cover_line__366_else [31:0] $end $var wire 32 { vlCoverageLineTrace_t_cover_line__366_if [31:0] $end $var wire 32 | vlCoverageLineTrace_t_cover_line__370_cond_else [31:0] $end $var wire 32 } vlCoverageLineTrace_t_cover_line__370_cond_then [31:0] $end $var wire 32 ~ vlCoverageLineTrace_t_cover_line__373_block [31:0] $end $var wire 32 !! vlCoverageLineTrace_t_cover_line__374_else [31:0] $end $var wire 32 "! vlCoverageLineTrace_t_cover_line__374_if [31:0] $end $scope module unnamedblk1 $end $var wire 32 N! i [31:0] $end $upscope $end $scope module unnamedblk2 $end $var wire 32 #! i [31:0] $end $upscope $end $upscope $end $scope module o1 $end $var wire 1 >! clk $end $var wire 1 = toggle $end $var wire 32 $! vlCoverageLineTrace_t_cover_line__253_block [31:0] $end $var wire 32 %! vlCoverageLineTrace_t_cover_line__254_else [31:0] $end $var wire 32 &! vlCoverageLineTrace_t_cover_line__254_if [31:0] $end $var wire 32 '! vlCoverageLineTrace_t_cover_line__257_else [31:0] $end $var wire 32 O! vlCoverageLineTrace_t_cover_line__257_if [31:0] $end $upscope $end $scope module par1 $end $var wire 32 P! CALLS_FUNC [31:0] $end $var wire 32 Q! vlCoverageLineTrace_t_cover_line__288_block [31:0] $end $var wire 32 R! vlCoverageLineTrace_t_cover_line__289_else [31:0] $end $var wire 32 S! vlCoverageLineTrace_t_cover_line__289_if [31:0] $end $upscope $end $scope module tab1 $end $var wire 1 >! clk $end $var wire 4 (! cyc4 [3:0] $end $var wire 32 )! decoded [31:0] $end $var wire 32 *! vlCoverageLineTrace_t_cover_line__266_block [31:0] $end $var wire 32 +! vlCoverageLineTrace_t_cover_line__268_case [31:0] $end $var wire 32 ,! vlCoverageLineTrace_t_cover_line__269_case [31:0] $end $var wire 32 -! vlCoverageLineTrace_t_cover_line__270_case [31:0] $end $var wire 32 .! vlCoverageLineTrace_t_cover_line__271_case [31:0] $end $var wire 32 /! vlCoverageLineTrace_t_cover_line__272_case [31:0] $end $var wire 32 0! vlCoverageLineTrace_t_cover_line__273_case [31:0] $end $var wire 32 1! vlCoverageLineTrace_t_cover_line__277_block [31:0] $end $upscope $end $upscope $end $scope module my_pkg $end $var wire 32 ( x [31:0] $end $var wire 32 ) vlCoverageLineTrace_t_cover_line__301_block [31:0] $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000001 # b00000000000000000000000000000001 $ b00000000000000000000000000000001 % b00000000000000000000000000000001 & b00000000000000000000000000000101 ' b00000000000000000000000000000001 ( b00000000000000000000000000000001 ) 0* 0+ b000001 , b00000000000000000000000000000010 - b00000000000000000000000000000000 . b00000000000000000000000000000010 / b00000000000000000000000000000010 0 b00000000000000000000000000000000 1 02 03 04 b00000000000000000000000000000010 5 b00000000000000000000000000000000 6 b00000000000000000000000000000000 7 b00000000000000000000000000000010 8 b00000000000000000000000000000000 9 b00000000000000000000000000000010 : b00000000000000000000000000000010 ; b00000000000000000000000000000000 < 0= b00000000000000000000000000000001 > b00000001 ? b00000000000000000000000000000000 @ b00000000000000000000000000000000 A b00000000000000000000000000000000 B b00000000000000000000000000000000 C b00000000000000000000000000000000 D b00000000000000000000000000000000 E b00000000000000000000000000000000 F b00000000000000000000000000000000 G b00000000000000000000000000000000 H b00000000000000000000000000000000 I b00000000000000000000000000000000 J b00000000000000000000000000000000 K b00000000000000000000000000000000 L b00000000000000000000000000000000 M b00000000000000000000000000000000 N b00000000000000000000000000000000 O b00000000000000000000000000000000 P b00000000000000000000000000000000 Q b00000000000000000000000000000000 R b00000000000000000000000000000000 S b00000000000000000000000000000000 T b00000000000000000000000000000000 U b00000000000000000000000000000000 V b00000000000000000000000000000000 W b00000000000000000000000000000000 X b00000000000000000000000000000000 Y b00000000000000000000000000000000 Z b00000000000000000000000000000000 [ b00000000000000000000000000000000 \ b00000000000000000000000000000000 ] b00000000000000000000000000000000 ^ b00000000000000000000000000000000 _ 0` 1a 1b 0c b00000000 d b00000000 e b00000000 f b00000000 g b00000000000000100000000000000000 h b00000000000000000000000000000001 i b00000000000000000000000000000000 j b00000000000000000000000000000000 k b00000000000000000000000000000000 l b00000000000000000000000000000000 m b00000000000000000000000000000000 n b00000000000000000000000000000000 o b00000000000000000000000000000001 p b00000000000000000000000000000001 q b00000000000000000000000000000000 r b00000000000000000000000000000000 s b00000000000000000000000000000000 t b00000000000000000000000000000001 u b00000000000000000000000000000000 v b00000000000000000000000000000100 w b00000000000000000000000000000011 x b00000000000000000000000000000001 y b00000000000000000000000000000001 z b00000000000000000000000000000000 { b00000000000000000000000000000000 | b00000000000000000000000000000001 } b00000000000000000000000000000000 ~ b00000000000000000000000000000000 !! b00000000000000000000000000000000 "! b00000000000000000000000000000111 #! b00000000000000000000000000000000 $! b00000000000000000000000000000000 %! b00000000000000000000000000000000 &! b00000000000000000000000000000000 '! b0000 (! b00000000000000000000000000000000 )! b00000000000000000000000000000000 *! b00000000000000000000000000000000 +! b00000000000000000000000000000000 ,! b00000000000000000000000000000000 -! b00000000000000000000000000000000 .! b00000000000000000000000000000000 /! b00000000000000000000000000000000 0! b00000000000000000000000000000000 1! b00000000000000000000000000000000 2! b00000000000000000000000000000000 3! b00000000000000000000000000000000 4! b00000000000000000000000000000000 5! b00000000000000000000000000000000 6! b00000000000000000000000000000000 7! b00000000000000000000000000000000 8! b00000000000000000000000000000000 9! b00000000000000000000000000000000 :! b00000000000000000000000000000000 ;! b00000000000000000000000000000000 ! b00000000000000000000000000000000 ?! 0@! b00000000000000000000000000000000 A! b00000000000000000000000000000000 B! b00000000000000000000000000000000 C! b00000000000000000000000000000000 D! b00000000000000000000000000000000 E! b00000000000000000000000000000000 F! b00000000000000000000000000000000 G! b00000000000000000000000000000000 H! 0I! b00000000 J! b00000000 K! b00000000000000000000000000000000 L! b00000000000000000000000000000000 M! b00000000000000000000000000000101 N! b00000000000000000000000000000000 O! b00000000000000000000000000000010 P! b00000000000000000000000000000000 Q! b00000000000000000000000000000000 R! b00000000000000000000000000000000 S! b00000000000000000000000000000000 T! b00000000000000000000000000000000 U! #10 1* 1+ b000011 , b00000000000000000000000000000011 - b00000000000000000000000000000011 / b00000000000000000000000000000001 1 14 b00000000000000000000000000000100 5 b00000000000000000000000000000001 7 b00000000000000000000000000000011 8 b00000000000000000000000000000001 9 b00000000000000000000000000000011 : b00000000000000000000000000000001 < b00000000000000000000000000000010 > b00000010 ? b00000000000000000000000000000001 @ b00000000000000000000000000000001 B b00000000000000000000000000000001 C b00000000000000000000000000000001 E b00000000000000000000000000000001 G b00000000000000000000000000000001 I b00000000000000000000000000000001 K b00000000000000000000000000000001 M b00000000000000000000000000000001 Q b00000000000000000000000000000001 S b00000000000000000000000000000001 V b00000000000000000000000000000001 X b00000000000000000000000000000001 Y b00000000000000000000000000000001 [ b00000000000000000000000000000001 \ b00000000000000000000000000000001 ] b00000000000000000000000000000001 _ b00000010 d b00000001 e b00000000000000110000000000000000 h b00000000000000000000000000000001 j b00000000000000000000000000000001 k b00000000000000000000000000000001 m b00000000000000000000000000000010 p b00000000000000000000000000000010 q b00000000000000000000000000000001 v b00000000000000000000000000001000 w b00000000000000000000000000000110 x b00000000000000000000000000000010 y b00000000000000000000000000000010 z b00000000000000000000000000000001 | b00000000000000000000000000000001 ~ b00000000000000000000000000000001 !! b00000000000000000000000000000001 $! b00000000000000000000000000000001 %! b0001 (! b00000000000000000000000000000001 *! b00000000000000000000000000000001 0! b00000000000000000000000000000001 1! b00000000000000000000000000000001 2! b00000000000000000000000000000001 3! b00000000000000000000000000000001 4! b00000000000000000000000000000001 6! b00000000000000000000000000000001 7! b00000000000000000000000000000001 8! b00000000000000000000000000000001 9! b00000000000000000000000000000001 ;! b00000000000000000000000000000001 ! b00000000000000000000000000000001 A! b00000000000000000000000000000001 B! #15 0* 0+ b00000000000000000000000000000100 - b00000000000000000000000000000100 / b00000000000000000000000000000011 0 b00000000000000000000000000000101 5 b00000000000000000000000000000010 7 b00000000000000000000000000000010 9 0>! #20 1* 1+ b00000000000000000000000000000101 - b00000000000000000000000000000101 / b00000000000000000000000000000010 1 b00000000000000000000000000000111 5 b00000000000000000000000000000100 7 b00000000000000000000000000000100 9 b00000000000000000000000000000011 > b00000011 ? b00000000000000000000000000000010 @ b00000000000000000000000000000010 B b00000000000000000000000000000010 C b00000000000000000000000000000010 E b00000000000000000000000000000010 G b00000000000000000000000000000010 I b00000000000000000000000000000010 K b00000000000000000000000000000010 M b00000000000000000000000000000010 Q b00000000000000000000000000000010 S b00000000000000000000000000000010 V b00000000000000000000000000000010 X b00000000000000000000000000000010 Y b00000000000000000000000000000010 [ b00000000000000000000000000000010 \ b00000000000000000000000000000010 ] b00000000000000000000000000000010 _ b00000000 d b00000000 e b00000000000000000000000000000010 i b00000000000000000000000000000010 j b00000000000000000000000000000010 k b00000000000000000000000000000010 m b00000000000000000000000000000011 p b00000000000000000000000000000011 q b00000000000000000000000000000010 u b00000000000000000000000000001100 w b00000000000000000000000000001001 x b00000000000000000000000000000011 y b00000000000000000000000000000011 z b00000000000000000000000000000010 | b00000000000000000000000000000010 ~ b00000000000000000000000000000001 "! b00000000000000000000000000000010 $! b00000000000000000000000000000010 %! b0010 (! b00000000000000000000000000001010 )! b00000000000000000000000000000010 *! b00000000000000000000000000000001 +! b00000000000000000000000000000010 1! b00000000000000000000000000000010 2! b00000000000000000000000000000010 3! b00000000000000000000000000000010 4! b00000000000000000000000000000010 6! b00000000000000000000000000000010 7! b00000000000000000000000000000010 8! b00000000000000000000000000000010 9! b00000000000000000000000000000010 ;! b00000000000000000000000000000010 ! b00000000000000000000000000000010 A! b00000000000000000000000000000010 B! #25 0* 0+ b00000000000000000000000000000110 - b00000000000000000000000000000110 / b00000000000000000000000000000100 0 b00000000000000000000000000001000 5 b00000000000000000000000000000101 7 b00000000000000000000000000000101 9 0>! #30 1* 1+ b00000000000000000000000000000111 - b00000000000000000000000000000111 / b00000000000000000000000000000011 1 b00000000000000000000000000001010 5 b00000000000000000000000000000111 7 b00000000000000000000000000000110 9 b00000000000000000000000000000100 : b00000000000000000000000000000010 < 1= b00000000000000000000000000000100 > b00000100 ? b00000000000000000000000000000011 @ b00000000000000000000000000000011 B b00000000000000000000000000000001 D b00000000000000000000000000000001 F b00000000000000000000000000000001 H b00000000000000000000000000000001 J b00000000000000000000000000000001 L b00000000000000000000000000000001 N b00000000000000000000000000000001 O b00000000000000000000000000000011 S b00000000000000000000000000000001 T b00000000000000000000000000000011 X b00000000000000000000000000000011 Y b00000000000000000000000000000011 [ b00000000000000000000000000000011 \ b00000000000000000000000000000011 ] b00000000000000000000000000000011 _ 1` b00000000000000000000000000000011 i b00000000000000000000000000000011 j b00000000000000000000000000000001 l b00000000000000000000000000000011 m b00000000000000000000000000000100 p b00000000000000000000000000000100 q b00000000000000000000000000000011 u b00000000000000000000000000010000 w b00000000000000000000000000001100 x b00000000000000000000000000000100 y b00000000000000000000000000000100 z b00000000000000000000000000000011 | b00000000000000000000000000000011 ~ b00000000000000000000000000000010 !! b00000000000000000000000000000011 $! b00000000000000000000000000000011 %! b0011 (! b00000000000000000000000000010100 )! b00000000000000000000000000000011 *! b00000000000000000000000000000001 ,! b00000000000000000000000000000011 1! b00000000000000000000000000000011 2! b00000000000000000000000000000011 3! b00000000000000000000000000000011 4! b00000000000000000000000000000011 6! b00000000000000000000000000000011 7! b00000000000000000000000000000011 8! b00000000000000000000000000000011 9! b00000000000000000000000000000011 ;! b00000000000000000000000000000011 ! b00000000000000000000000000000011 A! b00000000000000000000000000000011 B! #35 0* 0+ b00000000000000000000000000001000 - b00000000000000000000000000001000 / b00000000000000000000000000000101 0 04 b00000000000000000000000000001011 5 b00000000000000000000000000001000 7 b00000000000000000000000000000101 : b00000000000000000000000000000011 ; 0>! #40 1* 1+ b00000000000000000000000000001001 - b00000000000000000000000000001001 / b00000000000000000000000000000100 1 14 b00000000000000000000000000001101 5 b00000000000000000000000000001010 7 b00000000000000000000000000000111 9 b00000000000000000000000000000110 : b00000000000000000000000000000011 < 0= b00000000000000000000000000000101 > b00000101 ? b00000000000000000000000000000100 @ b00000000000000000000000000000100 B b00000000000000000000000000000011 C b00000000000000000000000000000011 E b00000000000000000000000000000011 G b00000000000000000000000000000011 I b00000000000000000000000000000011 K b00000000000000000000000000000011 M b00000000000000000000000000000001 P b00000000000000000000000000000100 S b00000000000000000000000000000011 V b00000000000000000000000000000100 X b00000000000000000000000000000001 Z b00000000000000000000000000000100 \ b00000000000000000000000000000001 ^ 0` 0b b00000000000000000000000000000100 i b00000000000000000000000000000100 j b00000000000000000000000000000011 k b00000000000000000000000000000100 m b00000000000000000000000000000101 p b00000000000000000000000000000001 r b00000000000000000000000000000001 s b00000000000000000000000000000100 u b00000000000000000000000000010100 w b00000000000000000000000000001111 x b00000000000000000000000000000101 y b00000000000000000000000000000101 z b00000000000000000000000000000100 | b00000000000000000000000000000100 ~ b00000000000000000000000000000011 !! b00000000000000000000000000000100 $! b00000000000000000000000000000001 &! b00000000000000000000000000000001 '! b0100 (! b00000000000000000000000000011110 )! b00000000000000000000000000000100 *! b00000000000000000000000000000001 -! b00000000000000000000000000000100 1! b00000000000000000000000000000100 2! b00000000000000000000000000000100 3! b00000000000000000000000000000001 5! b00000000000000000000000000000100 7! b00000000000000000000000000000100 8! b00000000000000000000000000000001 :! b00000000000000000000000000000100 ! b00000000000000000000000000000100 A! b00000000000000000000000000000001 C! #45 0* 0+ b00000000000000000000000000001010 - b00000000000000000000000000001010 / b00000000000000000000000000000110 0 b00000000000000000000000000001110 5 b00000000000000000000000000001011 7 b00000000000000000000000000001000 9 0>! #50 1* 1+ b00000000000000000000000000001011 - b00000000000000000000000000001011 / b00000000000000000000000000000101 1 b00000000000000000000000000010000 5 b00000000000000000000000000001101 7 b00000000000000000000000000001010 9 b00000000000000000000000000000110 > b00000110 ? b00000000000000000000000000000101 @ b00000000000000000000000000000101 B b00000000000000000000000000000100 C b00000000000000000000000000000100 E b00000000000000000000000000000100 G b00000000000000000000000000000100 I b00000000000000000000000000000100 K b00000000000000000000000000000100 M b00000000000000000000000000000001 R b00000000000000000000000000000101 S b00000000000000000000000000000001 U b00000000000000000000000000000101 X b00000000000000000000000000000100 Y b00000000000000000000000000000100 [ b00000000000000000000000000000101 \ b00000000000000000000000000000100 ] b00000000000000000000000000000100 _ 1b b00000000000000000000000000000101 i b00000000000000000000000000000101 j b00000000000000000000000000000100 k b00000000000000000000000000000101 m b00000000000000000000000000000110 p b00000000000000000000000000000101 q b00000000000000000000000000000101 u b00000000000000000000000000011000 w b00000000000000000000000000010010 x b00000000000000000000000000000110 y b00000000000000000000000000000110 z b00000000000000000000000000000101 | b00000000000000000000000000000101 ~ b00000000000000000000000000000100 !! b00000000000000000000000000000101 $! b00000000000000000000000000000100 %! b0101 (! b00000000000000000000000000101000 )! b00000000000000000000000000000101 *! b00000000000000000000000000000001 .! b00000000000000000000000000000101 1! b00000000000000000000000000000101 2! b00000000000000000000000000000101 3! b00000000000000000000000000000100 4! b00000000000000000000000000000100 6! b00000000000000000000000000000101 7! b00000000000000000000000000000101 8! b00000000000000000000000000000100 9! b00000000000000000000000000000100 ;! b00000000000000000000000000000101 ! b00000000000000000000000000000001 ?! b00000000000000000000000000000110 A! b00000000000000000000000000000101 B! b00000000000000000000000000000001 D! #55 0* 0+ b00000000000000000000000000001100 - b00000000000000000000000000001100 / b00000000000000000000000000000111 0 b00000000000000000000000000010001 5 b00000000000000000000000000001110 7 b00000000000000000000000000001011 9 0>! #60 1* 1+ b00000000000000000000000000001101 - b00000000000000000000000000001101 / b00000000000000000000000000000110 1 b00000000000000000000000000010011 5 b00000000000000000000000000010000 7 b00000000000000000000000000001100 9 b00000000000000000000000000000111 : b00000000000000000000000000000100 < b00000000000000000000000000000111 > b00000111 ? b00000000000000000000000000000110 @ b00000000000000000000000000000110 B b00000000000000000000000000000101 C b00000000000000000000000000000101 E b00000000000000000000000000000101 G b00000000000000000000000000000101 I b00000000000000000000000000000101 K b00000000000000000000000000000101 M b00000000000000000000000000000011 Q b00000000000000000000000000000110 S b00000000000000000000000000000100 V b00000000000000000000000000000110 X b00000000000000000000000000000101 Y b00000000000000000000000000000101 [ b00000000000000000000000000000110 \ b00000000000000000000000000000101 ] b00000000000000000000000000000101 _ 1` b00000000000000000000000000000110 i b00000000000000000000000000000110 j b00000000000000000000000000000010 l b00000000000000000000000000000110 m b00000000000000000000000000000111 p b00000000000000000000000000000110 q b00000000000000000000000000000110 u b00000000000000000000000000011100 w b00000000000000000000000000010101 x b00000000000000000000000000000111 y b00000000000000000000000000000111 z b00000000000000000000000000000110 | b00000000000000000000000000000110 ~ b00000000000000000000000000000101 !! b00000000000000000000000000000110 $! b00000000000000000000000000000101 %! b0110 (! b00000000000000000000000000110010 )! b00000000000000000000000000000110 *! b00000000000000000000000000000001 /! b00000000000000000000000000000110 1! b00000000000000000000000000000110 2! b00000000000000000000000000000110 3! b00000000000000000000000000000101 4! b00000000000000000000000000000101 6! b00000000000000000000000000000110 7! b00000000000000000000000000000110 8! b00000000000000000000000000000101 9! b00000000000000000000000000000101 ;! b00000000000000000000000000000110 ! b00000000000000000000000000000111 A! b00000000000000000000000000000110 B! #65 0* 0+ b00000000000000000000000000001110 - b00000000000000000000000000001110 / b00000000000000000000000000001000 0 04 b00000000000000000000000000010100 5 b00000000000000000000000000010001 7 b00000000000000000000000000001000 : b00000000000000000000000000000100 ; 0>! #70 1* 1+ b00000000000000000000000000001111 - b00000000000000000000000000001111 / b00000000000000000000000000000111 1 14 b00000000000000000000000000010110 5 b00000000000000000000000000010011 7 b00000000000000000000000000001101 9 b00000000000000000000000000001001 : b00000000000000000000000000000101 < b00000000000000000000000000001000 > b00001000 ? b00000000000000000000000000000111 @ b00000000000000000000000000000111 B b00000000000000000000000000000110 C b00000000000000000000000000000110 E b00000000000000000000000000000110 G b00000000000000000000000000000110 I b00000000000000000000000000000110 K b00000000000000000000000000000110 M b00000000000000000000000000000100 Q b00000000000000000000000000000111 S b00000000000000000000000000000101 V b00000000000000000000000000000111 X b00000000000000000000000000000110 Y b00000000000000000000000000000110 [ b00000000000000000000000000000111 \ b00000000000000000000000000000110 ] b00000000000000000000000000000110 _ 0` b00000000000000000000000000000111 i b00000000000000000000000000000111 j b00000000000000000000000000000101 k b00000000000000000000000000000111 m b00000000000000000000000000001000 p b00000000000000000000000000000111 q b00000000000000000000000000000111 u b00000000000000000000000000100000 w b00000000000000000000000000011000 x b00000000000000000000000000001000 y b00000000000000000000000000001000 z b00000000000000000000000000000111 | b00000000000000000000000000000111 ~ b00000000000000000000000000000110 !! b00000000000000000000000000000111 $! b00000000000000000000000000000110 %! b0111 (! b00000000000000000000000000000000 )! b00000000000000000000000000000111 *! b00000000000000000000000000000010 0! b00000000000000000000000000000111 1! b00000000000000000000000000000111 2! b00000000000000000000000000000111 3! b00000000000000000000000000000110 4! b00000000000000000000000000000110 6! b00000000000000000000000000000111 7! b00000000000000000000000000000111 8! b00000000000000000000000000000110 9! b00000000000000000000000000000110 ;! b00000000000000000000000000000111 ! b00000000000000000000000000001000 A! b00000000000000000000000000000111 B! #75 0* 0+ b00000000000000000000000000010000 - b00000000000000000000000000010000 / b00000000000000000000000000001001 0 b00000000000000000000000000010111 5 b00000000000000000000000000010100 7 b00000000000000000000000000001110 9 0>! #80 1* 1+ b00000000000000000000000000010001 - b00000000000000000000000000010001 / b00000000000000000000000000001000 1 b00000000000000000000000000011001 5 b00000000000000000000000000010110 7 b00000000000000000000000000010000 9 b00000000000000000000000000001001 > b00001001 ? b00000000000000000000000000001000 @ b00000000000000000000000000001000 B b00000000000000000000000000000111 C b00000000000000000000000000000111 E b00000000000000000000000000000111 G b00000000000000000000000000000111 I b00000000000000000000000000000111 K b00000000000000000000000000000111 M b00000000000000000000000000000101 Q b00000000000000000000000000001000 S b00000000000000000000000000000110 V b00000000000000000000000000001000 X b00000000000000000000000000000111 Y b00000000000000000000000000000111 [ b00000000000000000000000000001000 \ b00000000000000000000000000000111 ] b00000000000000000000000000000111 _ b00000000000000000000000000001000 i b00000000000000000000000000001000 j b00000000000000000000000000000110 k b00000000000000000000000000001000 m b00000000000000000000000000001001 p b00000000000000000000000000001000 q b00000000000000000000000000001000 u b00000000000000000000000000100100 w b00000000000000000000000000011011 x b00000000000000000000000000001001 y b00000000000000000000000000001001 z b00000000000000000000000000001000 | b00000000000000000000000000001000 ~ b00000000000000000000000000000111 !! b00000000000000000000000000001000 $! b00000000000000000000000000000111 %! b1000 (! b00000000000000000000000000001000 *! b00000000000000000000000000000011 0! b00000000000000000000000000001000 1! b00000000000000000000000000001000 2! b00000000000000000000000000001000 3! b00000000000000000000000000000111 4! b00000000000000000000000000000111 6! b00000000000000000000000000001000 7! b00000000000000000000000000001000 8! b00000000000000000000000000000111 9! b00000000000000000000000000000111 ;! b00000000000000000000000000001000 ! b00000000000000000000000000001001 A! b00000000000000000000000000001000 B! #85 0* 0+ b00000000000000000000000000010010 - b00000000000000000000000000010010 / b00000000000000000000000000001010 0 b00000000000000000000000000011010 5 b00000000000000000000000000010111 7 b00000000000000000000000000010001 9 0>! #90 1* 1+ b00000000000000000000000000010011 - b00000000000000000000000000010011 / b00000000000000000000000000001001 1 b00000000000000000000000000011100 5 b00000000000000000000000000011001 7 b00000000000000000000000000010010 9 b00000000000000000000000000001010 : b00000000000000000000000000000110 < b00000000000000000000000000001010 > b00001010 ? b00000000000000000000000000001001 @ b00000000000000000000000000001001 B b00000000000000000000000000001000 C b00000000000000000000000000001000 E b00000000000000000000000000001000 G b00000000000000000000000000001000 I b00000000000000000000000000001000 K b00000000000000000000000000001000 M b00000000000000000000000000000110 Q b00000000000000000000000000001001 S b00000000000000000000000000000111 V b00000000000000000000000000001001 X b00000000000000000000000000001000 Y b00000000000000000000000000001000 [ b00000000000000000000000000001001 \ b00000000000000000000000000001000 ] b00000000000000000000000000001000 _ 1` b00000000000000000000000000001001 i b00000000000000000000000000001001 j b00000000000000000000000000000011 l b00000000000000000000000000001001 m b00000000000000000000000000001010 p b00000000000000000000000000001001 q b00000000000000000000000000001001 u b00000000000000000000000000101000 w b00000000000000000000000000011110 x b00000000000000000000000000001010 y b00000000000000000000000000001010 z b00000000000000000000000000001001 | b00000000000000000000000000001001 ~ b00000000000000000000000000001000 !! b00000000000000000000000000001001 $! b00000000000000000000000000001000 %! b1001 (! b00000000000000000000000000001001 *! b00000000000000000000000000000100 0! b00000000000000000000000000001001 1! b00000000000000000000000000001001 2! b00000000000000000000000000001001 3! b00000000000000000000000000001000 4! b00000000000000000000000000001000 6! b00000000000000000000000000001001 7! b00000000000000000000000000001001 8! b00000000000000000000000000001000 9! b00000000000000000000000000001000 ;! b00000000000000000000000000001001 ! b00000000000000000000000000001010 A! b00000000000000000000000000001001 B! #95 0* 0+ b00000000000000000000000000010100 - b00000000000000000000000000010100 / b00000000000000000000000000001011 0 04 b00000000000000000000000000011101 5 b00000000000000000000000000011010 7 b00000000000000000000000000001011 : b00000000000000000000000000000101 ; 0>! #100 1* 1+ b00000000000000000000000000010101 - b00000000000000000000000000010101 / b00000000000000000000000000001010 1 14 b00000000000000000000000000011111 5 b00000000000000000000000000011100 7 b00000000000000000000000000010011 9 b00000000000000000000000000001100 : b00000000000000000000000000000111 < b00000000000000000000000000001011 > b00001011 ? b00000000000000000000000000001010 @ b00000000000000000000000000001010 B b00000000000000000000000000001001 C b00000000000000000000000000001001 E b00000000000000000000000000001001 G b00000000000000000000000000001001 I b00000000000000000000000000001001 K b00000000000000000000000000001001 M b00000000000000000000000000000111 Q b00000000000000000000000000001010 S b00000000000000000000000000000001 W b00000000000000000000000000001010 X b00000000000000000000000000001001 Y b00000000000000000000000000001001 [ b00000000000000000000000000001010 \ b00000000000000000000000000001001 ] b00000000000000000000000000001001 _ 0` b00000000000000000000000000001010 i b00000000000000000000000000001010 j b00000000000000000000000000000111 k b00000000000000000000000000001010 m b00000000000000000000000000001011 p b00000000000000000000000000001010 q b00000000000000000000000000001010 u b00000000000000000000000000101100 w b00000000000000000000000000100001 x b00000000000000000000000000001011 y b00000000000000000000000000001011 z b00000000000000000000000000001010 | b00000000000000000000000000001010 ~ b00000000000000000000000000001001 !! b00000000000000000000000000001010 $! b00000000000000000000000000001001 %! b1010 (! b00000000000000000000000000001010 *! b00000000000000000000000000000101 0! b00000000000000000000000000001010 1! b00000000000000000000000000001010 2! b00000000000000000000000000001010 3! b00000000000000000000000000001001 4! b00000000000000000000000000001001 6! b00000000000000000000000000001010 7! b00000000000000000000000000001010 8! b00000000000000000000000000001001 9! b00000000000000000000000000001001 ;! b00000000000000000000000000001010 ! b00000000000000000000000000001011 A! b00000000000000000000000000001010 B! verilator-5.044/test_regress/t/t_dpi_2exparg_bad.out0000644000542200017500000000343215125463617023171 0ustar mahmoudyfreeshell%Warning-WIDTHEXPAND: t/t_dpi_2exparg_bad.v:19:56: Operator NOT expects 64 bits on the LHS, but LHS's VARREF 'i' generates 32 bits. : ... note: In instance 't.b' 19 | task dpix_twice(input int i, output [63:0] o); o = ~i; endtask | ^ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. %Warning-WIDTHTRUNC: t/t_dpi_2exparg_bad.v:12:53: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS's NOT generates 32 bits. : ... note: In instance 't.a' 12 | task dpix_twice(input int i, output [2:0] o); o = ~i; endtask | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: t/t_dpi_2exparg_bad.v:19:9: Duplicate declaration of DPI function with different signature: 'dpix_twice' 19 | task dpix_twice(input int i, output [63:0] o); o = ~i; endtask | ^~~~~~~~~~ : ... New signature: void dpix_twice (int, svLogicVecVal* /* logic[63:0] */ ) t/t_dpi_2exparg_bad.v:12:9: ... Original signature: void dpix_twice (int, svLogicVecVal* /* logic[2:0] */ ) 12 | task dpix_twice(input int i, output [2:0] o); o = ~i; endtask | ^~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_queue_assignment.v0000644000542200017500000000267115125463617023175 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by PlanV GmbH. // SPDX-License-Identifier: CC0-1.0 module t_queue_assignment; typedef int T_QI[$]; T_QI jagged_array[$]; // int jagged_array[$][$]; initial begin jagged_array = '{ {1}, T_QI'{2,3,4}, {5,6} }; // jagged_array[0][0] = 1 -- jagged_array[0] is a queue of 1 int // jagged_array[1][0] = 2 -- jagged_array[1] is a queue of 3 ints // jagged_array[1][1] = 3 // jagged_array[1][2] = 4 // jagged_array[2][0] = 5 -- jagged_array[2] is a queue of 2 ints // jagged_array[2][1] = 6 jagged_array.push_back('{7}); jagged_array.push_back('{8, 9, 10}); jagged_array.push_front('{0, 1}); print_and_check(); $write("*-* All Finished *-*\n"); $finish; end task automatic print_and_check(); integer i, j; int expected_values[][] = '{ '{0, 1}, '{1}, '{2, 3, 4}, '{5, 6}, '{7}, '{8, 9, 10} }; for (i = 0; i < jagged_array.size(); i++) begin for (j = 0; j < jagged_array[i].size(); j++) begin // $display("jagged_array[%0d][%0d] = %0d", i, j, jagged_array[i][j]); if (jagged_array[i][j] !== expected_values[i][j]) begin $stop; end end end endtask endmodule verilator-5.044/test_regress/t/t_class_vparam.py0000755000542200017500000000073415125463617022460 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_trace_complex_structs_fst.py0000755000542200017500000000121415125463617025267 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_complex.v" test.compile(verilator_flags2=['--cc --trace-fst --trace-structs --no-trace-params']) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_past_funcs.v0000644000542200017500000001027215125463617021762 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Peter Monsson. // SPDX-License-Identifier: Unlicense module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; wire [31:0] in = cyc; Test test (/*AUTOINST*/ // Inputs .clk (clk), .in (in[31:0])); Test2 test2 (/*AUTOINST*/ // Inputs .clk (clk), .in (in[31:0])); Test3 test3 (/*AUTOINST*/ // Inputs .clk (clk), .in (in[31:0])); always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module Test (/*AUTOARG*/ // Inputs clk, in ); input clk; input [31:0] in; bit [31:0] dly0 = 0; bit [31:0] dly1 = 0; bit [31:0] dly2 = 0; // If called in an assertion, sequence, or property, the appropriate clocking event. // Otherwise, if called in a disable condition or a clock expression in an assertion, sequence, or prop, explicit. // Otherwise, if called in an action block of an assertion, the leading clock of the assertion is used. // Otherwise, if called in a procedure, the inferred clock // Otherwise, default clocking always @(posedge clk) begin dly0 <= in; dly1 <= dly0; dly2 <= dly1; // In clock expression $write("in=%0d, dly0=%0d, rose=%0d, past=%0d\n", in, dly0, $rose(dly0), $past(dly0)); if ($rose(dly0[4])) $stop; if ($fell(dly0[4])) $stop; if (!$stable(dly0[4])) $stop; if ($changed(dly0[4])) $stop; end assert property (@(posedge clk) $rose(dly0) || dly0%2==0 || dly2 < 3); assert property (@(posedge clk) $fell(dly1) || dly1%2==1 || dly2 < 3); assert property (@(posedge clk) !$stable(dly2) || dly2 < 3); assert property (@(posedge clk) $changed(dly2) || dly2 < 3); global clocking @(posedge clk); endclocking always @ ($global_clock) $display("gc in=%0d", in); // assert property (@(posedge clk) $rose(dly0, $global_clock) || dly0%2==0 || dly2 < 3); assert property (@(posedge clk) $fell(dly1, $global_clock) || dly1%2==1 || dly2 < 3); assert property (@(posedge clk) !$stable(dly2, $global_clock) || dly2 < 3); assert property (@(posedge clk) $changed(dly2, $global_clock) || dly2 < 3); // assert property (@(posedge clk) $rose_gclk(dly0) || dly0%2==0 || dly2 < 3); assert property (@(posedge clk) $fell_gclk(dly1) || dly1%2==1 || dly2 < 3); assert property (@(posedge clk) $past_gclk(dly1) == dly2 || dly2 < 3); assert property (@(posedge clk) !$stable_gclk(dly2) || dly2 < 3); assert property (@(posedge clk) $changed_gclk(dly2) || dly2 < 3); // global_clocking_future_functions are not supported yet: // $changing_gclk global_clocking_future_function // $falling_gclk global_clocking_future_function // $future_gclk global_clocking_future_function // $rising_gclk global_clocking_future_function // $steady_gclk global_clocking_future_function endmodule module Test2 (/*AUTOARG*/ // Inputs clk, in ); input clk; input [31:0] in; bit [31:0] dly0 = 0; bit [31:0] dly1 = 0; bit [31:0] dly2 = 0; always @(posedge clk) begin dly0 <= in; dly1 <= dly0; dly2 <= dly1; if ($rose(dly0[31:4])) $stop; if ($fell(dly1[31:4])) $stop; if (!$stable(dly2[31:4])) $stop; if ($changed(dly2[31:4])) $stop; end default clocking @(posedge clk); endclocking assert property ($rose(dly0[0]) || dly0%2==0 || dly2 < 3); assert property ($fell(dly1[0]) || dly1%2==1 || dly2 < 3); assert property ($stable(dly2[31:4]) || dly2 < 3); assert property (!$changed(dly2[31:4]) || dly2 < 3); endmodule module Test3 (/*AUTOARG*/ // Inputs clk, in ); input clk; input [31:0] in; // Check the named form of global clocking global clocking gck @(posedge clk); endclocking endmodule verilator-5.044/test_regress/t/t_case_66bits.py0000755000542200017500000000073415125463617022115 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_xml_primary_io.out0000644000542200017500000000620715125463617023214 0ustar mahmoudyfreeshell verilator-5.044/test_regress/t/t_interface_generic_modport_bad3.out0000755000542200017500000000065715125463617026261 0ustar mahmoudyfreeshell%Error: t/t_interface_generic_modport_bad3.v:18:11: Can't find definition of 'v' in dotted signal: 'a.v' : ... note: In instance 't.genericModule' 18 | if (a.v != 7) $stop; | ^ ... Known scopes under 'v': ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_process_rand.v0000644000542200017500000000236715125463617022305 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; process p; integer seed; string state; int a; int b; initial begin p = process::self(); // Test setting RNG state with state string state = p.get_randstate(); p.set_randstate(state); a = $random; p.set_randstate(state); b = $random; $display("a=%d, b=%d", a, b); if (a != b) $stop; // Test the same with $urandom state = p.get_randstate(); p.set_randstate(state); a = $urandom; p.set_randstate(state); b = $urandom; $display("a=%d, b=%d", a, b); if (a != b) $stop; // Test if the results repeat after the state is reset state = p.get_randstate(); for (int i = 0; i < 10; i++) $random; a = $random; // Now reset the state and take 11th result again p.set_randstate(state); for (int i = 0; i < 10; i++) $random; b = $random; $display("a=%d, b=%d", a, b); if (a != b) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_extend_c_class.py0000755000542200017500000000100115125463617022747 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(make_flags=["CPPFLAGS_ADD=-I" + test.t_dir]) test.execute() test.passes() verilator-5.044/test_regress/t/t_while_cond_is_stmt.py0000755000542200017500000000073415125463617023662 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_func_unit.py0000755000542200017500000000073415125463617021777 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_debug_trace.v0000644000542200017500000000056715125463617022067 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Dotted reference that uses another dotted reference // as the select expression // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs a ); input a; sub sub (); endmodule module sub; reg svar; endmodule verilator-5.044/test_regress/t/t_for_local.py0000755000542200017500000000073415125463617021745 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_dpi_open_oob_bad.py0000755000542200017500000000124115125463617023241 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(v_flags2=["t/t_dpi_open_oob_bad_c.cpp"], verilator_flags2=["-Wall -Wno-DECLFILENAME -unroll-count 1"]) test.execute( fails=False, # DPI warnings are not errors expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_disable_within_task_unsup.py0000755000542200017500000000077115125463617025247 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_nba_commit_queue.py0000755000542200017500000000127015125463617023315 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(verilator_flags2=["-unroll-count 1", "--stats"]) test.execute() test.file_grep(test.stats, r'NBA, variables using ValueQueueWhole scheme\s+(\d+)', 6) test.file_grep(test.stats, r'NBA, variables using ValueQueuePartial scheme\s+(\d+)', 3) test.passes() verilator-5.044/test_regress/t/t_pp_circdef_bad.py0000755000542200017500000000112715125463617022706 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True) # EOF result varies with Bison version, so can't use .out test.file_grep(test.compile_log_filename, r'define or other nested inclusion') test.passes() verilator-5.044/test_regress/t/t_nba_shared_flag_reuse.py0000755000542200017500000000077115125463617024270 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.044/test_regress/t/t_unpacked_slice.v0000644000542200017500000000361015125463617022564 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t; parameter int sliceddn[4:-3] = '{'h100, 'h101, 'h102, 'h103, 'h104, 'h105, 'h106, 'h107}; parameter int slicedup[-3:4] = '{'h100, 'h101, 'h102, 'h103, 'h104, 'h105, 'h106, 'h107}; int alldn[7:0]; int allup[0:7]; int twodn[1:0]; int twoup[0:1]; initial begin `checkh(sliceddn[4], 'h100); alldn[7:0] = sliceddn[4:-3]; `checkh(alldn[7], 'h100); alldn[7:0] = sliceddn[-3 +: 8]; // down: lsb/lo +: width `checkh(alldn[7], 'h100); alldn[7:0] = sliceddn[4 -: 8]; // down: msb/hi -: width `checkh(alldn[7], 'h100); twodn[1:0] = sliceddn[3:2]; `checkh(twodn[1], 'h101); `checkh(twodn[0], 'h102); twodn[1:0] = sliceddn[1 +: 2]; `checkh(twodn[1], 'h102); `checkh(twodn[0], 'h103); twodn[1:0] = sliceddn[1 -: 2]; `checkh(twodn[1], 'h103); `checkh(twodn[0], 'h104); `checkh(slicedup[4], 'h107); allup[0:7] = slicedup[-3:4]; `checkh(alldn[7], 'h100); allup[0:7] = slicedup[-3 +: 8]; // up: msb/lo +: width `checkh(alldn[7], 'h100); allup[0:7] = slicedup[4 -: 8]; // up: lsb/hi -: width `checkh(alldn[7], 'h100); twoup[0:1] = slicedup[2:3]; `checkh(twoup[1], 'h106); `checkh(twoup[0], 'h105); twoup[0:1] = slicedup[1 +: 2]; `checkh(twoup[1], 'h105); `checkh(twoup[0], 'h104); twoup[0:1] = slicedup[1 -: 2]; `checkh(twoup[1], 'h104); `checkh(twoup[0], 'h103); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_timing_always.py0000755000542200017500000000077115125463617022655 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_randomize_with_constraint.out0000644000542200017500000000073715125463617025453 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_randomize_with_constraint.v:13:26: Unsupported: 'randomize with (...) {...}' 13 | return obj.randomize() with ( | ^~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_randomize_with_constraint.v:21:26: Unsupported: 'randomize with (...) {...}' 21 | return obj.randomize() with ( | ^~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_vpi_stop_bad.v0000644000542200017500000000105215125463617022262 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; import "DPI-C" function void dpii_test(); initial begin dpii_test(); $display("Should have stopped above"); //$write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_param_store_bad.py0000755000542200017500000000076615125463617023134 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_property_fail_1.py0000755000542200017500000000126015125463617023077 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_property.v" test.compile(v_flags2=['+define+FAIL_ASSERT_1'], verilator_flags2=['--assert --cc']) test.execute() # We expect to get a message when this assert fires: test.file_grep(test.run_log_filename, r'cyc != 3') test.passes() verilator-5.044/test_regress/t/t_lint_multiple_msgs.v0000644000542200017500000000065615125463617023534 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input [3:1] i3, input [4:1] i4, output [3:1] o3, output [4:1] o4 ); // verilator lint_off WIDTHTRUNC,WIDTHEXPAND // after slashes ignored assign o3 = i4; assign o4 = i3; endmodule verilator-5.044/test_regress/t/t_json_only_flat.py0000755000542200017500000000144515125463617023025 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_json_only_first.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums', '--flatten'], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.files_identical(out_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_inst_paren_bad.out0000644000542200017500000000152415125463617023127 0ustar mahmoudyfreeshell%Warning-MULTITOP: t/t_inst_paren_bad.v:10:8: Multiple top level modules : ... Suggest see manual; fix the duplicates, or use --top-module to select top. ... For warning description see https://verilator.org/warn/MULTITOP?v=latest ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message. : ... Top module 'sub' 7 | module sub; | ^~~ : ... Top module 't' 10 | module t; | ^ %Error: t/t_inst_paren_bad.v:11:4: Can't find typedef/interface: 'sub' 11 | sub sub_inst; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_class_extends_arg.v0000644000542200017500000000177415125463617023314 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); class Base; int m_s = 2; function new(int def = 3); m_s = def; endfunction endclass class Cls5Exp extends Base(5); int m_a = 11; function new(int def = 42); // Explicit new m_a = def; endfunction endclass class Cls5Imp extends Base(5); int m_a = 12; // Implicit new endclass module t (); Cls5Exp ce; Cls5Imp ci; initial begin ce = new(37); `checkh(ce.m_s, 5); `checkh(ce.m_a, 37); ci = new; `checkh(ci.m_s, 5); `checkh(ci.m_a, 12); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_inst_misarray2_bad.out0000644000542200017500000000067515125463617023741 0ustar mahmoudyfreeshell%Error: t/t_inst_misarray2_bad.v:10:17: Illegal input port connection 'i_data', mismatch between port which is not an array, and expression which is an array. (IEEE 1800-2023 7.6) : ... note: In instance 't' 10 | .i_data(fft_oQ[6:0]) | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_assert_synth_full_vlt.py0000755000542200017500000000134115125463617024435 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_assert_synth.v" test.compile(v_flags2=['+define+FAILING_FULL', "t/t_assert_synth_full.vlt"], verilator_flags2=['--assert'], nc_flags2=['+assert']) test.execute(check_finished=False, fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_func_plog.v0000644000542200017500000000525415125463617021575 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; reg rst_n; // Take CRC data and apply to testblock inputs /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [2:0] pos1; // From test of Test.v wire [2:0] pos2; // From test of Test.v // End of automatics Test test ( // Outputs .pos1 (pos1[2:0]), .pos2 (pos2[2:0]), /*AUTOINST*/ // Inputs .clk (clk), .rst_n (rst_n)); // Aggregate outputs into a single result vector wire [63:0] result = {61'h0, pos1}; // What checksum will we end up with `define EXPECTED_SUM 64'h039ea4d039c2e70b // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; rst_n <= ~1'b0; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; rst_n <= ~1'b1; end else if (cyc<10) begin sum <= 64'h0; rst_n <= ~1'b1; end else if (cyc<90) begin if (pos1 !== pos2) $stop; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test #(parameter SAMPLE_WIDTH = 5 ) ( `ifdef verilator // Some simulators don't support clog2 output reg [$clog2(SAMPLE_WIDTH)-1:0] pos1, `else output reg [log2(SAMPLE_WIDTH-1)-1:0] pos1, `endif output reg [log2(SAMPLE_WIDTH-1)-1:0] pos2, // System input clk, input rst_n ); function integer log2(input integer arg); begin for(log2=0; arg>0; log2=log2+1) arg = (arg >> 1); end endfunction always @ (posedge clk or negedge rst_n) if (!rst_n) begin pos1 <= 0; pos2 <= 0; end else begin pos1 <= pos1 + 1; pos2 <= pos2 + 1; end endmodule verilator-5.044/test_regress/t/t_lint_edge_real_bad.py0000755000542200017500000000076315125463617023552 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_timescale_parse_bad.out0000644000542200017500000000231615125463617024125 0ustar mahmoudyfreeshell%Error: t/t_timescale_parse_bad.v:8:1: `timescale timeunit '1ps' must be greater than or equal to timeprecision '1ns' 8 | `timescale 1ps/1ns | ^~~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_timescale_parse_bad.v:11:1: `timescale timeunit syntax error: 'frump' 11 | `timescale frump | ^~~~~~~~~~~~~~~~ %Error: t/t_timescale_parse_bad.v:12:1: `timescale timeunit syntax error: '1xs' 12 | `timescale 1xs | ^~~~~~~~~~~~~~ %Error: t/t_timescale_parse_bad.v:13:1: `timescale timeunit syntax error: '2ps' 13 | `timescale 2ps | ^~~~~~~~~~~~~~ %Error: t/t_timescale_parse_bad.v:14:1: `timescale timeprecision syntax error: 'frump' 14 | `timescale 1ns / frump | ^~~~~~~~~~~~~~~~~~~~~~ %Error: t/t_timescale_parse_bad.v:15:1: `timescale syntax error: ' 1ns / 1ps /extra' 15 | `timescale 1ns / 1ps /extra | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error: t/t_timescale_parse_bad.v:18:12: timeunit illegal value 18 | timeunit 2ps; | ^~~ %Error: t/t_timescale_parse_bad.v:19:17: timeprecision illegal value 19 | timeprecision 2ps; | ^~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_force_initial.v0000644000542200017500000000153015125463617022421 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) // verilog_format: on module t; reg [1:0] a = 0; reg [1:0] b = 2; initial begin force b = a; `checkh(a, 0); `checkh(b, 0); end initial begin #1; `checkh(b, 0); a = 1; #1; `checkh(a, 1); `checkh(b, 1); a = 3; #1; `checkh(a, 3); `checkh(b, 3); release b; `checkh(a, 3); `checkh(b, 3); b = 0; #1; `checkh(b, 0); #1 $finish; end endmodule verilator-5.044/test_regress/t/t_class_member_sens.v0000644000542200017500000000114315125463617023276 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; class EventClass; event e; endclass EventClass ec = new; int cyc = 0; always @ec.e ec = new; always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 1) ->ec.e; else if (cyc == 2) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.044/test_regress/t/t_flag_wpedantic_bad.py0000755000542200017500000000102415125463617023553 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["-Wpedantic"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_lint_iface_array_topmodule1.v0000644000542200017500000000177715125463617025273 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Josh Redford. // SPDX-License-Identifier: CC0-1.0 interface my_if; logic valid; logic [7:0] data ; modport slave_mp ( input valid, input data ); modport master_mp ( output valid, output data ); endinterface module t ( input wire clk, my_if.slave_mp in_if [2], my_if.master_mp out_if [2] ); my_if my_i [2] (); always @(posedge clk) begin my_i[0].valid <= in_if[0].valid; my_i[0].data <= in_if[0].data; my_i[1].valid <= in_if[1].valid; my_i[1].data <= in_if[1].data; end assign out_if[0].valid = my_i[0].valid; assign out_if[0].data = my_i[0].data; assign out_if[1].valid = my_i[1].valid; assign out_if[1].data = my_i[1].data; endmodule verilator-5.044/test_regress/t/t_wire_behp1800_bad.out0000644000542200017500000000153315125463617023242 0ustar mahmoudyfreeshell%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:23:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'w' : ... note: In instance 't' 23 | w = '0; | ^ ... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest %Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:24:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'o' : ... note: In instance 't' 24 | o = '0; | ^ %Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:25:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'oa' : ... note: In instance 't' 25 | oa = '0; | ^~ %Error: Exiting due to verilator-5.044/test_regress/t/t_mod_topmodule.v0000644000542200017500000000124415125463617022463 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This test verifies that a top-module can be specified which // is instantiated beneath another module in the compiled source // code. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Dan Petrisko // SPDX-License-Identifier: CC0-1.0 module top(/*AUTOARG*/ // Inputs clk ); input clk; always_ff @(posedge clk) begin $write("*-* All Finished *-*\n"); $finish(); end endmodule module faketop(/*AUTOARG*/ ); top top(); // Stop immediately if this module is instantiated initial begin $stop(); end endmodule verilator-5.044/test_regress/t/t_param_circ_bad.py0000755000542200017500000000076615125463617022720 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_dfg_true_cycle_bad.v0000644000542200017500000000060515125463617023400 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 `default_nettype none module t ( output wire [9:0] o ); assign o[1:0] = o[9:8]; assign o[3:2] = o[1:0]; assign o[7:4] = 4'(o[3:2]); assign o[9:8] = o[5:4]; endmodule verilator-5.044/test_regress/t/t_inst_tree.v0000644000542200017500000000403215125463617021606 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg printclk; ps ps (printclk); reg [7:0] a; wire [7:0] z; l1 u (~a,z); always @ (posedge clk) begin printclk <= 0; if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin printclk <= 1'b1; end if (cyc==2) begin a <= 8'b1; end if (cyc==3) begin if (z !== 8'hf8) $stop; //if (u.u1.u1.u1.u0.PARAM !== 1) $stop; //if (u.u1.u1.u1.u1.PARAM !== 2) $stop; //if (u.u0.u0.u0.u0.z !== 8'hfe) $stop; //if (u.u0.u0.u0.u1.z !== 8'hff) $stop; //if (u.u1.u1.u1.u0.z !== 8'h00) $stop; //if (u.u1.u1.u1.u1.z !== 8'h01) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule module ps (input printclk); // Check that %m stays correct across inlines always @ (posedge printclk) $write("[%0t] %m: Clocked\n", $time); endmodule module l1 (input [7:0] a, output [7:0] z); wire [7:0] z0; wire [7:0] z1; assign z = z0+z1; l2 u0 (a, z0); l2 u1 (a, z1); endmodule module l2 (input [7:0] a, output [7:0] z); wire [7:0] z0; wire [7:0] z1; assign z = z0+z1; wire [7:0] a1 = a+8'd1; l3 u0 (a, z0); l3 u1 (a1, z1); endmodule module l3 (input [7:0] a, output [7:0] z); wire [7:0] z0; wire [7:0] z1; assign z = z0+z1; wire [7:0] a1 = a+8'd1; l4 u0 (a, z0); l4 u1 (a1, z1); endmodule module l4 (input [7:0] a, output [7:0] z); wire [7:0] z0; wire [7:0] z1; assign z = z0+z1; wire [7:0] a1 = a+8'd1; l5 #(1) u0 (a, z0); l5 #(2) u1 (a1, z1); endmodule module l5 (input [7:0] a, output [7:0] z); parameter PARAM = 5; wire [7:0] z0; wire [7:0] z1; assign z = a; endmodule verilator-5.044/test_regress/t/t_past_unsup.out0000644000542200017500000000115315125463617022356 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_past_unsup.v:16:11: Unsupported: $past expr2 and/or clock arguments 16 | if ($past(d, 1, 1)) $stop; | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_past_unsup.v:17:11: Unsupported: $past expr2 and/or clock arguments 17 | if ($past(d, 1, 1, )) $stop; | ^~~~~ %Error-UNSUPPORTED: t/t_past_unsup.v:18:11: Unsupported: $past expr2 and/or clock arguments 18 | if ($past(d, 1, 1, @(posedge clk))) $stop; | ^~~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_randomize_member_select.v0000644000542200017500000000212715125463617024473 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class B; rand int insideB; constraint i { insideB inside {[0:10]}; }; endclass class A; rand logic[31:0] rdata; rand int delay; int i = 97; rand B b; function new(); b = new; endfunction constraint delay_bounds { delay inside {[0:2]}; } endclass module t; A a; int i; int delay; logic[31:0] rdata; int b; initial begin a = new; i = 7; repeat (120) begin a.b.insideB = 3; a.delay = 1; a.rdata = 3; if (a.randomize() with {if (a.delay == 1) a.rdata == i;} == 0) $stop; if (a.b.randomize() with {a.b.insideB < 3;} == 0) $stop; if (a.delay == 1 && a.rdata != 97) $stop; if (a.b.insideB >= 3) $stop; if (a.randomize() with {if (a.delay == 1) a.rdata == local::i;} == 0) $stop; if (a.delay == 1 && a.rdata != 7) $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_trace_off_sc.py0000755000542200017500000000121515125463617022415 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_ena.v" test.compile(verilator_flags2=['-notrace -sc']) test.execute() if test.vlt_all: if os.path.exists(test.trace_filename): test.error("Tracing should be off") test.passes() verilator-5.044/test_regress/t/t_hier_block_cmake.py0000755000542200017500000000354315125463617023247 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap import os # If a test fails, broken .cmake may disturb the next run test.clean_objs() test.priority(30) test.scenarios('simulator') test.top_filename = "t/t_hier_block.v" threads = ('-DTEST_THREADS=6' if test.vltmt else '-DTEST_THREADS=1') if not test.have_cmake: test.skip("Test requires CMake; ignore error since not available or version too old") test.run(logfile=test.obj_dir + "/cmake.log", cmd=[ 'cd "' + test.obj_dir + '" && cmake ' + test.t_dir + '/t_hier_block_cmake', "-DCMAKE_PREFIX_PATH=" + os.environ["VERILATOR_ROOT"], threads ]) test.run(logfile=test.obj_dir + "/build.log", cmd=[ 'cd "' + test.obj_dir + '" && cmake --build', '.', ('-v' if test.verbose else ''), '-j ' + str(test.max_procs), '--', "CXX_FLAGS=" + str(threads) ]) test.run(logfile=test.obj_dir + "/run.log", cmd=['cd "' + test.obj_dir + '" && ./t_hier_block_cmake', '.']) target_dir = test.obj_dir + '/CMakeFiles/t_hier_block_cmake.dir/Vt_hier_block.dir/' test.file_grep(target_dir + 'Vsub0/sub0.sv', r'^module\s+(\S+)\s+', "sub0") test.file_grep(target_dir + 'Vsub1/sub1.sv', r'^module\s+(\S+)\s+', "sub1") test.file_grep(target_dir + 'Vsub2/sub2.sv', r'^module\s+(\S+)\s+', "sub2") test.file_grep(target_dir + 'Vt_hier_block__stats.txt', r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14) test.file_grep(test.obj_dir + '/run.log', r'MACRO:(\S+) is defined', "cplusplus") test.passes() verilator-5.044/test_regress/t/t_math_shift_huge.py0000755000542200017500000000071415125463617023141 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.044/test_regress/t/t_slice_struct_array_modport.v0000644000542200017500000000065115125463617025262 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Varun Koyyalagunta. // SPDX-License-Identifier: CC0-1.0 typedef struct packed { logic p; } s_data; module m1 (output s_data data[1:0]); assign data[0].p = 0; assign data[1].p = 0; endmodule module top (output s_data data[2:0]); m1 m1_inst (.data(data[1:0])); endmodule verilator-5.044/test_regress/t/t_mem_multidim.py0000755000542200017500000000073415125463617022467 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_past_unsup.py0000755000542200017500000000076315125463617022210 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_constraint_unsup.out0000644000542200017500000000045415125463617023576 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_constraint_unsup.v:9:22: Unsupported expression inside constraint 9 | constraint cons { $onehot(m_one) == 1; } | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.044/test_regress/t/t_cover_expr_max.py0000755000542200017500000000200615125463617023020 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap from pathlib import Path test.scenarios('simulator') test.top_filename = "t/t_cover_expr.v" test.compile(verilator_flags2=['--cc', '--coverage-expr', '--coverage-expr-max', '128']) test.execute() # Read the input .v file and do any CHECK_COVER requests test.inline_checks() test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--annotate-points", "--annotate", test.obj_dir + "/annotated", test.obj_dir + "/coverage.dat", ], verilator_run=True) top = Path(test.top_filename) test.files_identical(test.obj_dir + f"/annotated/{top.name}", test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_vpi_hierarchy_clear.cpp0000644000542200017500000000567315125463617024145 0ustar mahmoudyfreeshell// ====================================================================== // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty. // SPDX-License-Identifier: CC0-1.0 // ====================================================================== // DESCRIPTION: Scope hierarchy map clearing upon VerilatedModel destruction // // VerilatedImp::s() is a VerilatedImpData singleton that contains an m_hierMap // whose keys are pointers to VerilatedScope objects. Because it is a // singleton, it is not automatically destroyed together with the // VerilatedModel, so this test checks that the VerilatedSyms destructor that is // invoked upon the VerilatedModel's destruction clears the keys from the map. // Workaround to be able to include verilated_imp.h, needed to directly test the hierarchy map #define VERILATOR_VERILATED_CPP_ #include "verilated_imp.h" #include #include "TestVpi.h" #include "Vt_vpi_hierarchy_clear.h" #include "Vt_vpi_hierarchy_clear__Syms.h" #include int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; contextp->commandArgs(argc, argv); // Vt_vpi_hierarchy_clear::vlSymsp is private, so create a dummy syms object just to be able to // construct the VerilatedScope objects std::unique_ptr dummySymsp = std::make_unique(contextp.get(), "dummySymsObject", nullptr); std::unique_ptr additionalScope = std::make_unique(dummySymsp.get(), "t.additional", "additional", "Additional", -12, VerilatedScope::SCOPE_MODULE); { // Construct and destroy const std::unique_ptr topp{ new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; // Insert additional scope into map for the first topp VerilatedImp::hierarchyAdd(additionalScope.get(), nullptr); const bool scopeFound = (VerilatedImp::hierarchyMap()->find(additionalScope.get()) != VerilatedImp::hierarchyMap()->end()); CHECK_RESULT_NZ(scopeFound); // NOLINT(concurrency-mt-unsafe) } // Test second construction const std::unique_ptr topp{new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; // Do not insert additionalScope this time, so it should not be present in the map any more const bool scopeFound = (VerilatedImp::hierarchyMap()->find(additionalScope.get()) != VerilatedImp::hierarchyMap()->end()); CHECK_RESULT_Z(scopeFound); // NOLINT(concurrency-mt-unsafe) return 0; } verilator-5.044/test_regress/t/t_var_local.v0000644000542200017500000000307215125463617021557 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class cls; static task automatic tsk1; integer task_assign = 1; if (task_assign != 1) $stop; task_assign = 2; if (task_assign != 2) $stop; endtask static task tsk2; integer task_assign = 1; if (task_assign != 1) $stop; task_assign = 2; if (task_assign != 2) $stop; endtask endclass module t; integer top; integer top_assign=1; task automatic tsk; integer task_assign = 1; if (task_assign != 1) $stop; task_assign = 2; if (task_assign != 2) $stop; endtask initial begin begin : a integer lower; integer lower_assign=1; lower = 1; top = 1; if (lower != 1) $stop; if (lower_assign != 1) $stop; begin : aa integer lev2; lev2 = 1; lower = 2; lower_assign = 2; top = 2; end if (lower != 2) $stop; if (lower_assign != 2) $stop; end begin : b integer lower; lower = 1; top = 2; begin : empty begin : empty end end end // Repeat task calls to ensure we reinit the initial value tsk; tsk; cls::tsk1(); cls::tsk1(); cls::tsk2(); cls::tsk2(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_math_shift_extend.v0000644000542200017500000000261215125463617023311 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; logic in1 = 1; logic [1:0] in2 = 2'b11; logic [31:0] out; logic [7:0] ones = 8'b11111111; logic [9:0] ones10 = 10'b1111111111; typedef logic [7:0] data_t; typedef logic [9:0] ten_t; ten_t out10; // verilator lint_off WIDTH initial begin in1 = 1; in2 = 0; out = data_t'(in1 << in2); if (out != 8'b1) $stop; in2 = 1; out = data_t'(in1 << in2); if (out != 8'b10) $stop; in2 = 2; out = data_t'(in1 << in2); if (out != 8'b100) $stop; in2 = 3; out = data_t'(in1 << in2); if (out != 8'b1000) $stop; // Check upper bits get cleared when cast in2 = 3; out = data_t'(ones << in2); if (out != 8'b11111000) $stop; in2 = 3; out = data_t'(ones10 << in2); if (out != 8'b11111000) $stop; // bug2597 out = data_t'(10'h208 >> 2); if (out != 8'h82) $stop; out = data_t'(10'h208 >> 2); if (out != 8'h82) $stop; out = data_t'('h208 >> 2); if (out != 8'h82) $stop; out10 = ten_t'('h404 >> 2); if (out10 != 10'h101) $stop; $write("*-* All Finished *-*\n"); $finish(); end endmodule verilator-5.044/test_regress/t/t_select_bad_msb.v0000644000542200017500000000067215125463617022546 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; reg [43:0] mi; reg [3:0] sel2; reg [0:22] backwd; always @ (posedge clk) begin mi = 44'h123; sel2 = mi[1:4]; $write ("Bad select %x\n", sel2); end endmodule verilator-5.044/test_regress/t/t_param_module.v0000644000542200017500000000241315125463617022260 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This test case is used for testing a modeule parameterized with a typed // localparam. // // We find Verilator appears to mis-evaluate the parameter WIDTH as -16 when // used in the test module to set the value of MSB. A number of warnings and // errors follow, starting with: // // %Warning-ASCRANGE: t/t_param_module.v:42: Ascending bit range vector: MSB // < LSB of bit range: -17:0 // // This file ONLY is placed into the Public Domain, for any use, without // warranty, 2013 by Jie Xu. // SPDX-License-Identifier: CC0-1.0 // bug606 module t (/*AUTOARG*/ // Inputs clk ); input clk; localparam logic[4:0] WID = 16; //localparam WID = 16; // No problem if defined like this wire [15:0] b33; test #(WID) i_test_33(.clk (clk), .b (b33)); endmodule module test (/*AUTOARG*/ //Inputs clk, // Outputs b ); parameter WIDTH = 10; localparam MSB = WIDTH - 1; input clk; output wire [MSB:0] b; wire [MSB:0] a; assign b = {~a[MSB-1:0], clk}; initial begin if ($bits(WIDTH)!=5) $stop; // Comes from the parent! if ($bits(MSB)!=32) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_unconnected_bad.out0000644000542200017500000000077215125463617023276 0ustar mahmoudyfreeshell%Error: t/t_unconnected_bad.v:7:1: Bad `unconnected_drive syntax 7 | `unconnected_drive | ^~~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_unconnected_bad.v:9:1: Bad `unconnected_drive syntax 9 | `unconnected_drive pull2 | ^~~~~~~~~~~~~~~~~~ %Error: t/t_unconnected_bad.v:9:20: syntax error, unexpected IDENTIFIER 9 | `unconnected_drive pull2 | ^~~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_assign_automatic_bad.py0000755000542200017500000000076615125463617024152 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_debug_width.out0000644000542200017500000000053015125463617022440 0ustar mahmoudyfreeshell%Error: Internal Error: t/t_opt_const.v:12:8: ../V3Ast.cpp:#: widthMismatch detected 'lhsp()->widthMin() != rhsp()->widthMin()' @ ../V3AstNodes.cpp:#OUT:(G/wu32/1) LHS:(G/w32) RHS:(G/wu32/1) 12 | module t( | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. verilator-5.044/test_regress/t/t_flag_fi.py0000755000542200017500000000114215125463617021366 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(make_top_shell=False, make_main=False, v_flags2=["-FI", test.t_dir + "/t_flag_fi_h.h", "--exe", test.pli_filename]) test.execute() test.passes() verilator-5.044/test_regress/t/t_unopt_array.v0000644000542200017500000000453515125463617022165 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[31:0]), // Inputs .clk (clk), .in (in[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h458c2de282e30f8b if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs clk, in ); input clk; input [31:0] in; output wire [31:0] out; `ifdef USE_TYPEDEF typedef reg [3:0][31:0] stage_t [3:0]; stage_t stage; `else reg [3:0][31:0] stage [3:0]; `endif genvar g; generate for (g=0; g<4; g++) begin always_comb begin if (g==0) stage[g] = {4{in}}; else stage[g] = {4{stage[g-1][0][30:0],1'b1}}; end end endgenerate assign out = stage[3][0]; endmodule verilator-5.044/test_regress/t/t_disable.v0000644000542200017500000000101315125463617021211 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin fork : foo disable foo; #1 $stop; join_none #2; begin : forked fork disable forked; #1 $stop; join_none end #2; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_lint_const_func_dpi_bad.v0000644000542200017500000000046615125463617024452 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Donald Owen. // SPDX-License-Identifier: CC0-1.0 module t (); import "DPI-C" function int dpiFunc(); localparam PARAM = dpiFunc(); endmodule verilator-5.044/test_regress/t/t_randomize_inline_var_ctl_bad.v0000644000542200017500000000104015125463617025454 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Foo; int x; function void test; int y; void'(randomize(y)); endfunction endclass class Bar; int y; endclass module t; initial begin Foo foo = new; Foo qux = new; Bar bar = new; int x; void'(foo.randomize(x, foo.x, null, qux.x, bar.y, 0 + 1, x ** 2)); end endmodule verilator-5.044/test_regress/t/t_std_randomize_no_args.py0000755000542200017500000000071115125463617024352 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.lint() test.passes() verilator-5.044/test_regress/t/t_gen_local.py0000755000542200017500000000073415125463617021730 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_lint_didnotconverge_nodbg_bad.py0000755000542200017500000000152115125463617026017 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_lint_didnotconverge_bad.v" if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") test.compile(make_flags=['CPPFLAGS_ADD=-UVL_DEBUG']) test.execute(fails=True, expect_filename=test.golden_filename) test.extract(in_filename=test.golden_filename, out_filename=test.root + "/docs/gen/ex_DIDNOTCONVERGE_nodbg_msg.rst", lines="1") test.passes() verilator-5.044/test_regress/t/t_program.v0000644000542200017500000000047315125463617021266 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 program t; initial begin $write("*-* All Finished *-*\n"); $finish; end endprogram verilator-5.044/test_regress/t/t_lint_procassinit_bad.py0000755000542200017500000000176415125463617024203 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=['-Wall -Wno-DECLFILENAME'], fails=True, expect_filename=test.golden_filename) test.extract(in_filename=test.top_filename, out_filename=test.root + "/docs/gen/ex_PROCASSINIT_faulty.rst", lines="26-32") test.extract(in_filename=test.top_filename, out_filename=test.root + "/docs/gen/ex_PROCASSINIT_fixed.rst", lines="36-45") test.extract(in_filename=test.golden_filename, out_filename=test.root + "/docs/gen/ex_PROCASSINIT_msg.rst", lines="1-9") test.passes() verilator-5.044/test_regress/t/t_math_clog2.py0000755000542200017500000000073415125463617022024 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_vlt_warn_range_bad.v0000644000542200017500000000223015125463617023426 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifdef verilator `verilator_config lint_off -rule DECLFILENAME // Test overlapping ranges work correctly lint_off -rule UNUSED -file "*/t_*" -lines 21-23 lint_off -rule UNUSED -file "*/t_*" -lines 20-22 // Intentional overlap with above lint_off -rule UNUSED -file "*/t_*" -lines 25-99 lint_on -rule UNUSED -file "*/t_*" -lines 26 `verilog `endif module t; reg unuse_warn_var_line20; // Unused warning - must be line 20 reg unuse_warn2_var_line21; // Unused warning - must be line 21 reg unuse_warn3_var_line22; // Unused warning - must be line 22 reg unuse_warn4_var_line23; // Unused warning - must be line 23 reg unuse_warn5_var_line24; // Unused warning - must be line 24 (not suppressed) reg unuse_warn5_var_line25; // Unused warning - must be line 25 reg unuse_warn5_var_line26; // Unused warning - must be line 26 (turned on) reg unuse_warn5_var_line27; // Unused warning - must be line 27 endmodule verilator-5.044/test_regress/t/t_select_bound3.v0000644000542200017500000000137715125463617022354 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2025 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 class cls; int m_field; endclass module t(); cls inst[2]; initial begin // Loop (even just 1 iteration) is needed to reproduce the error for (int i = 0; i < 2; ++i) begin inst[i] = new(); inst[i].m_field = i; end for (int i = 0; i < 2; ++i) begin if (inst[i].m_field != i) $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_inst_mism.py0000755000542200017500000000073415125463617022007 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_flag_compiler_bad.py0000755000542200017500000000106015125463617023407 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--compiler bad_one"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_opt_assemble_cellarray.py0000755000542200017500000000125015125463617024512 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["--stats -fno-dfg"]) test.execute() if test.vlt_all: test.file_grep(test.stats, r'Optimizations, Gate assign merged\s+(\d+)', 28) test.file_grep(test.stats, r'Optimizations, Concat merges\s+(\d+)', 42) test.passes() verilator-5.044/test_regress/t/t_for_assign.py0000755000542200017500000000073415125463617022137 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_vlt_warn_one_on_bad.v0000644000542200017500000000145615125463617023620 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifdef verilator `verilator_config // Issue #4185 lint_off lint_on -rule UNUSEDPARAM `verilog `endif module t; reg unuse_warn_var_line20; // Unused warning - must be line 20 reg unuse_warn2_var_line21; // Unused warning - must be line 21 reg unuse_warn3_var_line22; // Unused warning - must be line 22 reg unuse_warn4_var_line23; // Unused warning - must be line 23 localparam unuse_warn5_var_line24 = 0; // Unused warning - must be line 24 (not suppressed) localparam unuse_warn5_var_line25 = 0; // Unused warning - must be line 25 (not suppressed) endmodule verilator-5.044/test_regress/t/t_clocker.py0000755000542200017500000000107315125463617021424 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--trace-vcd"]) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_interface_wrong_bad.py0000755000542200017500000000076615125463617023774 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_opt_localize_max_size.py0000755000542200017500000000116715125463617024371 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--stats"]) test.execute() # Value must differ from that in t_opt_localize_max_size.py test.file_grep(test.stats, r'Optimizations, Vars localized\s+(\d+)', 1) test.passes() verilator-5.044/test_regress/t/t_dpi_if_cond.py0000755000542200017500000000077615125463617022250 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["t/t_dpi_if_cond_c.cpp"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_fork_func2_bad.py0000755000542200017500000000076615125463617022656 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_trace_scope_vlt.py0000755000542200017500000000116515125463617023160 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_trace_scope_vlt.v" test.compile(v_flags2=["--trace-vcd t/t_trace_scope_vlt.vlt"]) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_pipe_exit_bad_pf.pf0000755000542200017500000000101215125463617023231 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # mypy: disallow-untyped-defs # pylint: disable=C0114 # # DESCRIPTION: Verilator: Verilog Test example --pipe-filter script # # Copyright 2010 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import sys sys.exit("%Error: t_pipe_exit_bad_pf.pf: Intentional bad exit status...") verilator-5.044/test_regress/t/t_tri_select_eqcase.py0000755000542200017500000000073415125463617023463 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_flag_future_bad.py0000755000542200017500000000103315125463617023107 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_flag_future.v" test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_dfg_3679.py0000755000542200017500000000073415125463617021235 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_struct_genfor.py0000755000542200017500000000070615125463617022670 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.044/test_regress/t/t_dfg_3679.v0000644000542200017500000000176215125463617021051 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; reg [31:0] dly0; // DFG can fold this into 'dly3 = dly1 = dly0 + 1' and 'dly2 = dly0 + 2', // but the 'dly0 + 1' term having multiple sinks needs to considered. wire [31:0] dly1 = dly0 + 32'h1; wire [31:0] dly2 = dly1 + 32'h1; wire [31:0] dly3 = dly0 + 32'h1; always @ (posedge clk) begin $display("[%0t] dly0=%h dly1=%h dly2=%h dly3=%h", $time, dly0, dly1, dly2, dly3); cyc <= cyc + 1; if (cyc == 1) begin dly0 <= 32'h55; end else if (cyc == 3) begin if (dly1 !== 32'h56) $stop; if (dly2 !== 32'h57) $stop; if (dly3 !== 32'h56) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.044/test_regress/t/t_sv_bus_mux_demux/0000755000542200017500000000000015125463617023020 5ustar mahmoudyfreeshellverilator-5.044/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv0000644000542200017500000000447515125463617030202 0ustar mahmoudyfreeshell//////////////////////////////////////////////////////////////////////////////// // // // This file is placed into the Public Domain, for any use, without warranty. // // 2012 by Iztok Jeras // // SPDX-License-Identifier: CC0-1.0 // // // //////////////////////////////////////////////////////////////////////////////// import package_bus::*; import package_str::*; module sv_bus_mux_demux_demux ( // system signals input logic clk, // clock input logic rst, // reset // output stream input logic str_vld, // valid (chip select) input logic [7:0] str_bus, // byte data bus output logic str_rdy, // ready (acknowledge) // input bus output logic bus_vld, // valid (chip select) output logic [31:0] bus_adr, // address output logic [31:0] bus_dat, // data input logic bus_rdy // ready (acknowledge) ); logic bus_trn; // bus data transfer logic str_trn; // stream data transfer logic [2:0] pkt_cnt; // packet byte counter logic pkt_end; // packet byte counter end t_str pkt_str; // transfer packet as a structure t_bus pkt_bus; // transfer packet as an array // stream data transfer assign str_trn = str_vld & str_rdy; // ready if pipe is empty or output is ready assign str_rdy = ~bus_vld | bus_rdy; // packet byte counter always @ (posedge clk, posedge rst) if (rst) pkt_cnt <= 3'd0; else if (str_trn) pkt_cnt <= pkt_cnt + 3'd1; // packet byte counter end assign pkt_end = (&pkt_cnt); always @ (posedge clk) if (str_trn) pkt_str [pkt_cnt] <= str_bus; // the input packed array is mapped onto the output structure assign pkt_bus = pkt_str; // the output structure is mapped onto address/data outputs assign bus_adr = pkt_bus.adr; assign bus_dat = pkt_bus.dat; // output valid is set on the last input packed byte // or cleared by each output transfer always @ (posedge clk, posedge rst) if (rst) bus_vld <= 1'b0; else bus_vld <= str_trn & pkt_end | bus_vld & ~bus_rdy; // bus data transfer assign bus_trn = bus_vld & bus_rdy; endmodule : sv_bus_mux_demux_demux verilator-5.044/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv0000644000542200017500000000660315125463617030024 0ustar mahmoudyfreeshell//////////////////////////////////////////////////////////////////////////////// // // // This file is placed into the Public Domain, for any use, without warranty. // // 2012 by Iztok Jeras // // SPDX-License-Identifier: CC0-1.0 // // // //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // // // This wrapper contains a bus multiplexer and a bus demultiplexer. Both // // modules have all ports exposed an there are no signals connecting them. // // // // --------------------- // // | wrap | // // | | // // | ----------- | // // bsi -> | -> | mux | -> | -> sto // // | ----------- | // // | | // // | ----------- | // // bso <- | <- | demux | <- | <- sto // // | ----------- | // // | | // // --------------------- // // // //////////////////////////////////////////////////////////////////////////////// module sv_bus_mux_demux_wrap ( // system signals input logic clk, input logic rst, // input bus input logic bsi_vld, // valid (chip select) input logic [31:0] bsi_adr, // address input logic [31:0] bsi_dat, // data output logic bsi_rdy, // ready (acknowledge) // output stream output logic sto_vld, output logic [7:0] sto_bus, input logic sto_rdy, // input stream input logic sti_vld, input logic [7:0] sti_bus, output logic sti_rdy, // output bus output logic bso_vld, // valid (chip select) output logic [31:0] bso_adr, // address output logic [31:0] bso_dat, // data input logic bso_rdy // ready (acknowledge) ); sv_bus_mux_demux_mux mux ( // system signals .clk (clk), .rst (rst), // input bus .bus_vld (bsi_vld), .bus_adr (bsi_adr), .bus_dat (bsi_dat), .bus_rdy (bsi_rdy), // output stream .str_vld (sto_vld), .str_bus (sto_bus), .str_rdy (sto_rdy) ); sv_bus_mux_demux_demux demux ( // system signals .clk (clk), .rst (rst), // input stream .str_vld (sti_vld), .str_bus (sti_bus), .str_rdy (sti_rdy), // output bus .bus_vld (bso_vld), .bus_adr (bso_adr), .bus_dat (bso_dat), .bus_rdy (bso_rdy) ); endmodule : sv_bus_mux_demux_wrap verilator-5.044/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv0000644000542200017500000000212115125463617027600 0ustar mahmoudyfreeshell//////////////////////////////////////////////////////////////////////////////// // // // This file is placed into the Public Domain, for any use, without warranty. // // 2012 by Iztok Jeras // // SPDX-License-Identifier: CC0-1.0 // // // //////////////////////////////////////////////////////////////////////////////// // definition of data bus structure package package_bus; typedef struct packed { logic [3:0] [7:0] adr; // address logic [3:0] [7:0] dat; // data } t_bus; endpackage : package_bus // definition of streaming bus packet as an array package package_str; typedef logic [7:0][7:0] t_str; endpackage : package_str // union of the structure and array representation package package_uni; import package_bus::*; import package_str::*; typedef union packed { t_bus bus; t_str str; } t_uni; endpackage : package_uni verilator-5.044/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv0000644000542200017500000000455715125463617027672 0ustar mahmoudyfreeshell//////////////////////////////////////////////////////////////////////////////// // // // This file is placed into the Public Domain, for any use, without warranty. // // 2012 by Iztok Jeras // // SPDX-License-Identifier: CC0-1.0 // // // //////////////////////////////////////////////////////////////////////////////// import package_bus::*; import package_str::*; import package_uni::*; module sv_bus_mux_demux_mux ( // system signals input logic clk, // clock input logic rst, // reset // input bus input logic bus_vld, // valid (chip select) input logic [31:0] bus_adr, // address input logic [31:0] bus_dat, // data output logic bus_rdy, // ready (acknowledge) // output stream output logic str_vld, // valid (chip select) output logic [7:0] str_bus, // byte data bus input logic str_rdy // ready (acknowledge) ); logic bus_trn; // bus data transfer logic str_trn; // stream data transfer logic [2:0] pkt_cnt; // packet byte counter logic pkt_end; // packet byte counter end //t_bus pkt_bus; // transfer packet as a structure //t_str pkt_str; // transfer packet as an array t_uni pkt_uni; // transfer packet as an union // bus data transfer assign bus_trn = bus_vld & bus_rdy; // ready if pipe is empty or output is ready assign bus_rdy = ~str_vld | pkt_end; // writing input address/data into a structure always @ (posedge clk) if (bus_trn) begin pkt_uni.bus.adr <= bus_adr; pkt_uni.bus.dat <= bus_dat; end // output valid is set by an input transfer // or cleared by the last output transfer always @ (posedge clk, posedge rst) if (rst) str_vld <= 1'b0; else str_vld <= bus_trn | (str_vld & ~pkt_end); // packet byte counter always @ (posedge clk, posedge rst) if (rst) pkt_cnt <= '0; else if (str_trn) pkt_cnt <= pkt_cnt + 3'd1; // packet byte counter end assign pkt_end = str_rdy & (&pkt_cnt); // TODO, this should be a registered signal assign str_bus = pkt_uni.str [pkt_cnt]; // stream data transfer assign str_trn = str_vld & str_rdy; endmodule : sv_bus_mux_demux_mux verilator-5.044/test_regress/t/t_cover_unused_bad.v0000644000542200017500000000057015125463617023124 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; logic unu3 = 0; logic isusd = 0; cover property (@(posedge clk) isusd == 0); endmodule verilator-5.044/test_regress/t/t_interface_virtual_unused.py0000755000542200017500000000073415125463617025076 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_enum_bad_cell.out0000644000542200017500000000101415125463617022722 0ustar mahmoudyfreeshell%Warning-VARHIDDEN: t/t_enum_bad_cell.v:12:14: Declaration of enum value hides declaration in upper scope: s1 12 | enum {s0, s1} state; | ^~ t/t_enum_bad_cell.v:8:8: ... Location of original declaration 8 | sub s1(); | ^~ ... For warning description see https://verilator.org/warn/VARHIDDEN?v=latest ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.044/test_regress/t/t_fuzz_triand_bad.v0000644000542200017500000000037715125463617022767 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (); tri g=g.and.g; endmodule verilator-5.044/test_regress/t/t_gen_duplicated_blocks_bad.v0000644000542200017500000000056115125463617024727 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; parameter X = 2; begin : block end begin : block end if (X > 0) begin : block1 end if (X > 1) begin : block1 end endmodule verilator-5.044/test_regress/t/t_class_mod_bad.py0000755000542200017500000000076615125463617022564 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_multitop_xref.v0000644000542200017500000000141715125463617022517 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on // verilator lint_off MULTITOP module dut; bit [15:0] acp; function void reset(); acp = 0; endfunction initial reset(); endmodule module t; class Cls; static task rw(); dut.acp++; endtask endclass initial begin Cls c; c = new; c.rw(); `checkd(dut.acp, 1); $finish; end endmodule verilator-5.044/test_regress/t/t_func_outfirst.py0000755000542200017500000000073415125463617022677 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_extract_static_const.v0000644000542200017500000000277115125463617024051 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 module t; bit [255:0] C; initial C = {32'h1111_1111, 32'h2222_2222, 32'h3333_3333, 32'h4444_4444, 32'h5555_5555, 32'h6666_6666, 32'h7777_7777, 32'h8888_8888}; // Same values as above, but with different type logic [255:0] D; initial D = {32'h1111_1111, 32'h2222_2222, 32'h3333_3333, 32'h4444_4444, 32'h5555_5555, 32'h6666_6666, 32'h7777_7777, 32'h8888_8888}; int i; initial begin // Note: Base index via $c to prevent optimization by Verilator i = $c(0*32); $display("0x%8x", C[i+:32]); i = $c(1*32); $display("0x%8x", D[i+:32]); i = $c(2*32); $display("0x%8x", C[i+:32]); i = $c(3*32); $display("0x%8x", D[i+:32]); i = $c(4*32); $display("0x%8x", C[i+:32]); i = $c(5*32); $display("0x%8x", D[i+:32]); i = $c(6*32); $display("0x%8x", C[i+:32]); i = $c(7*32); $display("0x%8x", D[i+:32]); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_hier_block_sc_trace_fst.py0000755000542200017500000000316715125463617024630 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.priority(30) test.scenarios('vlt_all') test.top_filename = "t/t_hier_block.v" # stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. test.clean_objs() # CI environment offers 2 VCPUs, 2 thread setting causes the following warning. # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. # So use 6 threads here though it's not optimal in performance, but ok. test.compile(v_flags2=['t/t_hier_block.cpp'], verilator_flags2=[ '--sc', '--stats', '--hierarchical', '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"', "--CFLAGS", '"-O0 -ggdb"', "--trace-fst" ], threads=(6 if test.vltmt else 1)) test.execute() test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") test.file_grep(test.obj_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") test.file_grep(test.obj_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14) test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_multitop_xref.py0000755000542200017500000000073415125463617022706 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_interface_virtual_unused2.py0000755000542200017500000000073415125463617025160 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_timescale_unit.v0000644000542200017500000000105215125463617022616 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 timeunit 10ps; timeprecision 10ps; task show; $printtimescale; endtask module from_unit; task show; $printtimescale; endtask endmodule module t; from_unit from_unit (); timeunit 100ps; initial begin show(); from_unit.show(); $printtimescale; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_vpi_time_cb.cpp0000644000542200017500000000462015125463617022412 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "verilated.h" #include "verilated_vcd_c.h" #include "verilated_vpi.h" #include "Vt_vpi_time_cb.h" #include "Vt_vpi_time_cb__Dpi.h" #include "svdpi.h" #include // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" //====================================================================== int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; uint64_t sim_time = 1100; contextp->debug(0); contextp->commandArgs(argc, argv); const std::unique_ptr topp{new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; #ifdef TEST_VERBOSE contextp->scopesDump(); #endif #if VM_TRACE contextp->traceEverOn(true); VL_PRINTF("Enabling waves...\n"); VerilatedVcdC* tfp = new VerilatedVcdC; topp->trace(tfp, 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); #endif VerilatedVpi::callCbs(cbStartOfSimulation); topp->eval(); topp->clk = 0; while (vl_time_stamp64() < sim_time && !contextp->gotFinish()) { contextp->timeInc(1); topp->eval(); VerilatedVpi::callValueCbs(); VerilatedVpi::callTimedCbs(); if (contextp->time() > 20) { // Else haven't registered callbacks TEST_CHECK_EQ(VerilatedVpi::cbNextDeadline(), contextp->time() + 1); } if ((contextp->time() % 5) == 0) topp->clk = !topp->clk; // mon_do(); #if VM_TRACE if (tfp) tfp->dump(contextp->time()); #endif } VerilatedVpi::callCbs(cbEndOfSimulation); if (!contextp->gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); #if VM_TRACE if (tfp) tfp->close(); #endif return errors ? 10 : 0; } verilator-5.044/test_regress/t/t_const_slicesel.v0000644000542200017500000000107615125463617022630 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Michael Lefebvre. // SPDX-License-Identifier: CC0-1.0 module t; localparam int unsigned A2 [1:0] = '{5,6}; localparam int unsigned A3 [2:0] = '{4,5,6}; // Matching sizes with slicesel are okay. localparam int unsigned B22 [1:0] = A2[1:0]; localparam int unsigned B33 [2:0] = A3[2:0]; // See issue #3186 localparam int unsigned B32_B [1:0] = A3[1:0]; localparam int unsigned B32_T [1:0] = A3[2:1]; endmodule verilator-5.044/test_regress/t/t_enum_enumvalue_struct_bad.py0000755000542200017500000000076615125463617025251 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(expect_filename=test.golden_filename, fails=True) test.passes() verilator-5.044/test_regress/t/t_trace_dumpvars_dyn.cpp0000644000542200017500000000366315125463617024031 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #if VM_TRACE_FST #include #define TRACE_FILE_NAME "simx.fst" #define TRACE_CLASS VerilatedFstC #elif VM_TRACE_VCD #include #define TRACE_FILE_NAME "simx.vcd" #define TRACE_CLASS VerilatedVcdC #elif VM_TRACE_SAIF #include #define TRACE_FILE_NAME "simx.saif" #define TRACE_CLASS VerilatedSaifC #endif #include #include VM_PREFIX_INCLUDE unsigned long long main_time = 0; double sc_time_stamp() { return (double)main_time; } const unsigned long long dt_2 = 3; int main(int argc, char** argv) { Verilated::debug(0); Verilated::traceEverOn(true); Verilated::commandArgs(argc, argv); std::unique_ptr top{new VM_PREFIX{"top"}}; std::unique_ptr tfp{new TRACE_CLASS}; #if defined(T_TRACE_DUMPVARS_DYN_VCD_0) || defined(T_TRACE_DUMPVARS_DYN_FST_0) \ || defined(T_TRACE_DUMPVARS_DYN_SAIF_0) tfp->dumpvars(0, ""); #elif defined(T_TRACE_DUMPVARS_DYN_VCD_1) || defined(T_TRACE_DUMPVARS_DYN_FST_1) \ || defined(T_TRACE_DUMPVARS_DYN_SAIF_1) tfp->dumpvars(99, "t"); // This should not match "top." tfp->dumpvars(1, "top.t.cyc"); // A signal tfp->dumpvars(1, "top.t.sub1a"); // Scope tfp->dumpvars(2, "top.t.sub1b"); // Scope #else #error "Bad test" #endif top->trace(tfp.get(), 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/" TRACE_FILE_NAME); top->clk = 0; while (main_time <= 20) { top->eval(); tfp->dump((unsigned int)(main_time)); ++main_time; top->clk = !top->clk; } tfp->close(); top->final(); tfp.reset(); top.reset(); printf("*-* All Finished *-*\n"); return 0; } verilator-5.044/test_regress/t/t_class_this_super.v0000644000542200017500000000200515125463617023162 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on // Based on icarus/ivtest/ivltests/sv_class_super6.v class B; int m_x, m_y; task set_y; m_y = 2000; endtask function void check_x; `checkd(m_x, 1000); endfunction endclass class C extends B; byte m_x, m_y; task set_x; m_x = 6; this.m_y = 7; this.super.m_x = 1000; endtask function void check_y; `checkd(m_x, 6); `checkd(this.m_y, 7); `checkd(this.super.m_y, 2000); endfunction endclass module test; C c; initial begin c = new; c.set_x(); c.set_y(); c.check_x(); c.check_y(); $finish; end endmodule verilator-5.044/test_regress/t/t_structu_dataType_assignment.v0000644000542200017500000000766615125463617025426 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for specialized type default values // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Mostafa Gamal. // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off UNPACKED */ module top(); typedef struct { // IEEE 1800-2023 5.10 int a; shortint b; } ab_struct; typedef struct { // IEEE 1800-2023 10.9.2 int x; int y; } st_struct; typedef struct { // IEEE 1800-2023 10.9.2 logic [7:0] a; bit b; bit signed [31:0] c; int s; } sa_struct; typedef struct { // IEEE 1800-2023 10.9.2 int A; struct { int B, C; } BC1, BC2; } DEF_struct; typedef struct { // IEEE 1800-2023 10.9.2 int A; struct { int B, C; struct { int D, E; struct { int F; shortint G; } FG1; } DE1; } BC1; } HIJ_struct; // struct ab ab_struct ab; ab_struct abkey[1:0]; // struct st st_struct st; int k = 1; // struct sa sa_struct sa; // struct DEF DEF_struct DEF; // struct HIJ HIJ_struct HIJ; initial begin // struct ab ab = '{0, 0}; //constant member by position if (ab.a != 0) $stop; if (ab.b != 0) $stop; ab = '{default: 0}; //default value if (ab.a != 0) $stop; if (ab.b != 0) $stop; ab = '{int: 1, shortint: 0}; //data type and default value if (ab.a != 1) $stop; if (ab.b != 0) $stop; abkey[1:0] = '{'{a:1, b:2}, '{int:2, shortint:3}}; // member: value & data_type: value if (abkey[1].a != 1) $stop; if (abkey[1].b != 2) $stop; if (abkey[0].a != 2) $stop; if (abkey[0].b != 3) $stop; // struct st st = '{1, 2+k}; //constant member by position if (st.x != 1) $stop; if (st.y != 2+k) $stop; st = '{x:2, y:3+k}; //member: value if (st.x != 2) $stop; if (st.y != 3+k) $stop; st = '{int:2, int:3+k}; //data_type: value override if (st.x != 3+k) $stop; if (st.y != 3+k) $stop; // struct sa sa = '{default:'1}; if (sa.a != '1) $stop; if (sa.b != '1) $stop; if (sa.c != '1) $stop; if (sa.s != '1) $stop; sa = '{default:'1, int: 5}; if (sa.a != '1) $stop; if (sa.b != '1) $stop; if (sa.c != '1) $stop; if (sa.s != 5) $stop; sa = '{default:'1, int: 5, b: 0}; if (sa.a != '1) $stop; if (sa.b != 0) $stop; if (sa.c != '1) $stop; if (sa.s != 5) $stop; // struct DEF DEF = '{A:1, BC1:'{B:2, C:3}, BC2:'{B:4,C:5}}; if (DEF.A != 1) $stop; if (DEF.BC1.B != 2) $stop; if (DEF.BC1.C != 3) $stop; if (DEF.BC2.B != 4) $stop; if (DEF.BC2.C != 5) $stop; DEF = '{int:0, BC1:'{int:10}, BC2:'{default:5}}; if (DEF.A != 0) $stop; if (DEF.BC1.B != 10) $stop; if (DEF.BC1.C != 10) $stop; if (DEF.BC2.B != 5) $stop; if (DEF.BC2.C != 5) $stop; DEF = '{default:1, BC1:'{int:10}, BC2:'{default:5}}; if (DEF.A != 1) $stop; if (DEF.BC1.B != 10) $stop; if (DEF.BC1.C != 10) $stop; if (DEF.BC2.B != 5) $stop; if (DEF.BC2.C != 5) $stop; DEF = '{default:10}; if (DEF.A != 10) $stop; if (DEF.BC1.B != 10) $stop; if (DEF.BC1.C != 10) $stop; if (DEF.BC2.B != 10) $stop; if (DEF.BC2.C != 10) $stop; DEF = '{int:10}; if (DEF.A != 10) $stop; if (DEF.BC1.B != 10) $stop; if (DEF.BC1.C != 10) $stop; if (DEF.BC2.B != 10) $stop; if (DEF.BC2.C != 10) $stop; // struct HIJ HIJ = '{int:10, default: 5}; if (HIJ.A != 10) $stop; if (HIJ.BC1.B != 10) $stop; if (HIJ.BC1.C != 10) $stop; if (HIJ.BC1.DE1.D != 10) $stop; if (HIJ.BC1.DE1.E != 10) $stop; if (HIJ.BC1.DE1.FG1.F != 10) $stop; if (HIJ.BC1.DE1.FG1.G != 5) $stop; HIJ = '{shortint:10, default: 5}; if (HIJ.A != 5) $stop; if (HIJ.BC1.B != 5) $stop; if (HIJ.BC1.C != 5) $stop; if (HIJ.BC1.DE1.D != 5) $stop; if (HIJ.BC1.DE1.E != 5) $stop; if (HIJ.BC1.DE1.FG1.F != 5) $stop; if (HIJ.BC1.DE1.FG1.G != 10) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_udp_binary_top.v0000644000542200017500000000066615125463617022641 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Test that a standalone primitive can be a top level module primitive p(output id_2, input id_1); table 1 : 0; 0 : 1; endtable endprimitive module t; // Overridden by --top-module initial $stop; endmodule verilator-5.044/test_regress/t/t_string_add_bad.v0000644000542200017500000000073315125463617022542 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; string s; initial begin for (int a = 0; a < 3; ++a) begin : a_loop s += $sformatf(" a%0d", a); // <--- Error: += is not legal on strings s = s + s; // <--- Error: += is not legal on strings end $stop; end endmodule verilator-5.044/test_regress/t/t_let_stmt_bad.py0000755000542200017500000000076615125463617022453 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_typedef_param.v0000644000542200017500000000477115125463617022444 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef reg [2:0] threeansi_t; module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [2:0] in = crc[2:0]; localparam type three_t = reg [2:0]; three_t outna; three_t outa; TestNonAnsi #( .p_t (reg [2:0]) ) test (// Outputs .out (outna), /*AUTOINST*/ // Inputs .clk (clk), .in (in[2:0])); TestAnsi #( .p_t (reg [2:0])) testa (// Outputs .out (outa), /*AUTOINST*/ // Inputs .clk (clk), .in (in[2:0])); // Aggregate outputs into a single result vector wire [63:0] result = {57'h0, outna, 1'b0, outa}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h018decfea0a8828a if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module TestNonAnsi (/*AUTOARG*/ // Outputs out, // Inputs clk, in ); /*verilator hier_block*/ parameter type p_t = shortint; input clk; input p_t in; output p_t out; always @(posedge clk) begin out <= ~in; end endmodule module TestAnsi #( parameter type p_t = shortint ) ( input clk, input p_t in, output p_t out ); /*verilator hier_block*/ always @(posedge clk) begin out <= ~in; end endmodule // Local Variables: // verilog-typedef-regexp: "_t$" // End: verilator-5.044/test_regress/t/t_sys_file_null.py0000755000542200017500000000112715125463617022651 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() filename = test.obj_dir + "/zeros.log" if os.path.getsize(filename) != 20: test.error(filename + ": Wrong file size") test.passes() verilator-5.044/test_regress/t/t_tri_graph.v0000644000542200017500000000101415125463617021566 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Unsupported tristate construct error // // This is a compile only regression test of tristate handling for bug514 // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; wire [11:0] ck; assign ck[1:0] = {1'bz,{1{1'b0}}}; test i_test (.clk (ck[1:0])); endmodule module test (clk); output wire [1:0] clk; endmodule // test verilator-5.044/test_regress/t/t_stream_crc_example.py0000755000542200017500000000073415125463617023642 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_interface_twod_noinl.py0000755000542200017500000000103715125463617024176 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_twod.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_lint_iface_array_topmodule_bad.v0000644000542200017500000000204515125463617026005 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Josh Redford. // SPDX-License-Identifier: CC0-1.0 interface my_if #( parameter integer DW ) (); logic valid; logic [7:0] data ; modport slave_mp ( input valid, input data ); modport master_mp ( output valid, output data ); endinterface module t ( input wire clk, my_if.slave_mp in_if [2], my_if.master_mp out_if [2] ); my_if my_i [2] (); always @(posedge clk) begin my_i[0].valid <= in_if[0].valid; my_i[0].data <= in_if[0].data; my_i[1].valid <= in_if[1].valid; my_i[1].data <= in_if[1].data; end assign out_if[0].valid = my_i[0].valid; assign out_if[0].data = my_i[0].data; assign out_if[1].valid = my_i[1].valid; assign out_if[1].data = my_i[1].data; endmodule verilator-5.044/test_regress/t/t_math_div_noexpand.py0000755000542200017500000000103315125463617023465 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_math_div.v" test.compile(verilator_flags2=['-fno-expand']) test.execute() test.passes() verilator-5.044/test_regress/t/t_mem_banks.py0000755000542200017500000000073415125463617021741 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_opt_table_display.py0000755000542200017500000000103415125463617023475 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--stats"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_var_ref_bad1.py0000755000542200017500000000076315125463617022322 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_trace_noflag_bad.v0000644000542200017500000000052115125463617023043 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; int i; initial begin i = 10; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_std_identifier_bad.py0000755000542200017500000000104115125463617023577 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_std_identifier.v" test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_export_packed_struct2.py0000755000542200017500000000105215125463617024315 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.044/test_regress/t/t_hier_block_typedef_param.py0000755000542200017500000000105115125463617024777 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_typedef_param.v" test.compile(verilator_flags2=["--hierarchical"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_clk_concat2.py0000755000542200017500000000073415125463617022167 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_covergroup_with_sample_args_default.py0000755000542200017500000000070615125463617027313 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.044/test_regress/t/t_class_extends1.v0000644000542200017500000000464315125463617022542 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Base0; class BaseInnerOnly; int inneronly; function new(); inneronly = 10; if (inneronly != 10) $stop; endfunction endclass class BaseInnerOver; int innerover; function new(); innerover = 10; if (innerover != 10) $stop; endfunction endclass int baseonly; int baseover; BaseInnerOnly inneronly = new; BaseInnerOver innerover = new; function void b_set_bo(int v); baseover = v; endfunction function int b_get_bo(); return baseover; endfunction function int get_bo(); return baseover; endfunction function void b_set_io(int v); innerover.innerover = v; endfunction function int b_get_io(); return innerover.innerover; endfunction function int get_io(); return innerover.innerover; endfunction endclass class Ext extends Base0; class BaseInnerOver; int innerover; function new(); innerover = 20; if (innerover != 20) $stop; endfunction endclass int baseover; int extonly; BaseInnerOnly inneronly = new; BaseInnerOver innerover = new; function void e_set_bo(int v); baseover = v; endfunction function int e_get_bo(); return baseover; endfunction function int get_bo(); return baseover; endfunction function void e_set_io(int v); innerover.innerover = v; endfunction function int e_get_io(); return innerover.innerover; endfunction function int get_io(); return innerover.innerover; endfunction endclass module t; initial begin Ext c; c = new; c.baseonly = 10; c.baseover = 20; c.extonly = 30; c.inneronly.inneronly = 40; c.innerover.innerover = 50; if (c.baseonly != 10) $stop; if (c.baseover != 20) $stop; if (c.extonly != 30) $stop; if (c.inneronly.inneronly != 40) $stop; if (c.innerover.innerover != 50) $stop; c.b_set_bo(100); c.e_set_bo(200); c.b_set_io(300); c.e_set_io(400); if (c.b_get_bo() != 100) $stop; if (c.e_get_bo() != 200) $stop; if (c.get_bo() != 200) $stop; if (c.b_get_io() != 300) $stop; if (c.e_get_io() != 400) $stop; if (c.get_io() != 400) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_trace_fst.v0000644000542200017500000000515615125463617021574 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // Author: Yu-Sheng Lin johnjohnlys@media.ee.ntu.edu.tw // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs state, // Inouts fst_inout, // Inputs clk ); input clk; int cyc; reg rstn; output [4:0] state; parameter real fst_gparam_real = 1.23; localparam real fst_lparam_real = 4.56; real fst_real = 1.23; integer fst_integer; bit fst_bit; logic fst_logic; int fst_int; shortint fst_shortint; longint fst_longint; byte fst_byte; time fst_time; parameter fst_parameter = 123; localparam fst_lparam = 456; supply0 fst_supply0; supply1 fst_supply1; tri0 fst_tri0; tri1 fst_tri1; tri fst_tri; triand fst_triand; trior fst_trior; //trireg fst_trireg; // Error-UNSUPPORTED wand fst_wand; wor fst_wor; wire fst_wire; uwire fst_uwire; inout fst_inout; Test test (/*AUTOINST*/ // Outputs .state (state[4:0]), // Inputs .clk (clk), .rstn (rstn)); // Test loop always @ (posedge clk) begin cyc <= cyc + 1; fst_time <= $time; if (cyc==0) begin // Setup rstn <= ~'1; end else if (cyc<10) begin rstn <= ~'1; end else if (cyc<90) begin rstn <= ~'0; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( input clk, input rstn, output logic [4:0] state ); logic [4:0] state_w; logic [4:0] state_array [3]; assign state = state_array[0]; always_comb begin state_w[4] = state_array[2][0]; state_w[3] = state_array[2][4]; state_w[2] = state_array[2][3] ^ state_array[2][0]; state_w[1] = state_array[2][2]; state_w[0] = state_array[2][1]; end always_ff @(posedge clk or negedge rstn) begin if (!rstn) begin for (int i = 0; i < 3; i++) state_array[i] <= 'b1; end else begin for (int i = 0; i < 2; i++) state_array[i] <= state_array[i+1]; state_array[2] <= state_w; end end endmodule verilator-5.044/test_regress/t/t_case_write1_noexpand.py0000755000542200017500000000103615125463617024103 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_case_write1.v" test.compile(verilator_flags2=['-fno-expand']) test.execute() test.passes() verilator-5.044/test_regress/t/t_gen_defparam.py0000755000542200017500000000073415125463617022415 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_opt_dead_noassigns.py0000755000542200017500000000116215125463617023644 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--fno-dead-assigns']) test.execute() files = test.glob_some(test.obj_dir + "/" + test.vm_prefix + "_*.cpp") test.file_grep_any(files, r'keptdead') test.passes() verilator-5.044/test_regress/t/t_randsequence_recurse.out0000644000542200017500000000040015125463617024354 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_randsequence_recurse.v:21:5: Unsupported: randsequence 21 | randsequence(main) | ^~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.044/test_regress/t/t_func_wide_out_bad.py0000755000542200017500000000103515125463617023440 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_func_wide_out.v" test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_timing_dpi_unsup.py0000755000542200017500000000104315125463617023354 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_timing_dpi_unsup.v" test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_randomize_srandom.py0000755000542200017500000000073415125463617023520 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_class_capitalization.v0000644000542200017500000000234715125463617024021 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Test different uppercase/lowercase capitalization cases class ClsMixed; int m; int M; endclass class Clsmixed; int m; int M; endclass module ModMixed; // verilator no_inline_module int m; int M; endmodule module Modmixed; // verilator no_inline_module int m; int M; endmodule module t; // verilator no_inline_module ModMixed modMixed(); Modmixed modmixed(); initial begin ClsMixed clsMixed; Clsmixed clsmixed; clsMixed = new; clsMixed.m = 1; clsMixed.M = 2; clsmixed = new; clsmixed.m = 3; clsmixed.M = 4; if (clsMixed.m != 1) $stop; if (clsMixed.M != 2) $stop; if (clsmixed.m != 3) $stop; if (clsmixed.M != 4) $stop; modMixed.m = 1; modMixed.M = 2; modmixed.m = 3; modmixed.M = 4; if (modMixed.m != 1) $stop; if (modMixed.M != 2) $stop; if (modmixed.m != 3) $stop; if (modmixed.M != 4) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_dpi_context.v0000644000542200017500000000443515125463617022141 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); sub a (.inst(1)); sub b (.inst(2)); initial begin a.test1; b.test1; a.test2; b.test2; $write("*-* All Finished *-*\n"); $finish; end import "DPI-C" context function void dpic_final(); final dpic_final(); endmodule module sub (input integer inst); import "DPI-C" context function int dpic_line(); import "DPI-C" context function int dpic_save(int value); import "DPI-C" context function int dpic_restore(); import "DPI-C" context function int unsigned dpic_getcontext(); import "DPI-C" context function int unsigned dpic_get1(); int result; // Exports here are only to cover the export dumper of Verilated::internalsDump export "DPI-C" function dpix_void; function void dpix_void; endfunction export "DPI-C" function dpix_result; function int dpix_result; return result; endfunction task test1; // Check line numbering `ifndef verilator // Not all sims support SV2009 `__LINE__, and some that do fail the specific-line test result = dpic_line(); if (!result) $stop; `else result = dpic_line(); if (result !== `__LINE__) $stop; // result = dpic_line(); if (result !== `__LINE__) $stop; `endif // Check save-restore result = dpic_save(23+inst); if (result==0) $stop; endtask task test2; if (dpic_restore() != 23+inst) $stop; endtask function automatic int call_dpic_get1; int res = dpic_get1(); return res; endfunction int unsigned cntxt1; int unsigned cntxt2; initial begin cntxt1 = dpic_getcontext(); begin : caller_context // call from a different scope - should still get the context of the function declaration cntxt2 = dpic_getcontext(); end // svContext should be the context of the function declaration, not the context of the function call if (cntxt1 != cntxt2) $stop; if (call_dpic_get1() != 1) $stop; end endmodule verilator-5.044/test_regress/t/t_gen_intdot.v0000644000542200017500000000424215125463617021747 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; wire out; reg in; Genit g (.clk(clk), .value(in), .result(out)); always @ (posedge clk) begin //$write("[%0t] cyc==%0d %x %x\n", $time, cyc, in, out); cyc <= cyc + 1; if (cyc==0) begin // Setup in <= 1'b1; end else if (cyc==1) begin in <= 1'b0; end else if (cyc==2) begin if (out != 1'b1) $stop; end else if (cyc==3) begin if (out != 1'b0) $stop; end else if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module Generate (clk, value, result); input clk; input value; output result; reg Internal; assign result = Internal; always @(posedge clk) Internal <= value; endmodule module Checker (clk, value); input clk, value; always @(posedge clk) begin $write ("[%0t] value=%h\n", $time, value); end endmodule module Test (clk, value, result); input clk; input value; output result; Generate gen (clk, value, result); Checker chk (clk, gen.Internal); endmodule module Genit (clk, value, result); input clk; input value; output result; `ifndef ATSIM // else unsupported `ifndef NC // else unsupported `ifndef IVERILOG // else unsupported `define WITH_FOR_GENVAR `endif `endif `endif `define WITH_GENERATE `ifdef WITH_GENERATE `ifndef WITH_FOR_GENVAR genvar i; `endif generate for ( `ifdef WITH_FOR_GENVAR genvar `endif i = 0; i < 1; i = i + 1) begin : foo Test tt (clk, value, result); end endgenerate `else Test tt (clk, value, result); `endif wire Result2 = t.g.foo[0].tt.gen.Internal; // Works - Do not change! always @ (posedge clk) begin $write("[%0t] Result2 = %x\n", $time, Result2); end endmodule verilator-5.044/test_regress/t/t_sampled_expr.v0000644000542200017500000000220415125463617022274 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [3:0] a, b; Test1 t1(clk, a, b); Test2 t2(clk, a, b); Test3 t3(clk); initial begin a = 0; b = 0; end always @(posedge clk) begin a <= a + 1; b = b + 1; $display("a = %0d, b = %0d, %0d == %0d", a, b, $sampled(a), $sampled(b)); if (b >= 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test1( clk, a, b ); input clk; input [3:0] a, b; assert property (@(posedge clk) $sampled(a == b) == ($sampled(a) == $sampled(b))); endmodule module Test2( clk, a, b ); input clk; input [3:0] a, b; assert property (@(posedge clk) eq(a, b)); function [0:0] eq([3:0] x, y); return x == y; endfunction endmodule module Test3( clk ); input clk; assert property (@(posedge clk) $sampled($time) == $time); endmodule verilator-5.044/test_regress/t/t_increment_bad.py0000755000542200017500000000076315125463617022601 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_lparam_assign_iface_typedef3.py0000755000542200017500000000077115125463617025560 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_math_tri.v0000644000542200017500000000110415125463617021416 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [3:0] a; reg [99:0] x; initial begin a = 4'b010x; if (a[3:2] !== 2'b01) $stop; if (|a !== 1'b1) $stop; if (&a !== 1'b0) $stop; x = 100'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_opt_const_red.py0000755000542200017500000000116115125463617022642 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-Wno-UNOPTTHREADS", "--stats"]) test.execute() if test.vlt: test.file_grep(test.stats, r'Optimizations, Const bit op reduction\s+(\d+)', 160) test.passes() verilator-5.044/test_regress/t/t_preproc_inc_recurse_bad.out0000644000542200017500000000050115125463617025012 0ustar mahmoudyfreeshell%Error: t/t_preproc_inc_recurse_bad.v:7:10: Recursive inclusion of file: t/t_preproc_inc_recurse_bad.v 7 | `include "t_preproc_inc_recurse_bad.v" | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_param_type_bit.py0000755000542200017500000000071415125463617023002 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.044/test_regress/t/t_func_named.py0000755000542200017500000000073415125463617022104 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_time_vpi_1ns1ns.py0000755000542200017500000000147215125463617023024 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.pli_filename = "t/t_time_vpi_c.cpp" test.top_filename = "t/t_time_vpi.v" test.main_time_multiplier = 1e-9 / 1e-9 test.compile( v_flags2=['+define+time_scale_units=1ns +define+time_scale_prec=1ns', test.pli_filename], verilator_flags2=['--vpi --trace-vcd']) test.execute(expect_filename=test.golden_filename) test.file_grep(test.trace_filename, r'timescale +1ns') test.passes() verilator-5.044/test_regress/t/t_timing_fork_comb.v0000644000542200017500000000241715125463617023127 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; bit clk; assign #5 clk = ~clk; int a = 0; always @(posedge clk) begin a <= a + 1; `ifdef TEST_VERBOSE $display("a=%0d, b=%0d, c=%0d, d=%0d, e=%0d, f=%0d, v=%b", a, b, c, d, e, f, v); `endif end int b = 0, c = 0, d = 0, e = 0, f = 0; always @a begin b = a << 1; fork #10 d = b + c; e = c + d; #5 f = d + e; join_none c = a + b; end bit [5:0] v; always @a begin v[0] = a[0]; fork begin v[1] = a[1]; #5 v[2] = a[2]; end #10 v[3] = a[3]; join_none v[4] = a[4]; end initial #100 begin `ifdef TEST_VERBOSE $display("a=%0d, b=%0d, c=%0d, d=%0d, e=%0d, f=%0d, v=%b", a, b, c, d, e, f, v); `endif if (a != 10) $stop; if (b != 20) $stop; if (c != 30) $stop; if (d != 45) $stop; if (e != 75) $stop; if (f != 107) $stop; if (v != 'b001010) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_mod_interface_array0_noinl.py0000755000542200017500000000104515125463617025255 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_mod_interface_array0.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_dpi_binary.py0000755000542200017500000000110215125463617022113 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.pli_filename = "t/t_dpi_binary_c.cpp" test.compile(v_flags2=[test.pli_filename], verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.044/test_regress/t/t_trace_scstruct.v0000644000542200017500000000100115125463617022633 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off UNUSED // verilator lint_off UNDRIVEN //bug858 typedef struct packed { logic m_1; logic m_2; } struct_t; typedef struct packed { logic [94:0] m_1; logic m_2; } struct96_t; module t ( input struct_t test_input, input struct96_t t96 ); endmodule verilator-5.044/test_regress/t/t_trace_scope_no_inline.out0000644000542200017500000000336615125463617024506 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $scope module t $end $scope module mid_a $end $upscope $end $scope module mid_b $end $var wire 1 ' clk $end $var wire 32 # cnt [31:0] $end $scope module sub_a $end $var wire 1 ' clk $end $var wire 32 $ cnt [31:0] $end $upscope $end $scope module sub_b $end $var wire 1 ' clk $end $var wire 32 % cnt [31:0] $end $upscope $end $scope module sub_c $end $var wire 1 ' clk $end $var wire 32 & cnt [31:0] $end $upscope $end $upscope $end $scope module mid_c $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000000 # b00000000000000000000000000000000 $ b00000000000000000000000000000000 % b00000000000000000000000000000000 & 0' #10 b00000000000000000000000000000001 # b00000000000000000000000000000010 $ b00000000000000000000000000000010 % b00000000000000000000000000000010 & 1' #15 0' #20 b00000000000000000000000000000010 # b00000000000000000000000000000100 $ b00000000000000000000000000000100 % b00000000000000000000000000000100 & 1' #25 0' #30 b00000000000000000000000000000011 # b00000000000000000000000000000110 $ b00000000000000000000000000000110 % b00000000000000000000000000000110 & 1' #35 0' #40 b00000000000000000000000000000100 # b00000000000000000000000000001000 $ b00000000000000000000000000001000 % b00000000000000000000000000001000 & 1' #45 0' #50 b00000000000000000000000000000101 # b00000000000000000000000000001010 $ b00000000000000000000000000001010 % b00000000000000000000000000001010 & 1' #55 0' #60 b00000000000000000000000000000110 # b00000000000000000000000000001100 $ b00000000000000000000000000001100 % b00000000000000000000000000001100 & 1' verilator-5.044/test_regress/t/t_interface_array_nocolon.py0000755000542200017500000000073415125463617024672 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_vpi_module.cpp0000644000542200017500000001313315125463617022274 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #ifdef IS_VPI #include "vpi_user.h" #include #else #include "verilated.h" #include "verilated_vcd_c.h" #include "verilated_vpi.h" #include "Vt_vpi_module.h" #include "Vt_vpi_module__Dpi.h" #include "svdpi.h" #endif #include #include #include // These require the above. Comment prevents clang-format moving them #include "TestSimulator.h" #include "TestVpi.h" #define DEBUG \ if (0) printf void modDump(const TestVpiHandle& it, int n) { while (TestVpiHandle hndl = vpi_scan(it)) { const char* nm = vpi_get_str(vpiName, hndl); for (int i = 0; i < n; i++) printf(" "); printf("%s\n", nm); TestVpiHandle subIt = vpi_iterate(vpiModule, hndl); if (subIt) modDump(subIt, n + 1); } } extern "C" { int mon_check() { #ifdef TEST_VERBOSE printf("-mon_check()\n"); #endif TestVpiHandle it = vpi_iterate(vpiModule, NULL); CHECK_RESULT_NZ(it); // Uncomment to see what other simulators return // modDump(it, 0); // return 1; TestVpiHandle topmod; // both somepackage and t exist at the top level while ((topmod = vpi_scan(it))) { if (vpi_get(vpiType, topmod) == vpiModule) break; } CHECK_RESULT_NZ(topmod); const char* t_name = vpi_get_str(vpiName, topmod); CHECK_RESULT_NZ(t_name); // Icarus reports the top most module as "top" if (std::strcmp(t_name, "top") == 0) { it = vpi_iterate(vpiModule, topmod); CHECK_RESULT_NZ(it); CHECK_RESULT(vpi_get(vpiType, it), vpiModule); topmod = vpi_scan(it); t_name = vpi_get_str(vpiName, topmod); CHECK_RESULT_NZ(t_name); } CHECK_RESULT_CSTR(t_name, "t"); TestVpiHandle topmod_done_should_be_0 = (vpi_scan(it)); it.freed(); // IEEE 37.2.2 vpi_scan at end does a vpi_release_handle CHECK_RESULT_Z(topmod_done_should_be_0); TestVpiHandle it2 = vpi_iterate(vpiModule, topmod); CHECK_RESULT_NZ(it2); TestVpiHandle mod2 = vpi_scan(it2); CHECK_RESULT_NZ(mod2); const char* mod_a_name = vpi_get_str(vpiName, mod2); CHECK_RESULT_CSTR(mod_a_name, "\\mod.a "); TestVpiHandle it3 = vpi_iterate(vpiModule, mod2); CHECK_RESULT_NZ(it3); TestVpiHandle mod3 = vpi_scan(it3); CHECK_RESULT_NZ(mod3); const char* mod_c_name = vpi_get_str(vpiName, mod3); if (std::strcmp(mod_c_name, "\\mod_b$ ") == 0) { // Full visibility in other simulators, skip mod_b TestVpiHandle mod4 = vpi_scan(it3); CHECK_RESULT_NZ(mod4); mod_c_name = vpi_get_str(vpiName, mod4); } CHECK_RESULT_CSTR(mod_c_name, "\\mod\\c$ "); return 0; // Ok } } //====================================================================== #ifdef IS_VPI static int mon_check_vpi() { TestVpiHandle href = vpi_handle(vpiSysTfCall, 0); s_vpi_value vpi_value; vpi_value.format = vpiIntVal; vpi_value.value.integer = mon_check(); vpi_put_value(href, &vpi_value, NULL, vpiNoDelay); return 0; } static s_vpi_systf_data vpi_systf_data[] = {{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$mon_check", (PLI_INT32(*)(PLI_BYTE8*))mon_check_vpi, 0, 0, 0}, 0}; // cver entry void vpi_compat_bootstrap(void) { p_vpi_systf_data systf_data_p; systf_data_p = &(vpi_systf_data[0]); while (systf_data_p->type != 0) vpi_register_systf(systf_data_p++); } // icarus entry void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; #else int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; uint64_t sim_time = 1100; contextp->debug(0); contextp->commandArgs(argc, argv); // We're going to be checking for these errors so don't crash out contextp->fatalOnVpiError(0); { // Construct and destroy const std::unique_ptr topp{ new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; } // Test second construction const std::unique_ptr topp{new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; #ifdef VERILATOR #ifdef TEST_VERBOSE contextp->scopesDump(); #endif #endif #if VM_TRACE contextp->traceEverOn(true); VL_PRINTF("Enabling waves...\n"); VerilatedVcdC* tfp = new VerilatedVcdC; topp->trace(tfp, 99); tfp->open(STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); #endif topp->eval(); topp->clk = 0; contextp->timeInc(10); while (contextp->time() < sim_time && !contextp->gotFinish()) { contextp->timeInc(1); topp->eval(); VerilatedVpi::callValueCbs(); topp->clk = !topp->clk; // mon_do(); #if VM_TRACE if (tfp) tfp->dump(contextp->time()); #endif } if (!contextp->gotFinish()) { vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); #if VM_TRACE if (tfp) tfp->close(); #endif return 0; } #endif verilator-5.044/test_regress/t/t_fork_bbox.py0000755000542200017500000000076015125463617021757 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=['--no-timing --bbox-unsup']) test.passes() verilator-5.044/test_regress/t/t_constraint_global_random_simple.py0000755000542200017500000000104615125463617026417 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_alias_force.v0000644000542200017500000000132615125463617022064 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ // Inputs clk ); input clk; wire [15:0] a, b; integer cyc = 0; alias a = b; always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 1) begin force a = 16'h1234; if (a != 16'h1234 || a != b) $stop; release a; end else if (cyc == 2) begin force b = 16'h5678; if (a != 16'h5678 || a != b) $stop; release b; end else if (cyc == 3) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.044/test_regress/t/t_gantt_io_noproc.py0000755000542200017500000000132115125463617023162 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') test.run(cmd=[ "cd " + test.obj_dir + " && " + os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt" + " --no-vcd", test.t_dir + "/" + test.name + ".dat > gantt.log" ], check_finished=False) test.files_identical(test.obj_dir + "/gantt.log", test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_var_overcmp.py0000755000542200017500000000073415125463617022330 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_preproc_ifdef.py0000755000542200017500000000073415125463617022614 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_trace_iface.out0000644000542200017500000000326515125463617022410 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 ( clk $end $scope module t $end $var wire 1 ( clk $end $var wire 32 # cyc [31:0] $end $scope module c5_data $end $var wire 1 $ valid $end $var wire 4 % value [3:0] $end $var wire 1 ) reset $end $upscope $end $scope module c6_data $end $var wire 1 & valid $end $var wire 4 ' value [3:0] $end $var wire 1 * reset $end $upscope $end $scope module cif2 $end $upscope $end $scope module cif3 $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000001 # 0$ b0000 % 0& b0000 ' 0( 0) 0* #10 b00000000000000000000000000000010 # 1( #15 0( #20 b00000000000000000000000000000011 # b1111 % 1& b1010 ' 1( #25 0( #30 b00000000000000000000000000000100 # 1( #35 0( #40 b00000000000000000000000000000101 # 1( #45 0( #50 b00000000000000000000000000000110 # 1( #55 0( #60 b00000000000000000000000000000111 # 1( #65 0( #70 b00000000000000000000000000001000 # 1( #75 0( #80 b00000000000000000000000000001001 # 1( #85 0( #90 b00000000000000000000000000001010 # 1( #95 0( #100 b00000000000000000000000000001011 # 1( #105 0( #110 b00000000000000000000000000001100 # 1( #115 0( #120 b00000000000000000000000000001101 # 1( #125 0( #130 b00000000000000000000000000001110 # 1( #135 0( #140 b00000000000000000000000000001111 # 1( #145 0( #150 b00000000000000000000000000010000 # 1( #155 0( #160 b00000000000000000000000000010001 # 1( #165 0( #170 b00000000000000000000000000010010 # 1( #175 0( #180 b00000000000000000000000000010011 # 1( #185 0( #190 b00000000000000000000000000010100 # 1( #195 0( #200 b00000000000000000000000000010101 # 1( verilator-5.044/test_regress/t/t_cover_toggle_min.info.out0000644000542200017500000000041315125463617024427 0ustar mahmoudyfreeshellTN:verilator_coverage SF:t/t_cover_toggle_min.v DA:10,1 BRDA:10,0,0,1 BRDA:10,0,1,0 BRDA:10,0,2,0 BRDA:10,0,3,0 DA:11,1 BRDA:11,0,0,0 BRDA:11,0,1,0 BRDA:11,0,2,1 BRDA:11,0,3,0 DA:12,1 BRDA:12,0,0,1 BRDA:12,0,1,1 BRDA:12,0,2,1 BRDA:12,0,3,0 BRF:12 BRH:0 end_of_record verilator-5.044/test_regress/t/t_dpi_unpack_bad.py0000755000542200017500000000076615125463617022735 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_string_size.py0000755000542200017500000000100015125463617022330 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_interface_array3.v0000644000542200017500000000212015125463617023027 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface my_ifc (); logic sig; modport master ( output sig ); modport slave ( input sig ); endinterface package my_pkg; typedef virtual my_ifc my_vif; function void my_func; input my_vif in_vif; begin in_vif.sig = 1'b1; end endfunction endpackage module dut (input logic clk, my_ifc.slave sif[2]); generate genvar i; for (i=0; i<2; i++) begin always_ff @( posedge clk ) begin if (sif[i].sig == 1'b1) $display("Hello World %0d", i); end end endgenerate endmodule module t; import my_pkg::*; logic clk; my_ifc sif[2] (); dut DUT (.*); initial begin clk = 0; forever #(5) clk = ~clk; end initial begin repeat (4) @(posedge clk); my_func(sif[0]); my_func(sif[1]); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_xml_flat_pub_mod.v0000644000542200017500000000060715125463617023131 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module foo(input logic i_clk); /* verilator public_module */ endmodule // --flatten forces inlining of public module foo. module top(input logic i_clk); foo f(.*); endmodule verilator-5.044/test_regress/t/t_enum_func.py0000755000542200017500000000073415125463617021764 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_preproc_ifexpr.out0000644000542200017500000000065415125463617023211 0ustar mahmoudyfreeshell`begin_keywords "1800-2023" "ok ( ONE )" "ok ( ! ONE )" "ok ( ! ZERO )" "ok ( ZERO || ZERO || ONE )" "ok ( ONE && ONE && ONE )" "ok ( ZERO && ZERO || ONE )" "ok ( ZERO -> ZERO)" "ok ( ZERO -> ONE)" "ok ( ZERO -> ONE)" "ok ( ZERO -> ONE)" "ok ( ONE -> ZERO)" "ok ( ONE -> ONE)" "ok ( ZERO <-> ZERO)" "ok ( ZERO <-> ONE)" "ok ( ONE <-> ZERO)" "ok ( ONE <-> ONE)" "ok " Line: 117 verilator-5.044/test_regress/t/t_gate_loop.v0000644000542200017500000000046415125463617021570 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 module t; wire a; wire b; wire c; assign a = b; assign b = c; assign c = a; endmodule verilator-5.044/test_regress/t/t_randomize_inline_var_ctl_unsup_2.out0000644000542200017500000000123615125463617026672 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_randomize_inline_var_ctl_unsup_2.v:17:29: Unsupported: Inline random variable control with 'randomize()' called on complex expressions 17 | initial void'(Foo::get().randomize(x)); | ^~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: t/t_randomize_inline_var_ctl_unsup_2.v:17:39: Can't find definition of variable: 'x' 17 | initial void'(Foo::get().randomize(x)); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_enum_name_sformatf.v0000644000542200017500000000143415125463617023462 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Demonstrate struct literal param assignment problem // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module sub #(parameter int param_a, parameter bit [1:0] enum_param = '0) (); typedef enum logic [1:0] { FOO = enum_param, BAR, BAZ } enum_t; enum_t the_enum = enum_t'(1); initial $display("%s", the_enum.name()); endmodule module t (/*AUTOARG*/ // Inputs clk ); input clk; // finish report always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end sub #(.param_a(1)) the_sub1(); sub #(.param_a(2)) the_sub2(); sub #(.param_a(2), .enum_param(2'd1)) the_sub3(); endmodule verilator-5.044/test_regress/t/t_mem_first.py0000755000542200017500000000073415125463617021772 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_class_extern2.py0000755000542200017500000000073415125463617022561 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_class_super_new3.py0000755000542200017500000000073415125463617023264 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_class_param_override_local_bad.v0000644000542200017500000000120115125463617025751 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Cls1; parameter type T = int; endclass class Cls2; localparam int P = 0; endclass interface class Icls1; localparam LP1 = 1; endclass interface class Icls2; parameter LP1 = 1; endclass class Cls3 implements Icls1#(2), Icls2#(0); endclass module t; initial begin automatic Cls1#(bit) cls1 = new; automatic Cls2#(1) cls2 = new; automatic Cls3 cls3 = new; $stop; end endmodule verilator-5.044/test_regress/t/t_stream3.py0000755000542200017500000000073415125463617021363 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_stream2.v0000644000542200017500000000445315125463617021176 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [67:0] left; // From test of Test.v wire [67:0] right; // From test of Test.v // End of automatics wire [6:0] amt = crc[6:0]; wire [67:0] in = {crc[3:0], crc[63:0]}; Test test (/*AUTOINST*/ // Outputs .left (left[67:0]), .right (right[67:0]), // Inputs .amt (amt[6:0]), .in (in[67:0])); wire [63:0] result = (left[63:0] ^ {60'h0, left[67:64]} ^ right[63:0] ^ {60'h0, right[67:64]}); // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x amt=%x left=%x right=%x\n", $time, cyc, crc, result, amt, left, right); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h0da01049b480c38a if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs left, right, // Inputs amt, in ); input [6:0] amt; input [67:0] in; // amt must be constant output wire [67:0] left; output wire [67:0] right; assign right = { << 33 {in}}; assign left = { >> 33 {in}}; endmodule verilator-5.044/test_regress/t/t_inst_pin_realnreal.v0000644000542200017500000000276515125463617023475 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Peter Monsson. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; wire gain = 1'b0; real in; always_comb in = (cyc-4) * 1.0; wire cmp; adc_netlist netlist(.clk, .in, .gain, .cmp); always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; $display("cyc=%0d cmp=%d", cyc, cmp); if (cyc == 3) begin if (cmp != 0) $stop; end else if (cyc == 4) begin if (cmp != 1) $stop; end else if (cyc == 5) begin if (cmp != 0) $stop; end else if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module adc_netlist(clk, in, gain, cmp); input clk; input real in; input gain; output cmp; wire pga_out; //TODO: convert to real or support real pga_model pga0(.in, .gain, .out(pga_out)); comparator_model cmp0(.clk, .in(pga_out), .cmp); endmodule module pga_model(in, gain, out); input real in; input gain; output real out; always_comb begin out = in * 3.0; end endmodule module comparator_model(clk, in, cmp); input clk; input real in; output logic cmp; always_ff @(posedge clk) begin cmp <= in > 0.0; end endmodule verilator-5.044/test_regress/t/t_order.py0000755000542200017500000000107115125463617021113 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.main_time_multiplier = 1e-8 / 1e-9 test.compile(verilator_flags2=["--timescale 10ns/1ns --no-timing"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_stream_string_array.v0000644000542200017500000000116315125463617023673 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; string qs[$]; string as[]; string s; initial begin s = {>>{qs}}; if (s != "") $stop; s = {>>{as}}; if (s != "") $stop; qs = '{"ab", "c", ""}; s = {>>{qs}}; if (s != "abc") $stop; as = new[3]; as[0] = "abcd"; as[2] = "ef"; s = {>>{as}}; if (s != "abcdef") $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_final.v0000644000542200017500000000121515125463617020703 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Charlie Brej. // SPDX-License-Identifier: CC0-1.0 module submodule (); // This bug only appears when not inlining // verilator no_inline_module initial begin $write("d"); end final begin $write("d"); end final ; // Empty test endmodule module t (); generate for (genvar i = 0; i < 100; i = i + 1) begin : module_set submodule u_submodule(); end endgenerate initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_var_in_assign_pedantic.py0000755000542200017500000000130315125463617024467 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_var_in_assign_bad.v" # Although this is mostly a lint test, do 'compile' to make sure we do not # generate thrash code in the presence of a warning that is not fatal test.compile(verilator_flags2=['-Wpedantic -Wno-fatal --flatten -fno-gate']) test.passes() verilator-5.044/test_regress/t/t_struct_negate.v0000644000542200017500000000072215125463617022463 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input logic signed [64:0] i_x, output logic signed [64:0] o_y ); struct {logic signed [64:0] m_x;} s; assign s.m_x = i_x; assign o_y = -s.m_x; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_cover_line.vlt0000644000542200017500000000057415125463617022306 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config coverage_block_off -file "t/t_cover_line.v" -lines 145 coverage_block_off -file "t/t_cover_line.v" -lines 179 coverage_block_off -module "beta" -block "block" verilator-5.044/test_regress/t/t_class_super_new_noextend_bad.v0000644000542200017500000000046315125463617025524 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // class Cls; function new(); super.new(); // Bad - no extends endfunction endclass verilator-5.044/test_regress/t/t_constraint_struct_complex.v0000755000542200017500000004154515125463617025146 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by PlanV GmbH. // SPDX-License-Identifier: CC0-1.0 class ArrayStruct; /* verilator lint_off SIDEEFFECT */ // Struct with an unpacked array typedef int arr_3_t[3]; typedef int arr_4_t[4]; typedef struct { rand arr_3_t arr_3; arr_4_t arr_4; rand int arr[3]; } unpacked_struct_t; // Struct with a dynamic array typedef struct { rand int arr[]; } dynamic_struct_t; // Struct with a queue typedef struct { rand int arr[$]; } queue_struct_t; // Struct with an associative array (string as index) typedef struct { rand int arr[string]; } associative_struct_t; // Struct with a multi-dimensional array typedef struct { rand int arr[2][3]; } multi_dim_struct_t; // Struct with a mix of dynamic and unpacked arrays typedef struct { rand int mix_arr[3][]; } mixed_struct_t; rand unpacked_struct_t s1; rand dynamic_struct_t s2; rand queue_struct_t s3; rand associative_struct_t s4; rand multi_dim_struct_t s5; rand mixed_struct_t s6; constraint c_unpacked { foreach (s1.arr[i]) s1.arr[i] inside {1, 2, 3, 4}; foreach (s1.arr_3[i]) s1.arr_3[i] inside {11, 22, 33, 44, 55}; } constraint c_dynamic { foreach (s2.arr[i]) s2.arr[i] inside {[10:20]}; } constraint c_queue { foreach (s3.arr[i]) s3.arr[i] inside {[100:200]}; } constraint c_assoc { s4.arr["one"] inside {[10:50]}; s4.arr["two"] inside {[51:100]}; s4.arr["three"] inside {[101:150]}; } constraint c_multi_dim { foreach (s5.arr[i, j]) s5.arr[i][j] inside {[0:9]}; } constraint c_mix { foreach (s6.mix_arr[i, j]) s6.mix_arr[i][j] inside {[50:100]}; } function new(); s1.arr = '{1, 2, 3}; s1.arr_3 = '{1, 2, 3}; s1.arr_4 = '{0, 2, 3, 4}; s2.arr = new[3]; foreach(s2.arr[i]) begin s2.arr[i] = 'h0 + i; end s3.arr.push_back(100); s3.arr.push_back(200); s3.arr.push_back(300); s4.arr["one"] = 1000; s4.arr["two"] = 2000; s4.arr["three"] = 3000; s5.arr = '{ '{default:0}, '{default:0} }; foreach (s6.mix_arr[i]) begin s6.mix_arr[i] = new[i + 1]; end endfunction function void print(); foreach (s1.arr[i]) $display("s1.arr[%0d] = %0d", i, s1.arr[i]); foreach (s1.arr_3[i]) $display("s1.arr_3[%0d] = %0d", i, s1.arr_3[i]); foreach (s1.arr_4[i]) $display("s1.arr_4[%0d] = %0d", i, s1.arr_4[i]); foreach (s2.arr[i]) $display("s2.arr[%0d] = %0d", i, s2.arr[i]); foreach (s3.arr[i]) $display("s3.arr[%0d] = %0d", i, s3.arr[i]); foreach (s4.arr[i]) $display("s4.arr[\"%s\"] = %0d", i, s4.arr[i]); foreach (s5.arr[i, j]) $display("s5.arr[%0d][%0d] = %0d", i, j, s5.arr[i][j]); foreach (s6.mix_arr[i, j]) $display("s6.mix_arr[%0d][%0d] = %0d", i, j, s6.mix_arr[i][j]); endfunction // Self-test function to verify constraints function void self_test(); foreach (s1.arr[i]) if (!(s1.arr[i] inside {1, 2, 3, 4})) $stop; foreach (s1.arr_3[i]) if (!(s1.arr_3[i] inside {11, 22, 33, 44, 55})) $stop; // Note: s1.arr_4[0] is not rand if ((s1.arr_4[0] != 0) || (s1.arr_4[1] != 2) || (s1.arr_4[2] != 3) || (s1.arr_4[3] != 4)) $stop; foreach (s2.arr[i]) if (!(s2.arr[i] inside {[10:20]})) $stop; foreach (s3.arr[i]) if (!(s3.arr[i] inside {[100:200]})) $stop; if (!(s4.arr["one"] inside {[10:50]})) $stop; if (!(s4.arr["two"] inside {[51:100]})) $stop; if (!(s4.arr["three"] inside {[101:150]})) $stop; foreach (s5.arr[i, j]) if (!(s5.arr[i][j] inside {[0:9]})) $stop; foreach (s6.mix_arr[i]) if (s6.mix_arr[i].size() == 0) $stop; foreach (s6.mix_arr[i, j]) if (!(s6.mix_arr[i][j] inside {[50:100]})) $stop; endfunction /* verilator lint_off SIDEEFFECT */ endclass class StructArray; /* verilator lint_off WIDTHTRUNC */ typedef struct { rand int arr[3]; // static unpacked array rand int a; rand bit [3:0] b; bit c; } struct_t; rand struct_t s_arr[2]; rand struct_t s_2d_arr[2][3]; rand struct_t s_dyn_arr[]; rand struct_t s_que_arr[$]; rand struct_t s_assoc_arr[string]; rand struct_t s_assoc_arr_2[bit[5:0]]; constraint c_arr { foreach (s_arr[i]) foreach (s_arr[i].arr[j]) s_arr[i].arr[j] inside {[0:9]}; foreach (s_2d_arr[i, j]) foreach (s_2d_arr[i][j].arr[k]) s_2d_arr[i][j].arr[k] inside {[9:19]}; foreach (s_dyn_arr[i]) foreach (s_dyn_arr[i].arr[j]) s_dyn_arr[i].arr[j] inside {[19:29]}; foreach (s_que_arr[i]) foreach (s_que_arr[i].arr[j]) s_que_arr[i].arr[j] inside {[29:39]}; foreach (s_assoc_arr[i]) foreach (s_assoc_arr[i].arr[j]) s_assoc_arr[i].arr[j] inside {[39:49]}; foreach (s_assoc_arr_2[i]) foreach (s_assoc_arr_2[i].arr[j]) s_assoc_arr_2[i].arr[j] inside {[49:59]}; } constraint c_others { foreach (s_arr[i]) s_arr[i].a inside {[40:50]}; foreach (s_arr[i]) s_arr[i].b inside {[0:7]}; foreach (s_2d_arr[i, j]) s_2d_arr[i][j].a inside {[50:60]}; foreach (s_dyn_arr[i]) s_dyn_arr[i].a inside {[60:70]}; foreach (s_que_arr[i]) s_que_arr[i].a inside {[70:80]}; foreach (s_assoc_arr[i]) s_assoc_arr[i].a inside {[80:90]}; foreach (s_assoc_arr_2[i]) s_assoc_arr_2[i].a inside {[90:100]}; } function new(); foreach (s_arr[i]) begin foreach (s_arr[i].arr[j]) s_arr[i].arr[j] = j; s_arr[i].a = 40 + i; s_arr[i].b = i; s_arr[i].c = 0; end foreach (s_2d_arr[i, j]) begin foreach (s_2d_arr[i][j].arr[k]) s_2d_arr[i][j].arr[k] = k + 10; s_2d_arr[i][j].a = 50 + i + j; s_2d_arr[i][j].b = i + j; s_2d_arr[i][j].c = 0; end foreach (s_dyn_arr[i]) begin s_dyn_arr = new[3]; foreach (s_dyn_arr[i].arr[j]) s_dyn_arr[i].arr[j] = j + 20; s_dyn_arr[i].a = 60 + i; s_dyn_arr[i].b = i; s_dyn_arr[i].c = 0; end for (int i = 0; i < 3; i++) begin s_que_arr.push_back('{arr: '{30, 31, 32}, a: 70 + i, b: i, c: 0}); end // Associative array with string index foreach (s_assoc_arr["x"].arr[j]) s_assoc_arr["x"].arr[j] = j + 40; foreach (s_assoc_arr["y"].arr[j]) s_assoc_arr["y"].arr[j] = j + 50; foreach (s_assoc_arr["long_string_index"].arr[j]) s_assoc_arr["long_string_index"].arr[j] = j + 60; s_assoc_arr["x"].a = 80; s_assoc_arr["x"].b = 0; s_assoc_arr["x"].c = 0; s_assoc_arr["y"].a = 90; s_assoc_arr["y"].b = 1; s_assoc_arr["y"].c = 0; s_assoc_arr["long_string_index"].a = 100; s_assoc_arr["long_string_index"].b = 2; s_assoc_arr["long_string_index"].c = 0; foreach (s_assoc_arr_2[6'd30].arr[j]) s_assoc_arr_2[6'd30].arr[j] = j + 70; foreach (s_assoc_arr_2[6'd7].arr[j]) s_assoc_arr_2[6'd7].arr[j] = j + 80; s_assoc_arr_2[6'd30].a = 90; s_assoc_arr_2[6'd30].b = 0; s_assoc_arr_2[6'd30].c = 0; s_assoc_arr_2[6'd7].a = 100; s_assoc_arr_2[6'd7].b = 1; s_assoc_arr_2[6'd7].c = 0; endfunction function void print(); foreach (s_arr[i]) begin foreach (s_arr[i].arr[j]) $display("s_arr[%0d].arr[%0d] = %0d", i, j, s_arr[i].arr[j]); $display("s_arr[%0d].a = %0d", i, s_arr[i].a); $display("s_arr[%0d].b = %0d", i, s_arr[i].b); $display("s_arr[%0d].c = %0d", i, s_arr[i].c); end foreach (s_2d_arr[i, j]) begin foreach (s_2d_arr[i][j].arr[k]) $display("s_2d_arr[%0d][%0d].arr[%0d] = %0d", i, j, k, s_2d_arr[i][j].arr[k]); $display("s_2d_arr[%0d][%0d].a = %0d", i, j, s_2d_arr[i][j].a); $display("s_2d_arr[%0d][%0d].b = %0d", i, j, s_2d_arr[i][j].b); $display("s_2d_arr[%0d][%0d].c = %0d", i, j, s_2d_arr[i][j].c); end foreach (s_dyn_arr[i]) begin foreach (s_dyn_arr[i].arr[j]) $display("s_dyn_arr[%0d].arr[%0d] = %0d", i, j, s_dyn_arr[i].arr[j]); $display("s_dyn_arr[%0d].a = %0d", i, s_dyn_arr[i].a); $display("s_dyn_arr[%0d].b = %0d", i, s_dyn_arr[i].b); $display("s_dyn_arr[%0d].c = %0d", i, s_dyn_arr[i].c); end foreach (s_que_arr[i]) begin foreach (s_que_arr[i].arr[j]) $display("s_que_arr[%0d].arr[%0d] = %0d", i, j, s_que_arr[i].arr[j]); $display("s_que_arr[%0d].a = %0d", i, s_que_arr[i].a); $display("s_que_arr[%0d].b = %0d", i, s_que_arr[i].b); $display("s_que_arr[%0d].c = %0d", i, s_que_arr[i].c); end foreach (s_assoc_arr["x"].arr[j]) $display("s_assoc_arr[x].arr[%0d] = %0d", j, s_assoc_arr["x"].arr[j]); $display("s_assoc_arr[x].a = %0d", s_assoc_arr["x"].a); $display("s_assoc_arr[x].b = %0d", s_assoc_arr["x"].b); $display("s_assoc_arr[x].c = %0d", s_assoc_arr["x"].c); foreach (s_assoc_arr["y"].arr[j]) $display("s_assoc_arr[y].arr[%0d] = %0d", j, s_assoc_arr["y"].arr[j]); $display("s_assoc_arr[y].a = %0d", s_assoc_arr["y"].a); $display("s_assoc_arr[y].b = %0d", s_assoc_arr["y"].b); $display("s_assoc_arr[y].c = %0d", s_assoc_arr["y"].c); foreach (s_assoc_arr["long_string_index"].arr[j]) $display("s_assoc_arr[long_string_index].arr[%0d] = %0d", j, s_assoc_arr["long_string_index"].arr[j]); $display("s_assoc_arr[long_string_index].a = %0d", s_assoc_arr["long_string_index"].a); $display("s_assoc_arr[long_string_index].b = %0d", s_assoc_arr["long_string_index"].b); $display("s_assoc_arr[long_string_index].c = %0d", s_assoc_arr["long_string_index"].c); foreach (s_assoc_arr_2[6'd30].arr[j]) $display("s_assoc_arr_2[30].arr[%0d] = %0d", j, s_assoc_arr_2[6'd30].arr[j]); $display("s_assoc_arr_2[30].a = %0d", s_assoc_arr_2[6'd30].a); $display("s_assoc_arr_2[30].b = %0d", s_assoc_arr_2[6'd30].b); $display("s_assoc_arr_2[30].c = %0d", s_assoc_arr_2[6'd30].c); foreach (s_assoc_arr_2[6'd7].arr[j]) $display("s_assoc_arr_2[7].arr[%0d] = %0d", j, s_assoc_arr_2[6'd7].arr[j]); $display("s_assoc_arr_2[7].a = %0d", s_assoc_arr_2[6'd7].a); $display("s_assoc_arr_2[7].b = %0d", s_assoc_arr_2[6'd7].b); $display("s_assoc_arr_2[7].c = %0d", s_assoc_arr_2[6'd7].c); endfunction function void self_test(); foreach (s_arr[i]) begin foreach (s_arr[i].arr[j]) if (!(s_arr[i].arr[j] inside {[0:9]})) $stop; if (!(s_arr[i].a inside {[40:50]})) $stop; end foreach (s_2d_arr[i, j]) begin foreach (s_2d_arr[i][j].arr[k]) if (!(s_2d_arr[i][j].arr[k] inside {[9:19]})) $stop; if (!(s_2d_arr[i][j].a inside {[50:60]})) $stop; end foreach (s_dyn_arr[i]) begin foreach (s_dyn_arr[i].arr[j]) if (!(s_dyn_arr[i].arr[j] inside {[19:29]})) $stop; if (!(s_dyn_arr[i].a inside {[60:70]})) $stop; end foreach (s_que_arr[i]) begin foreach (s_que_arr[i].arr[j]) if (!(s_que_arr[i].arr[j] inside {[29:39]})) $stop; if (!(s_que_arr[i].a inside {[70:80]})) $stop; end foreach (s_assoc_arr["x"].arr[j]) if (!(s_assoc_arr["x"].arr[j] inside {[39:49]})) $stop; if (!(s_assoc_arr["x"].a inside {[80:90]})) $stop; foreach (s_assoc_arr["y"].arr[j]) if (!(s_assoc_arr["y"].arr[j] inside {[39:49]})) $stop; if (!(s_assoc_arr["y"].a inside {[80:90]})) $stop; foreach (s_assoc_arr["long_string_index"].arr[j]) if (!(s_assoc_arr["long_string_index"].arr[j] inside {[39:49]})) $stop; if (!(s_assoc_arr["long_string_index"].a inside {[80:90]})) $stop; foreach (s_assoc_arr_2[6'd30].arr[j]) if (!(s_assoc_arr_2[6'd30].arr[j] inside {[49:59]})) $stop; if (!(s_assoc_arr_2[6'd30].a inside {[90:100]})) $stop; foreach (s_assoc_arr_2[6'd7].arr[j]) if (!(s_assoc_arr_2[6'd7].arr[j] inside {[49:59]})) $stop; if (!(s_assoc_arr_2[6'd7].a inside {[90:100]})) $stop; endfunction /* verilator lint_off WIDTHTRUNC */ endclass class MixedStructure; /* verilator lint_off WIDTHTRUNC */ typedef struct { rand int arr[3]; // static unpacked array rand int dyn[]; // dynamic array rand int que[$]; // queue rand int assoc[string]; // associative array with string key rand int a; rand bit [3:0] b; bit c; } struct_t; rand struct_t s_arr[2]; constraint c_static { foreach (s_arr[i]) foreach (s_arr[i].arr[j]) s_arr[i].arr[j] inside {[0:9]}; } constraint c_dyn { foreach (s_arr[i]) foreach (s_arr[i].dyn[j]) s_arr[i].dyn[j] inside {[10:19]}; } constraint c_queue { foreach (s_arr[i]) foreach (s_arr[i].que[j]) s_arr[i].que[j] inside {[20:29]}; } constraint c_assoc { foreach (s_arr[i]) { s_arr[i].assoc["x"] inside {[30:39]}; s_arr[i].assoc["y"] inside {[30:39]}; } } constraint c_other { foreach (s_arr[i]) s_arr[i].a inside {[40:50]}; } function new(); foreach (s_arr[i]) begin s_arr[i].dyn = new[2]; s_arr[i].que = {0, 0}; s_arr[i].assoc = '{"x": 0, "y": 0}; foreach (s_arr[i].arr[j]) s_arr[i].arr[j] = j; foreach (s_arr[i].dyn[j]) s_arr[i].dyn[j] = 10 + j; foreach (s_arr[i].que[j]) s_arr[i].que[j] = 20 + j; s_arr[i].assoc["x"] = i + 30; s_arr[i].assoc["y"] = i + 31; s_arr[i].a = 40 + i; s_arr[i].b = i; s_arr[i].c = i; end endfunction function void print(); foreach (s_arr[i]) begin foreach (s_arr[i].arr[j]) $display("s_arr[%0d].arr[%0d] = %0d", i, j, s_arr[i].arr[j]); foreach (s_arr[i].dyn[j]) $display("s_arr[%0d].dyn[%0d] = %0d", i, j, s_arr[i].dyn[j]); foreach (s_arr[i].que[j]) $display("s_arr[%0d].que[%0d] = %0d", i, j, s_arr[i].que[j]); $display("s_arr[%0d].assoc[\"x\"] = %0d", i, s_arr[i].assoc["x"]); $display("s_arr[%0d].assoc[\"y\"] = %0d", i, s_arr[i].assoc["y"]); $display("s_arr[%0d].a = %0d", i, s_arr[i].a); $display("s_arr[%0d].b = %0d", i, s_arr[i].b); $display("s_arr[%0d].c = %0d", i, s_arr[i].c); end endfunction function void self_test(); foreach (s_arr[i]) begin foreach (s_arr[i].arr[j]) if (!(s_arr[i].arr[j] inside {[0:9]})) $stop; foreach (s_arr[i].dyn[j]) if (!(s_arr[i].dyn[j] inside {[10:19]})) $stop; foreach (s_arr[i].que[j]) if (!(s_arr[i].que[j] inside {[20:29]})) $stop; if (!(s_arr[i].assoc.exists("x") && s_arr[i].assoc["x"] inside {[30:39]})) $stop; if (!(s_arr[i].assoc.exists("y") && s_arr[i].assoc["y"] inside {[30:39]})) $stop; if (!(s_arr[i].a inside {[40:50]})) $stop; if (i == 0 && s_arr[i].c != 0) $stop; if (i == 1 && s_arr[i].c != 1) $stop; end endfunction /* verilator lint_off WIDTHTRUNC */ endclass module t_constraint_struct_complex; int success; ArrayStruct as_c; StructArray sa_c; MixedStructure mixed_c; initial begin as_c = new(); sa_c = new(); mixed_c = new(); success = as_c.randomize(); if (success != 1) $stop; as_c.self_test(); // as_c.print(); // $display(" ArrayStruct passed! \n"); success = sa_c.randomize(); if (success != 1) $stop; sa_c.self_test(); // sa_c.print(); // $display(" StructArray passed! \n"); success = mixed_c.randomize(); if (success != 1) $stop; mixed_c.self_test(); // mixed_c.print(); // $display(" MixedStructure passed! \n"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_force_bad_rw.py0000755000542200017500000000076315125463617022423 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_initial_edge_bad.py0000755000542200017500000000122315125463617023222 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # This works with other vlt_alls, we we don't run it for them. It should # fail with Verilator if --x-initial-edge is not specified. import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_initial_edge.v" test.compile() test.execute(fails=True) test.passes() verilator-5.044/test_regress/t/t_vlcov_merge.out0000644000542200017500000000046015125463617022465 0ustar mahmoudyfreeshell# SystemC::Coverage-3 C 'CoverPoint0ffile1.sphl159' 0 C 'CoverPoint1ffile1.sphl159' 1 C 'CoverPoint2ffile1.sphl159' 20 C 'CoverPoint3ffile1.sphl159' 0 C 'CoverPoint4ffile1.sphl159' 1 C 'CoverPoint5ffile1.sphl159' 9 C 'CoverPoint6ffile1.sphl159' 22 verilator-5.044/test_regress/t/t_class_param.py0000755000542200017500000000073415125463617022272 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_lparam_assign_iface_typedef_nested4.py0000755000542200017500000000077115125463617027123 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_timescale_parse_bad.v0000644000542200017500000000067115125463617023565 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // units < precision `timescale 1ps/1ns // Bad scale `timescale frump `timescale 1xs `timescale 2ps `timescale 1ns / frump `timescale 1ns / 1ps /extra module t; timeunit 2ps; // Bad timeprecision 2ps; // Bad endmodule verilator-5.044/test_regress/t/t_tri_public.py0000755000542200017500000000074115125463617022137 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() # Compile only test test.passes() verilator-5.044/test_regress/t/t_lint_ftask_output_assign_bad.py0000755000542200017500000000076315125463617025737 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_randomize_local_param.v0000644000542200017500000000131415125463617024134 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package Pkg; virtual class uvm_sequence #( type REQ = int ); REQ m_req; endclass endpackage package SubPkg; import Pkg::*; class s_trgt_txn; int m_txn_val; endclass class p_mem_seq extends uvm_sequence #(s_trgt_txn); rand bit m_wr_flag; virtual task body(); if (0 !== (m_req.randomize() with {local:: m_wr_flag;})) begin end endtask endclass endpackage module t; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_hier_block_sc_trace_vcd.out0000644000542200017500000142341115125463617024763 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $scope module t $end $var wire 32 {" PARAM_A [31:0] $end $var wire 32 |" PARAM_B [31:0] $end $var wire 1 z" clk $end $var wire 8 G" out0 [7:0] $end $var wire 8 H" out1 [7:0] $end $var wire 8 I" out2 [7:0] $end $var wire 8 C! out3 [7:0] $end $var wire 8 ' out3_2 [7:0] $end $var wire 8 ( out5 [7:0] $end $var wire 8 ) out6 [7:0] $end $var wire 32 * count [31:0] $end $scope module i_delay0 $end $var wire 32 }" N [31:0] $end $var wire 32 ~" WIDTH [31:0] $end $var wire 1 z" clk $end $var wire 8 C! in [7:0] $end $var wire 8 ( out [7:0] $end $var wire 8 + tmp [7:0] $end $scope module genblk1 $end $scope module i_delay $end $var wire 32 !# N [31:0] $end $var wire 32 ~" WIDTH [31:0] $end $var wire 1 z" clk $end $var wire 8 + in [7:0] $end $var wire 8 ( out [7:0] $end $var wire 8 ( tmp [7:0] $end $upscope $end $upscope $end $upscope $end $scope module i_delay1 $end $var wire 32 "# N [31:0] $end $var wire 32 ~" WIDTH [31:0] $end $var wire 1 z" clk $end $var wire 8 ( in [7:0] $end $var wire 8 ) out [7:0] $end $var wire 8 , tmp [7:0] $end $scope module genblk1 $end $scope module i_delay $end $var wire 32 }" N [31:0] $end $var wire 32 ~" WIDTH [31:0] $end $var wire 1 z" clk $end $var wire 8 , in [7:0] $end $var wire 8 ) out [7:0] $end $var wire 8 - tmp [7:0] $end $scope module genblk1 $end $scope module i_delay $end $var wire 32 !# N [31:0] $end $var wire 32 ~" WIDTH [31:0] $end $var wire 1 z" clk $end $var wire 8 - in [7:0] $end $var wire 8 ) out [7:0] $end $var wire 8 ) tmp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub0 $end $var wire 1 z" clk $end $var wire 8 C! in [7:0] $end $var wire 8 G" out [7:0] $end $scope module i_sub0 $end $var wire 1 z" clk $end $var wire 8 C! in [7:0] $end $var wire 8 G" out [7:0] $end $upscope $end $upscope $end $scope module i_sub1 $end $var wire 1 z" clk $end $var wire 8 G" in [11:4] $end $var wire 8 H" out [7:0] $end $upscope $end $scope module i_sub2 $end $var wire 1 z" clk $end $var wire 8 H" in [7:0] $end $var wire 8 I" out [7:0] $end $upscope $end $scope module i_sub3 $end $var wire 8 ## P0 [7:0] $end $var wire 32 $# UNPACKED_ARRAY[0] [31:0] $end $var wire 32 %# UNPACKED_ARRAY[1] [31:0] $end $var wire 16 &# UNUSED [15:0] $end $var wire 2 '# ENUM [1:0] $end $var wire 1 z" clk $end $var wire 8 I" in [7:0] $end $var wire 8 C! out [7:0] $end $var wire 8 D! ff [7:0] $end $var wire 8 C! out4 [7:0] $end $var wire 8 . out4_2 [7:0] $end $scope module i_sub4_0 $end $var wire 32 (# P0 [31:0] $end $var real 64 )# P1 $end $var real 64 +# P3 $end $var wire 1 z" clk $end $var wire 8 D! in [7:0] $end $var wire 8 C! out [7:0] $end $var wire 8 C! ff [7:0] $end $var wire 128 / sub5_in[0][0] [127:0] $end $var wire 128 3 sub5_in[0][1] [127:0] $end $var wire 128 7 sub5_in[0][2] [127:0] $end $var wire 128 ; sub5_in[1][0] [127:0] $end $var wire 128 ? sub5_in[1][1] [127:0] $end $var wire 128 C sub5_in[1][2] [127:0] $end $var wire 8 J" sub5_out[0][0] [7:0] $end $var wire 8 K" sub5_out[0][1] [7:0] $end $var wire 8 L" sub5_out[0][2] [7:0] $end $var wire 8 M" sub5_out[1][0] [7:0] $end $var wire 8 N" sub5_out[1][1] [7:0] $end $var wire 8 O" sub5_out[1][2] [7:0] $end $var wire 32 G count [31:0] $end $var wire 32 # driven_from_bind [31:0] $end $scope module i_sub4_bound $end $var real 64 )# P1 $end $var wire 32 # driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end $var wire 1 z" clk $end $var wire 128 E! in[0][0] [127:0] $end $var wire 128 I! in[0][1] [127:0] $end $var wire 128 M! in[0][2] [127:0] $end $var wire 128 Q! in[1][0] [127:0] $end $var wire 128 U! in[1][1] [127:0] $end $var wire 128 Y! in[1][2] [127:0] $end $var wire 8 P" out[0][0] [7:0] $end $var wire 8 Q" out[0][1] [7:0] $end $var wire 8 R" out[0][2] [7:0] $end $var wire 8 S" out[1][0] [7:0] $end $var wire 8 T" out[1][1] [7:0] $end $var wire 8 U" out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 H i [31:0] $end $scope module unnamedblk2 $end $var wire 32 I j [31:0] $end $scope module unnamedblk3 $end $var wire 8 J exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end $var wire 32 (# P0 [31:0] $end $var real 64 )# P1 $end $var real 64 -# P3 $end $var wire 1 z" clk $end $var wire 8 D! in [7:0] $end $var wire 8 . out [7:0] $end $var wire 8 . ff [7:0] $end $var wire 128 K sub5_in[0][0] [127:0] $end $var wire 128 O sub5_in[0][1] [127:0] $end $var wire 128 S sub5_in[0][2] [127:0] $end $var wire 128 W sub5_in[1][0] [127:0] $end $var wire 128 [ sub5_in[1][1] [127:0] $end $var wire 128 _ sub5_in[1][2] [127:0] $end $var wire 8 V" sub5_out[0][0] [7:0] $end $var wire 8 W" sub5_out[0][1] [7:0] $end $var wire 8 X" sub5_out[0][2] [7:0] $end $var wire 8 Y" sub5_out[1][0] [7:0] $end $var wire 8 Z" sub5_out[1][1] [7:0] $end $var wire 8 [" sub5_out[1][2] [7:0] $end $var wire 32 c count [31:0] $end $var wire 32 $ driven_from_bind [31:0] $end $scope module i_sub4_bound $end $var real 64 )# P1 $end $var wire 32 $ driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end $var wire 1 z" clk $end $var wire 128 ]! in[0][0] [127:0] $end $var wire 128 a! in[0][1] [127:0] $end $var wire 128 e! in[0][2] [127:0] $end $var wire 128 i! in[1][0] [127:0] $end $var wire 128 m! in[1][1] [127:0] $end $var wire 128 q! in[1][2] [127:0] $end $var wire 8 \" out[0][0] [7:0] $end $var wire 8 ]" out[0][1] [7:0] $end $var wire 8 ^" out[0][2] [7:0] $end $var wire 8 _" out[1][0] [7:0] $end $var wire 8 `" out[1][1] [7:0] $end $var wire 8 a" out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 d i [31:0] $end $scope module unnamedblk2 $end $var wire 32 e j [31:0] $end $scope module unnamedblk3 $end $var wire 8 f exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub3_2 $end $var wire 8 ## P0 [7:0] $end $var wire 32 /# UNPACKED_ARRAY[0] [31:0] $end $var wire 32 0# UNPACKED_ARRAY[1] [31:0] $end $var wire 16 &# UNUSED [15:0] $end $var wire 2 '# ENUM [1:0] $end $var wire 1 z" clk $end $var wire 8 I" in [7:0] $end $var wire 8 ' out [7:0] $end $var wire 8 g ff [7:0] $end $var wire 8 ' out4 [7:0] $end $var wire 8 h out4_2 [7:0] $end $scope module i_sub4_0 $end $var wire 32 (# P0 [31:0] $end $var real 64 )# P1 $end $var real 64 +# P3 $end $var wire 1 z" clk $end $var wire 8 g in [7:0] $end $var wire 8 ' out [7:0] $end $var wire 8 ' ff [7:0] $end $var wire 128 i sub5_in[0][0] [127:0] $end $var wire 128 m sub5_in[0][1] [127:0] $end $var wire 128 q sub5_in[0][2] [127:0] $end $var wire 128 u sub5_in[1][0] [127:0] $end $var wire 128 y sub5_in[1][1] [127:0] $end $var wire 128 } sub5_in[1][2] [127:0] $end $var wire 8 b" sub5_out[0][0] [7:0] $end $var wire 8 c" sub5_out[0][1] [7:0] $end $var wire 8 d" sub5_out[0][2] [7:0] $end $var wire 8 e" sub5_out[1][0] [7:0] $end $var wire 8 f" sub5_out[1][1] [7:0] $end $var wire 8 g" sub5_out[1][2] [7:0] $end $var wire 32 #! count [31:0] $end $var wire 32 % driven_from_bind [31:0] $end $scope module i_sub4_bound $end $var real 64 )# P1 $end $var wire 32 % driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end $var wire 1 z" clk $end $var wire 128 u! in[0][0] [127:0] $end $var wire 128 y! in[0][1] [127:0] $end $var wire 128 }! in[0][2] [127:0] $end $var wire 128 #" in[1][0] [127:0] $end $var wire 128 '" in[1][1] [127:0] $end $var wire 128 +" in[1][2] [127:0] $end $var wire 8 h" out[0][0] [7:0] $end $var wire 8 i" out[0][1] [7:0] $end $var wire 8 j" out[0][2] [7:0] $end $var wire 8 k" out[1][0] [7:0] $end $var wire 8 l" out[1][1] [7:0] $end $var wire 8 m" out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 $! i [31:0] $end $scope module unnamedblk2 $end $var wire 32 %! j [31:0] $end $scope module unnamedblk3 $end $var wire 8 &! exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end $var wire 32 (# P0 [31:0] $end $var real 64 )# P1 $end $var real 64 -# P3 $end $var wire 1 z" clk $end $var wire 8 g in [7:0] $end $var wire 8 h out [7:0] $end $var wire 8 h ff [7:0] $end $var wire 128 '! sub5_in[0][0] [127:0] $end $var wire 128 +! sub5_in[0][1] [127:0] $end $var wire 128 /! sub5_in[0][2] [127:0] $end $var wire 128 3! sub5_in[1][0] [127:0] $end $var wire 128 7! sub5_in[1][1] [127:0] $end $var wire 128 ;! sub5_in[1][2] [127:0] $end $var wire 8 n" sub5_out[0][0] [7:0] $end $var wire 8 o" sub5_out[0][1] [7:0] $end $var wire 8 p" sub5_out[0][2] [7:0] $end $var wire 8 q" sub5_out[1][0] [7:0] $end $var wire 8 r" sub5_out[1][1] [7:0] $end $var wire 8 s" sub5_out[1][2] [7:0] $end $var wire 32 ?! count [31:0] $end $var wire 32 & driven_from_bind [31:0] $end $scope module i_sub4_bound $end $var real 64 )# P1 $end $var wire 32 & driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end $var wire 1 z" clk $end $var wire 128 /" in[0][0] [127:0] $end $var wire 128 3" in[0][1] [127:0] $end $var wire 128 7" in[0][2] [127:0] $end $var wire 128 ;" in[1][0] [127:0] $end $var wire 128 ?" in[1][1] [127:0] $end $var wire 128 C" in[1][2] [127:0] $end $var wire 8 t" out[0][0] [7:0] $end $var wire 8 u" out[0][1] [7:0] $end $var wire 8 v" out[0][2] [7:0] $end $var wire 8 w" out[1][0] [7:0] $end $var wire 8 x" out[1][1] [7:0] $end $var wire 8 y" out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 @! i [31:0] $end $scope module unnamedblk2 $end $var wire 32 A! j [31:0] $end $scope module unnamedblk3 $end $var wire 8 B! exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub0.i_sub0 $end $var wire 1 2# clk $end $var wire 8 3# in [7:0] $end $var wire 8 4# out [7:0] $end $scope module sub0 $end $var wire 1 2# clk $end $var wire 8 3# in [7:0] $end $var wire 8 4# out [7:0] $end $var wire 8 5# ff [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub1 $end $var wire 1 7# clk $end $var wire 8 8# in [11:4] $end $var wire 8 9# out [7:0] $end $scope module sub1 $end $var wire 1 7# clk $end $var wire 8 8# in [11:4] $end $var wire 8 9# out [7:0] $end $var wire 8 :# ff [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub2 $end $var wire 1 +' clk $end $var wire 8 ,' in [7:0] $end $var wire 8 -' out [7:0] $end $scope module sub2 $end $var wire 1 +' clk $end $var wire 8 ,' in [7:0] $end $var wire 8 -' out [7:0] $end $var wire 8 "$ ff [7:0] $end $scope module in_ifs $end $var wire 1 +' clk $end $var wire 8 "$ data [7:0] $end $upscope $end $scope module out_ifs $end $var wire 1 +' clk $end $var wire 8 #$ data [7:0] $end $upscope $end $scope module i_sub3 $end $scope module in $end $var wire 1 +' clk $end $var wire 8 "$ data [7:0] $end $upscope $end $scope module out $end $var wire 1 +' clk $end $var wire 8 #$ data [7:0] $end $upscope $end $var wire 8 "$ in_wire [7:0] $end $var wire 8 #$ out_1 [7:0] $end $var wire 8 $$ out_2 [7:0] $end $scope module i_sub3 $end $var wire 8 .' P0 [7:0] $end $var wire 32 /' UNPACKED_ARRAY[0] [31:0] $end $var wire 32 0' UNPACKED_ARRAY[1] [31:0] $end $var wire 16 1' UNUSED [15:0] $end $var wire 2 2' ENUM [1:0] $end $var wire 1 +' clk $end $var wire 8 "$ in [7:0] $end $var wire 8 #$ out [7:0] $end $var wire 8 %$ ff [7:0] $end $var wire 8 #$ out4 [7:0] $end $var wire 8 &$ out4_2 [7:0] $end $scope module i_sub4_0 $end $var wire 32 3' P0 [31:0] $end $var real 64 4' P1 $end $var real 64 6' P3 $end $var wire 1 +' clk $end $var wire 8 %$ in [7:0] $end $var wire 8 #$ out [7:0] $end $var wire 8 #$ ff [7:0] $end $var wire 128 '$ sub5_in[0][0] [127:0] $end $var wire 128 +$ sub5_in[0][1] [127:0] $end $var wire 128 /$ sub5_in[0][2] [127:0] $end $var wire 128 3$ sub5_in[1][0] [127:0] $end $var wire 128 7$ sub5_in[1][1] [127:0] $end $var wire 128 ;$ sub5_in[1][2] [127:0] $end $var wire 8 ?$ sub5_out[0][0] [7:0] $end $var wire 8 @$ sub5_out[0][1] [7:0] $end $var wire 8 A$ sub5_out[0][2] [7:0] $end $var wire 8 B$ sub5_out[1][0] [7:0] $end $var wire 8 C$ sub5_out[1][1] [7:0] $end $var wire 8 D$ sub5_out[1][2] [7:0] $end $var wire 32 E$ count [31:0] $end $var wire 32 <# driven_from_bind [31:0] $end $scope module i_sub4_bound $end $var real 64 4' P1 $end $var wire 32 <# driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end $var wire 1 +' clk $end $var wire 128 F$ in[0][0] [127:0] $end $var wire 128 J$ in[0][1] [127:0] $end $var wire 128 N$ in[0][2] [127:0] $end $var wire 128 R$ in[1][0] [127:0] $end $var wire 128 V$ in[1][1] [127:0] $end $var wire 128 Z$ in[1][2] [127:0] $end $var wire 8 ^$ out[0][0] [7:0] $end $var wire 8 _$ out[0][1] [7:0] $end $var wire 8 `$ out[0][2] [7:0] $end $var wire 8 a$ out[1][0] [7:0] $end $var wire 8 b$ out[1][1] [7:0] $end $var wire 8 c$ out[1][2] [7:0] $end $var wire 32 d$ count [31:0] $end $var wire 8 =# val0[0] [7:0] $end $var wire 8 ># val0[1] [7:0] $end $var wire 8 ?# val1[0] [7:0] $end $var wire 8 @# val1[1] [7:0] $end $var wire 8 A# val2[0] [7:0] $end $var wire 8 B# val2[1] [7:0] $end $var wire 8 C# val3[0] [7:0] $end $var wire 8 D# val3[1] [7:0] $end $scope module i_sub0 $end $var wire 32 8' P0 [31:0] $end $var wire 32 9' P1 [31:0] $end $var wire 8 E# out[0] [7:0] $end $var wire 8 F# out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var wire 32 8' P0 [31:0] $end $var wire 32 9' P1 [31:0] $end $var wire 8 G# out[0] [7:0] $end $var wire 8 H# out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var wire 32 8' P0 [31:0] $end $var wire 32 9' P1 [31:0] $end $var wire 8 I# out[0] [7:0] $end $var wire 8 J# out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var wire 32 8' P0 [31:0] $end $var wire 32 :' P1 [31:0] $end $var wire 8 K# out[0] [7:0] $end $var wire 8 L# out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 e$ i [31:0] $end $scope module unnamedblk2 $end $var wire 32 f$ j [31:0] $end $scope module unnamedblk3 $end $var wire 128 g$ exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module unnamedblk1 $end $var wire 32 k$ i [31:0] $end $scope module unnamedblk2 $end $var wire 32 l$ j [31:0] $end $scope module unnamedblk3 $end $var wire 8 m$ exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end $var wire 32 3' P0 [31:0] $end $var real 64 4' P1 $end $var real 64 ;' P3 $end $var wire 1 +' clk $end $var wire 8 %$ in [7:0] $end $var wire 8 &$ out [7:0] $end $var wire 8 &$ ff [7:0] $end $var wire 128 n$ sub5_in[0][0] [127:0] $end $var wire 128 r$ sub5_in[0][1] [127:0] $end $var wire 128 v$ sub5_in[0][2] [127:0] $end $var wire 128 z$ sub5_in[1][0] [127:0] $end $var wire 128 ~$ sub5_in[1][1] [127:0] $end $var wire 128 $% sub5_in[1][2] [127:0] $end $var wire 8 (% sub5_out[0][0] [7:0] $end $var wire 8 )% sub5_out[0][1] [7:0] $end $var wire 8 *% sub5_out[0][2] [7:0] $end $var wire 8 +% sub5_out[1][0] [7:0] $end $var wire 8 ,% sub5_out[1][1] [7:0] $end $var wire 8 -% sub5_out[1][2] [7:0] $end $var wire 32 .% count [31:0] $end $var wire 32 M# driven_from_bind [31:0] $end $scope module i_sub4_bound $end $var real 64 4' P1 $end $var wire 32 M# driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end $var wire 1 +' clk $end $var wire 128 /% in[0][0] [127:0] $end $var wire 128 3% in[0][1] [127:0] $end $var wire 128 7% in[0][2] [127:0] $end $var wire 128 ;% in[1][0] [127:0] $end $var wire 128 ?% in[1][1] [127:0] $end $var wire 128 C% in[1][2] [127:0] $end $var wire 8 G% out[0][0] [7:0] $end $var wire 8 H% out[0][1] [7:0] $end $var wire 8 I% out[0][2] [7:0] $end $var wire 8 J% out[1][0] [7:0] $end $var wire 8 K% out[1][1] [7:0] $end $var wire 8 L% out[1][2] [7:0] $end $var wire 32 M% count [31:0] $end $var wire 8 N# val0[0] [7:0] $end $var wire 8 O# val0[1] [7:0] $end $var wire 8 P# val1[0] [7:0] $end $var wire 8 Q# val1[1] [7:0] $end $var wire 8 R# val2[0] [7:0] $end $var wire 8 S# val2[1] [7:0] $end $var wire 8 T# val3[0] [7:0] $end $var wire 8 U# val3[1] [7:0] $end $scope module i_sub0 $end $var wire 32 8' P0 [31:0] $end $var wire 32 9' P1 [31:0] $end $var wire 8 V# out[0] [7:0] $end $var wire 8 W# out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var wire 32 8' P0 [31:0] $end $var wire 32 9' P1 [31:0] $end $var wire 8 X# out[0] [7:0] $end $var wire 8 Y# out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var wire 32 8' P0 [31:0] $end $var wire 32 9' P1 [31:0] $end $var wire 8 Z# out[0] [7:0] $end $var wire 8 [# out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var wire 32 8' P0 [31:0] $end $var wire 32 :' P1 [31:0] $end $var wire 8 \# out[0] [7:0] $end $var wire 8 ]# out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 N% i [31:0] $end $scope module unnamedblk2 $end $var wire 32 O% j [31:0] $end $scope module unnamedblk3 $end $var wire 128 P% exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module unnamedblk1 $end $var wire 32 T% i [31:0] $end $scope module unnamedblk2 $end $var wire 32 U% j [31:0] $end $scope module unnamedblk3 $end $var wire 8 V% exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub3_2 $end $var wire 8 .' P0 [7:0] $end $var wire 32 =' UNPACKED_ARRAY[0] [31:0] $end $var wire 32 >' UNPACKED_ARRAY[1] [31:0] $end $var wire 16 1' UNUSED [15:0] $end $var wire 2 2' ENUM [1:0] $end $var wire 1 +' clk $end $var wire 8 "$ in [7:0] $end $var wire 8 $$ out [7:0] $end $var wire 8 W% ff [7:0] $end $var wire 8 $$ out4 [7:0] $end $var wire 8 X% out4_2 [7:0] $end $scope module i_sub4_0 $end $var wire 32 3' P0 [31:0] $end $var real 64 4' P1 $end $var real 64 6' P3 $end $var wire 1 +' clk $end $var wire 8 W% in [7:0] $end $var wire 8 $$ out [7:0] $end $var wire 8 $$ ff [7:0] $end $var wire 128 Y% sub5_in[0][0] [127:0] $end $var wire 128 ]% sub5_in[0][1] [127:0] $end $var wire 128 a% sub5_in[0][2] [127:0] $end $var wire 128 e% sub5_in[1][0] [127:0] $end $var wire 128 i% sub5_in[1][1] [127:0] $end $var wire 128 m% sub5_in[1][2] [127:0] $end $var wire 8 q% sub5_out[0][0] [7:0] $end $var wire 8 r% sub5_out[0][1] [7:0] $end $var wire 8 s% sub5_out[0][2] [7:0] $end $var wire 8 t% sub5_out[1][0] [7:0] $end $var wire 8 u% sub5_out[1][1] [7:0] $end $var wire 8 v% sub5_out[1][2] [7:0] $end $var wire 32 w% count [31:0] $end $var wire 32 ^# driven_from_bind [31:0] $end $scope module i_sub4_bound $end $var real 64 4' P1 $end $var wire 32 ^# driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end $var wire 1 +' clk $end $var wire 128 x% in[0][0] [127:0] $end $var wire 128 |% in[0][1] [127:0] $end $var wire 128 "& in[0][2] [127:0] $end $var wire 128 && in[1][0] [127:0] $end $var wire 128 *& in[1][1] [127:0] $end $var wire 128 .& in[1][2] [127:0] $end $var wire 8 2& out[0][0] [7:0] $end $var wire 8 3& out[0][1] [7:0] $end $var wire 8 4& out[0][2] [7:0] $end $var wire 8 5& out[1][0] [7:0] $end $var wire 8 6& out[1][1] [7:0] $end $var wire 8 7& out[1][2] [7:0] $end $var wire 32 8& count [31:0] $end $var wire 8 _# val0[0] [7:0] $end $var wire 8 `# val0[1] [7:0] $end $var wire 8 a# val1[0] [7:0] $end $var wire 8 b# val1[1] [7:0] $end $var wire 8 c# val2[0] [7:0] $end $var wire 8 d# val2[1] [7:0] $end $var wire 8 e# val3[0] [7:0] $end $var wire 8 f# val3[1] [7:0] $end $scope module i_sub0 $end $var wire 32 8' P0 [31:0] $end $var wire 32 9' P1 [31:0] $end $var wire 8 g# out[0] [7:0] $end $var wire 8 h# out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var wire 32 8' P0 [31:0] $end $var wire 32 9' P1 [31:0] $end $var wire 8 i# out[0] [7:0] $end $var wire 8 j# out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var wire 32 8' P0 [31:0] $end $var wire 32 9' P1 [31:0] $end $var wire 8 k# out[0] [7:0] $end $var wire 8 l# out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var wire 32 8' P0 [31:0] $end $var wire 32 :' P1 [31:0] $end $var wire 8 m# out[0] [7:0] $end $var wire 8 n# out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 9& i [31:0] $end $scope module unnamedblk2 $end $var wire 32 :& j [31:0] $end $scope module unnamedblk3 $end $var wire 128 ;& exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module unnamedblk1 $end $var wire 32 ?& i [31:0] $end $scope module unnamedblk2 $end $var wire 32 @& j [31:0] $end $scope module unnamedblk3 $end $var wire 8 A& exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end $var wire 32 3' P0 [31:0] $end $var real 64 4' P1 $end $var real 64 ;' P3 $end $var wire 1 +' clk $end $var wire 8 W% in [7:0] $end $var wire 8 X% out [7:0] $end $var wire 8 X% ff [7:0] $end $var wire 128 B& sub5_in[0][0] [127:0] $end $var wire 128 F& sub5_in[0][1] [127:0] $end $var wire 128 J& sub5_in[0][2] [127:0] $end $var wire 128 N& sub5_in[1][0] [127:0] $end $var wire 128 R& sub5_in[1][1] [127:0] $end $var wire 128 V& sub5_in[1][2] [127:0] $end $var wire 8 Z& sub5_out[0][0] [7:0] $end $var wire 8 [& sub5_out[0][1] [7:0] $end $var wire 8 \& sub5_out[0][2] [7:0] $end $var wire 8 ]& sub5_out[1][0] [7:0] $end $var wire 8 ^& sub5_out[1][1] [7:0] $end $var wire 8 _& sub5_out[1][2] [7:0] $end $var wire 32 `& count [31:0] $end $var wire 32 o# driven_from_bind [31:0] $end $scope module i_sub4_bound $end $var real 64 4' P1 $end $var wire 32 o# driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end $var wire 1 +' clk $end $var wire 128 a& in[0][0] [127:0] $end $var wire 128 e& in[0][1] [127:0] $end $var wire 128 i& in[0][2] [127:0] $end $var wire 128 m& in[1][0] [127:0] $end $var wire 128 q& in[1][1] [127:0] $end $var wire 128 u& in[1][2] [127:0] $end $var wire 8 y& out[0][0] [7:0] $end $var wire 8 z& out[0][1] [7:0] $end $var wire 8 {& out[0][2] [7:0] $end $var wire 8 |& out[1][0] [7:0] $end $var wire 8 }& out[1][1] [7:0] $end $var wire 8 ~& out[1][2] [7:0] $end $var wire 32 !' count [31:0] $end $var wire 8 p# val0[0] [7:0] $end $var wire 8 q# val0[1] [7:0] $end $var wire 8 r# val1[0] [7:0] $end $var wire 8 s# val1[1] [7:0] $end $var wire 8 t# val2[0] [7:0] $end $var wire 8 u# val2[1] [7:0] $end $var wire 8 v# val3[0] [7:0] $end $var wire 8 w# val3[1] [7:0] $end $scope module i_sub0 $end $var wire 32 8' P0 [31:0] $end $var wire 32 9' P1 [31:0] $end $var wire 8 x# out[0] [7:0] $end $var wire 8 y# out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var wire 32 8' P0 [31:0] $end $var wire 32 9' P1 [31:0] $end $var wire 8 z# out[0] [7:0] $end $var wire 8 {# out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var wire 32 8' P0 [31:0] $end $var wire 32 9' P1 [31:0] $end $var wire 8 |# out[0] [7:0] $end $var wire 8 }# out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var wire 32 8' P0 [31:0] $end $var wire 32 :' P1 [31:0] $end $var wire 8 ~# out[0] [7:0] $end $var wire 8 !$ out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 "' i [31:0] $end $scope module unnamedblk2 $end $var wire 32 #' j [31:0] $end $scope module unnamedblk3 $end $var wire 128 $' exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module unnamedblk1 $end $var wire 32 (' i [31:0] $end $scope module unnamedblk2 $end $var wire 32 )' j [31:0] $end $scope module unnamedblk3 $end $var wire 8 *' exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3.i_sub4_0.i_sub5 $end $var wire 1 u' clk $end $var wire 128 v' in[0][0] [127:0] $end $var wire 128 z' in[0][1] [127:0] $end $var wire 128 ~' in[0][2] [127:0] $end $var wire 128 $( in[1][0] [127:0] $end $var wire 128 (( in[1][1] [127:0] $end $var wire 128 ,( in[1][2] [127:0] $end $var wire 8 0( out[0][0] [7:0] $end $var wire 8 1( out[0][1] [7:0] $end $var wire 8 2( out[0][2] [7:0] $end $var wire 8 3( out[1][0] [7:0] $end $var wire 8 4( out[1][1] [7:0] $end $var wire 8 5( out[1][2] [7:0] $end $scope module sub5 $end $var wire 1 u' clk $end $var wire 128 P' in[0][0] [127:0] $end $var wire 128 T' in[0][1] [127:0] $end $var wire 128 X' in[0][2] [127:0] $end $var wire 128 \' in[1][0] [127:0] $end $var wire 128 `' in[1][1] [127:0] $end $var wire 128 d' in[1][2] [127:0] $end $var wire 8 h' out[0][0] [7:0] $end $var wire 8 i' out[0][1] [7:0] $end $var wire 8 j' out[0][2] [7:0] $end $var wire 8 k' out[1][0] [7:0] $end $var wire 8 l' out[1][1] [7:0] $end $var wire 8 m' out[1][2] [7:0] $end $var wire 32 n' count [31:0] $end $var wire 8 @' val0[0] [7:0] $end $var wire 8 A' val0[1] [7:0] $end $var wire 8 B' val1[0] [7:0] $end $var wire 8 C' val1[1] [7:0] $end $var wire 8 D' val2[0] [7:0] $end $var wire 8 E' val2[1] [7:0] $end $var wire 8 F' val3[0] [7:0] $end $var wire 8 G' val3[1] [7:0] $end $scope module i_sub0 $end $var wire 32 6( P0 [31:0] $end $var wire 32 7( P1 [31:0] $end $var wire 8 H' out[0] [7:0] $end $var wire 8 I' out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var wire 32 6( P0 [31:0] $end $var wire 32 7( P1 [31:0] $end $var wire 8 J' out[0] [7:0] $end $var wire 8 K' out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var wire 32 6( P0 [31:0] $end $var wire 32 7( P1 [31:0] $end $var wire 8 L' out[0] [7:0] $end $var wire 8 M' out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var wire 32 6( P0 [31:0] $end $var wire 32 8( P1 [31:0] $end $var wire 8 N' out[0] [7:0] $end $var wire 8 O' out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 o' i [31:0] $end $scope module unnamedblk2 $end $var wire 32 p' j [31:0] $end $scope module unnamedblk3 $end $var wire 128 q' exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3.i_sub4_1.i_sub5 $end $var wire 1 o( clk $end $var wire 128 p( in[0][0] [127:0] $end $var wire 128 t( in[0][1] [127:0] $end $var wire 128 x( in[0][2] [127:0] $end $var wire 128 |( in[1][0] [127:0] $end $var wire 128 ") in[1][1] [127:0] $end $var wire 128 &) in[1][2] [127:0] $end $var wire 8 *) out[0][0] [7:0] $end $var wire 8 +) out[0][1] [7:0] $end $var wire 8 ,) out[0][2] [7:0] $end $var wire 8 -) out[1][0] [7:0] $end $var wire 8 .) out[1][1] [7:0] $end $var wire 8 /) out[1][2] [7:0] $end $scope module sub5 $end $var wire 1 o( clk $end $var wire 128 J( in[0][0] [127:0] $end $var wire 128 N( in[0][1] [127:0] $end $var wire 128 R( in[0][2] [127:0] $end $var wire 128 V( in[1][0] [127:0] $end $var wire 128 Z( in[1][1] [127:0] $end $var wire 128 ^( in[1][2] [127:0] $end $var wire 8 b( out[0][0] [7:0] $end $var wire 8 c( out[0][1] [7:0] $end $var wire 8 d( out[0][2] [7:0] $end $var wire 8 e( out[1][0] [7:0] $end $var wire 8 f( out[1][1] [7:0] $end $var wire 8 g( out[1][2] [7:0] $end $var wire 32 h( count [31:0] $end $var wire 8 :( val0[0] [7:0] $end $var wire 8 ;( val0[1] [7:0] $end $var wire 8 <( val1[0] [7:0] $end $var wire 8 =( val1[1] [7:0] $end $var wire 8 >( val2[0] [7:0] $end $var wire 8 ?( val2[1] [7:0] $end $var wire 8 @( val3[0] [7:0] $end $var wire 8 A( val3[1] [7:0] $end $scope module i_sub0 $end $var wire 32 0) P0 [31:0] $end $var wire 32 1) P1 [31:0] $end $var wire 8 B( out[0] [7:0] $end $var wire 8 C( out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var wire 32 0) P0 [31:0] $end $var wire 32 1) P1 [31:0] $end $var wire 8 D( out[0] [7:0] $end $var wire 8 E( out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var wire 32 0) P0 [31:0] $end $var wire 32 1) P1 [31:0] $end $var wire 8 F( out[0] [7:0] $end $var wire 8 G( out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var wire 32 0) P0 [31:0] $end $var wire 32 2) P1 [31:0] $end $var wire 8 H( out[0] [7:0] $end $var wire 8 I( out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 i( i [31:0] $end $scope module unnamedblk2 $end $var wire 32 j( j [31:0] $end $scope module unnamedblk3 $end $var wire 128 k( exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3_2.i_sub4_0.i_sub5 $end $var wire 1 i) clk $end $var wire 128 j) in[0][0] [127:0] $end $var wire 128 n) in[0][1] [127:0] $end $var wire 128 r) in[0][2] [127:0] $end $var wire 128 v) in[1][0] [127:0] $end $var wire 128 z) in[1][1] [127:0] $end $var wire 128 ~) in[1][2] [127:0] $end $var wire 8 $* out[0][0] [7:0] $end $var wire 8 %* out[0][1] [7:0] $end $var wire 8 &* out[0][2] [7:0] $end $var wire 8 '* out[1][0] [7:0] $end $var wire 8 (* out[1][1] [7:0] $end $var wire 8 )* out[1][2] [7:0] $end $scope module sub5 $end $var wire 1 i) clk $end $var wire 128 D) in[0][0] [127:0] $end $var wire 128 H) in[0][1] [127:0] $end $var wire 128 L) in[0][2] [127:0] $end $var wire 128 P) in[1][0] [127:0] $end $var wire 128 T) in[1][1] [127:0] $end $var wire 128 X) in[1][2] [127:0] $end $var wire 8 \) out[0][0] [7:0] $end $var wire 8 ]) out[0][1] [7:0] $end $var wire 8 ^) out[0][2] [7:0] $end $var wire 8 _) out[1][0] [7:0] $end $var wire 8 `) out[1][1] [7:0] $end $var wire 8 a) out[1][2] [7:0] $end $var wire 32 b) count [31:0] $end $var wire 8 4) val0[0] [7:0] $end $var wire 8 5) val0[1] [7:0] $end $var wire 8 6) val1[0] [7:0] $end $var wire 8 7) val1[1] [7:0] $end $var wire 8 8) val2[0] [7:0] $end $var wire 8 9) val2[1] [7:0] $end $var wire 8 :) val3[0] [7:0] $end $var wire 8 ;) val3[1] [7:0] $end $scope module i_sub0 $end $var wire 32 ** P0 [31:0] $end $var wire 32 +* P1 [31:0] $end $var wire 8 <) out[0] [7:0] $end $var wire 8 =) out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var wire 32 ** P0 [31:0] $end $var wire 32 +* P1 [31:0] $end $var wire 8 >) out[0] [7:0] $end $var wire 8 ?) out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var wire 32 ** P0 [31:0] $end $var wire 32 +* P1 [31:0] $end $var wire 8 @) out[0] [7:0] $end $var wire 8 A) out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var wire 32 ** P0 [31:0] $end $var wire 32 ,* P1 [31:0] $end $var wire 8 B) out[0] [7:0] $end $var wire 8 C) out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 c) i [31:0] $end $scope module unnamedblk2 $end $var wire 32 d) j [31:0] $end $scope module unnamedblk3 $end $var wire 128 e) exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3_2.i_sub4_1.i_sub5 $end $var wire 1 c* clk $end $var wire 128 d* in[0][0] [127:0] $end $var wire 128 h* in[0][1] [127:0] $end $var wire 128 l* in[0][2] [127:0] $end $var wire 128 p* in[1][0] [127:0] $end $var wire 128 t* in[1][1] [127:0] $end $var wire 128 x* in[1][2] [127:0] $end $var wire 8 |* out[0][0] [7:0] $end $var wire 8 }* out[0][1] [7:0] $end $var wire 8 ~* out[0][2] [7:0] $end $var wire 8 !+ out[1][0] [7:0] $end $var wire 8 "+ out[1][1] [7:0] $end $var wire 8 #+ out[1][2] [7:0] $end $scope module sub5 $end $var wire 1 c* clk $end $var wire 128 >* in[0][0] [127:0] $end $var wire 128 B* in[0][1] [127:0] $end $var wire 128 F* in[0][2] [127:0] $end $var wire 128 J* in[1][0] [127:0] $end $var wire 128 N* in[1][1] [127:0] $end $var wire 128 R* in[1][2] [127:0] $end $var wire 8 V* out[0][0] [7:0] $end $var wire 8 W* out[0][1] [7:0] $end $var wire 8 X* out[0][2] [7:0] $end $var wire 8 Y* out[1][0] [7:0] $end $var wire 8 Z* out[1][1] [7:0] $end $var wire 8 [* out[1][2] [7:0] $end $var wire 32 \* count [31:0] $end $var wire 8 .* val0[0] [7:0] $end $var wire 8 /* val0[1] [7:0] $end $var wire 8 0* val1[0] [7:0] $end $var wire 8 1* val1[1] [7:0] $end $var wire 8 2* val2[0] [7:0] $end $var wire 8 3* val2[1] [7:0] $end $var wire 8 4* val3[0] [7:0] $end $var wire 8 5* val3[1] [7:0] $end $scope module i_sub0 $end $var wire 32 $+ P0 [31:0] $end $var wire 32 %+ P1 [31:0] $end $var wire 8 6* out[0] [7:0] $end $var wire 8 7* out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var wire 32 $+ P0 [31:0] $end $var wire 32 %+ P1 [31:0] $end $var wire 8 8* out[0] [7:0] $end $var wire 8 9* out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var wire 32 $+ P0 [31:0] $end $var wire 32 %+ P1 [31:0] $end $var wire 8 :* out[0] [7:0] $end $var wire 8 ;* out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var wire 32 $+ P0 [31:0] $end $var wire 32 &+ P1 [31:0] $end $var wire 8 <* out[0] [7:0] $end $var wire 8 =* out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 ]* i [31:0] $end $scope module unnamedblk2 $end $var wire 32 ^* j [31:0] $end $scope module unnamedblk3 $end $var wire 128 _* exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000110 # b00000000000000000000000000000110 $ b00000000000000000000000000000110 % b00000000000000000000000000000110 & b00000000 ' b00000000 ( b00000000 ) b00000000000000000000000000000000 * b00000000 + b00000000 , b00000000 - b00000000 . b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C b00000000000000000000000000000000 G b00000000000000000000000000000000 H b00000000000000000000000000000000 I b00000000 J b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _ b00000000000000000000000000000000 c b00000000000000000000000000000000 d b00000000000000000000000000000000 e b00000000 f b00000000 g b00000000 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 } b00000000000000000000000000000000 #! b00000000000000000000000000000000 $! b00000000000000000000000000000000 %! b00000000 &! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;! b00000000000000000000000000000000 ?! b00000000000000000000000000000000 @! b00000000000000000000000000000000 A! b00000000 B! b00000000 C! b00000000 D! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C" b00000000 G" b00000000 H" b00000000 I" b00000000 J" b00000000 K" b00000000 L" b00000000 M" b00000000 N" b00000000 O" b00000000 P" b00000000 Q" b00000000 R" b00000000 S" b00000000 T" b00000000 U" b00000000 V" b00000000 W" b00000000 X" b00000000 Y" b00000000 Z" b00000000 [" b00000000 \" b00000000 ]" b00000000 ^" b00000000 _" b00000000 `" b00000000 a" b00000000 b" b00000000 c" b00000000 d" b00000000 e" b00000000 f" b00000000 g" b00000000 h" b00000000 i" b00000000 j" b00000000 k" b00000000 l" b00000000 m" b00000000 n" b00000000 o" b00000000 p" b00000000 q" b00000000 r" b00000000 s" b00000000 t" b00000000 u" b00000000 v" b00000000 w" b00000000 x" b00000000 y" 0z" 02# b00000000 3# b00000000 4# b00000000 5# 07# b00000000 8# b00000000 9# b00000000 :# b00000000000000000000000000000110 <# b00000001 =# b00000010 ># b00000001 ?# b00000010 @# b00000001 A# b00000010 B# b00000001 C# b00000011 D# b00000001 E# b00000010 F# b00000001 G# b00000010 H# b00000001 I# b00000010 J# b00000001 K# b00000011 L# b00000000000000000000000000000110 M# b00000001 N# b00000010 O# b00000001 P# b00000010 Q# b00000001 R# b00000010 S# b00000001 T# b00000011 U# b00000001 V# b00000010 W# b00000001 X# b00000010 Y# b00000001 Z# b00000010 [# b00000001 \# b00000011 ]# b00000000000000000000000000000110 ^# b00000001 _# b00000010 `# b00000001 a# b00000010 b# b00000001 c# b00000010 d# b00000001 e# b00000011 f# b00000001 g# b00000010 h# b00000001 i# b00000010 j# b00000001 k# b00000010 l# b00000001 m# b00000011 n# b00000000000000000000000000000110 o# b00000001 p# b00000010 q# b00000001 r# b00000010 s# b00000001 t# b00000010 u# b00000001 v# b00000011 w# b00000001 x# b00000010 y# b00000001 z# b00000010 {# b00000001 |# b00000010 }# b00000001 ~# b00000011 !$ b00000000 "$ b00000000 #$ b00000000 $$ b00000000 %$ b00000000 &$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;$ b00000000 ?$ b00000000 @$ b00000000 A$ b00000000 B$ b00000000 C$ b00000000 D$ b00000000000000000000000000000000 E$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Z$ b00000000 ^$ b00000000 _$ b00000000 `$ b00000000 a$ b00000000 b$ b00000000 c$ b00000000000000000000000000000000 d$ b00000000000000000000000000000000 e$ b00000000000000000000000000000000 f$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 g$ b00000000000000000000000000000000 k$ b00000000000000000000000000000000 l$ b00000000 m$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $% b00000000 (% b00000000 )% b00000000 *% b00000000 +% b00000000 ,% b00000000 -% b00000000000000000000000000000000 .% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C% b00000000 G% b00000000 H% b00000000 I% b00000000 J% b00000000 K% b00000000 L% b00000000000000000000000000000000 M% b00000000000000000000000000000000 N% b00000000000000000000000000000000 O% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P% b00000000000000000000000000000000 T% b00000000000000000000000000000000 U% b00000000 V% b00000000 W% b00000000 X% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m% b00000000 q% b00000000 r% b00000000 s% b00000000 t% b00000000 u% b00000000 v% b00000000000000000000000000000000 w% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 && b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 *& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 .& b00000000 2& b00000000 3& b00000000 4& b00000000 5& b00000000 6& b00000000 7& b00000000000000000000000000000000 8& b00000000000000000000000000000000 9& b00000000000000000000000000000000 :& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;& b00000000000000000000000000000000 ?& b00000000000000000000000000000000 @& b00000000 A& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V& b00000000 Z& b00000000 [& b00000000 \& b00000000 ]& b00000000 ^& b00000000 _& b00000000000000000000000000000000 `& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u& b00000000 y& b00000000 z& b00000000 {& b00000000 |& b00000000 }& b00000000 ~& b00000000000000000000000000000000 !' b00000000000000000000000000000000 "' b00000000000000000000000000000000 #' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $' b00000000000000000000000000000000 (' b00000000000000000000000000000000 )' b00000000 *' 0+' b00000000 ,' b00000000 -' b00000001 @' b00000010 A' b00000001 B' b00000010 C' b00000001 D' b00000010 E' b00000001 F' b00000011 G' b00000001 H' b00000010 I' b00000001 J' b00000010 K' b00000001 L' b00000010 M' b00000001 N' b00000011 O' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 `' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 d' b00000000 h' b00000000 i' b00000000 j' b00000000 k' b00000000 l' b00000000 m' b00000000000000000000000000000000 n' b00000000000000000000000000000000 o' b00000000000000000000000000000000 p' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q' 0u' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 (( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ,( b00000000 0( b00000000 1( b00000000 2( b00000000 3( b00000000 4( b00000000 5( b00000001 :( b00000010 ;( b00000001 <( b00000010 =( b00000001 >( b00000010 ?( b00000001 @( b00000011 A( b00000001 B( b00000010 C( b00000001 D( b00000010 E( b00000001 F( b00000010 G( b00000001 H( b00000011 I( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Z( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ^( b00000000 b( b00000000 c( b00000000 d( b00000000 e( b00000000 f( b00000000 g( b00000000000000000000000000000000 h( b00000000000000000000000000000000 i( b00000000000000000000000000000000 j( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 k( 0o( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ") b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 &) b00000000 *) b00000000 +) b00000000 ,) b00000000 -) b00000000 .) b00000000 /) b00000001 4) b00000010 5) b00000001 6) b00000010 7) b00000001 8) b00000010 9) b00000001 :) b00000011 ;) b00000001 <) b00000010 =) b00000001 >) b00000010 ?) b00000001 @) b00000010 A) b00000001 B) b00000011 C) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X) b00000000 \) b00000000 ]) b00000000 ^) b00000000 _) b00000000 `) b00000000 a) b00000000000000000000000000000000 b) b00000000000000000000000000000000 c) b00000000000000000000000000000000 d) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e) 0i) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~) b00000000 $* b00000000 %* b00000000 &* b00000000 '* b00000000 (* b00000000 )* b00000001 .* b00000010 /* b00000001 0* b00000010 1* b00000001 2* b00000010 3* b00000001 4* b00000011 5* b00000001 6* b00000010 7* b00000001 8* b00000010 9* b00000001 :* b00000010 ;* b00000001 <* b00000011 =* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R* b00000000 V* b00000000 W* b00000000 X* b00000000 Y* b00000000 Z* b00000000 [* b00000000000000000000000000000000 \* b00000000000000000000000000000000 ]* b00000000000000000000000000000000 ^* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _* 0c* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x* b00000000 |* b00000000 }* b00000000 ~* b00000000 !+ b00000000 "+ b00000000 #+ b00000000000000000000000000100001 {" b00000000000000000000000000101100 |" b00000000000000000000000000000010 }" b00000000000000000000000000001000 ~" b00000000000000000000000000000001 !# b00000000000000000000000000000011 "# b00000001 ## b00000000000000000000000000000000 $# b00000000000000000000000000000001 %# b1111111111111101 &# b00 '# b00000000000000000000000000000010 (# r3.1 )# r4.1 +# r5 -# b00000000000000000000000000000000 /# b00000000000000000000000000000001 0# b00000011 .' b00000000000000000000000000000000 /' b00000000000000000000000000000001 0' b1111111111111101 1' b11 2' b00000000000000000000000000000010 3' r3.1 4' r4.1 6' b00000000000000000000000000000001 8' b00000000000000000000000000000010 9' b00000000000000000000000000000011 :' r5 ;' b00000000000000000000000000000000 =' b00000000000000000000000000000001 >' b00000000000000000000000000000001 6( b00000000000000000000000000000010 7( b00000000000000000000000000000011 8( b00000000000000000000000000000001 0) b00000000000000000000000000000010 1) b00000000000000000000000000000011 2) b00000000000000000000000000000001 ** b00000000000000000000000000000010 +* b00000000000000000000000000000011 ,* b00000000000000000000000000000001 $+ b00000000000000000000000000000010 %+ b00000000000000000000000000000011 &+ #10 b00000010 ' b00000000000000000000000000000001 * b00000010 . b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 C b00000000000000000000000000000001 G b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _ b00000000000000000000000000000001 c b00000001 g b00000010 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 y b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 } b00000000000000000000000000000001 #! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;! b00000000000000000000000000000001 ?! b00000010 C! b00000001 D! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 Y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 +" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ?" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 C" b00000001 H" b00000010 I" 1z" 12# b00000010 3# 17# b00000001 9# b00000001 :# b00000010 "$ b00000010 #$ b00000010 $$ b00000011 %$ b00000010 &$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;$ b00000000000000000000000000000001 E$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 R$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 V$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 Z$ b00000000000000000000000000000001 d$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 z$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $% b00000000000000000000000000000001 .% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ?% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 C% b00000000000000000000000000000001 M% b00000011 W% b00000010 X% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m% b00000000000000000000000000000001 w% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 && b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 *& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 .& b00000000000000000000000000000001 8& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 N& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 R& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 V& b00000000000000000000000000000001 `& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 m& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 q& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 u& b00000000000000000000000000000001 !' 1+' b00000001 ,' b00000010 -' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 `' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 d' b00000000000000000000000000000001 n' 1u' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 $( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 (( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ,( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 V( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 Z( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ^( b00000000000000000000000000000001 h( 1o( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 |( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ") b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 &) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 P) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 T) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 X) b00000000000000000000000000000001 b) 1i) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 v) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ~) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 J* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 R* b00000000000000000000000000000001 \* 1c* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 p* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 t* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 x* #15 0z" 02# 07# 0+' 0u' 0o( 0i) 0c* #20 b00000011 ' b00000000000000000000000000000010 * b00000010 + b00000011 . b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C b00000000000000000000000000000010 G b00000000000000000000000000000010 H b00000000000000000000000000000011 I b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _ b00000000000000000000000000000010 c b00000000000000000000000000000010 d b00000000000000000000000000000011 e b00000011 g b00000011 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 } b00000000000000000000000000000010 #! b00000000000000000000000000000010 $! b00000000000000000000000000000011 %! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;! b00000000000000000000000000000010 ?! b00000000000000000000000000000010 @! b00000000000000000000000000000011 A! b00000011 C! b00000011 D! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C" b00000010 G" b00000101 I" b00000110 J" b00000101 K" b00000100 L" b00000011 M" b00000010 N" b00000001 O" b00000110 P" b00000101 Q" b00000100 R" b00000011 S" b00000010 T" b00000001 U" b00000110 V" b00000101 W" b00000100 X" b00000011 Y" b00000010 Z" b00000001 [" b00000110 \" b00000101 ]" b00000100 ^" b00000011 _" b00000010 `" b00000001 a" b00000110 b" b00000101 c" b00000100 d" b00000011 e" b00000010 f" b00000001 g" b00000110 h" b00000101 i" b00000100 j" b00000011 k" b00000010 l" b00000001 m" b00000110 n" b00000101 o" b00000100 p" b00000011 q" b00000010 r" b00000001 s" b00000110 t" b00000101 u" b00000100 v" b00000011 w" b00000010 x" b00000001 y" 1z" 12# b00000011 3# b00000010 4# b00000010 5# 17# b00000010 8# b00000011 "$ b00000101 #$ b00000101 $$ b00000101 %$ b00000101 &$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;$ b00000110 ?$ b00000101 @$ b00000100 A$ b00000011 B$ b00000010 C$ b00000001 D$ b00000000000000000000000000000010 E$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Z$ b00000110 ^$ b00000101 _$ b00000100 `$ b00000011 a$ b00000010 b$ b00000001 c$ b00000000000000000000000000000010 d$ b00000000000000000000000000000010 e$ b00000000000000000000000000000011 f$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 g$ b00000000000000000000000000000010 k$ b00000000000000000000000000000011 l$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $% b00000110 (% b00000101 )% b00000100 *% b00000011 +% b00000010 ,% b00000001 -% b00000000000000000000000000000010 .% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C% b00000110 G% b00000101 H% b00000100 I% b00000011 J% b00000010 K% b00000001 L% b00000000000000000000000000000010 M% b00000000000000000000000000000010 N% b00000000000000000000000000000011 O% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 P% b00000000000000000000000000000010 T% b00000000000000000000000000000011 U% b00000101 W% b00000101 X% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m% b00000110 q% b00000101 r% b00000100 s% b00000011 t% b00000010 u% b00000001 v% b00000000000000000000000000000010 w% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 && b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 *& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 .& b00000110 2& b00000101 3& b00000100 4& b00000011 5& b00000010 6& b00000001 7& b00000000000000000000000000000010 8& b00000000000000000000000000000010 9& b00000000000000000000000000000011 :& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;& b00000000000000000000000000000010 ?& b00000000000000000000000000000011 @& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V& b00000110 Z& b00000101 [& b00000100 \& b00000011 ]& b00000010 ^& b00000001 _& b00000000000000000000000000000010 `& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u& b00000110 y& b00000101 z& b00000100 {& b00000011 |& b00000010 }& b00000001 ~& b00000000000000000000000000000010 !' b00000000000000000000000000000010 "' b00000000000000000000000000000011 #' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $' b00000000000000000000000000000010 (' b00000000000000000000000000000011 )' 1+' b00000101 -' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 `' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 d' b00000110 h' b00000101 i' b00000100 j' b00000011 k' b00000010 l' b00000001 m' b00000000000000000000000000000010 n' b00000000000000000000000000000010 o' b00000000000000000000000000000011 p' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 q' 1u' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 (( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ,( b00000110 0( b00000101 1( b00000100 2( b00000011 3( b00000010 4( b00000001 5( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Z( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ^( b00000110 b( b00000101 c( b00000100 d( b00000011 e( b00000010 f( b00000001 g( b00000000000000000000000000000010 h( b00000000000000000000000000000010 i( b00000000000000000000000000000011 j( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 k( 1o( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ") b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 &) b00000110 *) b00000101 +) b00000100 ,) b00000011 -) b00000010 .) b00000001 /) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X) b00000110 \) b00000101 ]) b00000100 ^) b00000011 _) b00000010 `) b00000001 a) b00000000000000000000000000000010 b) b00000000000000000000000000000010 c) b00000000000000000000000000000011 d) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 e) 1i) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~) b00000110 $* b00000101 %* b00000100 &* b00000011 '* b00000010 (* b00000001 )* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R* b00000110 V* b00000101 W* b00000100 X* b00000011 Y* b00000010 Z* b00000001 [* b00000000000000000000000000000010 \* b00000000000000000000000000000010 ]* b00000000000000000000000000000011 ^* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _* 1c* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x* b00000110 |* b00000101 }* b00000100 ~* b00000011 !+ b00000010 "+ b00000001 #+ #25 0z" 02# 07# 0+' 0u' 0o( 0i) 0c* #30 b00000101 ' b00000010 ( b00000000000000000000000000000011 * b00000011 + b00000101 . b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 C b00000000000000000000000000000011 G b00000001 J b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _ b00000000000000000000000000000011 c b00000001 f b00000110 g b00000101 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 y b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 } b00000000000000000000000000000011 #! b00000001 &! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;! b00000000000000000000000000000011 ?! b00000001 B! b00000101 C! b00000110 D! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 Y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 +" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ?" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 C" b00000011 G" b00000011 H" b00000111 I" b00000000 J" b00000000 K" b00000000 L" b00000000 M" b00000000 N" b00000000 O" b00000000 P" b00000000 Q" b00000000 R" b00000000 S" b00000000 T" b00000000 U" b00000000 V" b00000000 W" b00000000 X" b00000000 Y" b00000000 Z" b00000000 [" b00000000 \" b00000000 ]" b00000000 ^" b00000000 _" b00000000 `" b00000000 a" b00000000 b" b00000000 c" b00000000 d" b00000000 e" b00000000 f" b00000000 g" b00000000 h" b00000000 i" b00000000 j" b00000000 k" b00000000 l" b00000000 m" b00000000 n" b00000000 o" b00000000 p" b00000000 q" b00000000 r" b00000000 s" b00000000 t" b00000000 u" b00000000 v" b00000000 w" b00000000 x" b00000000 y" 1z" 12# b00000101 3# b00000011 4# b00000011 5# 17# b00000011 8# b00000011 9# b00000011 :# b00000111 #$ b00000111 $$ b00000110 %$ b00000111 &$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;$ b00000000 ?$ b00000000 @$ b00000000 A$ b00000000 B$ b00000000 C$ b00000000 D$ b00000000000000000000000000000011 E$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 R$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 V$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 Z$ b00000000 ^$ b00000000 _$ b00000000 `$ b00000000 a$ b00000000 b$ b00000000 c$ b00000000000000000000000000000011 d$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 g$ b00000001 m$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 z$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $% b00000000 (% b00000000 )% b00000000 *% b00000000 +% b00000000 ,% b00000000 -% b00000000000000000000000000000011 .% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ?% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 C% b00000000 G% b00000000 H% b00000000 I% b00000000 J% b00000000 K% b00000000 L% b00000000000000000000000000000011 M% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P% b00000001 V% b00000110 W% b00000111 X% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m% b00000000 q% b00000000 r% b00000000 s% b00000000 t% b00000000 u% b00000000 v% b00000000000000000000000000000011 w% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 && b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 *& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 .& b00000000 2& b00000000 3& b00000000 4& b00000000 5& b00000000 6& b00000000 7& b00000000000000000000000000000011 8& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;& b00000001 A& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 N& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 R& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 V& b00000000 Z& b00000000 [& b00000000 \& b00000000 ]& b00000000 ^& b00000000 _& b00000000000000000000000000000011 `& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 m& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 q& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 u& b00000000 y& b00000000 z& b00000000 {& b00000000 |& b00000000 }& b00000000 ~& b00000000000000000000000000000011 !' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $' b00000001 *' 1+' b00000011 ,' b00000111 -' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 `' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 d' b00000000 h' b00000000 i' b00000000 j' b00000000 k' b00000000 l' b00000000 m' b00000000000000000000000000000011 n' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q' 1u' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 $( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 (( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ,( b00000000 0( b00000000 1( b00000000 2( b00000000 3( b00000000 4( b00000000 5( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 V( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 Z( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ^( b00000000 b( b00000000 c( b00000000 d( b00000000 e( b00000000 f( b00000000 g( b00000000000000000000000000000011 h( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 k( 1o( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 |( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ") b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 &) b00000000 *) b00000000 +) b00000000 ,) b00000000 -) b00000000 .) b00000000 /) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 P) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 T) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 X) b00000000 \) b00000000 ]) b00000000 ^) b00000000 _) b00000000 `) b00000000 a) b00000000000000000000000000000011 b) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e) 1i) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 v) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ~) b00000000 $* b00000000 %* b00000000 &* b00000000 '* b00000000 (* b00000000 )* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 J* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 R* b00000000 V* b00000000 W* b00000000 X* b00000000 Y* b00000000 Z* b00000000 [* b00000000000000000000000000000011 \* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _* 1c* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 p* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 t* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 x* b00000000 |* b00000000 }* b00000000 ~* b00000000 !+ b00000000 "+ b00000000 #+ #35 0z" 02# 07# 0+' 0u' 0o( 0i) 0c* #40 b00001000 ' b00000011 ( b00000000000000000000000000000100 * b00000101 + b00000010 , b00001000 . b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C b00000000000000000000000000000100 G b00000000 J b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _ b00000000000000000000000000000100 c b00000000 f b00001000 g b00001000 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 } b00000000000000000000000000000100 #! b00000000 &! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;! b00000000000000000000000000000100 ?! b00000000 B! b00001000 C! b00001000 D! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C" b00000101 G" b00000100 H" b00001000 I" b00000110 J" b00000101 K" b00000100 L" b00000011 M" b00000010 N" b00000001 O" b00000110 P" b00000101 Q" b00000100 R" b00000011 S" b00000010 T" b00000001 U" b00000110 V" b00000101 W" b00000100 X" b00000011 Y" b00000010 Z" b00000001 [" b00000110 \" b00000101 ]" b00000100 ^" b00000011 _" b00000010 `" b00000001 a" b00000110 b" b00000101 c" b00000100 d" b00000011 e" b00000010 f" b00000001 g" b00000110 h" b00000101 i" b00000100 j" b00000011 k" b00000010 l" b00000001 m" b00000110 n" b00000101 o" b00000100 p" b00000011 q" b00000010 r" b00000001 s" b00000110 t" b00000101 u" b00000100 v" b00000011 w" b00000010 x" b00000001 y" 1z" 12# b00001000 3# b00000101 4# b00000101 5# 17# b00000101 8# b00000100 9# b00000100 :# b00000101 "$ b00001000 #$ b00001000 $$ b00001000 &$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;$ b00000110 ?$ b00000101 @$ b00000100 A$ b00000011 B$ b00000010 C$ b00000001 D$ b00000000000000000000000000000100 E$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Z$ b00000110 ^$ b00000101 _$ b00000100 `$ b00000011 a$ b00000010 b$ b00000001 c$ b00000000000000000000000000000100 d$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 g$ b00000000 m$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $% b00000110 (% b00000101 )% b00000100 *% b00000011 +% b00000010 ,% b00000001 -% b00000000000000000000000000000100 .% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C% b00000110 G% b00000101 H% b00000100 I% b00000011 J% b00000010 K% b00000001 L% b00000000000000000000000000000100 M% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 P% b00000000 V% b00001000 X% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m% b00000110 q% b00000101 r% b00000100 s% b00000011 t% b00000010 u% b00000001 v% b00000000000000000000000000000100 w% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 && b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 *& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 .& b00000110 2& b00000101 3& b00000100 4& b00000011 5& b00000010 6& b00000001 7& b00000000000000000000000000000100 8& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;& b00000000 A& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V& b00000110 Z& b00000101 [& b00000100 \& b00000011 ]& b00000010 ^& b00000001 _& b00000000000000000000000000000100 `& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u& b00000110 y& b00000101 z& b00000100 {& b00000011 |& b00000010 }& b00000001 ~& b00000000000000000000000000000100 !' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $' b00000000 *' 1+' b00000100 ,' b00001000 -' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 `' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 d' b00000110 h' b00000101 i' b00000100 j' b00000011 k' b00000010 l' b00000001 m' b00000000000000000000000000000100 n' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 q' 1u' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 (( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ,( b00000110 0( b00000101 1( b00000100 2( b00000011 3( b00000010 4( b00000001 5( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Z( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ^( b00000110 b( b00000101 c( b00000100 d( b00000011 e( b00000010 f( b00000001 g( b00000000000000000000000000000100 h( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 k( 1o( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ") b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 &) b00000110 *) b00000101 +) b00000100 ,) b00000011 -) b00000010 .) b00000001 /) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X) b00000110 \) b00000101 ]) b00000100 ^) b00000011 _) b00000010 `) b00000001 a) b00000000000000000000000000000100 b) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 e) 1i) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~) b00000110 $* b00000101 %* b00000100 &* b00000011 '* b00000010 (* b00000001 )* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R* b00000110 V* b00000101 W* b00000100 X* b00000011 Y* b00000010 Z* b00000001 [* b00000000000000000000000000000100 \* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _* 1c* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x* b00000110 |* b00000101 }* b00000100 ~* b00000011 !+ b00000010 "+ b00000001 #+ #45 0z" 02# 07# 0+' 0u' 0o( 0i) 0c* #50 b00001010 ' b00000101 ( b00000000000000000000000000000101 * b00001000 + b00000011 , b00000010 - b00001010 . b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 C b00000000000000000000000000000101 G b00000001 J b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _ b00000000000000000000000000000101 c b00000001 f b00001001 g b00001010 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 y b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 } b00000000000000000000000000000101 #! b00000001 &! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;! b00000000000000000000000000000101 ?! b00000001 B! b00001010 C! b00001001 D! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 Y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 +" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ?" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 C" b00001000 G" b00000110 H" b00000000 J" b00000000 K" b00000000 L" b00000000 M" b00000000 N" b00000000 O" b00000000 P" b00000000 Q" b00000000 R" b00000000 S" b00000000 T" b00000000 U" b00000000 V" b00000000 W" b00000000 X" b00000000 Y" b00000000 Z" b00000000 [" b00000000 \" b00000000 ]" b00000000 ^" b00000000 _" b00000000 `" b00000000 a" b00000000 b" b00000000 c" b00000000 d" b00000000 e" b00000000 f" b00000000 g" b00000000 h" b00000000 i" b00000000 j" b00000000 k" b00000000 l" b00000000 m" b00000000 n" b00000000 o" b00000000 p" b00000000 q" b00000000 r" b00000000 s" b00000000 t" b00000000 u" b00000000 v" b00000000 w" b00000000 x" b00000000 y" 1z" 12# b00001010 3# b00001000 4# b00001000 5# 17# b00001000 8# b00000110 9# b00000110 :# b00000110 "$ b00001000 %$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;$ b00000000 ?$ b00000000 @$ b00000000 A$ b00000000 B$ b00000000 C$ b00000000 D$ b00000000000000000000000000000101 E$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 R$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 V$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 Z$ b00000000 ^$ b00000000 _$ b00000000 `$ b00000000 a$ b00000000 b$ b00000000 c$ b00000000000000000000000000000101 d$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 g$ b00000001 m$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 z$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $% b00000000 (% b00000000 )% b00000000 *% b00000000 +% b00000000 ,% b00000000 -% b00000000000000000000000000000101 .% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ?% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 C% b00000000 G% b00000000 H% b00000000 I% b00000000 J% b00000000 K% b00000000 L% b00000000000000000000000000000101 M% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P% b00000001 V% b00001000 W% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m% b00000000 q% b00000000 r% b00000000 s% b00000000 t% b00000000 u% b00000000 v% b00000000000000000000000000000101 w% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 && b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 *& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 .& b00000000 2& b00000000 3& b00000000 4& b00000000 5& b00000000 6& b00000000 7& b00000000000000000000000000000101 8& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;& b00000001 A& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 N& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 R& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 V& b00000000 Z& b00000000 [& b00000000 \& b00000000 ]& b00000000 ^& b00000000 _& b00000000000000000000000000000101 `& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 m& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 q& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 u& b00000000 y& b00000000 z& b00000000 {& b00000000 |& b00000000 }& b00000000 ~& b00000000000000000000000000000101 !' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $' b00000001 *' 1+' b00000110 ,' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 `' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 d' b00000000 h' b00000000 i' b00000000 j' b00000000 k' b00000000 l' b00000000 m' b00000000000000000000000000000101 n' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q' 1u' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 $( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 (( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ,( b00000000 0( b00000000 1( b00000000 2( b00000000 3( b00000000 4( b00000000 5( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 V( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 Z( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ^( b00000000 b( b00000000 c( b00000000 d( b00000000 e( b00000000 f( b00000000 g( b00000000000000000000000000000101 h( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 k( 1o( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 |( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ") b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 &) b00000000 *) b00000000 +) b00000000 ,) b00000000 -) b00000000 .) b00000000 /) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 P) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 T) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 X) b00000000 \) b00000000 ]) b00000000 ^) b00000000 _) b00000000 `) b00000000 a) b00000000000000000000000000000101 b) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e) 1i) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 v) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ~) b00000000 $* b00000000 %* b00000000 &* b00000000 '* b00000000 (* b00000000 )* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 J* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 R* b00000000 V* b00000000 W* b00000000 X* b00000000 Y* b00000000 Z* b00000000 [* b00000000000000000000000000000101 \* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _* 1c* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 p* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 t* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 x* b00000000 |* b00000000 }* b00000000 ~* b00000000 !+ b00000000 "+ b00000000 #+ #55 0z" 02# 07# 0+' 0u' 0o( 0i) 0c* #60 b00001011 ' b00001000 ( b00000010 ) b00000000000000000000000000000110 * b00001010 + b00000101 , b00000011 - b00001011 . b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C b00000000000000000000000000000110 G b00000000 J b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _ b00000000000000000000000000000110 c b00000000 f b00001011 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 } b00000000000000000000000000000110 #! b00000000 &! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;! b00000000000000000000000000000110 ?! b00000000 B! b00001011 C! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C" b00001010 G" b00001001 H" b00001010 I" b00000110 J" b00000101 K" b00000100 L" b00000011 M" b00000010 N" b00000001 O" b00000110 P" b00000101 Q" b00000100 R" b00000011 S" b00000010 T" b00000001 U" b00000110 V" b00000101 W" b00000100 X" b00000011 Y" b00000010 Z" b00000001 [" b00000110 \" b00000101 ]" b00000100 ^" b00000011 _" b00000010 `" b00000001 a" b00000110 b" b00000101 c" b00000100 d" b00000011 e" b00000010 f" b00000001 g" b00000110 h" b00000101 i" b00000100 j" b00000011 k" b00000010 l" b00000001 m" b00000110 n" b00000101 o" b00000100 p" b00000011 q" b00000010 r" b00000001 s" b00000110 t" b00000101 u" b00000100 v" b00000011 w" b00000010 x" b00000001 y" 1z" 12# b00001011 3# b00001010 4# b00001010 5# 17# b00001010 8# b00001001 9# b00001001 :# b00001000 "$ b00001010 #$ b00001010 $$ b00001001 %$ b00001010 &$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;$ b00000110 ?$ b00000101 @$ b00000100 A$ b00000011 B$ b00000010 C$ b00000001 D$ b00000000000000000000000000000110 E$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Z$ b00000110 ^$ b00000101 _$ b00000100 `$ b00000011 a$ b00000010 b$ b00000001 c$ b00000000000000000000000000000110 d$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 g$ b00000000 m$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $% b00000110 (% b00000101 )% b00000100 *% b00000011 +% b00000010 ,% b00000001 -% b00000000000000000000000000000110 .% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C% b00000110 G% b00000101 H% b00000100 I% b00000011 J% b00000010 K% b00000001 L% b00000000000000000000000000000110 M% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 P% b00000000 V% b00001001 W% b00001010 X% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m% b00000110 q% b00000101 r% b00000100 s% b00000011 t% b00000010 u% b00000001 v% b00000000000000000000000000000110 w% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 && b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 *& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 .& b00000110 2& b00000101 3& b00000100 4& b00000011 5& b00000010 6& b00000001 7& b00000000000000000000000000000110 8& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;& b00000000 A& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V& b00000110 Z& b00000101 [& b00000100 \& b00000011 ]& b00000010 ^& b00000001 _& b00000000000000000000000000000110 `& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u& b00000110 y& b00000101 z& b00000100 {& b00000011 |& b00000010 }& b00000001 ~& b00000000000000000000000000000110 !' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $' b00000000 *' 1+' b00001001 ,' b00001010 -' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 `' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 d' b00000110 h' b00000101 i' b00000100 j' b00000011 k' b00000010 l' b00000001 m' b00000000000000000000000000000110 n' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 q' 1u' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 (( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ,( b00000110 0( b00000101 1( b00000100 2( b00000011 3( b00000010 4( b00000001 5( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Z( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ^( b00000110 b( b00000101 c( b00000100 d( b00000011 e( b00000010 f( b00000001 g( b00000000000000000000000000000110 h( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 k( 1o( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ") b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 &) b00000110 *) b00000101 +) b00000100 ,) b00000011 -) b00000010 .) b00000001 /) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X) b00000110 \) b00000101 ]) b00000100 ^) b00000011 _) b00000010 `) b00000001 a) b00000000000000000000000000000110 b) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 e) 1i) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~) b00000110 $* b00000101 %* b00000100 &* b00000011 '* b00000010 (* b00000001 )* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R* b00000110 V* b00000101 W* b00000100 X* b00000011 Y* b00000010 Z* b00000001 [* b00000000000000000000000000000110 \* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _* 1c* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x* b00000110 |* b00000101 }* b00000100 ~* b00000011 !+ b00000010 "+ b00000001 #+ #65 0z" 02# 07# 0+' 0u' 0o( 0i) 0c* #70 b00001010 ( b00000011 ) b00000000000000000000000000000111 * b00001011 + b00001000 , b00000101 - b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 C b00000000000000000000000000000111 G b00000001 J b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _ b00000000000000000000000000000111 c b00000001 f b00001011 g b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 y b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 } b00000000000000000000000000000111 #! b00000001 &! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;! b00000000000000000000000000000111 ?! b00000001 B! b00001011 D! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 Y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 +" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ?" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 C" b00001011 G" b00001011 H" b00001011 I" b00000000 J" b00000000 K" b00000000 L" b00000000 M" b00000000 N" b00000000 O" b00000000 P" b00000000 Q" b00000000 R" b00000000 S" b00000000 T" b00000000 U" b00000000 V" b00000000 W" b00000000 X" b00000000 Y" b00000000 Z" b00000000 [" b00000000 \" b00000000 ]" b00000000 ^" b00000000 _" b00000000 `" b00000000 a" b00000000 b" b00000000 c" b00000000 d" b00000000 e" b00000000 f" b00000000 g" b00000000 h" b00000000 i" b00000000 j" b00000000 k" b00000000 l" b00000000 m" b00000000 n" b00000000 o" b00000000 p" b00000000 q" b00000000 r" b00000000 s" b00000000 t" b00000000 u" b00000000 v" b00000000 w" b00000000 x" b00000000 y" 1z" 12# b00001011 4# b00001011 5# 17# b00001011 8# b00001011 9# b00001011 :# b00001011 "$ b00001011 #$ b00001011 $$ b00001011 %$ b00001011 &$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;$ b00000000 ?$ b00000000 @$ b00000000 A$ b00000000 B$ b00000000 C$ b00000000 D$ b00000000000000000000000000000111 E$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 R$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 V$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 Z$ b00000000 ^$ b00000000 _$ b00000000 `$ b00000000 a$ b00000000 b$ b00000000 c$ b00000000000000000000000000000111 d$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 g$ b00000001 m$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 z$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $% b00000000 (% b00000000 )% b00000000 *% b00000000 +% b00000000 ,% b00000000 -% b00000000000000000000000000000111 .% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ?% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 C% b00000000 G% b00000000 H% b00000000 I% b00000000 J% b00000000 K% b00000000 L% b00000000000000000000000000000111 M% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P% b00000001 V% b00001011 W% b00001011 X% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m% b00000000 q% b00000000 r% b00000000 s% b00000000 t% b00000000 u% b00000000 v% b00000000000000000000000000000111 w% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 && b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 *& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 .& b00000000 2& b00000000 3& b00000000 4& b00000000 5& b00000000 6& b00000000 7& b00000000000000000000000000000111 8& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;& b00000001 A& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 N& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 R& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 V& b00000000 Z& b00000000 [& b00000000 \& b00000000 ]& b00000000 ^& b00000000 _& b00000000000000000000000000000111 `& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 m& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 q& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 u& b00000000 y& b00000000 z& b00000000 {& b00000000 |& b00000000 }& b00000000 ~& b00000000000000000000000000000111 !' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $' b00000001 *' 1+' b00001011 ,' b00001011 -' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 `' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 d' b00000000 h' b00000000 i' b00000000 j' b00000000 k' b00000000 l' b00000000 m' b00000000000000000000000000000111 n' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q' 1u' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 $( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 (( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ,( b00000000 0( b00000000 1( b00000000 2( b00000000 3( b00000000 4( b00000000 5( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 V( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 Z( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ^( b00000000 b( b00000000 c( b00000000 d( b00000000 e( b00000000 f( b00000000 g( b00000000000000000000000000000111 h( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 k( 1o( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 |( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ") b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 &) b00000000 *) b00000000 +) b00000000 ,) b00000000 -) b00000000 .) b00000000 /) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 P) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 T) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 X) b00000000 \) b00000000 ]) b00000000 ^) b00000000 _) b00000000 `) b00000000 a) b00000000000000000000000000000111 b) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e) 1i) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 v) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ~) b00000000 $* b00000000 %* b00000000 &* b00000000 '* b00000000 (* b00000000 )* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 J* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 R* b00000000 V* b00000000 W* b00000000 X* b00000000 Y* b00000000 Z* b00000000 [* b00000000000000000000000000000111 \* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _* 1c* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 p* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 t* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 x* b00000000 |* b00000000 }* b00000000 ~* b00000000 !+ b00000000 "+ b00000000 #+ #75 0z" 02# 07# 0+' 0u' 0o( 0i) 0c* #80 b00001101 ' b00001011 ( b00000101 ) b00000000000000000000000000001000 * b00001010 , b00001000 - b00001101 . b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C b00000000000000000000000000001000 G b00000000 J b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _ b00000000000000000000000000001000 c b00000000 f b00001100 g b00001101 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 } b00000000000000000000000000001000 #! b00000000 &! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;! b00000000000000000000000000001000 ?! b00000000 B! b00001101 C! b00001100 D! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C" b00001100 H" b00001101 I" b00000110 J" b00000101 K" b00000100 L" b00000011 M" b00000010 N" b00000001 O" b00000110 P" b00000101 Q" b00000100 R" b00000011 S" b00000010 T" b00000001 U" b00000110 V" b00000101 W" b00000100 X" b00000011 Y" b00000010 Z" b00000001 [" b00000110 \" b00000101 ]" b00000100 ^" b00000011 _" b00000010 `" b00000001 a" b00000110 b" b00000101 c" b00000100 d" b00000011 e" b00000010 f" b00000001 g" b00000110 h" b00000101 i" b00000100 j" b00000011 k" b00000010 l" b00000001 m" b00000110 n" b00000101 o" b00000100 p" b00000011 q" b00000010 r" b00000001 s" b00000110 t" b00000101 u" b00000100 v" b00000011 w" b00000010 x" b00000001 y" 1z" 12# b00001101 3# 17# b00001100 9# b00001100 :# b00001101 "$ b00001101 #$ b00001101 $$ b00001110 %$ b00001101 &$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;$ b00000110 ?$ b00000101 @$ b00000100 A$ b00000011 B$ b00000010 C$ b00000001 D$ b00000000000000000000000000001000 E$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Z$ b00000110 ^$ b00000101 _$ b00000100 `$ b00000011 a$ b00000010 b$ b00000001 c$ b00000000000000000000000000001000 d$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 g$ b00000000 m$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $% b00000110 (% b00000101 )% b00000100 *% b00000011 +% b00000010 ,% b00000001 -% b00000000000000000000000000001000 .% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C% b00000110 G% b00000101 H% b00000100 I% b00000011 J% b00000010 K% b00000001 L% b00000000000000000000000000001000 M% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 P% b00000000 V% b00001110 W% b00001101 X% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m% b00000110 q% b00000101 r% b00000100 s% b00000011 t% b00000010 u% b00000001 v% b00000000000000000000000000001000 w% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 && b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 *& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 .& b00000110 2& b00000101 3& b00000100 4& b00000011 5& b00000010 6& b00000001 7& b00000000000000000000000000001000 8& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;& b00000000 A& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V& b00000110 Z& b00000101 [& b00000100 \& b00000011 ]& b00000010 ^& b00000001 _& b00000000000000000000000000001000 `& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u& b00000110 y& b00000101 z& b00000100 {& b00000011 |& b00000010 }& b00000001 ~& b00000000000000000000000000001000 !' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $' b00000000 *' 1+' b00001100 ,' b00001101 -' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 `' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 d' b00000110 h' b00000101 i' b00000100 j' b00000011 k' b00000010 l' b00000001 m' b00000000000000000000000000001000 n' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 q' 1u' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 (( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ,( b00000110 0( b00000101 1( b00000100 2( b00000011 3( b00000010 4( b00000001 5( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Z( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ^( b00000110 b( b00000101 c( b00000100 d( b00000011 e( b00000010 f( b00000001 g( b00000000000000000000000000001000 h( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 k( 1o( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ") b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 &) b00000110 *) b00000101 +) b00000100 ,) b00000011 -) b00000010 .) b00000001 /) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X) b00000110 \) b00000101 ]) b00000100 ^) b00000011 _) b00000010 `) b00000001 a) b00000000000000000000000000001000 b) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 e) 1i) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~) b00000110 $* b00000101 %* b00000100 &* b00000011 '* b00000010 (* b00000001 )* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R* b00000110 V* b00000101 W* b00000100 X* b00000011 Y* b00000010 Z* b00000001 [* b00000000000000000000000000001000 \* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _* 1c* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x* b00000110 |* b00000101 }* b00000100 ~* b00000011 !+ b00000010 "+ b00000001 #+ #85 0z" 02# 07# 0+' 0u' 0o( 0i) 0c* #90 b00001110 ' b00001000 ) b00000000000000000000000000001001 * b00001101 + b00001011 , b00001010 - b00001110 . b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 C b00000000000000000000000000001001 G b00000001 J b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _ b00000000000000000000000000001001 c b00000001 f b00001110 g b00001110 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 y b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 } b00000000000000000000000000001001 #! b00000001 &! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;! b00000000000000000000000000001001 ?! b00000001 B! b00001110 C! b00001110 D! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 Y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 +" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ?" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 C" b00001101 G" b00010000 I" b00000000 J" b00000000 K" b00000000 L" b00000000 M" b00000000 N" b00000000 O" b00000000 P" b00000000 Q" b00000000 R" b00000000 S" b00000000 T" b00000000 U" b00000000 V" b00000000 W" b00000000 X" b00000000 Y" b00000000 Z" b00000000 [" b00000000 \" b00000000 ]" b00000000 ^" b00000000 _" b00000000 `" b00000000 a" b00000000 b" b00000000 c" b00000000 d" b00000000 e" b00000000 f" b00000000 g" b00000000 h" b00000000 i" b00000000 j" b00000000 k" b00000000 l" b00000000 m" b00000000 n" b00000000 o" b00000000 p" b00000000 q" b00000000 r" b00000000 s" b00000000 t" b00000000 u" b00000000 v" b00000000 w" b00000000 x" b00000000 y" 1z" 12# b00001110 3# b00001101 4# b00001101 5# 17# b00001101 8# b00001110 "$ b00010000 #$ b00010000 $$ b00010000 %$ b00010000 &$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;$ b00000000 ?$ b00000000 @$ b00000000 A$ b00000000 B$ b00000000 C$ b00000000 D$ b00000000000000000000000000001001 E$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 R$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 V$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 Z$ b00000000 ^$ b00000000 _$ b00000000 `$ b00000000 a$ b00000000 b$ b00000000 c$ b00000000000000000000000000001001 d$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 g$ b00000001 m$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 z$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $% b00000000 (% b00000000 )% b00000000 *% b00000000 +% b00000000 ,% b00000000 -% b00000000000000000000000000001001 .% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ?% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 C% b00000000 G% b00000000 H% b00000000 I% b00000000 J% b00000000 K% b00000000 L% b00000000000000000000000000001001 M% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P% b00000001 V% b00010000 W% b00010000 X% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m% b00000000 q% b00000000 r% b00000000 s% b00000000 t% b00000000 u% b00000000 v% b00000000000000000000000000001001 w% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 && b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 *& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 .& b00000000 2& b00000000 3& b00000000 4& b00000000 5& b00000000 6& b00000000 7& b00000000000000000000000000001001 8& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;& b00000001 A& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 N& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 R& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 V& b00000000 Z& b00000000 [& b00000000 \& b00000000 ]& b00000000 ^& b00000000 _& b00000000000000000000000000001001 `& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 m& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 q& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 u& b00000000 y& b00000000 z& b00000000 {& b00000000 |& b00000000 }& b00000000 ~& b00000000000000000000000000001001 !' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $' b00000001 *' 1+' b00010000 -' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 `' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 d' b00000000 h' b00000000 i' b00000000 j' b00000000 k' b00000000 l' b00000000 m' b00000000000000000000000000001001 n' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q' 1u' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 $( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 (( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ,( b00000000 0( b00000000 1( b00000000 2( b00000000 3( b00000000 4( b00000000 5( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 V( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 Z( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ^( b00000000 b( b00000000 c( b00000000 d( b00000000 e( b00000000 f( b00000000 g( b00000000000000000000000000001001 h( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 k( 1o( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 |( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ") b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 &) b00000000 *) b00000000 +) b00000000 ,) b00000000 -) b00000000 .) b00000000 /) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 P) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 T) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 X) b00000000 \) b00000000 ]) b00000000 ^) b00000000 _) b00000000 `) b00000000 a) b00000000000000000000000000001001 b) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e) 1i) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 v) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ~) b00000000 $* b00000000 %* b00000000 &* b00000000 '* b00000000 (* b00000000 )* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 J* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 R* b00000000 V* b00000000 W* b00000000 X* b00000000 Y* b00000000 Z* b00000000 [* b00000000000000000000000000001001 \* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _* 1c* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 p* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 t* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 x* b00000000 |* b00000000 }* b00000000 ~* b00000000 !+ b00000000 "+ b00000000 #+ #95 0z" 02# 07# 0+' 0u' 0o( 0i) 0c* #100 b00010000 ' b00001101 ( b00001010 ) b00000000000000000000000000001010 * b00001110 + b00001011 - b00010000 . b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C b00000000000000000000000000001010 G b00000000 J b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _ b00000000000000000000000000001010 c b00000000 f b00010001 g b00010000 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 } b00000000000000000000000000001010 #! b00000000 &! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;! b00000000000000000000000000001010 ?! b00000000 B! b00010000 C! b00010001 D! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C" b00001110 G" b00001110 H" b00010010 I" b00000110 J" b00000101 K" b00000100 L" b00000011 M" b00000010 N" b00000001 O" b00000110 P" b00000101 Q" b00000100 R" b00000011 S" b00000010 T" b00000001 U" b00000110 V" b00000101 W" b00000100 X" b00000011 Y" b00000010 Z" b00000001 [" b00000110 \" b00000101 ]" b00000100 ^" b00000011 _" b00000010 `" b00000001 a" b00000110 b" b00000101 c" b00000100 d" b00000011 e" b00000010 f" b00000001 g" b00000110 h" b00000101 i" b00000100 j" b00000011 k" b00000010 l" b00000001 m" b00000110 n" b00000101 o" b00000100 p" b00000011 q" b00000010 r" b00000001 s" b00000110 t" b00000101 u" b00000100 v" b00000011 w" b00000010 x" b00000001 y" 1z" 12# b00010000 3# b00001110 4# b00001110 5# 17# b00001110 8# b00001110 9# b00001110 :# b00010010 #$ b00010010 $$ b00010001 %$ b00010010 &$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;$ b00000110 ?$ b00000101 @$ b00000100 A$ b00000011 B$ b00000010 C$ b00000001 D$ b00000000000000000000000000001010 E$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Z$ b00000110 ^$ b00000101 _$ b00000100 `$ b00000011 a$ b00000010 b$ b00000001 c$ b00000000000000000000000000001010 d$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 g$ b00000000 m$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $% b00000110 (% b00000101 )% b00000100 *% b00000011 +% b00000010 ,% b00000001 -% b00000000000000000000000000001010 .% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C% b00000110 G% b00000101 H% b00000100 I% b00000011 J% b00000010 K% b00000001 L% b00000000000000000000000000001010 M% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 P% b00000000 V% b00010001 W% b00010010 X% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m% b00000110 q% b00000101 r% b00000100 s% b00000011 t% b00000010 u% b00000001 v% b00000000000000000000000000001010 w% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 && b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 *& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 .& b00000110 2& b00000101 3& b00000100 4& b00000011 5& b00000010 6& b00000001 7& b00000000000000000000000000001010 8& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;& b00000000 A& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V& b00000110 Z& b00000101 [& b00000100 \& b00000011 ]& b00000010 ^& b00000001 _& b00000000000000000000000000001010 `& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u& b00000110 y& b00000101 z& b00000100 {& b00000011 |& b00000010 }& b00000001 ~& b00000000000000000000000000001010 !' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $' b00000000 *' 1+' b00001110 ,' b00010010 -' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 `' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 d' b00000110 h' b00000101 i' b00000100 j' b00000011 k' b00000010 l' b00000001 m' b00000000000000000000000000001010 n' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 q' 1u' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 (( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ,( b00000110 0( b00000101 1( b00000100 2( b00000011 3( b00000010 4( b00000001 5( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Z( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ^( b00000110 b( b00000101 c( b00000100 d( b00000011 e( b00000010 f( b00000001 g( b00000000000000000000000000001010 h( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 k( 1o( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ") b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 &) b00000110 *) b00000101 +) b00000100 ,) b00000011 -) b00000010 .) b00000001 /) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X) b00000110 \) b00000101 ]) b00000100 ^) b00000011 _) b00000010 `) b00000001 a) b00000000000000000000000000001010 b) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 e) 1i) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~) b00000110 $* b00000101 %* b00000100 &* b00000011 '* b00000010 (* b00000001 )* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R* b00000110 V* b00000101 W* b00000100 X* b00000011 Y* b00000010 Z* b00000001 [* b00000000000000000000000000001010 \* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _* 1c* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x* b00000110 |* b00000101 }* b00000100 ~* b00000011 !+ b00000010 "+ b00000001 #+ #105 0z" 02# 07# 0+' 0u' 0o( 0i) 0c* #110 b00010011 ' b00001110 ( b00001011 ) b00000000000000000000000000001011 * b00010000 + b00001101 , b00010011 . b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 C b00000000000000000000000000001011 G b00000001 J b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _ b00000000000000000000000000001011 c b00000001 f b00010011 g b00010011 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 y b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 } b00000000000000000000000000001011 #! b00000001 &! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;! b00000000000000000000000000001011 ?! b00000001 B! b00010011 C! b00010011 D! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 Y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 +" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ?" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 C" b00010000 G" b00001111 H" b00010011 I" b00000000 J" b00000000 K" b00000000 L" b00000000 M" b00000000 N" b00000000 O" b00000000 P" b00000000 Q" b00000000 R" b00000000 S" b00000000 T" b00000000 U" b00000000 V" b00000000 W" b00000000 X" b00000000 Y" b00000000 Z" b00000000 [" b00000000 \" b00000000 ]" b00000000 ^" b00000000 _" b00000000 `" b00000000 a" b00000000 b" b00000000 c" b00000000 d" b00000000 e" b00000000 f" b00000000 g" b00000000 h" b00000000 i" b00000000 j" b00000000 k" b00000000 l" b00000000 m" b00000000 n" b00000000 o" b00000000 p" b00000000 q" b00000000 r" b00000000 s" b00000000 t" b00000000 u" b00000000 v" b00000000 w" b00000000 x" b00000000 y" 1z" 12# b00010011 3# b00010000 4# b00010000 5# 17# b00010000 8# b00001111 9# b00001111 :# b00010000 "$ b00010011 #$ b00010011 $$ b00010011 &$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;$ b00000000 ?$ b00000000 @$ b00000000 A$ b00000000 B$ b00000000 C$ b00000000 D$ b00000000000000000000000000001011 E$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 R$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 V$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 Z$ b00000000 ^$ b00000000 _$ b00000000 `$ b00000000 a$ b00000000 b$ b00000000 c$ b00000000000000000000000000001011 d$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 g$ b00000001 m$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 z$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $% b00000000 (% b00000000 )% b00000000 *% b00000000 +% b00000000 ,% b00000000 -% b00000000000000000000000000001011 .% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ?% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 C% b00000000 G% b00000000 H% b00000000 I% b00000000 J% b00000000 K% b00000000 L% b00000000000000000000000000001011 M% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P% b00000001 V% b00010011 X% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m% b00000000 q% b00000000 r% b00000000 s% b00000000 t% b00000000 u% b00000000 v% b00000000000000000000000000001011 w% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 && b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 *& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 .& b00000000 2& b00000000 3& b00000000 4& b00000000 5& b00000000 6& b00000000 7& b00000000000000000000000000001011 8& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;& b00000001 A& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 N& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 R& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 V& b00000000 Z& b00000000 [& b00000000 \& b00000000 ]& b00000000 ^& b00000000 _& b00000000000000000000000000001011 `& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 m& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 q& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 u& b00000000 y& b00000000 z& b00000000 {& b00000000 |& b00000000 }& b00000000 ~& b00000000000000000000000000001011 !' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $' b00000001 *' 1+' b00001111 ,' b00010011 -' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 `' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 d' b00000000 h' b00000000 i' b00000000 j' b00000000 k' b00000000 l' b00000000 m' b00000000000000000000000000001011 n' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q' 1u' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 $( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 (( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ,( b00000000 0( b00000000 1( b00000000 2( b00000000 3( b00000000 4( b00000000 5( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 V( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 Z( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ^( b00000000 b( b00000000 c( b00000000 d( b00000000 e( b00000000 f( b00000000 g( b00000000000000000000000000001011 h( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 k( 1o( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 |( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ") b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 &) b00000000 *) b00000000 +) b00000000 ,) b00000000 -) b00000000 .) b00000000 /) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 P) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 T) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 X) b00000000 \) b00000000 ]) b00000000 ^) b00000000 _) b00000000 `) b00000000 a) b00000000000000000000000000001011 b) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e) 1i) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 v) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ~) b00000000 $* b00000000 %* b00000000 &* b00000000 '* b00000000 (* b00000000 )* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 J* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 R* b00000000 V* b00000000 W* b00000000 X* b00000000 Y* b00000000 Z* b00000000 [* b00000000000000000000000000001011 \* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _* 1c* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 p* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 t* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 x* b00000000 |* b00000000 }* b00000000 ~* b00000000 !+ b00000000 "+ b00000000 #+ #115 0z" 02# 07# 0+' 0u' 0o( 0i) 0c* #120 b00010101 ' b00010000 ( b00000000000000000000000000001100 * b00010011 + b00001110 , b00001101 - b00010101 . b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C b00000000000000000000000000001100 G b00000000 J b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _ b00000000000000000000000000001100 c b00000000 f b00010100 g b00010101 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 } b00000000000000000000000000001100 #! b00000000 &! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;! b00000000000000000000000000001100 ?! b00000000 B! b00010101 C! b00010100 D! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C" b00010011 G" b00010001 H" b00000110 J" b00000101 K" b00000100 L" b00000011 M" b00000010 N" b00000001 O" b00000110 P" b00000101 Q" b00000100 R" b00000011 S" b00000010 T" b00000001 U" b00000110 V" b00000101 W" b00000100 X" b00000011 Y" b00000010 Z" b00000001 [" b00000110 \" b00000101 ]" b00000100 ^" b00000011 _" b00000010 `" b00000001 a" b00000110 b" b00000101 c" b00000100 d" b00000011 e" b00000010 f" b00000001 g" b00000110 h" b00000101 i" b00000100 j" b00000011 k" b00000010 l" b00000001 m" b00000110 n" b00000101 o" b00000100 p" b00000011 q" b00000010 r" b00000001 s" b00000110 t" b00000101 u" b00000100 v" b00000011 w" b00000010 x" b00000001 y" 1z" 12# b00010101 3# b00010011 4# b00010011 5# 17# b00010011 8# b00010001 9# b00010001 :# b00010001 "$ b00010011 %$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;$ b00000110 ?$ b00000101 @$ b00000100 A$ b00000011 B$ b00000010 C$ b00000001 D$ b00000000000000000000000000001100 E$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Z$ b00000110 ^$ b00000101 _$ b00000100 `$ b00000011 a$ b00000010 b$ b00000001 c$ b00000000000000000000000000001100 d$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 g$ b00000000 m$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $% b00000110 (% b00000101 )% b00000100 *% b00000011 +% b00000010 ,% b00000001 -% b00000000000000000000000000001100 .% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C% b00000110 G% b00000101 H% b00000100 I% b00000011 J% b00000010 K% b00000001 L% b00000000000000000000000000001100 M% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 P% b00000000 V% b00010011 W% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m% b00000110 q% b00000101 r% b00000100 s% b00000011 t% b00000010 u% b00000001 v% b00000000000000000000000000001100 w% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 && b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 *& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 .& b00000110 2& b00000101 3& b00000100 4& b00000011 5& b00000010 6& b00000001 7& b00000000000000000000000000001100 8& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;& b00000000 A& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V& b00000110 Z& b00000101 [& b00000100 \& b00000011 ]& b00000010 ^& b00000001 _& b00000000000000000000000000001100 `& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u& b00000110 y& b00000101 z& b00000100 {& b00000011 |& b00000010 }& b00000001 ~& b00000000000000000000000000001100 !' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $' b00000000 *' 1+' b00010001 ,' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 `' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 d' b00000110 h' b00000101 i' b00000100 j' b00000011 k' b00000010 l' b00000001 m' b00000000000000000000000000001100 n' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 q' 1u' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 (( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ,( b00000110 0( b00000101 1( b00000100 2( b00000011 3( b00000010 4( b00000001 5( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Z( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ^( b00000110 b( b00000101 c( b00000100 d( b00000011 e( b00000010 f( b00000001 g( b00000000000000000000000000001100 h( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 k( 1o( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ") b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 &) b00000110 *) b00000101 +) b00000100 ,) b00000011 -) b00000010 .) b00000001 /) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X) b00000110 \) b00000101 ]) b00000100 ^) b00000011 _) b00000010 `) b00000001 a) b00000000000000000000000000001100 b) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 e) 1i) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~) b00000110 $* b00000101 %* b00000100 &* b00000011 '* b00000010 (* b00000001 )* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R* b00000110 V* b00000101 W* b00000100 X* b00000011 Y* b00000010 Z* b00000001 [* b00000000000000000000000000001100 \* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _* 1c* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x* b00000110 |* b00000101 }* b00000100 ~* b00000011 !+ b00000010 "+ b00000001 #+ #125 0z" 02# 07# 0+' 0u' 0o( 0i) 0c* #130 b00010110 ' b00010011 ( b00001101 ) b00000000000000000000000000001101 * b00010101 + b00010000 , b00001110 - b00010110 . b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 C b00000000000000000000000000001101 G b00000001 J b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _ b00000000000000000000000000001101 c b00000001 f b00010110 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 y b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 } b00000000000000000000000000001101 #! b00000001 &! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;! b00000000000000000000000000001101 ?! b00000001 B! b00010110 C! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 Y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 +" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ?" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 C" b00010101 G" b00010100 H" b00010101 I" b00000000 J" b00000000 K" b00000000 L" b00000000 M" b00000000 N" b00000000 O" b00000000 P" b00000000 Q" b00000000 R" b00000000 S" b00000000 T" b00000000 U" b00000000 V" b00000000 W" b00000000 X" b00000000 Y" b00000000 Z" b00000000 [" b00000000 \" b00000000 ]" b00000000 ^" b00000000 _" b00000000 `" b00000000 a" b00000000 b" b00000000 c" b00000000 d" b00000000 e" b00000000 f" b00000000 g" b00000000 h" b00000000 i" b00000000 j" b00000000 k" b00000000 l" b00000000 m" b00000000 n" b00000000 o" b00000000 p" b00000000 q" b00000000 r" b00000000 s" b00000000 t" b00000000 u" b00000000 v" b00000000 w" b00000000 x" b00000000 y" 1z" 12# b00010110 3# b00010101 4# b00010101 5# 17# b00010101 8# b00010100 9# b00010100 :# b00010011 "$ b00010101 #$ b00010101 $$ b00010100 %$ b00010101 &$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;$ b00000000 ?$ b00000000 @$ b00000000 A$ b00000000 B$ b00000000 C$ b00000000 D$ b00000000000000000000000000001101 E$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 R$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 V$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 Z$ b00000000 ^$ b00000000 _$ b00000000 `$ b00000000 a$ b00000000 b$ b00000000 c$ b00000000000000000000000000001101 d$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 g$ b00000001 m$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 z$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $% b00000000 (% b00000000 )% b00000000 *% b00000000 +% b00000000 ,% b00000000 -% b00000000000000000000000000001101 .% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ?% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 C% b00000000 G% b00000000 H% b00000000 I% b00000000 J% b00000000 K% b00000000 L% b00000000000000000000000000001101 M% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P% b00000001 V% b00010100 W% b00010101 X% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m% b00000000 q% b00000000 r% b00000000 s% b00000000 t% b00000000 u% b00000000 v% b00000000000000000000000000001101 w% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 && b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 *& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 .& b00000000 2& b00000000 3& b00000000 4& b00000000 5& b00000000 6& b00000000 7& b00000000000000000000000000001101 8& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;& b00000001 A& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 N& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 R& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 V& b00000000 Z& b00000000 [& b00000000 \& b00000000 ]& b00000000 ^& b00000000 _& b00000000000000000000000000001101 `& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 m& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 q& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 u& b00000000 y& b00000000 z& b00000000 {& b00000000 |& b00000000 }& b00000000 ~& b00000000000000000000000000001101 !' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $' b00000001 *' 1+' b00010100 ,' b00010101 -' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 `' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 d' b00000000 h' b00000000 i' b00000000 j' b00000000 k' b00000000 l' b00000000 m' b00000000000000000000000000001101 n' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q' 1u' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 $( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 (( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ,( b00000000 0( b00000000 1( b00000000 2( b00000000 3( b00000000 4( b00000000 5( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 V( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 Z( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ^( b00000000 b( b00000000 c( b00000000 d( b00000000 e( b00000000 f( b00000000 g( b00000000000000000000000000001101 h( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 k( 1o( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 |( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ") b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 &) b00000000 *) b00000000 +) b00000000 ,) b00000000 -) b00000000 .) b00000000 /) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 P) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 T) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 X) b00000000 \) b00000000 ]) b00000000 ^) b00000000 _) b00000000 `) b00000000 a) b00000000000000000000000000001101 b) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e) 1i) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 v) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ~) b00000000 $* b00000000 %* b00000000 &* b00000000 '* b00000000 (* b00000000 )* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 J* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 R* b00000000 V* b00000000 W* b00000000 X* b00000000 Y* b00000000 Z* b00000000 [* b00000000000000000000000000001101 \* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _* 1c* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 p* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 t* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 x* b00000000 |* b00000000 }* b00000000 ~* b00000000 !+ b00000000 "+ b00000000 #+ #135 0z" 02# 07# 0+' 0u' 0o( 0i) 0c* #140 b00010101 ( b00001110 ) b00000000000000000000000000001110 * b00010110 + b00010011 , b00010000 - b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C b00000000000000000000000000001110 G b00000000 J b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _ b00000000000000000000000000001110 c b00000000 f b00010110 g b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 } b00000000000000000000000000001110 #! b00000000 &! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;! b00000000000000000000000000001110 ?! b00000000 B! b00010110 D! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C" b00010110 G" b00010110 H" b00010110 I" b00000110 J" b00000101 K" b00000100 L" b00000011 M" b00000010 N" b00000001 O" b00000110 P" b00000101 Q" b00000100 R" b00000011 S" b00000010 T" b00000001 U" b00000110 V" b00000101 W" b00000100 X" b00000011 Y" b00000010 Z" b00000001 [" b00000110 \" b00000101 ]" b00000100 ^" b00000011 _" b00000010 `" b00000001 a" b00000110 b" b00000101 c" b00000100 d" b00000011 e" b00000010 f" b00000001 g" b00000110 h" b00000101 i" b00000100 j" b00000011 k" b00000010 l" b00000001 m" b00000110 n" b00000101 o" b00000100 p" b00000011 q" b00000010 r" b00000001 s" b00000110 t" b00000101 u" b00000100 v" b00000011 w" b00000010 x" b00000001 y" 1z" 12# b00010110 4# b00010110 5# 17# b00010110 8# b00010110 9# b00010110 :# b00010110 "$ b00010110 #$ b00010110 $$ b00010110 %$ b00010110 &$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;$ b00000110 ?$ b00000101 @$ b00000100 A$ b00000011 B$ b00000010 C$ b00000001 D$ b00000000000000000000000000001110 E$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Z$ b00000110 ^$ b00000101 _$ b00000100 `$ b00000011 a$ b00000010 b$ b00000001 c$ b00000000000000000000000000001110 d$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 g$ b00000000 m$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $% b00000110 (% b00000101 )% b00000100 *% b00000011 +% b00000010 ,% b00000001 -% b00000000000000000000000000001110 .% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C% b00000110 G% b00000101 H% b00000100 I% b00000011 J% b00000010 K% b00000001 L% b00000000000000000000000000001110 M% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 P% b00000000 V% b00010110 W% b00010110 X% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m% b00000110 q% b00000101 r% b00000100 s% b00000011 t% b00000010 u% b00000001 v% b00000000000000000000000000001110 w% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 && b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 *& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 .& b00000110 2& b00000101 3& b00000100 4& b00000011 5& b00000010 6& b00000001 7& b00000000000000000000000000001110 8& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;& b00000000 A& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V& b00000110 Z& b00000101 [& b00000100 \& b00000011 ]& b00000010 ^& b00000001 _& b00000000000000000000000000001110 `& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u& b00000110 y& b00000101 z& b00000100 {& b00000011 |& b00000010 }& b00000001 ~& b00000000000000000000000000001110 !' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $' b00000000 *' 1+' b00010110 ,' b00010110 -' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 `' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 d' b00000110 h' b00000101 i' b00000100 j' b00000011 k' b00000010 l' b00000001 m' b00000000000000000000000000001110 n' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 q' 1u' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 (( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ,( b00000110 0( b00000101 1( b00000100 2( b00000011 3( b00000010 4( b00000001 5( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Z( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ^( b00000110 b( b00000101 c( b00000100 d( b00000011 e( b00000010 f( b00000001 g( b00000000000000000000000000001110 h( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 k( 1o( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ") b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 &) b00000110 *) b00000101 +) b00000100 ,) b00000011 -) b00000010 .) b00000001 /) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X) b00000110 \) b00000101 ]) b00000100 ^) b00000011 _) b00000010 `) b00000001 a) b00000000000000000000000000001110 b) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 e) 1i) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~) b00000110 $* b00000101 %* b00000100 &* b00000011 '* b00000010 (* b00000001 )* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R* b00000110 V* b00000101 W* b00000100 X* b00000011 Y* b00000010 Z* b00000001 [* b00000000000000000000000000001110 \* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _* 1c* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x* b00000110 |* b00000101 }* b00000100 ~* b00000011 !+ b00000010 "+ b00000001 #+ #145 0z" 02# 07# 0+' 0u' 0o( 0i) 0c* #150 b00011000 ' b00010110 ( b00010000 ) b00000000000000000000000000001111 * b00010101 , b00010011 - b00011000 . b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 C b00000000000000000000000000001111 G b00000001 J b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _ b00000000000000000000000000001111 c b00000001 f b00010111 g b00011000 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 y b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 } b00000000000000000000000000001111 #! b00000001 &! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;! b00000000000000000000000000001111 ?! b00000001 B! b00011000 C! b00010111 D! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 Y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 +" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ?" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 C" b00010111 H" b00011000 I" b00000000 J" b00000000 K" b00000000 L" b00000000 M" b00000000 N" b00000000 O" b00000000 P" b00000000 Q" b00000000 R" b00000000 S" b00000000 T" b00000000 U" b00000000 V" b00000000 W" b00000000 X" b00000000 Y" b00000000 Z" b00000000 [" b00000000 \" b00000000 ]" b00000000 ^" b00000000 _" b00000000 `" b00000000 a" b00000000 b" b00000000 c" b00000000 d" b00000000 e" b00000000 f" b00000000 g" b00000000 h" b00000000 i" b00000000 j" b00000000 k" b00000000 l" b00000000 m" b00000000 n" b00000000 o" b00000000 p" b00000000 q" b00000000 r" b00000000 s" b00000000 t" b00000000 u" b00000000 v" b00000000 w" b00000000 x" b00000000 y" 1z" 12# b00011000 3# 17# b00010111 9# b00010111 :# b00011000 "$ b00011000 #$ b00011000 $$ b00011001 %$ b00011000 &$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;$ b00000000 ?$ b00000000 @$ b00000000 A$ b00000000 B$ b00000000 C$ b00000000 D$ b00000000000000000000000000001111 E$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 R$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 V$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 Z$ b00000000 ^$ b00000000 _$ b00000000 `$ b00000000 a$ b00000000 b$ b00000000 c$ b00000000000000000000000000001111 d$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 g$ b00000001 m$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 z$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $% b00000000 (% b00000000 )% b00000000 *% b00000000 +% b00000000 ,% b00000000 -% b00000000000000000000000000001111 .% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ?% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 C% b00000000 G% b00000000 H% b00000000 I% b00000000 J% b00000000 K% b00000000 L% b00000000000000000000000000001111 M% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P% b00000001 V% b00011001 W% b00011000 X% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m% b00000000 q% b00000000 r% b00000000 s% b00000000 t% b00000000 u% b00000000 v% b00000000000000000000000000001111 w% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 && b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 *& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 .& b00000000 2& b00000000 3& b00000000 4& b00000000 5& b00000000 6& b00000000 7& b00000000000000000000000000001111 8& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;& b00000001 A& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 N& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 R& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 V& b00000000 Z& b00000000 [& b00000000 \& b00000000 ]& b00000000 ^& b00000000 _& b00000000000000000000000000001111 `& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 m& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 q& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 u& b00000000 y& b00000000 z& b00000000 {& b00000000 |& b00000000 }& b00000000 ~& b00000000000000000000000000001111 !' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $' b00000001 *' 1+' b00010111 ,' b00011000 -' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 `' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 d' b00000000 h' b00000000 i' b00000000 j' b00000000 k' b00000000 l' b00000000 m' b00000000000000000000000000001111 n' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q' 1u' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 $( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 (( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ,( b00000000 0( b00000000 1( b00000000 2( b00000000 3( b00000000 4( b00000000 5( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 V( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 Z( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ^( b00000000 b( b00000000 c( b00000000 d( b00000000 e( b00000000 f( b00000000 g( b00000000000000000000000000001111 h( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 k( 1o( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 |( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ") b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 &) b00000000 *) b00000000 +) b00000000 ,) b00000000 -) b00000000 .) b00000000 /) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 P) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 T) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 X) b00000000 \) b00000000 ]) b00000000 ^) b00000000 _) b00000000 `) b00000000 a) b00000000000000000000000000001111 b) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e) 1i) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 v) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ~) b00000000 $* b00000000 %* b00000000 &* b00000000 '* b00000000 (* b00000000 )* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 J* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 R* b00000000 V* b00000000 W* b00000000 X* b00000000 Y* b00000000 Z* b00000000 [* b00000000000000000000000000001111 \* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _* 1c* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 p* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 t* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 x* b00000000 |* b00000000 }* b00000000 ~* b00000000 !+ b00000000 "+ b00000000 #+ #155 0z" 02# 07# 0+' 0u' 0o( 0i) 0c* #160 b00011001 ' b00010011 ) b00000000000000000000000000010000 * b00011000 + b00010110 , b00010101 - b00011001 . b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C b00000000000000000000000000010000 G b00000000 J b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _ b00000000000000000000000000010000 c b00000000 f b00011001 g b00011001 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 } b00000000000000000000000000010000 #! b00000000 &! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;! b00000000000000000000000000010000 ?! b00000000 B! b00011001 C! b00011001 D! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C" b00011000 G" b00011011 I" b00000110 J" b00000101 K" b00000100 L" b00000011 M" b00000010 N" b00000001 O" b00000110 P" b00000101 Q" b00000100 R" b00000011 S" b00000010 T" b00000001 U" b00000110 V" b00000101 W" b00000100 X" b00000011 Y" b00000010 Z" b00000001 [" b00000110 \" b00000101 ]" b00000100 ^" b00000011 _" b00000010 `" b00000001 a" b00000110 b" b00000101 c" b00000100 d" b00000011 e" b00000010 f" b00000001 g" b00000110 h" b00000101 i" b00000100 j" b00000011 k" b00000010 l" b00000001 m" b00000110 n" b00000101 o" b00000100 p" b00000011 q" b00000010 r" b00000001 s" b00000110 t" b00000101 u" b00000100 v" b00000011 w" b00000010 x" b00000001 y" 1z" 12# b00011001 3# b00011000 4# b00011000 5# 17# b00011000 8# b00011001 "$ b00011011 #$ b00011011 $$ b00011011 %$ b00011011 &$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;$ b00000110 ?$ b00000101 @$ b00000100 A$ b00000011 B$ b00000010 C$ b00000001 D$ b00000000000000000000000000010000 E$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Z$ b00000110 ^$ b00000101 _$ b00000100 `$ b00000011 a$ b00000010 b$ b00000001 c$ b00000000000000000000000000010000 d$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 g$ b00000000 m$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $% b00000110 (% b00000101 )% b00000100 *% b00000011 +% b00000010 ,% b00000001 -% b00000000000000000000000000010000 .% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C% b00000110 G% b00000101 H% b00000100 I% b00000011 J% b00000010 K% b00000001 L% b00000000000000000000000000010000 M% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 P% b00000000 V% b00011011 W% b00011011 X% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m% b00000110 q% b00000101 r% b00000100 s% b00000011 t% b00000010 u% b00000001 v% b00000000000000000000000000010000 w% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 && b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 *& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 .& b00000110 2& b00000101 3& b00000100 4& b00000011 5& b00000010 6& b00000001 7& b00000000000000000000000000010000 8& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;& b00000000 A& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V& b00000110 Z& b00000101 [& b00000100 \& b00000011 ]& b00000010 ^& b00000001 _& b00000000000000000000000000010000 `& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u& b00000110 y& b00000101 z& b00000100 {& b00000011 |& b00000010 }& b00000001 ~& b00000000000000000000000000010000 !' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $' b00000000 *' 1+' b00011011 -' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 `' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 d' b00000110 h' b00000101 i' b00000100 j' b00000011 k' b00000010 l' b00000001 m' b00000000000000000000000000010000 n' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 q' 1u' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 (( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ,( b00000110 0( b00000101 1( b00000100 2( b00000011 3( b00000010 4( b00000001 5( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Z( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ^( b00000110 b( b00000101 c( b00000100 d( b00000011 e( b00000010 f( b00000001 g( b00000000000000000000000000010000 h( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 k( 1o( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ") b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 &) b00000110 *) b00000101 +) b00000100 ,) b00000011 -) b00000010 .) b00000001 /) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X) b00000110 \) b00000101 ]) b00000100 ^) b00000011 _) b00000010 `) b00000001 a) b00000000000000000000000000010000 b) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 e) 1i) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~) b00000110 $* b00000101 %* b00000100 &* b00000011 '* b00000010 (* b00000001 )* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R* b00000110 V* b00000101 W* b00000100 X* b00000011 Y* b00000010 Z* b00000001 [* b00000000000000000000000000010000 \* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _* 1c* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x* b00000110 |* b00000101 }* b00000100 ~* b00000011 !+ b00000010 "+ b00000001 #+ #165 0z" 02# 07# 0+' 0u' 0o( 0i) 0c* #170 b00011011 ' b00011000 ( b00010101 ) b00000000000000000000000000010001 * b00011001 + b00010110 - b00011011 . b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 C b00000000000000000000000000010001 G b00000001 J b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _ b00000000000000000000000000010001 c b00000001 f b00011100 g b00011011 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 y b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 } b00000000000000000000000000010001 #! b00000001 &! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;! b00000000000000000000000000010001 ?! b00000001 B! b00011011 C! b00011100 D! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 Y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 +" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ?" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 C" b00011001 G" b00011001 H" b00011101 I" b00000000 J" b00000000 K" b00000000 L" b00000000 M" b00000000 N" b00000000 O" b00000000 P" b00000000 Q" b00000000 R" b00000000 S" b00000000 T" b00000000 U" b00000000 V" b00000000 W" b00000000 X" b00000000 Y" b00000000 Z" b00000000 [" b00000000 \" b00000000 ]" b00000000 ^" b00000000 _" b00000000 `" b00000000 a" b00000000 b" b00000000 c" b00000000 d" b00000000 e" b00000000 f" b00000000 g" b00000000 h" b00000000 i" b00000000 j" b00000000 k" b00000000 l" b00000000 m" b00000000 n" b00000000 o" b00000000 p" b00000000 q" b00000000 r" b00000000 s" b00000000 t" b00000000 u" b00000000 v" b00000000 w" b00000000 x" b00000000 y" 1z" 12# b00011011 3# b00011001 4# b00011001 5# 17# b00011001 8# b00011001 9# b00011001 :# b00011101 #$ b00011101 $$ b00011100 %$ b00011101 &$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;$ b00000000 ?$ b00000000 @$ b00000000 A$ b00000000 B$ b00000000 C$ b00000000 D$ b00000000000000000000000000010001 E$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 R$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 V$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 Z$ b00000000 ^$ b00000000 _$ b00000000 `$ b00000000 a$ b00000000 b$ b00000000 c$ b00000000000000000000000000010001 d$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 g$ b00000001 m$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 z$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $% b00000000 (% b00000000 )% b00000000 *% b00000000 +% b00000000 ,% b00000000 -% b00000000000000000000000000010001 .% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ?% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 C% b00000000 G% b00000000 H% b00000000 I% b00000000 J% b00000000 K% b00000000 L% b00000000000000000000000000010001 M% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P% b00000001 V% b00011100 W% b00011101 X% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m% b00000000 q% b00000000 r% b00000000 s% b00000000 t% b00000000 u% b00000000 v% b00000000000000000000000000010001 w% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 && b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 *& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 .& b00000000 2& b00000000 3& b00000000 4& b00000000 5& b00000000 6& b00000000 7& b00000000000000000000000000010001 8& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;& b00000001 A& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 N& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 R& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 V& b00000000 Z& b00000000 [& b00000000 \& b00000000 ]& b00000000 ^& b00000000 _& b00000000000000000000000000010001 `& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 m& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 q& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 u& b00000000 y& b00000000 z& b00000000 {& b00000000 |& b00000000 }& b00000000 ~& b00000000000000000000000000010001 !' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $' b00000001 *' 1+' b00011001 ,' b00011101 -' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 `' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 d' b00000000 h' b00000000 i' b00000000 j' b00000000 k' b00000000 l' b00000000 m' b00000000000000000000000000010001 n' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q' 1u' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 $( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 (( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ,( b00000000 0( b00000000 1( b00000000 2( b00000000 3( b00000000 4( b00000000 5( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 V( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 Z( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ^( b00000000 b( b00000000 c( b00000000 d( b00000000 e( b00000000 f( b00000000 g( b00000000000000000000000000010001 h( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 k( 1o( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 |( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ") b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 &) b00000000 *) b00000000 +) b00000000 ,) b00000000 -) b00000000 .) b00000000 /) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 P) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 T) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 X) b00000000 \) b00000000 ]) b00000000 ^) b00000000 _) b00000000 `) b00000000 a) b00000000000000000000000000010001 b) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e) 1i) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 v) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ~) b00000000 $* b00000000 %* b00000000 &* b00000000 '* b00000000 (* b00000000 )* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 J* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 R* b00000000 V* b00000000 W* b00000000 X* b00000000 Y* b00000000 Z* b00000000 [* b00000000000000000000000000010001 \* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _* 1c* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 p* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 t* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 x* b00000000 |* b00000000 }* b00000000 ~* b00000000 !+ b00000000 "+ b00000000 #+ #174 verilator-5.044/test_regress/t/t_randomize_unpacked_wide.py0000755000542200017500000000104615125463617024654 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_wire_behp1800_bad.py0000755000542200017500000000106215125463617023063 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--language 1800-2017"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_lint_latch_4.py0000755000542200017500000000070315125463617022345 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint() test.passes() verilator-5.044/test_regress/t/t_assert_past.v0000644000542200017500000000144715125463617022151 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ clk ); input clk; int cyc = 0; logic val = 0; // Example: always @(posedge clk) begin cyc <= cyc + 1; val = ~val; $display("t=%0t cyc=%0d val=%b", $time, cyc, val); if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end assert property(@(posedge clk) cyc % 2 == 0 |=> $past(val) == 0) else $display("$past assert 1 failed"); assert property(@(posedge clk) cyc % 2 == 1 |=> $past(val) == 1) else $display("$past assert 2 failed"); // Example end endmodule verilator-5.044/test_regress/t/t_let_arg_bad.py0000755000542200017500000000076615125463617022235 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_func_nansi_mism_bad.py0000755000542200017500000000076615125463617023770 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_wrapper_context__trace0.vcd.out0000644000542200017500000000155615125463617025560 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top1 $end $var wire 1 # clk $end $var wire 1 $ rst $end $var wire 32 % trace_number [31:0] $end $var wire 1 & stop $end $var wire 32 ' counter [31:0] $end $var wire 1 ( done_o $end $scope module top $end $var wire 1 # clk $end $var wire 1 $ rst $end $var wire 32 % trace_number [31:0] $end $var wire 1 & stop $end $var wire 32 ' counter [31:0] $end $var wire 1 ( done_o $end $upscope $end $upscope $end $enddefinitions $end #0 0# 1$ b00000000000000000000000000000000 % 1& b00000000000000000000000000000000 ' 0( #1 1# #2 0# 0$ #3 1# b00000000000000000000000000000001 ' #4 0# #5 1# b00000000000000000000000000000010 ' #6 0# #7 1# b00000000000000000000000000000011 ' #8 0# #9 1# b00000000000000000000000000000100 ' #10 0# #11 1# b00000000000000000000000000000101 ' 1( verilator-5.044/test_regress/t/t_inst_recurse2_bad.out0000644000542200017500000000064715125463617023561 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_inst_recurse2_bad.v:13:8: Unsupported: Identically recursive module (module instantiates itself, without changing parameters): 'looped' : ... note: In instance 't.looped.looped.looped' 13 | module looped; | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.044/test_regress/t/t_display_qqq.v0000644000542200017500000000056715125463617022152 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $display("""First "quoted"\nsecond\ third fourth"""); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_param_repl.py0000755000542200017500000000073415125463617022127 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_unopt_bound.v0000644000542200017500000000126015125463617022146 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jue Xu. // SPDX-License-Identifier: CC0-1.0 // bug630 module t ( clk, out ); input clk; output out; reg a; reg b; typedef struct packed { logic config_a; logic config_b; } param_t; // verilator lint_off UNOPTFLAT param_t conf [1:2] ; // verilator lint_on UNOPTFLAT always @ (posedge clk) begin conf[2].config_b <= a; $write("*-* All Finished *-*\n"); $finish; end always @ (posedge conf[2].config_b) begin a = conf[2].config_a; end endmodule verilator-5.044/test_regress/t/t_trace_sc_empty.py0000755000542200017500000000076315125463617023010 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['-sc', '--trace-vcd']) test.passes() verilator-5.044/test_regress/t/t_wire_beh1364_bad.v0000644000542200017500000000130315125463617022520 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs o, oa, ro, roa, wo, woa ); wire w; reg r; output o; output [1:0] oa; output reg ro; output reg [1:0] roa; output wire wo; output wire [1:0] woa; //1800 only: //output var vo; //output var [1:0] voa; initial begin // Error w = 0; o = 0; oa = 0; wo = 0; woa = 0; // Not an error r = 0; ro = 0; roa = 0; //vo = 0; //voa = 0; end endmodule verilator-5.044/test_regress/t/t_dpi_import_c.cpp0000644000542200017500000001646215125463617022611 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include #include //====================================================================== // clang-format off #if defined(VERILATOR) # include "Vt_dpi_import__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif // clang-format on typedef struct { int a; int b; } substruct_t; #ifdef NEED_EXTERNS extern "C" { // If get ncsim: *F,NOFDPI: Function {foo} not found in default libdpi. // Then probably forgot to list a function here. extern unsigned char dpii_f_bit(unsigned char i); extern svBitVecVal dpii_f_bit8(const svBitVecVal* i); extern svBitVecVal dpii_f_bit9(const svBitVecVal* i); extern svBitVecVal dpii_f_bit16(const svBitVecVal* i); extern svBitVecVal dpii_f_bit17(const svBitVecVal* i); extern svBitVecVal dpii_f_bit32(const svBitVecVal* i); extern long long dpii_f_bit33(const svBitVecVal* i); extern long long dpii_f_bit64(const svBitVecVal* i); extern long long dpii_f_bit95(const svBitVecVal* i, svBitVecVal* o); extern int dpii_f_int(int i); extern char dpii_f_byte(char i); extern short int dpii_f_shortint(short int i); extern long long dpii_f_longint(long long i); extern void* dpii_f_chandle(void* i); extern const char* dpii_f_string(const char* i); extern const char* dpii_f_null(); extern double dpii_f_real(double i); extern float dpii_f_shortreal(float i); extern void dpii_v_bit(unsigned char i, unsigned char* o); extern void dpii_v_int(int i, int* o); extern void dpii_v_uint(unsigned int i, unsigned int* o); extern void dpii_v_byte(char i, char* o); extern void dpii_v_shortint(short int i, short int* o); extern void dpii_v_ushort(unsigned short i, unsigned short* o); extern void dpii_v_longint(long long i, long long* o); extern void dpii_v_ulong(unsigned long long i, unsigned long long* o); extern void dpii_v_struct(const svBitVecVal* i, svBitVecVal* o); extern void dpii_v_substruct(const svBitVecVal* i, int* o); extern void dpii_v_chandle(void* i, void** o); extern void dpii_v_string(const char* i, const char** o); extern void dpii_v_real(double i, double* o); extern void dpii_v_shortreal(float i, float* o); extern void dpii_v_struct(const svBitVecVal* i, svBitVecVal* o); extern void dpii_v_substruct(const svBitVecVal* i, int* o); extern void dpii_v_bit64(const svBitVecVal* i, svBitVecVal* o); extern void dpii_v_bit95(const svBitVecVal* i, svBitVecVal* o); extern void dpii_v_bit96(const svBitVecVal* i, svBitVecVal* o); extern void dpii_v_reg(unsigned char i, unsigned char* o); extern void dpii_v_reg15(const svLogicVecVal* i, svLogicVecVal* o); extern void dpii_v_reg95(const svLogicVecVal* i, svLogicVecVal* o); extern void dpii_v_integer(const svLogicVecVal* i, svLogicVecVal* o); extern void dpii_v_time(const svLogicVecVal* i, svLogicVecVal* o); extern int dpii_f_strlen(const char* i); extern void dpii_f_void(); extern int dpii_t_void(); extern int dpii_t_void_context(); extern int dpii_t_int(int i, int* o); extern int dpii_fa_bit(int i); } #endif //====================================================================== unsigned char dpii_f_bit(unsigned char i) { return 0x1 & ~i; } svBitVecVal dpii_f_bit8(const svBitVecVal* i) { return 0xffUL & ~*i; } svBitVecVal dpii_f_bit9(const svBitVecVal* i) { return 0x1ffUL & ~*i; } svBitVecVal dpii_f_bit16(const svBitVecVal* i) { return 0xffffUL & ~*i; } svBitVecVal dpii_f_bit17(const svBitVecVal* i) { return 0x1ffffUL & ~*i; } svBitVecVal dpii_f_bit32(const svBitVecVal* i) { return ~*i; } long long dpii_f_bit33(const svBitVecVal* i) { return ((1ULL << 33) - 1) & ~((long long)(i[1]) << 32ULL | i[0]); } long long dpii_f_bit64(const svBitVecVal* i) { return ~((long long)(i[1]) << 32ULL | i[0]); } int dpii_f_int(int i) { return ~i; } char dpii_f_byte(char i) { return ~i; } short int dpii_f_shortint(short int i) { return ~i; } long long dpii_f_longint(long long i) { return ~i; } void* dpii_f_chandle(void* i) { return i; } const char* dpii_f_string(const char* i) { return i; } const char* dpii_f_null() { return nullptr; } double dpii_f_real(double i) { return i + 1.5; } float dpii_f_shortreal(float i) { return i + 1.5f; } void dpii_v_bit(unsigned char i, unsigned char* o) { *o = 1 & ~i; } void dpii_v_int(int i, int* o) { *o = ~i; } void dpii_v_uint(unsigned int i, unsigned int* o) { *o = ~i; } void dpii_v_byte(char i, char* o) { *o = ~i; } void dpii_v_shortint(short int i, short int* o) { *o = ~i; } void dpii_v_ushort(unsigned short i, unsigned short* o) { *o = ~i; } void dpii_v_longint(long long i, long long* o) { *o = ~i; } void dpii_v_ulong(unsigned long long i, unsigned long long* o) { *o = ~i; } void dpii_v_chandle(void* i, void** o) { *o = i; } void dpii_v_string(const char* i, const char** o) { *o = i; } void dpii_v_real(double i, double* o) { *o = i + 1.5; } void dpii_v_shortreal(float i, float* o) { *o = i + 1.5f; } void dpii_v_reg(unsigned char i, unsigned char* o) { *o = (~i) & 1; } void dpii_v_reg15(const svLogicVecVal* i, svLogicVecVal* o) { o[0].aval = (~i[0].aval) & 0x7fffUL; o[0].bval = 0; } void dpii_v_reg95(const svLogicVecVal* i, svLogicVecVal* o) { o[0].aval = (~i[0].aval); o[1].aval = (~i[1].aval); o[2].aval = (~i[2].aval) & 0x7fffffffUL; o[0].bval = 0; o[1].bval = 0; o[2].bval = 0; } void dpii_v_integer(const svLogicVecVal* i, svLogicVecVal* o) { o[0].aval = (~i[0].aval); o[0].bval = 0; } void dpii_v_time(const svLogicVecVal* i, svLogicVecVal* o) { o[0].aval = (~i[0].aval); o[1].aval = (~i[1].aval); o[0].bval = 0; o[1].bval = 0; } void dpii_v_struct(const svBitVecVal* i, svBitVecVal* o) { o[0] = ~i[0]; o[1] = ~i[1]; o[2] = ~i[2]; } void dpii_v_substruct(const svBitVecVal* i, int* o) { // To be most like other tools, this should automagically take the substruct_t // as an argument, and not require this cast... substruct_t* issp = (substruct_t*)i; o[0] = issp->b - issp->a; } void dpii_v_bit64(const svBitVecVal* i, svBitVecVal* o) { o[0] = ~i[0]; o[1] = ~i[1]; } void dpii_v_bit95(const svBitVecVal* i, svBitVecVal* o) { o[0] = (~i[0]); o[1] = (~i[1]); o[2] = (~i[2]) & 0x7fffffffUL; } void dpii_v_bit96(const svBitVecVal* i, svBitVecVal* o) { o[0] = ~i[0]; o[1] = ~i[1]; o[2] = ~i[2]; } int dpii_f_strlen(const char* i) { return strlen(i); } int dpii__under___score(int i) { return i + 1; } //====================================================================== void dpii_f_void() {} #ifdef VCS void dpii_t_void() {} void dpii_t_void_context() {} void dpii_t_int(int i, int* o) { *o = i; } #else int dpii_t_void() { return svIsDisabledState(); } int dpii_t_void_context() { return svIsDisabledState(); } int dpii_t_int(int i, int* o) { *o = i; bool disabled = svIsDisabledState(); // Tasks generally need this svAckDisabledState(); return disabled; } #endif int dpii_fa_bit(int i) { return ~i; } verilator-5.044/test_regress/t/t_altera_lpm_divide.py0000755000542200017500000000111115125463617023437 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module]) test.passes() verilator-5.044/test_regress/t/t_config_work.map0000644000542200017500000000046615125463617022440 0ustar mahmoudyfreeshell// -*- Verilog -*- // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // lib.map file: library nonelib none.sv, none*.sv, none/; // no matches verilator-5.044/test_regress/t/t_class_super_new2.py0000755000542200017500000000073415125463617023263 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_class_static_member_pkg.py0000755000542200017500000000073415125463617024651 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_debug_gate.v0000644000542200017500000000076315125463617021707 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Dotted reference that uses another dotted reference // as the select expression // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs o, // Inputs i ); input i; output o; sub sub (.i, .o); endmodule module sub(/*AUTOARG*/ // Outputs o, // Inputs i ); input i; output o; assign o = !i; endmodule verilator-5.044/test_regress/t/t_class_format.v0000644000542200017500000000214015125463617022265 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifdef verilator `define stop $stop `else `define stop `endif `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); class Cls; bit b; int i; bit [15:0] carray4 [4]; bit [64:0] cwide[2]; string name; real r; task debug(); $display("DEBUG: %s (@%0t) %s", this.name, $realtime, "message"); endtask endclass module t; initial begin Cls c; c = new; c.b = '1; c.i = 42; c.r = 2.2; c.name = "object_name"; c.carray4[0] = 16'h11; c.carray4[1] = 16'h22; c.carray4[2] = 16'h33; c.carray4[3] = 16'h44; $display("'%p'", c); c.carray4 = '{16'h911, 16'h922, 16'h933, 16'h944}; $display("'%p'", c); c.debug(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_func_no_parentheses_bad.v0000644000542200017500000000056615125463617024460 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 function static int func(); int cnt = 0; return ++cnt; endfunction module t; int a; initial begin a = func; $stop; end endmodule verilator-5.044/test_regress/t/t_no_std_pkg_bad.py0000755000542200017500000000121515125463617022735 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_no_std_bad.v" test.golden_filename = "t/t_no_std_bad.out" test.lint(fails=True, verilator_flags2=["--no-std-package", "-Wall"], expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_trace_complex_fst_sc.out0000644000542200017500000001134415125463617024346 0ustar mahmoudyfreeshell$date Sat Apr 5 13:56:23 2025 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end $attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $scope module $unit $end $var bit 1 ! global_bit $end $upscope $end $scope module t $end $var wire 1 " clk $end $var integer 32 # cyc [31:0] $end $var bit 2 $ v_strp [1:0] $end $var bit 4 % v_strp_strp [3:0] $end $var bit 2 & v_unip_strp [1:0] $end $var bit 2 ' v_arrp [2:1] $end $var bit 4 ( v_arrp_arrp [3:0] $end $var bit 4 ) v_arrp_strp [3:0] $end $var bit 1 * v_arru[1] $end $var bit 1 + v_arru[2] $end $var bit 1 , v_arru_arru[3][1] $end $var bit 1 - v_arru_arru[3][2] $end $var bit 1 . v_arru_arru[4][1] $end $var bit 1 / v_arru_arru[4][2] $end $var bit 2 0 v_arru_arrp[3] [2:1] $end $var bit 2 1 v_arru_arrp[4] [2:1] $end $var bit 2 2 v_arru_strp[3] [1:0] $end $var bit 2 3 v_arru_strp[4] [1:0] $end $var real 64 4 v_real $end $var real 64 5 v_arr_real[0] $end $var real 64 6 v_arr_real[1] $end $var longint 64 7 v_chandle [63:0] $end $var logic 64 8 v_str32x2 [63:0] $end $attrbegin misc 07 "" 1 $end $var int 32 9 v_enumed [31:0] $end $attrbegin misc 07 "" 1 $end $var int 32 : v_enumed2 [31:0] $end $attrbegin misc 07 "" 2 $end $var logic 3 ; v_enumb [2:0] $end $var logic 6 < v_enumb2_str [5:0] $end $var logic 8 = unpacked_array[-2] [7:0] $end $var logic 8 > unpacked_array[-1] [7:0] $end $var logic 8 ? unpacked_array[0] [7:0] $end $var bit 1 @ LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end $scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end $var parameter 32 A PARAM [31:0] $end $upscope $end $scope module p2 $end $var parameter 32 B PARAM [31:0] $end $upscope $end $scope module p3 $end $var parameter 32 C PARAM [31:0] $end $upscope $end $scope module unnamedblk1 $end $var integer 32 D b [31:0] $end $scope module unnamedblk2 $end $var integer 32 E a [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b00000000000000000000000000000000 E b00000000000000000000000000000000 D b00000000000000000000000000000011 C b00000000000000000000000000000010 B b00000000000000000000000000000100 A 0@ b00000000 ? b00000000 > b00000000 = b000000 < b000 ; b00000000000000000000000000000000 : b00000000000000000000000000000000 9 b0000000000000000000000000000000000000000000000000000000011111111 8 b0000000000000000000000000000000000000000000000000000000000000000 7 r0 6 r0 5 r0 4 b00 3 b00 2 b00 1 b00 0 0/ 0. 0- 0, 0+ 0* b0000 ) b0000 ( b00 ' b00 & b0000 % b00 $ b00000000000000000000000000000000 # 0" 1! $end #10 1" b00000000000000000000000000000001 # b11 $ b1111 % b11 & b11 ' b1111 ( b1111 ) b11 0 b11 1 b11 2 b11 3 r0.1 4 r0.2 5 r0.3 6 b0000000000000000000000000000000100000000000000000000000011111110 8 b00000000000000000000000000000001 9 b00000000000000000000000000000010 : b111 ; b00000000000000000000000000000101 D b00000000000000000000000000000101 E #15 0" #20 1" b110 ; b00000000000000000000000000000100 : b00000000000000000000000000000010 9 b0000000000000000000000000000001000000000000000000000000011111101 8 r0.6 6 r0.4 5 r0.2 4 b00 3 b00 2 b00 1 b00 0 b0000 ) b0000 ( b00 ' b00 & b0000 % b00 $ b00000000000000000000000000000010 # b111111 < #25 0" #30 1" b110110 < b00000000000000000000000000000011 # b11 $ b1111 % b11 & b11 ' b1111 ( b1111 ) b11 0 b11 1 b11 2 b11 3 r0.3 4 r0.6000000000000001 5 r0.8999999999999999 6 b0000000000000000000000000000001100000000000000000000000011111100 8 b00000000000000000000000000000011 9 b00000000000000000000000000000110 : b101 ; #35 0" #40 1" b100 ; b00000000000000000000000000001000 : b00000000000000000000000000000100 9 b0000000000000000000000000000010000000000000000000000000011111011 8 r1.2 6 r0.8 5 r0.4 4 b00 3 b00 2 b00 1 b00 0 b0000 ) b0000 ( b00 ' b00 & b0000 % b00 $ b00000000000000000000000000000100 # b101101 < #45 0" #50 1" b100100 < b00000000000000000000000000000101 # b11 $ b1111 % b11 & b11 ' b1111 ( b1111 ) b11 0 b11 1 b11 2 b11 3 r0.5 4 r1 5 r1.5 6 b0000000000000000000000000000010100000000000000000000000011111010 8 b00000000000000000000000000000101 9 b00000000000000000000000000001010 : b011 ; #55 0" #60 1" b010 ; b00000000000000000000000000001100 : b00000000000000000000000000000110 9 b0000000000000000000000000000011000000000000000000000000011111001 8 r1.8 6 r1.2 5 r0.6 4 b00 3 b00 2 b00 1 b00 0 b0000 ) b0000 ( b00 ' b00 & b0000 % b00 $ b00000000000000000000000000000110 # b011011 < #64 verilator-5.044/test_regress/t/t_sys_readmem_eof.py0000755000542200017500000000146115125463617023144 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') def gen(filename): # Generate using file to avoid missing newline in repository with open(filename, 'w', encoding="utf8") as fh: fh.write("// Generated by t_vthread.py\n") fh.write("1\n") fh.write("10\n") fh.write("20\n") fh.write("30") # No newline gen(test.obj_dir + "/dat.mem") test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_vlcov_nfound_bad.py0000755000542200017500000000123315125463617023310 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') test.run(fails=True, cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "t/t_NOT_FOUND"], logfile=test.run_log_filename, expect_filename=test.golden_filename, verilator_run=True) test.passes() verilator-5.044/test_regress/t/t_math_pow2.py0000755000542200017500000000073415125463617021705 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_class_extends_this3.v0000644000542200017500000000156415125463617023572 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef class Cls; class Base; class Inner; int value = 10; function void testBaseInner; if (value != 10) $stop; endfunction endclass int value = 1; Inner inner = new; function void testBase; if (value != 1) $stop; if (inner.value != 10) $stop; endfunction endclass class Cls extends Base; function void testDerived; if (value != 1) $stop; if (inner.value != 10) $stop; endfunction endclass module t; initial begin Cls c; c = new; c.testBase(); c.testDerived(); c.inner.testBaseInner(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_union_hard_bad.out0000644000542200017500000000054715125463617023117 0ustar mahmoudyfreeshell%Error: t/t_union_hard_bad.v:11:21: Hard packed union members must have equal size (IEEE 1800-2023 7.3.1) : ... note: In instance 't' 11 | bit [7 : 0] val1; | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_interface_missing_bad.out0000644000542200017500000000106315125463617024454 0ustar mahmoudyfreeshell%Error: t/t_interface_missing_bad.v:14:4: Can't find typedef/interface: 'foo_intf' 14 | foo_intf foo | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_interface_missing_bad.v:20:4: Cannot find file containing interface: 'foo_intf' 20 | foo_intf the_foo (); | ^~~~~~~~ %Error: t/t_interface_missing_bad.v:25:15: Found definition of 'the_foo' as a CELL but expected a variable 25 | .foo (the_foo) | ^~~~~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_process_propagation.v0000644000542200017500000000220715125463617023675 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 event evt1, evt2; class Foo; process p; bit event_received; function new(); p = process::self(); endfunction virtual task ewait(); @evt1 $display("Foo received event `evt1`"); event_received = 1; ->evt2; endtask endclass class Bar extends Foo; function new(); super.new(); $display("Constructing Bar"); endfunction virtual task ewait(); @evt1 $display("Bar received event `evt1`"); event_received = 1; endtask endclass module t(); initial begin process p; Foo foo; Bar bar; fork begin foo = new; foo.ewait(); end begin bar = new; p = process::self(); bar.ewait(); end join_none #1; p.kill(); ->evt1; @evt2 begin if (!foo.event_received) $stop; if (bar.event_received) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.044/test_regress/t/t_math_repl_bad.py0000755000542200017500000000076615125463617022573 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_lparam_assign_iface_typedef_nested_modules.py0000755000542200017500000000077115125463617030567 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_interface_ref_trace_inlb.py0000755000542200017500000000132215125463617024755 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_ref_trace.v" test.golden_filename = "t/t_interface_ref_trace.out" test.compile(v_flags2=['+define+NO_INLINE_B'], verilator_flags2=['--trace-structs --trace-vcd']) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_order_a.v0000644000542200017500000000321415125463617021226 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_order_a (/*AUTOARG*/ // Outputs m_from_clk_lev1_r, n_from_clk_lev2, o_from_com_levs11, o_from_comandclk_levs12, // Inputs clk, a_to_clk_levm3, b_to_clk_levm1, c_com_levs10, d_to_clk_levm2, one ); input clk; input [7:0] a_to_clk_levm3; input [7:0] b_to_clk_levm1; input [7:0] c_com_levs10; input [7:0] d_to_clk_levm2; input [7:0] one; output [7:0] m_from_clk_lev1_r; output [7:0] n_from_clk_lev2; output [7:0] o_from_com_levs11; output [7:0] o_from_comandclk_levs12; /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) reg [7:0] m_from_clk_lev1_r; // End of automatics // surefire lint_off ASWEBB // surefire lint_off ASWEMB wire [7:0] a_to_clk_levm1; wire [7:0] a_to_clk_levm2; wire [7:0] c_com_levs11; reg [7:0] o_from_comandclk_levs12; wire [7:0] n_from_clk_lev2; wire [7:0] n_from_clk_lev3; assign a_to_clk_levm1 = a_to_clk_levm2 + d_to_clk_levm2; assign a_to_clk_levm2 = a_to_clk_levm3 + 0; always @ (posedge clk) begin m_from_clk_lev1_r <= a_to_clk_levm1 + b_to_clk_levm1; end assign c_com_levs11 = c_com_levs10 + one; always @ (/*AS*/c_com_levs11 or n_from_clk_lev3) o_from_comandclk_levs12 = c_com_levs11 + n_from_clk_lev3; assign n_from_clk_lev2 = m_from_clk_lev1_r; assign n_from_clk_lev3 = n_from_clk_lev2; wire [7:0] o_from_com_levs11 = c_com_levs10 + 1; endmodule verilator-5.044/test_regress/t/t_enum_name3.v0000644000542200017500000000073015125463617021642 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jonathon Donaldson. // SPDX-License-Identifier: CC0-1.0 // bug855 module our; typedef enum logic {n,N} T_Flg_N; typedef struct packed { T_Flg_N N; } T_PS_Reg; T_PS_Reg PS = 1'b1; initial begin $write ("P:%s\n", PS.N.name); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_cover_toggle.v0000644000542200017500000001460115125463617022274 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef struct packed {logic a;} str_logic; module t (/*AUTOARG*/ // Inputs clk, check_real, check_array_real, check_string ); input clk; input real check_real; // Check issue #2741 input real check_array_real [1:0]; input string check_string; // Check issue #2766 typedef struct packed { union packed { logic ua; logic ub; } u; logic b; } str_t; reg toggle; initial toggle='0; logic _under_toggle = toggle; // For --coverage-underscore str_t stoggle; initial stoggle='0; str_logic strl; initial strl='0; union { real val1; // TODO use bit [7:0] here real val2; // TODO use bit [3:0] here } utoggle; const reg aconst = '0; reg [1:0][1:0] ptoggle; initial ptoggle=0; integer cyc; initial cyc=1; wire [7:0] cyc_copy = cyc[7:0]; wire toggle_up; typedef struct { int q[$]; } str_queue_t; str_queue_t str_queue; typedef struct packed { // verilator lint_off ASCRANGE bit [3:5] x; // verilator lint_on ASCRANGE bit [0:0] y; } str_bit_t; str_bit_t str_bit; str_bit_t [5:2] str_bit_arr; assign strl.a = clk; alpha a1 (/*AUTOINST*/ // Outputs .toggle_up (toggle_up), // Inputs .clk (clk), .toggle (toggle), .cyc_copy (cyc_copy[7:0])); alpha a2 (/*AUTOINST*/ // Outputs .toggle_up (toggle_up), // Inputs .clk (clk), .toggle (toggle), .cyc_copy (cyc_copy[7:0])); beta b1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle_up (toggle_up)); off o1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); param#(1) p1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); param#() p2 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); mod_struct i_mod_struct (/*AUTOINST*/ // Inputs .input_struct (strl)); reg [1:0] memory[121:110]; wire [1023:0] largeish = {992'h0, cyc}; // CHECK_COVER_MISSING(-1) always @ (posedge clk) begin if (cyc != 0) begin cyc <= cyc + 1; memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1; toggle <= '0; stoggle.u <= toggle; stoggle.b <= toggle; utoggle.val1 <= real'(cyc[7:0]); ptoggle[0][0] <= toggle; if (cyc == 3) begin str_queue.q.push_back(1); toggle <= '1; str_bit.x <= '1; str_bit.y <= '1; str_bit_arr[4].x <= '1; end if (cyc == 4) begin if (str_queue.q.size() != 1) $stop; toggle <= '0; str_bit.x[3] <= 0; str_bit.y[0] <= 0; str_bit_arr[4].x[3] <= 0; end else if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module alpha (/*AUTOARG*/ // Outputs toggle_up, // Inputs clk, toggle, cyc_copy ); // t.a1 and t.a2 collapse to a count of 2 input clk; input toggle; // CHECK_COVER(-1,"top.t.a*","toggle:0->1",2) // CHECK_COVER(-2,"top.t.a*","toggle:1->0",2) // (t.a1 and t.a2) input [7:0] cyc_copy; // CHECK_COVER(-1,"top.t.a*","cyc_copy[0]:0->1",12) // CHECK_COVER(-2,"top.t.a*","cyc_copy[0]:1->0",10) // CHECK_COVER(-3,"top.t.a*","cyc_copy[1]:0->1",6) // CHECK_COVER(-4,"top.t.a*","cyc_copy[1]:1->0",4) // CHECK_COVER(-5,"top.t.a*","cyc_copy[2]:0->1",2) // CHECK_COVER(-6,"top.t.a*","cyc_copy[2]:1->0",2) // CHECK_COVER(-7,"top.t.a*","cyc_copy[3]:0->1",2) // CHECK_COVER(-8,"top.t.a*","cyc_copy[3]:1->0",0) // CHECK_COVER(-9,"top.t.a*","cyc_copy[4]:0->1",0) // CHECK_COVER(-10,"top.t.a*","cyc_copy[4]:1->0",0) // CHECK_COVER(-11,"top.t.a*","cyc_copy[5]:0->1",0) // CHECK_COVER(-12,"top.t.a*","cyc_copy[5]:1->0",0) // CHECK_COVER(-13,"top.t.a*","cyc_copy[6]:0->1",0) // CHECK_COVER(-14,"top.t.a*","cyc_copy[6]:1->0",0) // CHECK_COVER(-15,"top.t.a*","cyc_copy[7]:0->1",0) // CHECK_COVER(-16,"top.t.a*","cyc_copy[7]:1->0",0) reg toggle_internal; // CHECK_COVER(-1,"top.t.a*","toggle_internal:0->1",2) // CHECK_COVER(-2,"top.t.a*","toggle_internal:1->0",2) // (t.a1 and t.a2) output reg toggle_up; // CHECK_COVER(-1,"top.t.a*","toggle_up:0->1",2) // CHECK_COVER(-2,"top.t.a*","toggle_up:1->0",2) // (t.a1 and t.a2) always @ (posedge clk) begin toggle_internal <= toggle; toggle_up <= toggle; end endmodule module beta (/*AUTOARG*/ // Inputs clk, toggle_up ); input clk; input toggle_up; // CHECK_COVER(-1,"top.t.b1","toggle_up:0->1",1) // CHECK_COVER(-2,"top.t.b1","toggle_up:1->0",1) /* verilator public_module */ always @ (posedge clk) begin if (0 && toggle_up) begin end end endmodule module off (/*AUTOARG*/ // Inputs clk, toggle ); // verilator coverage_off input clk; // CHECK_COVER_MISSING(-1) // verilator coverage_on input toggle; // CHECK_COVER(-1,"top.t.o1","toggle:0->1",1) // CHECK_COVER(-2,"top.t.o1","toggle:1->0",1) endmodule module param #(parameter P = 2) (/*AUTOARG*/ // Inputs clk, toggle ); input clk; input toggle; logic z; for (genvar i = 0; i < P; i++) begin logic x; always @ (posedge clk) begin x <= toggle; end for (genvar j = 0; j < 3; j++) begin logic [2:0] y; always @ (negedge clk) begin y <= {toggle, ~toggle, 1'b1}; end end end if (P > 1) begin : gen_1 assign z = 1; end endmodule module mod_struct(/*AUTOARG*/ // Inputs input_struct ); input str_logic input_struct; endmodule verilator-5.044/test_regress/t/t_alias_transitive.v0000644000542200017500000000131015125463617023147 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' // // Simple bi-directional transitive alias test. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ // Inputs clk ); input clk; wire [31:0] a = 32'hdeadbeef; wire [31:0] b; wire [31:0] c; alias a = b = c; always @(posedge clk) begin `ifdef TEST_VERBOSE $write("a = %x, b = %x, c = %x\n", a, b, c); `endif if (a != 32'hdeadbeef) $stop; if (b != 32'hdeadbeef) $stop; if (c != 32'hdeadbeef) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_interface_derived_type.v0000644000542200017500000000302615125463617024317 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: SystemVerilog interface test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 interface intf #( parameter type data_t = bit, parameter int arr[2][4] ) (); data_t data; // TODO -- some kind of issue with multi-dimensional array constness: // %Error: t/t_interface_derived_type.v:12:12: Expecting expression to be constant, but variable isn't const: 'arr' // : ... note: In instance 't.sub16' // 19 | logic [arr[0][0]-1:0] other_data; // | ^~~ // `define SHOW_2D_BUG `ifdef SHOW_2D_BUG logic [arr[0][0]-1:0] other_data; `else logic [$bits(data)-1:0] other_data; `endif endinterface module t (/*AUTOARG*/ // Inputs clk ); input clk; // finish report always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end sub #(.width(8), .arr('{'{8, 2, 3, 4}, '{1, 2, 3, 4}})) sub8 (); sub #(.width(16), .arr('{'{16, 2, 3, 4}, '{1, 2, 3, 4}})) sub16 (); endmodule module sub #( parameter int width, parameter int arr[2][4] ) (); typedef struct packed { logic [3:3] [0:0] [width-1:0] field; } user_type_t; intf #( .data_t(user_type_t), .arr(arr) ) the_intf (); logic [width-1:0] signal; always_comb begin the_intf.data.field = signal; the_intf.other_data = signal; end endmodule verilator-5.044/test_regress/t/t_vpi_release_dup_bad.py0000755000542200017500000000117515125463617023761 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(v_flags2=["t/" + test.name + "_c.cpp"], verilator_flags2=['--vpi']) test.execute(fails=True) test.file_grep(test.run_log_filename, r'vpi_release_handle.*called on same object twice') test.passes() verilator-5.044/test_regress/t/t_var_xref_bad.v0000644000542200017500000000044715125463617022242 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; task tsk; endtask initial tsk.bad_missing_ref = 0; endmodule verilator-5.044/test_regress/t/t_class_hier_construction.py0000755000542200017500000000073415125463617024733 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_display_concat2.v0000644000542200017500000000121515125463617022670 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module test( /*AUTOARG*/ // Inputs clk ); input clk; int cnt = 32'h12345678; int cyc = 0; always @(posedge clk) begin if (cyc > 3) begin $write("*-* All Finished *-*\n"); $finish; end else begin cyc <= cyc + 1; cnt <= cnt + 1; $write("%08x\n", {16'h0, cnt[15: 0]}); $write("%08x\n", {16'h0, cnt[31:16]}); end end endmodule verilator-5.044/test_regress/t/t_assert_synth_full.out0000644000542200017500000000057315125463617023732 0ustar mahmoudyfreeshell[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test [0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test [0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test [40] %Error: t_assert_synth.v:31: Assertion failed in top.t: synthesis full_case, but non-match found for '2'h3' %Error: t/t_assert_synth.v:31: Verilog $stop Aborting... verilator-5.044/test_regress/t/t_savable_open_bad2.cpp0000644000542200017500000000204215125463617023454 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include #include #include VM_PREFIX_INCLUDE // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" //====================================================================== unsigned int main_time = 0; int errors = 0; double sc_time_stamp() { return main_time; } int main(int argc, char* argv[]) { Verilated::debug(0); Verilated::commandArgs(argc, argv); // No need to make a model: topp = new VM_PREFIX; { VerilatedSave os; os.open("/No/such_file_as_this"); TEST_CHECK_EQ(os.isOpen(), false); } { VerilatedRestore os; os.open("/No/such_file_as_this"); TEST_CHECK_EQ(os.isOpen(), false); } return errors ? 10 : 0; } verilator-5.044/test_regress/t/t_unopt_array.py0000755000542200017500000000101315125463617022337 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-Wno-UNOPTFLAT", "-fno-dfg"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_order_dpi_export_6.v0000644000542200017500000000254115125463617023412 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2022 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module testbench( /*AUTOARG*/ // Inputs clk ); input clk; // Top level input clock bit other_clk; // Dependent clock set via DPI export "DPI-C" function set_other_clk; function void set_other_clk(bit val); other_clk = val; endfunction; bit even_other = 1; bit current_even_other = 1; import "DPI-C" context function void toggle_other_clk(bit val); always @(posedge clk) begin even_other <= ~even_other; current_even_other = even_other; toggle_other_clk(even_other); end int n = 0; always @(edge other_clk) begin // This always block needs to evaluate before the NBA to even_other // above is committed, as setting clocks via the set_other_clk uses // blocking assignment. if (even_other !== current_even_other) $stop; $display("[%0t] n=%0d", $time, n); if ($time != (2*n+1) * 500) $stop; if (n == 20) begin $write("*-* All Finished *-*\n"); $finish; end n += 1; end endmodule verilator-5.044/test_regress/t/t_premit_rw.py0000755000542200017500000000073515125463617022016 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() #test.execute() test.passes() verilator-5.044/test_regress/t/t_sys_readmem_bad_digit.mem0000644000542200017500000000053415125463617024424 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 a0 verilator-5.044/test_regress/t/t_wire_behp1800_bad.v0000644000542200017500000000136215125463617022700 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( output o, output [1:0] oa, output reg ro, output reg [1:0] roa, output wire wo, output wire [1:0] woa, // 1800 only output var vo, output var [1:0] voa ); wire w; reg r; initial begin w = '0; // Error o = '0; // Error oa = '0; // Error wo = '0; // Error woa = '0; // Error r = '0; // Not an error ro = '0; // Not an error roa = '0; // Not an error vo = '0; // Not an error voa = '0; // Not an error end endmodule verilator-5.044/test_regress/t/t_lint_paramnodefault.py0000755000542200017500000000077615125463617024043 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=['-Wno-PARAMNODEFAULT']) test.execute() test.passes() verilator-5.044/test_regress/t/t_config_include_bad.out0000644000542200017500000000124615125463617023736 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_config_include_bad.v:7:1: Unsupported: IEEE 1800-2001-config lib.map reserved word not implemented: 'include' : ... Suggest unless in a lib.map file, want `include instead 7 | include "meant_to_tick_include.v" | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: t/t_config_include_bad.v:7:9: syntax error, unexpected STRING 7 | include "meant_to_tick_include.v" | ^~~~~~~~~~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_trace_fst_sc.py0000755000542200017500000000117215125463617022441 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') if not test.have_sc: test.skip("No SystemC installed") test.compile(verilator_flags2=["--trace-fst --sc"]) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_mod_interface_array4_noinl.py0000755000542200017500000000104515125463617025261 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_mod_interface_array4.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_force_bad_rw.v0000644000542200017500000000071415125463617022231 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; int ass[int]; initial begin ass[2] = 20; foreach (ass[index]) begin force index = 0; $display("ii %d\n", index); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_do_while_continue_bad.out0000644000542200017500000000060015125463617024455 0ustar mahmoudyfreeshell%Warning-INFINITELOOP: t/t_do_while_continue_bad.v:14:7: Infinite loop (condition always true) 14 | do begin | ^~ ... For warning description see https://verilator.org/warn/INFINITELOOP?v=latest ... Use "/* verilator lint_off INFINITELOOP */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.044/test_regress/t/t_static_elab.v0000644000542200017500000000213515125463617022066 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Simple static elaboration case // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module t; typedef struct packed { logic [ 31 : 0 ] _five; } five_t; typedef enum { LOW_FIVE = 32'hdeadbeef, HIGH_FIVE } five_style_t; function five_t gimme_five (); automatic five_t result; result._five = 5; return result; endfunction function five_style_t gimme_high_five (); automatic five_style_t result; result = HIGH_FIVE; return result; endfunction localparam five_t FIVE = gimme_five(); localparam five_style_t THE_HIGH_FIVE = gimme_high_five(); initial begin if (FIVE._five != 5) begin $display("%%Error: Got 0b%b instead of 5", FIVE._five); $stop; end if (THE_HIGH_FIVE != HIGH_FIVE) begin $display("%%Error: Got 0b%b instead of HIGH_FIVE", THE_HIGH_FIVE); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_flag_lib_dpi.v0000644000542200017500000000053615125463617022212 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Shupei Fan. // SPDX-License-Identifier: CC0-1.0 import "DPI-C" function void write_all_finished(); module t; initial begin write_all_finished; $finish; end endmodule verilator-5.044/test_regress/t/t_func_automatic_clear.v0000644000542200017500000000723715125463617023773 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test automatic function variables lifetime // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Augustin Fabre. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on // Bug5747: Make sure that a variable with automatic storage is freshly // allocated when entering the function. module t(); function automatic int ts_queue(); static int qs[$]; qs.push_back(0); // $display(" qs: %p", qs); return qs.size(); endfunction function automatic int t_queue(); int q[$]; q.push_back(0); // $display(" q: %p", q); return q.size(); endfunction function automatic int t_scalar(); int x; ++x; return x; endfunction typedef struct { int y; } y_t; function automatic int t_struct(); y_t y; ++y.y; return y.y; endfunction function automatic string t_string(); string x; x = {x, "s"}; return x; endfunction class ClsZ; int z; endclass function automatic int t_class(); ClsZ z = new(); ++z.z; return z.z; endfunction typedef string dyn_t[]; function automatic dyn_t t_dyn(); dyn_t x; x = {x, "s"}; return x; endfunction typedef string assoc_t[int]; function automatic assoc_t t_assoc(); static int ins = 0; assoc_t x; ins = ins + 1; x[ins] = "s"; return x; endfunction typedef string wild_t[*]; function automatic wild_t t_wild(); static int ins = 0; wild_t x; ins = ins + 1; x[ins] = "s"; return x; endfunction typedef int unpack_t[8]; function automatic unpack_t t_unpack(); static int ins = 0; unpack_t x; ins = ins + 1; x[ins] = ins; return x; endfunction // ======================= function automatic void main(); for (int i = 0; i < 3; ++i) begin int qn = ts_queue(); int qo = ts_queue(); `checkh(qn, i * 2 + 1); `checkh(qo, i * 2 + 2); end for (int i = 0; i < 3; ++i) begin int qn = t_queue(); `checkh(qn, 1); end for (int i = 0; i < 3; ++i) begin int x = t_scalar(); `checkh(x, 1); end for (int i = 0; i < 3; ++i) begin int y = t_struct(); `checkh(y, 1); end for (int i = 0; i < 3; ++i) begin int z = t_class(); `checkh(z, 1); end for (int i = 0; i < 3; ++i) begin string z = t_string(); `checks(z, "s"); end for (int i = 0; i < 3; ++i) begin dyn_t z = t_dyn(); `checkh(z.size(), 1); end for (int i = 0; i < 3; ++i) begin assoc_t z = t_assoc(); `checkh(z.size(), 1); end for (int i = 0; i < 3; ++i) begin wild_t z = t_wild(); `checkh(z.size(), 1); end for (int i = 0; i < 3; ++i) begin int cnt; unpack_t z = t_unpack(); cnt = 0; for (int j = 0; j < $high(z); ++j) begin if (z[j] != 0) cnt = cnt + 1; end `checkh(cnt, 1); end endfunction initial begin main(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_flag_f__2.vc0000644000542200017500000000012415125463617021551 0ustar mahmoudyfreeshell +define+GOT_DEF1 // -DNON_DEF /* +define+NON_DEF */ +define+GOT_DEF2=1 verilator-5.044/test_regress/t/t_typedef_fwd_class.v0000644000542200017500000000114415125463617023300 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef logic [3:0] T; class Cls; extern static function int f(T x); // This is after the usage above, but to match other simulators, // no error about use after declaration typedef logic [7:0] T; endclass function int Cls::f(T x); return $bits(x); endfunction module t; initial begin if (Cls::f('1) != 8) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_func_wide_out.py0000755000542200017500000000111315125463617022627 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-Wno-WIDTHTRUNC"], v_flags2=["+define+T_FUNC_WIDE_OUT t/t_func_wide_out_c.cpp"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_alw_reorder_inlined_func.v0000644000542200017500000000273415125463617024643 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: $time=%0t got='h%x exp='h%x\n", `__FILE__,`__LINE__, $time, (got), (exp)); `stop; end while(0) // verilog_format: on module t; logic clk = 0; always #5 clk = ~clk; int cyc = 0; always @(posedge clk) cyc <= cyc + 1; // Constant 1 set in initial block, but not known at compile time logic enable = 1'b0; int array[32]; function automatic int get(logic en, logic [4:0] idx); if (en) begin // Always taken, but need the 'if' to show bug int tmp; idx = ~idx; tmp = array[~idx]; return tmp; end else begin return 0; end endfunction int q; always @(posedge clk) begin // Function inlined on RHS or NBA used to have its body reordered as if // assignments in the body were NBAs themselves. q <= cyc == 0 ? 0 : get(enable, 5'(cyc)); end initial begin enable = 1'b1; for (int n = 0; n < 32; ++n) begin array[n] = 100 + n; end repeat (100) begin @(posedge clk); #1; $display("$08t %3d %3d", $time, cyc - 1, q); `check(q, cyc == 1 ? 0 : 100 + (cyc - 1) % 32); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_func_ref_bad.py0000755000542200017500000000103015125463617022370 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["-fno-var-split"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_interface_modport_noinl.py0000755000542200017500000000104215125463617024701 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_modport.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_vpi_release_dup_bad_c.cpp0000644000542200017500000000224515125463617024411 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2011 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include "vpi_user.h" #include //#include "verilated.h" #include "Vt_vpi_release_dup_bad__Dpi.h" //====================================================================== void dpii_check() { vpiHandle mod; // Not TestVpiHandle as testing double free // Verilated::scopesDump(); mod = vpi_handle_by_name((PLI_BYTE8*)"top.t", NULL); if (!mod) vpi_printf(const_cast("-- Cannot vpi_find module\n")); #ifdef VL_NO_LEGACY vpi_release_handle(mod); vpi_release_handle(mod); #else vpi_free_object(mod); // using vpi_free_object instead of vpi_release_handle for coverage vpi_free_object(mod); // error: double free #endif } verilator-5.044/test_regress/t/t_wrapper_del_context_bad.v0000644000542200017500000000040015125463617024463 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module top; initial $finish; endmodule verilator-5.044/test_regress/t/t_select_ascending.v0000644000542200017500000000444215125463617023111 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // verilator lint_off ASCRANGE wire [10:41] sel2 = crc[31:0]; wire [10:100] sel3 = {crc[26:0],crc}; wire out20 = sel2[{1'b0,crc[3:0]} + 11]; wire [3:0] out21 = sel2[13 : 16]; wire [3:0] out22 = sel2[{1'b0,crc[3:0]} + 20 +: 4]; wire [3:0] out23 = sel2[{1'b0,crc[3:0]} + 20 -: 4]; wire out30 = sel3[{2'b0,crc[3:0]} + 11]; wire [3:0] out31 = sel3[13 : 16]; wire [3:0] out32 = sel3[crc[5:0] + 20 +: 4]; wire [3:0] out33 = sel3[crc[5:0] + 20 -: 4]; // Aggregate outputs into a single result vector wire [63:0] result = {38'h0, out20, out21, out22, out23, out30, out31, out32, out33}; reg [19:50] sel1; initial begin // Path clearing // 122333445 // 826048260 sel1 = 32'h12345678; if (sel1 != 32'h12345678) $stop; if (sel1[47 : 50] != 4'h8) $stop; if (sel1[31 : 34] != 4'h4) $stop; if (sel1[27 +: 4] != 4'h3) $stop; //==[27:30], in memory as [23:20] if (sel1[26 -: 4] != 4'h2) $stop; //==[23:26], in memory as [27:24] end // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] sels=%x,%x,%x,%x %x,%x,%x,%x\n", $time, out20,out21,out22,out23, out30,out31,out32,out33); $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; `define EXPECTED_SUM 64'h28bf65439eb12c00 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.044/test_regress/t/t_vlt_warn_one_on_bad.py0000755000542200017500000000102015125463617023771 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=['--Wall'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_flag_main_top_name_empty.py0000755000542200017500000000132215125463617025014 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_flag_main_top_name.v" test.compile(verilator_flags=["-Mdir " + test.obj_dir, "--exe", "--build", "--main"], verilator_flags2=["--top-module top", "--main-top-name -", "-DMAIN_TOP_NAME_EMPTY"], make_main=False) test.execute() test.passes() verilator-5.044/test_regress/t/t_randsequence_bad.out0000644000542200017500000000152515125463617023443 0ustar mahmoudyfreeshell%Error: t/t_randsequence_bad.v:23:7: Duplicate declaration of randsequence production: 'duplicated_bad' 23 | duplicated_bad: { $display("dup2"); }; | ^~~~~~~~~~~~~~ t/t_randsequence_bad.v:22:7: ... Location of original declaration 22 | duplicated_bad: { $display("dup1"); }; | ^~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_randsequence_bad.v:12:5: Production 'no_such_production' not found : ... Suggested alternative: 'such_production' 12 | randsequence(no_such_production) | ^~~~~~~~~~~~ %Error: t/t_randsequence_bad.v:17:13: Production 'production_bad' not found 17 | main: production_bad; | ^~~~~~~~~~~~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_constraint_xml.py0000755000542200017500000000136415125463617023051 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') out_filename = test.obj_dir + "/V" + test.name + ".xml" test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only', '-Wno-CONSTRAINTIGN'], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.files_identical(out_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_covergroup_with_sample_args_too_many_bad.py0000755000542200017500000000077115125463617030324 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_structu_dataType_assignment_bad.py0000755000542200017500000000103515125463617026402 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--structs-packed'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_inst_param_comma_bad.py0000755000542200017500000000076615125463617024131 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_force_release_net_trace.out0000644000542200017500000000431415125463617025001 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 # clk $end $scope module t $end $var wire 1 # clk $end $var wire 32 $ cyc [31:0] $end $var wire 1 % net_1 $end $var wire 8 & net_8 [7:0] $end $var wire 8 & alias_net_8 [7:0] $end $upscope $end $upscope $end $enddefinitions $end #0 0# b00000000000000000000000000000000 $ 1% b11111111 & #10 1# b00000000000000000000000000000001 $ 0% #15 0# #20 1# b00000000000000000000000000000010 $ 1% b11111110 & #25 0# #30 1# b00000000000000000000000000000011 $ 0% #35 0# #40 1# b00000000000000000000000000000100 $ b11111101 & #45 0# #50 1# b00000000000000000000000000000101 $ b01011111 & #55 0# #60 1# b00000000000000000000000000000110 $ 1% #65 0# #70 1# b00000000000000000000000000000111 $ b11110101 & #75 0# #80 1# b00000000000000000000000000001000 $ #85 0# #90 1# b00000000000000000000000000001001 $ 0% #95 0# #100 1# b00000000000000000000000000001010 $ 1% b11111010 & #105 0# #110 1# b00000000000000000000000000001011 $ b01011010 & #115 0# #120 1# b00000000000000000000000000001100 $ #125 0# #130 1# b00000000000000000000000000001101 $ 0% b10100101 & #135 0# #140 1# b00000000000000000000000000001110 $ #145 0# #150 1# b00000000000000000000000000001111 $ b11111000 & #155 0# #160 1# b00000000000000000000000000010000 $ 1% b11110111 & #165 0# #170 1# b00000000000000000000000000010001 $ 0% #175 0# #180 1# b00000000000000000000000000010010 $ 1% b11110110 & #185 0# #190 1# b00000000000000000000000000010011 $ 0% #195 0# #200 1# b00000000000000000000000000010100 $ 1% b11110101 & #205 0# #210 1# b00000000000000000000000000010101 $ 0% #215 0# #220 1# b00000000000000000000000000010110 $ 1% b11110100 & #225 0# #230 1# b00000000000000000000000000010111 $ 0% #235 0# #240 1# b00000000000000000000000000011000 $ 1% b11110011 & #245 0# #250 1# b00000000000000000000000000011001 $ 0% #255 0# #260 1# b00000000000000000000000000011010 $ 1% b11110010 & #265 0# #270 1# b00000000000000000000000000011011 $ 0% #275 0# #280 1# b00000000000000000000000000011100 $ 1% b11110001 & #285 0# #290 1# b00000000000000000000000000011101 $ 0% #295 0# #300 1# b00000000000000000000000000011110 $ 1% b11110000 & #305 0# #310 1# b00000000000000000000000000011111 $ 0% verilator-5.044/test_regress/t/t_probdist_bad.v0000644000542200017500000000207515125463617022253 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; integer seed; integer r; initial begin // Illegal values r = $dist_chi_square(seed, 0); if (r != 0 && !$isunknown(r)) $stop; r = $dist_erlang(seed, 0, 0); if (r != 0 && !$isunknown(r)) $stop; r = $dist_exponential(seed, 0); if (r != 0 && !$isunknown(r)) $stop; // r =$dist_exponential(seed, mean); // Always valid r = $dist_poisson(seed, 0); if (r != 0 && !$isunknown(r)) $stop; r = $dist_t(seed, 0); if (r != 0 && !$isunknown(r)) $stop; r = $dist_uniform(seed, 10, 0); if (r != 10 && !$isunknown(r)) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_disable_genfor_unsup.out0000644000542200017500000000101215125463617024344 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_disable_genfor_unsup.v:13:23: Unsupported: Generate block referenced by disable 13 | if (i == 5) disable t.genblk[0].init.named; | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_disable_genfor_unsup.v:13:23: Node of type CELLREF referenced by disable 13 | if (i == 5) disable t.genblk[0].init.named; | ^~~~~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_strength_assignments_constants.v0000644000542200017500000000173715125463617026170 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; wire a; assign (weak0, weak1) a = 1; assign (weak0, supply1) a = 1; assign (strong0, strong1) a = 0; wire (weak0, weak1) b = 1; assign (strong0, strong1) b = 0; wire [1:0] c; assign (weak0, supply1) c = 2'b11; assign (supply0, pull1) c = 2'b11; assign (strong0, strong1) c = 0; wire [1:0] cr; assign (supply1, weak0) cr = 2'b11; assign (pull1, supply0) cr = 2'b11; assign (strong1, strong0) cr = 0; supply0 d; assign (strong0, strong1) d = 1; wire (supply0, supply1) e = 1'bz; assign (weak0, weak1) e = 1; always begin if (a !== 1'b1) $stop; if (b !== 1'b0) $stop; if (c !== 2'b11) $stop; if (cr !== 2'b11) $stop; if (e !== 1'b1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_func_const3_bad.out0000644000542200017500000000100415125463617023202 0ustar mahmoudyfreeshell%Warning-WIDTHCONCAT: t/t_func_const3_bad.v:12:28: More than a 8k bit replication is probably wrong: 9000 : ... note: In instance 't.b9k.c9' 12 | localparam SOMEP = {BITS{1'b0}}; | ^ ... For warning description see https://verilator.org/warn/WIDTHCONCAT?v=latest ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.044/test_regress/t/t_mod_interface_array6_noinl.py0000755000542200017500000000104515125463617025263 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_mod_interface_array6.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_notiming_off.py0000755000542200017500000000110215125463617022451 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_timing_off.v" test.lint(verilator_flags2=["--no-timing"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_dpi_context_noopt.py0000755000542200017500000000114715125463617023543 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_dpi_context.v" test.compile(v_flags2=["t/t_dpi_context_c.cpp"], verilator_flags2=[("-O0" if test.vlt_all else "")]) test.execute() test.passes() verilator-5.044/test_regress/t/t_func_outfirst.v0000644000542200017500000000604315125463617022510 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define DDIFF_BITS 9 `define AOA_BITS 8 `define HALF_DDIFF `DDIFF_BITS'd256 `define MAX_AOA `AOA_BITS'd255 `define BURP_DIVIDER 9'd16 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [`DDIFF_BITS-1:0] DDIFF_B = crc[`DDIFF_BITS-1:0]; wire reset = (cyc<7); /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [`AOA_BITS-1:0] AOA_B; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .AOA_B (AOA_B[`AOA_BITS-1:0]), // Inputs .DDIFF_B (DDIFF_B[`DDIFF_BITS-1:0]), .reset (reset), .clk (clk)); // Aggregate outputs into a single result vector wire [63:0] result = {56'h0, AOA_B}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h3a74e9d34771ad93 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs AOA_B, // Inputs DDIFF_B, reset, clk ); input [`DDIFF_BITS-1:0] DDIFF_B; input reset; input clk; output reg [`AOA_BITS-1:0] AOA_B; reg [`AOA_BITS-1:0] AOA_NEXT_B; reg [`AOA_BITS-1:0] tmp; always @(posedge clk) begin if (reset) begin AOA_B <= 8'h80; end else begin AOA_B <= AOA_NEXT_B; end end always @* begin // verilator lint_off WIDTH tmp = ((`HALF_DDIFF-DDIFF_B)/`BURP_DIVIDER); t_aoa_update(AOA_NEXT_B, AOA_B, ((`HALF_DDIFF-DDIFF_B)/`BURP_DIVIDER)); // verilator lint_on WIDTH end task t_aoa_update; output [`AOA_BITS-1:0] aoa_reg_next; input [`AOA_BITS-1:0] aoa_reg; input [`AOA_BITS-1:0] aoa_delta_update; begin if ((`MAX_AOA-aoa_reg)= 0); endmodule verilator-5.044/test_regress/t/t_uniqueif_fail2.out0000644000542200017500000000021515125463617023055 0ustar mahmoudyfreeshell[10] %Error: t_uniqueif.v:82: Assertion failed in top.t: 'unique if' statement violated %Error: t/t_uniqueif.v:82: Verilog $stop Aborting... verilator-5.044/test_regress/t/t_std_randomize_mod.py0000755000542200017500000000071115125463617023501 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.lint() test.passes() verilator-5.044/test_regress/t/t_order_blkandnblk_bad.v0000644000542200017500000000125515125463617023721 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test of select from constant // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs o, // Inputs clk, i, idx ); input clk; input [3:0] i; input idx; output [3:0] o; logic [1:0][3:0] array; always_comb array[0] = i; always @ (posedge clk) array[0] <= array[0]; struct { logic [3:0] a; logic [3:0] b; } unpacked; always_comb unpacked.a = i; always @ (posedge clk) unpacked.b <= unpacked.a; assign o = array[idx] + unpacked.a; endmodule verilator-5.044/test_regress/t/t_math_cond_clean.v0000644000542200017500000000454615125463617022722 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [3:0] cnt = crc[3:0]; wire [6:0] decr = crc[14:8]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [3:0] next; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .next (next[3:0]), // Inputs .cnt (cnt[3:0]), .decr (decr[6:0])); // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, next}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc<10) begin sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h7cd85c944415d2ef if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs next, // Inputs cnt, decr ); input [3:0] cnt; input signed [6:0] decr; output reg [3:0] next; always_comb begin reg signed [6:0] tmp; tmp = 0; // verilator lint_off WIDTH tmp = ($signed({1'b0, cnt}) - decr); // verilator lint_on WIDTH if ((tmp > 15)) begin next = 15; end else if ((tmp < 0)) begin next = 0; end else begin next = tmp[3:0]; end end endmodule verilator-5.044/test_regress/t/t_dfg_peephole.py0000755000542200017500000000772315125463617022433 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.sim_time = 2000000 test.top_filename = "t/t_dfg_peephole.v" if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") # Read optimizations optimizations = [] hdrFile = "../src/V3DfgPeepholePatterns.h" with open(hdrFile, 'r', encoding="utf8") as hdrFh: prevOpt = "" lineno = 0 for line in hdrFh: lineno += 1 m = re.search(r'^\s*_FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY\(macro, (\w+)\)', line) if not m: continue opt = m.group(1) if prevOpt > opt: test.error(hdrFile + ":" + str(lineno) + ": '" + opt + "; is not in sorted order") prevOpt = opt optimizations.append(opt) if len(optimizations) < 1: test.error("no optimizations defined in " + hdrFile) # Generate the equivalence checks and declaration boilerplate rdFile = test.top_filename plistFile = test.obj_dir + "/portlist.vh" pdeclFile = test.obj_dir + "/portdecl.vh" checkFile = test.obj_dir + "/checks.h" with open(rdFile, 'r', encoding="utf8") as rdFh, \ open(plistFile, 'w', encoding="utf8") as plistFh, \ open(pdeclFile, 'w', encoding="utf8") as pdeclFh, \ open(checkFile, 'w', encoding="utf8") as checkFh: for line in rdFh: m = re.search(r'^\s*.*`signal\((\w+),', line) if not m: continue sig = m.group(1) plistFh.write(sig + ",\n") pdeclFh.write("output " + sig + ";\n") checkFh.write("if (ref." + sig + " != opt." + sig + ") {\n") checkFh.write(" std::cout << \"Mismatched " + sig + "\" << std::endl;\n") checkFh.write(" std::cout << \"Ref: 0x\" << std::hex << (ref." + sig + " + 0) << std::endl;\n") checkFh.write(" std::cout << \"Opt: 0x\" << std::hex << (opt." + sig + " + 0) << std::endl;\n") checkFh.write(" std::exit(1);\n") checkFh.write("}\n") # Compile un-optimized test.compile(verilator_flags2=[ "--stats", "--build", "-fno-dfg", "+incdir+" + test.obj_dir, "-Mdir", test.obj_dir + "/obj_ref", "--prefix", "Vref" ]) # yapf:disable # Compile optimized - also builds executable extraArgs = [] if test.name == "t_dfg_peephole_off_all": extraArgs.append("-fno-dfg-peephole") if test.name == "t_dfg_peephole_off_each": for opt in optimizations: opt = opt.lower() opt = re.sub(r"_", "-", opt) extraArgs.append("-fno-dfg-peephole-" + opt) test.compile(verilator_flags2=[ "--stats", "--build", "--exe", "+incdir+" + test.obj_dir, "-Mdir", test.obj_dir + "/obj_opt", "--prefix", "Vopt", "-fno-const-before-dfg", # Otherwise V3Const makes testing painful "-fdfg-synthesize-all", "--dump-dfg", # To fill code coverage "-CFLAGS \"-I .. -I ../obj_ref\"", "../obj_ref/Vref__ALL.a", "../../t/t_dfg_peephole.cpp" ] + extraArgs) # yapf:disable def check(name, enabled): name = name.lower() name = re.sub(r'_', ' ', name) pattern = r'DFG\s+(pre inline|post inline|scoped) Peephole, ' + name + r'\s+([1-9]\d*)\s*$' if enabled: test.file_grep(test.obj_dir + "/obj_opt/Vopt__stats.txt", pattern) else: test.file_grep_not(test.obj_dir + "/obj_opt/Vopt__stats.txt", pattern) # Check all optimizations defined in for opt in optimizations: check(opt, test.name == "t_dfg_peephole") test.file_grep_not(test.obj_dir + "/obj_opt/Vopt__stats.txt", r'DFG.*non-representable.*\s[1-9]\d*$') # Execute test to check equivalence test.execute(executable=test.obj_dir + "/obj_opt/Vopt") test.passes() verilator-5.044/test_regress/t/t_genfor_init_o0.py0000755000542200017500000000101315125463617022675 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=['-O0'], make_main=False, verilator_make_gmake=False) test.passes() verilator-5.044/test_regress/t/t_assert_unique_case.out0000644000542200017500000000172215125463617024041 0ustar mahmoudyfreeshell[0] %Error: t_assert_unique_case_bad.v:56: Assertion failed in top.t: priority case, but non-match found match_item0 [20] %Error: t_assert_unique_case_bad.v:47: Assertion failed in top.t: unique case, but none matched match_item0 match_item0 [40] %Error: t_assert_unique_case_bad.v:47: Assertion failed in top.t: unique case, but none matched match_item0 match_item0 [60] %Error: t_assert_unique_case_bad.v:47: Assertion failed in top.t: unique case, but none matched match_item0 match_item0 [80] %Error: t_assert_unique_case_bad.v:47: Assertion failed in top.t: unique case, but none matched match_item0 [90] %Error: t_assert_unique_case_bad.v:47: Assertion failed in top.t: unique case, but none matched match_item0 [90] %Error: t_assert_unique_case_bad.v:38: Assertion failed in top.t: unique case, but multiple matches found for '12'h388' *-* All Finished *-* [100] %Error: t_assert_unique_case_bad.v:47: Assertion failed in top.t: unique case, but none matched match_item0 verilator-5.044/test_regress/t/t_var_overwidth_bad.v0000644000542200017500000000077615125463617023316 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_benchmark_sim.py0000755000542200017500000000126515125463617022607 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_gen_alw.v" # Use any top file # As an example, compile and simulate the top file with varying optimization level l_opts = ['-O0', '-O1', '-O2', '-O3'] for l_opt in l_opts: test.compile(v_flags2=[l_opt]) test.execute() test.passes() verilator-5.044/test_regress/t/t_debug_emitv.py0000755000542200017500000000237715125463617022304 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios("vlt") test.lint( # We also have dump-tree turned on, so hit a lot of AstNode*::dump() functions # Likewise XML v_flags=[ "--lint-only", "--dumpi-tree 9 --dumpi-V3EmitV 9 --debug-emitv", # Dev coverage of the V3EmitV code "--dump-graph --dumpi-tree-json 9 --no-json-ids" ]) output_vs = test.glob_some(test.obj_dir + "/" + test.vm_prefix + "_*_width.tree.v") for output_v in output_vs: test.files_identical(output_v, test.golden_filename) if test.verbose: # Print if that the output Verilog is clean # TODO not yet round-trip clean test.run( cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator", "--lint-only", output_vs[0], ], logfile=test.obj_dir + "/sim_roundtrip.log", fails=True, verilator_run=True, ) test.passes() verilator-5.044/test_regress/t/t_mem_first.v0000644000542200017500000000675415125463617021614 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer _mode; initial _mode = 0; // verilator lint_off ASCRANGE reg [7:0] mem_narrow [0:31]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM reg [77:0] mem_wide [1024:0]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM reg [7:0] mem_dly_narrow [0:1]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM reg [77:0] mem_dly_wide [1:0]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM reg [34:0] vec_wide; // verilator lint_on ASCRANGE reg [31:0] wrd0 [15:0]; wire [3:0] sel = 4'h3; wire [31:0] selout = wrd0[sel]; // Must take LSBs into account in bit extract widths. wire [15:14] sixt = 2'b10; // surefire lint_off_line ASWCBB wire [16:14] sixt2 = 3'b110; // surefire lint_off_line ASWCBB wire [3:0] sixfrom = 13; wire [4:0] sixfrom2 = 16; wire sixtext = sixt[sixfrom]; wire sixtext2 = sixt2[sixfrom2]; // Non-power of 2 memory overwriting checks reg [2:0] np2_mem [5:0] /*verilator public*/; reg [2:0] np2_guard [7:6] /*verilator public*/; integer i; always @ (posedge clk) begin if (_mode!=0) begin wrd0[0] = 32'h1; // for (i=0; i<32; i=i+1) begin //surefire lint_off_line STMFOR mem_narrow[i] = i[7:0]; mem_wide[i] = {i[7:0],70'hfeed}; end // for (i=0; i<32; i=i+1) begin //surefire lint_off_line STMFOR if (mem_narrow[i] !== i[7:0]) $stop; if (mem_wide[i] !== {i[7:0],70'hfeed}) $stop; end // vec_wide <= 0; // np2_guard[6] = 0; np2_guard[7] = 0; // $write("selout %b %b %b\n", selout, sixtext, sixtext2); end if (_mode == 1) begin _mode <= 2; // i=0; mem_dly_narrow[0] <= ~i[7:0]; mem_dly_wide[0] <= {~i[7:0],70'hface}; i=1; mem_dly_narrow[i] <= ~i[7:0]; mem_dly_wide[i] <= {~i[7:0],70'hface}; // for (i=0; i<16; i=i+1) begin //surefire lint_off_line STMFOR // verilator lint_off width np2_mem[i] = i[2:0]; // surefire lint_off_line ASWSBB // verilator lint_on width if (np2_guard[6]!=0 || np2_guard[7]!=0) $stop; end // verilator lint_off SELRANGE if (np2_mem[6] !== np2_mem[7]) begin $write("Mem[6]!=Mem[7] during randomize...\n"); //$stop; // Random value, so this can happen end // verilator lint_on SELRANGE //if (np2_mem[8] !== np2_mem[9]) $stop; // Enhancement: Illegal indexes, make sure map to X's // vec_wide[32:31] <= 2'b11; vec_wide[34] <= 1'b1; $display("%x",vec_wide); end if (_mode == 2) begin _mode <= 3; // for (i=0; i<2; i=i+1) begin //surefire lint_off_line STMFOR if (mem_dly_narrow[i] !== ~i[7:0]) $stop; if (mem_dly_wide[i] !== {~i[7:0],70'hface}) $stop; end // //$write ("VW %x %x\n", vec_wide[34:32], vec_wide[31:0]); if (vec_wide != {4'b101_1,31'd0}) $stop; // $write("*-* All Finished *-*\n"); $finish; end _mode <= _mode + 1; end endmodule verilator-5.044/test_regress/t/t_inst_wideconst.v0000644000542200017500000000270715125463617022655 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [41:0] aaa; wire [41:0] bbb; // verilator public_module wire [41:0] z_0; wire [41:0] z_1; wide w_0( .xxx( { {40{1'b0}},2'b11 } ), .yyy( aaa[1:0] ), .zzz( z_0 ) ); wide w_1( .xxx( aaa ), .yyy( 2'b10 ), .zzz( z_1 ) ); assign bbb= z_0 + z_1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin aaa <= 42'b01; end if (cyc==2) begin aaa <= 42'b10; if (z_0 != 42'h4) $stop; if (z_1 != 42'h3) $stop; end if (cyc==3) begin if (z_0 != 42'h5) $stop; if (z_1 != 42'h4) $stop; end if (cyc==4) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module wide ( input [41:0] xxx, input [1:0] yyy, output [41:0] zzz ); // verilator public_module assign zzz = xxx+ { {40{1'b0}},yyy }; endmodule verilator-5.044/test_regress/t/t_dfg_3676.py0000755000542200017500000000070615125463617021231 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.044/test_regress/t/t_timing_fork_no_timing_ctrl.py0000755000542200017500000000077115125463617025405 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_inst_tree_inl0_pub1.vlt0000644000542200017500000000042215125463617024016 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config no_inline -module "l*" public -module "l*" -var "z*" verilator-5.044/test_regress/t/t_fork_label_timing.py0000755000542200017500000000106115125463617023446 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_fork_label.v" test.compile(verilator_flags2=["--binary"], make_main=False) test.execute() test.passes() verilator-5.044/test_regress/t/t_tri_compass_bad.py0000755000542200017500000000076315125463617023140 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_trace_packed_struct.v0000644000542200017500000000160715125463617023630 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Andrew Bardsley. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int cnt; // This won't compile with tracing as an incorrect declaration is made for // the temp variables used to represent the elements of localparam v typedef struct packed { logic [2:0][31:0] a; } t; localparam t v[2:0] = '{ '{'{32'h10000002, 32'h10000001, 32'h10000000}}, '{'{32'h20000002, 32'h20000001, 32'h20000000}}, '{'{32'h30000002, 32'h30000001, 32'h30000000}} }; initial cnt = 0; always@(posedge clk) begin if (cnt < 3) begin cnt = cnt + 1; end else begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.044/test_regress/t/t_flag_parameter_hier.v0000644000542200017500000000307015125463617023573 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: %m: Wrong parameter value\n", `__FILE__,`__LINE__); `stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; u u (); tx x (); parameter PARAM = 0; parameter HIER = 0; initial begin $display("%m PARAM=%0d HIER=%0d", PARAM, HIER); `ifdef IVERILOG `check(PARAM, 0); `elsif NC `check(PARAM, 0); `elsif VCS `check(PARAM, 10); `else `check(PARAM, 10); `endif `check(HIER, 0); end always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule module u; ux x(); endmodule module ux; parameter PARAM = 0; parameter HIER = 0; initial begin $display("%m PARAM=%0d HIER=%0d", PARAM, HIER); `ifdef IVERILOG `check(PARAM, 0); `elsif NC `check(PARAM, 0); `elsif VCS `check(PARAM, 10); `else `check(PARAM, 0); `endif `check(HIER, 0); end endmodule module tx; parameter PARAM = 0; parameter HIER = 0; initial begin $display("%m PARAM=%0d HIER=%0d", PARAM, HIER); `ifdef IVERILOG `check(PARAM, 0); `elsif NC `check(PARAM, 10); `elsif VCS `check(PARAM, 10); `else `check(PARAM, 0); `endif `ifdef NC `check(HIER, 20); `else `check(HIER, 0); `endif end endmodule verilator-5.044/test_regress/t/t_math_pow6.v0000644000542200017500000000266015125463617021523 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs i65, j65, i33, j33, i30, j30, q65, r65, q33, r33, q30, r30, w65, x65, w33, x33, w30, x30, // Inputs a, a40, a70 ); input [3:0] a; input [39:0] a40; input [69:0] a70; // -- Verilator 621c515 creates code that uses the undeclared function VL_POW_WWI() // verilator lint_off WIDTH output [3:0] i65 = 65'd3 ** a; // IWI output [3:0] j65 = a ** 65'd3; // IIW output [3:0] i33 = 33'd3 ** a; // QQI output [3:0] j33 = a ** 33'd3; // IIQ output [3:0] i30 = 30'd3 ** a; // III output [3:0] j30 = a ** 30'd3; // III output [39:0] q65 = 65'd3 ** a40; // WWQ output [39:0] r65 = a40 ** 65'd3; // WWQ output [39:0] q33 = 33'd3 ** a40; // QQQ output [39:0] r33 = a40 ** 33'd3; // QQQ output [39:0] q30 = 30'd3 ** a40; // QQI output [39:0] r30 = a40 ** 30'd3; // QQI output [69:0] w65 = 65'd3 ** a70; // WWW output [69:0] x65 = a70 ** 65'd3; // WWW output [69:0] w33 = 33'd3 ** a70; // WWW output [69:0] x33 = a70 ** 33'd3; // WWW output [69:0] w30 = 30'd3 ** a70; // WWW output [69:0] x30 = a70 ** 30'd3; // WWW // verilator lint_on WIDTH initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_stream_unpack_lhs.v0000644000542200017500000001345415125463617023324 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // Ref. to IEEE Std 1800-2017 11.4.14 & A.8.1 // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Victor Besyakov. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // 1D packed array into concatenation logic [32-1:0] concat_din; logic [8-1:0] concat4_dout3, concat4_dout2, concat4_dout1, concat4_dout0; // same size logic [8-1:0] concat3_dout3, concat3_dout2, concat3_dout1 ; // smaller logic [8-1:0] concat5_dout4, concat5_dout3, concat5_dout2, concat5_dout1, concat5_dout0; // larger // 2D packed array into unpacked array /* verilator lint_off ASCRANGE */ logic [0:4-1][8-1:0] packed_siz_din; logic [0:4-1][8-1:0] packed_asc_din; /* verilator lint_on ASCRANGE */ logic [4-1:0][8-1:0] packed_des_din; logic [8-1:0] unpacked_siz_dout [4]; logic [8-1:0] unpacked_asc_dout [0:4-1]; logic [8-1:0] unpacked_des_dout [4-1:0]; // 2D unpacked array into packed array logic [8-1:0] unpacked_siz_din [4]; logic [8-1:0] unpacked_asc_din [0:4-1]; logic [8-1:0] unpacked_des_din [4-1:0]; /* verilator lint_off ASCRANGE */ logic [0:4-1][8-1:0] packed_siz_dout; logic [0:4-1][8-1:0] packed_asc_dout; /* verilator lint_on ASCRANGE */ logic [4-1:0][8-1:0] packed_des_dout; // 2D packed array into queue logic [8-1:0] packed_siz_queue_dout [$]; logic [8-1:0] packed_asc_queue_dout [$]; logic [8-1:0] packed_des_queue_dout [$]; // 2D unpacked array into queue logic [8-1:0] unpacked_siz_queue_dout [$]; logic [8-1:0] unpacked_asc_queue_dout [$]; logic [8-1:0] unpacked_des_queue_dout [$]; integer cyc = 1; always_comb begin // 1D packed array into concatenation {>>{ concat4_dout3, concat4_dout2, concat4_dout1, concat4_dout0}} = concat_din; /* verilator lint_off WIDTHTRUNC */ {>>{ concat3_dout3, concat3_dout2, concat3_dout1 }} = concat_din; /* verilator lint_on WIDTHTRUNC */ /* verilator lint_off WIDTHEXPAND */ {>>{concat5_dout4, concat5_dout3, concat5_dout2, concat5_dout1, concat5_dout0}} = concat_din; /* verilator lint_on WIDTHEXPAND */ // 2D packed array into unpacked array {>>{unpacked_siz_dout}} = packed_asc_din; {>>{unpacked_asc_dout}} = packed_asc_din; {>>{unpacked_des_dout}} = packed_des_din; // 2D unpacked array into packed array {>>{packed_siz_dout}} = unpacked_siz_din; {>>{packed_asc_dout}} = unpacked_asc_din; {>>{packed_des_dout}} = unpacked_des_din; // 2D packed array into queue {>>{packed_siz_queue_dout}} = packed_siz_din; {>>{packed_asc_queue_dout}} = packed_asc_din; {>>{packed_des_queue_dout}} = packed_des_din; // 2D unpacked array into queue {>>{unpacked_siz_queue_dout}} = unpacked_siz_din; {>>{unpacked_asc_queue_dout}} = unpacked_asc_din; {>>{unpacked_des_queue_dout}} = unpacked_des_din; end always @(posedge clk) begin if (cyc != 0) begin cyc <= cyc + 1; if (cyc == 1) begin // 1D packed array into concatenation concat_din <= 32'h76543210; // 2D packed array into unpacked array packed_siz_din <= '{8'h01, 8'h23, 8'h45, 8'h67}; packed_asc_din <= '{8'h01, 8'h23, 8'h45, 8'h67}; packed_des_din <= '{8'h76, 8'h54, 8'h32, 8'h10}; // 2D unpacked array into packed array unpacked_siz_din <= '{8'h01, 8'h23, 8'h45, 8'h67}; unpacked_asc_din <= '{8'h01, 8'h23, 8'h45, 8'h67}; unpacked_des_din <= '{8'h76, 8'h54, 8'h32, 8'h10}; end if (cyc == 2) begin // 1D packed array into concatenation (same size) if (concat4_dout0 != 8'h10) $stop; if (concat4_dout1 != 8'h32) $stop; if (concat4_dout2 != 8'h54) $stop; if (concat4_dout3 != 8'h76) $stop; // 1D packed array into concatenation (smaller) if (concat3_dout1 != 8'h32) $stop; if (concat3_dout2 != 8'h54) $stop; if (concat3_dout3 != 8'h76) $stop; // 1D packed array into concatenation (larger) if (concat5_dout0 != 8'h00) $stop; if (concat5_dout1 != 8'h10) $stop; if (concat5_dout2 != 8'h32) $stop; if (concat5_dout3 != 8'h54) $stop; if (concat5_dout4 != 8'h76) $stop; // 2D packed array into unpacked array if (unpacked_siz_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; if (unpacked_asc_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; if (unpacked_des_dout != '{8'h76, 8'h54, 8'h32, 8'h10}) $stop; // 2D unpacked array into packed array if (packed_siz_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; if (packed_asc_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; if (packed_des_dout != '{8'h76, 8'h54, 8'h32, 8'h10}) $stop; // 2D packed array into queue if (packed_siz_queue_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; if (packed_asc_queue_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; if (packed_des_queue_dout != '{8'h76, 8'h54, 8'h32, 8'h10}) $stop; // 2D unpacked array into queue if (unpacked_siz_queue_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; if (unpacked_asc_queue_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; if (unpacked_des_queue_dout != '{8'h76, 8'h54, 8'h32, 8'h10}) $stop; end if (cyc == 3) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.044/test_regress/t/t_preproc_eof2_bad.py0000755000542200017500000000076615125463617023205 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_dpi_open_c.cpp0000644000542200017500000002721315125463617022234 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include #include #include // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" //====================================================================== // clang-format off #if defined(VERILATOR) # include "Vt_dpi_open__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(NC) # define NEED_EXTERNS // #elif defined(MS) // # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif // clang-format on #ifdef NEED_EXTERNS extern "C" { // If get ncsim: *F,NOFDPI: Function {foo} not found in default libdpi. // Then probably forgot to list a function here. extern void dpii_unused(const svOpenArrayHandle u); extern void dpii_open_p0_u1(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_p1_u0(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_p1_u1(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_p1_u2(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_p1_u3(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_pw_u0(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_pw_u1(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_pw_u2(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_pw_u3(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_bit(const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_byte(const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_int(const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_integer(const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_logic(const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_int_u1(int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_int_u2(int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_int_u3(int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern int dpii_failure(); } #endif int errors = 0; int dpii_failure() { return errors; } void dpii_unused(const svOpenArrayHandle u) {} void _dpii_all(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { #ifdef TEST_VERBOSE fprintf(stderr, "-:%s:%d: For case c=%d p=%d u=%d data=%p\n", // __FILE__, __LINE__, c, p, u, svGetArrayPtr(i)); #endif (void)svGetArrayPtr(i); #ifndef NC // NC always returns zero and warns (void)svSizeOfArray(i); #endif #ifndef VCS // VCS does not support dimension 0 query if (p) { int d = 0; if (c == 0 || c == 1) { TEST_CHECK_HEX_EQ(svLeft(i, d), 1); TEST_CHECK_HEX_EQ(svRight(i, d), -1); TEST_CHECK_HEX_EQ(svLow(i, d), -1); TEST_CHECK_HEX_EQ(svHigh(i, d), 1); // TEST_CHECK_HEX_EQ(svIncrement(i, d), 0); TEST_CHECK_HEX_EQ(svSize(i, d), 3); } else if (c == 2) { TEST_CHECK_HEX_EQ(svLeft(i, d), 95); TEST_CHECK_HEX_EQ(svRight(i, d), 1); TEST_CHECK_HEX_EQ(svLow(i, d), 1); TEST_CHECK_HEX_EQ(svHigh(i, d), 95); // TEST_CHECK_HEX_EQ(svIncrement(i, d), 0); TEST_CHECK_HEX_EQ(svSize(i, d), 95); } else { TEST_CHECK_HEX_EQ(0, 1); } } #endif if (u >= 1) { int d = 1; if (c == 0) { TEST_CHECK_HEX_EQ(svLeft(i, d), -2); TEST_CHECK_HEX_EQ(svRight(i, d), 2); TEST_CHECK_HEX_EQ(svLow(i, d), -2); TEST_CHECK_HEX_EQ(svHigh(i, d), 2); // TEST_CHECK_HEX_EQ(svIncrement(i, d), 0); TEST_CHECK_HEX_EQ(svSize(i, d), 5); } else if (c == 1) { TEST_CHECK_HEX_EQ(svLeft(i, d), 2); TEST_CHECK_HEX_EQ(svRight(i, d), -2); TEST_CHECK_HEX_EQ(svLow(i, d), -2); TEST_CHECK_HEX_EQ(svHigh(i, d), 2); // TEST_CHECK_HEX_EQ(svIncrement(i, d), 0); TEST_CHECK_HEX_EQ(svSize(i, d), 5); } } if (u >= 2) { int d = 2; if (c == 0) { TEST_CHECK_HEX_EQ(svLeft(i, d), -3); TEST_CHECK_HEX_EQ(svRight(i, d), 3); TEST_CHECK_HEX_EQ(svLow(i, d), -3); TEST_CHECK_HEX_EQ(svHigh(i, d), 3); // TEST_CHECK_HEX_EQ(svIncrement(i, d), 0); TEST_CHECK_HEX_EQ(svSize(i, d), 7); } else if (c == 1) { TEST_CHECK_HEX_EQ(svLeft(i, d), 3); TEST_CHECK_HEX_EQ(svRight(i, d), -3); TEST_CHECK_HEX_EQ(svLow(i, d), -3); TEST_CHECK_HEX_EQ(svHigh(i, d), 3); // TEST_CHECK_HEX_EQ(svIncrement(i, d), 0); TEST_CHECK_HEX_EQ(svSize(i, d), 7); } } #ifdef VERILATOR // Check out-of-bounds read doesn't access bad memory (when sanitizer used) (void)svLeft(i, -1); (void)svRight(i, -1); (void)svLow(i, -1); (void)svHigh(i, -1); (void)svIncrement(i, -1); (void)svSize(i, -1); // (void)svLeft(i, 99); (void)svRight(i, 99); (void)svLow(i, 99); (void)svHigh(i, 99); (void)svIncrement(i, 99); (void)svSize(i, 99); #endif if (c == 2 && p == 1 && u == 3) { for (int a = svLow(i, 1); a <= svHigh(i, 1); ++a) { for (int b = svLow(i, 2); b <= svHigh(i, 2); ++b) { for (int c = svLow(i, 3); c <= svHigh(i, 3); ++c) { // printf("Copy abc %d,%d,%d\n", a,b,c); svLogicVecVal vec[3]; svGetLogicArrElemVecVal(vec, i, a, b, c); #ifdef NC // printf(" %08lx_%08lx_%08lx\n", vec[2].a, vec[1].a, vec[0].a); vec[0].a = (~vec[0].a); vec[1].a = (~vec[1].a); vec[2].a = (~vec[2].a) & 0x7fffffff; // vec[0].b = vec[0].b; // vec[1].b = vec[1].b; // vec[2].b = vec[2].b; #else vec[0].aval = (~vec[0].aval); vec[1].aval = (~vec[1].aval); vec[2].aval = (~vec[2].aval) & 0x7fffffff; // vec[0].bval = vec[0].bval; // vec[1].bval = vec[1].bval; // vec[2].bval = vec[2].bval; #endif svPutLogicArrElemVecVal(o, vec, a, b, c); } } } } } void dpii_open_p0_u1(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_all(c, p, u, i, o); } void dpii_open_p1_u0(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_all(c, p, u, i, o); } void dpii_open_p1_u1(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_all(c, p, u, i, o); } void dpii_open_p1_u2(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_all(c, p, u, i, o); } void dpii_open_p1_u3(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_all(c, p, u, i, o); } void dpii_open_pw_u0(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_all(c, p, u, i, o); } void dpii_open_pw_u1(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_all(c, p, u, i, o); } void dpii_open_pw_u2(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_all(c, p, u, i, o); } void dpii_open_pw_u3(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_all(c, p, u, i, o); } void dpii_open_bit(const svOpenArrayHandle i, const svOpenArrayHandle o) {} void dpii_open_byte(const svOpenArrayHandle i, const svOpenArrayHandle o) { intptr_t arrPtr = (intptr_t)svGetArrayPtr(i); TEST_CHECK_HEX_NE(arrPtr, 0); // All the arrays should actually exist #ifndef NC // NC always returns zero and warns int sizeInputOfArray = svSizeOfArray(i); TEST_CHECK_HEX_NE(sizeInputOfArray, 0); // None of the test cases have zero size TEST_CHECK_HEX_NE(svDimensions(i), 0); // All the test cases are unpacked arrays #endif } void dpii_open_integer(const svOpenArrayHandle i, const svOpenArrayHandle o) {} void dpii_open_logic(const svOpenArrayHandle i, const svOpenArrayHandle o) {} static void _dpii_open_int_ux(int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { intptr_t arrPtr = (intptr_t)svGetArrayPtr(i); TEST_CHECK_HEX_NE(arrPtr, 0); // All the arrays should actually exist #ifndef NC // NC always returns zero and warns int sizeInputOfArray = svSizeOfArray(i); TEST_CHECK_HEX_NE(sizeInputOfArray, 0); // None of the test cases have zero size TEST_CHECK_HEX_EQ(svDimensions(i), u); #endif int dim = svDimensions(i); for (int a = svLow(i, 1); a <= svHigh(i, 1); ++a) { if (dim == 1) { intptr_t ip = (intptr_t)svGetArrElemPtr(i, a); intptr_t i2p = (intptr_t)svGetArrElemPtr1(i, a); TEST_CHECK_HEX_EQ(ip, i2p); TEST_CHECK_HEX_NE(ip, 0); intptr_t op = (intptr_t)svGetArrElemPtr(o, a); TEST_CHECK_HEX_NE(op, 0); *reinterpret_cast(op) = ~*reinterpret_cast(ip); } else { for (int b = svLow(i, 2); b <= svHigh(i, 2); ++b) { if (dim == 2) { intptr_t ip = (intptr_t)svGetArrElemPtr(i, a, b); intptr_t i2p = (intptr_t)svGetArrElemPtr2(i, a, b); TEST_CHECK_HEX_EQ(ip, i2p); TEST_CHECK_HEX_NE(ip, 0); intptr_t op = (intptr_t)svGetArrElemPtr(o, a, b); TEST_CHECK_HEX_NE(op, 0); *reinterpret_cast(op) = ~*reinterpret_cast(ip); } else { for (int c = svLow(i, 3); c <= svHigh(i, 3); ++c) { if (dim == 3) { intptr_t ip = (intptr_t)svGetArrElemPtr(i, a, b, c); intptr_t i2p = (intptr_t)svGetArrElemPtr3(i, a, b, c); TEST_CHECK_HEX_EQ(ip, i2p); TEST_CHECK_HEX_NE(ip, 0); intptr_t op = (intptr_t)svGetArrElemPtr(o, a, b, c); TEST_CHECK_HEX_NE(op, 0); *reinterpret_cast(op) = ~*reinterpret_cast(ip); } } } } } } } void dpii_open_int_u1(int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_open_int_ux(u, i, o); } void dpii_open_int_u2(int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_open_int_ux(u, i, o); } void dpii_open_int_u3(int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_open_int_ux(u, i, o); } verilator-5.044/test_regress/t/t_compiler_include_dpi.cpp0000644000542200017500000000126715125463617024307 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2024 by Antmicro. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // t_compiler_include.h is implicitly included by `--compiler-include` int dpii_add_check(int actual, int expected) { return actual == expected; } void dpii_add(int a, int b, int* out) { *out = a + b; } verilator-5.044/test_regress/t/t_trace_enum_saif.py0000755000542200017500000000120115125463617023117 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_enum.v" test.compile(verilator_flags2=['--cc --trace-saif --output-split-ctrace 1']) test.execute() test.saif_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_randomize_method_param.v0000644000542200017500000000136115125463617024324 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package uvm_pkg; virtual class uvm_sequence #( type REQ = int ); endclass class uvm_sequence_library #( type REQ = int ) extends uvm_sequence #(REQ); rand bit [15:0] m_rand; randc bit [15:0] m_randc; task body(); if (0 == randomize(m_rand)) begin end if (0 == randomize(m_randc)) begin end endtask endclass endpackage module t; import uvm_pkg::*; class t1 extends uvm_sequence_library; endclass initial begin t1 c; c = new; $finish; end endmodule verilator-5.044/test_regress/t/t_event_method_bad.py0000755000542200017500000000076615125463617023301 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_cover_line.out0000644000542200017500000004664715125463617022323 0ustar mahmoudyfreeshell// // verilator_coverage annotation // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg toggle; %000001 initial toggle=0; -000001 point: comment=block hier=top.t integer cyc; %000001 initial cyc=1; -000001 point: comment=block hier=top.t wire [7:0] cyc_copy = cyc[7:0]; alpha a1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); alpha a2 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); beta b1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); beta b2 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); tsk t1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); off o1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); tab tab1 (/*AUTOINST*/ // Inputs .clk (clk)); par par1 (/*AUTOINST*/); cond cond1 (/*AUTOINST*/ // Inputs .clk (clk), .cyc (cyc)); 000010 always @ (posedge clk) begin +000010 point: comment=block hier=top.t ~000010 if (cyc!=0) begin +000010 point: comment=if hier=top.t -000000 point: comment=else hier=top.t 000010 cyc <= cyc + 1; +000010 point: comment=if hier=top.t 000010 toggle <= '0; +000010 point: comment=if hier=top.t // Single and multiline if %000009 if (cyc==3) $write(""); -000001 point: comment=if hier=top.t -000009 point: comment=else hier=top.t %000009 if (cyc==3) -000001 point: comment=if hier=top.t -000009 point: comment=else hier=top.t %000001 begin -000001 point: comment=if hier=top.t %000001 $write(""); -000001 point: comment=if hier=top.t end // Single and multiline else %000009 if (cyc==3) ; else $write(""); -000001 point: comment=if hier=top.t -000009 point: comment=else hier=top.t %000009 if (cyc==3) ; -000001 point: comment=if hier=top.t -000009 point: comment=else hier=top.t else %000009 begin -000009 point: comment=else hier=top.t %000009 $write(""); -000009 point: comment=else hier=top.t end // Single and multiline if else %000009 if (cyc==3) $write(""); else $write(""); -000001 point: comment=if hier=top.t -000009 point: comment=else hier=top.t %000009 if (cyc==3) -000001 point: comment=if hier=top.t -000009 point: comment=else hier=top.t %000001 begin -000001 point: comment=if hier=top.t %000001 $write(""); -000001 point: comment=if hier=top.t end else %000009 begin -000009 point: comment=else hier=top.t %000009 $write(""); -000009 point: comment=else hier=top.t end // multiline elseif %000001 if (cyc==3) -000001 point: comment=elsif hier=top.t %000001 begin -000001 point: comment=elsif hier=top.t %000001 $write(""); -000001 point: comment=elsif hier=top.t end %000001 else if (cyc==4) -000001 point: comment=elsif hier=top.t %000001 begin -000001 point: comment=elsif hier=top.t %000001 $write(""); -000001 point: comment=elsif hier=top.t end %000007 else if (cyc==5) -000001 point: comment=if hier=top.t -000007 point: comment=else hier=top.t %000001 begin -000001 point: comment=if hier=top.t %000001 $write(""); -000001 point: comment=if hier=top.t end else %000007 begin -000007 point: comment=else hier=top.t %000007 $write(""); -000007 point: comment=else hier=top.t end // Single and multiline while %000000 while (0); -000000 point: comment=block hier=top.t %000000 while (0) begin -000000 point: comment=block hier=top.t %000000 $write(""); -000000 point: comment=block hier=top.t end %000000 do ; while (0); -000000 point: comment=block hier=top.t ~000010 do begin -000000 point: comment=block hier=top.t +000010 point: comment=block hier=top.t 000010 $write(""); +000010 point: comment=block hier=top.t ~000010 end while (0); -000000 point: comment=block hier=top.t +000010 point: comment=block hier=top.t //=== // Task and complicated %000001 if (cyc==3) begin -000001 point: comment=elsif hier=top.t %000001 toggle <= '1; -000001 point: comment=elsif hier=top.t end %000001 else if (cyc==5) begin -000001 point: comment=elsif hier=top.t `ifdef VERILATOR %000001 $c("this->call_task();"); -000001 point: comment=elsif hier=top.t `else call_task(); `endif end %000007 else if (cyc==10) begin -000001 point: comment=if hier=top.t -000007 point: comment=else hier=top.t %000001 $write("*-* All Finished *-*\n"); -000001 point: comment=if hier=top.t %000001 $finish; -000001 point: comment=if hier=top.t end end end %000001 task call_task; -000001 point: comment=block hier=top.t /* verilator public */ %000001 t1.center_task(1'b1); -000001 point: comment=block hier=top.t endtask endmodule module alpha (/*AUTOARG*/ // Inputs clk, toggle ); input clk; input toggle; 000020 always @ (posedge clk) begin +000020 point: comment=block hier=top.t.a* ~000018 if (toggle) begin // CHECK_COVER(0,"top.t.a*",18) -000002 point: comment=if hier=top.t.a* +000018 point: comment=else hier=top.t.a* %000002 $write(""); -000002 point: comment=if hier=top.t.a* // t.a1 and t.a2 collapse to a count of 2 end 000018 if (toggle) begin // *** t_cover_line.vlt turns this off +000018 point: comment=else hier=top.t.a* $write(""); // CHECK_COVER_MISSING(0) // This doesn't even get added `ifdef ATTRIBUTE // verilator coverage_block_off `endif end end endmodule module beta (/*AUTOARG*/ // Inputs clk, toggle ); input clk; input toggle; /* verilator public_module */ 000020 always @ (posedge clk) begin +000020 point: comment=block hier=top.t.b* 000020 $write(""); // Always covered +000020 point: comment=block hier=top.t.b* ~000020 if (0) begin // CHECK_COVER(0,"top.t.b*",0) -000000 point: comment=if hier=top.t.b* +000020 point: comment=else hier=top.t.b* // Make sure that we don't optimize away zero buckets %000000 $write(""); -000000 point: comment=if hier=top.t.b* end ~000018 if (toggle) begin // CHECK_COVER(0,"top.t.b*",2) -000002 point: comment=if hier=top.t.b* +000018 point: comment=else hier=top.t.b* // t.b1 and t.b2 collapse to a count of 2 %000002 $write(""); -000002 point: comment=if hier=top.t.b* end 000018 if (toggle) begin : block +000018 point: comment=else hier=top.t.b* // This doesn't `ifdef ATTRIBUTE // verilator coverage_block_off `endif begin end // *** t_cover_line.vlt turns this off (so need begin/end) if (1) begin end // CHECK_COVER_MISSING(0) $write(""); // CHECK_COVER_MISSING(0) end end endmodule class Cls; bit m_toggle; 000011 function new(bit toggle); +000011 point: comment=block hier=top.$unit::Cls__Vclpkg 000011 m_toggle = toggle; +000011 point: comment=block hier=top.$unit::Cls__Vclpkg ~000011 if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",1) +000011 point: comment=if hier=top.$unit::Cls__Vclpkg -000000 point: comment=else hier=top.$unit::Cls__Vclpkg 000011 $write(""); +000011 point: comment=if hier=top.$unit::Cls__Vclpkg end endfunction 000011 static function void fstatic(bit toggle); +000011 point: comment=block hier=top.$unit::Cls__Vclpkg ~000011 if (1) begin // CHECK_COVER(0,"top.$unit::Cls",1) +000011 point: comment=if hier=top.$unit::Cls__Vclpkg -000000 point: comment=else hier=top.$unit::Cls__Vclpkg 000011 $write(""); +000011 point: comment=if hier=top.$unit::Cls__Vclpkg end endfunction 000011 function void fauto(); +000011 point: comment=block hier=top.$unit::Cls__Vclpkg ~000011 if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",11) +000011 point: comment=if hier=top.$unit::Cls__Vclpkg -000000 point: comment=else hier=top.$unit::Cls__Vclpkg 000011 $write(""); +000011 point: comment=if hier=top.$unit::Cls__Vclpkg end endfunction endclass module tsk (/*AUTOARG*/ // Inputs clk, toggle ); input clk; input toggle; /* verilator public_module */ 000010 always @ (posedge clk) begin +000010 point: comment=block hier=top.t.t1 000010 center_task(1'b0); +000010 point: comment=block hier=top.t.t1 end 000011 task automatic center_task; +000011 point: comment=block hier=top.t.t1 input external; 000011 begin +000011 point: comment=block hier=top.t.t1 ~000010 if (toggle) begin // CHECK_COVER(0,"top.t.t1",1) -000001 point: comment=if hier=top.t.t1 +000010 point: comment=else hier=top.t.t1 %000001 $write(""); -000001 point: comment=if hier=top.t.t1 end ~000010 if (external) begin // CHECK_COVER(0,"top.t.t1",1) -000001 point: comment=if hier=top.t.t1 +000010 point: comment=else hier=top.t.t1 %000001 $write("[%0t] Got external pulse\n", $time); -000001 point: comment=if hier=top.t.t1 end end 000011 begin +000011 point: comment=block hier=top.t.t1 Cls c; 000011 c = new(1'b1); +000011 point: comment=block hier=top.t.t1 000011 c.fauto(); +000011 point: comment=block hier=top.t.t1 000011 Cls::fstatic(1'b1); +000011 point: comment=block hier=top.t.t1 end endtask endmodule module off (/*AUTOARG*/ // Inputs clk, toggle ); input clk; input toggle; // verilator coverage_off always @ (posedge clk) begin if (toggle) begin $write(""); // CHECK_COVER_MISSING(0) // because under coverage_module_off end end // verilator coverage_on 000010 always @ (posedge clk) begin +000010 point: comment=block hier=top.t.o1 %000009 if (toggle) begin -000001 point: comment=if hier=top.t.o1 -000009 point: comment=else hier=top.t.o1 // because under coverage_module_off %000001 $write(""); -000001 point: comment=if hier=top.t.o1 %000001 if (0) ; // CHECK_COVER(0,"top.t.o1",1) -000000 point: comment=if hier=top.t.o1 -000001 point: comment=else hier=top.t.o1 end end endmodule module tab (input clk); bit [3:0] cyc4; int decoded; 000010 always @ (posedge clk) begin +000010 point: comment=block hier=top.t.tab1 000010 case (cyc4) +000010 point: comment=block hier=top.t.tab1 %000001 1: decoded = 10; -000001 point: comment=case hier=top.t.tab1 %000001 2: decoded = 20; -000001 point: comment=case hier=top.t.tab1 %000001 3: decoded = 30; -000001 point: comment=case hier=top.t.tab1 %000001 4: decoded = 40; -000001 point: comment=case hier=top.t.tab1 %000001 5: decoded = 50; -000001 point: comment=case hier=top.t.tab1 %000005 default: decoded = 0; -000005 point: comment=case hier=top.t.tab1 endcase end 000010 always @ (posedge clk) begin +000010 point: comment=block hier=top.t.tab1 000010 cyc4 <= cyc4 + 1; +000010 point: comment=block hier=top.t.tab1 end endmodule module par(); localparam int CALLS_FUNC = param_func(1); // We don't currently count elaboration time use towards coverage. This // seems safer for functions used both at elaboration time and not - but may // revisit this. %000000 function automatic int param_func(int i); -000000 point: comment=block hier=top.t.par1 %000000 if (i == 0) begin -000000 point: comment=if hier=top.t.par1 -000000 point: comment=else hier=top.t.par1 %000000 i = 99; // Uncovered -000000 point: comment=if hier=top.t.par1 end %000000 else begin -000000 point: comment=else hier=top.t.par1 %000000 i = i + 1; -000000 point: comment=else hier=top.t.par1 end %000000 return i; -000000 point: comment=block hier=top.t.par1 endfunction endmodule package my_pkg; %000001 int x = 1 ? 1 : 0; -000001 point: comment=block hier=top.my_pkg endpackage %000001 class Getter1; -000001 point: comment=block hier=top.$unit::Getter1__Vclpkg 000020 function int get_1; +000020 point: comment=block hier=top.$unit::Getter1__Vclpkg 000020 return 1; +000020 point: comment=block hier=top.$unit::Getter1__Vclpkg endfunction endclass module cond(input logic clk, input int cyc); logic a, b, c, d, e, f, g, h, k, l, m; logic [5:0] tab; typedef logic [7:0] arr_t[1:0]; arr_t data[1:0]; %000001 Getter1 getter1 = new; -000001 point: comment=block hier=top.t.cond1 string s; struct packed { logic unsigned [15:0] a; logic unsigned [15:0] b; } pstruct; 000021 function logic func_side_effect; +000021 point: comment=block hier=top.t.cond1 000021 $display("SIDE EFFECT"); +000021 point: comment=block hier=top.t.cond1 000021 return 1; +000021 point: comment=block hier=top.t.cond1 endfunction 000010 function arr_t get_arr; +000010 point: comment=block hier=top.t.cond1 arr_t arr; 000010 return arr; +000010 point: comment=block hier=top.t.cond1 endfunction ~000031 assign a = (cyc == 0) ? clk : 1'bz; -000000 point: comment=cond_then hier=top.t.cond1 +000031 point: comment=cond_else hier=top.t.cond1 ~000028 assign b = (cyc == 1) ? clk : 0; -000003 point: comment=cond_then hier=top.t.cond1 +000028 point: comment=cond_else hier=top.t.cond1 ~000021 assign c = func_side_effect() ? clk : 0; +000021 point: comment=cond_then hier=top.t.cond1 -000000 point: comment=cond_else hier=top.t.cond1 000010 always @(posedge clk) begin +000010 point: comment=block hier=top.t.cond1 ~000010 d = (cyc % 3 == 0) ? 1 : 0; +000010 point: comment=block hier=top.t.cond1 -000003 point: comment=cond_then hier=top.t.cond1 -000007 point: comment=cond_else hier=top.t.cond1 ~000010 s = (getter1.get_1() == 0) ? "abcd" : $sformatf("%d", getter1.get_1()[4:0]); +000010 point: comment=block hier=top.t.cond1 -000000 point: comment=cond_then hier=top.t.cond1 +000010 point: comment=cond_else hier=top.t.cond1 end ~000019 assign e = (cyc % 3 == 1) ? (clk ? 1 : 0) : 1; +000012 point: comment=cond_then hier=top.t.cond1 +000019 point: comment=cond_else hier=top.t.cond1 -000007 point: comment=cond_then hier=top.t.cond1 -000005 point: comment=cond_else hier=top.t.cond1 // ternary operator in condition shouldn't be included to the coverae ~000011 assign f = (cyc != 0 ? 1 : 0) ? 1 : 0; +000011 point: comment=cond_then hier=top.t.cond1 -000000 point: comment=cond_else hier=top.t.cond1 // the same as in index assign tab[clk ? 1 : 0] = 1; assign m = tab[clk ? 3 : 4]; for (genvar i = 0; i < 2; i++) begin 000011 assign g = clk ? 1 : 0; +000010 point: comment=cond_then hier=top.t.cond1 +000011 point: comment=cond_else hier=top.t.cond1 end 000011 always begin +000011 point: comment=block hier=top.t.cond1 ~000010 if (cyc == 5) h = cyc > 5 ? 1 : 0; -000000 point: comment=cond_then hier=top.t.cond1 -000001 point: comment=cond_else hier=top.t.cond1 -000001 point: comment=if hier=top.t.cond1 +000010 point: comment=else hier=top.t.cond1 000010 else h = 1; +000010 point: comment=else hier=top.t.cond1 ~000011 data[0] = (cyc == 2) ? '{8'h01, 8'h02} : get_arr(); +000011 point: comment=block hier=top.t.cond1 -000001 point: comment=cond_then hier=top.t.cond1 +000010 point: comment=cond_else hier=top.t.cond1 // ternary operator in conditions should be skipped 000055 for (int i = 0; (i < 5) ? 1 : 0; i++) begin +000011 point: comment=block hier=top.t.cond1 +000055 point: comment=block hier=top.t.cond1 000055 k = 1'(i); +000055 point: comment=block hier=top.t.cond1 end 000044 for (int i = 0; i < 7; i = (i > 4) ? i + 1 : i + 2) begin +000011 point: comment=block hier=top.t.cond1 +000011 point: comment=cond_then hier=top.t.cond1 +000033 point: comment=cond_else hier=top.t.cond1 +000044 point: comment=block hier=top.t.cond1 000044 k = 1'(i); +000044 point: comment=block hier=top.t.cond1 end ~000011 if (k ? 1 : 0) k = 1; -000000 point: comment=if hier=top.t.cond1 +000011 point: comment=else hier=top.t.cond1 000011 else k = 0; +000011 point: comment=else hier=top.t.cond1 end ~000010 assign pstruct.a = cyc == 1 ? 16'd2 : 16'd3; -000001 point: comment=cond_then hier=top.t.cond1 +000010 point: comment=cond_else hier=top.t.cond1 assign pstruct.b = 16'd0; 000010 always @(posedge clk) begin +000010 point: comment=block hier=top.t.cond1 %000009 if (cyc == 2) $display("%08x", pstruct); -000001 point: comment=if hier=top.t.cond1 -000009 point: comment=else hier=top.t.cond1 end endmodule verilator-5.044/test_regress/t/t_trace_decoration.py0000755000542200017500000000113515125463617023306 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--cc --trace-vcd --no-decoration']) test.execute() test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + ".h", r'// Body') test.passes() verilator-5.044/test_regress/t/t_net_delay.out0000644000542200017500000000433115125463617022122 0ustar mahmoudyfreeshell%Warning-STMTDLY: t/t_net_delay.v:16:11: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' 16 | always #2 clk = ~clk; | ^ ... For warning description see https://verilator.org/warn/STMTDLY?v=latest ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message. %Warning-STMTDLY: t/t_net_delay.v:22:14: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' 22 | wire[3:0] #3 val1; | ^ %Warning-STMTDLY: t/t_net_delay.v:23:14: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' 23 | wire[3:0] #3 val2; | ^ %Warning-ASSIGNDLY: t/t_net_delay.v:24:14: Ignoring timing control on this assignment/primitive due to --no-timing : ... note: In instance 't' 24 | wire[3:0] #5 val3 = cyc; | ^ ... For warning description see https://verilator.org/warn/ASSIGNDLY?v=latest ... Use "/* verilator lint_off ASSIGNDLY */" and lint_on around source to disable this message. %Warning-STMTDLY: t/t_net_delay.v:25:14: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' 25 | wire[3:0] #5 val4; | ^ %Warning-ASSIGNDLY: t/t_net_delay.v:26:14: Ignoring timing control on this assignment/primitive due to --no-timing : ... note: In instance 't' 26 | wire[3:0] #3 val5 = x, val6 = cyc; | ^ %Warning-ASSIGNDLY: t/t_net_delay.v:29:11: Ignoring timing control on this assignment/primitive due to --no-timing : ... note: In instance 't' 29 | assign #3 val2 = cyc; | ^ %Warning-STMTDLY: t/t_net_delay.v:41:26: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' 41 | always @(posedge clk) #1 begin | ^ %Error: Exiting due to verilator-5.044/test_regress/t/t_randomize_nested_unsup.out0000644000542200017500000000057015125463617024743 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_randomize_nested_unsup.v:17:41: Unsupported: randomize() nested in inline randomize() constraints 17 | if (a.randomize() with {rdata == aa.randomize();} == 0) $stop; | ^~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.044/test_regress/t/t_case_genx_bad.v0000644000542200017500000000071415125463617022357 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; parameter P = 32'b1000; generate case (P) 32'b0: initial begin end 32'b1xxx: initial begin end default initial begin end // No ':' to cover parser endcase endgenerate endmodule verilator-5.044/test_regress/t/t_bitsel_slice.py0000755000542200017500000000073415125463617022446 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_interface_gen12.v0000644000542200017500000000113715125463617022551 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 // bug1005 module foo_module; generate for (genvar i = 0; i < 2; i = i + 1) begin : my_gen_block logic baz; end endgenerate endmodule module bar_module; foo_module foo(); endmodule module t; bar_module bar(); initial begin bar.foo.my_gen_block[0].baz = 1; if (bar.foo.my_gen_block[0].baz) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.044/test_regress/t/t_clk_latch_edgestyle.py0000755000542200017500000000105015125463617023766 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_clk_latch.v" test.compile(v_flags2=['+define+EDGE_DETECT_STYLE']) test.execute() test.passes() verilator-5.044/test_regress/t/t_trace_saif.out0000644000542200017500000012246715125463617022271 0ustar mahmoudyfreeshell// Generated by verilated_saif (SAIFILE (SAIFVERSION "2.0") (DIRECTION "backward") (PROGRAM_NAME "Verilator") (DIVIDER / ) (TIMESCALE 1ps) (DURATION 1000) (INSTANCE top (NET (clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199)) (state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46)) (state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) (state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) (state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) (fst_inout (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE t (NET (clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199)) (cyc\[0\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 100)) (cyc\[1\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 50)) (cyc\[2\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 25)) (cyc\[3\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 12)) (cyc\[4\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 6)) (cyc\[5\] (T0 640) (T1 360) (TZ 0) (TX 0) (TB 0) (TC 3)) (cyc\[6\] (T0 640) (T1 360) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (rstn (T0 110) (T1 890) (TZ 0) (TX 0) (TB 0) (TC 1)) (state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46)) (state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) (state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) (state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) (fst_gparam_real\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[32\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[33\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[34\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[35\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[36\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[37\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[38\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[39\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[40\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[41\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[42\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[43\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[44\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[45\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[46\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[47\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[48\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[49\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[50\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[51\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[52\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[53\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[54\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[55\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[56\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[57\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[58\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[59\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[60\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[61\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[62\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[63\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[32\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[33\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[34\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[35\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[36\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[37\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[38\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[39\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[40\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[41\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[42\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[43\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[44\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[45\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[46\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[47\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[48\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[49\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[50\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[51\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[52\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[53\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[54\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[55\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[56\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[57\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[58\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[59\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[60\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[61\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[62\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[63\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[32\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[33\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[34\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[35\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[36\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[37\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[38\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[39\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[40\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[41\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[42\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[43\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[44\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[45\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[46\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[47\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[48\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[49\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[50\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[51\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[52\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[53\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[54\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[55\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[56\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[57\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[58\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[59\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[60\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[61\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[62\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[63\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_bit (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_logic (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[32\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[33\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[34\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[35\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[36\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[37\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[38\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[39\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[40\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[41\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[42\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[43\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[44\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[45\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[46\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[47\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[48\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[49\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[50\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[51\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[52\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[53\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[54\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[55\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[56\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[57\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[58\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[59\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[60\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[61\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[62\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[63\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[1\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 100)) (fst_time\[2\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 50)) (fst_time\[3\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 75)) (fst_time\[4\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 62)) (fst_time\[5\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 31)) (fst_time\[6\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 15)) (fst_time\[7\] (T0 510) (T1 490) (TZ 0) (TX 0) (TB 0) (TC 7)) (fst_time\[8\] (T0 510) (T1 490) (TZ 0) (TX 0) (TB 0) (TC 3)) (fst_time\[9\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_time\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[32\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[33\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[34\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[35\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[36\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[37\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[38\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[39\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[40\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[41\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[42\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[43\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[44\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[45\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[46\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[47\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[48\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[49\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[50\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[51\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[52\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[53\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[54\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[55\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[56\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[57\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[58\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[59\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[60\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[61\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[62\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[63\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[0\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[1\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[3\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[4\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[5\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[6\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[3\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_lparam\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[6\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_lparam\[7\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_lparam\[8\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_lparam\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_supply0 (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_supply1 (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_tri0 (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_tri1 (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_tri (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_triand (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_trior (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_wand (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_wor (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_wire (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_uwire (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_inout (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE test (NET (clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199)) (rstn (T0 110) (T1 890) (TZ 0) (TX 0) (TB 0) (TC 1)) (state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46)) (state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) (state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) (state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) (state_w\[0\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_w\[1\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_w\[2\] (T0 430) (T1 570) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_w\[3\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 47)) (state_w\[4\] (T0 420) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 48)) (state_array[0]\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[0]\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) (state_array[0]\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[0]\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) (state_array[0]\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) (state_array[1]\[0\] (T0 420) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 47)) (state_array[1]\[1\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[1]\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[1]\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) (state_array[1]\[4\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[2]\[0\] (T0 420) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 48)) (state_array[2]\[1\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[2]\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[2]\[3\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[2]\[4\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 47)) ) (INSTANCE unnamedblk1 (NET (i\[0\] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1)) (i\[1\] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1)) (i\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE unnamedblk2 (NET (i\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[1\] (T0 120) (T1 880) (TZ 0) (TX 0) (TB 0) (TC 1)) (i\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) ) verilator-5.044/test_regress/t/t_class_member_sens.py0000755000542200017500000000072615125463617023472 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_param_avec.v0000644000542200017500000000217215125463617021713 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; sub #(.IDX(0), .CHK(10)) i0(); sub #(.IDX(2), .CHK(12)) i2(); sub #(.IDX(7), .CHK(17)) i7(); always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule module sub (); function integer get_element; input integer index; input integer array_arg[7:0]; get_element = array_arg[index]; endfunction parameter integer IDX = 5; parameter integer CHK = 5; localparam integer array[0:7] = '{10, 11, 12, 13, 14, 15, 16, 17}; localparam element1 = array[IDX]; localparam elementf = get_element(IDX, array); initial begin `checkh (element1, CHK); `checkh (elementf, CHK); end endmodule verilator-5.044/test_regress/t/t_net_dtype_bad.py0000755000542200017500000000076615125463617022613 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_interface_gen2_noinl.py0000755000542200017500000000103715125463617024054 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_gen2.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_typedef_package.py0000755000542200017500000000073415125463617023120 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_unopt_converge_print_bad.out0000644000542200017500000000024215125463617025232 0ustar mahmoudyfreeshell-V{t#,#} 'stl' region trigger index 0 is active: @([hybrid] x) %Error: t/t_unopt_converge.v:7: Settle region did not converge after 100 tries Aborting... verilator-5.044/test_regress/t/t_param_default_bad.py0000755000542200017500000000076615125463617023424 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_trace_fst_sc.v0000644000542200017500000000444415125463617022260 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // Author: Yu-Sheng Lin johnjohnlys@media.ee.ntu.edu.tw // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc; reg rstn; parameter real fst_gparam_real = 1.23; localparam real fst_lparam_real = 4.56; real fst_real = 1.23; integer fst_integer; bit fst_bit; logic fst_logic; int fst_int; shortint fst_shortint; longint fst_longint; byte fst_byte; parameter fst_parameter = 123; localparam fst_lparam = 456; supply0 fst_supply0; supply1 fst_supply1; tri0 fst_tri0; tri1 fst_tri1; tri fst_tri; wire fst_wire; logic [4:0] state; Test test (/*AUTOINST*/ // Outputs .state (state[4:0]), // Inputs .clk (clk), .rstn (rstn)); // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin // Setup rstn <= ~'1; end else if (cyc<10) begin rstn <= ~'1; end else if (cyc<90) begin rstn <= ~'0; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( input clk, input rstn, output logic [4:0] state ); logic [4:0] state_w; logic [4:0] state_array [3]; assign state = state_array[0]; always_comb begin state_w[4] = state_array[2][0]; state_w[3] = state_array[2][4]; state_w[2] = state_array[2][3] ^ state_array[2][0]; state_w[1] = state_array[2][2]; state_w[0] = state_array[2][1]; end always_ff @(posedge clk or negedge rstn) begin if (!rstn) begin for (int i = 0; i < 3; i++) state_array[i] <= 'b1; end else begin for (int i = 0; i < 2; i++) state_array[i] <= state_array[i+1]; state_array[2] <= state_w; end end endmodule verilator-5.044/test_regress/t/t_inst_dtree_inlbd.py0000755000542200017500000000111615125463617023310 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_inst_dtree.v" test.compile(v_flags2=['+define+INLINE_B +define+INLINE_D'], verilator_flags2=['-trace']) test.execute() test.passes() verilator-5.044/test_regress/t/t_mod_param_class_typedef5.py0000755000542200017500000000077115125463617024737 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_sys_readmem_bad_end.py0000755000542200017500000000100015125463617023734 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_tri_gate_notif1_pins_inout.py0000755000542200017500000000141215125463617025324 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" test.compile(make_top_shell=False, make_main=False, v_flags2=['+define+T_NOTIF1'], make_flags=['CPPFLAGS_ADD=-DT_NOTIF1'], verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) test.execute() test.passes() verilator-5.044/test_regress/t/t_udp_bad_first_input.out0000644000542200017500000000046415125463617024205 0ustar mahmoudyfreeshell%Error: t/t_udp_bad_first_input.v:8:7: First UDP port must be the output port : ... note: In instance 'top' 8 | input a, b, c; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_altera_lpm_add_sub.py0000755000542200017500000000111115125463617023574 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module]) test.passes() verilator-5.044/test_regress/t/t_tri_top_en_out.cpp0000644000542200017500000001657615125463617023200 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module, C driver code // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Paul Wright. // SPDX-License-Identifier: CC0-1.0 #include "verilated.h" #include "TestCheck.h" #include VM_PREFIX_INCLUDE #include int main(int argc, char** argv, char**) { int errors; // Setup context, defaults, and parse command line Verilated::debug(0); const std::unique_ptr contextp{new VerilatedContext}; contextp->commandArgs(argc, argv); // Construct the Verilated model, from Vtop.h generated from Verilating const std::unique_ptr topp{new VM_PREFIX{contextp.get()}}; // Initial input topp->drv_en = 0; topp->single_bit_io = rand() & 1; topp->bidir_single_bit_io = rand() & 1; topp->bus_64_io = 0; topp->bidir_bus_64_io = rand() & 0xffffffffffffffff; topp->bus_128_io[0] = 0; topp->bus_128_io[1] = 0; topp->bus_128_io[2] = 0; topp->bus_128_io[3] = 0; topp->bidir_bus_128_io[0] = rand() & 0xffffffff; topp->bidir_bus_128_io[1] = rand() & 0xffffffff; topp->bidir_bus_128_io[2] = rand() & 0xffffffff; topp->bidir_bus_128_io[3] = rand() & 0xffffffff; topp->sub_io = rand() & 1; topp->test_en = 1; errors = 0; // Simulate until $finish while (!contextp->gotFinish()) { // Evaluate model topp->eval(); // Advance time (to scheduled events) if (!topp->eventsPending()) break; contextp->time(topp->nextTimeSlot()); // We want to check that the __en and __out signals can be accessed printf("Info:(cpp): drv_en = %x\n", topp->drv_en); printf("Info:(cpp): bidir_single_bit_io__en = %x\n", topp->bidir_single_bit_io__en); printf("Info:(cpp): bidir_bus_64_io__en = %x\n", (unsigned int)topp->bidir_bus_64_io__en); printf("Info:(cpp): bidir_bus_128_io__en = %x,%x,%x,%x\n", topp->bidir_bus_128_io__en[3], topp->bidir_bus_128_io__en[2], topp->bidir_bus_128_io__en[1], topp->bidir_bus_128_io__en[0]); printf("Info:(cpp): sub_io__en = %x\n", topp->sub_io__en); printf("Info:(cpp): bidir_single_bit_io = %x\n", topp->bidir_single_bit_io__out); printf("Info:(cpp): bidir_bus_64_io = %x\n", (unsigned int)topp->bidir_bus_64_io__out); printf("Info:(cpp): bidir_bus_128_io = %x,%x,%x,%x\n", topp->bidir_bus_128_io__out[3], topp->bidir_bus_128_io__out[2], topp->bidir_bus_128_io__out[1], topp->bidir_bus_128_io__out[0]); printf("Info:(cpp): sub_io = %x\n", topp->sub_io__out); // Loop back if verilog is driving // Verilator will not do this for itself // We must implement the top-level resolution if (topp->sub_io__en) topp->sub_io = topp->sub_io__out; if (topp->bidir_single_bit_io__en) { topp->bidir_single_bit_io = topp->bidir_single_bit_io__out; } // For bus signals, overwrite the bits which are driven by verilog, preserve the others if (topp->bidir_bus_64_io__en) { topp->bidir_bus_64_io = ((~topp->bidir_bus_64_io__en) & topp->bidir_bus_64_io) | (topp->bidir_bus_64_io__en & topp->bidir_bus_64_io__out); } for (int i = 0; i < 4; i++) { if (topp->bidir_bus_128_io__en[i]) { topp->bidir_bus_128_io[i] = ((~topp->bidir_bus_128_io__en[i]) & topp->bidir_bus_128_io[i]) | (topp->bidir_bus_128_io__en[i] & topp->bidir_bus_128_io__out[i]); } } // Has the verilog code finished a test loop? if (topp->loop_done == 1) { // Check the expected __en output if (topp->drv_en & 0x1) { TEST_CHECK_EQ(uint64_t(topp->sub_io__en), 1); TEST_CHECK_EQ(uint64_t(topp->bidir_single_bit_io__en), 1); } else { TEST_CHECK_EQ(uint64_t(topp->sub_io__en), 0); TEST_CHECK_EQ(uint64_t(topp->bidir_single_bit_io__en), 0); } for (int i = 0; i < 4; i++) { // __en enabled? if ((topp->drv_en & (1 << i)) != 0) { TEST_CHECK_EQ(uint64_t(topp->bidir_bus_64_io__en >> (i * 16) & 0xffff), 0xffff); TEST_CHECK_EQ(uint64_t(topp->bidir_bus_128_io__en[i]), 0xffffffff); } // __en not enabled else { TEST_CHECK_EQ(uint64_t(topp->bidir_bus_64_io__en >> (i * 16) & 0xffff), 0x0000); TEST_CHECK_EQ(uint64_t(topp->bidir_bus_128_io__en[i]), 0x00000000); } } // for if (topp->drv_en == 15) { topp->test_en = 0; } else { topp->drv_en++; // Drive the bits verilog shouldn't be driving if (topp->drv_en & 1) { topp->single_bit_io = rand() & 1; topp->bidir_single_bit_io = rand() & 1; topp->sub_io = rand() & 1; topp->bidir_bus_64_io = ((rand() & 0xffff) << 0) | (topp->bidir_bus_64_io & 0xffffffffffff0000); topp->bidir_bus_128_io[0] = rand() & 0xffffffff; } else { topp->single_bit_io = 0; topp->bidir_single_bit_io = 0; topp->sub_io = 0; topp->bidir_bus_64_io = (topp->bidir_bus_64_io & 0xffffffffffff0000); topp->bidir_bus_128_io[0] = 0; } if (topp->drv_en & 2) { topp->bidir_bus_64_io = ((rand() & 0xffff) << 16) | (topp->bidir_bus_64_io & 0xffffffff0000ffff); topp->bidir_bus_128_io[1] = rand() & 0xffffffff; } else { topp->bidir_bus_64_io = (topp->bidir_bus_64_io & 0xffffffff0000ffff); topp->bidir_bus_128_io[1] = 0; } if (topp->drv_en & 4) { topp->bidir_bus_64_io = (((uint64_t)(rand() & 0xffff)) << 32) | (topp->bidir_bus_64_io & 0xffff0000ffffffff); topp->bidir_bus_128_io[2] = rand() & 0xffffffff; } else { topp->bidir_bus_64_io = (topp->bidir_bus_64_io & 0xffff0000ffffffff); topp->bidir_bus_128_io[2] = 0; } if (topp->drv_en & 8) { topp->bidir_bus_64_io = (((uint64_t)(rand() & 0xffff)) << 48) | (topp->bidir_bus_64_io & 0x0000ffffffffffff); topp->bidir_bus_128_io[3] = rand() & 0xffffffff; } else { topp->bidir_bus_64_io = (topp->bidir_bus_64_io & 0x0000ffffffffffff); topp->bidir_bus_128_io[3] = 0; } } // Invert the input side topp->bidir_single_bit_io = (~topp->bidir_single_bit_io) & 0x1; topp->bidir_bus_64_io = ~topp->bidir_bus_64_io; for (int i = 0; i < 4; i++) topp->bidir_bus_128_io[i] = ~topp->bidir_bus_128_io[i]; } // if (loop_done) if (errors != 0) break; } // Final model cleanup topp->final(); return 0; } verilator-5.044/test_regress/t/t_clk_2in.cpp0000644000542200017500000000233015125463617021447 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include VM_PREFIX_INCLUDE unsigned int main_time = 0; double sc_time_stamp() { return main_time; } VM_PREFIX* topp = nullptr; void clockit(int clk1, int clk0) { topp->clks = clk1 << 1 | clk0; #ifndef T_CLK_2IN_VEC topp->c1 = clk1; topp->c0 = clk0; #endif #ifdef TEST_VERBOSE printf("[%u] c1=%d c0=%d\n", main_time, clk1, clk0); #endif topp->eval(); main_time++; } int main(int argc, char* argv[]) { Verilated::debug(0); Verilated::commandArgs(argc, argv); topp = new VM_PREFIX; topp->check = 0; clockit(0, 0); main_time += 10; for (int i = 0; i < 2; i++) { clockit(0, 0); clockit(0, 1); clockit(1, 1); clockit(0, 0); clockit(1, 1); clockit(1, 0); clockit(0, 0); clockit(0, 1); clockit(1, 0); clockit(0, 0); } topp->check = 1; clockit(0, 0); topp->final(); VL_DO_DANGLING(delete topp, topp); } verilator-5.044/test_regress/t/t_real_cast.py0000755000542200017500000000072615125463617021743 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios("vlt") test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_lint_realcvt_bad.py0000755000542200017500000000103315125463617023272 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["-Wwarn-REALCVT"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_param_concat_bad.out0000644000542200017500000000206215125463617023412 0ustar mahmoudyfreeshell%Warning-WIDTHCONCAT: t/t_param_concat.v:19:15: Unsized numbers/parameters not allowed in concatenations. : ... note: In instance 't' 19 | if ({UNSIZED,UNSIZED+1} != {32'd10, 32'd11}) $stop; | ^~~~~~~ ... For warning description see https://verilator.org/warn/WIDTHCONCAT?v=latest ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. %Warning-WIDTHCONCAT: t/t_param_concat.v:19:22: Unsized numbers/parameters not allowed in replications. : ... note: In instance 't' 19 | if ({UNSIZED,UNSIZED+1} != {32'd10, 32'd11}) $stop; | ^ %Warning-WIDTHCONCAT: t/t_param_concat.v:20:17: Unsized numbers/parameters not allowed in replications. : ... note: In instance 't' 20 | if ({2{UNSIZED}} != {32'd10, 32'd10}) $stop; | ^~~~~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_order_2d.v0000644000542200017500000000424415125463617021317 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2015 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire input_signal = crc[0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire output_signal; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .output_signal (output_signal), // Inputs .input_signal (input_signal)); // Aggregate outputs into a single result vector wire [63:0] result = {63'h0, output_signal}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc<10) begin sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h765b2e12b25ec97b if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( input input_signal, output output_signal ); // bug872 // verilator lint_off UNOPTFLAT wire some_signal[1:0][1:0]; assign some_signal[0][0] = input_signal; assign some_signal[0][1] = some_signal[0][0]; assign some_signal[1][0] = some_signal[0][1]; assign some_signal[1][1] = some_signal[1][0]; assign output_signal = some_signal[1][1]; endmodule verilator-5.044/test_regress/t/t_param_wide_io.py0000755000542200017500000000073515125463617022605 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() #test.execute() test.passes() verilator-5.044/test_regress/t/t_nba_commit_queue.v0000644000542200017500000002756515125463617023146 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) `define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t(clk); input clk; logic [31:0] cyc = 0; always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end reg [63:0] crc = 64'h5aef0c8d_d70a4497; always @ (posedge clk) crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; `define at_posedge_clk_on_cycle(n) always @(posedge clk) if (cyc == n) // Case 1: narrow packed variable, whole element updates only - 1D typedef logic [31:0] elem1_t; typedef elem1_t array1_t[128]; array1_t array1; `at_posedge_clk_on_cycle(0) begin for (int i = 0 ; i < 128; ++i) array1[i] = 0; for (int i = 0 ; i < 128; ++i) `checkh(array1[i], 0); end `at_posedge_clk_on_cycle(1) begin for (int i = 0 ; i < 128; ++i) `checkh(array1[i], 0); for (int i = 0 ; i < 128; ++i) array1[i] <= i; for (int i = 0 ; i < 128; ++i) `checkh(array1[i], 0); end `at_posedge_clk_on_cycle(2) begin for (int i = 0 ; i < 128; ++i) `checkh(array1[i], i); for (int i = 0 ; i < 128; ++i) array1[i] <= ~i; for (int i = 0 ; i < 128; ++i) `checkh(array1[i], i); end `at_posedge_clk_on_cycle(3) begin for (int i = 0 ; i < 128; ++i) `checkh(array1[i], ~i); for (int i = 0 ; i < 128; ++i) array1[i] <= -1; for (int i = 0 ; i < 128; ++i) `checkh(array1[i], ~i); end `at_posedge_clk_on_cycle(4) begin for (int i = 0 ; i < 128; ++i) `checkh(array1[i], -1); end // Case 2: wide packed variable, whole element updates only - 1D typedef logic [127:0] elem2_t; typedef elem2_t array2_t[128]; array2_t array2; `at_posedge_clk_on_cycle(0) begin for (int i = 0 ; i < 128; ++i) array2[i] = 0; for (int i = 0 ; i < 128; ++i) `checkh(array2[i], 0); end `at_posedge_clk_on_cycle(1) begin for (int i = 0 ; i < 128; ++i) `checkh(array2[i], 0); for (int i = 0 ; i < 128; ++i) array2[i] <= {4{i}}; for (int i = 0 ; i < 128; ++i) `checkh(array2[i], 0); end `at_posedge_clk_on_cycle(2) begin for (int i = 0 ; i < 128; ++i) `checkh(array2[i], {4{i}}); for (int i = 0 ; i < 128; ++i) array2[i] <= {4{~i}}; for (int i = 0 ; i < 128; ++i) `checkh(array2[i], {4{i}}); end `at_posedge_clk_on_cycle(3) begin for (int i = 0 ; i < 128; ++i) `checkh(array2[i], {4{~i}}); for (int i = 0 ; i < 128; ++i) array2[i] <= '1; for (int i = 0 ; i < 128; ++i) `checkh(array2[i], {4{~i}}); end `at_posedge_clk_on_cycle(4) begin for (int i = 0 ; i < 128; ++i) `checkh(array2[i], ~128'b0); end // Case 3: wide packed variable, whole element updates only - 2D typedef logic [127:0] elem3_t; typedef elem3_t array3sub_t[512]; typedef array3sub_t array3_t[128]; array3_t array3; `at_posedge_clk_on_cycle(0) begin for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 512; ++j) array3[i][j] = 0; for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 512; ++j) `checkh(array3[i][j], 0); end `at_posedge_clk_on_cycle(1) begin for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 512; ++j) `checkh(array3[i][j], 0); for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 512; ++j) array3[i][j] <= {4{i}}; for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 512; ++j) `checkh(array3[i][j], 0); end `at_posedge_clk_on_cycle(2) begin for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 512; ++j) `checkh(array3[i][j], {4{i}}); for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 512; ++j) array3[i][j] <= {4{~i}}; for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 512; ++j) `checkh(array3[i][j], {4{i}}); end `at_posedge_clk_on_cycle(3) begin for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 512; ++j) `checkh(array3[i][j], {4{~i}}); for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 512; ++j) array3[i][j] <= '1; for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 512; ++j) `checkh(array3[i][j], {4{~i}}); end `at_posedge_clk_on_cycle(4) begin for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 512; ++j) `checkh(array3[i][j], ~128'b0); end // Case 4: real typedef real elem4_t; typedef elem4_t array4_t[128]; array4_t array4; `at_posedge_clk_on_cycle(0) begin for (int i = 0 ; i < 128; ++i) array4[i] = 1e-5; for (int i = 0 ; i < 128; ++i) `checkr(array4[i], 1e-5); end `at_posedge_clk_on_cycle(1) begin for (int i = 0 ; i < 128; ++i) `checkr(array4[i], 1e-5); for (int i = 0 ; i < 128; ++i) array4[i] <= 3.14*real'(i); for (int i = 0 ; i < 128; ++i) `checkr(array4[i], 1e-5); end `at_posedge_clk_on_cycle(2) begin for (int i = 0 ; i < 128; ++i) `checkr(array4[i], 3.14*real'(i)); for (int i = 0 ; i < 128; ++i) array4[i] <= 2.78*real'(i); for (int i = 0 ; i < 128; ++i) `checkr(array4[i], 3.14*real'(i)); end `at_posedge_clk_on_cycle(3) begin for (int i = 0 ; i < 128; ++i) `checkr(array4[i], 2.78*real'(i)); for (int i = 0 ; i < 128; ++i) array4[i] <= 1e50; for (int i = 0 ; i < 128; ++i) `checkr(array4[i], 2.78*real'(i)); end `at_posedge_clk_on_cycle(4) begin for (int i = 0 ; i < 128; ++i) `checkr(array4[i], 1e50); end // Case 5: narrow packed variable, partial element updates - 1D typedef logic [31:0] elem5_t; typedef elem5_t array5_t[128]; array5_t array5; `at_posedge_clk_on_cycle(0) begin for (int i = 0 ; i < 128; ++i) array5[i] = -1; for (int i = 0 ; i < 128; ++i) `checkh(array5[i], -1); end `at_posedge_clk_on_cycle(1) begin for (int i = 0 ; i < 128; ++i) `checkh(array5[i], -1); for (int i = 0 ; i < 128; ++i) array5[i][0] <= 1'b0; for (int i = 0 ; i < 128; ++i) array5[i][1] <= 1'b0; for (int i = 0 ; i < 128; ++i) array5[i][2] <= 1'b0; for (int i = 0 ; i < 128; ++i) array5[i][1] <= 1'b1; for (int i = 0 ; i < 128; ++i) `checkh(array5[i], -1); end `at_posedge_clk_on_cycle(2) begin for (int i = 0 ; i < 128; ++i) `checkh(array5[i], 32'hffff_fffa); for (int i = 0 ; i < 128; ++i) array5[i][18:16] <= i[3:1]; for (int i = 0 ; i < 128; ++i) array5[i][19:17] <= ~i[2:0]; for (int i = 0 ; i < 128; ++i) `checkh(array5[i], 32'hffff_fffa); end `at_posedge_clk_on_cycle(3) begin for (int i = 0 ; i < 128; ++i) `checkh(array5[i], {12'hfff, ~i[2:0], i[1], 16'hfffa}); for (int i = 0 ; i < 128; ++i) array5[i] <= -1; for (int i = 0 ; i < 128; ++i) `checkh(array5[i], {12'hfff, ~i[2:0], i[1], 16'hfffa}); end `at_posedge_clk_on_cycle(4) begin for (int i = 0 ; i < 128; ++i) `checkh(array5[i], -1); end // Case 6: wide packed variable, partial element updates - 1D typedef logic [99:0] elem6_t; typedef elem6_t array6_t[128]; array6_t array6; `at_posedge_clk_on_cycle(0) begin for (int i = 0 ; i < 128; ++i) array6[i] = -1; for (int i = 0 ; i < 128; ++i) `checkh(array6[i], -1); end `at_posedge_clk_on_cycle(1) begin for (int i = 0 ; i < 128; ++i) `checkh(array6[i], -1); for (int i = 0 ; i < 128; ++i) array6[i][80] <= 1'b0; for (int i = 0 ; i < 128; ++i) array6[i][81] <= 1'b0; for (int i = 0 ; i < 128; ++i) array6[i][82] <= 1'b0; for (int i = 0 ; i < 128; ++i) array6[i][81] <= 1'b1; for (int i = 0 ; i < 128; ++i) `checkh(array6[i], -1); end `at_posedge_clk_on_cycle(2) begin for (int i = 0 ; i < 128; ++i) `checkh(array6[i], 100'hf_fffa_ffff_ffff_ffff_ffff_ffff); for (int i = 0 ; i < 128; ++i) array6[i][86:84] <= ~i[3:1]; for (int i = 0 ; i < 128; ++i) array6[i][87:85] <= i[2:0]; for (int i = 0 ; i < 128; ++i) `checkh(array6[i], 100'hf_fffa_ffff_ffff_ffff_ffff_ffff); end `at_posedge_clk_on_cycle(3) begin for (int i = 0 ; i < 128; ++i) `checkh(array6[i], {12'hfff, i[2:0], ~i[1], 84'ha_ffff_ffff_ffff_ffff_ffff}); for (int i = 0 ; i < 128; ++i) array6[i] <= -1; for (int i = 0 ; i < 128; ++i) `checkh(array6[i], {12'hfff, i[2:0], ~i[1], 84'ha_ffff_ffff_ffff_ffff_ffff}); end `at_posedge_clk_on_cycle(4) begin for (int i = 0 ; i < 128; ++i) `checkh(array6[i], -1); end // Case 7: variable partial updates typedef logic [99:0] elem7_t; typedef elem7_t array7sub_t[256]; typedef array7sub_t array7_t[128]; array7_t array7_nba; array7_t array7_ref; always @(posedge clk) begin if (cyc == 0) begin for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 256; ++j) array7_nba[i][j] = 100'b0; for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 256; ++j) array7_ref[i][j] = ~100'b0; end else begin for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 256; ++j) `checkh(array7_nba[i][j], ~array7_ref[i][j]); for (int i = 0 ; i < 128; ++i) begin for (int j = 0 ; j < 256; ++j) begin array7_nba[i[6:0] ^ crc[30+:7]][j[7:0] ^ crc[10+:8]][7'((crc % 10) * 5) +: 5] <= ~crc[4+:5]; array7_ref[i[6:0] ^ crc[30+:7]][j[7:0] ^ crc[10+:8]][7'((crc % 10) * 5) +: 5] = crc[4+:5]; end end end end // Case 8: Mixed dynamic/non-dynamic typedef longint elem8_t; typedef elem8_t array8_t[4]; array8_t array8; `at_posedge_clk_on_cycle(0) begin array8[0] <= 0; array8[1] <= 0; array8[2] <= 0; array8[3] <= 0; end `at_posedge_clk_on_cycle(1) begin `checkh(array8[0], 0); `checkh(array8[1], 0); `checkh(array8[2], 0); `checkh(array8[3], 0); array8[1] <= 42; array8[3] <= 63; for (int i = 1 ; i < 3 ; ++i) array8[i] <= 2*i + 7; array8[1] <= 74; end `at_posedge_clk_on_cycle(3) begin `checkh(array8[0], 0); `checkh(array8[1], 74); `checkh(array8[2], 11); `checkh(array8[3], 63); end // Case 9: string typedef string elem9_t; typedef elem9_t array9_t[10]; array9_t array9; `at_posedge_clk_on_cycle(0) begin for (int i = 0 ; i < 10; ++i) array9[i] = "squid"; for (int i = 0 ; i < 10; ++i) `checks(array9[i], "squid"); end `at_posedge_clk_on_cycle(1) begin for (int i = 0 ; i < 10; ++i) `checks(array9[i], "squid"); for (int i = 0 ; i < 10; ++i) array9[i] <= "octopus"; for (int i = 0 ; i < 10; ++i) `checks(array9[i], "squid"); end `at_posedge_clk_on_cycle(2) begin for (int i = 0 ; i < 10; ++i) `checks(array9[i], "octopus"); for (int i = 1 ; i < 9; ++i) begin string tmp; $sformat(tmp, "%0d-legged-cephalopod", i); array9[i] <= tmp; end for (int i = 0 ; i < 10; ++i) `checks(array9[i], "octopus"); end `at_posedge_clk_on_cycle(3) begin `checks(array9[0], "octopus"); `checks(array9[1], "1-legged-cephalopod"); `checks(array9[2], "2-legged-cephalopod"); `checks(array9[3], "3-legged-cephalopod"); `checks(array9[4], "4-legged-cephalopod"); `checks(array9[5], "5-legged-cephalopod"); `checks(array9[6], "6-legged-cephalopod"); `checks(array9[7], "7-legged-cephalopod"); `checks(array9[8], "8-legged-cephalopod"); `checks(array9[9], "octopus"); for (int i = 0 ; i < 10; ++i) array9[i] <= "cuttlefish"; `checks(array9[0], "octopus"); `checks(array9[1], "1-legged-cephalopod"); `checks(array9[2], "2-legged-cephalopod"); `checks(array9[3], "3-legged-cephalopod"); `checks(array9[4], "4-legged-cephalopod"); `checks(array9[5], "5-legged-cephalopod"); `checks(array9[6], "6-legged-cephalopod"); `checks(array9[7], "7-legged-cephalopod"); `checks(array9[8], "8-legged-cephalopod"); `checks(array9[9], "octopus"); end `at_posedge_clk_on_cycle(4) begin for (int i = 0 ; i < 10; ++i) `checks(array9[i], "cuttlefish"); end endmodule verilator-5.044/test_regress/t/t_fork_join_none_virtual.v0000644000542200017500000000226215125463617024362 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 event evt1; typedef enum {ENUM_VALUE} enum_t; class Foo; int m_member; enum_t m_en; virtual task do_something(); fork #20 begin m_member++; $display("this's m_member: %0d m_en: %s", m_member, m_en.name()); if (m_member != 3) $stop; ->evt1; end #10 begin m_member++; bar(this); end join_none endtask static task bar(Foo foo); fork begin foo.m_member++; $display("foo's m_member: %0d m_en: %s", foo.m_member, foo.m_en.name()); if (foo.m_member != 2) $stop; end join_none endtask endclass class Subfoo extends Foo; virtual task do_something();#5;endtask endclass module t(); initial begin Subfoo subfoo; Foo foo; subfoo = new; subfoo.do_something(); foo = new; foo.m_member = 0; foo.do_something(); end always @(evt1) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_enum_param_class.v0000644000542200017500000000165015125463617023126 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Anthony Donlon. // SPDX-License-Identifier: CC0-1.0 /// (See bug4551) /// Verilator creates an AstEnumItemRef for each reference. If the enum is inside a parameterizable class/module, it /// should be handled properly. class ClsParam #( int A = 0 ); typedef enum int { EN_A = A + 0, EN_B = A + 1, EN_C = A + 2 } enums_t; int val = EN_C; function int test(); return EN_C; endfunction endclass; module t; // localparam ENUM_VAL = ClsParam#(100)::EN_C; // TODO: Unsupported: dotted expressions in parameters // $info("ENUM_VAL: %0d", ENUM_VAL); ClsParam#(100) cls = new; initial begin if (cls.test() != 102) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_interface_modport_export.v0000644000542200017500000000253115125463617024721 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // A test of the export parameter used with modport // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 interface test_if; // Pre-declare function extern function myfunc (input logic val); // Interface variable logic data; // Modport modport mp_e( export myfunc, output data ); // Modport modport mp_i( import myfunc, output data ); endinterface // test_if module t (/*AUTOARG*/ // Inputs clk ); input clk; test_if i (); testmod_callee testmod_callee_i (.ie (i.mp_e)); testmod_caller testmod_caller_i (.clk (clk), .ii (i.mp_i)); endmodule module testmod_callee ( test_if.mp_e ie ); function automatic logic ie.myfunc (input logic val); begin myfunc = (val == 1'b0); end endfunction endmodule // testmod_caller module testmod_caller ( input clk, test_if.mp_i ii ); always @(posedge clk) begin ii.data = 1'b0; if (ii.myfunc (1'b0)) begin $write("*-* All Finished *-*\n"); $finish; end else begin $stop; end end endmodule verilator-5.044/test_regress/t/t_class_static_method_protect_ids.py0000755000542200017500000000152315125463617026415 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_class_static_method.v" # This test makes randomly named .cpp/.h files, which tend to collect, so remove them first for filename in (glob.glob(test.obj_dir + "/*_PS*.cpp") + glob.glob(test.obj_dir + "/*_PS*.h") + glob.glob(test.obj_dir + "/*.d")): test.unlink_ok(filename) test.compile(verilator_flags2=["--protect-ids", "--protect-key SECRET_KEY"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_lint_ftask_output_assign_bad.v0000644000542200017500000000114315125463617025542 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input logic in, output wire wire_out, output logic reg_out ); function void set_f(output set_out, input set_in); set_out = 1; endfunction task set_task(output set_out, input set_in); set_out = 1; endtask always_comb begin : setCall set_f(wire_out, in); set_f(reg_out, in); set_task(wire_out, in); set_task(reg_out, in); end endmodule verilator-5.044/test_regress/t/t_param_pattern3.v0000644000542200017500000000131415125463617022532 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on class Class_A #( parameter int myparam = 32 ); endclass module tb_top; localparam int WIDTH_A = 32; localparam int WIDTH_B = 2 * 16; Class_A #(32) a; Class_A #(WIDTH_A) b; Class_A #(WIDTH_B) c; initial begin #1; a = b; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_force_release_net_reverse.py0000755000542200017500000000105615125463617025202 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_force_release_net.v" test.compile(verilator_flags2=['+define+REVERSE']) test.execute() test.passes() verilator-5.044/test_regress/t/t_sdf_annotate_unsup.v0000644000542200017500000000115015125463617023507 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $sdf_annotate("file.sdf"); $sdf_annotate("file.sdf",); $sdf_annotate("file.sdf", t); // TArguments are all optional, so test more exhaustively $sdf_annotate("file.sdf", t, "config_file", "log_file", "mtm_spec", "scale_factors", "scale_type"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_std_randomize.v0000644000542200017500000001070715125463617022462 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by PlanV GmbH. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop; `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on class std_randomize_class; rand bit [7:0] addr; rand bit [31:0] data; rand bit [63:0] data_x_4; bit [7:0] old_addr; bit [31:0] old_data; bit [63:0] old_data_x_4; function bit std_randomize(); int success; bit valid; old_addr = addr; old_data = data; old_data_x_4 = data_x_4; success = std::randomize(addr, data); valid = (success == 1) && !(addr == old_addr || data == old_data) && data_x_4 == old_data_x_4; return valid; endfunction endclass module t_scope_std_randomize; bit [7:0] addr; bit [15:0] data; int limit[10]; bit [6:0] limit_7bits[10]; bit [14:0] limit_15bits[10]; bit [30:0] limit_31bits[10]; bit [62:0] limit_63bits[10]; bit [94:0] limit_95bits[10]; function bit run(); int ready; int success; bit [7:0] old_addr; bit [15:0] old_data; int old_ready; old_addr = addr; old_data = data; old_ready = ready; success = randomize(addr, ready); // std::randomize if (success == 0) return 0; if (addr == old_addr && data != old_data && ready == old_ready) begin return 0; end return 1; endfunction std_randomize_class test; initial begin // Test class member randomization test = new(); test.old_addr = test.addr; test.old_data = test.data; test.old_data_x_4 = test.data_x_4; `checkd(std::randomize(test.addr, test.data), 1); if (test.addr == test.old_addr && test.data == test.old_data) $stop; `checkd(test.data_x_4, test.old_data_x_4); // Test function-based randomization `checkd(run(), 1); `checkd(test.std_randomize(), 1); // Test array randomization with constraints `checkd(std::randomize(limit) with { foreach (limit[i]) { limit[i] < 32'd100;}}, 1); foreach (limit[i]) if (limit[i] >= 32'd100) $stop; `checkd(std::randomize(limit_7bits) with { foreach (limit_7bits[i]) { limit_7bits[i] < 7'd10;}}, 1); foreach (limit_7bits[i]) if (limit_7bits[i] >= 7'd10) $stop; `checkd(std::randomize(limit_15bits) with { foreach (limit_15bits[i]) { limit_15bits[i] < 15'd1000;}}, 1); foreach (limit_15bits[i]) if (limit_15bits[i] >= 15'd1000) $stop; `checkd(std::randomize(limit_31bits) with { foreach (limit_31bits[i]) { limit_31bits[i] < 31'd100000;}}, 1); foreach (limit_31bits[i]) if (limit_31bits[i] >= 31'd100000) $stop; `checkd(std::randomize(limit_63bits) with { foreach (limit_63bits[i]) { limit_63bits[i] < 63'd10000000000;}}, 1); foreach (limit_63bits[i]) if (limit_63bits[i] >= 63'd10000000000) $stop; `checkd(std::randomize(limit_95bits) with { foreach (limit_95bits[i]) { limit_95bits[i] < 95'd1000000000000;}}, 1); foreach (limit_95bits[i]) if (limit_95bits[i] >= 95'd1000000000000) $stop; foreach (limit_63bits[i]) begin `checkd(std::randomize(limit_63bits[i]) with { limit_63bits[i] >= 63'd50; limit_63bits[i] < 63'd100;}, 1); if ((limit_63bits[i] < 63'd50) || (limit_63bits[i] >= 63'd100)) `stop; end foreach (limit_95bits[i]) begin `checkd(std::randomize(limit_95bits[i]) with { limit_95bits[i] >= 95'd50; limit_95bits[i] < 95'd1000;}, 1); if (limit_95bits[i] < 95'd50 || limit_95bits[i] >= 95'd1000) $stop; end // Test mixed argument types (VarRef + MemberSel + ArraySel) with interdependent constraints `checkd(std::randomize(addr, test.addr, limit_31bits[0]) with { addr > 8'd10; addr < 8'd50; test.addr > addr; test.addr < 8'd100; limit_31bits[0] > 31'(test.addr); limit_31bits[0] < 31'd200; }, 1); if (addr <= 8'd10 || addr >= 8'd50) `stop; if (test.addr <= addr || test.addr >= 8'd100) `stop; if (limit_31bits[0] <= 31'(test.addr) || limit_31bits[0] >= 31'd200) `stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_func_range.v0000644000542200017500000000312315125463617021721 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; // verilator lint_off WIDTH `define INT_RANGE 31:0 `define INT_RANGE_MAX 31 `define VECTOR_RANGE 63:0 reg [`INT_RANGE] stashb, stasha, stashn, stashm; function [`VECTOR_RANGE] copy_range; input [`VECTOR_RANGE] y; input [`INT_RANGE] b; input [`INT_RANGE] a; input [`VECTOR_RANGE] x; input [`INT_RANGE] n; input [`INT_RANGE] m; begin copy_range = y; stashb = b; stasha = a; stashn = n; stashm = m; end endfunction parameter DATA_SIZE = 16; parameter NUM_OF_REGS = 32; reg [NUM_OF_REGS*DATA_SIZE-1 : 0] memread_rf; reg [DATA_SIZE-1:0] memread_rf_reg; always @(memread_rf) begin : memread_convert memread_rf_reg = copy_range('d0, DATA_SIZE-'d1, DATA_SIZE-'d1, memread_rf, DATA_SIZE-'d1, DATA_SIZE-'d1); end integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin memread_rf = 512'haa; end if (cyc==3) begin if (stashb != 'd15) $stop; if (stasha != 'd15) $stop; if (stashn != 'd15) $stop; if (stashm != 'd15) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.044/test_regress/t/t_select_set.v0000644000542200017500000000256415125463617021754 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; reg [63:0] inwide; reg [39:0] addr; integer cyc; initial cyc=1; always @ (posedge clk) begin `ifdef TEST_VERBOSE $write ("%x %x\n", cyc, addr); `endif if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin addr <= 40'h12_3456_7890; end if (cyc==2) begin if (addr !== 40'h1234567890) $stop; addr[31:0] <= 32'habcd_efaa; end if (cyc==3) begin if (addr !== 40'h12abcdefaa) $stop; addr[39:32] <= 8'h44; inwide <= 64'hffeeddcc_11334466; end if (cyc==4) begin if (addr !== 40'h44abcdefaa) $stop; addr[31:0] <= inwide[31:0]; end if (cyc==5) begin if (addr !== 40'h4411334466) $stop; $display ("Flip [%x]\n", inwide[3:0]); addr[{2'b0,inwide[3:0]}] <= ! addr[{2'b0,inwide[3:0]}]; end if (cyc==6) begin if (addr !== 40'h4411334426) $stop; end if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.044/test_regress/t/t_case_write1.out0000644000542200017500000001674715125463617022402 0ustar mahmoudyfreeshell[2] crc=0000000000000097 1410 [3] crc=000000000000012e 1410 [4] crc=000000000000025d 1410 [5] crc=00000000000004ba 1410 [6] crc=0000000000000974 1410 [7] crc=00000000000012e9 1410 [8] crc=00000000000025d3 1410 [9] crc=0000000000004ba7 1410 [10] crc=000000000000974e 1410 [11] crc=0000000000012e9d 1410 [12] crc=0000000000025d3a 1410 [13] crc=000000000004ba74 1410 [14] crc=00000000000974e9 1410 [15] crc=000000000012e9d3 1410 [16] crc=000000000025d3a7 1410 [17] crc=00000000004ba74e 1410 [18] crc=0000000000974e9d 1410 [19] crc=00000000012e9d3a 1410 [20] crc=00000000025d3a74 1410 [21] crc=0000000004ba74e9 1410 [22] crc=000000000974e9d3 1304a:000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002031303039;17 1304b:000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002031303039203233 1304c:000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020313030392032332031333033;4 1304d:000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002031303039203233203133303320313338 1304e:203130303920323320313330332031333820202020202020202020202020202020202020202020202020202020202020202020202020202020202020202020202020202020202020202020202020 1304: 1009 23 1303 138 [23] crc=0000000012e9d3a7 1313: 1009 46 1309 1311 143 1312 [24] crc=0000000025d3a74e 1129: 1009 172 407 175 408 409 410 1106 [25] crc=000000004ba74e9d 1017: 1009 223 1014 880 885 1015 1016 1007 [26] crc=00000000974e9d3a 1231: 1229 967 1230 718 [27] crc=000000012e9d3a74 1410 [28] crc=000000025d3a74e9 1370: 1009 58 1369 19 [29] crc=00000004ba74e9d3 1036: 1009 194 1033 1034 1008 1035 880 [30] crc=0000000974e9d3a7 1409:i [31] crc=00000012e9d3a74e 1321: 1009 29 1320 137 144 141 138 148 [32] crc=00000025d3a74e9d 1383:§ [33] crc=0000004ba74e9d3a 1021: 1009 216 1018 882 884 1019 1020 1007 [34] crc=000000974e9d3a74 1017: 1009 197 1014 882 883 1015 1016 1008 [35] crc=0000012e9d3a74e9 1231: 1228 979 1230 713 [36] crc=0000025d3a74e9d3 1013: 1009 194 1011 1006 1008 1012 880 [37] crc=000004ba74e9d3a7 1409:i [38] crc=00000974e9d3a74e 1321: 1009 29 1320 137 144 141 138 148 [39] crc=000012e9d3a74e9d 1383:§ [40] crc=000025d3a74e9d3a 1021: 1009 216 1018 882 884 1019 1020 1007 [41] crc=00004ba74e9d3a74 1017: 1009 197 1014 882 883 1015 1016 1008 [42] crc=0000974e9d3a74e9 1231: 1228 979 1230 713 [43] crc=00012e9d3a74e9d3 1013: 1009 194 1011 1006 1008 1012 880 [44] crc=00025d3a74e9d3a7 1409:i [45] crc=0004ba74e9d3a74e 1321: 1009 29 1320 137 144 141 138 148 [46] crc=000974e9d3a74e9d 1383:§ [47] crc=0012e9d3a74e9d3a 1021: 1009 216 1018 882 884 1019 1020 1007 [48] crc=0025d3a74e9d3a74 1017: 1009 197 1014 882 883 1015 1016 1008 [49] crc=004ba74e9d3a74e9 1231: 1228 979 1230 713 [50] crc=00974e9d3a74e9d3 1013: 1009 194 1011 1006 1008 1012 880 [51] crc=012e9d3a74e9d3a7 1409:i [52] crc=025d3a74e9d3a74e 1321: 1009 29 1320 137 144 141 138 148 [53] crc=04ba74e9d3a74e9d 1383:§ [54] crc=0974e9d3a74e9d3a 1021: 1009 216 1018 882 884 1019 1020 1007 [55] crc=12e9d3a74e9d3a74 1017: 1009 197 1014 882 883 1015 1016 1008 [56] crc=25d3a74e9d3a74e9 1231: 1228 979 1230 713 [57] crc=4ba74e9d3a74e9d3 1013: 1009 194 1011 1006 1008 1012 880 [58] crc=974e9d3a74e9d3a7 1409:i [59] crc=2e9d3a74e9d3a74f 1321: 1009 29 1320 137 144 141 138 149 [60] crc=5d3a74e9d3a74e9e 1383:§ [61] crc=ba74e9d3a74e9d3d 1021: 1009 216 1018 882 884 1019 1020 1007 [62] crc=74e9d3a74e9d3a7b 1017: 1009 197 1014 882 883 1015 1016 1008 [63] crc=e9d3a74e9d3a74f7 1231: 1228 979 1230 713 [64] crc=d3a74e9d3a74e9ef 1013: 1009 194 1011 1006 1008 1012 880 [65] crc=a74e9d3a74e9d3df 1409:i [66] crc=4e9d3a74e9d3a7bf 1321: 1009 29 1320 137 144 141 145 149 [67] crc=9d3a74e9d3a74f7e 1383:§ [68] crc=3a74e9d3a74e9efc 1021: 1009 216 1018 882 884 1019 1020 1007 [69] crc=74e9d3a74e9d3df9 1017: 1009 197 1014 882 883 1015 1016 1008 [70] crc=e9d3a74e9d3a7bf3 1231: 1228 979 1230 713 [71] crc=d3a74e9d3a74f7e6 1013: 1009 194 1011 1006 1008 1012 880 [72] crc=a74e9d3a74e9efcc 1409:i [73] crc=4e9d3a74e9d3df98 1321: 1009 29 1320 137 147 149 143 142 [74] crc=9d3a74e9d3a7bf30 1383:§ [75] crc=3a74e9d3a74f7e61 1021: 1009 216 1018 882 885 1019 1020 1007 [76] crc=74e9d3a74e9efcc3 1017: 1009 197 1014 882 884 1015 1016 1008 [77] crc=e9d3a74e9d3df987 1231: 1228 982 1230 713 [78] crc=d3a74e9d3a7bf30f 1013: 1009 194 1011 1006 1008 1012 881 885 [79] crc=a74e9d3a74f7e61f 1409:w [80] crc=4e9d3a74e9efcc3f 1321: 1009 30 1320 149 146 146 137 149 [81] crc=9d3a74e9d3df987e 1383:ß [82] crc=3a74e9d3a7bf30fc 1021: 1009 225 1018 882 885 1019 1020 1008 [83] crc=74e9d3a74f7e61f9 1017: 1009 218 1014 882 884 1015 1016 1008 [84] crc=e9d3a74e9efcc3f3 1231: 1228 981 1230 708 [85] crc=d3a74e9d3df987e6 1013: 1009 232 1011 1005 1008 1012 881 883 [86] crc=a74e9d3a7bf30fcc 1409:s [87] crc=4e9d3a74f7e61f98 1262: 1009 1006 1258 846 1259 1006 1260 833 1261 [88] crc=9d3a74e9efcc3f30 1321: 1009 124 1320 146 137 149 137 134 [89] crc=3a74e9d3df987e61 1383:˜ [90] crc=74e9d3a7bf30fcc3 1036: 1009 215 1033 1034 1008 1035 879 verilator-5.044/test_regress/t/t_udp_nonsequential_x.v0000644000542200017500000000137315125463617023703 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Michael Bikovitsky. // SPDX-License-Identifier: CC0-1.0 module t (); wire true1; not1 a(true1, '0); wire false1; not1 b(false1, '1); wire true2; not1 c(true2, '0); wire false2; not1 d(false2, '1); initial begin if (true1 != '1) $stop; if (false1 != '0) $stop; if (true2 != '1) $stop; if (false2 != '0) $stop; $finish; end endmodule primitive not1(q, d); output q; input d; table 0 : 1; 1 : 0; x : x; endtable endprimitive primitive not2(q, d); output q; input d; table 0 : 1; 1 : 0; X : X; endtable endprimitive verilator-5.044/test_regress/t/t_class_new_scoped_bad.out0000644000542200017500000000052215125463617024275 0ustar mahmoudyfreeshell%Error: t/t_class_new_scoped_bad.v:17:16: new() assignment not legal to non-class 'Pkg' : ... note: In instance 't' 17 | c = Pkg::new; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_mem_multiwire.py0000755000542200017500000000073415125463617022664 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_unpacked_str_pair.py0000755000542200017500000000073415125463617023502 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_struct_cons_cast.v0000644000542200017500000000246515125463617023202 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class uvm_policy; typedef enum { NEVER, STARTED, FINISHED } recursion_state_e; endclass typedef enum { UVM_DEFAULT_POLICY = 0, UVM_DEEP = (1<<16), UVM_SHALLOW = (1<<17), UVM_REFERENCE = (1<<18) } uvm_recursion_policy_enum; class Cls; typedef struct { uvm_policy::recursion_state_e state; bit ret_val; } state_info_t; state_info_t m_recur_states/*[uvm_object][uvm_object]*/[uvm_recursion_policy_enum]; function uvm_recursion_policy_enum get_recursion_policy(); return UVM_DEEP; endfunction function bit get_ret_val(); return $c(1); endfunction function void test(); bit ret_val; ret_val = $c1(1); // See issue #4568 m_recur_states[get_recursion_policy()] = '{uvm_policy::FINISHED, ret_val}; endfunction endclass module t; initial begin Cls c; c = new; $display("%p", c); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_clocker.out0000644000542200017500000000372715125463617021610 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 # clk $end $var wire 1 $ res $end $var wire 8 % res8 [7:0] $end $var wire 16 & res16 [15:0] $end $scope module $unit $end $var wire 32 + ID_MSB [31:0] $end $upscope $end $scope module t $end $var wire 1 # clk $end $var wire 1 $ res $end $var wire 8 % res8 [7:0] $end $var wire 16 & res16 [15:0] $end $var wire 8 ' clkSet [7:0] $end $var wire 1 # clk_1 $end $var wire 3 ( clk_3 [2:0] $end $var wire 4 ) clk_4 [3:0] $end $var wire 1 # clk_final $end $var wire 8 * count [7:0] $end $upscope $end $upscope $end $enddefinitions $end #0 0# 0$ b00000000 % b0000000000000000 & b00000000 ' b000 ( b0000 ) b00000000 * b00000000000000000000000000000001 + #10 1# 1$ b11101111 % b0000000111111111 & b11111111 ' b111 ( b1111 ) b00000001 * #15 0# 0$ b00000000 % b0000001000000000 & b00000000 ' b000 ( b0000 ) b00000010 * #20 1# 1$ b11101111 % b0000001111111111 & b11111111 ' b111 ( b1111 ) b00000011 * #25 0# 0$ b00000000 % b0000010000000000 & b00000000 ' b000 ( b0000 ) b00000100 * #30 1# 1$ b11101111 % b0000010111111111 & b11111111 ' b111 ( b1111 ) b00000101 * #35 0# 0$ b00000000 % b0000011000000000 & b00000000 ' b000 ( b0000 ) b00000110 * #40 1# 1$ b11101111 % b0000011111111111 & b11111111 ' b111 ( b1111 ) b00000111 * #45 0# 0$ b00000000 % b0000100000000000 & b00000000 ' b000 ( b0000 ) b00001000 * #50 1# 1$ b11101111 % b0000100111111111 & b11111111 ' b111 ( b1111 ) b00001001 * #55 0# 0$ b00000000 % b0000101000000000 & b00000000 ' b000 ( b0000 ) b00001010 * #60 1# 1$ b11101111 % b0000101111111111 & b11111111 ' b111 ( b1111 ) b00001011 * #65 0# 0$ b00000000 % b0000110000000000 & b00000000 ' b000 ( b0000 ) b00001100 * #70 1# 1$ b11101111 % b0000110111111111 & b11111111 ' b111 ( b1111 ) b00001101 * #75 0# 0$ b00000000 % b0000111000000000 & b00000000 ' b000 ( b0000 ) b00001110 * #80 1# 1$ b11101111 % b0000111111111111 & b11111111 ' b111 ( b1111 ) b00001111 * verilator-5.044/test_regress/t/t_interface_gen14.py0000755000542200017500000000077115125463617022744 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_opt_subst.py0000755000542200017500000000113515125463617022023 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.compile(verilator_flags2=["--stats"]) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, Substituted temps\s+(\d+)', 43) test.execute() test.passes() verilator-5.044/test_regress/t/t_lint_assigneqexpr_bad.py0000755000542200017500000000161715125463617024353 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_lint_assigneqexpr.v" test.lint(verilator_flags2=['-Wall -Wno-DECLFILENAME'], fails=True, expect_filename=test.golden_filename) test.extract(in_filename=test.top_filename, out_filename=test.root + "/docs/gen/ex_ASSIGNEQEXPR_faulty.rst", lines="26-29") test.extract(in_filename=test.golden_filename, out_filename=test.root + "/docs/gen/ex_ASSIGNEQEXPR_msg.rst", lines="7-8") test.passes() verilator-5.044/test_regress/t/t_dpi_export_scope_bad.out0000644000542200017500000000020615125463617024327 0ustar mahmoudyfreeshell%Error: unknown:0: Testbench C called 'dpix_task' but this DPI export function exists only in other scopes, not scope 't' Aborting... verilator-5.044/test_regress/t/t_interface_gen3_noinl.py0000755000542200017500000000103715125463617024055 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_gen3.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_clocking_input_0_delay.v0000644000542200017500000000121615125463617024220 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 `timescale 1ms / 1ns module t; bit clk = 0; bit data = 1; bit cb_data; initial forever #5 clk = ~clk; assign cb_data = cb.data; clocking cb @(posedge clk); input #0 data; endclocking initial begin @(posedge clk) data = 0; end initial begin #4 if (data != 1) $stop; if (cb.data != 0) $stop; #1; #1step; if (cb.data != 0) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_trace_public_func.vlt0000644000542200017500000000040615125463617023622 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config public -module "glbl" -function "setGSR" verilator-5.044/test_regress/t/t_order_clkinst.v0000644000542200017500000000551015125463617022456 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // verilator lint_off COMBDLY // verilator lint_off LATCH // verilator lint_off UNOPT // verilator lint_off UNOPTFLAT // verilator lint_off MULTIDRIVEN reg c1_start; initial c1_start = 0; wire [31:0] c1_count; comb_loop c1 (.count(c1_count), .start(c1_start)); wire s2_start = c1_start; wire [31:0] s2_count; seq_loop s2 (.count(s2_count), .start(s2_start)); wire c3_start = (s2_count[0]); wire [31:0] c3_count; comb_loop c3 (.count(c3_count), .start(c3_start)); reg [7:0] cyc; initial cyc = 0; always @ (posedge clk) begin //$write("[%0t] %x counts %x %x %x\n", $time,cyc,c1_count,s2_count,c3_count); cyc <= cyc + 8'd1; case (cyc) 8'd00: begin c1_start <= 1'b0; end 8'd01: begin c1_start <= 1'b1; end default: ; endcase case (cyc) 8'd02: begin // On Verilator, we expect these comparisons to match exactly, // confirming that our settle loop repeated the exact number of // iterations we expect. No '$stop' should be called here, and we // should reach the normal '$finish' below on the next cycle. if (c1_count!=32'h3) $stop; if (s2_count!=32'h3) $stop; if (c3_count!=32'h3) $stop; end 8'd03: begin $write("*-* All Finished *-*\n"); $finish; end default: ; endcase end endmodule module comb_loop (/*AUTOARG*/ // Outputs count, // Inputs start ); input start; output reg [31:0] count = 0; reg [31:0] runnerm1, runner; initial runner = 0; always @ (posedge start) begin count = 0; runner = 3; end always @ (/*AS*/runner) begin runnerm1 = runner - 32'd1; end always @ (/*AS*/runnerm1) begin if (runner > 0) begin count = count + 1; runner = runnerm1; $write ("%m count=%d runner =%x\n",count, runnerm1); end end endmodule module seq_loop (/*AUTOARG*/ // Outputs count, // Inputs start ); input start; output reg [31:0] count; initial count = 0; reg [31:0] runnerm1, runner; initial runner = 0; always @ (posedge start) begin count = 0; runner <= 3; end always @ (/*AS*/runner) begin runnerm1 = runner - 32'd1; end always @ (/*AS*/runnerm1) begin if (runner > 0) begin count = count + 1; runner <= runnerm1; $write ("%m count=%d runner<=%x\n",count, runnerm1); end end endmodule verilator-5.044/test_regress/t/t_vlt_syntax_bad.out0000644000542200017500000000265315125463617023204 0ustar mahmoudyfreeshell%Error: t/t_vlt_syntax_bad.vlt:9:20: sensitivity not expected for attribute 9 | public -module "t" @(posedge clk) | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_vlt_syntax_bad.vlt:11:1: isolate_assignments only applies to signals or functions/tasks 11 | isolate_assignments -module "t" | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_vlt_syntax_bad.vlt:13:1: Argument -match only supported for lint_off 13 | tracing_off --file "*" -match "nothing" | ^~~~~~~~~~~ %Error: t/t_vlt_syntax_bad.vlt:15:1: Argument -scope only supported for tracing_on/off 15 | lint_off --rule UNOPTFLAT -scope "top*" | ^~~~~~~~ %Error: t/t_vlt_syntax_bad.vlt:16:1: Argument -scope only supported for tracing_on/off_off 16 | lint_off --rule UNOPTFLAT -scope "top*" -levels 0 | ^~~~~~~~ %Error: t/t_vlt_syntax_bad.vlt:17:1: Argument -scope only supported for tracing_on/off 17 | lint_on --rule UNOPTFLAT -scope "top*" | ^~~~~~~ %Error: t/t_vlt_syntax_bad.vlt:18:1: Argument -scope only supported for tracing_on/off_off 18 | lint_on --rule UNOPTFLAT -scope "top*" -levels 0 | ^~~~~~~ %Error: t/t_vlt_syntax_bad.vlt:20:1: forceable missing -module 20 | forceable -module "" -var "net_*" | ^~~~~~~~~ %Error: t/t_vlt_syntax_bad.vlt:22:1: missing -var 22 | forceable -module "top" -var "" | ^~~~~~~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_gantt_two.py0000755000542200017500000000375715125463617022023 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test for bin/verilator_gantt, import vltest_bootstrap test.priority(50) test.scenarios('vlt_all') test.top_filename = "t/t_gantt.v" test.pli_filename = "t/t_gantt_c.cpp" threads_num = (2 if test.vltmt else 1) test.compile( make_top_shell=False, make_main=False, verilator_flags2=["--prof-exec --exe", test.pli_filename, "t/t_gantt_two.cpp"], # Checks below care about thread count, so use 2 (minimum reasonable) threads=threads_num, make_flags=["CPPFLAGS_ADD=\"-DVL_NO_LEGACY -DTEST_USE_THREADS=" + str(threads_num) + "\""]) test.execute(all_run_flags=[ "+verilator+prof+exec+start+4", " +verilator+prof+exec+window+4", " +verilator+prof+exec+file+" + test.obj_dir + "/profile_exec.dat", " +verilator+prof+vlt+file+" + test.obj_dir + "/profile.vlt"]) # yapf:disable gantt_log = test.obj_dir + "/gantt.log" # The profiling data goes direct to the runtime's STDOUT # (maybe that should go to a separate file - gantt.dat?) test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt", test.obj_dir + "/profile_exec.dat", "--vcd " + test.obj_dir + "/profile_exec.vcd", "| tee " + gantt_log]) # yapf:disable if test.vltmt: test.file_grep(gantt_log, r'Total threads += +(\d+)', 2) test.file_grep(gantt_log, r'Total mtasks += +(\d+)', 6) else: test.file_grep(gantt_log, r'Total threads += +(\d+)', 1) test.file_grep(gantt_log, r'Total mtasks += +(\d+)', 0) test.file_grep(gantt_log, r'\|\s+4\s+\|\s+4\.0+\s+\|\s+eval') # Diff to itself, just to check parsing test.vcd_identical(test.obj_dir + "/profile_exec.vcd", test.obj_dir + "/profile_exec.vcd") test.passes() verilator-5.044/test_regress/t/t_trace_two_port_cc.out0000644000542200017500000000365115125463617023662 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module topa $end $var wire 1 # clk $end $scope module t $end $var wire 1 # clk $end $var wire 32 $ cyc [31:0] $end $var wire 32 % c_trace_on [31:0] $end $scope module sub $end $var wire 32 & inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $scope module topb $end $var wire 1 ( clk $end $scope module t $end $var wire 1 ( clk $end $var wire 32 + cyc [31:0] $end $var wire 32 , c_trace_on [31:0] $end $var real 64 ) r $end $scope module sub $end $var wire 32 - inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #10 1# b00000000000000000000000000000001 $ b00000000000000000000000000000000 % 1( r0 ) b00000000000000000000000000000001 & b00000000000000000000000000000001 + b00000000000000000000000000000000 , b00000000000000000000000000000010 - #15 0# 0( #20 1# b00000000000000000000000000000010 $ b00000000000000000000000000000011 % 1( r0.1 ) #25 0# 0( #30 1# b00000000000000000000000000000011 $ b00000000000000000000000000000100 % 1( r0.2 ) #35 0# 0( #40 1# b00000000000000000000000000000100 $ b00000000000000000000000000000101 % 1( r0.3 ) #45 0# 0( #50 1# b00000000000000000000000000000101 $ b00000000000000000000000000000110 % 1( r0.4 ) #55 0# 0( #60 1# b00000000000000000000000000000110 $ b00000000000000000000000000000111 % 1( r0.5 ) #65 0# 0( #70 1# b00000000000000000000000000000111 $ b00000000000000000000000000001000 % 1( r0.6 ) #75 0# 0( #80 1# b00000000000000000000000000001000 $ b00000000000000000000000000001001 % 1( r0.7 ) #85 0# 0( #90 1# b00000000000000000000000000001001 $ b00000000000000000000000000001010 % 1( r0.7999999999999999 ) #95 0# 0( #100 1# b00000000000000000000000000001010 $ b00000000000000000000000000001011 % 1( r0.8999999999999999 ) #105 0# 0( #110 1# b00000000000000000000000000001011 $ b00000000000000000000000000001100 % 1( r0.9999999999999999 ) verilator-5.044/test_regress/t/t_func_v.v0000644000542200017500000000124615125463617021076 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Chandan Egbert. // SPDX-License-Identifier: CC0-1.0 // See bug569 module t(); `ifdef T_FUNC_V_NOINL // verilator no_inline_module `endif level1 ul1(); initial ul1.doit(4'b0); endmodule module level1(); `ifdef T_FUNC_V_NOINL // verilator no_inline_module `endif level2 ul2(); task doit(input logic [3:0] v); ul2.mem = v; $write("*-* All Finished *-*\n"); $finish; endtask endmodule module level2(); `ifdef T_FUNC_V_NOINL // verilator no_inline_module `endif logic [3:0] mem; endmodule verilator-5.044/test_regress/t/t_timing_func_bad.py0000755000542200017500000000103015125463617023103 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename, verilator_flags2=['--no-timing']) test.passes() verilator-5.044/test_regress/t/t_inside_unpacked.v0000644000542200017500000000163515125463617022745 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; int array [10]; logic l; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 0) begin // Setup array[0] = 10; array[1] = 20; array[9] = 90; end else if (cyc < 99) begin l = (10 inside {array}); if (l != 1) $stop; l = (20 inside {array}); if (l != 1) $stop; l = (90 inside {array}); if (l != 1) $stop; l = (99 inside {array}); if (l != 0) $stop; end else if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.044/test_regress/t/t_var_dup2.v0000644000542200017500000000055015125463617021335 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Legal with ANSI Verilog 2001 style ports module t ( output wire ok_ow, output reg ok_or); wire ok_o_w; reg ok_o_r; endmodule verilator-5.044/test_regress/t/t_math_eq.py0000755000542200017500000000073415125463617021423 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_select_bad_range.out0000644000542200017500000000126015125463617023415 0ustar mahmoudyfreeshell%Warning-SELRANGE: t/t_select_bad_range.v:16:15: Selection index out of range: 44:44 outside 43:0 : ... note: In instance 't' 16 | sel = mi[44]; | ^ ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Warning-SELRANGE: t/t_select_bad_range.v:17:16: Selection index out of range: 44:41 outside 43:0 : ... note: In instance 't' 17 | sel2 = mi[44:41]; | ^ %Error: Exiting due to verilator-5.044/test_regress/t/t_assert_iff_bad2.py0000755000542200017500000000110515125463617023013 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = 't_assert_iff.v' test.compile(verilator_flags2=['--assert --cc --coverage-user -DFAIL2']) test.execute(fails=True) test.passes() verilator-5.044/test_regress/t/t_dpi_2exp_bad.py0000755000542200017500000000077615125463617022333 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_semaphore.v0000644000542200017500000000240315125463617021575 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Methods defined by IEEE: // class semaphore; // function new(int keyCount = 0); // function void put(int keyCount = 1); // task get(int keyCount = 1); // function int try_get(int keyCount = 1); // endclass `ifndef SEMAPHORE_T `define SEMAPHORE_T semaphore `endif // verilator lint_off DECLFILENAME module t; // From UVM: `SEMAPHORE_T s; `SEMAPHORE_T s2; initial begin s = new(1); if (s.try_get() == 0) $stop; if (s.try_get() != 0) $stop; s = new; if (s.try_get() != 0) $stop; s.put(); s.get(); s.put(2); s.get(2); s.put(2); if (s.try_get(2) <= 0) $stop; fork begin #10; // So later then get() starts below s.put(1); s.put(1); end begin if (s.try_get(1) != 0) $stop; s.get(); // Blocks until put s.get(); end join s2 = new; if (s2.try_get() != 0) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_math_countbits2_bad.out0000644000542200017500000000207615125463617024075 0ustar mahmoudyfreeshell%Error: t/t_math_countbits2_bad.v:15:15: Expected numeric type, but got a 'logic$[0:3]' data type : ... note: In instance 't' 15 | count = $countones(my_vec); | ^~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_math_countbits2_bad.v:16:15: Expected numeric type, but got a 'logic$[0:3]' data type : ... note: In instance 't' 16 | count = $countbits(my_vec, '0); | ^~~~~~~~~~ %Error: t/t_math_countbits2_bad.v:17:14: Expected numeric type, but got a 'logic$[0:3]' data type : ... note: In instance 't' 17 | bool = $onehot(my_vec); | ^~~~~~~ %Error: t/t_math_countbits2_bad.v:18:14: Expected numeric type, but got a 'logic$[0:3]' data type : ... note: In instance 't' 18 | bool = $onehot0(my_vec); | ^~~~~~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_foreach.v0000644000542200017500000001111615125463617021222 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; // verilator lint_off ASCRANGE // verilator lint_off WIDTH reg [63:0] sum; // Checked not in objects reg [63:0] add; reg [2:1] [4:3] array [5:6] [7:8]; reg [1:2] [3:4] larray [6:5] [8:7]; bit [31:0] depth1_array [0:0]; int oned [3:1]; int twod [3:1][9:8]; string str1; string str2; typedef struct packed { reg [1:0] [63:0] subarray; } str_t; typedef struct packed { str_t mid; } mid_t; mid_t strarray[3]; function [63:0] crc (input [63:0] sum, input [31:0] a, input [31:0] b, input [31:0] c, input [31:0] d); crc = {sum[62:0],sum[63]} ^ {4'b0,a[7:0], 4'h0,b[7:0], 4'h0,c[7:0], 4'h0,d[7:0]}; endfunction initial begin sum = 0; // We use 'index_' as the prefix for all loop vars, // this allows t_foreach.py to confirm that all loops // have been unrolled and flattened away and no loop vars // remain in the generated .cpp foreach (depth1_array[index_a]) begin sum = crc(sum, index_a, 0, 0, 0); // Ensure the index never goes out of bounds. // We used to get this wrong for an array of depth 1. assert (index_a != -1); assert (index_a != 1); end `checkh(sum, 64'h0); sum = 0; foreach (array[index_a]) begin sum = crc(sum, index_a, 0, 0, 0); end `checkh(sum, 64'h000000c000000000); sum = 0; foreach (array[index_a,index_b]) begin sum = crc(sum, index_a, index_b, 0, 0); end `checkh(sum, 64'h000003601e000000); sum = 0; foreach (array[index_a,index_b,index_c]) begin sum = crc(sum, index_a, index_b, index_c, 0); end `checkh(sum, 64'h00003123fc101000); sum = 0; foreach (array[index_a,index_b,index_c,index_d]) begin sum = crc(sum, index_a, index_b, index_c, index_d); end `checkh(sum, 64'h0030128ab2a8e557); // comma syntax sum = 0; foreach (array[,index_b]) begin $display(index_b); sum = crc(sum, 0, index_b, 0, 0); end `checkh(sum, 64'h0000000006000000); // sum = 0; foreach (larray[index_a]) begin sum = crc(sum, index_a, 0, 0, 0); end `checkh(sum, 64'h0000009000000000); sum = 0; foreach (larray[index_a,index_b]) begin sum = crc(sum, index_a, index_b, 0, 0); sum = sum + {4'b0,index_a[7:0], 4'h0,index_b[7:0]}; end `checkh(sum, 64'h000002704b057073); sum = 0; foreach (larray[index_a,index_b,index_c]) begin sum = crc(sum, index_a, index_b, index_c, 0); end `checkh(sum, 64'h00002136f9000000); sum = 0; foreach (larray[index_a,index_b,index_c,index_d]) begin sum = crc(sum, index_a, index_b, index_c, index_d); end `checkh(sum, 64'h0020179aa7aa0aaa); add = 0; strarray[0].mid.subarray[0] = 1; strarray[0].mid.subarray[1] = 2; strarray[1].mid.subarray[0] = 4; strarray[1].mid.subarray[1] = 5; strarray[2].mid.subarray[0] = 6; strarray[2].mid.subarray[1] = 7; foreach (strarray[s]) foreach (strarray[s].mid.subarray[ss]) add += strarray[s].mid.subarray[ss]; `checkh(add, 'h19); add = 0; foreach (oned[i]) begin ++add; break; end `checkh(add, 1); // 9 add = 0; foreach (oned[i]) begin ++add; continue; add += 100; end `checkh(add, 3); // 9, 8, 7 add = 0; foreach (twod[i, j]) begin ++add; break; end // See https://www.accellera.org/images/eda/sv-bc/10303.html `checkh(add, 1); // 3,9 add = 0; foreach (twod[i, j]) begin ++add; continue; add += 100; end `checkh(add, 6); foreach (twod[i, j]); // Null body check str1 = "abcd"; str2 = "1234"; foreach (str1[i]) begin str2[i] = str1[i]; end if (str1 != str2) $stop; str1 = ""; add = 0; foreach(str1[i]) begin add++; end `checkh(add, 0); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_interface_dups.py0000755000542200017500000000073415125463617023000 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_udp_tableeof_bad.py0000755000542200017500000000120315125463617023234 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--bbox-unsup"], fails=test.vlt_all) # Cannot use .out, get "$end" or "end of file" depending on bison version test.file_grep(test.compile_log_filename, r"EOF in 'table'") test.passes() verilator-5.044/test_regress/t/t_covergroup_with_sample_args_too_many_bad.out0000644000542200017500000000062415125463617030475 0ustar mahmoudyfreeshell%Error: t/t_covergroup_with_sample_args_too_many_bad.v:15:26: Too many arguments in function call to FUNC 'sample' : ... note: In instance 't' 15 | cov1.sample(5, 1'b0, 42); | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_no_trace_top.py0000755000542200017500000000132015125463617022451 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t_trace_cat.v" test.compile(make_top_shell=False, make_main=False, v_flags2=["--trace-vcd --no-trace-top --exe", test.pli_filename]) test.execute() test.vcd_identical(test.obj_dir + "/simno_trace_top.vcd", test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_order_multialways.v0000644000542200017500000000254415125463617023366 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [31:0] in_a; reg [31:0] in_b; reg [31:0] e,f,g,h; always @ (/*AS*/in_a) begin e = in_a; f = {e[15:0], e[31:16]}; g = {f[15:0], f[31:16]}; h = {g[15:0], g[31:16]}; end reg [31:0] e2,f2,g2,h2; always @ (/*AS*/f2, g2) begin h2 = {g2[15:0], g2[31:16]}; g2 = {f2[15:0], f2[31:16]}; end always @ (/*AS*/in_a, e2) begin f2 = {e2[15:0], e2[31:16]}; e2 = in_a; end integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; //$write("%d %x %x\n", cyc, h, h2); if (h != h2) $stop; if (cyc==1) begin in_a <= 32'h89a14fab; in_b <= 32'h7ab512fa; end if (cyc==2) begin in_a <= 32'hf4c11a42; in_b <= 32'h359967c6; if (h != 32'h4fab89a1) $stop; end if (cyc==3) begin if (h != 32'h1a42f4c1) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.044/test_regress/t/t_union_soft.py0000755000542200017500000000072615125463617022171 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_sys_fscanf_bad.py0000755000542200017500000000076615125463617022756 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_json_only_flat_vlvbound.v0000644000542200017500000000117015125463617024551 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module vlvbound_test ( input logic [15:0] i_a, input logic [15:0] i_b, output logic [6:0] o_a, output logic [6:0] o_b ); function automatic logic [6:0] foo(input logic [15:0] val); logic [6:0] ret; integer i; for (i=0 ; i < 7; i++) begin ret[i] = (val[i*2 +: 2] == 2'b00); end return ret; endfunction assign o_a = foo(i_a); assign o_b = foo(i_b); endmodule verilator-5.044/test_regress/t/t_flag_errorlimit_bad.v0000644000542200017500000000047115125463617023604 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; int u1; int u1; int u1; int u1; int u1; int u1; int u1; endmodule verilator-5.044/test_regress/t/t_queue_empty_bad.out0000644000542200017500000000107415125463617023327 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_queue_empty_bad.v:11:11: Unsupported/Illegal: empty queue ('{}') in this context : ... note: In instance 't' 11 | i = {} + 1; | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_queue_empty_bad.v:13:9: Unsupported/Illegal: empty queue ('{}') in this assign context : ... note: In instance 't' 13 | i = {}; | ^ %Error: Exiting due to verilator-5.044/test_regress/t/t_debug_fatalsrc_bad.py0000755000542200017500000000145115125463617023555 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') if 'VERILATOR_TEST_NO_GDB' in os.environ: test.skip("Skipping due to VERILATOR_TEST_NO_GDB") if not test.have_gdb: test.skip("No gdb installed") test.lint(verilator_flags2=["--debug-fatalsrc"], fails='any') test.file_grep(test.compile_log_filename, r'%Error: Internal Error: .*: --debug-fatal-src') test.file_grep(test.compile_log_filename, r'See the manual') test.passes() verilator-5.044/test_regress/t/t_pp_line_bad.v0000644000542200017500000000052415125463617022050 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `line `line 100 `line 200 somefile `line 300 "somefile 1 `line 400 "some file" `line 500 "somefile" 3 `line 600 "some file" 3 verilator-5.044/test_regress/t/t_hier_block.py0000755000542200017500000000323215125463617022102 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.priority(30) test.scenarios('vlt_all') # stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. test.clean_objs() # CI environment offers 2 VCPUs, 2 thread setting causes the following warning. # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. # So use 6 threads here though it's not optimal in performance, but ok. test.compile( v_flags2=['t/t_hier_block.cpp'], verilator_flags2=[ '--stats', '--hierarchical', '--Wno-TIMESCALEMOD', # '-GPARAM_A=100', '-pvalue+PARAM_B=200', '-DPARAM_OVERRIDE', # '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"' ], threads=(6 if test.vltmt else 1)) test.execute() test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^\s+\/\/\s+timeprecision\s+(\d+)ps;', 1) test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") test.file_grep(test.obj_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") test.file_grep(test.obj_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14) test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") test.passes() verilator-5.044/test_regress/t/t_var_pins_sc_biguint.py0000755000542200017500000000474115125463617024036 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" test.compile(verilator_flags2=["-sc --pins-sc-biguint --trace-vcd --exe", test.pli_filename], make_main=False) def hgrep(re): test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) hgrep(r'sc_core::sc_in\s+&i1;') hgrep(r'sc_core::sc_in\s+&i8;') hgrep(r'sc_core::sc_in\s+&i16;') hgrep(r'sc_core::sc_in\s+&i32;') hgrep(r'sc_core::sc_in\s+&i64;') hgrep(r'sc_core::sc_in\s>\s+&i65;') hgrep(r'sc_core::sc_in\s>\s+&i128;') hgrep(r'sc_core::sc_in\s>\s+&i513;') hgrep(r'sc_core::sc_in\s>\s+&ibv1;') hgrep(r'sc_core::sc_in\s>\s+&ibv16;') hgrep(r'sc_core::sc_out\s+&o1;') hgrep(r'sc_core::sc_out\s+&o8;') hgrep(r'sc_core::sc_out\s+&o16;') hgrep(r'sc_core::sc_out\s+&o32;') hgrep(r'sc_core::sc_out\s+&o64;') hgrep(r'sc_core::sc_out\s>\s+&o65;') hgrep(r'sc_core::sc_out\s>\s+&o128;') hgrep(r'sc_core::sc_out\s>\s+&o513;') hgrep(r'sc_core::sc_out\s>\s+&obv1;') hgrep(r'sc_core::sc_out\s>\s+&obv16;') # sc_biguint pragma overrides `--pins-sc-biguint` flag hgrep(r'sc_core::sc_in\s>\s+&ibu1;') hgrep(r'sc_core::sc_in\s>\s+&ibu8;') hgrep(r'sc_core::sc_in\s>\s+&ibu16;') hgrep(r'sc_core::sc_in\s>\s+&ibu64;') hgrep(r'sc_core::sc_in\s>\s+&ibu512;') hgrep(r'sc_core::sc_in\s>\s+&ibu601;') hgrep(r'sc_core::sc_out\s>\s+&obu1;') hgrep(r'sc_core::sc_out\s>\s+&obu8;') hgrep(r'sc_core::sc_out\s>\s+&obu16;') hgrep(r'sc_core::sc_out\s>\s+&obu64;') hgrep(r'sc_core::sc_out\s>\s+&obu512;') hgrep(r'sc_core::sc_out\s>\s+&obu601;') test.execute() test.passes() verilator-5.044/test_regress/t/t_interface_virtual_sched_ico.py0000755000542200017500000000103315125463617025504 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(verilator_flags2=["--binary"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_dpi_export_noopt.py0000755000542200017500000000131315125463617023373 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # irun -sv top.v t_dpi_export.v -cpost t_dpi_export_c.c -end import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_dpi_export.v" test.compile( v_flags2=["t/t_dpi_export_c.cpp"], verilator_flags2=["-Wall -Wno-DECLFILENAME -no-l2name", ("-O0" if test.vlt_all else "")]) test.execute() test.passes() verilator-5.044/test_regress/t/t_lint_unused_vlt.vlt0000644000542200017500000000046615125463617023377 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `verilator_config lint_off --rule UNDRIVEN // Checks UNUSED delegation to UNUSEDSIGNAL etc lint_off --rule UNUSED verilator-5.044/test_regress/t/t_clk_gate_ext.py0000755000542200017500000000073415125463617022436 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_bitsel_struct2.py0000755000542200017500000000073415125463617022755 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_trace_two_dump_sc.out0000644000542200017500000000364315125463617023664 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module topa $end $scope module t $end $var wire 1 # clk $end $var wire 32 $ cyc [31:0] $end $var wire 32 % c_trace_on [31:0] $end $scope module sub $end $var wire 32 & inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $scope module topb $end $scope module t $end $var wire 1 ( clk $end $var wire 32 + cyc [31:0] $end $var wire 32 , c_trace_on [31:0] $end $var real 64 ) r $end $scope module sub $end $var wire 32 - inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 0# b00000000000000000000000000000001 $ b00000000000000000000000000000000 % 0( r0 ) b00000000000000000000000000000001 & b00000000000000000000000000000001 + b00000000000000000000000000000000 , b00000000000000000000000000000010 - #10000 1# b00000000000000000000000000000010 $ b00000000000000000000000000000011 % 1( r0.1 ) #15000 0# 0( #20000 1# b00000000000000000000000000000011 $ b00000000000000000000000000000100 % 1( r0.2 ) #25000 0# 0( #30000 1# b00000000000000000000000000000100 $ b00000000000000000000000000000101 % 1( r0.3 ) #35000 0# 0( #40000 1# b00000000000000000000000000000101 $ b00000000000000000000000000000110 % 1( r0.4 ) #45000 0# 0( #50000 1# b00000000000000000000000000000110 $ b00000000000000000000000000000111 % 1( r0.5 ) #55000 0# 0( #60000 1# b00000000000000000000000000000111 $ b00000000000000000000000000001000 % 1( r0.6 ) #65000 0# 0( #70000 1# b00000000000000000000000000001000 $ b00000000000000000000000000001001 % 1( r0.7 ) #75000 0# 0( #80000 1# b00000000000000000000000000001001 $ b00000000000000000000000000001010 % 1( r0.7999999999999999 ) #85000 0# 0( #90000 1# b00000000000000000000000000001010 $ b00000000000000000000000000001011 % 1( r0.8999999999999999 ) #95000 0# 0( #100000 1# b00000000000000000000000000001011 $ b00000000000000000000000000001100 % 1( r0.9999999999999999 ) verilator-5.044/test_regress/t/t_sampled_expr_unsup.py0000755000542200017500000000106415125463617023717 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert -Wno-UNSIGNED'], fails=True) test.passes() verilator-5.044/test_regress/t/t_assoc_method.py0000755000542200017500000000073415125463617022455 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_tri_pull_unsup.v0000644000542200017500000000131415125463617022676 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; wire u1; wire u2; wire u3; wire u4; wire u5; wire u6; pullup (supply1) pu1(a); pullup (strong1) pu2(a); pullup (pull1) pu3(a); pullup (weak1) pu4(a); pullup (supply1, supply0) pu5(a); pullup (strong0, strong1) pu6(a); wire d1; wire d2; wire d3; wire d4; wire d5; wire d6; pulldown (supply0) pd1(a); pulldown (strong0) pd2(a); pulldown (pull0) pd3(a); pulldown (weak0) pd4(a); pulldown (supply0, supply1) pd5(a); pulldown (strong1, strong0) pd6(a); endmodule verilator-5.044/test_regress/t/t_constraint_method_bad.v0000644000542200017500000000060315125463617024144 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Packet; rand int m_one; constraint cons { m_one > 0 && m_one < 2; } task test1; cons.bad_method(1); // BAD endtask endclass module t; endmodule verilator-5.044/test_regress/t/t_assigndly_task.v0000644000542200017500000000072015125463617022631 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t ( input clk, input [7:0] d, input [2:0] a, output [7:0] q ); always_ff @(posedge clk) tick(a); logic [7:0] d_ = d; logic [7:0] q_; assign q = q_; task automatic tick(logic [2:0] a); q_[a] <= d_[a]; endtask endmodule verilator-5.044/test_regress/t/t_vlt_public_spec.py0000755000542200017500000000116415125463617023160 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--binary", "--vpi", test.name + ".vlt"]) test.execute() test.files_identical(test.run_log_filename, test.golden_filename, is_logfile=True, strip_hex=True) test.passes() verilator-5.044/test_regress/t/t_param_shift.v0000644000542200017500000000113015125463617022103 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2016 by Mandy Xu. // SPDX-License-Identifier: CC0-1.0 module t #(parameter[95:0] P = 1) (input clk); localparam [32:0] M = 4; function [M:0] gen_matrix; gen_matrix[0] = 1>> M; endfunction reg [95: 0] lfsr = 0; always @(posedge clk) begin lfsr <= (1 >> P); end wire [95: 0] lfsr_w = 1 >> P; localparam [95: 0] LFSR_P = 1 >> P; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_scheduling_initial_event.v0000644000542200017500000000570015125463617024654 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); // verilog_format: on module top; logic pEdge = 1'b0; logic nEdge = 1'b1; logic edgeP = 1'b0; logic edgeN = 1'b1; logic changeP = 1'b0; logic changeN = 1'b1; int pEdgeCnt = 0; int nEdgeCnt = 0; int edgePCnt = 0; int edgeNCnt = 0; int changePCnt = 0; int changeNCnt = 0; time pEdgeTime[3] = '{-1, -1, -1}; time nEdgeTime[3] = '{-1, -1, -1}; time edgePTime[3] = '{-1, -1, -1}; time edgeNTime[3] = '{-1, -1, -1}; time changePTime[3] = '{-1, -1, -1}; time changeNTime[3] = '{-1, -1, -1}; initial begin pEdge = 1'b1; nEdge = 1'b0; edgeP = 1'b1; edgeN = 1'b0; changeP = 1'b1; changeN = 1'b0; #10; pEdge = 1'b0; nEdge = 1'b1; edgeP = 1'b0; edgeN = 1'b1; changeP = 1'b0; changeN = 1'b1; #10; pEdge = 1'b1; nEdge = 1'b0; edgeP = 1'b1; edgeN = 1'b0; changeP = 1'b1; changeN = 1'b0; #10; $display("pEdgeCnt: %0d", pEdgeCnt); $display("nEdgeCnt: %0d", nEdgeCnt); $display("edgePCnt: %0d", edgePCnt); $display("edgeNCnt: %0d", edgeNCnt); $display("changePCnt: %0d", changePCnt); $display("changeNCnt: %0d", changeNCnt); $display("pEdgeTime: %p", pEdgeTime); $display("nEdgeTime: %p", nEdgeTime); $display("edgePTime: %p", edgePTime); $display("edgeNTime: %p", edgeNTime); $display("changePTime: %p", changePTime); $display("changeNTime: %p", changeNTime); `checkh(pEdgeCnt, 2); `checkh(nEdgeCnt, 2); `checkh(edgePCnt, 3); `checkh(edgeNCnt, 3); `checkh(changePCnt, 3); `checkh(changeNCnt, 3); `checkh(pEdgeTime[0], 0); `checkh(pEdgeTime[1], 20); `checkh(pEdgeTime[2], -1); `checkh(nEdgeTime[0], 0); `checkh(nEdgeTime[1], 20); `checkh(nEdgeTime[2], -1); `checkh(edgePTime[0], 0); `checkh(edgePTime[1], 10); `checkh(edgePTime[2], 20); `checkh(edgeNTime[0], 0); `checkh(edgeNTime[1], 10); `checkh(edgeNTime[2], 20); `checkh(changePTime[0], 0); `checkh(changePTime[1], 10); `checkh(changePTime[2], 20); `checkh(changeNTime[0], 0); `checkh(changeNTime[1], 10); `checkh(changeNTime[2], 20); $write("*-* All Finished *-*\n"); $finish; end always @(posedge pEdge) pEdgeTime[pEdgeCnt++] = $time; always @(negedge nEdge) nEdgeTime[nEdgeCnt++] = $time; always @(edge edgeP) edgePTime[edgePCnt++] = $time; always @(edge edgeN) edgeNTime[edgeNCnt++] = $time; always @(changeP) changePTime[changePCnt++] = $time; always @(changeN) changeNTime[changeNCnt++] = $time; endmodule // test verilator-5.044/test_regress/t/t_var_local.py0000755000542200017500000000073415125463617021747 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_case_inside.py0000755000542200017500000000073415125463617022253 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_trace_cat_fst.py0000755000542200017500000000137515125463617022610 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(make_top_shell=False, make_main=False, v_flags2=["--trace-fst --exe", test.pli_filename]) test.execute() test.fst_identical(test.obj_dir + "/simpart_0000.fst", "t/" + test.name + "__0000.out") test.fst_identical(test.obj_dir + "/simpart_0100.fst", "t/" + test.name + "__0100.out") test.passes() verilator-5.044/test_regress/t/t_func_wide_out_noinl.py0000755000542200017500000000121315125463617024027 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t_func_wide_out.v" test.compile( verilator_flags2=["-Wno-WIDTHTRUNC"], v_flags2=["+define+T_FUNC_WIDE_OUT_NOINL +define+TEST_NOINLINE t/t_func_wide_out_c.cpp"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_timing_wait3.v0000644000542200017500000000150515125463617022212 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; typedef process pr; pr p[4]; int n = 0; initial begin wait (p[1]); p[1].await(); p[0] = process::self(); if (n == 3) n++; #2 $write("*-* All Finished *-*\n"); $finish; end initial begin wait (p[2]); p[2].await(); p[1] = process::self(); if (n == 2) n++; end initial begin wait (p[3]); p[3].await(); p[2] = process::self(); if (n == 1) n++; end initial begin p[3] = process::self(); if (n == 0) n++; end initial #1 if (n != 4) $stop; initial #3 $stop; // timeout endmodule verilator-5.044/test_regress/t/t_flag_help_valgrind.py0000755000542200017500000000104615125463617023611 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 test.run(fails=False, cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator", "--help", "--valgrind"], tee=False, verilator_run=True) test.passes() verilator-5.044/test_regress/t/t_func_paramed.py0000755000542200017500000000073415125463617022431 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_func_call_super_arg.v0000644000542200017500000000107015125463617023606 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class base; function new(string name); $display(name); if (name == "42") $finish; endfunction function string retstr(); return $sformatf("%0d", $c("42")); endfunction endclass class derived extends base; function new(); super.new(retstr()); endfunction endclass module t; initial begin derived test = new; end endmodule verilator-5.044/test_regress/t/t_opt_inline_cfuncs_off.py0000755000542200017500000000140315125463617024332 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_opt_inline_cfuncs.v" # Disable inlining with --inline-cfuncs 0 test.compile(verilator_flags2=["--stats", "--binary", "--inline-cfuncs", "0"]) # Verify inlining did NOT happen (stat doesn't exist when pass is skipped) test.file_grep_not(test.stats, r'Optimizations, Inlined CFuncs\s+[1-9]') test.execute() test.passes() verilator-5.044/test_regress/t/t_dpi_export_context_bad.v0000644000542200017500000000071315125463617024343 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; export "DPI-C" task dpix_task; task dpix_task(); $write("Hello in %m\n"); endtask endmodule verilator-5.044/test_regress/t/t_flag_mmd.v0000644000542200017500000000035215125463617021361 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; endmodule verilator-5.044/test_regress/t/t_trace_array_saif_portable.py0000755000542200017500000000153115125463617025167 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_trace_array.v" test.golden_filename = "t/t_trace_array_saif.out" # Don't pass --trace-max-width 0, we shrink the file intentionally test.compile(verilator_flags2=[ '--cc --trace-saif --trace-structs --trace-max-width 0', '-CFLAGS -DVL_PORTABLE_ONLY' ]) test.execute() # saif_identical is very slow, so require exact match test.files_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_unpacked_str_init2.out0000644000542200017500000000051015125463617023740 0ustar mahmoudyfreeshellREGX: zero REGX: ra REGX: sp REGX: gp REGX: tp REGX: t0 REGX: t1 REGX: t2 REGX: s0/fp REGX: s1 REGX: a0 REGX: a1 REGX: a2 REGX: a3 REGX: a4 REGX: a5 REGX: a6 REGX: a7 REGX: s2 REGX: s3 REGX: s4 REGX: s5 REGX: s6 REGX: s7 REGX: s8 REGX: s9 REGX: s10 REGX: s11 REGX: t3 REGX: t4 REGX: t5 REGX: t6 OP: ILLEGAL *-* All Finished *-* verilator-5.044/test_regress/t/t_split_var_types.v0000644000542200017500000000262115125463617023043 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; logic [7:0] data = 0; // Test loop always @ (posedge clk) begin if (data != 15) begin data <= data + 8'd1; end else begin $write("*-* All Finished *-*\n"); $finish; end end bug5782 u_bug5782(.data_out()); bug5984 u_bug5984(.in(data)); endmodule // #5782 internal error with --trace-vcd. Bit range is not properly handled. module bug5782 ( output logic [31:0][15:0] data_out ); logic [31:0][15:0] data [8] /*verilator split_var*/; always begin data_out = data[7]; end endmodule // #5984 inconsistent assignment due to wrong bit range calculation. module bug5984 ( input logic [1:0][3:0] in ); logic [1:0][5:2] internal; for (genvar dim1 = 0; dim1 < 2; dim1++) begin for (genvar dim2 = 0; dim2 < 4; dim2++) begin assign internal[dim1][dim2+2] = in[dim1][dim2]; end end for (genvar dim1 = 0; dim1 < 2; dim1++) begin for (genvar dim2 = 0; dim2 < 4; dim2++) begin always_ff @(negedge internal[dim1][dim2+2]) begin $display("%0b", internal[dim1][dim2+2]); end end end endmodule verilator-5.044/test_regress/t/t_wrapper_context.cpp0000644000542200017500000000747115125463617023365 0ustar mahmoudyfreeshell// // DESCRIPTION: Verilator: Verilog Multiple Model Test Module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020-2021 by Andreas Kuster. // SPDX-License-Identifier: CC0-1.0 // #include #include #include #include // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" #include VM_PREFIX_INCLUDE // Check we properly define the version integer #if VERILATOR_VERSION_INTEGER < 4219000 // Added in 4.219 #error "VERILATOR_VERSION_INTEGER not set" #endif double sc_time_stamp() { return 0; } int errors = 0; VerilatedMutex outputMutex; #ifdef T_WRAPPER_CONTEXT #elif defined(T_WRAPPER_CONTEXT_SEQ) VerilatedMutex sequentialMutex; #elif defined(T_WRAPPER_CONTEXT_FST) #else #error "Unexpected test name" #endif void sim(VM_PREFIX* topp) { #ifdef T_WRAPPER_CONTEXT_SEQ // Run each sim sequentially const VerilatedLockGuard seqLock(sequentialMutex); #endif VerilatedContext* contextp = topp->contextp(); // This test created a thread, so need to associate VerilatedContext with it Verilated::threadContextp(contextp); // reset topp->clk = 0; topp->rst = 1; topp->stop = (topp->trace_number == 0); topp->eval(); contextp->timeInc(1); topp->clk = 1; topp->eval(); contextp->timeInc(1); topp->rst = 0; topp->clk = 0; topp->eval(); // simulate until done while (!contextp->gotFinish()) { // increment time contextp->timeInc(1); { const VerilatedLockGuard lock(outputMutex); #ifdef TEST_VERBOSE // std::endl needed to flush output before mutex release std::cout << "{top" << topp->trace_number << ", ctx=" << reinterpret_cast(contextp) << "} [" << contextp->time() << "]" << std::endl; #endif } // toggle clk topp->clk = !topp->clk; // evaluate model topp->eval(); } std::string filename = std::string{VL_STRINGIFY(TEST_OBJ_DIR) "/coverage_"} + topp->name() + ".dat"; contextp->coveragep()->write(filename.c_str()); } int main(int argc, char** argv) { // Create contexts std::unique_ptr context0p{new VerilatedContext}; std::unique_ptr context1p{new VerilatedContext}; // configuration context0p->threads(1); context1p->threads(1); context0p->fatalOnError(false); context1p->fatalOnError(false); context0p->traceEverOn(true); context1p->traceEverOn(true); // error number checks TEST_CHECK_EQ(context0p->errorCount(), 0); TEST_CHECK_EQ(context1p->errorCount(), 0); context0p->errorCount(1); TEST_CHECK_EQ(context0p->errorCount(), 1); context0p->errorCount(0); TEST_CHECK_EQ(context0p->errorCount(), 0); // instantiate verilated design std::unique_ptr top0p{new VM_PREFIX{context0p.get(), "top0"}}; std::unique_ptr top1p{new VM_PREFIX{context1p.get(), "top1"}}; top0p->trace_number = 0; top0p->trace_number = 1; std::cout << "Below '%Error: ... Verilog $stop' is expected as part of the test\n"; // create threads std::thread t0(sim, top0p.get()); std::thread t1(sim, top1p.get()); // wait to finish t0.join(); t1.join(); // check if both finished bool pass = true; if (errors) { std::cout << "Error: comparison errors" << std::endl; pass = false; } else if (top0p->done_o && top1p->done_o) { std::cout << "*-* All Finished *-*" << std::endl; } else { std::cout << "Error: Early termination!" << std::endl; pass = false; } // final model cleanup top0p->final(); top1p->final(); // exit successful return pass ? 0 : 10; } verilator-5.044/test_regress/t/t_flag_deprecated_bad.out0000644000542200017500000000106515125463617024056 0ustar mahmoudyfreeshell%Warning-DEPRECATED: Option --trace-fst-thread is deprecated. Use --trace-fst with --trace-threads > 0. ... For warning description see https://verilator.org/warn/DEPRECATED?v=latest ... Use "/* verilator lint_off DEPRECATED */" and lint_on around source to disable this message. %Warning-DEPRECATED: Option order-clock-delay is deprecated and has no effect. %Warning-DEPRECATED: Option '--clk' is deprecated and has no effect. %Warning-DEPRECATED: Option '--no-clk' is deprecated and has no effect. %Error: Exiting due to verilator-5.044/test_regress/t/t_class_param_extra_bad.py0000755000542200017500000000076615125463617024310 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_flag_main_sc_bad.py0000755000542200017500000000110015125463617023201 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=['--exe --build --main --sc'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_randomize_inline_var_ctl.v0000644000542200017500000000772115125463617024662 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Foo; rand int zero; int two; endclass class Bar extends Foo; rand int one; static int three; function void test; logic[1:0] ok = '0; zero = 100; one = 200; two = 300; three = 400; for (int i = 0; i < 20; i++) begin void'(randomize(one)); if (zero != 100) $stop; if (one != 200) ok[0] = 1; if (two != 300) $stop; if (three != 400) $stop; end if (!ok[0]) $stop; ok = '0; if (zero.rand_mode() != 1) $stop; if (one.rand_mode() != 1) $stop; zero = 500; one = 600; two = 700; three = 800; one.rand_mode(0); for (int i = 0; i < 20; i++) begin void'(randomize(one, two)); if (zero != 500) $stop; if (one != 600) ok[0] = 1; if (two != 700) ok[1] = 1; if (three != 800) $stop; end if (one.rand_mode() != 0) $stop; one.rand_mode(1); if (ok != 'b11) $stop; endfunction endclass class Baz; int four; Bar bar; function new; bar = new; endfunction endclass class Qux; Baz baz; function new; baz = new; endfunction endclass class Boo extends Bar; rand int five; endclass module t; initial begin Boo boo = new; Bar bar = boo; Qux qux = new; logic[2:0] ok = '0; bar.test; bar.zero = 1000; bar.one = 2000; bar.two = 3000; bar.three = 4000; boo.five = 999999; for (int i = 0; i < 20; i++) begin int res = bar.randomize(two); if (boo.five != 999999) $stop; end bar.zero = 1000; bar.one = 2000; bar.two = 3000; bar.three = 4000; boo.five = 999999; for (int i = 0; i < 20; i++) begin int res = bar.randomize(two) with { two > 3000 && two < 4000; }; if (bar.zero != 1000) $stop; if (bar.one != 2000) $stop; if (!(bar.two > 3000 && bar.two < 4000)) $stop; if (bar.three != 4000) $stop; if (boo.five != 999999) $stop; end qux.baz.bar.zero = 5000; qux.baz.bar.one = 6000; qux.baz.bar.two = 7000; qux.baz.bar.three = 8000; qux.baz.four = 9000; for (int i = 0; i < 20; i++) begin void'(qux.randomize(baz)); if (qux.baz.bar.zero != 5000) $stop; if (qux.baz.bar.one != 6000) $stop; if (qux.baz.bar.two != 7000) $stop; if (qux.baz.bar.three != 8000) $stop; if (qux.baz.four != 9000) $stop; end for (int i = 0; i < 20; i++) begin void'(qux.randomize(baz.bar)); if (qux.baz.bar.zero != 5000) ok[0] = 1; if (qux.baz.bar.one != 6000) ok[1] = 1; if (qux.baz.bar.two != 7000) $stop; if (qux.baz.bar.three != 8000) $stop; if (qux.baz.four != 9000) $stop; end if (!ok[0]) $stop; if (!ok[1]) $stop; ok = '0; qux.baz.bar.zero = 10000; qux.baz.bar.one = 20000; for (int i = 0; i < 20; i++) begin void'(qux.randomize(baz.four)); if (qux.baz.bar.zero != 10000) $stop; if (qux.baz.bar.one != 20000) $stop; if (qux.baz.bar.two != 7000) $stop; if (qux.baz.bar.three != 8000) $stop; if (qux.baz.four != 9000) ok[0] = 1; end if (!ok[0]) $stop; ok = '0; qux.baz.four = 30000; for (int i = 0; i < 20; i++) begin void'(qux.randomize(baz.bar, qux.baz.bar.one, baz.four)); if (qux.baz.bar.zero != 10000) ok[0] = 1; if (qux.baz.bar.one != 20000) ok[1] = 1; if (qux.baz.bar.two != 7000) $stop; if (qux.baz.bar.three != 8000) $stop; if (qux.baz.four != 30000) ok[2] = 1; end if (ok != 'b111) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_preproc_def09.v0000644000542200017500000000355115125463617022260 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `undefineall // Definitions as speced // Note there are trailing spaces, which spec doesn't show properly `define D(x,y) initial $display("start", x , y, "end"); '`D( "msg1" , "msg2" )' 'initial $display("start", "msg1" , "msg2" , "end");' '`D( " msg1", )' 'initial $display("start", " msg1" , , "end");' '`D(, "msg2 ")' 'initial $display("start", , "msg2 ", "end");' '`D(,)' 'initial $display("start", , , "end");' '`D( , )' 'initial $display("start", , , "end");' //`D("msg1") // ILLEGAL: only one argument //`D() // ILLEGAL: only one empty argument //`D(,,) // ILLEGAL: more actual than formal arguments // Defaults: `define MACRO1(a=5,b="B",c) $display(a,,b,,c); '`MACRO1 ( , 2, 3 )' '$display(5,,2,,3);' '`MACRO1 ( 1 , , 3 )' '$display(1 ,,"B",,3 );' '`MACRO1 ( , 2, )' '$display(5,,2,,);' //`MACRO1 ( 1 ) // ILLEGAL: b and c omitted, no default for c `define MACRO2(a=5, b, c="C") $display(a,,b,,c); '`MACRO2 (1, , 3)' '$display(5,,,,"C");' '`MACRO2 (, 2, )' '$display(5,,2,,"C");' '`MACRO2 (, 2)' '$display(5,,2,,"C");' `define MACRO3(a=5, b=0, c="C") $display(a,,b,,c); '`MACRO3 ( 1 )' '$display(1 ,,0,,"C");' '`MACRO3 ( )' '$display(5,,0,,"C");' //`MACRO3 // ILLEGAL: parentheses required `define DTOP(a,b) a + b '`DTOP( `DTOP(b,1), `DTOP(42,a) )' 'b + 1 + 42 + a' // Local tests `define MACROQUOTE(a="==)",b="((((",c=() ) 'a b c' `MACROQUOTE(); '"==)" "((((" () '; // Also check our line counting doesn't go bad `define MACROPAREN(a=(6), b=(eq=al), c) 'a b c' `MACROPAREN( ,, ZOT) HERE-`__LINE__ - Line71 //====================================================================== verilator-5.044/test_regress/t/t_fuzz_eof_bad.v0000644000542200017500000000006615125463617022252 0ustar mahmoudyfreeshellmodule a; initial $lay(*Hello!=n"); endmodule verilator-5.044/test_regress/t/t_process_bad.out0000644000542200017500000000105415125463617022441 0ustar mahmoudyfreeshell%Error: t/t_process_bad.v:13:13: Class method 'bad_method' not found in class 'process' : ... note: In instance 't' 13 | if (p.bad_method() != 0) $stop; | ^~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_process_bad.v:15:9: Class method 'bad_method_2' not found in class 'process' : ... note: In instance 't' 15 | p.bad_method_2(); | ^~~~~~~~~~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_math_mul.py0000755000542200017500000000073415125463617021613 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_var_dotted2.v0000644000542200017500000000633415125463617022036 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifdef USE_INLINE `define INLINE_MODULE /*verilator inline_module*/ `else `define INLINE_MODULE /*verilator public_module*/ `endif module t; `define DRAM1(bank) mem.mem_bank[bank].dccm.dccm_bank.ram_core `define DRAM2(bank) mem.mem_bank2[bank].dccm.dccm_bank.ram_core `define DRAM3(bank) mem.mem_bank3[bank].dccm.dccm_bank.ram_core `define DRAM4(bank) mem.sub4.mem_bank4[bank].dccm.dccm_bank.ram_core initial begin `DRAM1(0)[3] = 130; `DRAM1(1)[3] = 131; `DRAM2(0)[3] = 230; `DRAM2(1)[3] = 231; `DRAM3(0)[3] = 330; `DRAM3(1)[3] = 331; `DRAM4(0)[3] = 430; `DRAM4(1)[3] = 431; if (`DRAM1(0)[3] !== 130) $stop; if (`DRAM1(1)[3] !== 131) $stop; if (`DRAM2(0)[3] !== 230) $stop; if (`DRAM2(1)[3] !== 231) $stop; if (`DRAM3(0)[3] !== 330) $stop; if (`DRAM3(1)[3] !== 331) $stop; if (`DRAM4(0)[3] !== 430) $stop; if (`DRAM4(1)[3] !== 431) $stop; $write("*-* All Finished *-*\n"); $finish; end eh2_lsu_dccm_mem mem (/*AUTOINST*/); endmodule module eh2_lsu_dccm_mem #( DCCM_INDEX_DEPTH = 8192, DCCM_NUM_BANKS = 2 )( ); `INLINE_MODULE // 8 Banks, 16KB each (2048 x 72) for (genvar i=0; i= SIZE) begin $stop; end end end end endgenerate generate for (g = 0; g < `MAX_SIZE; g = g + 1) begin if (!((g >= SIZE) || ~MASK[g])) begin always @(posedge clk) begin `ifdef TEST_VERBOSE $write ("Logical OR generate if MASK [%1d] = %d\n", g, MASK[g]); `endif if (g >= SIZE) begin $stop; end end end end endgenerate generate for (g = 0; g < `MAX_SIZE; g = g + 1) begin if (!((g < SIZE) -> ~MASK[g])) begin always @(posedge clk) begin `ifdef TEST_VERBOSE $write ("Logical infer generate if MASK [%1d] = %d\n", g, MASK[g]); `endif if (g >= SIZE) begin $stop; end end end end endgenerate generate for (g = 0; g < `MAX_SIZE; g = g + 1) begin if ( g < SIZE ? MASK[g] : 1'b0) begin always @(posedge clk) begin `ifdef TEST_VERBOSE $write ("Conditional generate if MASK [%1d] = %d\n", g, MASK[g]); `endif if (g >= SIZE) begin $stop; end end end end endgenerate // The other way round generate for (g = 0; g < `MAX_SIZE; g = g + 1) begin if ( g >= SIZE ? 1'b0 : MASK[g]) begin always @(posedge clk) begin `ifdef TEST_VERBOSE $write ("Conditional generate if MASK [%1d] = %d\n", g, MASK[g]); `endif if (g >= SIZE) begin $stop; end end end end endgenerate endmodule verilator-5.044/test_regress/t/t_clocking_bad5.v0000644000542200017500000000122015125463617022272 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; sub sub(.*); // Bad - no global clock always @ ($global_clock) $display; endmodule module sub(/*AUTOARG*/ // Inputs clk ); input clk; global clocking ck @(posedge clk); endclocking // Bad - global duplicate global clocking ogck @(posedge clk); endclocking // Bad - name duplicate global clocking ck @(posedge clk); endclocking endmodule verilator-5.044/test_regress/t/t_func_void.py0000755000542200017500000000073415125463617021761 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_forceable_net_trace.vcd.out0000644000542200017500000000450415125463617024701 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 # clk $end $var wire 1 $ rst $end $var wire 32 % cyc [31:0] $end $scope module t $end $var wire 1 # clk $end $var wire 1 $ rst $end $var wire 32 % cyc [31:0] $end $var wire 1 & net_1 $end $var wire 8 ' net_8 [7:0] $end $var wire 1 & obs_1 $end $var wire 8 ' obs_8 [7:0] $end $upscope $end $upscope $end $enddefinitions $end #0 0# 1$ b00000000000000000000000000000000 % 1& b11111111 ' #5 1# 0$ #10 0# #15 1# b00000000000000000000000000000001 % 0& #20 0# #25 1# b00000000000000000000000000000010 % 1& b11111110 ' #30 0# #35 1# b00000000000000000000000000000011 % 0& #40 0# #45 1# b00000000000000000000000000000100 % b01011111 ' #50 0# #55 1# b00000000000000000000000000000101 % 1& #60 0# #65 1# b00000000000000000000000000000110 % b11110101 ' #70 0# #75 1# b00000000000000000000000000000111 % #80 0# #85 1# b00000000000000000000000000001000 % #90 0# #95 1# b00000000000000000000000000001001 % 0& b11111011 ' #100 0# #105 1# b00000000000000000000000000001010 % 1& b01011010 ' #110 0# #115 1# b00000000000000000000000000001011 % #120 0# #125 1# b00000000000000000000000000001100 % 0& b10100101 ' #130 0# #135 1# b00000000000000000000000000001101 % #140 0# #145 1# b00000000000000000000000000001110 % 1& b11111000 ' #150 0# #155 1# b00000000000000000000000000001111 % 0& #160 0# #165 1# b00000000000000000000000000010000 % 1& b11110111 ' #170 0# #175 1# b00000000000000000000000000010001 % 0& #180 0# #185 1# b00000000000000000000000000010010 % 1& b11110110 ' #190 0# #195 1# b00000000000000000000000000010011 % 0& #200 0# #205 1# b00000000000000000000000000010100 % 1& b11110101 ' #210 0# #215 1# b00000000000000000000000000010101 % 0& #220 0# #225 1# b00000000000000000000000000010110 % 1& b11110100 ' #230 0# #235 1# b00000000000000000000000000010111 % 0& #240 0# #245 1# b00000000000000000000000000011000 % 1& b11110011 ' #250 0# #255 1# b00000000000000000000000000011001 % 0& #260 0# #265 1# b00000000000000000000000000011010 % 1& b11110010 ' #270 0# #275 1# b00000000000000000000000000011011 % 0& #280 0# #285 1# b00000000000000000000000000011100 % 1& b11110001 ' #290 0# #295 1# b00000000000000000000000000011101 % 0& #300 0# #305 1# b00000000000000000000000000011110 % 1& b11110000 ' #310 0# #315 1# b00000000000000000000000000011111 % 0& verilator-5.044/test_regress/t/t_fork_dynscope_interface.py0000755000542200017500000000100515125463617024662 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary --trace-fst']) test.execute() test.passes() verilator-5.044/test_regress/t/t_trace_primitive_fst_sc.py0000755000542200017500000000114115125463617024525 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_primitive.v" if not test.have_sc: test.skip("No SystemC installed") test.compile(v_flags2=["--sc --trace-fst"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_interface_down_inlab.py0000755000542200017500000000112215125463617024131 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_down.v" test.compile(v_flags2=['+define+INLINE_A +define+INLINE_B'], verilator_flags2=['-trace']) test.execute() test.passes() verilator-5.044/test_regress/t/t_package_export_bad2.v0000644000542200017500000000054315125463617023501 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package Pkg1; endpackage package Pkg10; // verilator lint_off PKGNODECL export Pkg1b::*; // BAD - typo in package name endpackage module t; endmodule verilator-5.044/test_regress/t/t_delay_incr_timing.py0000755000542200017500000000105515125463617023462 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_delay_incr.v" test.compile(verilator_flags2=['--binary -Wno-ZERODLY']) test.execute() test.passes() verilator-5.044/test_regress/t/t_dfg_bin_to_one_hot.py0000755000542200017500000000115015125463617023603 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--stats"]) test.execute() test.file_grep(test.stats, r'Optimizations, DFG pre inline BinToOneHot, decoders created\s+(\d+)', 4) test.passes() verilator-5.044/test_regress/t/t_timing_split.py0000755000542200017500000000177415125463617022514 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') def check_splits(): got1 = False gotSyms1 = False for filename in test.glob_some(test.obj_dir + "/*.cpp"): if re.search(r'Syms__.*__1', filename): gotSyms1 = True elif re.search(r'__1', filename): got1 = True if not got1: test.error("No __1 split file found") if not gotSyms1: test.error("No Syms__*__1 split file found") test.compile(timing_loop=True, verilator_flags2=["--timing --output-split-cfuncs 1 -CFLAGS -Werror"]) test.execute() if test.have_coroutines: check_splits() test.passes() verilator-5.044/test_regress/t/t_var_pins_sc_uint_bool.py0000755000542200017500000000423015125463617024360 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" test.compile(verilator_flags2=["-sc --pins-sc-uint-bool --trace-vcd --exe", test.pli_filename], make_main=False) def hgrep(re): test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) hgrep(r'sc_core::sc_in\s>\s+&i1;') hgrep(r'sc_core::sc_in\s+&i8;') hgrep(r'sc_core::sc_in\s+&i16;') hgrep(r'sc_core::sc_in\s+&i32;') hgrep(r'sc_core::sc_in\s+&i64;') hgrep(r'sc_core::sc_in\s>\s+&i65;') hgrep(r'sc_core::sc_in\s>\s+&i128;') hgrep(r'sc_core::sc_in\s>\s+&i513;') hgrep(r'sc_core::sc_out\s>\s+&o1;') hgrep(r'sc_core::sc_out\s+&o8;') hgrep(r'sc_core::sc_out\s+&o16;') hgrep(r'sc_core::sc_out\s+&o32;') hgrep(r'sc_core::sc_out\s+&o64;') hgrep(r'sc_core::sc_out\s>\s+&o65;') hgrep(r'sc_core::sc_out\s>\s+&o128;') hgrep(r'sc_core::sc_out\s>\s+&o513;') # sc_biguint pragma overrides `--pins-sc-uint-bool` flag hgrep(r'sc_core::sc_in\s>\s+&ibu1;') hgrep(r'sc_core::sc_in\s>\s+&ibu8;') hgrep(r'sc_core::sc_in\s>\s+&ibu16;') hgrep(r'sc_core::sc_in\s>\s+&ibu64;') hgrep(r'sc_core::sc_in\s>\s+&ibu512;') hgrep(r'sc_core::sc_out\s>\s+&obu1;') hgrep(r'sc_core::sc_out\s>\s+&obu8;') hgrep(r'sc_core::sc_out\s>\s+&obu16;') hgrep(r'sc_core::sc_out\s>\s+&obu64;') hgrep(r'sc_core::sc_out\s>\s+&obu512;') test.execute() test.passes() verilator-5.044/test_regress/t/t_trace_dumpvars_dyn_fst_0.out0000644000542200017500000001236115125463617025144 0ustar mahmoudyfreeshell$date Sat Jul 19 22:57:16 2025 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end $var int 32 " cyc [31:0] $end $scope module sub1a $end $var parameter 32 # ADD [31:0] $end $var wire 32 " cyc [31:0] $end $var int 32 $ value [31:0] $end $scope module sub2a $end $var parameter 32 % ADD [31:0] $end $var wire 32 " cyc [31:0] $end $var int 32 & value [31:0] $end $upscope $end $scope module sub2b $end $var parameter 32 ' ADD [31:0] $end $var wire 32 " cyc [31:0] $end $var int 32 ( value [31:0] $end $upscope $end $scope module sub2c $end $var parameter 32 ) ADD [31:0] $end $var wire 32 " cyc [31:0] $end $var int 32 * value [31:0] $end $upscope $end $upscope $end $scope module sub1b $end $var parameter 32 + ADD [31:0] $end $var wire 32 " cyc [31:0] $end $var int 32 , value [31:0] $end $scope module sub2a $end $var parameter 32 - ADD [31:0] $end $var wire 32 " cyc [31:0] $end $var int 32 . value [31:0] $end $upscope $end $scope module sub2b $end $var parameter 32 / ADD [31:0] $end $var wire 32 " cyc [31:0] $end $var int 32 0 value [31:0] $end $upscope $end $scope module sub2c $end $var parameter 32 1 ADD [31:0] $end $var wire 32 " cyc [31:0] $end $var int 32 2 value [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b00000000000000000000000000010111 2 b00000000000000000000000000010111 1 b00000000000000000000000000010110 0 b00000000000000000000000000010110 / b00000000000000000000000000010101 . b00000000000000000000000000010101 - b00000000000000000000000000010100 , b00000000000000000000000000010100 + b00000000000000000000000000001101 * b00000000000000000000000000001101 ) b00000000000000000000000000001100 ( b00000000000000000000000000001100 ' b00000000000000000000000000001011 & b00000000000000000000000000001011 % b00000000000000000000000000001010 $ b00000000000000000000000000001010 # b00000000000000000000000000000000 " 0! $end #1 1! b00000000000000000000000000000001 " b00000000000000000000000000001011 $ b00000000000000000000000000001100 & b00000000000000000000000000001101 ( b00000000000000000000000000001110 * b00000000000000000000000000010101 , b00000000000000000000000000010110 . b00000000000000000000000000010111 0 b00000000000000000000000000011000 2 #2 0! #3 1! b00000000000000000000000000011001 2 b00000000000000000000000000011000 0 b00000000000000000000000000010111 . b00000000000000000000000000010110 , b00000000000000000000000000001111 * b00000000000000000000000000001110 ( b00000000000000000000000000001101 & b00000000000000000000000000001100 $ b00000000000000000000000000000010 " #4 0! #5 1! b00000000000000000000000000000011 " b00000000000000000000000000001101 $ b00000000000000000000000000001110 & b00000000000000000000000000001111 ( b00000000000000000000000000010000 * b00000000000000000000000000010111 , b00000000000000000000000000011000 . b00000000000000000000000000011001 0 b00000000000000000000000000011010 2 #6 0! #7 1! b00000000000000000000000000011011 2 b00000000000000000000000000011010 0 b00000000000000000000000000011001 . b00000000000000000000000000011000 , b00000000000000000000000000010001 * b00000000000000000000000000010000 ( b00000000000000000000000000001111 & b00000000000000000000000000001110 $ b00000000000000000000000000000100 " #8 0! #9 1! b00000000000000000000000000000101 " b00000000000000000000000000001111 $ b00000000000000000000000000010000 & b00000000000000000000000000010001 ( b00000000000000000000000000010010 * b00000000000000000000000000011001 , b00000000000000000000000000011010 . b00000000000000000000000000011011 0 b00000000000000000000000000011100 2 #10 0! #11 1! b00000000000000000000000000011101 2 b00000000000000000000000000011100 0 b00000000000000000000000000011011 . b00000000000000000000000000011010 , b00000000000000000000000000010011 * b00000000000000000000000000010010 ( b00000000000000000000000000010001 & b00000000000000000000000000010000 $ b00000000000000000000000000000110 " #12 0! #13 1! b00000000000000000000000000000111 " b00000000000000000000000000010001 $ b00000000000000000000000000010010 & b00000000000000000000000000010011 ( b00000000000000000000000000010100 * b00000000000000000000000000011011 , b00000000000000000000000000011100 . b00000000000000000000000000011101 0 b00000000000000000000000000011110 2 #14 0! #15 1! b00000000000000000000000000011111 2 b00000000000000000000000000011110 0 b00000000000000000000000000011101 . b00000000000000000000000000011100 , b00000000000000000000000000010101 * b00000000000000000000000000010100 ( b00000000000000000000000000010011 & b00000000000000000000000000010010 $ b00000000000000000000000000001000 " #16 0! #17 1! b00000000000000000000000000001001 " b00000000000000000000000000010011 $ b00000000000000000000000000010100 & b00000000000000000000000000010101 ( b00000000000000000000000000010110 * b00000000000000000000000000011101 , b00000000000000000000000000011110 . b00000000000000000000000000011111 0 b00000000000000000000000000100000 2 #18 0! #19 1! b00000000000000000000000000100001 2 b00000000000000000000000000100000 0 b00000000000000000000000000011111 . b00000000000000000000000000011110 , b00000000000000000000000000010111 * b00000000000000000000000000010110 ( b00000000000000000000000000010101 & b00000000000000000000000000010100 $ b00000000000000000000000000001010 " #20 0! verilator-5.044/test_regress/t/t_gantt_two.cpp0000644000542200017500000000227715125463617022146 0ustar mahmoudyfreeshell// // DESCRIPTION: Verilator: Verilog Multiple Model Test Module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 // #include "verilated.h" #include VM_PREFIX_INCLUDE #include int main(int argc, char** argv) { srand48(5); const std::unique_ptr contextp{new VerilatedContext}; // VL_USE_THREADS define is set in t_gantt_two.py contextp->threads(TEST_USE_THREADS); contextp->debug(0); contextp->commandArgs(argc, argv); std::unique_ptr topap{new VM_PREFIX{contextp.get(), "topa"}}; std::unique_ptr topbp{new VM_PREFIX{contextp.get(), "topb"}}; topap->clk = false; topap->eval(); topbp->clk = false; topbp->eval(); contextp->timeInc(10); while ((contextp->time() < 1100) && !contextp->gotFinish()) { topap->clk = !topap->clk; topap->eval(); topbp->clk = !topbp->clk; topbp->eval(); contextp->timeInc(5); } if (!contextp->gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } return 0; } verilator-5.044/test_regress/t/t_case_deep.v0000644000542200017500000004777115125463617021543 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [33:0] in = crc[33:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] code; // From test of Test.v wire [4:0] len; // From test of Test.v wire next; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .next (next), .code (code[31:0]), .len (len[4:0]), // Inputs .clk (clk), .in (in[33:0])); // Aggregate outputs into a single result vector wire [63:0] result = {26'h0, next, len, code}; // What checksum will we end up with `define EXPECTED_SUM 64'h5537fa30d49bf865 // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs next, code, len, // Inputs clk, in ); input clk; input [33:0] in; output next; output [31:0] code; output [4:0] len; /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) reg [31:0] code; reg [4:0] len; reg next; // End of automatics /* #!/usr/bin/env perl use warnings; srand(5); my @used; pat: for (my $pat=0; 1; ) { last if $pat > 196; my $len = int($pat / (6 + $pat/50)) + 4; $len=20 if $len>20; my ($try, $val, $mask); try: for ($try=0; ; $try++) { next pat if $try>50; $val = 0; for (my $bit=23; $bit>(23-$len); $bit--) { my $b = int(rand()*2); $val |= (1<<$bit) if $b; } $mask = (1<<(23-$len+1))-1; for (my $testval = $val; $testval <= ($val + $mask); $testval ++) { next try if $used[$testval]; } last; } my $bits = ""; my $val2 = 0; for (my $bit=23; $bit>(23-$len); $bit--) { my $b = ($val & (1<<$bit)); $bits .= $b?'1':'0'; } for (my $testval = $val; $testval <= ($val + $mask); $testval++) { $used[$testval]= 1; #printf "U%08x\n", $testval; } if ($try<90) { printf +(" 24'b%s: {next, len, code} = {in[%02d], 5'd%02d, 32'd%03d};\n" ,$bits.("?"x(24-$len)), 31-$len, $len, $pat); $pat++; } } */ always @* begin next = 1'b0; code = 32'd0; len = 5'b11111; casez (in[31:8]) 24'b1010????????????????????: {next, len, code} = {in[27], 5'd04, 32'd000}; 24'b1100????????????????????: {next, len, code} = {in[27], 5'd04, 32'd001}; 24'b0110????????????????????: {next, len, code} = {in[27], 5'd04, 32'd002}; 24'b1001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd003}; 24'b1101????????????????????: {next, len, code} = {in[27], 5'd04, 32'd004}; 24'b0011????????????????????: {next, len, code} = {in[27], 5'd04, 32'd005}; 24'b0001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd006}; 24'b10001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd007}; 24'b01110???????????????????: {next, len, code} = {in[26], 5'd05, 32'd008}; 24'b01000???????????????????: {next, len, code} = {in[26], 5'd05, 32'd009}; 24'b00001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd010}; 24'b11100???????????????????: {next, len, code} = {in[26], 5'd05, 32'd011}; 24'b01011???????????????????: {next, len, code} = {in[26], 5'd05, 32'd012}; 24'b100001??????????????????: {next, len, code} = {in[25], 5'd06, 32'd013}; 24'b111110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd014}; 24'b010010??????????????????: {next, len, code} = {in[25], 5'd06, 32'd015}; 24'b001011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd016}; 24'b101110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd017}; 24'b111011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd018}; 24'b0111101?????????????????: {next, len, code} = {in[24], 5'd07, 32'd020}; 24'b0010100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd021}; 24'b0111111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd022}; 24'b1011010?????????????????: {next, len, code} = {in[24], 5'd07, 32'd023}; 24'b1000000?????????????????: {next, len, code} = {in[24], 5'd07, 32'd024}; 24'b1011111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd025}; 24'b1110100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd026}; 24'b01111100????????????????: {next, len, code} = {in[23], 5'd08, 32'd027}; 24'b00000110????????????????: {next, len, code} = {in[23], 5'd08, 32'd028}; 24'b00000101????????????????: {next, len, code} = {in[23], 5'd08, 32'd029}; 24'b01001100????????????????: {next, len, code} = {in[23], 5'd08, 32'd030}; 24'b10110110????????????????: {next, len, code} = {in[23], 5'd08, 32'd031}; 24'b00100110????????????????: {next, len, code} = {in[23], 5'd08, 32'd032}; 24'b11110010????????????????: {next, len, code} = {in[23], 5'd08, 32'd033}; 24'b010011101???????????????: {next, len, code} = {in[22], 5'd09, 32'd034}; 24'b001000000???????????????: {next, len, code} = {in[22], 5'd09, 32'd035}; 24'b010101111???????????????: {next, len, code} = {in[22], 5'd09, 32'd036}; 24'b010101010???????????????: {next, len, code} = {in[22], 5'd09, 32'd037}; 24'b010011011???????????????: {next, len, code} = {in[22], 5'd09, 32'd038}; 24'b010100011???????????????: {next, len, code} = {in[22], 5'd09, 32'd039}; 24'b010101000???????????????: {next, len, code} = {in[22], 5'd09, 32'd040}; 24'b1111010101??????????????: {next, len, code} = {in[21], 5'd10, 32'd041}; 24'b0010001000??????????????: {next, len, code} = {in[21], 5'd10, 32'd042}; 24'b0101001101??????????????: {next, len, code} = {in[21], 5'd10, 32'd043}; 24'b0010010100??????????????: {next, len, code} = {in[21], 5'd10, 32'd044}; 24'b1011001110??????????????: {next, len, code} = {in[21], 5'd10, 32'd045}; 24'b1111000011??????????????: {next, len, code} = {in[21], 5'd10, 32'd046}; 24'b0101000000??????????????: {next, len, code} = {in[21], 5'd10, 32'd047}; 24'b1111110000??????????????: {next, len, code} = {in[21], 5'd10, 32'd048}; 24'b10110111010?????????????: {next, len, code} = {in[20], 5'd11, 32'd049}; 24'b11110000011?????????????: {next, len, code} = {in[20], 5'd11, 32'd050}; 24'b01001111011?????????????: {next, len, code} = {in[20], 5'd11, 32'd051}; 24'b00101011011?????????????: {next, len, code} = {in[20], 5'd11, 32'd052}; 24'b01010010100?????????????: {next, len, code} = {in[20], 5'd11, 32'd053}; 24'b11110111100?????????????: {next, len, code} = {in[20], 5'd11, 32'd054}; 24'b00100111001?????????????: {next, len, code} = {in[20], 5'd11, 32'd055}; 24'b10110001010?????????????: {next, len, code} = {in[20], 5'd11, 32'd056}; 24'b10000010000?????????????: {next, len, code} = {in[20], 5'd11, 32'd057}; 24'b111111101100????????????: {next, len, code} = {in[19], 5'd12, 32'd058}; 24'b100000111110????????????: {next, len, code} = {in[19], 5'd12, 32'd059}; 24'b100000110010????????????: {next, len, code} = {in[19], 5'd12, 32'd060}; 24'b100000111001????????????: {next, len, code} = {in[19], 5'd12, 32'd061}; 24'b010100101111????????????: {next, len, code} = {in[19], 5'd12, 32'd062}; 24'b001000001100????????????: {next, len, code} = {in[19], 5'd12, 32'd063}; 24'b000001111111????????????: {next, len, code} = {in[19], 5'd12, 32'd064}; 24'b011111010100????????????: {next, len, code} = {in[19], 5'd12, 32'd065}; 24'b1110101111101???????????: {next, len, code} = {in[18], 5'd13, 32'd066}; 24'b0100110101110???????????: {next, len, code} = {in[18], 5'd13, 32'd067}; 24'b1111111011011???????????: {next, len, code} = {in[18], 5'd13, 32'd068}; 24'b0101011011001???????????: {next, len, code} = {in[18], 5'd13, 32'd069}; 24'b0010000101100???????????: {next, len, code} = {in[18], 5'd13, 32'd070}; 24'b1111111101101???????????: {next, len, code} = {in[18], 5'd13, 32'd071}; 24'b1011110010110???????????: {next, len, code} = {in[18], 5'd13, 32'd072}; 24'b0101010111010???????????: {next, len, code} = {in[18], 5'd13, 32'd073}; 24'b1111011010010???????????: {next, len, code} = {in[18], 5'd13, 32'd074}; 24'b01010100100011??????????: {next, len, code} = {in[17], 5'd14, 32'd075}; 24'b10110000110010??????????: {next, len, code} = {in[17], 5'd14, 32'd076}; 24'b10111101001111??????????: {next, len, code} = {in[17], 5'd14, 32'd077}; 24'b10110000010101??????????: {next, len, code} = {in[17], 5'd14, 32'd078}; 24'b00101011001111??????????: {next, len, code} = {in[17], 5'd14, 32'd079}; 24'b00100000101100??????????: {next, len, code} = {in[17], 5'd14, 32'd080}; 24'b11111110010111??????????: {next, len, code} = {in[17], 5'd14, 32'd081}; 24'b10110010100000??????????: {next, len, code} = {in[17], 5'd14, 32'd082}; 24'b11101011101000??????????: {next, len, code} = {in[17], 5'd14, 32'd083}; 24'b01010000011111??????????: {next, len, code} = {in[17], 5'd14, 32'd084}; 24'b101111011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd085}; 24'b101111010001100?????????: {next, len, code} = {in[16], 5'd15, 32'd086}; 24'b100000111100111?????????: {next, len, code} = {in[16], 5'd15, 32'd087}; 24'b001010101011000?????????: {next, len, code} = {in[16], 5'd15, 32'd088}; 24'b111111100100001?????????: {next, len, code} = {in[16], 5'd15, 32'd089}; 24'b001001011000010?????????: {next, len, code} = {in[16], 5'd15, 32'd090}; 24'b011110011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd091}; 24'b111111111111010?????????: {next, len, code} = {in[16], 5'd15, 32'd092}; 24'b101111001010011?????????: {next, len, code} = {in[16], 5'd15, 32'd093}; 24'b100000110000111?????????: {next, len, code} = {in[16], 5'd15, 32'd094}; 24'b0010010000000101????????: {next, len, code} = {in[15], 5'd16, 32'd095}; 24'b0010010010101001????????: {next, len, code} = {in[15], 5'd16, 32'd096}; 24'b1111011010110010????????: {next, len, code} = {in[15], 5'd16, 32'd097}; 24'b0010010001100100????????: {next, len, code} = {in[15], 5'd16, 32'd098}; 24'b0101011101110100????????: {next, len, code} = {in[15], 5'd16, 32'd099}; 24'b0101011010001111????????: {next, len, code} = {in[15], 5'd16, 32'd100}; 24'b0010000110011111????????: {next, len, code} = {in[15], 5'd16, 32'd101}; 24'b0101010010000101????????: {next, len, code} = {in[15], 5'd16, 32'd102}; 24'b1110101011000000????????: {next, len, code} = {in[15], 5'd16, 32'd103}; 24'b1111000000110010????????: {next, len, code} = {in[15], 5'd16, 32'd104}; 24'b0111100010001101????????: {next, len, code} = {in[15], 5'd16, 32'd105}; 24'b00100010110001100???????: {next, len, code} = {in[14], 5'd17, 32'd106}; 24'b00100010101101010???????: {next, len, code} = {in[14], 5'd17, 32'd107}; 24'b11111110111100000???????: {next, len, code} = {in[14], 5'd17, 32'd108}; 24'b00100000111010000???????: {next, len, code} = {in[14], 5'd17, 32'd109}; 24'b00100111011101001???????: {next, len, code} = {in[14], 5'd17, 32'd110}; 24'b11111110111000011???????: {next, len, code} = {in[14], 5'd17, 32'd111}; 24'b11110001101000100???????: {next, len, code} = {in[14], 5'd17, 32'd112}; 24'b11101011101011101???????: {next, len, code} = {in[14], 5'd17, 32'd113}; 24'b01010000100101011???????: {next, len, code} = {in[14], 5'd17, 32'd114}; 24'b00100100110011001???????: {next, len, code} = {in[14], 5'd17, 32'd115}; 24'b01001110010101000???????: {next, len, code} = {in[14], 5'd17, 32'd116}; 24'b010011110101001000??????: {next, len, code} = {in[13], 5'd18, 32'd117}; 24'b111010101110010010??????: {next, len, code} = {in[13], 5'd18, 32'd118}; 24'b001001001001111000??????: {next, len, code} = {in[13], 5'd18, 32'd119}; 24'b101111000110111101??????: {next, len, code} = {in[13], 5'd18, 32'd120}; 24'b101101111010101001??????: {next, len, code} = {in[13], 5'd18, 32'd121}; 24'b111101110010111110??????: {next, len, code} = {in[13], 5'd18, 32'd122}; 24'b010100100011010000??????: {next, len, code} = {in[13], 5'd18, 32'd123}; 24'b001001001111011001??????: {next, len, code} = {in[13], 5'd18, 32'd124}; 24'b010100110010001001??????: {next, len, code} = {in[13], 5'd18, 32'd125}; 24'b111010110000111000??????: {next, len, code} = {in[13], 5'd18, 32'd126}; 24'b111010110011000101??????: {next, len, code} = {in[13], 5'd18, 32'd127}; 24'b010100001000111001??????: {next, len, code} = {in[13], 5'd18, 32'd128}; 24'b1000001011000110100?????: {next, len, code} = {in[12], 5'd19, 32'd129}; 24'b0010010111001110110?????: {next, len, code} = {in[12], 5'd19, 32'd130}; 24'b0101011001000001101?????: {next, len, code} = {in[12], 5'd19, 32'd131}; 24'b0101000010010101011?????: {next, len, code} = {in[12], 5'd19, 32'd132}; 24'b1111011111101001101?????: {next, len, code} = {in[12], 5'd19, 32'd133}; 24'b1011001000101010110?????: {next, len, code} = {in[12], 5'd19, 32'd134}; 24'b1011000001000100001?????: {next, len, code} = {in[12], 5'd19, 32'd135}; 24'b1110101100010011001?????: {next, len, code} = {in[12], 5'd19, 32'd136}; 24'b0010010111010111110?????: {next, len, code} = {in[12], 5'd19, 32'd137}; 24'b0010010001100111100?????: {next, len, code} = {in[12], 5'd19, 32'd138}; 24'b1011001011100000101?????: {next, len, code} = {in[12], 5'd19, 32'd139}; 24'b1011000100010100101?????: {next, len, code} = {in[12], 5'd19, 32'd140}; 24'b1111111001000111011?????: {next, len, code} = {in[12], 5'd19, 32'd141}; 24'b00100010111101101101????: {next, len, code} = {in[11], 5'd20, 32'd142}; 24'b10000010101010101101????: {next, len, code} = {in[11], 5'd20, 32'd143}; 24'b10110010100101001101????: {next, len, code} = {in[11], 5'd20, 32'd144}; 24'b01010110111100010000????: {next, len, code} = {in[11], 5'd20, 32'd145}; 24'b10110111110011001001????: {next, len, code} = {in[11], 5'd20, 32'd146}; 24'b11111101101100100101????: {next, len, code} = {in[11], 5'd20, 32'd147}; 24'b10110000010100100001????: {next, len, code} = {in[11], 5'd20, 32'd148}; 24'b10110010011010110110????: {next, len, code} = {in[11], 5'd20, 32'd149}; 24'b01111001010000011000????: {next, len, code} = {in[11], 5'd20, 32'd150}; 24'b11110110001011011011????: {next, len, code} = {in[11], 5'd20, 32'd151}; 24'b01010000100100001011????: {next, len, code} = {in[11], 5'd20, 32'd152}; 24'b10110001100101110111????: {next, len, code} = {in[11], 5'd20, 32'd153}; 24'b10111100110111101000????: {next, len, code} = {in[11], 5'd20, 32'd154}; 24'b01010001010111010000????: {next, len, code} = {in[11], 5'd20, 32'd155}; 24'b01010100111110001110????: {next, len, code} = {in[11], 5'd20, 32'd156}; 24'b11111110011001100111????: {next, len, code} = {in[11], 5'd20, 32'd157}; 24'b11110111111101010001????: {next, len, code} = {in[11], 5'd20, 32'd158}; 24'b10110000010111100000????: {next, len, code} = {in[11], 5'd20, 32'd159}; 24'b01001111100001000101????: {next, len, code} = {in[11], 5'd20, 32'd160}; 24'b01010010000111010110????: {next, len, code} = {in[11], 5'd20, 32'd161}; 24'b11101010101011101111????: {next, len, code} = {in[11], 5'd20, 32'd162}; 24'b11111110010011100011????: {next, len, code} = {in[11], 5'd20, 32'd163}; 24'b01010111001111101111????: {next, len, code} = {in[11], 5'd20, 32'd164}; 24'b10110001111111111101????: {next, len, code} = {in[11], 5'd20, 32'd165}; 24'b10110001001100110000????: {next, len, code} = {in[11], 5'd20, 32'd166}; 24'b11110100011000111101????: {next, len, code} = {in[11], 5'd20, 32'd167}; 24'b00101011101110100011????: {next, len, code} = {in[11], 5'd20, 32'd168}; 24'b01010000011011111110????: {next, len, code} = {in[11], 5'd20, 32'd169}; 24'b00000111000010000010????: {next, len, code} = {in[11], 5'd20, 32'd170}; 24'b00101010000011001000????: {next, len, code} = {in[11], 5'd20, 32'd171}; 24'b01001110010100101110????: {next, len, code} = {in[11], 5'd20, 32'd172}; 24'b11110000000010000000????: {next, len, code} = {in[11], 5'd20, 32'd173}; 24'b01001101011001111001????: {next, len, code} = {in[11], 5'd20, 32'd174}; 24'b11110111000111010101????: {next, len, code} = {in[11], 5'd20, 32'd175}; 24'b01111001101001110110????: {next, len, code} = {in[11], 5'd20, 32'd176}; 24'b11110000101011101111????: {next, len, code} = {in[11], 5'd20, 32'd177}; 24'b00100100100110101010????: {next, len, code} = {in[11], 5'd20, 32'd178}; 24'b11110001011011000011????: {next, len, code} = {in[11], 5'd20, 32'd179}; 24'b01010111001000110011????: {next, len, code} = {in[11], 5'd20, 32'd180}; 24'b01111000000100010101????: {next, len, code} = {in[11], 5'd20, 32'd181}; 24'b00100101101011001101????: {next, len, code} = {in[11], 5'd20, 32'd182}; 24'b10110010110000111001????: {next, len, code} = {in[11], 5'd20, 32'd183}; 24'b10110000101010000011????: {next, len, code} = {in[11], 5'd20, 32'd184}; 24'b00100100111110001101????: {next, len, code} = {in[11], 5'd20, 32'd185}; 24'b01111001101001101011????: {next, len, code} = {in[11], 5'd20, 32'd186}; 24'b01010001000000010001????: {next, len, code} = {in[11], 5'd20, 32'd187}; 24'b11110101111111101110????: {next, len, code} = {in[11], 5'd20, 32'd188}; 24'b10000010111110110011????: {next, len, code} = {in[11], 5'd20, 32'd189}; 24'b00000100011110100111????: {next, len, code} = {in[11], 5'd20, 32'd190}; 24'b11111101001111101100????: {next, len, code} = {in[11], 5'd20, 32'd191}; 24'b00101011100011110000????: {next, len, code} = {in[11], 5'd20, 32'd192}; 24'b00100100111001011001????: {next, len, code} = {in[11], 5'd20, 32'd193}; 24'b10000010101000000100????: {next, len, code} = {in[11], 5'd20, 32'd194}; 24'b11110001001000111100????: {next, len, code} = {in[11], 5'd20, 32'd195}; 24'b10111100011010011001????: {next, len, code} = {in[11], 5'd20, 32'd196}; 24'b000000??????????????????: begin casez (in[33:32]) 2'b1?: {next, len, code} = {1'b0, 5'd18, 32'd197}; 2'b01: {next, len, code} = {1'b0, 5'd19, 32'd198}; 2'b00: {next, len, code} = {1'b0, 5'd19, 32'd199}; default: ; endcase end default: ; endcase end endmodule verilator-5.044/test_regress/t/t_wait.py0000755000542200017500000000103015125463617020737 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--no-timing'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_func_bad.v0000644000542200017500000000167215125463617021362 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin if (add(3'd1) != 0) $stop; // Too few args if (add(3'd1, 3'd2, 3'd3) != 0) $stop; // Too many args x; // Too few args if (hasout(3'd1) != 0) $stop; // outputs // f(.j(1), .no_such(2)); // Name mismatch f(.dup(1), .dup(3)); // Duplicate f(1,2,3); // Too many end function [2:0] add; input [2:0] from1; input [2:0] from2; begin add = from1 + from2; end endfunction task x; output y; begin end endtask function hasout; output [2:0] illegal_output; hasout = 0; endfunction function automatic int f( int j = 1, int dup = 0 ); return (j<<16) | dup; endfunction endmodule verilator-5.044/test_regress/t/t_class_extends_alias.out0000644000542200017500000000044315125463617024166 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_class_extends_alias.v:24:21: Unsupported: TYPEDEF 'foo_t' in 'class extends' 24 | class bar extends foo_t; | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.044/test_regress/t/t_display_impure.out0000644000542200017500000000005515125463617023203 0ustar mahmoudyfreeshell 1 2 *-* All Finished *-* verilator-5.044/test_regress/t/t_std_waiver.v0000644000542200017500000000060615125463617021764 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Rather than look at waivers, just check we included it `ifndef _VERILATED_STD_WAIVER_VLT_ `error "Didn't include, no _VERILATED_STD_WAIVER_VLT_" `endif module t; endmodule verilator-5.044/test_regress/t/t_compiler_include_split.py0000755000542200017500000000144115125463617024531 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.pli_filename = "t/t_compiler_include.cpp" test.top_filename = "t/t_compiler_include.v" test.compile(make_top_shell=False, make_main=False, verilator_flags2=[ "--exe", test.pli_filename, "--compiler-include", test.t_dir + "/t_compiler_include.h", "--output-split 1" ]) test.execute() test.passes() verilator-5.044/test_regress/t/t_select_little_pack.v0000644000542200017500000000114715125463617023450 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // No ascending range warning here reg [7:0] pack [3:0]; initial begin pack[0] = 8'h78; pack[1] = 8'h88; pack[2] = 8'h98; pack[3] = 8'hA8; if (pack[0] !== 8'h78) $stop; if (pack[1] !== 8'h88) $stop; if (pack[2] !== 8'h98) $stop; if (pack[3] !== 8'hA8) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_lint_const_func_dpi_bad.py0000755000542200017500000000076315125463617024640 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_class_param_typedef2.v0000644000542200017500000000120315125463617023676 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 virtual class Virt; endclass class MyInt; int x; endclass class uvm_object_registry #( type T = Virt ); static function T create_object(); T obj = new(); obj.x = 1; return obj; endfunction endclass typedef uvm_object_registry#(MyInt) type_id; module t; initial begin MyInt mi = type_id::create_object(); if (mi.x != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_trace_timescale.v0000644000542200017500000000103015125463617022731 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `timescale 1ms/1ms // See also t_time_sc_*.v/pl module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc = 0; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.044/test_regress/t/t_case_x_bad.py0000755000542200017500000000076615125463617022062 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_notiming_off.out0000644000542200017500000000362715125463617022643 0ustar mahmoudyfreeshell%Error-NOTIMING: t/t_timing_off.v:25:8: Event control statement in this location requires --timing : ... note: In instance 't' : ... With --no-timing, suggest have one event control statement per procedure, at the top of the procedure 25 | @e1; | ^ ... For error description see https://verilator.org/warn/NOTIMING?v=latest %Warning-STMTDLY: t/t_timing_off.v:33:12: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' 33 | initial #2 ->e1; | ^ ... For warning description see https://verilator.org/warn/STMTDLY?v=latest ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message. %Warning-STMTDLY: t/t_timing_off.v:37:12: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' 37 | initial #3 $stop; | ^ %Warning-STMTDLY: t/t_timing_off.v:38:12: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' 38 | initial #1 @(e1, e2) #1 $stop; | ^ %Error-NOTIMING: t/t_timing_off.v:38:15: Event control statement in this location requires --timing : ... note: In instance 't' : ... With --no-timing, suggest have one event control statement per procedure, at the top of the procedure 38 | initial #1 @(e1, e2) #1 $stop; | ^ %Warning-STMTDLY: t/t_timing_off.v:38:25: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' 38 | initial #1 @(e1, e2) #1 $stop; | ^ %Error: Exiting due to verilator-5.044/test_regress/t/t_math_width.v0000644000542200017500000000250515125463617021745 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (); // See also t_lint_width parameter A_ONE = '1; // verilator lint_off WIDTH parameter [3:0] A_W4 = A_ONE; // verilator lint_on WIDTH initial begin if ($bits(A_ONE) != 1 || A_ONE !== 1'b1) $stop; if ($bits(A_W4) != 4) $stop; if (A_W4 != 4'b0001) $stop; end b #(.B_WIDTH(48)) b (); reg [4:0] c; integer c_i; initial begin c_i = 3; c = 1'b1 << c_i; // No width warning when not embedded in expression, as is common syntax if (c != 5'b1000) $stop; end localparam D_TT = 32'd23; localparam D_SIX = 6; // verilator lint_off WIDTH localparam [5:0] D_SUB = D_TT - D_SIX; // verilator lint_on WIDTH initial begin if (D_SUB != 17) $stop; end initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule module b; parameter B_WIDTH = 1; localparam B_VALUE0 = {B_WIDTH{1'b0}}; localparam B_VALUE1 = {B_WIDTH{1'b1}}; reg [47:0] b_val; initial begin b_val = B_VALUE0; if (b_val != 48'b0) $stop; b_val = B_VALUE1; if (b_val != ~48'b0) $stop; end endmodule verilator-5.044/test_regress/t/t_inst_port_array.py0000755000542200017500000000073415125463617023224 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_sequence_unused.py0000755000542200017500000000073415125463617023200 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_inst_overwide.v0000644000542200017500000000235415125463617022500 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs outc_w30, outd_w73, // Inputs clk, ina_w1, inb_w61 ); input clk; input ina_w1; input [60:0] inb_w61; output [29:0] outc_w30; output [72:0] outd_w73; sub sub ( // Outputs .outy_w92 (outc_w30), // .large => (small) .outz_w22 (outd_w73), // .small => (large) // Inputs .clk (clk), .inw_w31 (ina_w1), // .large <= (small) .inx_w11 (inb_w61) // .small <= (large) ); endmodule module sub (/*AUTOARG*/ // Outputs outy_w92, outz_w22, // Inputs clk, inw_w31, inx_w11 ); input clk; input [30:0] inw_w31; input [10:0] inx_w11; output reg [91:0] outy_w92 /*verilator public*/; output reg [21:0] outz_w22 /*verilator public*/; always @(posedge clk) begin outy_w92 <= {inw_w31[29:0],inw_w31[29:0],inw_w31[29:0],2'b00}; outz_w22 <= {inx_w11[10:0],inx_w11[10:0]}; end endmodule // regfile verilator-5.044/test_regress/t/t_alias_sub_select.v0000644000542200017500000000100715125463617023112 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ // Inputs clk ); input clk; sub s (); assign s.a[0] = 0; assign s.b[1] = 1; initial begin if (s.a != 2) $stop; if (s.b != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module sub; wire [1:0] a, b; alias a = b; endmodule verilator-5.044/test_regress/t/t_let_unsup.out0000644000542200017500000000057515125463617022202 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_let_unsup.v:10:10: Unsupported: let typed ports 10 | let G(int a) = 30 + a; | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_let_unsup.v:11:10: Unsupported: let typed ports 11 | let H(signed a) = 30 + a; | ^~~~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_inst_signed.py0000755000542200017500000000073415125463617022313 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_trace_class.py0000755000542200017500000000116615125463617022270 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile( # verilator_flags2 = ['--binary --trace-vcd'], verilator_flags2=['--binary --trace-vcd']) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_udp_bad.v0000644000542200017500000000065615125463617021220 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; wire a, b; udp_x x (a, b); endmodule primitive udp_x (a_bad, b, c_bad); tri a_bad; output b; output c_bad; table //a b 0 : 1; 1 : 0; endtable endprimitive verilator-5.044/test_regress/t/t_preproc.out0000644000542200017500000003654315125463617021642 0ustar mahmoudyfreeshell`line 1 "t/t_preproc.v" 1 `line 6 "t/t_preproc.v" 0 `line 8 "t/t_preproc.v" 0 `line 10 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc2.vh" 1 `line 2 "t/t_preproc_inc2.vh" 0 At file "t/t_preproc_inc2.vh" line 5 `line 7 "t/t_preproc_inc2.vh" 0 `line 1 "t/t_preproc_inc3.vh" 1 `line 2 "t/t_preproc_inc3.vh" 0 `line 6 "t/t_preproc_inc3.vh" 0 At file "t/t_preproc_inc3.vh" line 10 `line 12 "inc3_a_filename_from_line_directive_with_LINE" 0 At file "inc3_a_filename_from_line_directive_with_LINE" line 12 `line 100 "inc3_a_filename_from_line_directive" 0 At file "inc3_a_filename_from_line_directive" line 100 `line 103 "inc3_a_filename_from_line_directive" 0 `line 106 "inc3_a_filename_from_line_directive" 0 `line 110 "inc3_a_filename_from_line_directive" 0 `line 7 "t/t_preproc_inc2.vh" 2 `line 9 "t/t_preproc_inc2.vh" 0 `line 10 "t/t_preproc.v" 2 `line 12 "t/t_preproc.v" 0 `line 15 "t/t_preproc.v" 0 /*verilator pass_thru comment*/ `line 17 "t/t_preproc.v" 0 /*verilator pass_thru_comment2*/ `line 19 "t/t_preproc.v" 0 `line 22 "t/t_preproc.v" 0 wire [3:0] q = { 1'b1 , 1'b0 , 1'b1 , 1'b1 }; `line 32 "t/t_preproc.v" 0 text. `line 34 "t/t_preproc.v" 0 foo bar foobar2 `line 39 "t/t_preproc.v" 0 `line 43 "t/t_preproc.v" 0 `line 48 "t/t_preproc.v" 0 first part `line 49 "t/t_preproc.v" 0 second part `line 49 "t/t_preproc.v" 0 third part { `line 50 "t/t_preproc.v" 0 a, `line 50 "t/t_preproc.v" 0 b, `line 50 "t/t_preproc.v" 0 c} Line_Preproc_Check 51 `line 53 "t/t_preproc.v" 0 `line 55 "t/t_preproc.v" 0 `line 57 "t/t_preproc.v" 0 deep deep `line 61 "t/t_preproc.v" 0 "Inside: `nosubst" "`nosubst" `line 66 "t/t_preproc.v" 0 x y LLZZ x y p q LLZZ p q r s LLZZ r s LLZZ p q LLZZ p q r s LLZZ r s `line 72 "t/t_preproc.v" 0 firstline comma","line LLZZ firstline comma","line `line 74 "t/t_preproc.v" 0 x y LLZZ "a" y `line 77 "t/t_preproc.v" 0 (a,b)(a,b) `line 80 "t/t_preproc.v" 0 $display("left side: \"right side\"") `line 83 "t/t_preproc.v" 0 bar_suffix more `line 86 "t/t_preproc.v" 0 arg suffix_after_space `line 89 "t/t_preproc.v" 0 `line 91 "t/t_preproc.v" 0 $c("Zap(\"",bug1,"\");");; `line 92 "t/t_preproc.v" 0 $c("Zap(\"","bug2","\");");; `line 94 "t/t_preproc.v" 0 `line 97 "t/t_preproc.v" 0 `line 100 "t/t_preproc.v" 0 initial begin $display("pre thrupre thrumid thrupost post: \"right side\""); $display("left side: \"right side\""); $display("left side: \"right side\""); $display("left_side: \"right_side\""); $display("na: \"right_side\""); $display("prep ( midp1 left_side midp2 ( outp ) ): \"right_side\""); $display("na: \"nana\""); $display("left_side right_side: \"left_side right_side\""); $display(": \"\""); $display("left side: \"right side\""); $display("left side: \"right side\""); $display("standalone"); `line 121 "t/t_preproc.v" 0 $display("twoline: \"first second\""); $write("*-* All Finished *-*\n"); $finish; end endmodule `line 131 "t/t_preproc.v" 0 `line 134 "t/t_preproc.v" 0 `line 139 "t/t_preproc.v" 0 module add1 ( input wire d1, output wire o1); `line 140 "t/t_preproc.v" 0 wire tmp_d1 = d1; `line 140 "t/t_preproc.v" 0 wire tmp_o1 = tmp_d1 + 1; `line 140 "t/t_preproc.v" 0 assign o1 = tmp_o1 ; endmodule module add2 ( input wire d2, output wire o2); `line 143 "t/t_preproc.v" 0 wire tmp_d2 = d2; `line 143 "t/t_preproc.v" 0 wire tmp_o2 = tmp_d2 + 1; `line 143 "t/t_preproc.v" 0 assign o2 = tmp_o2 ; endmodule `line 146 "t/t_preproc.v" 0 `line 152 "t/t_preproc.v" 0 `line 157 "t/t_preproc.v" 0 `line 157 "t/t_preproc.v" 0 generate for (i=0; i<(3); i=i+1) begin `line 157 "t/t_preproc.v" 0 psl cover { m5k.f .ctl._ctl_mvldx_m1.d[i] & ~m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoRise: m5kc_fcl._ctl_mvldx_m1"; `line 157 "t/t_preproc.v" 0 psl cover { ~m5k.f .ctl._ctl_mvldx_m1.d[i] & m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1"; `line 157 "t/t_preproc.v" 0 end endgenerate `line 159 "t/t_preproc.v" 0 module prot(); `protected I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] `line 165 "t/t_preproc.v" 0 `endprotected endmodule `line 169 "t/t_preproc.v" 0 module t_lint_pragma_protected; `line 173 "t/t_preproc.v" 0 `pragma protect begin_protected `pragma protect version=1 `pragma protect encrypt_agent="XXXXX" `pragma protect encrypt_agent_info="YYYYY" `pragma protect data_method="AES128-CBC" `pragma protect key_keyowner="BIG3#1" `pragma protect key_keyname="AAAAAA" `pragma protect key_method="RSA" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `pragma protect key_block ICAgICAgICAgICAgICAgICAgIEdOVSBMRVNTRVIgR0VORVJBTCBQVUJMSUMgTElDRU5TRQogICAg KSAyMDA3IE== `line 186 "t/t_preproc.v" 0 `pragma protect key_keyowner="BIG3#2" `pragma protect key_keyname="BBBBBB" `pragma protect key_method="RSA" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `pragma protect key_block IEV2ZXJ5b25lIGlzIHBlcm1pdHRlZCB0byBjb3B5IGFuZCBkaXN0cmlidXRlIHZlcmJhdGltIGNv cGllcwogb2YgdGhpcyBsaWNlbnNlIGRvY3VtZW50LCBidXQgY2hhbmdpbmcgaXQgaXMgbm90IGFs bG93ZWQuCgoKICBUaGl= `line 195 "t/t_preproc.v" 0 `pragma protect key_keyowner="BIG3#3" `pragma protect key_keyname="CCCCCCCC" `pragma protect key_method="RSA" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `pragma protect key_block TGljZW5zZSBpbmNvcnBvcmF0ZXMKdGhlIHRlcm1zIGFuZCBjb25kaXRpb25zIG9mIHZlcnNpb24g MyBvZiB0aGUgR05VIEdlbmVyYWwgUHVibGljCkxpY2Vuc2UsIHN1cHBsZW1lbnRlZCBieSB0aGUg YWRkaXRpb25hbCBwZXJ= `line 204 "t/t_preproc.v" 0 `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 295) `pragma protect data_block aW5pdGlvbnMuCgogIEFzIHVzZWQgaGVyZWluLCAidGhpcyBMaWNlbnNlIiByZWZlcnMgdG8gdmVy c2lvbiAzIG9mIHRoZSBHTlUgTGVzc2VyCkdlbmVyYWwgUHVibGljIExpY2Vuc2UsIGFuZCB0aGUg IkdOVSBHUEwiIHJlZmVycyB0byB2ZXJzaW9uIDMgb2YgdGhlIEdOVQpHZW5lcmFsIFB1YmxpYyBM aWNlbnNlLgoKICAiVGhlIExpYnJhcnkiIHJlZmVycyB0byBhIGNvdmVyZWQgd29yayBnb3Zlcm5l ZCBieSB0aGlzIExpY2Vuc2UsCm90aGVyIHRoYW4gYW4gQXBwbGljYXRpb24gb3IgYSBDb21iaW5l ZCBXb3JrIGFzIG== `line 214 "t/t_preproc.v" 0 `pragma protect end_protected `line 216 "t/t_preproc.v" 0 `pragma protect `pragma protect end `line 220 "t/t_preproc.v" 0 endmodule `line 222 "t/t_preproc.v" 0 `line 232 "t/t_preproc.v" 0 begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more `line 236 "t/t_preproc.v" 0 `line 239 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc4.vh" 1 `line 2 "t/t_preproc_inc4.vh" 0 `line 6 "t/t_preproc_inc4.vh" 0 `line 8 "t/t_preproc_inc4.vh" 0 `line 239 "t/t_preproc.v" 2 `line 240 "t/t_preproc.v" 0 `line 243 "t/t_preproc.v" 0 `line 245 "t/t_preproc.v" 0 `line 249 "t/t_preproc.v" 0 `line 252 "t/t_preproc.v" 0 $blah("ab,cd","e,f"); $blah(this.logfile,vec); $blah(this.logfile,vec[1,2,3]); $blah(this.logfile,{blah.name(), " is not foo"}); `line 258 "t/t_preproc.v" 0 `line 261 "t/t_preproc.v" 0 `pragma foo = 1 `default_nettype none `default_nettype uwire `line 265 "t/t_preproc.v" 0 `line 268 "t/t_preproc.v" 0 `line 272 "t/t_preproc.v" 0 Line_Preproc_Check 272 `line 274 "t/t_preproc.v" 0 `line 277 "t/t_preproc.v" 0 (p,q) `line 284 "t/t_preproc.v" 0 (x,y) Line_Preproc_Check 285 `line 287 "t/t_preproc.v" 0 `line 290 "t/t_preproc.v" 0 beginend beginend "beginend" `line 298 "t/t_preproc.v" 0 `\esc`def `line 304 "t/t_preproc.v" 0 Not a \`define `line 306 "t/t_preproc.v" 0 x,y)--bee submacro has comma paren `line 314 "t/t_preproc.v" 0 $display("bits %d %d", $bits(foo), 10); `line 319 "t/t_preproc.v" 0 `line 324 "t/t_preproc.v" 0 `line 327 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 assign a3 = ~b3 ; `line 341 "t/t_preproc.v" 0 `line 343 "t/t_preproc.v" 0 \ `line 352 "t/t_preproc.v" 0 `line 352 "t/t_preproc.v" 0 `line 352 "t/t_preproc.v" 0 def i `line 354 "t/t_preproc.v" 0 `line 356 "t/t_preproc.v" 0 `line 360 "t/t_preproc.v" 0 `line 366 "t/t_preproc.v" 0 1 /*verilator NOT IN DEFINE*/ (nodef) 2 /*verilator PART OF DEFINE*/ (hasdef) 3 `line 368 "t/t_preproc.v" 0 /*verilator NOT PART OF DEFINE*/ (nodef) `line 369 "t/t_preproc.v" 0 4 `line 369 "t/t_preproc.v" 0 /*verilator PART OF DEFINE*/ (nodef) `line 370 "t/t_preproc.v" 0 5 also in `line 370 "t/t_preproc.v" 0 also3 (nodef) HAS a NEW `line 373 "t/t_preproc.v" 0 LINE `line 375 "t/t_preproc.v" 0 `line 377 "t/t_preproc.v" 0 `line 390 "t/t_preproc.v" 0 `line 393 "t/t_preproc.v" 0 EXP: clxx_scen clxx_scen EXP: clxx_scen "clxx_scen" EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " end"}); end while(0); `line 399 "t/t_preproc.v" 0 do `line 399 "t/t_preproc.v" 0 `line 399 "t/t_preproc.v" 0 `line 399 "t/t_preproc.v" 0 `line 399 "t/t_preproc.v" 0 `line 399 "t/t_preproc.v" 0 if (start("t/t_preproc.v", 399)) begin `line 399 "t/t_preproc.v" 0 `line 399 "t/t_preproc.v" 0 message({"Blah-", "clx_scen", " end"}); `line 399 "t/t_preproc.v" 0 end `line 399 "t/t_preproc.v" 0 `line 399 "t/t_preproc.v" 0 while(0); `line 401 "t/t_preproc.v" 0 `line 403 "t/t_preproc.v" 0 `line 407 "t/t_preproc.v" 0 `line 407 "t/t_preproc.v" 0 `line 408 "t/t_preproc.v" 0 EXP: This is fooed This is fooed EXP: This is fooed_2 This is fooed_2 `line 415 "t/t_preproc.v" 0 np np `line 426 "t/t_preproc.v" 0 `line 429 "t/t_preproc.v" 0 `line 437 "t/t_preproc.v" 0 `line 441 "t/t_preproc.v" 0 hello3hello3hello3 hello4hello4hello4hello4 `line 447 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc4.vh" 1 `line 2 "t/t_preproc_inc4.vh" 0 `line 6 "t/t_preproc_inc4.vh" 0 `line 8 "t/t_preproc_inc4.vh" 0 `line 447 "t/t_preproc.v" 2 `line 448 "t/t_preproc.v" 0 `line 456 "t/t_preproc.v" 0 Line_Preproc_Check 460 Line_Preproc_Check 466 "FOO \ BAR " "arg_line1 \ arg_line2" "FOO \ BAR " `line 469 "t/t_preproc.v" 0 Line_Preproc_Check 469 `line 473 "t/t_preproc.v" 0 abc `line 483 "t/t_preproc.v" 0 EXP: sonet_frame sonet_frame `line 489 "t/t_preproc.v" 0 EXP: sonet_frame sonet_frame EXP: sonet_frame sonet_frame `line 499 "t/t_preproc.v" 0 EXP: module zzz ; endmodule module zzz ; endmodule module zzz ; endmodule `line 506 "t/t_preproc.v" 0 EXP: module a_b ; endmodule module a_b ; endmodule module a_b ; endmodule `line 511 "t/t_preproc.v" 0 integer foo; module t; initial begin : \`LEX_CAT(a[0],_assignment) `line 523 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) "); end initial begin : \a[0]_assignment_a[1] `line 530 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] "); end initial begin : \`CAT(pp,suffix) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(pp,suffix) "); end initial begin : \`CAT(ff,bb) `line 544 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) "); end initial begin : \`zzz `line 550 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz "); end initial begin : \`FOO `line 557 "t/t_preproc.v" 0 $write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO "); end initial begin : \xx`FOO `line 559 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO "); end initial begin : \`UNKNOWN $write("GOT%%m='%m' EXP='%s'\n", "t.\\`UNKNOWN "); end initial begin : \`DEF_NO_EXPAND $write("GOT%%m='%m' EXP='%s'\n", "t.\\`DEF_NO_EXPAND "); end initial $write("GOT='%s' EXP='%s'\n", "foo name baz", "foo bar baz"); initial $write("GOT='%s' EXP='%s'\n", "foo name baz", "foo `A(bar) baz"); initial $write("Slashed=`%s'\n", "1//2.3"); initial `line 590 "t/t_preproc.v" 0 $display("%s%s","a1","b2c3\n"); endmodule `line 593 "t/t_preproc.v" 0 `line 596 "t/t_preproc.v" 0 $display("RAM0"); $display("CPU"); `line 601 "t/t_preproc.v" 0 `line 606 "t/t_preproc.v" 0 XXE_FAMILY = XXE_ $display("XXE_ is defined"); `line 613 "t/t_preproc.v" 0 XYE_FAMILY = XYE_ $display("XYE_ is defined"); `line 620 "t/t_preproc.v" 0 XXS_FAMILY = XXS_some $display("XXS_some is defined"); `line 627 "t/t_preproc.v" 0 XYS_FAMILY = XYS_foo $display("XYS_foo is defined"); `line 634 "t/t_preproc.v" 0 `line 636 "t/t_preproc.v" 0 `line 644 "t/t_preproc.v" 0 `line 651 "t/t_preproc.v" 0 `line 658 "t/t_preproc.v" 0 `line 665 "t/t_preproc.v" 0 `line 667 "t/t_preproc.v" 0 `line 669 "t/t_preproc.v" 0 (.mySig (myInterface.pa5), `line 673 "t/t_preproc.v" 0 `line 676 "t/t_preproc.v" 0 `dbg_hdl(UVM_LOW, ("Functional coverage enabled: paramgrp")); `line 679 "t/t_preproc.v" 0 `line 687 "t/t_preproc.v" 0 module pcc2_cfg; generate `line 689 "t/t_preproc.v" 0 covergroup a @(posedge b); `line 689 "t/t_preproc.v" 0 c: coverpoint d iff ((c) === 1'b1); endgroup `line 689 "t/t_preproc.v" 0 a u_a; `line 689 "t/t_preproc.v" 0 initial do begin $display ("DEBUG : %s [%m]", $sformatf ("Functional coverage enabled: u_a")); end while(0); endgenerate endmodule `line 693 "t/t_preproc.v" 0 "`NOT_DEFINED_STR" `line 698 "t/t_preproc.v" 0 """First line with "quoted"\nSecond line\ Third line""" """First line Second line""" `line 705 "t/t_preproc.v" 0 """QQQ defform""" """QQQ defval""" `line 710 "t/t_preproc.v" 0 "string argument" `line 714 "t/t_preproc.v" 0 `line 717 "t/t_preproc.v" 0 bar "foo foo foo" bar bar """foo foo foo""" bar `line 722 "t/t_preproc.v" 0 predef 0 0 predef 1 1 predef 2 2 predef 3 3 predef 10 10 predef 11 11 predef 20 20 predef 21 21 predef 22 22 predef 23 23 predef -2 -2 predef -1 -1 predef 0 0 predef 1 1 predef 2 2 `line 744 "t/t_preproc.v" 0 string boo = "test"; string boo = "test x,y x,y"; string boo = "testx,ytest x x,y"; string boo = "testtest x,y xquux(test)"; `line 757 "t/t_preproc.v" 0 `line 760 "t/t_preproc.v" 0 `line 769 "t/t_preproc.v" 0 verilator-5.044/test_regress/t/t_altera_lpm_ram_dq.py0000755000542200017500000000111115125463617023436 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module]) test.passes() verilator-5.044/test_regress/t/t_class_static_member_pkg.v0000644000542200017500000000240615125463617024461 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); package Pkg; class Cls; int c_no = 2; //automatic int c_au = 2; // automatic not a legal keyword here static int c_st = 22; function int f_c_no (); ++c_no; return c_no; endfunction function int f_c_st (); ++c_st; return c_st; endfunction static function int f_cs_st (); ++c_st; return c_st; endfunction endclass endpackage module t; Pkg::Cls a = new; Pkg::Cls b = new; int v; initial begin v = a.f_c_no(); `checkh(v, 3); v = a.f_c_no(); `checkh(v, 4); v = b.f_c_no(); `checkh(v, 3); v = b.f_c_no(); `checkh(v, 4); v = a.f_c_st(); `checkh(v, 23); v = a.f_c_st(); `checkh(v, 24); v = b.f_c_st(); `checkh(v, 25); v = b.f_c_st(); `checkh(v, 26); // v = Pkg::Cls::f_cs_st(); `checkh(v, 27); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_func_no_parentheses_bad.out0000644000542200017500000000042515125463617025014 0ustar mahmoudyfreeshell%Error: t/t_func_no_parentheses_bad.v:16:11: Found definition of 'func' as a FUNC but expected a variable 16 | a = func; | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_typedef_unused_bad.py0000755000542200017500000000103015125463617023624 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--Wpedantic"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_json_only_tag.py0000755000542200017500000000135415125463617022651 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums'], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.files_identical(out_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_struct_literal_param.py0000755000542200017500000000077015125463617024225 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--debug"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_property_untyped_unsup.out0000644000542200017500000000056415125463617025050 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_property_untyped_unsup.v:20:52: Untyped property port following a typed port 20 | property check(cyc_mod_2, logic [4:0] expected, arg3, untyped arg4, arg5); | ^~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.044/test_regress/t/t_hier_block_perf.vlt0000644000542200017500000000050415125463617023267 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 `verilator_config `ifdef WORKERS hier_workers -module "Test" -workers `WORKERS hier_workers -module "Check" -workers `WORKERS `endif verilator-5.044/test_regress/t/t_semaphore_std.py0000755000542200017500000000110215125463617022630 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_semaphore.v" test.compile(verilator_flags2=["--binary -Wall -DSEMAPHORE_T=std::semaphore"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_package_struct.v0000644000542200017500000000106115125463617022610 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 package pkg; typedef struct { string a, b; struct { bit a, b; } has; } strings; endpackage module t; initial begin pkg::strings stct; stct.a = "hello"; stct.b = "world"; $display("%s, %s (%1b, %1b)", stct.a, stct.b, stct.has.a, stct.has.b); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_lint_literal_bad.out0000644000542200017500000000065115125463617023447 0ustar mahmoudyfreeshell%Warning-WIDTHTRUNC: t/t_lint_literal_bad.v:10:33: Value too large for 8 bit number: 256 10 | localparam the_localparam = 8'd256; | ^~~~~~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.044/test_regress/t/t_unopt_combo_isolate_vlt.py0000755000542200017500000000365215125463617024740 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_unopt_combo.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(verilator_flags2=[ "--no-json-edit-nums", "--stats", test.t_dir + "/t_unopt_combo_isolate.vlt", "-fno-dfg" ]) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, isolate_assignments blocks\s+4') test.file_grep( out_filename, r'{"type":"VAR","name":"t.b",.*"loc":"\w,23:[^"]*",.*"origName":"b",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' ) test.file_grep( out_filename, r'{"type":"VAR","name":"__Vfunc_t.file.get_31_16__0__Vfuncout",.*"loc":"\w,104:[^"]*",.*"origName":"__Vfunc_t__DOT__file__DOT__get_31_16__0__Vfuncout",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' ) test.file_grep( out_filename, r'{"type":"VAR","name":"__Vfunc_t.file.get_31_16__0__t_crc",.*"loc":"\w,105:[^"]*",.*"origName":"__Vfunc_t__DOT__file__DOT__get_31_16__0__t_crc",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' ) test.file_grep( out_filename, r'{"type":"VAR","name":"__Vtask_t.file.set_b_d__1__t_crc",.*"loc":"\w,115:[^"]*",.*"origName":"__Vtask_t__DOT__file__DOT__set_b_d__1__t_crc",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' ) test.file_grep( out_filename, r'{"type":"VAR","name":"__Vtask_t.file.set_b_d__1__t_c",.*"loc":"\w,116:[^"]*",.*"origName":"__Vtask_t__DOT__file__DOT__set_b_d__1__t_c",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' ) test.execute() test.passes() verilator-5.044/test_regress/t/t_trace_class.v0000644000542200017500000000134115125463617022075 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" class Cls #(parameter int PARAM); static int s_cls_static = 123; endclass module top(); typedef Cls#(.PARAM(0)) Cls_t; Cls_t obj; initial begin obj = new; `ifdef verilator obj.s_cls_static = $c("100"); // no-opt `else obj.s_cls_static = 100; `endif if (obj.s_cls_static != 100) $stop; if (obj.PARAM != 0) $stop; $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); $dumpvars(0); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_math_countbits_tri.v0000644000542200017500000000170415125463617023516 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Outputs num_zeros, num_ones, // Inputs clk, reset_l, vec ); input logic clk; input logic reset_l; input logic [7:0] vec; output logic [7:0] num_zeros; output logic [7:0] num_ones; always_comb begin num_zeros = '0; num_ones = '0; for (int i = 0; i < 8; i++) begin if (vec[i] == 0) begin num_zeros++; end else begin num_ones++; end end end assert property (@(negedge clk) disable iff (~reset_l) (num_ones == $countones(vec))); assert property (@(negedge clk) disable iff (~reset_l) (num_zeros == $countbits(vec, '0))); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_property_sexpr2_bad.out0000644000542200017500000000125215125463617024152 0ustar mahmoudyfreeshell%Error: t/t_property_sexpr2_bad.v:20:35: Delay value is not an elaboration-time constant (IEEE 1800-2023 16.7) : ... note: In instance 't' 20 | assert property (@(posedge clk) ##clk val); | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_property_sexpr2_bad.v:21:35: Delay value is not an elaboration-time constant (IEEE 1800-2023 16.7) : ... note: In instance 't' 21 | assert property (@(posedge clk) ##(1+clk) val); | ^~ %Error: Exiting due to verilator-5.044/test_regress/t/t_let_stmt_bad.out0000644000542200017500000000041015125463617022611 0ustar mahmoudyfreeshell%Error: t/t_let_stmt_bad.v:15:14: Expected statement, not let substitution 'letf' 15 | 0: letf(0); | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_sarif.py0000755000542200017500000000254615125463617021114 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=['-Wno-fatal --diagnostics-sarif --no-skip-identical'], expect_filename=test.golden_filename) sarif_filename = test.obj_dir + "/" + test.vm_prefix + ".sarif" # Make sure V3Error meta comments aren't in any outputs test.file_grep_not(test.compile_log_filename, r'__WARN') test.file_grep_not(sarif_filename, r'__WARN') test.files_identical(sarif_filename, "t/" + test.name + ".sarif.out", "logfile") # Check that sarif parses nout = test.run_capture("sarif --version", check=False) version_match = re.search(r'SARIF tools', nout, re.IGNORECASE) if not version_match: test.skip("sarif is not installed") html_filename = test.obj_dir + "/validation.html" test.run(cmd=['sarif', 'html', sarif_filename, '--output', html_filename]) # Validator: # https://sarifweb.azurewebsites.net/Validation # Rewrite # test.run(cmd=['sarif copy t/t_sarif.out --output ' + test.obj_dir + '/t_sarif.out.rewrite']) test.passes() verilator-5.044/test_regress/t/t_inst_notunsized.v0000644000542200017500000000552615125463617023062 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [71:0] muxed; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .muxed (muxed[71:0]), // Inputs .clk (clk), .in (in[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {muxed[63:0]}; wire [5:0] width_check = cyc[5:0] + 1; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h20050a66e7b253d1 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs muxed, // Inputs clk, in ); input clk; input [31:0] in; output [71:0] muxed; wire [71:0] a = {in[7:0],~in[31:0],in[31:0]}; wire [71:0] b = {~in[7:0],in[31:0],~in[31:0]}; /*AUTOWIRE*/ Muxer muxer ( .sa (0), .sb (in[0]), /*AUTOINST*/ // Outputs .muxed (muxed[71:0]), // Inputs .a (a[71:0]), .b (b[71:0])); endmodule module Muxer (/*AUTOARG*/ // Outputs muxed, // Inputs sa, sb, a, b ); input sa; input sb; output wire [71:0] muxed; input [71:0] a; input [71:0] b; // Constification wasn't sizing with inlining and gave // unsized error on below // v assign muxed = (({72{sa}} & a) | ({72{sb}} & b)); endmodule verilator-5.044/test_regress/t/t_wait_fork.v0000644000542200017500000000102015125463617021571 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; logic never; integer n = 0; initial begin disable fork; fork #10 if (n != 0) $stop; else n = 1; #15 if (n != 1) $stop; else n = 2; join_none wait fork; if (n != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_tri_unconn.v0000644000542200017500000001063015125463617021771 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; wire one = '1; wire z0 = 'z; wire z1 = 'z; wire z2 = 'z; wire z3 = 'z; wire tog = cyc[0]; // verilator lint_off PINMISSING t_tri0 tri0a (.line(`__LINE__), .expval(1'b0)); // Pin missing t_tri0 tri0b (.line(`__LINE__), .expval(1'b0), .tn()); t_tri0 tri0z (.line(`__LINE__), .expval(1'b0), .tn(z0)); t_tri0 tri0Z (.line(`__LINE__), .expval(1'b0), .tn(1'bz)); t_tri0 tri0c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); t_tri0 tri0d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); // Warning would be reasonable given tri0 connect t_tri0 tri0e (.line(`__LINE__), .expval(1'b0), .tn(~one)); t_tri0 tri0f (.line(`__LINE__), .expval(1'b1), .tn(one)); t_tri0 tri0g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog)); t_tri0 tri0h (.line(`__LINE__), .expval(cyc[0]), .tn(tog)); t_tri1 tri1a (.line(`__LINE__), .expval(1'b1)); // Pin missing t_tri1 tri1b (.line(`__LINE__), .expval(1'b1), .tn()); t_tri1 tri1z (.line(`__LINE__), .expval(1'b1), .tn(z1)); t_tri1 tri1Z (.line(`__LINE__), .expval(1'b1), .tn(1'bz)); t_tri1 tri1c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); // Warning would be reasonable given tri1 connect t_tri1 tri1d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); t_tri1 tri1e (.line(`__LINE__), .expval(1'b0), .tn(~one)); t_tri1 tri1f (.line(`__LINE__), .expval(1'b1), .tn(one)); t_tri1 tri1g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog)); t_tri1 tri1h (.line(`__LINE__), .expval(cyc[0]), .tn(tog)); t_tri2 tri2a (.line(`__LINE__), .expval(1'b0)); // Pin missing t_tri2 tri2b (.line(`__LINE__), .expval(1'b0), .tn()); t_tri2 tri2z (.line(`__LINE__), .expval(1'b0), .tn(z2)); t_tri2 tri2Z (.line(`__LINE__), .expval(1'b0), .tn(1'bz)); t_tri2 tri2c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); t_tri2 tri2d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); t_tri2 tri2e (.line(`__LINE__), .expval(1'b0), .tn(~one)); t_tri2 tri2f (.line(`__LINE__), .expval(1'b1), .tn(one)); t_tri2 tri2g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog)); t_tri2 tri2h (.line(`__LINE__), .expval(cyc[0]), .tn(tog)); t_tri3 tri3a (.line(`__LINE__), .expval(1'b1)); // Pin missing t_tri3 tri3b (.line(`__LINE__), .expval(1'b1), .tn()); t_tri3 tri3z (.line(`__LINE__), .expval(1'b1), .tn(z3)); t_tri3 tri3Z (.line(`__LINE__), .expval(1'b1), .tn(1'bz)); t_tri3 tri3c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); t_tri3 tri3d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); t_tri3 tri3e (.line(`__LINE__), .expval(1'b0), .tn(~one)); t_tri3 tri3f (.line(`__LINE__), .expval(1'b1), .tn(one)); t_tri3 tri3g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog)); t_tri3 tri3h (.line(`__LINE__), .expval(cyc[0]), .tn(tog)); // verilator lint_on PINMISSING // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module t_tri0 (line, expval, tn); input integer line; input expval; input tn; // Illegal to be inout; spec requires net connection to any inout tri0 tn; wire clk = t.clk; always @(posedge clk) if (tn !== expval) begin $display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop; end endmodule module t_tri1 (line, expval, tn); input integer line; input expval; input tn; tri1 tn; wire clk = t.clk; always @(posedge clk) if (tn !== expval) begin $display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop; end endmodule module t_tri2 (line, expval, tn); input integer line; input expval; input tn; pulldown(tn); wire clk = t.clk; always @(posedge clk) if (tn !== expval) begin $display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop; end endmodule module t_tri3 (line, expval, tn); input integer line; input expval; input tn; pullup(tn); wire clk = t.clk; always @(negedge clk) if (tn !== expval) begin $display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop; end endmodule verilator-5.044/test_regress/t/t_time_vpi_c.cpp0000644000542200017500000000626115125463617022253 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2011 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include "vpi_user.h" #include #include // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" #include "TestVpi.h" int errors = 0; //====================================================================== #define NEED_EXTERNS #ifdef NEED_EXTERNS extern "C" { extern void dpii_check(); } #endif //====================================================================== void dpi_bad() { { int res = svGetTime(0, nullptr); TEST_CHECK_EQ(res, -1); } { int res = svGetTimeUnit(0, nullptr); TEST_CHECK_EQ(res, -1); } { int res = svGetTimePrecision(0, nullptr); TEST_CHECK_EQ(res, -1); } } void dpi_show(svScope obj) { const char* namep; if (obj) { namep = svGetNameFromScope(obj); } else { namep = "global"; } svTimeVal t; // aka s_vpi_time t.type = vpiSimTime; int gres = svGetTime(obj, &t); vpi_printf(const_cast("%s svGetTime = %d %d,%d\n"), namep, gres, (int)t.high, (int)t.low); // These will both print the precision, because the 0 asks for global scope int32_t u = 99; int ures = svGetTimeUnit(obj, &u); int32_t p = 99; int pres = svGetTimePrecision(obj, &p); vpi_printf(const_cast("%s svGetTimeUnit = %d %d"), namep, ures, u); vpi_printf(const_cast(" svGetTmePrecision = %d %d\n"), pres, p); } void vpi_show(vpiHandle obj) { const char* namep; if (obj) { namep = vpi_get_str(vpiFullName, obj); } else { namep = "global"; } s_vpi_time t; t.type = vpiSimTime; vpi_get_time(obj, &t); vpi_printf(const_cast("%s vpiSimTime = %d,%d"), namep, (int)t.high, (int)t.low); // Should be same value as vpiSimTime, just converted to real t.type = vpiScaledRealTime; vpi_get_time(obj, &t); vpi_printf(const_cast(" vpiScaledRealTime = %g\n"), t.real); // These will both print the precision, because the 0 asks for global scope int u = vpi_get(vpiTimeUnit, obj); int p = vpi_get(vpiTimePrecision, obj); vpi_printf(const_cast("%s vpiTimeUnit = %d"), namep, u); vpi_printf(const_cast(" vpiTimePrecision = %d\n"), p); } void dpii_check() { dpi_bad(); dpi_show(0); vpi_show(0); svScope smod = svGetScopeFromName("top.t"); if (!smod) { vpi_printf(const_cast("-- Cannot svGetScopeFromName\n")); } else { dpi_show(smod); } TestVpiHandle mod = vpi_handle_by_name((PLI_BYTE8*)"top.t", NULL); if (!mod) { vpi_printf(const_cast("-- Cannot vpi_find module\n")); } else { vpi_show(mod); } } verilator-5.044/test_regress/t/t_class_extern_args_bad.py0000755000542200017500000000076615125463617024326 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_event_control_prev_name_collision.v0000644000542200017500000000277115125463617026612 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module S( input reset, io_i, output io_o ); reg s; always @(posedge reset) begin if (reset) begin s <= 1'h0; end else begin s <= io_i; end end assign io_o = s; endmodule module Q( input reset_e, input reset_d, output ready_e ); wire reset_n; wire io_v; wire io_e; S e ( .io_i (), .reset (reset_e | ~reset_n), .io_o (io_e) ); S v ( .io_i (io_e), .reset (reset_e), .io_o (io_v) ); assign reset_n = ~reset_d; assign ready_e = io_v; endmodule module Test( input reset, output valid ); wire ready_e; Q q ( .reset_e (reset), .reset_d (reset), .ready_e (ready_e) ); assign valid = ready_e; endmodule module Test2( input reset, input valid ); always begin if (~reset & valid) begin $fatal; end end endmodule module Dut( input reset ); wire valid_g; Test t ( .reset (reset), .valid (valid_g) ); Test2 t2 ( .reset (reset), .valid (valid_g) ); endmodule module t (/*AUTOARG*/ ); reg [$bits(dut.reset)-1:0] reset; Dut dut ( .reset(reset) ); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_concat_or.py0000755000542200017500000000070615125463617021753 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.044/test_regress/t/t_for_init_bug.v0000644000542200017500000000151515125463617022263 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs priority_mask, // Inputs muxed_requests ); parameter ARW = 7; // verilator lint_off UNOPTFLAT integer i,j; output reg [ARW-1:0] priority_mask; input [ARW-1:0] muxed_requests; always @* begin for (i=ARW-1;i>0;i=i-1) begin priority_mask[i]=1'b0; // vvvv=== note j=j not j=i; was bug for( j=j;j>=0;j=j-1) priority_mask[i]=priority_mask[j] | muxed_requests[j]; end //Bit zero is always enabled priority_mask[0]=1'b0; end endmodule // Local Variables: // verilog-auto-inst-param-value: t // End: verilator-5.044/test_regress/t/t_string_type_methods_bad.py0000755000542200017500000000076615125463617024712 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_queue_var_slice.v0000644000542200017500000000102315125463617022762 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer i = 0; integer q[$] = {0, 1}; always @(posedge clk) begin $display("%p", q[i:i+1]); q.push_back(i+2); i++; if (i >= 3) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.044/test_regress/t/t_typedef_iface_typedef3.py0000755000542200017500000000077115125463617024400 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_tri_gate_bufif1.py0000755000542200017500000000136515125463617023040 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" test.compile(make_top_shell=False, make_main=False, v_flags2=['+define+T_BUFIF1'], make_flags=['CPPFLAGS_ADD=-DT_BUFIF1'], verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.044/test_regress/t/t_math_div0.py0000755000542200017500000000077515125463617021665 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--x-assign 0']) test.execute() test.passes() verilator-5.044/test_regress/t/t_gate_strength.py0000755000542200017500000000075415125463617022645 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['-bbox-unsup']) test.passes() verilator-5.044/test_regress/t/t_bitsel_wire_array_bad.out0000644000542200017500000000052515125463617024473 0ustar mahmoudyfreeshell%Error: t/t_bitsel_wire_array_bad.v:16:16: Illegal assignment of constant to unpacked array : ... note: In instance 't' 16 | assign b = a[0]; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_var_pins_bad.out0000644000542200017500000000024015125463617022600 0ustar mahmoudyfreeshell%Error: --pins-bv maximum is 65: 99 ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_var_ref_static.v0000644000542200017500000000070215125463617022605 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Make sure type errors aren't suppressable // verilator lint_off WIDTH module t; // TODO make this a proper test function void crs(const ref static i); endfunction function void rs(ref static i); endfunction endmodule verilator-5.044/test_regress/t/t_property_var_unsup.out0000644000542200017500000000115515125463617024145 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_property_var_unsup.v:18:13: Unsupported: sequence match items 18 | (valid, prevcyc = cyc) |=> (cyc == prevcyc + 1); | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_property_var_unsup.v:17:11: Unsupported: property variable declaration 17 | int prevcyc; | ^~~~~~~ %Error-UNSUPPORTED: t/t_property_var_unsup.v:24:31: Unsupported: property variable default value 24 | property with_def(int nine = 9); | ^ %Error: Exiting due to verilator-5.044/test_regress/t/t_cast_stream.py0000755000542200017500000000071415125463617022310 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.044/test_regress/t/t_do_while.py0000755000542200017500000000073415125463617021577 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_func_const_packed_array_bad.v0000644000542200017500000000162315125463617025271 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module t; localparam [ 1 : 0 ] [ 31 : 0 ] P = {32'd5, 32'd1}; localparam P6 = f_add(P); localparam P14 = f_add2(2, 3, f_add(P)); localparam P24 = f_add2(7, 8, 9); initial begin // Should never get here $write("*-* All Finished *-*\n"); $finish; end function integer f_add(input [ 1 : 0 ] [ 31 : 0 ] params); f_add = params[0]+params[1]; if (f_add == 15) $fatal(2, "f_add = 15"); endfunction // Speced ok: function called from function function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); logic [ 1 : 0 ] [ 31 : 0 ] params; params[0] = a; params[1] = b; f_add2 = f_add(params)+c; endfunction endmodule verilator-5.044/test_regress/t/t_comb_input_2.cpp0000644000542200017500000000233715125463617022515 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2022 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "verilated.h" #include "Vt_comb_input_2.h" #include "Vt_comb_input_2__Syms.h" #include int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; contextp->debug(0); contextp->commandArgs(argc, argv); srand48(5); const std::unique_ptr topp{new VM_PREFIX}; topp->inc = 1; topp->clk = false; topp->eval(); while (!contextp->gotFinish() && contextp->time() < 100000) { contextp->timeInc(5); if (topp->clk) topp->inc += 1; topp->clk = !topp->clk; topp->eval(); } if (!contextp->gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } return 0; } verilator-5.044/test_regress/t/t_cover_expr.py0000755000542200017500000000170115125463617022154 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap from pathlib import Path test.scenarios('simulator') test.compile(verilator_flags2=['--cc', '--coverage-expr']) test.execute() # Read the input .v file and do any CHECK_COVER requests test.inline_checks() test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--annotate-points", "--annotate", test.obj_dir + "/annotated", test.obj_dir + "/coverage.dat", ], verilator_run=True) top = Path(test.top_filename) test.files_identical(test.obj_dir + f"/annotated/{top.name}", test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_package_alone_bad.py0000755000542200017500000000076615125463617023371 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_class_local_nested_bad.py0000755000542200017500000000100415125463617024423 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_timing_func_join.v0000644000542200017500000000124515125463617023136 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; function int fun(int val); fork $display("abc"); $display("def"); join_none // Although join is illegal, join_none legal (IEEE 1800-2023 13.4) return val + 2; endfunction task tsk(); fork $display("ghi"); $display("jkl"); join_none endtask initial begin $display("$d", fun(2)); tsk(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_interface_ar2a.py0000755000542200017500000000071415125463617022650 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.044/test_regress/t/t_param_array6.py0000755000542200017500000000073415125463617022371 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_mem_packed_assign.py0000755000542200017500000000073415125463617023436 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_force_select_bad.out0000644000542200017500000000327615125463617023430 0ustar mahmoudyfreeshell%Error: t/t_force_select_bad.v:24:5: Force left-hand-side must not have variable bit/part select (IEEE 1800-2023 10.6.2) : ... note: In instance 't' 24 | force array1[bad_index] = 1'b1; | ^~~~~ t/t_force_select_bad.v:24:18: ... Location of non-constant index 24 | force array1[bad_index] = 1'b1; | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_force_select_bad.v:25:5: Release left-hand-side must not have variable bit/part select (IEEE 1800-2023 10.6.2) : ... note: In instance 't' 25 | release array1[bad_index]; | ^~~~~~~ t/t_force_select_bad.v:25:20: ... Location of non-constant index 25 | release array1[bad_index]; | ^~~~~~~~~ %Error: t/t_force_select_bad.v:26:5: Force left-hand-side must not have variable bit/part select (IEEE 1800-2023 10.6.2) : ... note: In instance 't' 26 | force vec[bad_index+:1] = 1'b1; | ^~~~~ t/t_force_select_bad.v:26:15: ... Location of non-constant index 26 | force vec[bad_index+:1] = 1'b1; | ^~~~~~~~~ %Error: t/t_force_select_bad.v:27:5: Release left-hand-side must not have variable bit/part select (IEEE 1800-2023 10.6.2) : ... note: In instance 't' 27 | release vec[bad_index+:1]; | ^~~~~~~ t/t_force_select_bad.v:27:17: ... Location of non-constant index 27 | release vec[bad_index+:1]; | ^~~~~~~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_interface_virtual_bad.py0000755000542200017500000000076615125463617024326 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_trace_timing1.out0000644000542200017500000000043615125463617022706 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module t $end $var wire 32 % CLOCK_CYCLE [31:0] $end $var wire 1 # rst $end $var wire 1 $ clk $end $upscope $end $enddefinitions $end #0 1# 0$ b00000000000000000000000000001010 % #5 1$ #10 0# 0$ #15 1$ #20 0$ verilator-5.044/test_regress/t/t_interface_typedef.py0000755000542200017500000000102515125463617023457 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.compile(verilator_flags2=['--binary']) if not test.vlt_all: test.execute() test.passes() verilator-5.044/test_regress/t/t_interface_generic_modport_task_bad.v0000644000542200017500000000117215125463617026644 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; int v; task setup(); v = 3; endtask modport mp( input v ); endinterface interface inf2; int k; endinterface module GenericModule (interface.mp a); initial begin a.setup(); end endmodule module t; inf inf_inst(); GenericModule genericModule (inf_inst); initial begin #1; if (inf_inst.v != 3) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_altera_lpm_counter.py0000755000542200017500000000114115125463617023655 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module, "--binary --no-timing"]) test.passes() verilator-5.044/test_regress/t/t_case_string2.v0000644000542200017500000000102115125463617022170 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; function automatic string broken_case(input string some_string); case(some_string) "alpha": return "alpha"; default: return "beta"; endcase endfunction initial begin $display(broken_case("gamma")); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_interface_param1.v0000644000542200017500000000172315125463617023017 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jie Xu. // SPDX-License-Identifier: CC0-1.0 //bug692 module t (/*AUTOARG*/ // Inputs clk ); input wire clk; wire [31:0] result; test_if #(.ID(3)) s(); sub_test U_SUB_TEST(s.a.b, result); // the line causing error endmodule : t // --------------------------------------------------------------------------- module sub_test ( input [31:0] b, output [31:0] c ); assign c = b; endmodule // --------------------------------------------------------------------------- interface test_if #(parameter ID = 0) (); typedef struct packed { logic a; logic [31:0] b; } aType; aType a; typedef struct packed { logic c; logic [31:0] d; } bType; bType b; modport master (input a, output b); endinterface verilator-5.044/test_regress/t/t_typedef_fwd_class.py0000755000542200017500000000073415125463617023472 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_interface_generic_mod_param.v0000644000542200017500000000105315125463617025265 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; int v; endinterface module GenericModule#(type T, type Y = int) (interface a); initial begin #1; if (a.v != 7) $stop; end endmodule module t; inf inf_inst(); GenericModule #(string) genericModule (inf_inst); initial begin inf_inst.v = 7; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_class_param_func_return.py0000755000542200017500000000073415125463617024704 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_foreach_noivar_bad.out0000644000542200017500000000124515125463617023752 0ustar mahmoudyfreeshell%Warning-NOEFFECT: t/t_foreach_noivar.v:19:5: foreach with no loop variable has no effect : ... note: In instance 't' 19 | foreach (array[]) begin | ^~~~~~~ ... For warning description see https://verilator.org/warn/NOEFFECT?v=latest ... Use "/* verilator lint_off NOEFFECT */" and lint_on around source to disable this message. %Warning-NOEFFECT: t/t_foreach_noivar.v:25:5: foreach with no loop variable has no effect : ... note: In instance 't' 25 | foreach (array[,,]) begin | ^~~~~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_clk_gater.v0000644000542200017500000000732615125463617021556 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; reg reset; reg enable; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] out; // From test of Test.v // End of automatics // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; Test test (/*AUTOINST*/ // Outputs .out (out[31:0]), // Inputs .clk (clk), .reset (reset), .enable (enable), .in (in[31:0])); wire [63:0] result = {32'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; reset <= (cyc < 5); enable <= cyc[4] || (cyc < 2); if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; `define EXPECTED_SUM 64'h01e1553da1dcf3af if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs clk, reset, enable, in ); input clk; input reset; input enable; input [31:0] in; output [31:0] out; // No gating reg [31:0] d10; always @(posedge clk) begin d10 <= in; end reg displayit; `ifdef VERILATOR // Harder test initial displayit = $c1("0"); // Something that won't optimize away `else initial displayit = '0; `endif // Obvious gating + PLI reg [31:0] d20; always @(posedge clk) begin if (enable) begin d20 <= d10; // Obvious gating if (displayit) begin $display("hello!"); // Must glob with other PLI statements end end end // Reset means second-level gating reg [31:0] d30, d31a, d31b, d32; always @(posedge clk) begin d32 <= d31b; if (reset) begin d30 <= 32'h0; d31a <= 32'h0; d31b <= 32'h0; d32 <= 32'h0; // Overlaps above, just to make things interesting end else begin // Mix two outputs d30 <= d20; if (enable) begin d31a <= d30; d31b <= d31a; end end end // Multiple ORs for gater reg [31:0] d40a,d40b; always @(posedge clk) begin if (reset) begin d40a <= 32'h0; d40b <= 32'h0; end if (enable) begin d40a <= d32; d40b <= d40a; end end // Non-optimizable reg [31:0] d91, d92; reg [31:0] inverted; always @(posedge clk) begin inverted = ~d40b; if (reset) begin d91 <= 32'h0; end else begin if (enable) begin d91 <= inverted; end else begin d92 <= inverted ^ 32'h12341234; // Inverted gating condition end end end wire [31:0] out = d91 ^ d92; endmodule verilator-5.044/test_regress/t/t_waiveroutput_allgood.out0000644000542200017500000000056315125463617024440 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator output: Waivers generated with --waiver-output `verilator_config // Below are suggested waivers. You have three options: // 1. Fix the reason for the linter warning in the Verilog sources // 2. Keep the waiver permanently if you are sure it is okay // 3. Keep the waiver temporarily to suppress the output // No waivers needed - great! verilator-5.044/test_regress/t/t_lint_noreturn.v0000644000542200017500000000065115125463617022517 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // verilator lint_off UNDRIVEN function int no_rtn(); // <--- Warning: No return endfunction int i; initial begin i = no_rtn(); if (i !== 0) $stop; $finish; end endmodule verilator-5.044/test_regress/t/t_var_pins_sc32.py0000755000542200017500000000473315125463617022463 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" test.compile(verilator_flags2=[ "-sc -no-pins64 --trace-vcd --exe", test.pli_filename, test.t_dir + "/t_var_pinsizes.vlt" ], make_main=False) def hgrep(re): test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) hgrep(r'sc_core::sc_in\s+&i1;') hgrep(r'sc_core::sc_in\s+&i8;') hgrep(r'sc_core::sc_in\s+&i16;') hgrep(r'sc_core::sc_in\s+&i32;') hgrep(r'sc_core::sc_in\s>\s+&i64;') hgrep(r'sc_core::sc_in\s>\s+&i65;') hgrep(r'sc_core::sc_in\s>\s+&ibv1;') hgrep(r'sc_core::sc_in\s>\s+&ibv16;') hgrep(r'sc_core::sc_in\s>\s+&ibv1_vlt;') hgrep(r'sc_core::sc_in\s>\s+&ibv16_vlt;') hgrep(r'sc_core::sc_out\s+&o1;') hgrep(r'sc_core::sc_out\s+&o8;') hgrep(r'sc_core::sc_out\s+&o16;') hgrep(r'sc_core::sc_out\s+&o32;') hgrep(r'sc_core::sc_out\s>\s+&o64;') hgrep(r'sc_core::sc_out\s>\s+&o65;') hgrep(r'sc_core::sc_out\s>\s+&obv1;') hgrep(r'sc_core::sc_out\s>\s+&obv16;') hgrep(r'sc_core::sc_out\s>\s+&obv1_vlt;') hgrep(r'sc_core::sc_out\s>\s+&obv16_vlt;') # sc_biguint pragma overrides `-pins-bv 32` flag hgrep(r'sc_core::sc_in\s>\s+&ibu64;') hgrep(r'sc_core::sc_in\s>\s+&ibu512;') hgrep(r'sc_core::sc_in\s>\s+&ibu1_vlt;') hgrep(r'sc_core::sc_in\s>\s+&ibu16_vlt;') hgrep(r'sc_core::sc_out\s>\s+&obu1;') hgrep(r'sc_core::sc_out\s>\s+&obu8;') hgrep(r'sc_core::sc_out\s>\s+&obu16;') hgrep(r'sc_core::sc_out\s>\s+&obu64;') hgrep(r'sc_core::sc_out\s>\s+&obu512;') hgrep(r'sc_core::sc_out\s>\s+&obu1_vlt;') hgrep(r'sc_core::sc_out\s>\s+&obu16_vlt;') test.execute() test.passes() verilator-5.044/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg.py0000755000542200017500000000077115125463617027700 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_dpi_accessors.v0000644000542200017500000000453115125463617022437 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test for using DPI as general accessors // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // // Contributed by Jeremy Bennett and Jie Xul // // This test exercises the use of DPI to access signals and registers in a // module hierarchy in a uniform fashion. See the discussion at // // https://github.com/verilator/verilator/issues/1750 // // We need to test read and write access to: // - scalars // - vectors // - array elements // - slices of vectors or array elements // // We need to test that writing to non-writable elements generates an error. // // This Verilog would run forever. It will be stopped externally by the C++ // instantiating program. // Define the width of registers and size of memory we use `define REG_WIDTH 8 `define MEM_SIZE 256 // Top module defines the accessors and instantiates a sub-module with // substantive content. module t (/*AUTOARG*/ // Inputs clk ); input clk; `include "t_dpi_accessors_macros_inc.vh" `include "t_dpi_accessors_inc.vh" // Put the serious stuff in a sub-module, so we can check hierarchical // access works OK. test_sub i_test_sub (.clk (clk)); endmodule // t // A sub-module with all sorts of goodies we would like to access module test_sub (/*AUTOARG*/ // Inputs clk ); input clk; integer i; // General counter // Elements we would like to access from outside reg a; reg [`REG_WIDTH - 1:0] b; reg [`REG_WIDTH - 1:0] mem [`MEM_SIZE - 1:0]; wire c; wire [`REG_WIDTH - 1:0] d; reg [`REG_WIDTH - 1:0] e; reg [`REG_WIDTH - 1:0] f; // Drive our wires from our registers assign c = ~a; assign d = ~b; // Initial values for registers and array initial begin a = 0; b = `REG_WIDTH'h0; for (i = 0; i < `MEM_SIZE; i++) begin mem[i] = i [`REG_WIDTH - 1:0]; end e = 0; f = 0; end // Wipe out one memory cell in turn on the positive clock edge, restoring // the previous element. We toggle the wipeout value. always @(posedge clk) begin mem[b] <= {`REG_WIDTH {a}}; mem[b - 1] <= b - 1; a <= ~a; b <= b + 1; end endmodule // test_sub verilator-5.044/test_regress/t/t_case_write1.py0000755000542200017500000000117115125463617022207 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.priority(50) test.scenarios('simulator') test.compile(verilator_flags2=["--stats -O3 -x-assign fast"]) test.execute() test.files_identical(test.obj_dir + "/" + test.name + "_logger.log", test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_var_static_assign_decl_bad.v0000644000542200017500000000562115125463617025117 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 function static func_stat; input logic in; logic tmp = in; endfunction task static task_stat; input logic in; logic tmp = in; endtask package pkg; function static func_stat; input logic in; logic tmp = in; endfunction task static task_stat; input logic in; logic tmp = in; endtask endpackage interface iface; function static func_stat; input logic in; logic tmp = in; endfunction task static task_stat; input logic in; logic tmp = in; endtask endinterface program prog; function static func_stat; input logic in; logic tmp = in; endfunction task static task_stat; input logic in; logic tmp = in; endtask endprogram module no_warn#(PARAM = 1)(input in, input clk); typedef enum {A, B} enum_t; // Do not warn on variables under modules. logic tmp = in; // Do not warn on assignment with module var. function static func; static logic func_var = tmp; endfunction // Do not warn on constant assignments. function static func_param; static logic func_var = PARAM; static logic func_enum = A; endfunction // Do not warn on assignment referencing module I/O. function static func_module_input; logic tmp = in; endfunction // Do not warn on automatic assignment. function automatic func_auto; input logic in; logic tmp = in; endfunction // Do not warn on assignment separate from declaration. function static func_decl_and_assign; input logic in; logic tmp; tmp = in; endfunction // Do not warn on variables under blocks. initial begin logic init_tmp = in; end always @(posedge clk) begin static logic always_tmp = in; end endmodule module t(input clk); function static func_stat; input logic in; logic tmp = in; endfunction task static task_stat; input logic in; logic tmp = in; endtask function automatic func_auto_with_static; input logic in; static logic tmp = in; endfunction function static func_assign_out; output logic out; logic tmp = out; endfunction function static func_assign_expr; input logic in; logic tmp = in + 1; endfunction function static int func_assign_static_in_to_auto(input int i); automatic int tmp = i; static int foo = tmp + 1; return foo; endfunction function static int func_assign_auto_to_static(); automatic int tmp = 0; static int foo = tmp + 1; return foo; endfunction function static func_local; automatic logic loc; static logic func_var = loc; endfunction iface iface(); prog prog(); logic in; no_warn no_warn(.in(in), .clk(clk)); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_sys_plusargs.v0000644000542200017500000000747115125463617022362 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; integer p_i; // signal type IData reg [15:0] p_s; // signal type SData reg [7:0] p_c; // signal type CData real p_r; // signal type double reg [7*8:1] p_str; string sv_str; reg [7*8:1] p_in; string sv_in; integer unread; // never read initial begin if ($test$plusargs("PLUS")!==1) $stop; if ($test$plusargs("PLUSNOT")!==0) $stop; if ($test$plusargs("PL")!==1) $stop; //if ($test$plusargs("")!==1) $stop; // Simulators differ in this answer if ($test$plusargs("NOTTHERE")!==0) $stop; sv_in = "PLUS"; `ifdef VERILATOR if ($c1(0)) sv_in = "NEVER"; // Prevent constant propagation `endif if ($test$plusargs(sv_in)!==1) $stop; p_i = 10; if ($value$plusargs("NOTTHERE%d", p_i) !== 0) $stop; if ($value$plusargs("NOTTHERE%0d", p_i) !== 0) $stop; if (p_i !== 10) $stop; p_i = 0; if ($value$plusargs("INT=%d", p_i) !== 1) $stop; if (p_i !== 32'd1234) $stop; p_i = 0; if ($value$plusargs("INT=%0d", p_i) !== 1) $stop; if (p_i !== 32'd1234) $stop; p_i = 0; if ($value$plusargs("INT=%H", p_i)!==1) $stop; // tests uppercase % also if (p_i !== 32'h1234) $stop; p_i = 0; // Check octal and WIDTH if (!$value$plusargs("INT=%o", p_i)) $stop; if (p_i !== 32'o1234) $stop; // Check handling of 'SData' type signals (issue #1592) p_s = 0; if (!$value$plusargs("INT=%d", p_s)) $stop; if (p_s !== 16'd1234) $stop; // Check handling of 'CData' type signals (issue #1592) p_c = 0; if (!$value$plusargs("INT=%d", p_c)) $stop; if (p_c !== 8'd210) $stop; // Check handling of 'double' type signals (issue #1619) p_r = 0; if (!$value$plusargs("REAL=%e", p_r)) $stop; $display("r='%e'", p_r); if (p_r !== 1.2345) $stop; p_r = 0; if (!$value$plusargs("REAL=%f", p_r)) $stop; $display("r='%f'", p_r); if (p_r !== 1.2345) $stop; p_r = 0; if (!$value$plusargs("REAL=%g", p_r)) $stop; $display("r='%g'", p_r); if (p_r !== 1.2345) $stop; p_str = "none"; if ($value$plusargs("IN%s", p_str)!==1) $stop; $display("str='%s'",p_str); if (p_str !== "T=1234") $stop; sv_str = "none"; if ($value$plusargs("IN%s", sv_str)!==1) $stop; $display("str='%s'",sv_str); if (sv_str != "T=1234") $stop; sv_str = "none"; $value$plusargs("IN%s", sv_str); $display("str='%s'",sv_str); if (sv_str != "T=1234") $stop; p_in = "IN%s"; `ifdef VERILATOR p_in = $c(p_in); // Prevent constant propagation `endif sv_str = "none"; if ($value$plusargs(p_in, sv_str)!==1) $stop; $display("str='%s'",sv_str); if (sv_str != "T=1234") $stop; sv_str = "none"; if ($value$plusargs("IP%%P%b", p_i)!==1) $stop; $display("str='%s'",sv_str); if (p_i != 'b101) $stop; sv_in = "INT=%d"; `ifdef VERILATOR if ($c1(0)) sv_in = "NEVER"; // Prevent constant propagation `endif p_i = 0; if ($value$plusargs(sv_in, p_i)!==1) $stop; $display("i='%d'",p_i); if (p_i !== 32'd1234) $stop; // bug3131 - really "if" side effect test p_i = 0; if ($value$plusargs("INT=%d", p_i)) ; if (p_i !== 32'd1234) $stop; // bug5127 - assign side effect test p_i = 0; p_r = 0; unread = $value$plusargs("INT=%d", p_i); unread = $value$plusargs("REAL=%e", p_r); if (p_i !== 32'd1234) $stop; if (p_r !== 1.2345) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_lint_badvltpragma_bad.v0000644000542200017500000000047315125463617024117 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // verilator lintt_off WIDTH //<--- Warning (lint_off misspelled) bit one = 2; endmodule verilator-5.044/test_regress/t/t_order_clkinst.py0000755000542200017500000000142315125463617022643 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') # On Verilator, we expect this to pass. # # TBD: Will event-based simulators match Verilator's behavior # closely enough to pass the same test? # If not -- probably we should switch this to be vlt-only. test.compile(verilator_flags2=["--trace-vcd", "-fno-dfg"]) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_trace_complex_threads_1.py0000755000542200017500000000220715125463617024561 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_complex.v" test.golden_filename = "t/t_trace_complex.out" test.compile(verilator_flags2=['--cc --trace-vcd --trace-threads 1']) test.execute() test.file_grep(test.trace_filename, r' v_strp ') test.file_grep(test.trace_filename, r' v_strp_strp ') test.file_grep(test.trace_filename, r' v_arrp ') test.file_grep(test.trace_filename, r' v_arrp_arrp ') test.file_grep(test.trace_filename, r' v_arrp_strp ') test.file_grep(test.trace_filename, r' v_arru\[') test.file_grep(test.trace_filename, r' v_arru_arru\[') test.file_grep(test.trace_filename, r' v_arru_arrp\[') test.file_grep(test.trace_filename, r' v_arru_strp\[') test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_enum_int.py0000755000542200017500000000103615125463617021617 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--debug", "--debugi", "0", "--dumpi-tree", "0"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_forceable_var.v0000644000542200017500000000466615125463617022421 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t ( input wire clk, input wire rst, output reg [31:0] cyc ); always @(posedge clk) begin if (rst) begin cyc <= 0; end else begin cyc <= cyc +1; end end reg tmp_1; reg [7:0] tmp_8; always @(posedge clk) begin if (rst) begin tmp_1 <= 0; tmp_8 <= 0; end else begin tmp_1 <= cyc[0]; tmp_8 <= cyc[1 +: 8]; end end `ifdef CMT reg var_1 /* verilator forceable */; reg [7:0] var_8 /* verilator forceable */; `else reg var_1; reg [7:0] var_8; `endif always @* var_1 = tmp_1; always @* var_8 = tmp_8; reg obs_1; reg [7:0] obs_8; always @* obs_1 = var_1; always @* obs_8 = var_8; always @ (posedge clk) begin $display("%d: %x %x", cyc, obs_8, obs_1); if (!rst) begin case (cyc) 0: begin // Reset values `checkh (obs_1, 0); `checkh (obs_8, 0); end 13: begin `checkh (obs_1, 1); `checkh ({1'b0, obs_8}, (cyc[0 +: 9] - 1) >> 1); end 14: begin `checkh (obs_1, 1); `checkh (obs_8, 8'hf5); end 15: begin `checkh (obs_1, 0); `checkh (obs_8, 8'hf5); end 16, 17: begin `checkh (obs_1, 0); `checkh (obs_8, 8'h5f); end 18: begin `checkh (obs_1, ~cyc[0]); `checkh (obs_8, 8'h5f); end 20, 21: begin `checkh (obs_1, 1); `checkh (obs_8, 8'h5a); end 22, 23: begin `checkh (obs_1, 0); `checkh (obs_8, 8'ha5); end default: begin `checkh ({obs_8, obs_1}, cyc[0 +: 9] - 1); end endcase end if (cyc == 30) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.044/test_regress/t/t_time_sc_bad_mt.py0000755000542200017500000000135315125463617022734 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vltmt') test.top_filename = "t/t_time_sc.v" test.sc_time_resolution = 'SC_NS' test.compile( verilator_flags2=[ '-sc', '-timescale 1ps/1ps', # Mismatch w/sc_time_resolution '+define+TEST_EXPECT=2us' ], threads=2) test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_flag_unroll_limit_gen.v0000644000542200017500000000065115125463617024150 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; for (genvar i = 0; i < 4; ++i) begin initial $display("Should unroll: %0d", i); end for (genvar i = 0; i < 5; ++i) begin initial $display("Should NOT unroll: %0d", i); end endmodule verilator-5.044/test_regress/t/t_func_dotted_inl2.vlt0000644000542200017500000000047015125463617023376 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config inline -module "global_mod" inline -module "ma" no_inline -module "mb" inline -module "mc" verilator-5.044/test_regress/t/t_dump_dfg.py0000755000542200017500000000116315125463617021567 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') # For code coverage of graph dumping, so does not matter much what the input is test.top_filename = "t/t_benchmark_mux4k.v" test.compile(verilator_flags2=["--dump-dfg", "--dumpi-dfg 9"]) test.passes() verilator-5.044/test_regress/t/t_flag_build_jobs_bad.py0000755000542200017500000000114115125463617023711 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_flag_werror.v" test.lint(fails=True, verilator_flags=["--cc --build-jobs -1 --build"], expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_vlt_warn_bad.out0000644000542200017500000000104315125463617022615 0ustar mahmoudyfreeshell%Warning-WIDTHTRUNC: t/t_vlt_warn.v:20:33: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '2'h3' generates 2 bits. : ... note: In instance 't' 20 | reg width_warn3_var_line20 = 2'b11; | ^~~~~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.044/test_regress/t/t_timing_func_fork_bad.py0000755000542200017500000000110415125463617024126 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(fails=True, verilator_flags2=["--binary -Wno-UNOPTFLAT"], expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_fork_label.v0000644000542200017500000000131315125463617021711 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin // Label checks begin : b1 end : b1 // b2 : begin end : b2 // With no statements this is a NOP fork : f1 join : f1 // f2: fork join_any : f2 // fork join_none // With one statement this is supported and optimized to a begin/end fork : fblk begin $write("*-* All Finished *-*\n"); $finish; end join : fblk end endmodule verilator-5.044/test_regress/t/t_sv_bus_mux_demux.v0000644000542200017500000001644215125463617023216 0ustar mahmoudyfreeshell//////////////////////////////////////////////////////////////////////////////// // // // This file is placed into the Public Domain, for any use, without warranty. // // 2012 by Iztok Jeras // // SPDX-License-Identifier: CC0-1.0 // // // //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // // // This testbench contains a bus source and a bus drain. The source creates // // address and data bus values, while the drain is the final destination of // // such pairs. All source and drain transfers are logged into memories, which // // are used at the end of simulation to check for data transfer correctness. // // Inside the RLT wrapper there is a multiplexer and a demultiplexer, they // // bus transfers into a 8bit data stream and back. Both stream input and // // output are exposed, they are connected together into a loopback. // // // // ----------- --------------------- // // | bso_mem | | wrap | // // ----------- | | // // ----------- | | ----------- | // // | bsi src | ------------> | -> | mux | -> | -> - sto // // ----------- | ----------- | \ // // | | | loopback // // ----------- | ----------- | / // // | bso drn | <------------ | <- | demux | <- | <- - sti // // ----------- | | ----------- | // // ----------- | | // // | bso_mem | | | // // ----------- --------------------- // // // // PROTOCOL: // // // // The 'vld' signal is driven by the source to indicate valid data is // // available, 'rdy' is used by the drain to indicate is is ready to accept // // valid data. A data transfer only happens if both 'vld' & 'rdy' are active. // // // //////////////////////////////////////////////////////////////////////////////// `timescale 1ns/1ps // include RTL files `include "t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv" `include "t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv" `include "t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv" `include "t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv" module t (/*AUTOARG*/ // Inputs clk ); input clk; parameter SIZ = 10; // system signals //logic clk = 1'b1; // clock logic rst = 1'b1; // reset integer rst_cnt = 0; // input bus logic bsi_vld; // valid (chip select) logic [31:0] bsi_adr; // address logic [31:0] bsi_dat; // data logic bsi_rdy; // ready (acknowledge) logic bsi_trn; // data transfer logic [31:0] bsi_mem [SIZ]; // output stream logic sto_vld; // valid (chip select) logic [7:0] sto_bus; // data bus logic sto_rdy; // ready (acknowledge) // input stream logic sti_vld; // valid (chip select) logic [7:0] sti_bus; // data bus logic sti_rdy; // ready (acknowledge) // output bus logic bso_vld; // valid (chip select) logic [31:0] bso_adr; // address logic [31:0] bso_dat; // data logic bso_rdy; // ready (acknowledge) logic bso_trn; // data transfer logic [31:0] bso_mem [SIZ]; integer bso_cnt = 0; //////////////////////////////////////////////////////////////////////////////// // clock and reset //////////////////////////////////////////////////////////////////////////////// // clock toggling //always #5 clk = ~clk; // reset is removed after a delay always @ (posedge clk) begin rst_cnt <= rst_cnt + 1; rst <= rst_cnt <= 3; end // reset is removed after a delay always @ (posedge clk) if (bso_cnt == SIZ) begin if (bsi_mem === bso_mem) begin $write("*-* All Finished *-*\n"); $finish(); end else begin $display ("FAILED"); $stop(); end end //////////////////////////////////////////////////////////////////////////////// // input data generator //////////////////////////////////////////////////////////////////////////////// // input data transfer assign bsi_trn = bsi_vld & bsi_rdy; // valid (for SIZ transfers) always @ (posedge clk, posedge rst) if (rst) bsi_vld = 1'b0; else bsi_vld = (bsi_adr < SIZ); // address (increments every transfer) always @ (posedge clk, posedge rst) if (rst) bsi_adr <= 32'h00000000; else if (bsi_trn) bsi_adr <= bsi_adr + 'd1; // data (new random value generated after every transfer) always @ (posedge clk, posedge rst) if (rst) bsi_dat <= 32'h00000000; else if (bsi_trn) bsi_dat <= $random(); // storing transferred data into memory for final check always @ (posedge clk) if (bsi_trn) bsi_mem [bsi_adr] <= bsi_dat; //////////////////////////////////////////////////////////////////////////////// // RTL instance //////////////////////////////////////////////////////////////////////////////// sv_bus_mux_demux_wrap wrap ( // system signals .clk (clk), .rst (rst), // input bus .bsi_vld (bsi_vld), .bsi_adr (bsi_adr), .bsi_dat (bsi_dat), .bsi_rdy (bsi_rdy), // output stream .sto_vld (sto_vld), .sto_bus (sto_bus), .sto_rdy (sto_rdy), // input stream .sti_vld (sti_vld), .sti_bus (sti_bus), .sti_rdy (sti_rdy), // output bus .bso_vld (bso_vld), .bso_adr (bso_adr), .bso_dat (bso_dat), .bso_rdy (bso_rdy) ); // stream output from mux is looped back into stream input for demux assign sti_vld = sto_vld; assign sti_bus = sto_bus; assign sto_rdy = sti_rdy; //////////////////////////////////////////////////////////////////////////////// // output data monitor //////////////////////////////////////////////////////////////////////////////// // input data transfer assign bso_trn = bso_vld & bso_rdy; // output transfer counter used to end the test always @ (posedge clk, posedge rst) if (rst) bso_cnt <= 0; else if (bso_trn) bso_cnt <= bso_cnt + 1; // storing transferred data into memory for final check always @ (posedge clk) if (bso_trn) bso_mem [bso_adr] <= bso_dat; // every output transfer against expected value stored in memory always @ (posedge clk) if (bso_trn && (bsi_mem [bso_adr] !== bso_dat)) $display ("@%08h i:%08h o:%08h", bso_adr, bsi_mem [bso_adr], bso_dat); // ready is active for SIZ transfers always @ (posedge clk, posedge rst) if (rst) bso_rdy = 1'b0; else bso_rdy = 1'b1; endmodule verilator-5.044/test_regress/t/t_flag_threads_dpi_bad.out0000644000542200017500000000033615125463617024244 0ustar mahmoudyfreeshell%Error: Unknown setting for --threads-dpi: 'bad_one' ... Suggest 'all', 'none', or 'pure' ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_func_task_bad2.out0000644000542200017500000000124515125463617023024 0ustar mahmoudyfreeshell%Error-FUNCTIMECTL: t/t_func_task_bad2.v:14:5: Functions cannot invoke tasks (IEEE 1800-2023 13.4) : ... note: In instance 't' 14 | a_task(1'b0); | ^~~~~~ : ... Suggest make caller 'function func_calls_task' a task 13 | function void func_calls_task; | ^~~~~~~~~~~~~~~ : ... Or, suggest make called 'task a_task' a function void 9 | task a_task; | ^~~~~~ ... For error description see https://verilator.org/warn/FUNCTIMECTL?v=latest %Error: Exiting due to verilator-5.044/test_regress/t/t_vpi_package.cpp0000644000542200017500000001476015125463617022411 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #ifdef IS_VPI #include "sv_vpi_user.h" #include #else #include "verilated.h" #include "verilated_vcd_c.h" #include "verilated_vpi.h" #include "Vt_vpi_package.h" #include "Vt_vpi_package__Dpi.h" #include "svdpi.h" #endif #include #include #include // These require the above. Comment prevents clang-format moving them #include "TestSimulator.h" #include "TestVpi.h" extern "C" { int count_params(TestVpiHandle& handle, int expectedParams) { TestVpiHandle it = vpi_iterate(vpiParameter, handle); CHECK_RESULT_NZ(it) int params = 0; while (true) { TestVpiHandle handle = vpi_scan(it); if (!handle) break; const int vpi_type = vpi_get(vpiType, handle); CHECK_RESULT(vpi_type, vpiParameter); params++; } it.freed(); CHECK_RESULT(params, expectedParams); return 0; } int check_handle(char* name, vpiHandle scopeHandle) { const TestVpiHandle handle = vpi_handle_by_name(name, scopeHandle); CHECK_RESULT_NZ(handle) return 0; } int mon_check() { #ifdef TEST_VERBOSE printf("-mon_check()\n"); #endif TestVpiHandle it = vpi_iterate(vpiModule, NULL); CHECK_RESULT_NZ(it) bool found_t = false; while (true) { TestVpiHandle handle = vpi_scan(it); if (handle == NULL) break; CHECK_RESULT_CSTR("t", vpi_get_str(vpiName, handle)) CHECK_RESULT_Z(found_t) found_t = true; } it.freed(); CHECK_RESULT_NZ(found_t); it = vpi_iterate(vpiInstance, NULL); CHECK_RESULT_NZ(it) TestVpiHandle pkgHandle = NULL; TestVpiHandle tHandle = NULL; TestVpiHandle unitHandle = NULL; while (true) { TestVpiHandle handle = vpi_scan(it); if (handle == NULL) break; const char* name = vpi_get_str(vpiName, handle); const char* fullname = vpi_get_str(vpiFullName, handle); if (!strcmp("t", name)) { CHECK_RESULT_CSTR("t", fullname) CHECK_RESULT_Z(tHandle) tHandle = handle; handle.freed(); } else if (!strcmp("somepackage", name)) { CHECK_RESULT_CSTR("somepackage::", fullname) CHECK_RESULT_Z(pkgHandle) pkgHandle = handle; handle.freed(); } else if (!strcmp("$unit", name)) { CHECK_RESULT_CSTR("$unit::", fullname) CHECK_RESULT_Z(unitHandle) unitHandle = handle; handle.freed(); } else { CHECK_RESULT_NZ(0) } } it.freed(); CHECK_RESULT_NZ(pkgHandle) CHECK_RESULT_NZ(tHandle) CHECK_RESULT_NZ(unitHandle) CHECK_RESULT_Z(count_params(unitHandle, 1)); CHECK_RESULT_Z(count_params(pkgHandle, 2)); CHECK_RESULT_Z(count_params(tHandle, 6)); CHECK_RESULT_Z(check_handle(const_cast("someOtherInt"), tHandle)) CHECK_RESULT_Z(check_handle(const_cast("t.someOtherInt"), NULL)) CHECK_RESULT_Z(check_handle(const_cast("$root.t.someOtherInt"), NULL)) CHECK_RESULT_Z(check_handle(const_cast("someString"), tHandle)) CHECK_RESULT_Z(check_handle(const_cast("t.someString"), NULL)) CHECK_RESULT_Z(check_handle(const_cast("someInt"), pkgHandle)) CHECK_RESULT_Z(check_handle(const_cast("somepackage::someInt"), NULL)) CHECK_RESULT_Z(check_handle(const_cast("dollarUnitInt"), unitHandle)) CHECK_RESULT_Z(check_handle(const_cast("$unit::dollarUnitInt"), NULL)) CHECK_RESULT_Z(check_handle(const_cast("somepackage"), NULL)) return 0; // Ok } } //====================================================================== #ifdef IS_VPI static int mon_check_vpi() { TestVpiHandle href = vpi_handle(vpiSysTfCall, 0); s_vpi_value vpi_value; vpi_value.format = vpiIntVal; vpi_value.value.integer = mon_check(); vpi_put_value(href, &vpi_value, NULL, vpiNoDelay); return 0; } static s_vpi_systf_data vpi_systf_data[] = {{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$mon_check", (PLI_INT32(*)(PLI_BYTE8*))mon_check_vpi, 0, 0, 0}, 0}; // cver entry void vpi_compat_bootstrap(void) { p_vpi_systf_data systf_data_p; systf_data_p = &(vpi_systf_data[0]); while (systf_data_p->type != 0) vpi_register_systf(systf_data_p++); } // icarus entry void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; #else int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; uint64_t sim_time = 1100; contextp->debug(0); contextp->commandArgs(argc, argv); // We're going to be checking for these errors so don't crash out contextp->fatalOnVpiError(0); { // Construct and destroy const std::unique_ptr topp{ new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; } // Test second construction const std::unique_ptr topp{new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; #ifdef VERILATOR #ifdef TEST_VERBOSE contextp->scopesDump(); #endif #endif #if VM_TRACE contextp->traceEverOn(true); VL_PRINTF("Enabling waves...\n"); VerilatedVcdC* tfp = new VerilatedVcdC; topp->trace(tfp, 99); tfp->open(STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); #endif topp->eval(); contextp->timeInc(10); while (contextp->time() < sim_time && !contextp->gotFinish()) { contextp->timeInc(1); topp->eval(); VerilatedVpi::callValueCbs(); // mon_do(); #if VM_TRACE if (tfp) tfp->dump(contextp->time()); #endif } if (!contextp->gotFinish()) { vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); #if VM_TRACE if (tfp) tfp->close(); #endif return 0; } #endif verilator-5.044/test_regress/t/t_case_group.v0000644000542200017500000000103615125463617021742 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jonathon Donaldson. // SPDX-License-Identifier: CC0-1.0 module t ( input i_clk, input [6:0] i_input, output logic o_output ); always_ff @(posedge i_clk) // verilator lint_off CASEINCOMPLETE case (i_input) 7'(92+2), 7'(92+3): o_output <= 1'b1; endcase initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_trace_off_cc.py0000755000542200017500000000121115125463617022371 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_ena.v" test.compile(verilator_flags2=['-notrace']) test.execute() if test.vlt_all: if os.path.exists(test.trace_filename): test.error("Tracing should be off") test.passes() verilator-5.044/test_regress/t/t_detectarray_3.py0000755000542200017500000000103115125463617022525 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-Wno-UNOPTFLAT", "-Wno-WIDTH", "-fno-dfg"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_interface_param_genblk.py0000755000542200017500000000075215125463617024447 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_lint_latch_4.v0000644000542200017500000000134215125463617022157 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for issue #2938 // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2021 by Julien Margetts (Originally provided by YanJiun) // SPDX-License-Identifier: Unlicense module test ( input [2:0] a, input [3:0] c, output reg [7:0] o1, output reg [7:0] o2 ); integer i; always @ (*) begin case(a) {3'b000}: o1 = 8'd1; {3'b001}: for(i=0;i<4;i=i+1) o1[i*2+:2] = 2'(c[i]); {3'b010}: o1 = 8'd3; {3'b011}: o1 = 8'd4; default : o1 = 0; endcase end always_comb begin unique if (a[0]) o2 = 1; else if (a[1]) o2 = 2; else o2 = 3; end endmodule verilator-5.044/test_regress/t/t_interface_param_another_bad.py0000755000542200017500000000076615125463617025460 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_trace_cat.cpp0000644000542200017500000000343415125463617022061 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include #include #include VM_PREFIX_INCLUDE #include "TestCheck.h" int errors = 0; unsigned long long main_time = 0; double sc_time_stamp() { return (double)main_time; } const char* trace_name() { static char name[1000]; VL_SNPRINTF(name, 1000, VL_STRINGIFY(TEST_OBJ_DIR) "/simpart_%04d.vcd", (int)main_time); return name; } int main(int argc, char** argv) { Verilated::debug(0); Verilated::traceEverOn(true); Verilated::commandArgs(argc, argv); std::unique_ptr top{new VM_PREFIX{"top"}}; std::unique_ptr tfp{new VerilatedVcdC}; top->trace(tfp.get(), 99); // Test for traceCapable - randomly-ish selected this test TEST_CHECK_EQ(top->traceCapable, true); tfp->open(trace_name()); top->clk = 0; while (main_time < 190) { // Creates 2 files top->clk = !top->clk; top->eval(); if ((main_time % 100) == 0) { #if defined(T_TRACE_CAT) tfp->openNext(true); #elif defined(T_TRACE_CAT_REOPEN) tfp->close(); tfp->open(trace_name()); #elif defined(T_TRACE_CAT_RENEW) tfp->close(); tfp.reset(new VerilatedVcdC); top->trace(tfp.get(), 99); tfp->open(trace_name()); #else #error "Unknown test" #endif } tfp->dump((unsigned int)(main_time)); ++main_time; } tfp->close(); top->final(); tfp.reset(); top.reset(); printf("*-* All Finished *-*\n"); return errors; } verilator-5.044/test_regress/t/t_randomize_method_bad.v0000644000542200017500000000066515125463617023760 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls1; function int randomize; return 1; endfunction endclass class Cls2; function void randomize(int x); endfunction function void srandom(int seed); endfunction endclass module t; endmodule verilator-5.044/test_regress/t/t_profc.py0000755000542200017500000000273315125463617021117 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap import platform test.scenarios('vlt') test.top_filename = "t_prof.v" if re.search(r'clang', test.cxx_version) and 'aarch64' in platform.processor(): test.skip("Known compiler profile issues on clang aarch64") if platform.libc_ver()[0] != "glibc": test.skip("The test depends on GMON_OUT_PREFIX which is glibc-specific") test.compile(verilator_flags2=["--stats --prof-c +define+T_PROF"]) # TODO below might no longer be required as configure checks for -pg if 'VERILATOR_TEST_NO_GPROF' in os.environ: test.skip("Skipping due to VERILATOR_TEST_NO_GPROF") for filename in glob.glob(test.obj_dir + "/gmon.out.*"): test.unlink_ok(filename) test.setenv('GMON_OUT_PREFIX', test.obj_dir + "/gmon.out") test.execute() gmon_path = None for filename in glob.glob(test.obj_dir + "/gmon.out.*"): gmon_path = filename if not gmon_path: test.error("Profiler did not create a gmon.out") gmon_base = re.sub(r'.*[/\\]', '', gmon_path) test.run( cmd=["cd " + test.obj_dir + " && gprof " + test.vm_prefix + " " + gmon_base + " > gprof.log"], check_finished=False) test.passes() verilator-5.044/test_regress/t/t_hierarchy_unnamed.v0000644000542200017500000000067615125463617023311 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Chandan Egbert. // SPDX-License-Identifier: CC0-1.0 module sub(); endmodule module t(input logic a, input logic b, output logic x, output logic y); always_comb begin integer i; x = a; end sub u0(); always_comb begin integer j; y = b; end endmodule verilator-5.044/test_regress/t/t_lint_unusedloop_removed_bad.py0000755000542200017500000000107015125463617025551 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename, verilator_flags2=["--top-module t", "-Wall"]) test.passes() verilator-5.044/test_regress/t/t_unpacked_concat.py0000755000542200017500000000073415125463617023126 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_hier_block_threads_bad.vlt0000644000542200017500000000046015125463617024574 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 `verilator_config hier_workers -module "Core" -workers `WORKERS hier_workers -module "SubCore" -workers `WORKERS verilator-5.044/test_regress/t/t_randomize_rand_mode_constr.v0000644000542200017500000000633415125463617025211 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Foo; rand int a; rand int b; endclass class Bar; rand int x; rand Foo foo; constraint x_gt_0 {x > 0;}; function new; foo = new; endfunction endclass class Qux extends Bar; rand int y; constraint y_gt_x {y > x;}; constraint y_lt_10 {y < 10;}; function bit get_rand_mode(); return bit'(y.rand_mode()); endfunction function void test; logic ok = 0; x.rand_mode(1); if (x.rand_mode != 1) $stop; // Note no rand_mode parens if (get_rand_mode() != 1) $stop; y.rand_mode(0); if (y.rand_mode() != 0) $stop; // Note has rand_mode parens foo.a.rand_mode(0); if (foo.a.rand_mode != 0) $stop; // Note no rand_mode parens foo.b.rand_mode(1); if (foo.b.rand_mode() != 1) $stop; // Note has rand_mode parens for (int i = 0; i < 20; ++i) begin x = 4; y = 8; foo.a = 15; foo.b = 16; void'(randomize()); if (x >= y) $stop; if (x != 4) ok = 1; if (y != 8) $stop; if (foo.a != 15) $stop; if (foo.b != 16) ok = 1; end if (!ok) $stop; foo.b = 16; foo.rand_mode(0); if (foo.rand_mode == 1) $stop; if (foo.a.rand_mode == 1) $stop; if (foo.b.rand_mode == 0) $stop; void'(randomize()); if (foo.a != 15) $stop; if (foo.b != 16) $stop; ok = 0; foo.rand_mode(1); if (foo.rand_mode == 0) $stop; for (int i = 0; i < 20; ++i) begin foo.a = 23; foo.b = 42; void'(randomize()); if (foo.a != 23) $stop; if (foo.b != 42) ok = 1; end if (!ok) $stop; endfunction endclass class Baz; Qux qux; function new(); qux = new; endfunction function void test; qux.x = 42; qux.rand_mode(0); if (qux.x.rand_mode == 1) $stop; void'(qux.randomize()); if (qux.x != 42) $stop; endfunction endclass class Quux; rand int x; endclass module t; initial begin logic ok = 0; int res; Baz baz = new; Qux qux = new; Quux quux = new; baz.test; qux.test; qux.x.rand_mode(0); if (qux.x.rand_mode == 1) $stop; qux.y.rand_mode(1); if (qux.y.rand_mode == 0) $stop; qux.foo.a.rand_mode(1); if (qux.foo.a.rand_mode == 0) $stop; qux.foo.b.rand_mode(0); if (qux.foo.b.rand_mode == 1) $stop; for (int i = 0; i < 20; ++i) begin qux.x = 5; qux.y = 8; qux.foo.a = 13; qux.foo.b = 21; res = qux.randomize() with {y > 5;}; if (qux.x >= qux.y) $stop; if (qux.y <= 5) $stop; if (qux.x != 5) $stop; if (qux.y != 8) ok = 1; if (qux.foo.a != 13) ok = 1; if (qux.foo.b != 21) $stop; end if (!ok) $stop; quux.x.rand_mode(0); quux.x = 1000; res = quux.randomize() with {x != 1000;}; if (quux.x != 1000) $stop; quux.rand_mode(1); res = quux.randomize() with {x != 1000;}; if (quux.x == 1000) $stop; qux.x = 1024; qux.y = 512; qux.rand_mode(0); if (qux.randomize() == 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_interface_parameter_access.v0000644000542200017500000001010515125463617025131 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Interface parameter getter // // A test of the import parameter used with modport // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader // SPDX-License-Identifier: CC0-1.0 interface test_if #(parameter integer FOO = 1); // Interface variable logic data; localparam integer BAR = FOO + 1; // Modport modport mp( import getFoo, output data ); function integer getFoo (); return FOO; endfunction endinterface // test_if function integer identity (input integer x); return x; endfunction module t (/*AUTOARG*/ // Inputs clk ); input clk; test_if #( .FOO (identity(5)) ) the_interface (); test_if #( .FOO (identity(7)) ) array_interface [1:0] (); testmod testmod_i (.clk (clk), .intf (the_interface), .intf_no_mp (the_interface), .intf_array (array_interface) ); // verilator lint_off HIERPARAM localparam THE_TOP_FOO = the_interface.FOO; localparam THE_TOP_FOO_BITS = $bits({the_interface.FOO, the_interface.FOO}); localparam THE_ARRAY_FOO = array_interface[0].FOO; // verilator lint_on HIERPARAM initial begin if (THE_TOP_FOO != 5) begin $display("%%Error: THE_TOP_FOO = %0d", THE_TOP_FOO); $stop; end if (THE_TOP_FOO_BITS != 64) begin $display("%%Error: THE_TOP_FOO_BITS = %0d", THE_TOP_FOO_BITS); $stop; end if (THE_ARRAY_FOO != 7) begin $display("%%Error: THE_ARRAY_FOO = %0d", THE_ARRAY_FOO); $stop; end end endmodule module testmod #(parameter SOME_PARAM = 789) ( input clk, test_if.mp intf, test_if intf_no_mp, test_if.mp intf_array [1:0] ); test_if #(.FOO (intf.FOO)) some_other_intf (); // verilator lint_off HIERPARAM localparam THE_FOO = intf.FOO; localparam THE_OTHER_FOO = intf_no_mp.FOO; localparam THE_ARRAY_FOO = intf_array[0].FOO; localparam THE_BAR = intf.BAR; localparam THE_OTHER_BAR = intf_no_mp.BAR; localparam THE_ARRAY_BAR = intf_array[0].BAR; // verilator lint_on HIERPARAM always @(posedge clk) begin if (THE_FOO != 5) begin $display("%%Error: THE_FOO = %0d", THE_FOO); $stop; end if (some_other_intf.FOO != 5) begin $display("%%Error: some_other_intf.FOO = %0d", some_other_intf.FOO); $stop; end if (THE_OTHER_FOO != 5) begin $display("%%Error: THE_OTHER_FOO = %0d", THE_OTHER_FOO); $stop; end if (THE_ARRAY_FOO != 7) begin $display("%%Error: THE_ARRAY_FOO = %0d", THE_ARRAY_FOO); $stop; end if (intf.FOO != 5) begin $display("%%Error: intf.FOO = %0d", intf.FOO); $stop; end if (intf_no_mp.FOO != 5) begin $display("%%Error: intf_no_mp.FOO = %0d", intf_no_mp.FOO); $stop; end if (intf_array[0].FOO != 7) begin $display("%%Error: intf_array[0].FOO = %0d", intf_array[0].FOO); $stop; end // if (i.getFoo() != 5) begin // $display("%%Error: i.getFoo() = %0d", i.getFoo()); // $stop; // end if (THE_BAR != 6) begin $display("%%Error: THE_BAR = %0d", THE_BAR); $stop; end if (THE_OTHER_BAR != 6) begin $display("%%Error: THE_OTHER_BAR = %0d", THE_OTHER_BAR); $stop; end if (THE_ARRAY_BAR != 8) begin $display("%%Error: THE_ARRAY_BAR = %0d", THE_ARRAY_BAR); $stop; end if (intf.BAR != 6) begin $display("%%Error: intf.BAR = %0d", intf.BAR); $stop; end if (intf_no_mp.BAR != 6) begin $display("%%Error: intf_no_mp.BAR = %0d", intf_no_mp.BAR); $stop; end if (intf_array[0].BAR != 8) begin $display("%%Error: intf_array[0].BAR = %0d", intf_array[0].BAR); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_constraint_global_arr_unsup.out0000644000542200017500000000317615125463617025766 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_constraint_global_arr_unsup.v:41:20: Unsupported: Array element access in global constraint 41 | m_mid.m_arr[0].m_x == 200; | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_constraint_global_arr_unsup.v:42:20: Unsupported: Array element access in global constraint 42 | m_mid.m_arr[0].m_y == 201; | ^~~ %Error-UNSUPPORTED: t/t_constraint_global_arr_unsup.v:47:24: Unsupported: Array element access in global constraint 47 | m_mid_arr[0].m_obj.m_x == 300; | ^~~ %Error-UNSUPPORTED: t/t_constraint_global_arr_unsup.v:47:18: Unsupported: Array element access in global constraint 47 | m_mid_arr[0].m_obj.m_x == 300; | ^~~~~ %Error-UNSUPPORTED: t/t_constraint_global_arr_unsup.v:48:24: Unsupported: Array element access in global constraint 48 | m_mid_arr[0].m_obj.m_y == 301; | ^~~ %Error-UNSUPPORTED: t/t_constraint_global_arr_unsup.v:48:18: Unsupported: Array element access in global constraint 48 | m_mid_arr[0].m_obj.m_y == 301; | ^~~~~ %Error-UNSUPPORTED: t/t_constraint_global_arr_unsup.v:53:27: Unsupported: Array element access in global constraint 53 | m_mid_arr[1].m_arr[2].m_y == 400; | ^~~ %Error-UNSUPPORTED: t/t_constraint_global_arr_unsup.v:53:18: Unsupported: Array element access in global constraint 53 | m_mid_arr[1].m_arr[2].m_y == 400; | ^~~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_pgo_threads.py0000755000542200017500000000207015125463617022277 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vltmt') test.top_filename = "t/t_gen_alw.v" # It doesn't really matter what test test.compile(v_flags2=["--prof-pgo"], threads=2) test.execute(all_run_flags=[ "+verilator+prof+exec+start+0", " +verilator+prof+exec+file+/dev/null", " +verilator+prof+vlt+file+" + test.obj_dir + "/profile.vlt"]) # yapf:disable test.file_grep(test.obj_dir + "/profile.vlt", r'profile_data ') test.compile( # Intentionally no --prof-pgo here to make sure profile data can be read in # without it (that is: --prof-pgo has no effect on profile_data hash names) v_flags2=[" " + test.obj_dir + "/profile.vlt"], threads=2) test.execute() test.passes() verilator-5.044/test_regress/t/t_wire_beh1364_bad.py0000755000542200017500000000136015125463617022711 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') waiver_filename = test.obj_dir + "/" + test.name + "_waiver.vlt" test.lint(verilator_flags2=["--language 1364-2001 --waiver-output", waiver_filename], fails=True, expect_filename=test.golden_filename) if os.path.exists(waiver_filename): test.error("Waiver file generated, not expected") test.passes() verilator-5.044/test_regress/t/t_interface_generic2.py0000755000542200017500000000077115125463617023524 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--timing']) test.execute() test.passes() verilator-5.044/test_regress/t/t_event_control_star.out0000644000542200017500000000037115125463617024070 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_event_control_star.v:19:6: Unsupported: no sense equation (@*) 19 | @* a = c; | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.044/test_regress/t/t_class_new_bad.v0000644000542200017500000000204215125463617022375 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class ClsNoArg; int imembera; function new(); imembera = 5; endfunction endclass class ClsNoNew; int imembera; endclass class ClsArg; int imembera; function new(int i); imembera = i + 1; endfunction endclass class ClsNew1; static function new(); // <--- Error: new can't be static endfunction endclass class ClsNew2; virtual function new(); // <--- Error: new can't be virtual endfunction endclass class ClsNew3; extern virtual function new(); // <--- Error: new can't be virtual endclass function ClsNew3::new(); endfunction module t; initial begin ClsNoArg c1; ClsNoNew c2; ClsArg c3; c1 = new(3); // Bad, called with arg c2 = new(3); // Bad, called with arg c3 = new(); // Bad, called without arg c1 = new[2]; $stop; end endmodule verilator-5.044/test_regress/t/t_lint_assigneqexpr_bad.out0000644000542200017500000000134715125463617024527 0ustar mahmoudyfreeshell%Warning-ASSIGNEQEXPR: t/t_lint_assigneqexpr.v:32:11: Assignment '=' inside expression : ... Was a '==' intended, or suggest use a separate statement 32 | c_o = 1 | ^ ... For warning description see https://verilator.org/warn/ASSIGNEQEXPR?v=latest ... Use "/* verilator lint_off ASSIGNEQEXPR */" and lint_on around source to disable this message. %Warning-ASSIGNEQEXPR: t/t_lint_assigneqexpr.v:34:11: Assignment '=' inside expression : ... Was a '==' intended, or suggest use a separate statement 34 | c_o = 0 | ^ %Error: Exiting due to verilator-5.044/test_regress/t/t_past_bad.py0000755000542200017500000000076315125463617021564 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_export_packed_struct.cpp0000644000542200017500000001436515125463617024375 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // Copyright 2024 by Kefa Chen. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 //************************************************************************* #include #include VM_PREFIX_INCLUDE #include "TestCheck.h" /* typedef logic [5:0] udata6_t; typedef union packed { udata6_t a; logic [2:0] b; } sub_t; typedef struct packed { logic [40:0] a; udata6_t [3:0] b; sub_t c; } in_t ; typedef struct packed { udata6_t [3:0] b; sub_t c; logic [40:0] a; } out_t ; // struct in1_t should cover parts of VL_ASSIGNSEL_II functions typedef struct packed { logic [3:0] a; logic [11:0] b; } in1_t; // 4 + 12 = 16 typedef struct packed { logic [11:0] b; logic [3:0] a; } out1_t; // struct in2_t should cover all VL_ASSIGNSEL_II functions typedef struct packed { logic [2:0] a; logic [8:0] b; logic [18:0] c; } in2_t; // 3 + 9 + 19 = 31 typedef struct packed { logic [8:0] b; logic [18:0] c; logic [2:0] a; } out2_t; // struct in3_t should cover all VL_ASSIGNSEL_XQ functions typedef struct packed { logic [1:0] a; logic [8:0] b; logic [16:0] c; logic [32:0] d; } in3_t; // 33 + 17 + 9 + 2 = 61 typedef struct packed { logic [8:0] b; logic [1:0] a; logic [32:0] d; logic [16:0] c; } out3_t; // struct in4_t should cover all VL_ASSIGNSEL_XW functions typedef struct packed { logic [4:0] a; logic [12:0] b; logic [24:0] c; logic [48:0] d; logic [80:0] e; } in4_t; // 5 + 13 + 25 + 49 + 81 = 173 typedef struct packed { logic [24:0] c; logic [48:0] d; logic [80:0] e; logic [4:0] a; logic [12:0] b; } out4_t; */ #define CONCAT_IMPL(a, b) a##b #define CONCAT(a, b) CONCAT_IMPL(a, b) #define CONCAT5(a, b, c, d, e) CONCAT(CONCAT(CONCAT(CONCAT(a, b), c), d), e) #define EXPORTED_STRUCT_NAME(STRUCT_NAME, NUMBER) \ CONCAT5(VM_PREFIX, _, STRUCT_NAME, __struct__, NUMBER) #define EXPORTED_UNION_NAME(UNION_NAME, NUMBER) \ CONCAT5(VM_PREFIX, _, UNION_NAME, __union__, NUMBER) #define SUB_T EXPORTED_UNION_NAME(sub_t, 0) #define IN_T EXPORTED_STRUCT_NAME(in_t, 0) #define OUT_T EXPORTED_STRUCT_NAME(out_t, 0) #define IN1_T EXPORTED_STRUCT_NAME(in1_t, 0) #define IN2_T EXPORTED_STRUCT_NAME(in2_t, 0) #define IN3_T EXPORTED_STRUCT_NAME(in3_t, 0) #define IN4_T EXPORTED_STRUCT_NAME(in4_t, 0) #define OUT1_T EXPORTED_STRUCT_NAME(out1_t, 0) #define OUT2_T EXPORTED_STRUCT_NAME(out2_t, 0) #define OUT3_T EXPORTED_STRUCT_NAME(out3_t, 0) #define OUT4_T EXPORTED_STRUCT_NAME(out4_t, 0) int errors = 0; int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; contextp->debug(0); contextp->randReset(2); contextp->commandArgs(argc, argv); const std::unique_ptr adder{new VM_PREFIX{contextp.get()}}; { IN_T in1, in2; OUT_T out; in1.a = 0x12345678; in1.__SYM__nullptr[0] = 0x1; in1.__SYM__nullptr[1] = 0x2; in1.__SYM__nullptr[2] = 0x3; in1.__SYM__nullptr[3] = 0x4; in1.get__0.a = 0x5; in2.a = 0x11111111; in2.__SYM__nullptr[0] = 0x10; in2.__SYM__nullptr[1] = 0x20; in2.__SYM__nullptr[2] = 0x30; in2.__SYM__nullptr[3] = 0x30; in2.get__0.a = 0x20; adder->op1 = in1.get(); adder->op2 = in2.get(); adder->eval(); out.set(adder->out); TEST_CHECK_EQ(out.__SYM__nullptr[0], 0x11); TEST_CHECK_EQ(out.__SYM__nullptr[1], 0x22); TEST_CHECK_EQ(out.__SYM__nullptr[2], 0x33); TEST_CHECK_EQ(out.__SYM__nullptr[3], 0x34); TEST_CHECK_EQ(out.get__0.a, 0x25); TEST_CHECK_EQ(out.a, 0x23456789); // Additional tests IN1_T op1a, op1b; OUT1_T out1; op1a.a = 0x4; op1b.a = 0x5; op1a.b = 0x1fe; op1b.b = 0x1ef; adder->op1a = op1a.get(); adder->op1b = op1b.get(); adder->eval(); out1.set(adder->out1); TEST_CHECK_EQ(out1.a, op1a.a + op1b.a); TEST_CHECK_EQ(out1.b, op1a.b + op1b.b); IN2_T op2a, op2b; OUT2_T out2; op2a.a = 0x4; op2b.a = 0x3; op2a.b = 0xff; op2b.b = 0x1; op2a.c = 0x11212; op2b.c = 0x12121; adder->op2a = op2a.get(); adder->op2b = op2b.get(); adder->eval(); out2.set(adder->out2); TEST_CHECK_EQ(out2.a, op2a.a + op2b.a); TEST_CHECK_EQ(out2.b, op2a.b + op2b.b); TEST_CHECK_EQ(out2.c, op2a.c + op2b.c); IN3_T op3a, op3b; OUT3_T out3; op3a.a = 0x1; op3b.a = 0x2; op3a.b = 0x155; op3b.b = 0x44; op3a.c = 0xff; op3b.c = 0xff00; op3a.d = 0x123232323ULL; op3b.d = 0x32323232ULL; adder->op3a = op3a.get(); adder->op3b = op3b.get(); adder->eval(); out3.set(adder->out3); TEST_CHECK_EQ(out3.a, op3a.a + op3b.a); TEST_CHECK_EQ(out3.b, op3a.b + op3b.b); TEST_CHECK_EQ(out3.c, op3a.c + op3b.c); TEST_CHECK_EQ(out3.d, op3a.d + op3b.d); IN4_T op4a, op4b; OUT4_T out4; op4a.a = 0xf; op4b.a = 0x2; op4a.b = 0x123; op4b.b = 0x432; op4a.c = 0x123456; op4b.c = 0x654321; op4a.d = 0x123456789ULL; op4b.d = 0x987654321ULL; op4a.e[0] = 0x12345678; op4b.e[0] = 0x87654321; op4a.e[1] = 0xabcde000; op4b.e[1] = 0x000cdeba; op4a.e[2] = 0xe; op4b.e[2] = 0xf; adder->op4a = op4a.get(); adder->op4b = op4b.get(); adder->eval(); out4.set(adder->out4); TEST_CHECK_EQ(out4.a, op4a.a + op4b.a); TEST_CHECK_EQ(out4.b, op4a.b + op4b.b); TEST_CHECK_EQ(out4.c, op4a.c + op4b.c); TEST_CHECK_EQ(out4.d, op4a.d + op4b.d); TEST_CHECK_EQ(out4.e[0], op4a.e[0] + op4b.e[0]); TEST_CHECK_EQ(out4.e[1], op4a.e[1] + op4b.e[1]); TEST_CHECK_EQ(out4.e[2], op4a.e[2] + op4b.e[2]); } printf("*-* All Finished *-*\n"); return errors; } verilator-5.044/test_regress/t/t_enum_huge_methods_bad.v0000644000542200017500000000141515125463617024121 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; typedef enum logic [159:0] { E01 = 160'h1, ELARGE = 160'h1234_4567_abcd_1234_4567_abcd } my_t; my_t e; int cyc; // Check runtime always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin // Setup e <= E01; end else if (cyc==1) begin $display(e.name); e <= ELARGE; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.044/test_regress/t/t_class_param_comma_bad.py0000755000542200017500000000076615125463617024261 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_math_trig.py0000755000542200017500000000073415125463617021763 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_trace_packed_struct_saif.out0000644000542200017500000004577415125463617025211 0ustar mahmoudyfreeshell// Generated by verilated_saif (SAIFILE (SAIFVERSION "2.0") (DIRECTION "backward") (PROGRAM_NAME "Verilator") (DIVIDER / ) (TIMESCALE 1ps) (DURATION 40) (INSTANCE top (NET (clk (T0 25) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 7)) ) (INSTANCE t (NET (clk (T0 25) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 7)) (cnt\[0\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) (cnt\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (cnt\[2\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[8\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[9\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[10\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[11\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[12\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[13\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[14\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[15\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[16\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[17\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[18\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[19\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[20\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[21\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[22\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[23\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[24\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[25\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[26\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[27\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[28\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[29\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[30\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[31\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[0\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[1\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[2\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[8\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[9\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[10\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[11\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[12\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[13\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[14\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[15\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[16\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[17\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[18\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[19\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[20\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[21\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[22\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[23\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[24\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[25\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[26\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[27\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[28\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[0]\[29\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[0]\[30\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[31\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[32\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[0]\[33\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[34\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[35\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[36\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[37\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[38\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[39\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[40\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[41\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[42\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[43\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[44\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[45\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[46\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[47\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[48\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[49\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[50\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[51\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[52\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[53\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[54\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[55\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[56\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[57\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[58\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[59\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[60\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[0]\[61\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[0]\[62\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[63\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[64\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[65\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[0]\[66\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[67\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[68\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[69\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[70\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[71\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[72\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[73\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[74\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[75\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[76\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[77\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[78\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[79\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[80\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[81\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[82\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[83\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[84\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[85\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[86\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[87\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[88\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[89\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[90\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[91\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[92\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[0]\[93\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[0]\[94\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[95\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[0\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[1\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[2\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[8\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[9\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[10\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[11\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[12\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[13\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[14\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[15\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[16\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[17\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[18\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[19\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[20\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[21\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[22\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[23\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[24\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[25\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[26\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[27\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[28\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[29\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[1]\[30\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[31\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[32\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[1]\[33\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[34\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[35\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[36\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[37\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[38\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[39\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[40\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[41\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[42\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[43\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[44\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[45\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[46\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[47\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[48\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[49\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[50\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[51\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[52\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[53\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[54\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[55\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[56\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[57\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[58\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[59\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[60\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[61\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[1]\[62\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[63\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[64\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[65\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[1]\[66\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[67\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[68\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[69\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[70\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[71\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[72\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[73\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[74\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[75\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[76\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[77\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[78\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[79\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[80\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[81\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[82\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[83\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[84\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[85\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[86\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[87\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[88\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[89\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[90\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[91\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[92\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[93\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[1]\[94\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[95\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[0\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[1\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[2\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[8\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[9\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[10\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[11\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[12\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[13\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[14\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[15\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[16\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[17\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[18\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[19\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[20\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[21\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[22\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[23\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[24\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[25\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[26\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[27\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[28\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[2]\[29\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[30\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[31\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[32\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[2]\[33\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[34\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[35\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[36\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[37\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[38\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[39\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[40\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[41\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[42\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[43\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[44\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[45\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[46\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[47\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[48\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[49\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[50\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[51\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[52\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[53\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[54\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[55\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[56\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[57\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[58\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[59\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[60\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[2]\[61\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[62\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[63\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[64\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[65\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[2]\[66\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[67\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[68\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[69\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[70\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[71\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[72\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[73\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[74\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[75\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[76\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[77\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[78\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[79\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[80\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[81\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[82\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[83\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[84\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[85\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[86\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[87\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[88\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[89\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[90\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[91\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[92\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[2]\[93\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[94\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[95\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) verilator-5.044/test_regress/t/t_display_signed.out0000644000542200017500000000200015125463617023143 0ustar mahmoudyfreeshell[0] lp %x=0bbccc %x=0bbccc %o=2736314 %b=010111011110011001100 %0d=769228 %d= 769228 %p=769228 %0p='hbbccc [0] ln %x=1bbccc %x=1bbccc %o=6736314 %b=110111011110011001100 %0d=-279348 %d= -279348 %p=1817804 %0p='h1bbccc [0] qp %x=001bbbbcccc %x=001bbbbcccc %o=00067356746314 %b=00000000110111011101110111100110011001100 %0d=7444614348 %d= 7444614348 %p=7444614348 %0p='h1bbbbcccc [0] qn %x=101bbbbcccc %x=101bbbbcccc %o=20067356746314 %b=10000000110111011101110111100110011001100 %0d=-1092067013428 %d=-1092067013428 %p=1106956242124 %0p='h101bbbbcccc [0] wp %x=000bc1234567812345678 %x=000bc1234567812345678 %o=000570110642547402215053170 %b=000000000101111000001001000110100010101100111100000010010001101000101011001111000 %p=3469299654322568844920 %0p='hbc1234567812345678 [0] wn %x=000bc1234577812345678 %x=000bc1234577812345678 %o=000570110642567402215053170 %b=000000000101111000001001000110100010101110111100000010010001101000101011001111000 %p=3469299655422080472696 %0p='hbc1234577812345678 *-* All Finished *-* verilator-5.044/test_regress/t/t_trace_dumpvars_dyn_saif_0.py0000755000542200017500000000130515125463617025112 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_trace_dumpvars_dyn.cpp" test.top_filename = "t/t_trace_dumpvars_dyn.v" test.compile(make_main=False, verilator_flags2=["--trace-saif --exe", test.pli_filename]) test.execute() test.saif_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg.py0000755000542200017500000000077115125463617031430 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_math_shortcircuit_dynsel.v0000644000542200017500000000201715125463617024724 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; logic [31:0] dict [int] []; // verilator lint_off WIDTHTRUNC function automatic logic f(int a); int dict_size = dict.size; logic next_exists = dict.next(a); // incorrectly inserts element at `a` logic next_nonzero = !next_exists || (dict[a].size != 0); if (dict_size != dict.size) begin $display("Assertion failed: dict_size mismatch"); $display("Initial size: %0d, New size: %0d", dict_size, dict.size); $display("Dictionary contents:"); foreach (dict[key]) begin $display(" Key: %0d, Value: %0d", key, dict[key]); end $error; end return next_nonzero; endfunction initial begin logic r = f(0); $display(r); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_tri_array_pull.py0000755000542200017500000000073415125463617023035 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_vpi_time_cb.v0000644000542200017500000000174515125463617022102 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import "DPI-C" function void dpii_init(); import "DPI-C" function void dpii_final(); module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [31:0] count /*verilator public_flat_rd */; integer status; // Test loop initial begin count = 0; dpii_init(); end always @(posedge clk) begin `ifdef TEST_VERBOSE $display("[%0t] clk @ count %0d", $time, count); `endif count <= count + 2; if (count == 200) begin $display("Final section"); // See C++ code: $write("*-* All Finished *-*\n"); dpii_final(); $finish; end end endmodule : t verilator-5.044/test_regress/t/t_param_bit_sel.v0000644000542200017500000000141415125463617022414 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // We see Verilator assumes a 1-bit parameter is a scalar rather than a 1-bit // long vector. This causes the following code to fail. // // Other event drive simulators accept this. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // At this point it is ambiguous whether a is scalar or vector parameter A = 1'b0; wire b = A[0]; // Note however b[0] is illegal. always @(posedge clk) begin if (b == 1'b0) begin $write("*-* All Finished *-*\n"); $finish; end else begin $stop; end end endmodule verilator-5.044/test_regress/t/t_inside3.v0000644000542200017500000000165715125463617021162 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Foo; int callCount = 0; int value = 6; function int get(); callCount += 1; return value; endfunction endclass module t; Foo foo; Foo array[100]; Foo res[$]; initial begin foo = new; for (int i = 0; i < 100; ++i) begin array[i] = new; end if (!(foo.get() inside {3,4,5,6,7,8,9})) $stop; if (foo.callCount != 1) $stop; if (!(foo.get() inside {[3:9]})) $stop; if (foo.callCount != 2) $stop; res = array.find(x) with (x.get() inside {5,7,8,9}); if (res.size() != 0) $stop; for (int i = 0; i < 100; ++i) begin if (array[i].callCount != 1) $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_stop_winos_bad.py0000755000542200017500000000105015125463617023007 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['-no-MMD']) test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_cover_sva_trace.out0000644000542200017500000000377115125463617023332 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 # clk $end $scope module t $end $var wire 1 # clk $end $var wire 1 $ toggle $end $var wire 32 % cyc [31:0] $end $scope module suba $end $var wire 1 # clk $end $var wire 1 $ toggle $end $var wire 32 & cyc [31:0] $end $var wire 32 ' cyc_eq_5_vlCoverageUserTrace [31:0] $end $upscope $end $scope module subb $end $var wire 1 # clk $end $var wire 1 $ toggle $end $var wire 32 & cyc [31:0] $end $var wire 32 ( cyc_eq_5_vlCoverageUserTrace [31:0] $end $upscope $end $scope module subc $end $var wire 1 # clk $end $var wire 1 $ toggle $end $var wire 32 & cyc [31:0] $end $var wire 32 ) cyc_eq_5_vlCoverageUserTrace [31:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 0# 0$ b00000000000000000000000000000001 % b00000000000000000000000000000001 & b00000000000000000000000000000000 ' b00000000000000000000000000000000 ( b00000000000000000000000000000000 ) #10 1# b00000000000000000000000000000010 % b00000000000000000000000000000010 & #15 0# #20 1# 1$ b00000000000000000000000000000011 % b00000000000000000000000000000011 & #25 0# #30 1# 0$ b00000000000000000000000000000100 % b00000000000000000000000000000100 & #35 0# #40 1# 1$ b00000000000000000000000000000101 % b00000000000000000000000000000101 & #45 0# #50 1# 0$ b00000000000000000000000000000110 % b00000000000000000000000000000110 & b00000000000000000000000000000001 ' b00000000000000000000000000000001 ( b00000000000000000000000000000001 ) #55 0# #60 1# 1$ b00000000000000000000000000000111 % b00000000000000000000000000000111 & #65 0# #70 1# 0$ b00000000000000000000000000001000 % b00000000000000000000000000001000 & #75 0# #80 1# 1$ b00000000000000000000000000001001 % b00000000000000000000000000001001 & #85 0# #90 1# 0$ b00000000000000000000000000001010 % b00000000000000000000000000001010 & #95 0# #100 1# 1$ b00000000000000000000000000001011 % b00000000000000000000000000001011 & verilator-5.044/test_regress/t/t_vlt_warn_bad.vlt0000644000542200017500000000104315125463617022613 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `verilator_config lint_off -rule CASEINCOMPLETE -file "t/t_vlt_warn.v" lint_off -rule WIDTH -file "t/t_vlt_warn.v" -lines 18 // Test wildcard filenames lint_off -rule WIDTH -file "*/t_vlt_warn.v" -lines 19-19 coverage_off -file "t/t_vlt_warn.v" // Test --flag is also accepted tracing_off --file "t/t_vlt_warn.v" verilator-5.044/test_regress/t/t_interface_ref_trace_noinl.py0000755000542200017500000000150515125463617025153 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_ref_trace.v" # Should be the same as the inlined version, but might have declarations # in a different order. Sadly vcddiff can't check equivalence # test.golden_filename = "t/t_interface_ref_trace.out" test.compile(verilator_flags2=['-fno-inline --trace-structs --trace-vcd']) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_implements_notfound_bad.py0000755000542200017500000000076615125463617024711 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_inst_prepost.py0000755000542200017500000000071415125463617022534 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.044/test_regress/t/t_sys_strobe.out0000644000542200017500000000020515125463617022346 0ustar mahmoudyfreeshell[110] cyc=11 [110] cyc=11 also 00000000000000000000000000010010b 00000013h 00000000024o [230] cyc=23 new-strobe *-* All Finished *-* verilator-5.044/test_regress/t/t_randomize.out0000644000542200017500000000177515125463617022157 0ustar mahmoudyfreeshell%Warning-CONSTRAINTIGN: t/t_randomize.v:22:14: Constraint expression ignored (imperfect distribution) : ... note: In instance 't' 22 | length dist { [0:1], [2:5] :/ 2, 6 := 6, 7 := 10, 1}; | ^~~~ ... For warning description see https://verilator.org/warn/CONSTRAINTIGN?v=latest ... Use "/* verilator lint_off CONSTRAINTIGN */" and lint_on around source to disable this message. %Warning-CONSTRAINTIGN: t/t_randomize.v:40:7: Constraint expression ignored (unsupported) : ... note: In instance 't' 40 | unique { array[0], array[1] }; | ^~~~~~ %Warning-CONSTRAINTIGN: t/t_randomize.v:43:23: Constraint expression ignored (imperfect distribution) : ... note: In instance 't' 43 | constraint order { solve length before header; } | ^~~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_for_break.v0000644000542200017500000000775115125463617021557 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [3:0] l_stop = crc[3:0]; wire [3:0] l_break = crc[7:4]; wire [3:0] l_continue = crc[11:8]; /*AUTOWIRE*/ wire [15:0] out0 = Test0(l_stop, l_break, l_continue); wire [15:0] out1 = Test1(l_stop, l_break, l_continue); wire [15:0] out2 = Test2(l_stop, l_break, l_continue); wire [15:0] out3 = Test3(l_stop, l_break, l_continue); // Aggregate outputs into a single result vector wire [63:0] result = {out3,out2,out1,out0}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin if (out0!==out1) $stop; if (out0!==out2) $stop; if (out0!==out3) $stop; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h293e9f9798e97da0 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end function [15:0] Test0; input [3:0] loop_stop; input [3:0] loop_break; input [3:0] loop_continue; integer i; reg broken; Test0 = 0; broken = 0; begin for (i=1; i<20; i=i+1) begin if (!broken) begin Test0 = Test0 + 1; if (i[3:0] != loop_continue) begin // continue if (i[3:0] == loop_break) begin broken = 1'b1; end if (!broken) begin Test0 = Test0 + i[15:0]; end end end end end endfunction function [15:0] Test1; input [3:0] loop_stop; input [3:0] loop_break; input [3:0] loop_continue; integer i; Test1 = 0; begin : outer_block for (i=1; i<20; i=i+1) begin : inner_block Test1 = Test1 + 1; // continue, IE jump to end-of-inner_block. Must be inside inner_block. if (i[3:0] == loop_continue) disable inner_block; // break, IE jump to end-of-outer_block. Must be inside outer_block. if (i[3:0] == loop_break) disable outer_block; Test1 = Test1 + i[15:0]; end : inner_block end : outer_block endfunction function [15:0] Test2; input [3:0] loop_stop; input [3:0] loop_break; input [3:0] loop_continue; integer i; Test2 = 0; begin for (i=1; i<20; i=i+1) begin Test2 = Test2 + 1; if (i[3:0] == loop_continue) continue; if (i[3:0] == loop_break) break; Test2 = Test2 + i[15:0]; end end endfunction function [15:0] Test3; input [3:0] loop_stop; input [3:0] loop_break; input [3:0] loop_continue; integer i; Test3 = 0; begin for (i=1; i<20; i=i+1) begin Test3 = Test3 + 1; if (i[3:0] == loop_continue) continue; // return, IE jump to end-of-function optionally setting return value if (i[3:0] == loop_break) return Test3; Test3 = Test3 + i[15:0]; end end endfunction endmodule verilator-5.044/test_regress/t/t_sys_sformat.v0000644000542200017500000000611115125463617022163 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // Note $sscanf already tested elsewhere reg [3:0] n; reg [63:0] q; reg [16*8:1] wide; reg [8:1] ochar; reg [48*8:1] str; reg [48*8:1] str2; string str3; reg [39:0] instruction_str [1:0]; real r; initial begin n = 4'b1100; q = 64'h1234_5678_abcd_0123; wide = "hello-there12345"; $sformat(str, "n=%b q=%d w=%s", n, q, wide); `ifdef TEST_VERBOSE $display("str=%0s",str); `endif if (str !== "n=1100 q= 1311768467750060323 w=hello-there12345") $stop; q = {q[62:0],1'b1}; $swrite(str2, "n=%b q=%d w=%s", n, q, wide); `ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif if (str2 !== "n=1100 q= 2623536935500120647 w=hello-there12345") $stop; str3 = $sformatf("n=%b q=%d w=%s", n, q, wide); `ifdef TEST_VERBOSE $display("str3=%0s",str3); `endif if (str3 !== "n=1100 q= 2623536935500120647 w=hello-there12345") $stop; $swrite(str2, "e=%e", r); $swrite(str2, "e=%f", r); $swrite(str2, "e=%g", r); str3 = "hello"; $swrite(str2, {str3, str3}); `ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif if (str2 !== "hellohello") $stop; r = 0.01; $swrite(str2, "e=%e f=%f g=%g", r, r, r); `ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif if (str2 !== "e=1.000000e-02 f=0.010000 g=0.01") $stop; $swrite(str2, "mod=%m"); `ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif if (str2 !== "mod=top.t") $stop; $swrite(str2, "lib=%l"); `ifdef TEST_VERBOSE $display("chkl %0s",str2); `endif if (str2 !== "lib=work.t") $stop; str3 = $sformatf("u=%u", {"a","b","c","d"}); // Value selected so is printable `ifdef TEST_VERBOSE $display("chku %s", str3); `endif if (str3 !== "u=dcba") $stop; str3 = $sformatf("v=%v", 4'b01xz); // Value selected so is printable `ifdef TEST_VERBOSE $display("chkv %s", str3); `endif str3 = $sformatf("z=%z", {"a","b","c","d"}); // Value selected so is printable `ifdef TEST_VERBOSE $display("chkz %s", str3); `endif $sformat(ochar,"%s","c"); if (ochar != "c") $stop; $swrite(str2, 4'd12); if (str2 != "12") $stop; $swriteb(str2, 4'd12); if (str2 != "1100") $stop; $swriteh(str2, 4'd12); if (str2 != "c") $stop; $swriteo(str2, 4'd12); if (str2 != "14") $stop; str3 = "foo"; $sformat(str3, "%s", str3); // $sformat twice so verilator does not $sformat(str3, "%s", str3); // optimize the call to $sformat(str3, "%s", "foo") `ifdef TEST_VERBOSE $display("str3=%0s", str3); `endif if (str3 != "foo") $stop; $sformat(instruction_str[0], "%s", "Hello"); $sformat(instruction_str[1], "%s", "World"); if (instruction_str[0] != "Hello") $stop; if (instruction_str[1] != "World") $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_enum_value_assign.py0000755000542200017500000000073415125463617023511 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_randomize_prepost_super.v0000644000542200017500000000077415125463617024605 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; virtual class uvm_object; endclass class config_obj extends uvm_object; function void pre_randomize(); super.pre_randomize(); endfunction function void post_randomize(); super.post_randomize(); endfunction endclass initial $finish; endmodule verilator-5.044/test_regress/t/t_lint_didnotconverge_bad.py0000755000542200017500000000165615125463617024657 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") test.compile(verilator_flags2=["--prof-cfuncs"]) test.execute(fails=True, expect_filename=test.golden_filename) test.extract(in_filename=test.top_filename, out_filename=test.root + "/docs/gen/ex_DIDNOTCONVERGE_faulty.rst", lines="16-17") test.extract(in_filename=test.golden_filename, out_filename=test.root + "/docs/gen/ex_DIDNOTCONVERGE_msg.rst", lines="1-2") test.passes() verilator-5.044/test_regress/t/t_dfg_synthesis_pre_inline.v0000644000542200017500000000167315125463617024677 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 `define signal(name, expr) wire [$bits(expr)-1:0] ``name = expr module t ( `include "portlist.vh" // Boilerplate generated by t_dfg_break_cycles.py rand_a, rand_b, srand_a, srand_b ); `include "portdecl.vh" // Boilerplate generated by t_dfg_break_cycles.py input rand_a; input rand_b; input srand_a; input srand_b; wire logic [63:0] rand_a; wire logic [63:0] rand_b; wire logic signed [63:0] srand_a; wire logic signed [63:0] srand_b; ////////////////////////////////////////////////////////////////////////// logic concat_lhs_a; logic concat_lhs_b; always_comb begin {concat_lhs_a, concat_lhs_b} = rand_a[1:0] + rand_b[1:0]; end `signal(CONCAT_LHS, {concat_lhs_a, concat_lhs_b}); endmodule verilator-5.044/test_regress/t/t_fork_join_none_class_cap.py0000755000542200017500000000077115125463617025015 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_pp_display.out0000644000542200017500000000063615125463617022326 0ustar mahmoudyfreeshellpre thrupre thrumid thrupost post: "right side" left side: "right side" left side: "right side" left_side: "right_side" na: "right_side" prep ( midp1 left_side midp2 ( outp ) ): "right_side" na: "nana" left_side right_side: "left_side right_side" left side: "right side" : "" left side: "right side" left side: "right side" standalone twoline: "first second" Line 50 File "t/t_pp_display.v" *-* All Finished *-* verilator-5.044/test_regress/t/t_flag_context_bad.py0000755000542200017500000000110215125463617023256 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["-Wall -Wno-DECLFILENAME -Wno-context"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_recursive_module_bug_2.py0000755000542200017500000000071415125463617024435 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.044/test_regress/t/t_func_recurse.py0000755000542200017500000000073415125463617022470 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_class_override_bad.py0000755000542200017500000000076615125463617023624 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_class_dyn_cast_empty_if.py0000755000542200017500000000073415125463617024672 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_unpacked_struct_redef.v0000644000542200017500000000112215125463617024152 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Class#(parameter WIDTH); typedef logic [WIDTH-1:0] word; typedef struct { word w; } Struct; endclass module t; Class#(1)::Struct s1; Class#(1)::Struct s2; Class#(2)::Struct s3; initial begin $display("%p", s1); $display("%p", s2); $display("%p", s3); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_unroll_nested_param.v0000644000542200017500000000254215125463617023653 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; int a, b; int pos; function string value; // Debug 'initial' loops first value = ""; for (int exit_a = 0; exit_a < 2; ++exit_a) begin for (int exit_b = 0; exit_b < 3; ++exit_b) begin b = 0; value = {value, $sformatf("exit_a %0d %0d", exit_a, exit_b)}; for (a = 0; a < 3; ++a) begin : a_loop value = {value, $sformatf(" A%0d", a * 10 + b)}; for (b = 0; b < 3; ++b) begin : b_loop value = {value, $sformatf(" B%0d", a * 10 + b)}; if (exit_b == 1 && b == 1) disable b_loop; value = {value, $sformatf(" C%0d", a * 10 + b)}; if (exit_b == 2 && a == 1) disable a_loop; value = {value, $sformatf(" D%0d", a * 10 + b)}; end value = {value, $sformatf(" Y%0d", a * 10 + b)}; if (exit_a == 1 && a == 1) disable a_loop; value = {value, $sformatf(" Z%0d", a * 10 + b)}; end value = {value, "\n"}; end end endfunction localparam string VALUE = value(); initial begin $write("%s", VALUE); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_disable_fork1.py0000755000542200017500000000077115125463617022513 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_constraint_foreach.py0000755000542200017500000000104615125463617023655 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_reloop_cam.v0000644000542200017500000001227415125463617021741 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; reg rst; // Two phases, random so nothing optimizes away, and focused so get hits logic inval; wire [30:0] wdat = (cyc < 50 ? crc[30:0] : {29'h0, crc[1:0]}); wire [30:0] cdat = (cyc < 50 ? crc[30:0] : {29'h0, crc[1:0]}); wire wdat_val = 1'b1; wire camen = crc[32]; wire ren = crc[33]; wire wen = crc[34]; wire [7:0] rwidx = (cyc < 50 ? crc[63:56] : {6'h0, crc[57:56]}); /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) logic hit_d2r; // From cam of cam.v logic [7:0] hitidx_d1r; // From cam of cam.v logic [255:0] hitvec_d1r; // From cam of cam.v logic [30:0] rdat_d2r; // From cam of cam.v logic rdat_val_d2r; // From cam of cam.v // End of automatics cam cam (/*AUTOINST*/ // Outputs .hitvec_d1r (hitvec_d1r[255:0]), .hitidx_d1r (hitidx_d1r[7:0]), .hit_d2r (hit_d2r), .rdat_d2r (rdat_d2r[30:0]), .rdat_val_d2r (rdat_val_d2r), // Inputs .clk (clk), .rst (rst), .camen (camen), .inval (inval), .cdat (cdat[30:0]), .ren (ren), .wen (wen), .wdat (wdat[30:0]), .wdat_val (wdat_val), .rwidx (rwidx[7:0])); // Aggregate outputs into a single result vector wire [63:0] result = {hitvec_d1r[15:0], 15'h0, hit_d2r, rdat_val_d2r, rdat_d2r}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; rst <= 1'b1; end else if (cyc<10) begin sum <= '0; rst <= 1'b0; end else if (cyc==70) begin inval <= 1'b1; end else if (cyc==71) begin inval <= 1'b0; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; `define EXPECTED_SUM 64'h5182640870b07199 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module cam ( input clk, input rst, input camen, input inval, input [30:0] cdat, output logic [255:0] hitvec_d1r, output logic [7:0] hitidx_d1r, output logic hit_d2r, input ren, input wen, input [30:0] wdat, input wdat_val, input [7:0] rwidx, output logic [30:0] rdat_d2r, output logic rdat_val_d2r ); logic camen_d1r; logic inval_d1r; logic ren_d1r; logic wen_d1r; logic [7:0] rwidx_d1r; logic [30:0] cdat_d1r; logic [30:0] wdat_d1r; logic wdat_val_d1r; always_ff @(posedge clk) begin camen_d1r <= camen; inval_d1r <= inval; ren_d1r <= ren; wen_d1r <= wen; cdat_d1r <= cdat; rwidx_d1r <= rwidx; wdat_d1r <= wdat; wdat_val_d1r <= wdat_val; end typedef struct packed { logic [30:0] data; logic valid; } entry_t; entry_t [255:0] entries; always_ff @(posedge clk) begin if (camen_d1r) begin for (int i = 0; i < 256; i = i + 1) begin hitvec_d1r[i] <= entries[i].valid & (entries[i].data == cdat_d1r); end end end always_ff @(posedge clk) begin hit_d2r <= | hitvec_d1r; end always_ff @(posedge clk) begin if (rst) begin for (int i = 0; i < 256; i = i + 1) begin entries[i] <= '0; end end else if (wen_d1r) begin entries[rwidx_d1r] <= '{valid:wdat_val_d1r, data:wdat_d1r}; end else if (inval_d1r) begin for (int i = 0; i < 256; i = i + 1) begin entries[i] <= '{valid:'0, data:entries[i].data}; end end end always_ff @(posedge clk) begin if (ren_d1r) begin rdat_d2r <= entries[rwidx_d1r].data; rdat_val_d2r <= entries[rwidx_d1r].valid; end end endmodule verilator-5.044/test_regress/t/t_virtual_interface_method_bad.v0000644000542200017500000000151215125463617025466 0ustar mahmoudyfreeshell// Copyright 2003 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 class ExampleClass; localparam NUM_TXNS = 10; protected virtual example_if v_if; task run(); v_if.x(); endtask: run function void bind_if(virtual example_if v_if); this.v_if = v_if; endfunction: bind_if endclass: ExampleClass interface example_if(); logic clk; logic rstn; logic[7:0] x; endinterface: example_if module t; example_if example_if_inst(); initial begin: main ExampleClass exampleClass = new(); exampleClass.bind_if(example_if_inst); exampleClass.run(); end: main endmodule: t verilator-5.044/test_regress/t/t_struct_unpacked_param.py0000755000542200017500000000073415125463617024363 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios("simulator") test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_param_bit_sel.py0000755000542200017500000000073415125463617022606 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_case_enum_emptyish.py0000755000542200017500000000106515125463617023664 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile( # We have deep expressions we want to test) verilator_flags2=["--compiler msvc"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_class_mispure_bad.out0000644000542200017500000000073215125463617023636 0ustar mahmoudyfreeshell%Error: t/t_class_mispure_bad.v:11:1: Class 'Bar' extends 'Base' but is missing implementation for 'pvfunc' (IEEE 1800-2023 8.26) 11 | class Bar extends Base; | ^~~~~ t/t_class_mispure_bad.v:8:31: ... Location of interface class's function 8 | pure virtual function void pvfunc(); | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_lint_const_func_gen_bad.out0000644000542200017500000000164515125463617025011 0ustar mahmoudyfreeshell%Error: t/t_lint_const_func_gen_bad.v:11:30: Constant function may not be declared under generate (IEEE 1800-2023 13.4.3) : ... note: In instance 't' 11 | function automatic bit constFunc(); | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_lint_const_func_gen_bad.v:15:26: Expecting expression to be constant, but can't determine constant for FUNCREF 'constFunc' : ... note: In instance 't' t/t_lint_const_func_gen_bad.v:11:30: ... Location of non-constant FUNC 'constFunc': Constant function called under generate t/t_lint_const_func_gen_bad.v:15:26: ... Called from 'constFunc()' with parameters: 15 | localparam PARAM = constFunc(); | ^~~~~~~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_inst_overwide_bad.out0000644000542200017500000000337515125463617023654 0ustar mahmoudyfreeshell%Warning-WIDTHEXPAND: t/t_inst_overwide.v:23:14: Output port connection 'outy_w92' expects 92 bits on the pin connection, but pin connection's VARREF 'outc_w30' generates 30 bits. : ... note: In instance 't' 23 | .outy_w92 (outc_w30), | ^~~~~~~~ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. %Warning-WIDTHTRUNC: t/t_inst_overwide.v:24:14: Output port connection 'outz_w22' expects 22 bits on the pin connection, but pin connection's VARREF 'outd_w73' generates 73 bits. : ... note: In instance 't' 24 | .outz_w22 (outd_w73), | ^~~~~~~~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Warning-WIDTHEXPAND: t/t_inst_overwide.v:27:14: Input port connection 'inw_w31' expects 31 bits on the pin connection, but pin connection's VARREF 'ina_w1' generates 1 bits. : ... note: In instance 't' 27 | .inw_w31 (ina_w1), | ^~~~~~~ %Warning-WIDTHTRUNC: t/t_inst_overwide.v:28:14: Input port connection 'inx_w11' expects 11 bits on the pin connection, but pin connection's VARREF 'inb_w61' generates 61 bits. : ... note: In instance 't' 28 | .inx_w11 (inb_w61) | ^~~~~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_disable_iff_multi_bad.out0000644000542200017500000000055615125463617024432 0ustar mahmoudyfreeshell%Error: t/t_disable_iff_multi_bad.v:14:4: Only one 'default disable iff' allowed per module (IEEE 1800-2023 16.15) : ... note: In instance 't' 14 | default disable iff (!rstn); | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_func_inout_bit_sel.v0000644000542200017500000000135515125463617023471 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); class Cls; function bit get_x_set_1(inout bit x); bit a = x; x = 1; return a; endfunction endclass module t; int a; bit b; Cls cls; initial begin cls = new; b = cls.get_x_set_1(a[1]); `checkh(b, 0); `checkh(a[1], 1); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_func_task_bad2.v0000644000542200017500000000075415125463617022466 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; task a_task; input ign; endtask function void func_calls_task; a_task(1'b0); // <--- Bad: Calling task _from_ function endfunction function void func_ok; fork a_task(1'b0); // ok, and done in UVM join_none endfunction endmodule verilator-5.044/test_regress/t/t_queue_unpacked.v0000644000542200017500000000343215125463617022613 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; typedef string sarray_t[2]; typedef sarray_t q_sarray_t[$]; typedef bit [95:0] wide_t; typedef wide_t warray_t[2]; typedef warray_t q_warray_t[$]; initial begin begin q_sarray_t iq; sarray_t a; sarray_t b0; sarray_t b1; a[0] = "hello"; a[1] = "world"; iq.push_back(a); a[0] = "bye"; a[1] = "world"; iq.push_back(a); b0 = iq[0]; b1 = iq[1]; `checks(b0[0], "hello"); `checks(b0[1], "world"); `checks(b1[0], "bye"); `checks(b1[1], "world"); iq[2][0] = "goodbye"; iq[2][1] = "world"; `checks(iq[2][0], "goodbye"); `checks(iq[2][1], "world"); end `ifndef verilator // Need wide conversion into VlUnpacked types // If we convert all arrays to VlUnpacked it works, so we need to track // data types and insert conversions perhaps in V3Cast, but we currently // don't know the output datatypes, so work needed. begin q_warray_t iq; warray_t a; warray_t b0; a[0] = "abcdefg_ijkl"; a[1] = "012123123128"; iq.push_back(a); b0 = iq[0]; `checks(b0[0], "abcdefg_ijkl"); `checks(b0[1], "012123123128"); end `endif $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_interface_ref_trace_noinl_notrace.py0000755000542200017500000000105415125463617026665 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_ref_trace.v" test.compile(verilator_flags2=['-fno-inline']) test.execute() test.passes() verilator-5.044/test_regress/t/t_vpi_stop_bad_c.cpp0000644000542200017500000000145515125463617023110 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include "vpi_user.h" #include #include //====================================================================== extern "C" { extern void dpii_test(); } //====================================================================== void dpii_test() { vpi_control(vpiStop); } verilator-5.044/test_regress/t/t_order_quad.cpp0000644000542200017500000000222615125463617022257 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include VM_PREFIX_INCLUDE //====================================================================== unsigned int main_time = 0; double sc_time_stamp() { return main_time; } VM_PREFIX* topp = nullptr; bool fail = false; void check(QData got, QData exp) { if (got != exp) { VL_PRINTF("%%Error: got=0x%" PRIx64 " exp=0x%" PRIx64 "\n", got, exp); fail = true; } } int main(int argc, char* argv[]) { Verilated::debug(0); Verilated::commandArgs(argc, argv); topp = new VM_PREFIX; topp->a0 = 0; topp->eval(); check(topp->y, 0x0ULL); topp->a0 = 15; topp->eval(); check(topp->y, 0x3c00000000ULL); if (!fail) { VL_PRINTF("*-* All Finished *-*\n"); topp->final(); } else { vl_fatal(__FILE__, __LINE__, "top", "Unexpected results\n"); } VL_DO_DANGLING(delete topp, topp); return 0; } verilator-5.044/test_regress/t/t_extract_static_const_multimodule.py0000755000542200017500000000133015125463617026645 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(verilator_flags2=["--stats"]) test.execute(expect_filename=test.golden_filename) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, Prelim extracted value to ConstPool\s+(\d+)', 8) test.file_grep(test.stats, r'ConstPool, Constants emitted\s+(\d+)', 1) test.passes() verilator-5.044/test_regress/t/t_timing_wait1.py0000755000542200017500000000101015125463617022365 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary -Wno-WAITCONST"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_dpi_instr_count_large.cpp0000644000542200017500000000101615125463617024503 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2025 by Antmicro. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* extern "C" void dpii_call(void) {} verilator-5.044/test_regress/t/t_union_soft.out0000644000542200017500000000035415125463617022342 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_union_soft.v:9:10: Unsupported: 'union soft' 9 | union soft { | ^~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.044/test_regress/t/t_vlcov_info.py0000755000542200017500000000142415125463617022146 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--write-info", test.obj_dir + "/coverage.info", "t/t_vlcov_data_a.dat", "t/t_vlcov_data_b.dat", "t/t_vlcov_data_c.dat", "t/t_vlcov_data_d.dat" ], verilator_run=True) test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") test.passes() verilator-5.044/test_regress/t/t_flag_deprecated_bad.v0000644000542200017500000000035215125463617023512 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; endmodule verilator-5.044/test_regress/t/t_constraint_assoc_arr_wide.py0000755000542200017500000000104615125463617025232 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_vlt_match_contents.py0000755000542200017500000000107615125463617023703 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["-Wall t/t_vlt_match_contents.vlt"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_program_anonymous.py0000755000542200017500000000105515125463617023561 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) if not test.vlt_all: test.execute() test.passes() verilator-5.044/test_regress/t/t_typedef_circ_bad.v0000644000542200017500000000040515125463617023060 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef a_t; typedef a_t b_t; typedef b_t a_t; verilator-5.044/test_regress/t/t_var_dotted1_inl0.py0000755000542200017500000000104515125463617023137 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_var_dotted1.v" test.compile(v_flags2=['+define+NOUSE_INLINE']) test.execute() test.passes() verilator-5.044/test_regress/t/t_mem_slice_dtype_bad.py0000755000542200017500000000076615125463617023762 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_param_typedef.py0000755000542200017500000000070615125463617022624 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.044/test_regress/t/t_lint_once_bad.py0000755000542200017500000000103215125463617022555 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["-Wwarn-UNUSED"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_interface_down_inld.py0000755000542200017500000000110115125463617023767 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_down.v" test.compile(v_flags2=['+define+INLINE_D'], verilator_flags2=['-trace']) test.execute() test.passes() verilator-5.044/test_regress/t/t_nettype.v0000644000542200017500000000251215125463617021303 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package Pkg; typedef real real_t; real last_resolve; function automatic real resolver(input real drivers[]); resolver = 0.0; foreach (drivers[i]) resolver += drivers[i]; last_resolve = resolver; endfunction endpackage module t; function automatic real local_resolver(input real drivers[]); local_resolver = 0.0; foreach (drivers[i]) local_resolver += drivers[i]; endfunction nettype real real1_n with Pkg::resolver; real1_n real1; assign real1 = 1.23; nettype real real2_n with local_resolver; real2_n real2; assign real2 = 1.23; // Create alias using new name nettype real2_n real3_n; real3_n real3; assign real3 = 1.23; nettype Pkg::real_t real4_n with Pkg::resolver; real4_n real4; assign real4 = 1.23; // TODO when implement net types need to check multiple driver cases, across // submodules initial begin #10; if (real1 != 1.23) $stop; if (real2 != 1.23) $stop; if (real3 != 1.23) $stop; if (Pkg::last_resolve != 1.23) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_enum_bad_dup.py0000755000542200017500000000103515125463617022422 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["-Wwarn-VARHIDDEN"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_dfg_peephole.v0000644000542200017500000003503415125463617022241 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 `define signal(name, expr) wire [$bits(expr)-1:0] ``name = expr module t ( `include "portlist.vh" // Boilerplate generated by t_dfg_peephole.py rand_a, rand_b, srand_a, srand_b, arand_a, arand_b ); `include "portdecl.vh" // Boilerplate generated by t_dfg_peephole.py input rand_a; input rand_b; input srand_a; input srand_b; input arand_a; input arand_b; wire logic [63:0] rand_a; wire logic [63:0] rand_b; wire logic signed [63:0] srand_a; wire logic signed [63:0] srand_b; // verilator lint_off ASCRANGE wire logic [0:63] arand_a; wire logic [0:63] arand_b; // verilator lint_on ASCRANGE wire logic randbit_a = rand_a[0]; wire logic [127:0] rand_ba = {rand_b, rand_a}; wire logic [127:0] rand_aa = {2{rand_a}}; wire logic [63:0] const_a; wire logic [63:0] const_b; wire logic signed [63:0] sconst_a; wire logic signed [63:0] sconst_b; logic [63:0] array [3:0]; logic [63:0] unitArrayWhole [0:0]; logic [63:0] unitArrayParts [0:0]; assign array[0] = (rand_a << 32) | (rand_a >> 32); assign array[1] = (rand_a << 16) | (rand_a >> 48); assign array[2][3:0] = rand_a[3:0]; always @(rand_b) begin // Intentional non-combinational partial driver array[2][7:4] = rand_a[7:4]; end assign unitArrayWhole[0] = rand_a; assign unitArrayParts[0][1] = rand_a[1]; assign unitArrayParts[0][9] = rand_a[9]; `signal(FOLD_UNARY_LogNot, !const_a[0]); `signal(FOLD_UNARY_Negate, -const_a); `signal(FOLD_UNARY_Not, ~const_a); `signal(FOLD_UNARY_RedAnd, &const_a); `signal(FOLD_UNARY_RedOr, |const_a); `signal(FOLD_UNARY_RedXor, ^const_a); // verilator lint_off WIDTH wire logic [79:0] tmp_FOLD_UNARY_Extend = const_a; wire logic signed [79:0] tmp_FOLD_UNARY_ExtendS = sconst_a; //verilator lint_on WIDTH `signal(FOLD_UNARY_Extend, tmp_FOLD_UNARY_Extend); `signal(FOLD_UNARY_ExtendS, tmp_FOLD_UNARY_ExtendS); `signal(FOLD_BINARY_Add, const_a + const_b); `signal(FOLD_BINARY_And, const_a & const_b); `signal(FOLD_BINARY_Concat, {const_a, const_b}); `signal(FOLD_BINARY_Div, const_a / 64'd3); `signal(FOLD_BINARY_DivS, sconst_a / 64'sd3); `signal(FOLD_BINARY_Eq, const_a == const_b); `signal(FOLD_BINARY_Gt, const_a > const_b); `signal(FOLD_BINARY_GtS, sconst_a > sconst_b); `signal(FOLD_BINARY_Gte, const_a >= const_b); `signal(FOLD_BINARY_GteS, sconst_a >= sconst_b); `signal(FOLD_BINARY_LogAnd, const_a[0] && const_b[0]); `signal(FOLD_BINARY_LogEq, const_a[0] <-> const_b[0]); `signal(FOLD_BINARY_LogIf, const_a[0] -> const_b[0]); `signal(FOLD_BINARY_LogOr, const_a[0] || const_b[0]); `signal(FOLD_BINARY_Lt, const_a < const_b); `signal(FOLD_BINARY_Lt2, const_a < const_a); `signal(FOLD_BINARY_LtS, sconst_a < sconst_b); `signal(FOLD_BINARY_LtS2, sconst_a < sconst_a); `signal(FOLD_BINARY_Lte, const_a <= const_b); `signal(FOLD_BINARY_Lte2, const_a <= const_a); `signal(FOLD_BINARY_LteS, sconst_a <= sconst_b); `signal(FOLD_BINARY_LteS2, sconst_a <= sconst_a); `signal(FOLD_BINARY_ModDiv, const_a % 64'd3); `signal(FOLD_BINARY_ModDivS, sconst_a % 64'sd3); `signal(FOLD_BINARY_Mul, const_a * 64'd3); `signal(FOLD_BINARY_MulS, sconst_a * 64'sd3); `signal(FOLD_BINARY_Neq, const_a != const_b); `signal(FOLD_BINARY_Or, const_a | const_b); `signal(FOLD_BINARY_Pow, const_a ** 64'd2); `signal(FOLD_BINARY_PowSS, sconst_a ** 64'sd2); `signal(FOLD_BINARY_PowSU, sconst_a ** 64'd2); `signal(FOLD_BINARY_PowUS, const_a ** 64'sd2); `signal(FOLD_BINARY_Replicate, {2{const_a}}); `signal(FOLD_BINARY_ShiftL, const_a << 2); `signal(FOLD_BINARY_ShiftR, const_a >> 2); `signal(FOLD_BINARY_ShiftRS, sconst_a >>> 2); `signal(FOLD_BINARY_Sub, const_a - const_b); `signal(FOLD_BINARY_Xor, const_a ^ const_b); `signal(FOLD_ASSOC_BINARY_LHS_OF_RHS_And, (const_a & (const_b & rand_a))); `signal(FOLD_ASSOC_BINARY_LHS_OF_RHS_Or, (const_a | (const_b | rand_a))); `signal(FOLD_ASSOC_BINARY_LHS_OF_RHS_Xor, (const_a ^ (const_b ^ rand_a))); `signal(FOLD_ASSOC_BINARY_LHS_OF_RHS_Add, (const_a + (const_b + rand_a))); `signal(FOLD_ASSOC_BINARY_LHS_OF_RHS_Mul, (const_a * (const_b * rand_a))); `signal(FOLD_ASSOC_BINARY_LHS_OF_RHS_MulS, (sconst_a * (sconst_b * srand_a))); `signal(FOLD_ASSOC_BINARY_LHS_OF_RHS_Concat, {const_a, {const_b, rand_a}}); `signal(FOLD_ASSOC_BINARY_RHS_OF_LHS_And, ((rand_a & const_b) & const_a)); `signal(FOLD_ASSOC_BINARY_RHS_OF_LHS_Or, ((rand_a | const_b) | const_a)); `signal(FOLD_ASSOC_BINARY_RHS_OF_LHS_Xor, ((rand_a ^ const_b) ^ const_a)); `signal(FOLD_ASSOC_BINARY_RHS_OF_LHS_Add, ((rand_a + const_b) + const_a)); `signal(FOLD_ASSOC_BINARY_RHS_OF_LHS_Mul, ((rand_a * const_b) * const_a)); `signal(FOLD_ASSOC_BINARY_RHS_OF_LHS_MulS, ((srand_a * sconst_b) * sconst_a)); `signal(FOLD_ASSOC_BINARY_RHS_OF_LHS_Concat, {{rand_a, const_b}, const_a}); `signal(FOLD_SEL, const_a[3:1]); `signal(SWAP_CONST_IN_COMMUTATIVE_BINARY, rand_a + const_a); `signal(SWAP_NOT_IN_COMMUTATIVE_BINARY, rand_a + ~rand_a); `signal(SWAP_VAR_IN_COMMUTATIVE_BINARY, rand_b + rand_a); `signal(PUSH_BITWISE_OP_THROUGH_CONCAT, 32'h12345678 ^ {8'h0, rand_a[23:0]}); `signal(PUSH_BITWISE_OP_THROUGH_CONCAT_2, 32'h12345678 ^ {rand_b[7:0], rand_a[23:0]}); `signal(PUSH_COMPARE_OP_THROUGH_CONCAT, 4'b1011 == {2'b10, rand_a[1:0]}); `signal(PUSH_REDUCTION_THROUGH_COND_WITH_CONST_BRANCH, |(rand_a[32] ? rand_a[3:0] : 4'h0)); `signal(REPLACE_REDUCTION_OF_CONST_AND, &const_a); `signal(REPLACE_REDUCTION_OF_CONST_OR, |const_a); `signal(REPLACE_REDUCTION_OF_CONST_XOR, ^const_a); `signal(REPLACE_EXTEND, 4'(rand_a[0])); `signal(PUSH_NOT_THROUGH_COND, ~(rand_a[0] ? rand_a[4:0] : 5'hb)); `signal(REMOVE_NOT_NOT, ~~rand_a); `signal(REPLACE_NOT_NEQ, ~(rand_a != rand_b)); `signal(REPLACE_NOT_EQ, ~(srand_a == srand_b)); `signal(REPLACE_NOT_OF_CONST, ~4'd0); `signal(REPLACE_DISTRIBUTIVE_AND_OR_ABAC, ((rand_a >> 10) | (rand_b >> 10)) & ((rand_a >> 10) | (srand_b >> 10))); `signal(REPLACE_DISTRIBUTIVE_AND_OR_ABCA, ((rand_a >> 11) | (rand_b >> 11)) & ((srand_b >> 11) | (rand_a >> 11))); `signal(REPLACE_DISTRIBUTIVE_AND_OR_BAAC, ((rand_b >> 12) | (rand_a >> 12)) & ((rand_a >> 12) | (srand_b >> 12))); `signal(REPLACE_DISTRIBUTIVE_AND_OR_BACA, ((rand_b >> 13) | (rand_a >> 13)) & ((srand_b >> 13) | (rand_a >> 13))); `signal(REPLACE_AND_OF_NOT_AND_NOT, ~rand_a[1] & ~rand_b[1]); `signal(REPLACE_AND_OF_NOT_AND_NEQ, ~rand_a[2] & (rand_b != 64'd2)); `signal(REPLACE_AND_OF_CONST_AND_CONST, const_a & const_b); `signal(REPLACE_AND_WITH_ZERO, 64'd0 & rand_a); `signal(REMOVE_AND_WITH_ONES, -64'd1 & rand_a); `signal(REMOVE_AND_WITH_SELF, ~rand_a & ~rand_a); `signal(REPLACE_CONTRADICTORY_AND, rand_a & ~rand_a); `signal(REPLACE_CONTRADICTORY_AND_3, ~(rand_a + 1) & ((rand_a + 1) & rand_b)); `signal(REPLACE_OR_DISTRIBUTIVE, (rand_a & rand_b) | (rand_a & srand_b)); `signal(REPLACE_DISTRIBUTIVE_OR_AND_ABAC, ((rand_a >> 14) & (rand_b >> 14)) | ((rand_a >> 14) & (srand_b >> 14))); `signal(REPLACE_DISTRIBUTIVE_OR_AND_ABCA, ((rand_a >> 15) & (rand_b >> 15)) | ((srand_b >> 15) & (rand_a >> 15))); `signal(REPLACE_DISTRIBUTIVE_OR_AND_BAAC, ((rand_b >> 16) & (rand_a >> 16)) | ((rand_a >> 16) & (srand_b >> 16))); `signal(REPLACE_DISTRIBUTIVE_OR_AND_BACA, ((rand_b >> 17) & (rand_a >> 17)) | ((srand_b >> 17) & (rand_a >> 17))); `signal(REPLACE_OR_OF_NOT_AND_NOT, ~rand_a[3] | ~rand_b[3]); `signal(REPLACE_OR_OF_NOT_AND_NEQ, ~rand_a[4] | (rand_b != 64'd3)); `signal(REPLACE_OR_OF_CONCAT_ZERO_LHS_AND_CONCAT_RHS_ZERO, {2'd0, rand_a[1:0]} | {rand_b[1:0], 2'd0}); `signal(REPLACE_OR_OF_CONCAT_LHS_ZERO_AND_CONCAT_ZERO_RHS, {rand_a[1:0], 2'd0} | {2'd0, rand_b[1:0]}); `signal(REPLACE_OR_OF_CONST_AND_CONST, const_a | const_b); `signal(REPLACE_OR_WITH_ONES, -64'd1 | rand_a); `signal(REMOVE_OR_WITH_SELF, ~rand_a | ~rand_a); `signal(REMOVE_OR_WITH_ZERO, 64'd0 | rand_a); `signal(REPLACE_TAUTOLOGICAL_OR, rand_a | ~rand_a); `signal(REPLACE_TAUTOLOGICAL_OR_3, ~(rand_a + 1) | ((rand_a + 1) | rand_b)); `signal(REMOVE_SUB_ZERO, rand_a - 64'd0); `signal(REPLACE_SUB_WITH_NOT, rand_a[0] - 1'b1); `signal(REMOVE_REDUNDANT_ZEXT_ON_RHS_OF_SHIFT, rand_a << {2'b0, rand_a[2:0]}); `signal(REPLACE_EQ_OF_CONST_AND_CONST, 4'd0 == 4'd1); `signal(REMOVE_FULL_WIDTH_SEL, rand_a[63:0]); `signal(REMOVE_SEL_FROM_RHS_OF_CONCAT, rand_ba[63:0]); `signal(REMOVE_SEL_FROM_LHS_OF_CONCAT, rand_ba[127:64]); `signal(PUSH_SEL_THROUGH_CONCAT, rand_ba[120:0]); `signal(PUSH_SEL_THROUGH_REPLICATE, rand_aa[0]); `signal(REPLACE_SEL_FROM_CONST, const_a[2]); `signal(REPLACE_CONCAT_OF_CONSTS, {const_a, const_b}); `signal(REPLACE_CONCAT_ZERO_AND_SEL_TOP_WITH_SHIFTR, {62'd0, rand_a[63:62]}); `signal(REPLACE_CONCAT_SEL_BOTTOM_AND_ZERO_WITH_SHIFTL, {rand_a[1:0], 62'd0}); `signal(PUSH_CONCAT_THROUGH_NOTS, {~(rand_a+64'd101), ~(rand_b+64'd101)} ); `signal(REMOVE_CONCAT_OF_ADJOINING_SELS, {rand_a[10:3], rand_a[2:1]}); `signal(REPLACE_NESTED_CONCAT_OF_ADJOINING_SELS_ON_LHS_CAT, {rand_a[2:1], rand_b}); `signal(REPLACE_NESTED_CONCAT_OF_ADJOINING_SELS_ON_RHS_CAT, {rand_b, rand_a[10:3]}); `signal(REPLACE_NESTED_CONCAT_OF_ADJOINING_SELS_ON_LHS, {rand_a[10:3], {rand_a[2:1], rand_b}}); `signal(REPLACE_NESTED_CONCAT_OF_ADJOINING_SELS_ON_RHS, {{rand_b, rand_a[10:3]}, rand_a[2:1]}); `signal(REMOVE_COND_WITH_FALSE_CONDITION, 1'd0 ? rand_a : rand_b); `signal(REMOVE_COND_WITH_TRUE_CONDITION, 1'd1 ? rand_a : rand_b); `signal(REMOVE_COND_WITH_BRANCHES_SAME, rand_a[0] ? ~rand_b : ~rand_b); `signal(SWAP_COND_WITH_NOT_CONDITION, (~rand_a[0] & 1'd1) ? rand_a : rand_b); `signal(SWAP_COND_WITH_NEQ_CONDITION, rand_b != rand_a ? rand_a : rand_b); `signal(PULL_NOTS_THROUGH_COND, rand_a[0] ? ~rand_a[4:0] : ~rand_b[4:0]); `signal(REPLACE_COND_OR_THEN_COND_LHS, (rand_a[0] | rand_b[0] ? (rand_a[0] ? rand_a : rand_b) : srand_a)); `signal(REPLACE_COND_OR_THEN_COND_RHS, (rand_a[0] | rand_b[0] ? (rand_b[0] ? rand_a : rand_b) : srand_a)); `signal(REPLACE_COND_WITH_THEN_BRANCH_COND, rand_a[0] ? rand_a[0] : rand_a[1]); `signal(REPLACE_COND_WITH_THEN_BRANCH_ZERO, rand_a[0] ? 1'd0 : rand_a[1]); `signal(REPLACE_COND_WITH_THEN_BRANCH_ONES, rand_a[0] ? 1'd1 : rand_a[1]); `signal(REPLACE_COND_WITH_ELSE_BRANCH_ZERO, rand_a[0] ? rand_a[1] : 1'd0); `signal(REPLACE_COND_WITH_ELSE_BRANCH_ONES, rand_a[0] ? rand_a[1] : 1'd1); `signal(INLINE_ARRAYSEL_SPLICE, array[0]); `signal(NO_INLINE_ARRAYSEL_SPLICE_PARTIAL, array[2]); `signal(INLINE_ARRAYSEL_UNIT, unitArrayWhole[0]); `signal(NO_INLINE_ARRAYSEL_UNIT_PARTIAL, unitArrayParts[0]); `signal(PUSH_BITWISE_THROUGH_REDUCTION_AND, (&(rand_a + 64'd105)) & (&(rand_b + 64'd108))); `signal(PUSH_BITWISE_THROUGH_REDUCTION_OR, (|(rand_a + 64'd106)) | (|(rand_b + 64'd109))); `signal(PUSH_BITWISE_THROUGH_REDUCTION_XOR, (^(rand_a + 64'd107)) ^ (^(rand_b + 64'd110))); `signal(PUSH_REDUCTION_THROUGH_CONCAT_AND, &{1'd1, rand_b}); `signal(PUSH_REDUCTION_THROUGH_CONCAT_OR, |{1'd1, rand_b}); `signal(PUSH_REDUCTION_THROUGH_CONCAT_XOR, ^{1'd1, rand_b}); `signal(REMOVE_WIDTH_ONE_REDUCTION_AND, &rand_a[0]); `signal(REMOVE_WIDTH_ONE_REDUCTION_OR, |rand_a[0]); `signal(REMOVE_WIDTH_ONE_REDUCTION_XOR, ^rand_a[0]); `signal(REMOVE_XOR_WITH_ZERO, 64'd0 ^ rand_a); `signal(REPLACE_XOR_WITH_SELF, ~rand_a ^ ~rand_a); `signal(REPLACE_XOR_WITH_ONES, -64'd1 ^ rand_a); `signal(REPLACE_COND_DEC, randbit_a ? rand_b - 64'b1 : rand_b); `signal(REPLACE_COND_INC, randbit_a ? rand_b + 64'b1 : rand_b); `signal(NO_REPLACE_COND_DEC, randbit_a ? rand_b - 64'hf000000000000000 : rand_b); `signal(NO_REPLACE_COND_INC, randbit_a ? rand_b + 64'hf000000000000000 : rand_b); `signal(REPLACE_LOGAND_WITH_AND, rand_a[0] && rand_a[1]); `signal(REPLACE_LOGOR_WITH_OR, rand_a[0] || rand_a[1]); `signal(RIGHT_LEANING_ASSOC, (((rand_a + rand_b) + rand_a) + rand_b)); `signal(RIGHT_LEANING_CONCET, {{{rand_a, rand_b}, rand_a}, rand_b}); // Operators that should work wiht mismatched widths `signal(MISMATCHED_ShiftL,const_a << 4'd2); `signal(MISMATCHED_ShiftR,const_a >> 4'd2); `signal(MISMATCHED_ShiftRS, const_a >> 4'd2); `signal(MISMATCHED_PowUU, rand_a ** 4'd5); `signal(MISMATCHED_PowSS, srand_a ** 4'sd5); `signal(MISMATCHED_PowSU, srand_b ** 4'd5); `signal(MISMATCHED_PowUS, rand_b ** 4'sd5); // Some selects need extra temporaries wire [63:0] sel_from_cond = rand_a[0] ? rand_a : const_a; wire [63:0] sel_from_shiftl = rand_a << 10; wire [31:0] sel_from_sel = rand_a[10+:32]; `signal(PUSH_SEL_THROUGH_COND, sel_from_cond[2]); `signal(PUSH_SEL_THROUGH_SHIFTL, sel_from_shiftl[20:0]); `signal(REPLACE_SEL_FROM_SEL, sel_from_sel[4:3]); logic [2:0] sel_from_partial_tmp;; always_comb begin sel_from_partial_tmp[1:0] = 2'd0; if (rand_a[0]) begin sel_from_partial_tmp[0] = rand_b[0]; end end `signal(PUSH_SEL_THROUGH_SPLICE, sel_from_partial_tmp[1:0]); // Asscending ranges `signal(ASCENDNG_SEL, arand_a[0:4]); // verilator lint_off ASCRANGE wire [0:7] ascending_assign; // verilator lint_on ASCRANGE assign ascending_assign[0:3] = arand_a[4:7]; assign ascending_assign[4:7] = arand_b[0:3]; `signal(ASCENDING_ASSIGN, ascending_assign); // Special cases to be covered `signal(REPLICATE_WIDTH, {4'd8{rand_a[0]}}); // Replicate count unsigned, but MSB set if ($bits(REPLICATE_WIDTH) != 8) $fatal("%0d != 8", $bits(REPLICATE_WIDTH)); // Sel from not requires the operand to have a sinle sink, so can't use // the chekc due to the raw expression referencing the operand wire [63:0] sel_from_not_tmp = ~(rand_a >> rand_b[2:0] << rand_a[3:0]); wire sel_from_not = sel_from_not_tmp[2]; always @(posedge randbit_a) if ($c(0)) $display(sel_from_not); // Do not remove signal // Assigned at the end to avoid inlining by other passes assign const_a = 64'h0123456789abcdef; assign const_b = 64'h98badefc10325647; assign sconst_a = 64'hfedcba9876543210; assign sconst_b = 64'hba0123456789cdef; endmodule verilator-5.044/test_regress/t/t_randomize_complex_dynamic_arrays.py0000755000542200017500000000104615125463617026606 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_struct_param.v0000644000542200017500000000301315125463617022314 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Matt Myers. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkd(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on package config_pkg; typedef struct packed { int UPPER0; struct packed { int USE_QUAD0; int USE_QUAD1; int USE_QUAD2; } mac; int UPPER2; } config_struct_t; function automatic config_struct_t static_config(int selector); config_struct_t return_config; return_config = '0; return_config.UPPER0 = 10; return_config.UPPER2 = 20; return_config.mac.USE_QUAD0 = 4; return_config.mac.USE_QUAD2 = 6; case (selector) 1: return_config.mac.USE_QUAD1 = 5; endcase return return_config; endfunction endpackage module t; import config_pkg::*; localparam config_struct_t MY_CONFIG = static_config(1); struct_submodule #(.MY_CONFIG(MY_CONFIG)) a_submodule_I (); endmodule module struct_submodule import config_pkg::*; #( parameter config_struct_t MY_CONFIG = '0 ); initial begin `checkd(MY_CONFIG.UPPER0, 10); `checkd(MY_CONFIG.mac.USE_QUAD0, 4); `checkd(MY_CONFIG.mac.USE_QUAD1, 5); `checkd(MY_CONFIG.mac.USE_QUAD2, 6); `checkd(MY_CONFIG.UPPER2, 20); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_math_shift_rep.v0000644000542200017500000000402415125463617022607 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; //bug765; disappears if add this wire //wire [7:0] a = (crc[7] ? {7'b0,crc[0]} : crc[7:0]); // favor low values wire [7:0] a = crc[7:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [15:0] y; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .y (y[15:0]), // Inputs .a (a[7:0])); // Aggregate outputs into a single result vector wire [63:0] result = {48'h0, y}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h0 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs y, // Inputs a ); input signed [7:0] a; output [15:0] y; // verilator lint_off WIDTH assign y = ~66'd0 <<< {4{a}}; // verilator lint_on WIDTH endmodule verilator-5.044/test_regress/t/t_nba_assign_on_rhs.v0000644000542200017500000000133415125463617023270 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; int x; int y; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 0) begin x <= 1; end else if (cyc == 1) begin // verilator lint_off ASSIGNEQEXPR y <= (x = 2); // verilator lint_on ASSIGNEQEXPR end else begin if (x != 2) $stop; if (y != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.044/test_regress/t/t_mem_func.py0000755000542200017500000000073415125463617021576 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_constraint_mode.py0000755000542200017500000000104615125463617023172 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_preproc_kwd_bad.py0000755000542200017500000000103515125463617023125 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, verilator_flags2=['--no-std'], expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_event_control_assign.py0000755000542200017500000000114215125463617024224 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile( verilator_flags2=["--binary"], make_main=False, # Multithreading would cause a warning on event assignments threads=1) test.execute() test.passes() verilator-5.044/test_regress/t/t_flag_relinc.v0000644000542200017500000000060715125463617022063 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; t_flag_relinc_sub sub (); endmodule verilator-5.044/test_regress/t/t_clocking_out_on_change.py0000755000542200017500000000077115125463617024467 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_dpi_result_type.out0000644000542200017500000000252515125463617023374 0ustar mahmoudyfreeshelli_void 0 i_chandle 0 i_string 0 i_bit 0 i_logic 0 i_chandle_t 0 i_string_t 0 i_bit_t 0 i_logic_t 0 i_array_2_state_1 0 i_array_2_state_32 0 i_struct_2_state_1 0 i_struct_2_state_32 0 i_union_2_state_1 0 i_union_2_state_32 0 e_void 0 e_chandle 0 e_string 0 e_bit 0 e_logic 0 e_chandle_t 0 e_string_t 0 e_bit_t 0 e_logic_t 0 e_array_2_state_1 0 e_array_2_state_32 0 e_struct_2_state_1 0 e_struct_2_state_32 0 e_union_2_state_1 0 e_union_2_state_32 0 i_void 1 i_chandle 1 i_string 1 i_bit 1 i_logic 1 i_chandle_t 1 i_string_t 1 i_bit_t 1 i_logic_t 1 i_array_2_state_1 1 i_array_2_state_32 1 i_struct_2_state_1 1 i_struct_2_state_32 1 i_union_2_state_1 1 i_union_2_state_32 1 e_void 1 e_chandle 1 e_string 1 e_bit 1 e_logic 1 e_chandle_t 1 e_string_t 1 e_bit_t 1 e_logic_t 1 e_array_2_state_1 1 e_array_2_state_32 1 e_struct_2_state_1 1 e_struct_2_state_32 1 e_union_2_state_1 1 e_union_2_state_32 1 i_void 2 i_chandle 2 i_string 2 i_bit 2 i_logic 2 i_chandle_t 2 i_string_t 2 i_bit_t 2 i_logic_t 2 i_array_2_state_1 2 i_array_2_state_32 2 i_struct_2_state_1 2 i_struct_2_state_32 2 i_union_2_state_1 2 i_union_2_state_32 2 e_void 2 e_chandle 2 e_string 2 e_bit 2 e_logic 2 e_chandle_t 2 e_string_t 2 e_bit_t 2 e_logic_t 2 e_array_2_state_1 2 e_array_2_state_32 2 e_struct_2_state_1 2 e_struct_2_state_32 2 e_union_2_state_1 2 e_union_2_state_32 2 *-* All Finished *-* verilator-5.044/test_regress/t/t_flag_no_unlimited_stack.v0000644000542200017500000000035215125463617024457 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; endmodule verilator-5.044/test_regress/t/t_class_ref_ref.v0000644000542200017500000000061215125463617022407 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls#(type T = bit); endclass module t; Cls#(bit) cb; Cls#(Cls#(bit)) ccb; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_typedef_signed.py0000755000542200017500000000073415125463617022776 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_virtual_interface_delayed.v0000644000542200017500000000201515125463617025006 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); // verilog_format: on interface Ifc; bit [7:0] rdata; endinterface class drv_c; virtual Ifc vif; virtual task run(); #100; `checkh(vif.rdata, 8'haa); #100; `checkh(vif.rdata, 8'haa); #100; endtask endclass module dut (output wire [7:0] rd_val); assign rd_val = 8'haa; endmodule module m; drv_c d_0; Ifc u_Ifc (); dut u_dut (.rd_val (u_Ifc.rdata)); initial begin d_0 = new(); d_0.vif = u_Ifc; //u_Ifc.rdata = 10; d_0.run(); $write("*-* All Finished *-*\n"); $finish(2); end endmodule verilator-5.044/test_regress/t/t_math_cmp.py0000755000542200017500000000073415125463617021575 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_class_param_subtype_bad_paren.py0000755000542200017500000000110615125463617026032 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_class_param_subtype.v" test.lint(fails=True, v_flags2=['+define+BAD_PAREN'], expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_func_under2.v0000644000542200017500000000174515125463617022034 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug598 module t (/*AUTOARG*/ // Outputs val, // Inputs clk ); input clk; output integer val; integer dbg_addr = 0; function func1; input en; input [31:0] a; func1 = en && (a == 1); endfunction function func2; input en; input [31:0] a; func2 = en && (a == 2); endfunction always @(posedge clk) begin case( 1'b1 ) // This line is OK: func1(1'b1, dbg_addr) : val = 1; // This fails: // %Error: Internal Error: test.v:23: ../V3Task.cpp:993: Function not underneath a statement func2(1'b1, dbg_addr) : val = 2; default : val = 0; endcase // $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_order_dpi_export_2.cpp0000644000542200017500000000213615125463617023723 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2021 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include void toggle_other_clk(svBit val) { set_other_clk(val); } int main(int argc, char* argv[]) { VM_PREFIX* const tb = new VM_PREFIX; tb->contextp()->commandArgs(argc, argv); bool clk = true; while (!tb->contextp()->gotFinish()) { // Timeout if (tb->contextp()->time() > 100000) break; // Toggle and set main clock clk = !clk; tb->clk = clk; // Eval tb->eval(); // Advance time tb->contextp()->timeInc(500); } delete tb; return 0; } verilator-5.044/test_regress/t/t_inst_param_override_bad.py0000755000542200017500000000076615125463617024654 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_tri_pullup.cpp0000644000542200017500000000272615125463617022336 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2008 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE VM_PREFIX* tb = nullptr; double sc_time_stamp() { return 0; } bool check() { bool pass; int Z, Y, X; if (tb->OE) { Z = tb->A; Y = tb->A; X = tb->A; } else { Z = 1; Y = 0; X = 1; } #ifdef TEST_VERBOSE bool verbose = true; #else bool verbose = false; #endif if (tb->Z == Z && tb->Y == Y && tb->X == X) { if (verbose) printf("PASS: "); pass = true; } else { printf("%%E-FAIL: "); verbose = true; pass = false; } if (verbose) printf("OE=%d A=%d X=%d xexp=%d Y=%d yexp=%d Z=%d zexp=%d\n", tb->OE, tb->A, tb->X, X, tb->Y, Y, tb->Z, Z); return pass; } int main() { Verilated::debug(0); tb = new VM_PREFIX{"tb"}; // loop through every possibility and check the result bool pass = true; for (tb->OE = 0; tb->OE < 2; tb->OE++) { for (tb->A = 0; tb->A < 2; tb->A++) { tb->eval(); if (!check()) pass = false; } } if (pass) { VL_PRINTF("*-* All Finished *-*\n"); tb->final(); } else { vl_fatal(__FILE__, __LINE__, "top", "Unexpected results from pullup test\n"); } VL_DO_DANGLING(delete tb, tb); return 0; } verilator-5.044/test_regress/t/t_math_red.py0000755000542200017500000000073415125463617021570 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_type_compare.v0000644000542200017500000000350515125463617022305 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module Sub #(parameter type T = type(logic[11:0])); endmodule module t; int case_ok; Sub #(.T(int)) sub(); typedef logic [12:0] logic12_t; // Generate if if (type(logic[12:0]) !== type(logic[12:0])) initial $stop; if (type(logic[12:0]) != type(logic12_t)) initial $stop; if (type(logic[12:0]) !== type(logic12_t)) initial $stop; if (type(logic[22:0]) == type(logic12_t)) initial $stop; if (type(logic[22:0]) === type(logic12_t)) initial $stop; // Generate case case (type(real)) type(int): initial $stop; type(real): ; default: initial $stop; endcase initial begin if (type(real) == type(logic[12:0])) $stop; if (type(real) === type(logic[12:0])) $stop; if (type(real) != type(real)) $stop; if (type(real) !== type(real)) $stop; if (type(logic[12:0]) !== type(logic[12:0])) $stop; if (type(logic[12:0]) != type(logic12_t)) $stop; if (type(logic[12:0]) !== type(logic12_t)) $stop; if (type(logic[22:0]) == type(logic12_t)) $stop; if (type(logic[22:0]) === type(logic12_t)) $stop; // Item selected case (type(real)) type(real): case_ok = 1; type(int): $stop; type(chandle): $stop; default: $stop; endcase if (case_ok != 1) $stop; // Default selected case (type(real)) type(int): $stop; default: case_ok = 2; endcase if (case_ok != 2) $stop; // No body selected case (type(real)) type(int): $stop; endcase if (case_ok != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_trace_complex_structs_fst_sc.out0000644000542200017500000001243615125463617026140 0ustar mahmoudyfreeshell$date Sat Apr 5 13:56:24 2025 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end $attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $scope module $unit $end $var bit 1 ! global_bit $end $upscope $end $scope module t $end $var wire 1 " clk $end $var integer 32 # cyc [31:0] $end $scope struct v_strp $end $var bit 1 $ b1 $end $var bit 1 % b0 $end $upscope $end $scope struct v_strp_strp $end $scope struct x1 $end $var bit 1 & b1 $end $var bit 1 ' b0 $end $upscope $end $scope struct x0 $end $var bit 1 ( b1 $end $var bit 1 ) b0 $end $upscope $end $upscope $end $scope union v_unip_strp $end $scope struct x1 $end $var bit 1 * b1 $end $var bit 1 + b0 $end $upscope $end $scope struct x0 $end $var bit 1 * b1 $end $var bit 1 + b0 $end $upscope $end $upscope $end $var bit 2 , v_arrp [2:1] $end $var bit 2 - v_arrp_arrp[3] [2:1] $end $var bit 2 . v_arrp_arrp[4] [2:1] $end $scope struct v_arrp_strp[3] $end $var bit 1 / b1 $end $var bit 1 0 b0 $end $upscope $end $scope struct v_arrp_strp[4] $end $var bit 1 1 b1 $end $var bit 1 2 b0 $end $upscope $end $var bit 1 3 v_arru[1] $end $var bit 1 4 v_arru[2] $end $var bit 1 5 v_arru_arru[3][1] $end $var bit 1 6 v_arru_arru[3][2] $end $var bit 1 7 v_arru_arru[4][1] $end $var bit 1 8 v_arru_arru[4][2] $end $var bit 2 9 v_arru_arrp[3] [2:1] $end $var bit 2 : v_arru_arrp[4] [2:1] $end $scope struct v_arru_strp[3] $end $var bit 1 ; b1 $end $var bit 1 < b0 $end $upscope $end $scope struct v_arru_strp[4] $end $var bit 1 = b1 $end $var bit 1 > b0 $end $upscope $end $var real 64 ? v_real $end $var real 64 @ v_arr_real[0] $end $var real 64 A v_arr_real[1] $end $var longint 64 B v_chandle [63:0] $end $scope struct v_str32x2[0] $end $var logic 32 C data [31:0] $end $upscope $end $scope struct v_str32x2[1] $end $var logic 32 D data [31:0] $end $upscope $end $attrbegin misc 07 "" 1 $end $var int 32 E v_enumed [31:0] $end $attrbegin misc 07 "" 1 $end $var int 32 F v_enumed2 [31:0] $end $attrbegin misc 07 "" 2 $end $var logic 3 G v_enumb [2:0] $end $scope struct v_enumb2_str $end $attrbegin misc 07 "" 2 $end $var logic 3 H a [2:0] $end $attrbegin misc 07 "" 2 $end $var logic 3 I b [2:0] $end $upscope $end $var logic 8 J unpacked_array[-2] [7:0] $end $var logic 8 K unpacked_array[-1] [7:0] $end $var logic 8 L unpacked_array[0] [7:0] $end $var bit 1 M LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end $scope module unnamedblk1 $end $var integer 32 N b [31:0] $end $scope module unnamedblk2 $end $var integer 32 O a [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b00000000000000000000000000000000 O b00000000000000000000000000000000 N 0M b00000000 L b00000000 K b00000000 J b000 I b000 H b000 G b00000000000000000000000000000000 F b00000000000000000000000000000000 E b00000000000000000000000000000000 D b00000000000000000000000011111111 C b0000000000000000000000000000000000000000000000000000000000000000 B r0 A r0 @ r0 ? 0> 0= 0< 0; b00 : b00 9 08 07 06 05 04 03 02 01 00 0/ b00 . b00 - b00 , 0+ 0* 0) 0( 0' 0& 0% 0$ b00000000000000000000000000000000 # 0" 1! $end #10 1" b00000000000000000000000000000001 # 1$ 1% 1& 1' 1( 1) 1* 1+ b11 , b11 - b11 . 1/ 10 11 12 b11 9 b11 : 1; 1< 1= 1> r0.1 ? r0.2 @ r0.3 A b00000000000000000000000011111110 C b00000000000000000000000000000001 D b00000000000000000000000000000001 E b00000000000000000000000000000010 F b111 G b00000000000000000000000000000101 N b00000000000000000000000000000101 O #15 0" #20 1" b110 G b00000000000000000000000000000100 F b00000000000000000000000000000010 E b00000000000000000000000000000010 D b00000000000000000000000011111101 C r0.6 A r0.4 @ r0.2 ? 0> 0= 0< 0; b00 : b00 9 02 01 00 0/ b00 . b00 - b00 , 0+ 0* 0) 0( 0' 0& 0% 0$ b00000000000000000000000000000010 # b111 H b111 I #25 0" #30 1" b110 I b110 H b00000000000000000000000000000011 # 1$ 1% 1& 1' 1( 1) 1* 1+ b11 , b11 - b11 . 1/ 10 11 12 b11 9 b11 : 1; 1< 1= 1> r0.3 ? r0.6000000000000001 @ r0.8999999999999999 A b00000000000000000000000011111100 C b00000000000000000000000000000011 D b00000000000000000000000000000011 E b00000000000000000000000000000110 F b101 G #35 0" #40 1" b100 G b00000000000000000000000000001000 F b00000000000000000000000000000100 E b00000000000000000000000000000100 D b00000000000000000000000011111011 C r1.2 A r0.8 @ r0.4 ? 0> 0= 0< 0; b00 : b00 9 02 01 00 0/ b00 . b00 - b00 , 0+ 0* 0) 0( 0' 0& 0% 0$ b00000000000000000000000000000100 # b101 H b101 I #45 0" #50 1" b100 I b100 H b00000000000000000000000000000101 # 1$ 1% 1& 1' 1( 1) 1* 1+ b11 , b11 - b11 . 1/ 10 11 12 b11 9 b11 : 1; 1< 1= 1> r0.5 ? r1 @ r1.5 A b00000000000000000000000011111010 C b00000000000000000000000000000101 D b00000000000000000000000000000101 E b00000000000000000000000000001010 F b011 G #55 0" #60 1" b010 G b00000000000000000000000000001100 F b00000000000000000000000000000110 E b00000000000000000000000000000110 D b00000000000000000000000011111001 C r1.8 A r1.2 @ r0.6 ? 0> 0= 0< 0; b00 : b00 9 02 01 00 0/ b00 . b00 - b00 , 0+ 0* 0) 0( 0' 0& 0% 0$ b00000000000000000000000000000110 # b011 H b011 I #64 verilator-5.044/test_regress/t/t_concat_large.v0000644000542200017500000000073315125463617022237 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2015 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [32767:0] a; initial begin // verilator lint_off WIDTHCONCAT a = {32768{1'b1}}; // verilator lint_on WIDTHCONCAT if (a[32000] != 1'b1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_sys_fstrobe.v0000644000542200017500000000242615125463617022161 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" module t(/*AUTOARG*/ // Inputs clk ); input clk; int cyc = 0; int fd; // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 5) begin fd = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/open.log"}, "w"); end else if (cyc == 10) begin $fstrobe(fd, "[%0t] cyc=%0d", $time, cyc); $fstrobe(fd, "[%0t] cyc=%0d also", $time, cyc); end else if (cyc == 17) begin $fstrobeb(fd, cyc, "b"); end else if (cyc == 18) begin $fstrobeh(fd, cyc, "h"); end else if (cyc == 19) begin $fstrobeo(fd, cyc, "o"); end else if (cyc == 22) begin $fstrobe(fd, "[%0t] cyc=%0d new-strobe", $time, cyc); end else if (cyc == 24) begin $monitoroff; end else if (cyc == 26) begin $monitoron; end else if (cyc == 27) begin $fclose(fd); end else if (cyc == 30) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.044/test_regress/t/t_gen_mislevel.v0000644000542200017500000000126215125463617022265 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 /// We define the modules in "backward" order. module d; endmodule module b; generate if (1) begin c c1 (); c c2 (); end endgenerate endmodule module c; generate if (1) begin d d1 (); d d2 (); end endgenerate endmodule module a; generate if (1) begin b b1 (); b b2 (); end endgenerate endmodule module t; a a1 (); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_class_param_extends2.py0000755000542200017500000000073415125463617024106 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_tri_array_bufif.py0000755000542200017500000000073415125463617023154 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_math_synmul_mul.v0000644000542200017500000120467415125463617023046 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Mahesh Kumashikar // SPDX-License-Identifier: CC0-1.0 module t_math_synmul_mul (/*AUTOARG*/ // Outputs product_d4, // Inputs clk, enable, negate, datA, datB ); input clk; input enable; input negate; input [31:0] datA; input [31:0] datB; // verilator lint_off UNOPTFLAT output reg [64:0] product_d4; reg [33:0] datA_d1r; reg [33:0] datB_d1r; always @ (posedge clk) begin if (enable) begin datA_d1r <= {2'b0,datA}; datB_d1r <= {2'b0,datB}; // The extra multiplier bits were for signed, for this // test we've ripped that out if (negate) $stop; end end reg en_d1; reg en_d2; reg en_d3; always @ (posedge clk) begin en_d1 <= enable; en_d2 <= en_d1; en_d3 <= en_d2; end wire [63:0] prod_d3; smmultiplier_34_34 mul (.OPA(datA_d1r), .OPB(datB_d1r), .RESULT(prod_d3), /*AUTOINST*/ // Inputs .clk (clk), .en_d1 (en_d1), .en_d2 (en_d2)); always @ (posedge clk) begin if (en_d3) begin product_d4 <= {1'b0,prod_d3}; end end endmodule // The below was originally generated by the "Synthesizable Arithmetic Module Generator" // at http://modgen.fysel.ntnu.no/~pihl/iwlas98/ then cleaned up by hand. // Unfortunately the generator no longer appears available. Please contact // us if you know otherwise. // verilog_format: off module smmultiplier_34_34 ( input clk, input en_d1, input en_d2, input [33:0] OPA, input [33:0] OPB, output [63:0] RESULT ); wire [628:0] PPBIT; wire [66:0] INT_CARRY; wire [66:0] INT_SUM; smboothcoder_34_34 db (.OPA(OPA[33:0]), .OPB(OPB[33:0]), .SUMMAND(PPBIT[628:0]) ); smwallace_34_34 dw (.SUMMAND(PPBIT[628:0]), .CARRY(INT_CARRY[66:1]), .SUM(INT_SUM[66:0]), /*AUTOINST*/ // Inputs .clk (clk), .en_d1 (en_d1), .en_d2 (en_d2)); assign INT_CARRY[0] = 1'b0; smdblcadder_128_128 dd (.OPA(INT_SUM[63:0]), .OPB(INT_CARRY[63:0]), .CIN (1'b0), .SUM(RESULT)); endmodule module smdblcadder_128_128 (OPA, OPB, CIN, SUM); input [63:0] OPA; input [63:0] OPB; input CIN; output [63:0] SUM; wire [63:0] INTPROP; wire [63:0] INTGEN; wire [0:0] PBIT; wire [63:0] CARRY; smprestage_128 dp (OPA[63:0], OPB[63:0], CIN, INTPROP, INTGEN); smdblctree_128 dd (INTPROP[63:0], INTGEN[63:0], CARRY[63:0], PBIT); smxorstage_128 dx (OPA[63:0], OPB[63:0], PBIT[0], CARRY[63:0], SUM); endmodule module smdblctree_128 (PIN, GIN, GOUT, POUT); input [63:0] PIN; input [63:0] GIN; output [63:0] GOUT; output [0:0] POUT; wire [63:0] INTPROP_0; wire [63:0] INTGEN_0; wire [63:0] INTPROP_1; wire [63:0] INTGEN_1; wire [63:0] INTPROP_2; wire [63:0] INTGEN_2; wire [63:0] INTPROP_3; wire [63:0] INTGEN_3; wire [63:0] INTPROP_4; wire [63:0] INTGEN_4; wire [63:0] INTPROP_5; wire [63:0] INTGEN_5; smdblc_0_128 ddb0 (.PIN(PIN), .GIN(GIN), .POUT(INTPROP_0), .GOUT(INTGEN_0) ); smdblc_1_128 ddb1 (.PIN(INTPROP_0), .GIN(INTGEN_0), .POUT(INTPROP_1), .GOUT(INTGEN_1) ); smdblc_2_128 ddb2 (.PIN(INTPROP_1), .GIN(INTGEN_1), .POUT(INTPROP_2), .GOUT(INTGEN_2) ); smdblc_3_128 ddb3 (.PIN(INTPROP_2), .GIN(INTGEN_2), .POUT(INTPROP_3), .GOUT(INTGEN_3) ); smdblc_4_128 ddb4 (.PIN(INTPROP_3), .GIN(INTGEN_3), .POUT(INTPROP_4), .GOUT(INTGEN_4) ); smdblc_5_128 ddb5 (.PIN(INTPROP_4), .GIN(INTGEN_4), .POUT(INTPROP_5), .GOUT(INTGEN_5) ); smdblc_6_128 ddb6 (.PIN(INTPROP_5), .GIN(INTGEN_5), .POUT(POUT), .GOUT(GOUT) ); endmodule module smwallace_34_34 ( input clk, input en_d1, input en_d2, input [628:0] SUMMAND, output [65:0] CARRY, output [66:0] SUM ); wire [628:0] LATCHED_PP; wire [551:0] INT_CARRY; wire [687:0] INT_SUM; smffa dla0 (.D(SUMMAND[0]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[0]) ); smffa dla1 (.D(SUMMAND[1]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[1]) ); smhalfadder dha0 (.DATA_A (LATCHED_PP[0]), .DATA_B (LATCHED_PP[1]), .SAVE (INT_SUM[0]), .CARRY (INT_CARRY[0]) ); smffb dla2 (.D(INT_SUM[0]), .clk(clk), .en_d2(en_d2), .Q(SUM[0]) ); smffb dla3 (.D(INT_CARRY[0]), .clk(clk), .en_d2(en_d2), .Q(CARRY[0]) ); smffa dla4 (.D(SUMMAND[2]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[2]) ); assign INT_SUM[1] = LATCHED_PP[2]; assign CARRY[1] = 1'b0; smffb dla5 (.D(INT_SUM[1]), .clk(clk), .en_d2(en_d2), .Q(SUM[1]) ); smffa dla6 (.D(SUMMAND[3]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[3]) ); smffa dla7 (.D(SUMMAND[4]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[4]) ); smffa dla8 (.D(SUMMAND[5]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[5]) ); smfulladder dfa0 (.DATA_A (LATCHED_PP[3]), .DATA_B (LATCHED_PP[4]), .DATA_C (LATCHED_PP[5]), .SAVE (INT_SUM[2]), .CARRY (INT_CARRY[1]) ); smffb dla9 (.D(INT_SUM[2]), .clk(clk), .en_d2(en_d2), .Q(SUM[2]) ); smffb dla10 (.D(INT_CARRY[1]), .clk(clk), .en_d2(en_d2), .Q(CARRY[2]) ); smffa dla11 (.D(SUMMAND[6]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[6]) ); smffa dla12 (.D(SUMMAND[7]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[7]) ); smhalfadder dha1 (.DATA_A (LATCHED_PP[6]), .DATA_B (LATCHED_PP[7]), .SAVE (INT_SUM[3]), .CARRY (INT_CARRY[2]) ); smffb dla13 (.D(INT_SUM[3]), .clk(clk), .en_d2(en_d2), .Q(SUM[3]) ); smffb dla14 (.D(INT_CARRY[2]), .clk(clk), .en_d2(en_d2), .Q(CARRY[3]) ); smffa dla15 (.D(SUMMAND[8]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[8]) ); smffa dla16 (.D(SUMMAND[9]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[9]) ); smffa dla17 (.D(SUMMAND[10]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[10]) ); smfulladder dfa1 (.DATA_A (LATCHED_PP[8]), .DATA_B (LATCHED_PP[9]), .DATA_C (LATCHED_PP[10]), .SAVE (INT_SUM[4]), .CARRY (INT_CARRY[4]) ); smffa dla18 (.D(SUMMAND[11]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[11]) ); assign INT_SUM[5] = LATCHED_PP[11]; smhalfadder dha2 (.DATA_A (INT_SUM[4]), .DATA_B (INT_SUM[5]), .SAVE (INT_SUM[6]), .CARRY (INT_CARRY[3]) ); smffb dla19 (.D(INT_SUM[6]), .clk(clk), .en_d2(en_d2), .Q(SUM[4]) ); smffb dla20 (.D(INT_CARRY[3]), .clk(clk), .en_d2(en_d2), .Q(CARRY[4]) ); smffa dla21 (.D(SUMMAND[12]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[12]) ); smffa dla22 (.D(SUMMAND[13]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[13]) ); smffa dla23 (.D(SUMMAND[14]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[14]) ); smfulladder dfa2 (.DATA_A (LATCHED_PP[12]), .DATA_B (LATCHED_PP[13]), .DATA_C (LATCHED_PP[14]), .SAVE (INT_SUM[7]), .CARRY (INT_CARRY[6]) ); smhalfadder dha3 (.DATA_A (INT_SUM[7]), .DATA_B (INT_CARRY[4]), .SAVE (INT_SUM[8]), .CARRY (INT_CARRY[5]) ); smffb dla24 (.D(INT_SUM[8]), .clk(clk), .en_d2(en_d2), .Q(SUM[5]) ); smffb dla25 (.D(INT_CARRY[5]), .clk(clk), .en_d2(en_d2), .Q(CARRY[5]) ); smffa dla26 (.D(SUMMAND[15]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[15]) ); smffa dla27 (.D(SUMMAND[16]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[16]) ); smffa dla28 (.D(SUMMAND[17]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[17]) ); smfulladder dfa3 (.DATA_A (LATCHED_PP[15]), .DATA_B (LATCHED_PP[16]), .DATA_C (LATCHED_PP[17]), .SAVE (INT_SUM[9]), .CARRY (INT_CARRY[8]) ); smffa dla29 (.D(SUMMAND[18]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[18]) ); smffa dla30 (.D(SUMMAND[19]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[19]) ); smhalfadder dha4 (.DATA_A (LATCHED_PP[18]), .DATA_B (LATCHED_PP[19]), .SAVE (INT_SUM[10]), .CARRY (INT_CARRY[9]) ); smfulladder dfa4 (.DATA_A (INT_SUM[9]), .DATA_B (INT_SUM[10]), .DATA_C (INT_CARRY[6]), .SAVE (INT_SUM[11]), .CARRY (INT_CARRY[7]) ); smffb dla31 (.D(INT_SUM[11]), .clk(clk), .en_d2(en_d2), .Q(SUM[6]) ); smffb dla32 (.D(INT_CARRY[7]), .clk(clk), .en_d2(en_d2), .Q(CARRY[6]) ); smffa dla33 (.D(SUMMAND[20]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[20]) ); smffa dla34 (.D(SUMMAND[21]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[21]) ); smffa dla35 (.D(SUMMAND[22]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[22]) ); smfulladder dfa5 (.DATA_A (LATCHED_PP[20]), .DATA_B (LATCHED_PP[21]), .DATA_C (LATCHED_PP[22]), .SAVE (INT_SUM[12]), .CARRY (INT_CARRY[11]) ); smffa dla36 (.D(SUMMAND[23]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[23]) ); assign INT_SUM[13] = LATCHED_PP[23]; smfulladder dfa6 (.DATA_A (INT_SUM[12]), .DATA_B (INT_SUM[13]), .DATA_C (INT_CARRY[8]), .SAVE (INT_SUM[14]), .CARRY (INT_CARRY[12]) ); assign INT_SUM[15] = INT_CARRY[9]; smhalfadder dha5 (.DATA_A (INT_SUM[14]), .DATA_B (INT_SUM[15]), .SAVE (INT_SUM[16]), .CARRY (INT_CARRY[10]) ); smffb dla37 (.D(INT_SUM[16]), .clk(clk), .en_d2(en_d2), .Q(SUM[7]) ); smffb dla38 (.D(INT_CARRY[10]), .clk(clk), .en_d2(en_d2), .Q(CARRY[7]) ); smffa dla39 (.D(SUMMAND[24]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[24]) ); smffa dla40 (.D(SUMMAND[25]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[25]) ); smffa dla41 (.D(SUMMAND[26]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[26]) ); smfulladder dfa7 (.DATA_A (LATCHED_PP[24]), .DATA_B (LATCHED_PP[25]), .DATA_C (LATCHED_PP[26]), .SAVE (INT_SUM[17]), .CARRY (INT_CARRY[14]) ); smffa dla42 (.D(SUMMAND[27]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[27]) ); smffa dla43 (.D(SUMMAND[28]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[28]) ); smffa dla44 (.D(SUMMAND[29]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[29]) ); smfulladder dfa8 (.DATA_A (LATCHED_PP[27]), .DATA_B (LATCHED_PP[28]), .DATA_C (LATCHED_PP[29]), .SAVE (INT_SUM[18]), .CARRY (INT_CARRY[15]) ); smfulladder dfa9 (.DATA_A (INT_SUM[17]), .DATA_B (INT_SUM[18]), .DATA_C (INT_CARRY[11]), .SAVE (INT_SUM[19]), .CARRY (INT_CARRY[16]) ); smhalfadder dha6 (.DATA_A (INT_SUM[19]), .DATA_B (INT_CARRY[12]), .SAVE (INT_SUM[20]), .CARRY (INT_CARRY[13]) ); smffb dla45 (.D(INT_SUM[20]), .clk(clk), .en_d2(en_d2), .Q(SUM[8]) ); smffb dla46 (.D(INT_CARRY[13]), .clk(clk), .en_d2(en_d2), .Q(CARRY[8]) ); smffa dla47 (.D(SUMMAND[30]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[30]) ); smffa dla48 (.D(SUMMAND[31]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[31]) ); smffa dla49 (.D(SUMMAND[32]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[32]) ); smfulladder dfa10 (.DATA_A (LATCHED_PP[30]), .DATA_B (LATCHED_PP[31]), .DATA_C (LATCHED_PP[32]), .SAVE (INT_SUM[21]), .CARRY (INT_CARRY[18]) ); smffa dla50 (.D(SUMMAND[33]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[33]) ); smffa dla51 (.D(SUMMAND[34]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[34]) ); smhalfadder dha7 (.DATA_A (LATCHED_PP[33]), .DATA_B (LATCHED_PP[34]), .SAVE (INT_SUM[22]), .CARRY (INT_CARRY[19]) ); smfulladder dfa11 (.DATA_A (INT_SUM[21]), .DATA_B (INT_SUM[22]), .DATA_C (INT_CARRY[14]), .SAVE (INT_SUM[23]), .CARRY (INT_CARRY[20]) ); assign INT_SUM[24] = INT_CARRY[15]; smfulladder dfa12 (.DATA_A (INT_SUM[23]), .DATA_B (INT_SUM[24]), .DATA_C (INT_CARRY[16]), .SAVE (INT_SUM[25]), .CARRY (INT_CARRY[17]) ); smffb dla52 (.D(INT_SUM[25]), .clk(clk), .en_d2(en_d2), .Q(SUM[9]) ); smffb dla53 (.D(INT_CARRY[17]), .clk(clk), .en_d2(en_d2), .Q(CARRY[9]) ); smffa dla54 (.D(SUMMAND[35]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[35]) ); smffa dla55 (.D(SUMMAND[36]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[36]) ); smffa dla56 (.D(SUMMAND[37]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[37]) ); smfulladder dfa13 (.DATA_A (LATCHED_PP[35]), .DATA_B (LATCHED_PP[36]), .DATA_C (LATCHED_PP[37]), .SAVE (INT_SUM[26]), .CARRY (INT_CARRY[22]) ); smffa dla57 (.D(SUMMAND[38]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[38]) ); smffa dla58 (.D(SUMMAND[39]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[39]) ); smffa dla59 (.D(SUMMAND[40]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[40]) ); smfulladder dfa14 (.DATA_A (LATCHED_PP[38]), .DATA_B (LATCHED_PP[39]), .DATA_C (LATCHED_PP[40]), .SAVE (INT_SUM[27]), .CARRY (INT_CARRY[23]) ); smffa dla60 (.D(SUMMAND[41]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[41]) ); assign INT_SUM[28] = LATCHED_PP[41]; smfulladder dfa15 (.DATA_A (INT_SUM[26]), .DATA_B (INT_SUM[27]), .DATA_C (INT_SUM[28]), .SAVE (INT_SUM[29]), .CARRY (INT_CARRY[24]) ); smhalfadder dha8 (.DATA_A (INT_CARRY[18]), .DATA_B (INT_CARRY[19]), .SAVE (INT_SUM[30]), .CARRY (INT_CARRY[25]) ); smfulladder dfa16 (.DATA_A (INT_SUM[29]), .DATA_B (INT_SUM[30]), .DATA_C (INT_CARRY[20]), .SAVE (INT_SUM[31]), .CARRY (INT_CARRY[21]) ); smffb dla61 (.D(INT_SUM[31]), .clk(clk), .en_d2(en_d2), .Q(SUM[10]) ); smffb dla62 (.D(INT_CARRY[21]), .clk(clk), .en_d2(en_d2), .Q(CARRY[10]) ); smffa dla63 (.D(SUMMAND[42]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[42]) ); smffa dla64 (.D(SUMMAND[43]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[43]) ); smffa dla65 (.D(SUMMAND[44]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[44]) ); smfulladder dfa17 (.DATA_A (LATCHED_PP[42]), .DATA_B (LATCHED_PP[43]), .DATA_C (LATCHED_PP[44]), .SAVE (INT_SUM[32]), .CARRY (INT_CARRY[27]) ); smffa dla66 (.D(SUMMAND[45]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[45]) ); smffa dla67 (.D(SUMMAND[46]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[46]) ); smffa dla68 (.D(SUMMAND[47]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[47]) ); smfulladder dfa18 (.DATA_A (LATCHED_PP[45]), .DATA_B (LATCHED_PP[46]), .DATA_C (LATCHED_PP[47]), .SAVE (INT_SUM[33]), .CARRY (INT_CARRY[28]) ); smfulladder dfa19 (.DATA_A (INT_SUM[32]), .DATA_B (INT_SUM[33]), .DATA_C (INT_CARRY[22]), .SAVE (INT_SUM[34]), .CARRY (INT_CARRY[29]) ); assign INT_SUM[35] = INT_CARRY[23]; smfulladder dfa20 (.DATA_A (INT_SUM[34]), .DATA_B (INT_SUM[35]), .DATA_C (INT_CARRY[24]), .SAVE (INT_SUM[36]), .CARRY (INT_CARRY[30]) ); assign INT_SUM[37] = INT_CARRY[25]; smhalfadder dha9 (.DATA_A (INT_SUM[36]), .DATA_B (INT_SUM[37]), .SAVE (INT_SUM[38]), .CARRY (INT_CARRY[26]) ); smffb dla69 (.D(INT_SUM[38]), .clk(clk), .en_d2(en_d2), .Q(SUM[11]) ); smffb dla70 (.D(INT_CARRY[26]), .clk(clk), .en_d2(en_d2), .Q(CARRY[11]) ); smffa dla71 (.D(SUMMAND[48]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[48]) ); smffa dla72 (.D(SUMMAND[49]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[49]) ); smffa dla73 (.D(SUMMAND[50]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[50]) ); smfulladder dfa21 (.DATA_A (LATCHED_PP[48]), .DATA_B (LATCHED_PP[49]), .DATA_C (LATCHED_PP[50]), .SAVE (INT_SUM[39]), .CARRY (INT_CARRY[32]) ); smffa dla74 (.D(SUMMAND[51]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[51]) ); smffa dla75 (.D(SUMMAND[52]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[52]) ); smffa dla76 (.D(SUMMAND[53]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[53]) ); smfulladder dfa22 (.DATA_A (LATCHED_PP[51]), .DATA_B (LATCHED_PP[52]), .DATA_C (LATCHED_PP[53]), .SAVE (INT_SUM[40]), .CARRY (INT_CARRY[33]) ); smffa dla77 (.D(SUMMAND[54]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[54]) ); assign INT_SUM[41] = LATCHED_PP[54]; smffa dla78 (.D(SUMMAND[55]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[55]) ); assign INT_SUM[42] = LATCHED_PP[55]; smfulladder dfa23 (.DATA_A (INT_SUM[39]), .DATA_B (INT_SUM[40]), .DATA_C (INT_SUM[41]), .SAVE (INT_SUM[43]), .CARRY (INT_CARRY[34]) ); smfulladder dfa24 (.DATA_A (INT_SUM[42]), .DATA_B (INT_CARRY[27]), .DATA_C (INT_CARRY[28]), .SAVE (INT_SUM[44]), .CARRY (INT_CARRY[35]) ); smfulladder dfa25 (.DATA_A (INT_SUM[43]), .DATA_B (INT_SUM[44]), .DATA_C (INT_CARRY[29]), .SAVE (INT_SUM[45]), .CARRY (INT_CARRY[36]) ); smhalfadder dha10 (.DATA_A (INT_SUM[45]), .DATA_B (INT_CARRY[30]), .SAVE (INT_SUM[46]), .CARRY (INT_CARRY[31]) ); smffb dla79 (.D(INT_SUM[46]), .clk(clk), .en_d2(en_d2), .Q(SUM[12]) ); smffb dla80 (.D(INT_CARRY[31]), .clk(clk), .en_d2(en_d2), .Q(CARRY[12]) ); smffa dla81 (.D(SUMMAND[56]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[56]) ); smffa dla82 (.D(SUMMAND[57]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[57]) ); smffa dla83 (.D(SUMMAND[58]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[58]) ); smfulladder dfa26 (.DATA_A (LATCHED_PP[56]), .DATA_B (LATCHED_PP[57]), .DATA_C (LATCHED_PP[58]), .SAVE (INT_SUM[47]), .CARRY (INT_CARRY[38]) ); smffa dla84 (.D(SUMMAND[59]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[59]) ); smffa dla85 (.D(SUMMAND[60]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[60]) ); smffa dla86 (.D(SUMMAND[61]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[61]) ); smfulladder dfa27 (.DATA_A (LATCHED_PP[59]), .DATA_B (LATCHED_PP[60]), .DATA_C (LATCHED_PP[61]), .SAVE (INT_SUM[48]), .CARRY (INT_CARRY[39]) ); smffa dla87 (.D(SUMMAND[62]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[62]) ); assign INT_SUM[49] = LATCHED_PP[62]; smfulladder dfa28 (.DATA_A (INT_SUM[47]), .DATA_B (INT_SUM[48]), .DATA_C (INT_SUM[49]), .SAVE (INT_SUM[50]), .CARRY (INT_CARRY[40]) ); smhalfadder dha11 (.DATA_A (INT_CARRY[32]), .DATA_B (INT_CARRY[33]), .SAVE (INT_SUM[51]), .CARRY (INT_CARRY[41]) ); smfulladder dfa29 (.DATA_A (INT_SUM[50]), .DATA_B (INT_SUM[51]), .DATA_C (INT_CARRY[34]), .SAVE (INT_SUM[52]), .CARRY (INT_CARRY[42]) ); assign INT_SUM[53] = INT_CARRY[35]; smfulladder dfa30 (.DATA_A (INT_SUM[52]), .DATA_B (INT_SUM[53]), .DATA_C (INT_CARRY[36]), .SAVE (INT_SUM[54]), .CARRY (INT_CARRY[37]) ); smffb dla88 (.D(INT_SUM[54]), .clk(clk), .en_d2(en_d2), .Q(SUM[13]) ); smffb dla89 (.D(INT_CARRY[37]), .clk(clk), .en_d2(en_d2), .Q(CARRY[13]) ); smffa dla90 (.D(SUMMAND[63]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[63]) ); smffa dla91 (.D(SUMMAND[64]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[64]) ); smffa dla92 (.D(SUMMAND[65]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[65]) ); smfulladder dfa31 (.DATA_A (LATCHED_PP[63]), .DATA_B (LATCHED_PP[64]), .DATA_C (LATCHED_PP[65]), .SAVE (INT_SUM[55]), .CARRY (INT_CARRY[44]) ); smffa dla93 (.D(SUMMAND[66]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[66]) ); smffa dla94 (.D(SUMMAND[67]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[67]) ); smffa dla95 (.D(SUMMAND[68]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[68]) ); smfulladder dfa32 (.DATA_A (LATCHED_PP[66]), .DATA_B (LATCHED_PP[67]), .DATA_C (LATCHED_PP[68]), .SAVE (INT_SUM[56]), .CARRY (INT_CARRY[45]) ); smffa dla96 (.D(SUMMAND[69]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[69]) ); smffa dla97 (.D(SUMMAND[70]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[70]) ); smffa dla98 (.D(SUMMAND[71]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[71]) ); smfulladder dfa33 (.DATA_A (LATCHED_PP[69]), .DATA_B (LATCHED_PP[70]), .DATA_C (LATCHED_PP[71]), .SAVE (INT_SUM[57]), .CARRY (INT_CARRY[46]) ); smfulladder dfa34 (.DATA_A (INT_SUM[55]), .DATA_B (INT_SUM[56]), .DATA_C (INT_SUM[57]), .SAVE (INT_SUM[58]), .CARRY (INT_CARRY[47]) ); smhalfadder dha12 (.DATA_A (INT_CARRY[38]), .DATA_B (INT_CARRY[39]), .SAVE (INT_SUM[59]), .CARRY (INT_CARRY[48]) ); smfulladder dfa35 (.DATA_A (INT_SUM[58]), .DATA_B (INT_SUM[59]), .DATA_C (INT_CARRY[40]), .SAVE (INT_SUM[60]), .CARRY (INT_CARRY[49]) ); assign INT_SUM[61] = INT_CARRY[41]; smfulladder dfa36 (.DATA_A (INT_SUM[60]), .DATA_B (INT_SUM[61]), .DATA_C (INT_CARRY[42]), .SAVE (INT_SUM[62]), .CARRY (INT_CARRY[43]) ); smffb dla99 (.D(INT_SUM[62]), .clk(clk), .en_d2(en_d2), .Q(SUM[14]) ); smffb dla100 (.D(INT_CARRY[43]), .clk(clk), .en_d2(en_d2), .Q(CARRY[14]) ); smffa dla101 (.D(SUMMAND[72]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[72]) ); smffa dla102 (.D(SUMMAND[73]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[73]) ); smffa dla103 (.D(SUMMAND[74]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[74]) ); smfulladder dfa37 (.DATA_A (LATCHED_PP[72]), .DATA_B (LATCHED_PP[73]), .DATA_C (LATCHED_PP[74]), .SAVE (INT_SUM[63]), .CARRY (INT_CARRY[51]) ); smffa dla104 (.D(SUMMAND[75]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[75]) ); smffa dla105 (.D(SUMMAND[76]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[76]) ); smffa dla106 (.D(SUMMAND[77]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[77]) ); smfulladder dfa38 (.DATA_A (LATCHED_PP[75]), .DATA_B (LATCHED_PP[76]), .DATA_C (LATCHED_PP[77]), .SAVE (INT_SUM[64]), .CARRY (INT_CARRY[52]) ); smffa dla107 (.D(SUMMAND[78]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[78]) ); smffa dla108 (.D(SUMMAND[79]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[79]) ); smhalfadder dha13 (.DATA_A (LATCHED_PP[78]), .DATA_B (LATCHED_PP[79]), .SAVE (INT_SUM[65]), .CARRY (INT_CARRY[53]) ); smfulladder dfa39 (.DATA_A (INT_SUM[63]), .DATA_B (INT_SUM[64]), .DATA_C (INT_SUM[65]), .SAVE (INT_SUM[66]), .CARRY (INT_CARRY[54]) ); smfulladder dfa40 (.DATA_A (INT_CARRY[44]), .DATA_B (INT_CARRY[45]), .DATA_C (INT_CARRY[46]), .SAVE (INT_SUM[67]), .CARRY (INT_CARRY[55]) ); smfulladder dfa41 (.DATA_A (INT_SUM[66]), .DATA_B (INT_SUM[67]), .DATA_C (INT_CARRY[47]), .SAVE (INT_SUM[68]), .CARRY (INT_CARRY[56]) ); assign INT_SUM[69] = INT_CARRY[48]; smfulladder dfa42 (.DATA_A (INT_SUM[68]), .DATA_B (INT_SUM[69]), .DATA_C (INT_CARRY[49]), .SAVE (INT_SUM[70]), .CARRY (INT_CARRY[50]) ); smffb dla109 (.D(INT_SUM[70]), .clk(clk), .en_d2(en_d2), .Q(SUM[15]) ); smffb dla110 (.D(INT_CARRY[50]), .clk(clk), .en_d2(en_d2), .Q(CARRY[15]) ); smffa dla111 (.D(SUMMAND[80]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[80]) ); smffa dla112 (.D(SUMMAND[81]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[81]) ); smffa dla113 (.D(SUMMAND[82]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[82]) ); smfulladder dfa43 (.DATA_A (LATCHED_PP[80]), .DATA_B (LATCHED_PP[81]), .DATA_C (LATCHED_PP[82]), .SAVE (INT_SUM[71]), .CARRY (INT_CARRY[58]) ); smffa dla114 (.D(SUMMAND[83]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[83]) ); smffa dla115 (.D(SUMMAND[84]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[84]) ); smffa dla116 (.D(SUMMAND[85]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[85]) ); smfulladder dfa44 (.DATA_A (LATCHED_PP[83]), .DATA_B (LATCHED_PP[84]), .DATA_C (LATCHED_PP[85]), .SAVE (INT_SUM[72]), .CARRY (INT_CARRY[59]) ); smffa dla117 (.D(SUMMAND[86]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[86]) ); smffa dla118 (.D(SUMMAND[87]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[87]) ); smffa dla119 (.D(SUMMAND[88]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[88]) ); smfulladder dfa45 (.DATA_A (LATCHED_PP[86]), .DATA_B (LATCHED_PP[87]), .DATA_C (LATCHED_PP[88]), .SAVE (INT_SUM[73]), .CARRY (INT_CARRY[60]) ); smffa dla120 (.D(SUMMAND[89]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[89]) ); assign INT_SUM[74] = LATCHED_PP[89]; smfulladder dfa46 (.DATA_A (INT_SUM[71]), .DATA_B (INT_SUM[72]), .DATA_C (INT_SUM[73]), .SAVE (INT_SUM[75]), .CARRY (INT_CARRY[61]) ); smfulladder dfa47 (.DATA_A (INT_SUM[74]), .DATA_B (INT_CARRY[51]), .DATA_C (INT_CARRY[52]), .SAVE (INT_SUM[76]), .CARRY (INT_CARRY[62]) ); assign INT_SUM[77] = INT_CARRY[53]; smfulladder dfa48 (.DATA_A (INT_SUM[75]), .DATA_B (INT_SUM[76]), .DATA_C (INT_SUM[77]), .SAVE (INT_SUM[78]), .CARRY (INT_CARRY[63]) ); smhalfadder dha14 (.DATA_A (INT_CARRY[54]), .DATA_B (INT_CARRY[55]), .SAVE (INT_SUM[79]), .CARRY (INT_CARRY[64]) ); smfulladder dfa49 (.DATA_A (INT_SUM[78]), .DATA_B (INT_SUM[79]), .DATA_C (INT_CARRY[56]), .SAVE (INT_SUM[80]), .CARRY (INT_CARRY[57]) ); smffb dla121 (.D(INT_SUM[80]), .clk(clk), .en_d2(en_d2), .Q(SUM[16]) ); smffb dla122 (.D(INT_CARRY[57]), .clk(clk), .en_d2(en_d2), .Q(CARRY[16]) ); smffa dla123 (.D(SUMMAND[90]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[90]) ); smffa dla124 (.D(SUMMAND[91]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[91]) ); smffa dla125 (.D(SUMMAND[92]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[92]) ); smfulladder dfa50 (.DATA_A (LATCHED_PP[90]), .DATA_B (LATCHED_PP[91]), .DATA_C (LATCHED_PP[92]), .SAVE (INT_SUM[81]), .CARRY (INT_CARRY[66]) ); smffa dla126 (.D(SUMMAND[93]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[93]) ); smffa dla127 (.D(SUMMAND[94]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[94]) ); smffa dla128 (.D(SUMMAND[95]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[95]) ); smfulladder dfa51 (.DATA_A (LATCHED_PP[93]), .DATA_B (LATCHED_PP[94]), .DATA_C (LATCHED_PP[95]), .SAVE (INT_SUM[82]), .CARRY (INT_CARRY[67]) ); smffa dla129 (.D(SUMMAND[96]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[96]) ); smffa dla130 (.D(SUMMAND[97]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[97]) ); smffa dla131 (.D(SUMMAND[98]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[98]) ); smfulladder dfa52 (.DATA_A (LATCHED_PP[96]), .DATA_B (LATCHED_PP[97]), .DATA_C (LATCHED_PP[98]), .SAVE (INT_SUM[83]), .CARRY (INT_CARRY[68]) ); smfulladder dfa53 (.DATA_A (INT_SUM[81]), .DATA_B (INT_SUM[82]), .DATA_C (INT_SUM[83]), .SAVE (INT_SUM[84]), .CARRY (INT_CARRY[69]) ); smfulladder dfa54 (.DATA_A (INT_CARRY[58]), .DATA_B (INT_CARRY[59]), .DATA_C (INT_CARRY[60]), .SAVE (INT_SUM[85]), .CARRY (INT_CARRY[70]) ); smfulladder dfa55 (.DATA_A (INT_SUM[84]), .DATA_B (INT_SUM[85]), .DATA_C (INT_CARRY[61]), .SAVE (INT_SUM[86]), .CARRY (INT_CARRY[71]) ); assign INT_SUM[87] = INT_CARRY[62]; smfulladder dfa56 (.DATA_A (INT_SUM[86]), .DATA_B (INT_SUM[87]), .DATA_C (INT_CARRY[63]), .SAVE (INT_SUM[88]), .CARRY (INT_CARRY[72]) ); assign INT_SUM[89] = INT_CARRY[64]; smhalfadder dha15 (.DATA_A (INT_SUM[88]), .DATA_B (INT_SUM[89]), .SAVE (INT_SUM[90]), .CARRY (INT_CARRY[65]) ); smffb dla132 (.D(INT_SUM[90]), .clk(clk), .en_d2(en_d2), .Q(SUM[17]) ); smffb dla133 (.D(INT_CARRY[65]), .clk(clk), .en_d2(en_d2), .Q(CARRY[17]) ); smffa dla134 (.D(SUMMAND[99]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[99]) ); smffa dla135 (.D(SUMMAND[100]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[100]) ); smffa dla136 (.D(SUMMAND[101]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[101]) ); smfulladder dfa57 (.DATA_A (LATCHED_PP[99]), .DATA_B (LATCHED_PP[100]), .DATA_C (LATCHED_PP[101]), .SAVE (INT_SUM[91]), .CARRY (INT_CARRY[74]) ); smffa dla137 (.D(SUMMAND[102]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[102]) ); smffa dla138 (.D(SUMMAND[103]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[103]) ); smffa dla139 (.D(SUMMAND[104]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[104]) ); smfulladder dfa58 (.DATA_A (LATCHED_PP[102]), .DATA_B (LATCHED_PP[103]), .DATA_C (LATCHED_PP[104]), .SAVE (INT_SUM[92]), .CARRY (INT_CARRY[75]) ); smffa dla140 (.D(SUMMAND[105]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[105]) ); smffa dla141 (.D(SUMMAND[106]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[106]) ); smffa dla142 (.D(SUMMAND[107]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[107]) ); smfulladder dfa59 (.DATA_A (LATCHED_PP[105]), .DATA_B (LATCHED_PP[106]), .DATA_C (LATCHED_PP[107]), .SAVE (INT_SUM[93]), .CARRY (INT_CARRY[76]) ); smffa dla143 (.D(SUMMAND[108]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[108]) ); assign INT_SUM[94] = LATCHED_PP[108]; smffa dla144 (.D(SUMMAND[109]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[109]) ); assign INT_SUM[95] = LATCHED_PP[109]; smfulladder dfa60 (.DATA_A (INT_SUM[91]), .DATA_B (INT_SUM[92]), .DATA_C (INT_SUM[93]), .SAVE (INT_SUM[96]), .CARRY (INT_CARRY[77]) ); smfulladder dfa61 (.DATA_A (INT_SUM[94]), .DATA_B (INT_SUM[95]), .DATA_C (INT_CARRY[66]), .SAVE (INT_SUM[97]), .CARRY (INT_CARRY[78]) ); assign INT_SUM[98] = INT_CARRY[67]; assign INT_SUM[99] = INT_CARRY[68]; smfulladder dfa62 (.DATA_A (INT_SUM[96]), .DATA_B (INT_SUM[97]), .DATA_C (INT_SUM[98]), .SAVE (INT_SUM[100]), .CARRY (INT_CARRY[79]) ); smfulladder dfa63 (.DATA_A (INT_SUM[99]), .DATA_B (INT_CARRY[69]), .DATA_C (INT_CARRY[70]), .SAVE (INT_SUM[101]), .CARRY (INT_CARRY[80]) ); smfulladder dfa64 (.DATA_A (INT_SUM[100]), .DATA_B (INT_SUM[101]), .DATA_C (INT_CARRY[71]), .SAVE (INT_SUM[102]), .CARRY (INT_CARRY[81]) ); smhalfadder dha16 (.DATA_A (INT_SUM[102]), .DATA_B (INT_CARRY[72]), .SAVE (INT_SUM[103]), .CARRY (INT_CARRY[73]) ); smffb dla145 (.D(INT_SUM[103]), .clk(clk), .en_d2(en_d2), .Q(SUM[18]) ); smffb dla146 (.D(INT_CARRY[73]), .clk(clk), .en_d2(en_d2), .Q(CARRY[18]) ); smffa dla147 (.D(SUMMAND[110]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[110]) ); smffa dla148 (.D(SUMMAND[111]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[111]) ); smffa dla149 (.D(SUMMAND[112]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[112]) ); smfulladder dfa65 (.DATA_A (LATCHED_PP[110]), .DATA_B (LATCHED_PP[111]), .DATA_C (LATCHED_PP[112]), .SAVE (INT_SUM[104]), .CARRY (INT_CARRY[83]) ); smffa dla150 (.D(SUMMAND[113]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[113]) ); smffa dla151 (.D(SUMMAND[114]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[114]) ); smffa dla152 (.D(SUMMAND[115]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[115]) ); smfulladder dfa66 (.DATA_A (LATCHED_PP[113]), .DATA_B (LATCHED_PP[114]), .DATA_C (LATCHED_PP[115]), .SAVE (INT_SUM[105]), .CARRY (INT_CARRY[84]) ); smffa dla153 (.D(SUMMAND[116]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[116]) ); smffa dla154 (.D(SUMMAND[117]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[117]) ); smffa dla155 (.D(SUMMAND[118]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[118]) ); smfulladder dfa67 (.DATA_A (LATCHED_PP[116]), .DATA_B (LATCHED_PP[117]), .DATA_C (LATCHED_PP[118]), .SAVE (INT_SUM[106]), .CARRY (INT_CARRY[85]) ); smffa dla156 (.D(SUMMAND[119]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[119]) ); assign INT_SUM[107] = LATCHED_PP[119]; smfulladder dfa68 (.DATA_A (INT_SUM[104]), .DATA_B (INT_SUM[105]), .DATA_C (INT_SUM[106]), .SAVE (INT_SUM[108]), .CARRY (INT_CARRY[86]) ); smfulladder dfa69 (.DATA_A (INT_SUM[107]), .DATA_B (INT_CARRY[74]), .DATA_C (INT_CARRY[75]), .SAVE (INT_SUM[109]), .CARRY (INT_CARRY[87]) ); assign INT_SUM[110] = INT_CARRY[76]; smfulladder dfa70 (.DATA_A (INT_SUM[108]), .DATA_B (INT_SUM[109]), .DATA_C (INT_SUM[110]), .SAVE (INT_SUM[111]), .CARRY (INT_CARRY[88]) ); smhalfadder dha17 (.DATA_A (INT_CARRY[77]), .DATA_B (INT_CARRY[78]), .SAVE (INT_SUM[112]), .CARRY (INT_CARRY[89]) ); smfulladder dfa71 (.DATA_A (INT_SUM[111]), .DATA_B (INT_SUM[112]), .DATA_C (INT_CARRY[79]), .SAVE (INT_SUM[113]), .CARRY (INT_CARRY[90]) ); assign INT_SUM[114] = INT_CARRY[80]; smfulladder dfa72 (.DATA_A (INT_SUM[113]), .DATA_B (INT_SUM[114]), .DATA_C (INT_CARRY[81]), .SAVE (INT_SUM[115]), .CARRY (INT_CARRY[82]) ); smffb dla157 (.D(INT_SUM[115]), .clk(clk), .en_d2(en_d2), .Q(SUM[19]) ); smffb dla158 (.D(INT_CARRY[82]), .clk(clk), .en_d2(en_d2), .Q(CARRY[19]) ); smffa dla159 (.D(SUMMAND[120]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[120]) ); smffa dla160 (.D(SUMMAND[121]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[121]) ); smffa dla161 (.D(SUMMAND[122]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[122]) ); smfulladder dfa73 (.DATA_A (LATCHED_PP[120]), .DATA_B (LATCHED_PP[121]), .DATA_C (LATCHED_PP[122]), .SAVE (INT_SUM[116]), .CARRY (INT_CARRY[92]) ); smffa dla162 (.D(SUMMAND[123]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[123]) ); smffa dla163 (.D(SUMMAND[124]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[124]) ); smffa dla164 (.D(SUMMAND[125]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[125]) ); smfulladder dfa74 (.DATA_A (LATCHED_PP[123]), .DATA_B (LATCHED_PP[124]), .DATA_C (LATCHED_PP[125]), .SAVE (INT_SUM[117]), .CARRY (INT_CARRY[93]) ); smffa dla165 (.D(SUMMAND[126]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[126]) ); smffa dla166 (.D(SUMMAND[127]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[127]) ); smffa dla167 (.D(SUMMAND[128]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[128]) ); smfulladder dfa75 (.DATA_A (LATCHED_PP[126]), .DATA_B (LATCHED_PP[127]), .DATA_C (LATCHED_PP[128]), .SAVE (INT_SUM[118]), .CARRY (INT_CARRY[94]) ); smffa dla168 (.D(SUMMAND[129]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[129]) ); smffa dla169 (.D(SUMMAND[130]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[130]) ); smffa dla170 (.D(SUMMAND[131]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[131]) ); smfulladder dfa76 (.DATA_A (LATCHED_PP[129]), .DATA_B (LATCHED_PP[130]), .DATA_C (LATCHED_PP[131]), .SAVE (INT_SUM[119]), .CARRY (INT_CARRY[95]) ); smfulladder dfa77 (.DATA_A (INT_SUM[116]), .DATA_B (INT_SUM[117]), .DATA_C (INT_SUM[118]), .SAVE (INT_SUM[120]), .CARRY (INT_CARRY[96]) ); smfulladder dfa78 (.DATA_A (INT_SUM[119]), .DATA_B (INT_CARRY[83]), .DATA_C (INT_CARRY[84]), .SAVE (INT_SUM[121]), .CARRY (INT_CARRY[97]) ); assign INT_SUM[122] = INT_CARRY[85]; smfulladder dfa79 (.DATA_A (INT_SUM[120]), .DATA_B (INT_SUM[121]), .DATA_C (INT_SUM[122]), .SAVE (INT_SUM[123]), .CARRY (INT_CARRY[98]) ); smhalfadder dha18 (.DATA_A (INT_CARRY[86]), .DATA_B (INT_CARRY[87]), .SAVE (INT_SUM[124]), .CARRY (INT_CARRY[99]) ); smfulladder dfa80 (.DATA_A (INT_SUM[123]), .DATA_B (INT_SUM[124]), .DATA_C (INT_CARRY[88]), .SAVE (INT_SUM[125]), .CARRY (INT_CARRY[100]) ); assign INT_SUM[126] = INT_CARRY[89]; smfulladder dfa81 (.DATA_A (INT_SUM[125]), .DATA_B (INT_SUM[126]), .DATA_C (INT_CARRY[90]), .SAVE (INT_SUM[127]), .CARRY (INT_CARRY[91]) ); smffb dla171 (.D(INT_SUM[127]), .clk(clk), .en_d2(en_d2), .Q(SUM[20]) ); smffb dla172 (.D(INT_CARRY[91]), .clk(clk), .en_d2(en_d2), .Q(CARRY[20]) ); smffa dla173 (.D(SUMMAND[132]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[132]) ); smffa dla174 (.D(SUMMAND[133]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[133]) ); smffa dla175 (.D(SUMMAND[134]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[134]) ); smfulladder dfa82 (.DATA_A (LATCHED_PP[132]), .DATA_B (LATCHED_PP[133]), .DATA_C (LATCHED_PP[134]), .SAVE (INT_SUM[128]), .CARRY (INT_CARRY[102]) ); smffa dla176 (.D(SUMMAND[135]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[135]) ); smffa dla177 (.D(SUMMAND[136]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[136]) ); smffa dla178 (.D(SUMMAND[137]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[137]) ); smfulladder dfa83 (.DATA_A (LATCHED_PP[135]), .DATA_B (LATCHED_PP[136]), .DATA_C (LATCHED_PP[137]), .SAVE (INT_SUM[129]), .CARRY (INT_CARRY[103]) ); smffa dla179 (.D(SUMMAND[138]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[138]) ); smffa dla180 (.D(SUMMAND[139]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[139]) ); smffa dla181 (.D(SUMMAND[140]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[140]) ); smfulladder dfa84 (.DATA_A (LATCHED_PP[138]), .DATA_B (LATCHED_PP[139]), .DATA_C (LATCHED_PP[140]), .SAVE (INT_SUM[130]), .CARRY (INT_CARRY[104]) ); smffa dla182 (.D(SUMMAND[141]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[141]) ); assign INT_SUM[131] = LATCHED_PP[141]; smffa dla183 (.D(SUMMAND[142]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[142]) ); assign INT_SUM[132] = LATCHED_PP[142]; smfulladder dfa85 (.DATA_A (INT_SUM[128]), .DATA_B (INT_SUM[129]), .DATA_C (INT_SUM[130]), .SAVE (INT_SUM[133]), .CARRY (INT_CARRY[105]) ); smfulladder dfa86 (.DATA_A (INT_SUM[131]), .DATA_B (INT_SUM[132]), .DATA_C (INT_CARRY[92]), .SAVE (INT_SUM[134]), .CARRY (INT_CARRY[106]) ); smfulladder dfa87 (.DATA_A (INT_CARRY[93]), .DATA_B (INT_CARRY[94]), .DATA_C (INT_CARRY[95]), .SAVE (INT_SUM[135]), .CARRY (INT_CARRY[107]) ); smfulladder dfa88 (.DATA_A (INT_SUM[133]), .DATA_B (INT_SUM[134]), .DATA_C (INT_SUM[135]), .SAVE (INT_SUM[136]), .CARRY (INT_CARRY[108]) ); smhalfadder dha19 (.DATA_A (INT_CARRY[96]), .DATA_B (INT_CARRY[97]), .SAVE (INT_SUM[137]), .CARRY (INT_CARRY[109]) ); smfulladder dfa89 (.DATA_A (INT_SUM[136]), .DATA_B (INT_SUM[137]), .DATA_C (INT_CARRY[98]), .SAVE (INT_SUM[138]), .CARRY (INT_CARRY[110]) ); assign INT_SUM[139] = INT_CARRY[99]; smfulladder dfa90 (.DATA_A (INT_SUM[138]), .DATA_B (INT_SUM[139]), .DATA_C (INT_CARRY[100]), .SAVE (INT_SUM[140]), .CARRY (INT_CARRY[101]) ); smffb dla184 (.D(INT_SUM[140]), .clk(clk), .en_d2(en_d2), .Q(SUM[21]) ); smffb dla185 (.D(INT_CARRY[101]), .clk(clk), .en_d2(en_d2), .Q(CARRY[21]) ); smffa dla186 (.D(SUMMAND[143]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[143]) ); smffa dla187 (.D(SUMMAND[144]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[144]) ); smffa dla188 (.D(SUMMAND[145]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[145]) ); smfulladder dfa91 (.DATA_A (LATCHED_PP[143]), .DATA_B (LATCHED_PP[144]), .DATA_C (LATCHED_PP[145]), .SAVE (INT_SUM[141]), .CARRY (INT_CARRY[112]) ); smffa dla189 (.D(SUMMAND[146]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[146]) ); smffa dla190 (.D(SUMMAND[147]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[147]) ); smffa dla191 (.D(SUMMAND[148]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[148]) ); smfulladder dfa92 (.DATA_A (LATCHED_PP[146]), .DATA_B (LATCHED_PP[147]), .DATA_C (LATCHED_PP[148]), .SAVE (INT_SUM[142]), .CARRY (INT_CARRY[113]) ); smffa dla192 (.D(SUMMAND[149]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[149]) ); smffa dla193 (.D(SUMMAND[150]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[150]) ); smffa dla194 (.D(SUMMAND[151]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[151]) ); smfulladder dfa93 (.DATA_A (LATCHED_PP[149]), .DATA_B (LATCHED_PP[150]), .DATA_C (LATCHED_PP[151]), .SAVE (INT_SUM[143]), .CARRY (INT_CARRY[114]) ); smffa dla195 (.D(SUMMAND[152]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[152]) ); smffa dla196 (.D(SUMMAND[153]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[153]) ); smffa dla197 (.D(SUMMAND[154]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[154]) ); smfulladder dfa94 (.DATA_A (LATCHED_PP[152]), .DATA_B (LATCHED_PP[153]), .DATA_C (LATCHED_PP[154]), .SAVE (INT_SUM[144]), .CARRY (INT_CARRY[115]) ); smffa dla198 (.D(SUMMAND[155]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[155]) ); assign INT_SUM[145] = LATCHED_PP[155]; smfulladder dfa95 (.DATA_A (INT_SUM[141]), .DATA_B (INT_SUM[142]), .DATA_C (INT_SUM[143]), .SAVE (INT_SUM[146]), .CARRY (INT_CARRY[116]) ); smfulladder dfa96 (.DATA_A (INT_SUM[144]), .DATA_B (INT_SUM[145]), .DATA_C (INT_CARRY[102]), .SAVE (INT_SUM[147]), .CARRY (INT_CARRY[117]) ); smhalfadder dha20 (.DATA_A (INT_CARRY[103]), .DATA_B (INT_CARRY[104]), .SAVE (INT_SUM[148]), .CARRY (INT_CARRY[118]) ); smfulladder dfa97 (.DATA_A (INT_SUM[146]), .DATA_B (INT_SUM[147]), .DATA_C (INT_SUM[148]), .SAVE (INT_SUM[149]), .CARRY (INT_CARRY[119]) ); smfulladder dfa98 (.DATA_A (INT_CARRY[105]), .DATA_B (INT_CARRY[106]), .DATA_C (INT_CARRY[107]), .SAVE (INT_SUM[150]), .CARRY (INT_CARRY[120]) ); smfulladder dfa99 (.DATA_A (INT_SUM[149]), .DATA_B (INT_SUM[150]), .DATA_C (INT_CARRY[108]), .SAVE (INT_SUM[151]), .CARRY (INT_CARRY[121]) ); assign INT_SUM[152] = INT_CARRY[109]; smfulladder dfa100 (.DATA_A (INT_SUM[151]), .DATA_B (INT_SUM[152]), .DATA_C (INT_CARRY[110]), .SAVE (INT_SUM[153]), .CARRY (INT_CARRY[111]) ); smffb dla199 (.D(INT_SUM[153]), .clk(clk), .en_d2(en_d2), .Q(SUM[22]) ); smffb dla200 (.D(INT_CARRY[111]), .clk(clk), .en_d2(en_d2), .Q(CARRY[22]) ); smffa dla201 (.D(SUMMAND[156]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[156]) ); smffa dla202 (.D(SUMMAND[157]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[157]) ); smffa dla203 (.D(SUMMAND[158]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[158]) ); smfulladder dfa101 (.DATA_A (LATCHED_PP[156]), .DATA_B (LATCHED_PP[157]), .DATA_C (LATCHED_PP[158]), .SAVE (INT_SUM[154]), .CARRY (INT_CARRY[123]) ); smffa dla204 (.D(SUMMAND[159]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[159]) ); smffa dla205 (.D(SUMMAND[160]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[160]) ); smffa dla206 (.D(SUMMAND[161]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[161]) ); smfulladder dfa102 (.DATA_A (LATCHED_PP[159]), .DATA_B (LATCHED_PP[160]), .DATA_C (LATCHED_PP[161]), .SAVE (INT_SUM[155]), .CARRY (INT_CARRY[124]) ); smffa dla207 (.D(SUMMAND[162]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[162]) ); smffa dla208 (.D(SUMMAND[163]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[163]) ); smffa dla209 (.D(SUMMAND[164]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[164]) ); smfulladder dfa103 (.DATA_A (LATCHED_PP[162]), .DATA_B (LATCHED_PP[163]), .DATA_C (LATCHED_PP[164]), .SAVE (INT_SUM[156]), .CARRY (INT_CARRY[125]) ); smffa dla210 (.D(SUMMAND[165]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[165]) ); smffa dla211 (.D(SUMMAND[166]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[166]) ); smffa dla212 (.D(SUMMAND[167]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[167]) ); smfulladder dfa104 (.DATA_A (LATCHED_PP[165]), .DATA_B (LATCHED_PP[166]), .DATA_C (LATCHED_PP[167]), .SAVE (INT_SUM[157]), .CARRY (INT_CARRY[126]) ); smfulladder dfa105 (.DATA_A (INT_SUM[154]), .DATA_B (INT_SUM[155]), .DATA_C (INT_SUM[156]), .SAVE (INT_SUM[158]), .CARRY (INT_CARRY[127]) ); smfulladder dfa106 (.DATA_A (INT_SUM[157]), .DATA_B (INT_CARRY[112]), .DATA_C (INT_CARRY[113]), .SAVE (INT_SUM[159]), .CARRY (INT_CARRY[128]) ); smhalfadder dha21 (.DATA_A (INT_CARRY[114]), .DATA_B (INT_CARRY[115]), .SAVE (INT_SUM[160]), .CARRY (INT_CARRY[129]) ); smfulladder dfa107 (.DATA_A (INT_SUM[158]), .DATA_B (INT_SUM[159]), .DATA_C (INT_SUM[160]), .SAVE (INT_SUM[161]), .CARRY (INT_CARRY[130]) ); smfulladder dfa108 (.DATA_A (INT_CARRY[116]), .DATA_B (INT_CARRY[117]), .DATA_C (INT_CARRY[118]), .SAVE (INT_SUM[162]), .CARRY (INT_CARRY[131]) ); smfulladder dfa109 (.DATA_A (INT_SUM[161]), .DATA_B (INT_SUM[162]), .DATA_C (INT_CARRY[119]), .SAVE (INT_SUM[163]), .CARRY (INT_CARRY[132]) ); assign INT_SUM[164] = INT_CARRY[120]; smfulladder dfa110 (.DATA_A (INT_SUM[163]), .DATA_B (INT_SUM[164]), .DATA_C (INT_CARRY[121]), .SAVE (INT_SUM[165]), .CARRY (INT_CARRY[122]) ); smffb dla213 (.D(INT_SUM[165]), .clk(clk), .en_d2(en_d2), .Q(SUM[23]) ); smffb dla214 (.D(INT_CARRY[122]), .clk(clk), .en_d2(en_d2), .Q(CARRY[23]) ); smffa dla215 (.D(SUMMAND[168]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[168]) ); smffa dla216 (.D(SUMMAND[169]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[169]) ); smffa dla217 (.D(SUMMAND[170]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[170]) ); smfulladder dfa111 (.DATA_A (LATCHED_PP[168]), .DATA_B (LATCHED_PP[169]), .DATA_C (LATCHED_PP[170]), .SAVE (INT_SUM[166]), .CARRY (INT_CARRY[134]) ); smffa dla218 (.D(SUMMAND[171]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[171]) ); smffa dla219 (.D(SUMMAND[172]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[172]) ); smffa dla220 (.D(SUMMAND[173]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[173]) ); smfulladder dfa112 (.DATA_A (LATCHED_PP[171]), .DATA_B (LATCHED_PP[172]), .DATA_C (LATCHED_PP[173]), .SAVE (INT_SUM[167]), .CARRY (INT_CARRY[135]) ); smffa dla221 (.D(SUMMAND[174]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[174]) ); smffa dla222 (.D(SUMMAND[175]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[175]) ); smffa dla223 (.D(SUMMAND[176]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[176]) ); smfulladder dfa113 (.DATA_A (LATCHED_PP[174]), .DATA_B (LATCHED_PP[175]), .DATA_C (LATCHED_PP[176]), .SAVE (INT_SUM[168]), .CARRY (INT_CARRY[136]) ); smffa dla224 (.D(SUMMAND[177]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[177]) ); smffa dla225 (.D(SUMMAND[178]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[178]) ); smffa dla226 (.D(SUMMAND[179]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[179]) ); smfulladder dfa114 (.DATA_A (LATCHED_PP[177]), .DATA_B (LATCHED_PP[178]), .DATA_C (LATCHED_PP[179]), .SAVE (INT_SUM[169]), .CARRY (INT_CARRY[137]) ); smffa dla227 (.D(SUMMAND[180]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[180]) ); smffa dla228 (.D(SUMMAND[181]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[181]) ); smhalfadder dha22 (.DATA_A (LATCHED_PP[180]), .DATA_B (LATCHED_PP[181]), .SAVE (INT_SUM[170]), .CARRY (INT_CARRY[138]) ); smfulladder dfa115 (.DATA_A (INT_SUM[166]), .DATA_B (INT_SUM[167]), .DATA_C (INT_SUM[168]), .SAVE (INT_SUM[171]), .CARRY (INT_CARRY[139]) ); smfulladder dfa116 (.DATA_A (INT_SUM[169]), .DATA_B (INT_SUM[170]), .DATA_C (INT_CARRY[123]), .SAVE (INT_SUM[172]), .CARRY (INT_CARRY[140]) ); smfulladder dfa117 (.DATA_A (INT_CARRY[124]), .DATA_B (INT_CARRY[125]), .DATA_C (INT_CARRY[126]), .SAVE (INT_SUM[173]), .CARRY (INT_CARRY[141]) ); smfulladder dfa118 (.DATA_A (INT_SUM[171]), .DATA_B (INT_SUM[172]), .DATA_C (INT_SUM[173]), .SAVE (INT_SUM[174]), .CARRY (INT_CARRY[142]) ); smfulladder dfa119 (.DATA_A (INT_CARRY[127]), .DATA_B (INT_CARRY[128]), .DATA_C (INT_CARRY[129]), .SAVE (INT_SUM[175]), .CARRY (INT_CARRY[143]) ); smfulladder dfa120 (.DATA_A (INT_SUM[174]), .DATA_B (INT_SUM[175]), .DATA_C (INT_CARRY[130]), .SAVE (INT_SUM[176]), .CARRY (INT_CARRY[144]) ); assign INT_SUM[177] = INT_CARRY[131]; smfulladder dfa121 (.DATA_A (INT_SUM[176]), .DATA_B (INT_SUM[177]), .DATA_C (INT_CARRY[132]), .SAVE (INT_SUM[178]), .CARRY (INT_CARRY[133]) ); smffb dla229 (.D(INT_SUM[178]), .clk(clk), .en_d2(en_d2), .Q(SUM[24]) ); smffb dla230 (.D(INT_CARRY[133]), .clk(clk), .en_d2(en_d2), .Q(CARRY[24]) ); smffa dla231 (.D(SUMMAND[182]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[182]) ); smffa dla232 (.D(SUMMAND[183]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[183]) ); smffa dla233 (.D(SUMMAND[184]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[184]) ); smfulladder dfa122 (.DATA_A (LATCHED_PP[182]), .DATA_B (LATCHED_PP[183]), .DATA_C (LATCHED_PP[184]), .SAVE (INT_SUM[179]), .CARRY (INT_CARRY[146]) ); smffa dla234 (.D(SUMMAND[185]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[185]) ); smffa dla235 (.D(SUMMAND[186]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[186]) ); smffa dla236 (.D(SUMMAND[187]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[187]) ); smfulladder dfa123 (.DATA_A (LATCHED_PP[185]), .DATA_B (LATCHED_PP[186]), .DATA_C (LATCHED_PP[187]), .SAVE (INT_SUM[180]), .CARRY (INT_CARRY[147]) ); smffa dla237 (.D(SUMMAND[188]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[188]) ); smffa dla238 (.D(SUMMAND[189]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[189]) ); smffa dla239 (.D(SUMMAND[190]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[190]) ); smfulladder dfa124 (.DATA_A (LATCHED_PP[188]), .DATA_B (LATCHED_PP[189]), .DATA_C (LATCHED_PP[190]), .SAVE (INT_SUM[181]), .CARRY (INT_CARRY[148]) ); smffa dla240 (.D(SUMMAND[191]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[191]) ); smffa dla241 (.D(SUMMAND[192]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[192]) ); smffa dla242 (.D(SUMMAND[193]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[193]) ); smfulladder dfa125 (.DATA_A (LATCHED_PP[191]), .DATA_B (LATCHED_PP[192]), .DATA_C (LATCHED_PP[193]), .SAVE (INT_SUM[182]), .CARRY (INT_CARRY[149]) ); smffa dla243 (.D(SUMMAND[194]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[194]) ); assign INT_SUM[183] = LATCHED_PP[194]; smfulladder dfa126 (.DATA_A (INT_SUM[179]), .DATA_B (INT_SUM[180]), .DATA_C (INT_SUM[181]), .SAVE (INT_SUM[184]), .CARRY (INT_CARRY[150]) ); smfulladder dfa127 (.DATA_A (INT_SUM[182]), .DATA_B (INT_SUM[183]), .DATA_C (INT_CARRY[134]), .SAVE (INT_SUM[185]), .CARRY (INT_CARRY[151]) ); smfulladder dfa128 (.DATA_A (INT_CARRY[135]), .DATA_B (INT_CARRY[136]), .DATA_C (INT_CARRY[137]), .SAVE (INT_SUM[186]), .CARRY (INT_CARRY[152]) ); assign INT_SUM[187] = INT_CARRY[138]; smfulladder dfa129 (.DATA_A (INT_SUM[184]), .DATA_B (INT_SUM[185]), .DATA_C (INT_SUM[186]), .SAVE (INT_SUM[188]), .CARRY (INT_CARRY[153]) ); smfulladder dfa130 (.DATA_A (INT_SUM[187]), .DATA_B (INT_CARRY[139]), .DATA_C (INT_CARRY[140]), .SAVE (INT_SUM[189]), .CARRY (INT_CARRY[154]) ); assign INT_SUM[190] = INT_CARRY[141]; smfulladder dfa131 (.DATA_A (INT_SUM[188]), .DATA_B (INT_SUM[189]), .DATA_C (INT_SUM[190]), .SAVE (INT_SUM[191]), .CARRY (INT_CARRY[155]) ); smhalfadder dha23 (.DATA_A (INT_CARRY[142]), .DATA_B (INT_CARRY[143]), .SAVE (INT_SUM[192]), .CARRY (INT_CARRY[156]) ); smfulladder dfa132 (.DATA_A (INT_SUM[191]), .DATA_B (INT_SUM[192]), .DATA_C (INT_CARRY[144]), .SAVE (INT_SUM[193]), .CARRY (INT_CARRY[145]) ); smffb dla244 (.D(INT_SUM[193]), .clk(clk), .en_d2(en_d2), .Q(SUM[25]) ); smffb dla245 (.D(INT_CARRY[145]), .clk(clk), .en_d2(en_d2), .Q(CARRY[25]) ); smffa dla246 (.D(SUMMAND[195]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[195]) ); smffa dla247 (.D(SUMMAND[196]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[196]) ); smffa dla248 (.D(SUMMAND[197]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[197]) ); smfulladder dfa133 (.DATA_A (LATCHED_PP[195]), .DATA_B (LATCHED_PP[196]), .DATA_C (LATCHED_PP[197]), .SAVE (INT_SUM[194]), .CARRY (INT_CARRY[158]) ); smffa dla249 (.D(SUMMAND[198]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[198]) ); smffa dla250 (.D(SUMMAND[199]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[199]) ); smffa dla251 (.D(SUMMAND[200]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[200]) ); smfulladder dfa134 (.DATA_A (LATCHED_PP[198]), .DATA_B (LATCHED_PP[199]), .DATA_C (LATCHED_PP[200]), .SAVE (INT_SUM[195]), .CARRY (INT_CARRY[159]) ); smffa dla252 (.D(SUMMAND[201]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[201]) ); smffa dla253 (.D(SUMMAND[202]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[202]) ); smffa dla254 (.D(SUMMAND[203]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[203]) ); smfulladder dfa135 (.DATA_A (LATCHED_PP[201]), .DATA_B (LATCHED_PP[202]), .DATA_C (LATCHED_PP[203]), .SAVE (INT_SUM[196]), .CARRY (INT_CARRY[160]) ); smffa dla255 (.D(SUMMAND[204]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[204]) ); smffa dla256 (.D(SUMMAND[205]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[205]) ); smffa dla257 (.D(SUMMAND[206]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[206]) ); smfulladder dfa136 (.DATA_A (LATCHED_PP[204]), .DATA_B (LATCHED_PP[205]), .DATA_C (LATCHED_PP[206]), .SAVE (INT_SUM[197]), .CARRY (INT_CARRY[161]) ); smffa dla258 (.D(SUMMAND[207]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[207]) ); smffa dla259 (.D(SUMMAND[208]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[208]) ); smffa dla260 (.D(SUMMAND[209]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[209]) ); smfulladder dfa137 (.DATA_A (LATCHED_PP[207]), .DATA_B (LATCHED_PP[208]), .DATA_C (LATCHED_PP[209]), .SAVE (INT_SUM[198]), .CARRY (INT_CARRY[162]) ); smfulladder dfa138 (.DATA_A (INT_SUM[194]), .DATA_B (INT_SUM[195]), .DATA_C (INT_SUM[196]), .SAVE (INT_SUM[199]), .CARRY (INT_CARRY[163]) ); smfulladder dfa139 (.DATA_A (INT_SUM[197]), .DATA_B (INT_SUM[198]), .DATA_C (INT_CARRY[146]), .SAVE (INT_SUM[200]), .CARRY (INT_CARRY[164]) ); smfulladder dfa140 (.DATA_A (INT_CARRY[147]), .DATA_B (INT_CARRY[148]), .DATA_C (INT_CARRY[149]), .SAVE (INT_SUM[201]), .CARRY (INT_CARRY[165]) ); smfulladder dfa141 (.DATA_A (INT_SUM[199]), .DATA_B (INT_SUM[200]), .DATA_C (INT_SUM[201]), .SAVE (INT_SUM[202]), .CARRY (INT_CARRY[166]) ); smfulladder dfa142 (.DATA_A (INT_CARRY[150]), .DATA_B (INT_CARRY[151]), .DATA_C (INT_CARRY[152]), .SAVE (INT_SUM[203]), .CARRY (INT_CARRY[167]) ); smfulladder dfa143 (.DATA_A (INT_SUM[202]), .DATA_B (INT_SUM[203]), .DATA_C (INT_CARRY[153]), .SAVE (INT_SUM[204]), .CARRY (INT_CARRY[168]) ); assign INT_SUM[205] = INT_CARRY[154]; smfulladder dfa144 (.DATA_A (INT_SUM[204]), .DATA_B (INT_SUM[205]), .DATA_C (INT_CARRY[155]), .SAVE (INT_SUM[206]), .CARRY (INT_CARRY[169]) ); assign INT_SUM[207] = INT_CARRY[156]; smhalfadder dha24 (.DATA_A (INT_SUM[206]), .DATA_B (INT_SUM[207]), .SAVE (INT_SUM[208]), .CARRY (INT_CARRY[157]) ); smffb dla261 (.D(INT_SUM[208]), .clk(clk), .en_d2(en_d2), .Q(SUM[26]) ); smffb dla262 (.D(INT_CARRY[157]), .clk(clk), .en_d2(en_d2), .Q(CARRY[26]) ); smffa dla263 (.D(SUMMAND[210]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[210]) ); smffa dla264 (.D(SUMMAND[211]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[211]) ); smffa dla265 (.D(SUMMAND[212]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[212]) ); smfulladder dfa145 (.DATA_A (LATCHED_PP[210]), .DATA_B (LATCHED_PP[211]), .DATA_C (LATCHED_PP[212]), .SAVE (INT_SUM[209]), .CARRY (INT_CARRY[171]) ); smffa dla266 (.D(SUMMAND[213]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[213]) ); smffa dla267 (.D(SUMMAND[214]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[214]) ); smffa dla268 (.D(SUMMAND[215]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[215]) ); smfulladder dfa146 (.DATA_A (LATCHED_PP[213]), .DATA_B (LATCHED_PP[214]), .DATA_C (LATCHED_PP[215]), .SAVE (INT_SUM[210]), .CARRY (INT_CARRY[172]) ); smffa dla269 (.D(SUMMAND[216]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[216]) ); smffa dla270 (.D(SUMMAND[217]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[217]) ); smffa dla271 (.D(SUMMAND[218]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[218]) ); smfulladder dfa147 (.DATA_A (LATCHED_PP[216]), .DATA_B (LATCHED_PP[217]), .DATA_C (LATCHED_PP[218]), .SAVE (INT_SUM[211]), .CARRY (INT_CARRY[173]) ); smffa dla272 (.D(SUMMAND[219]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[219]) ); smffa dla273 (.D(SUMMAND[220]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[220]) ); smffa dla274 (.D(SUMMAND[221]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[221]) ); smfulladder dfa148 (.DATA_A (LATCHED_PP[219]), .DATA_B (LATCHED_PP[220]), .DATA_C (LATCHED_PP[221]), .SAVE (INT_SUM[212]), .CARRY (INT_CARRY[174]) ); smffa dla275 (.D(SUMMAND[222]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[222]) ); smffa dla276 (.D(SUMMAND[223]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[223]) ); smhalfadder dha25 (.DATA_A (LATCHED_PP[222]), .DATA_B (LATCHED_PP[223]), .SAVE (INT_SUM[213]), .CARRY (INT_CARRY[175]) ); smfulladder dfa149 (.DATA_A (INT_SUM[209]), .DATA_B (INT_SUM[210]), .DATA_C (INT_SUM[211]), .SAVE (INT_SUM[214]), .CARRY (INT_CARRY[176]) ); smfulladder dfa150 (.DATA_A (INT_SUM[212]), .DATA_B (INT_SUM[213]), .DATA_C (INT_CARRY[158]), .SAVE (INT_SUM[215]), .CARRY (INT_CARRY[177]) ); smfulladder dfa151 (.DATA_A (INT_CARRY[159]), .DATA_B (INT_CARRY[160]), .DATA_C (INT_CARRY[161]), .SAVE (INT_SUM[216]), .CARRY (INT_CARRY[178]) ); assign INT_SUM[217] = INT_CARRY[162]; smfulladder dfa152 (.DATA_A (INT_SUM[214]), .DATA_B (INT_SUM[215]), .DATA_C (INT_SUM[216]), .SAVE (INT_SUM[218]), .CARRY (INT_CARRY[179]) ); smfulladder dfa153 (.DATA_A (INT_SUM[217]), .DATA_B (INT_CARRY[163]), .DATA_C (INT_CARRY[164]), .SAVE (INT_SUM[219]), .CARRY (INT_CARRY[180]) ); assign INT_SUM[220] = INT_CARRY[165]; smfulladder dfa154 (.DATA_A (INT_SUM[218]), .DATA_B (INT_SUM[219]), .DATA_C (INT_SUM[220]), .SAVE (INT_SUM[221]), .CARRY (INT_CARRY[181]) ); assign INT_SUM[222] = INT_CARRY[166]; assign INT_SUM[223] = INT_CARRY[167]; smfulladder dfa155 (.DATA_A (INT_SUM[221]), .DATA_B (INT_SUM[222]), .DATA_C (INT_SUM[223]), .SAVE (INT_SUM[224]), .CARRY (INT_CARRY[182]) ); assign INT_SUM[225] = INT_CARRY[168]; smfulladder dfa156 (.DATA_A (INT_SUM[224]), .DATA_B (INT_SUM[225]), .DATA_C (INT_CARRY[169]), .SAVE (INT_SUM[226]), .CARRY (INT_CARRY[170]) ); smffb dla277 (.D(INT_SUM[226]), .clk(clk), .en_d2(en_d2), .Q(SUM[27]) ); smffb dla278 (.D(INT_CARRY[170]), .clk(clk), .en_d2(en_d2), .Q(CARRY[27]) ); smffa dla279 (.D(SUMMAND[224]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[224]) ); smffa dla280 (.D(SUMMAND[225]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[225]) ); smffa dla281 (.D(SUMMAND[226]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[226]) ); smfulladder dfa157 (.DATA_A (LATCHED_PP[224]), .DATA_B (LATCHED_PP[225]), .DATA_C (LATCHED_PP[226]), .SAVE (INT_SUM[227]), .CARRY (INT_CARRY[184]) ); smffa dla282 (.D(SUMMAND[227]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[227]) ); smffa dla283 (.D(SUMMAND[228]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[228]) ); smffa dla284 (.D(SUMMAND[229]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[229]) ); smfulladder dfa158 (.DATA_A (LATCHED_PP[227]), .DATA_B (LATCHED_PP[228]), .DATA_C (LATCHED_PP[229]), .SAVE (INT_SUM[228]), .CARRY (INT_CARRY[185]) ); smffa dla285 (.D(SUMMAND[230]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[230]) ); smffa dla286 (.D(SUMMAND[231]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[231]) ); smffa dla287 (.D(SUMMAND[232]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[232]) ); smfulladder dfa159 (.DATA_A (LATCHED_PP[230]), .DATA_B (LATCHED_PP[231]), .DATA_C (LATCHED_PP[232]), .SAVE (INT_SUM[229]), .CARRY (INT_CARRY[186]) ); smffa dla288 (.D(SUMMAND[233]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[233]) ); smffa dla289 (.D(SUMMAND[234]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[234]) ); smffa dla290 (.D(SUMMAND[235]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[235]) ); smfulladder dfa160 (.DATA_A (LATCHED_PP[233]), .DATA_B (LATCHED_PP[234]), .DATA_C (LATCHED_PP[235]), .SAVE (INT_SUM[230]), .CARRY (INT_CARRY[187]) ); smffa dla291 (.D(SUMMAND[236]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[236]) ); smffa dla292 (.D(SUMMAND[237]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[237]) ); smffa dla293 (.D(SUMMAND[238]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[238]) ); smfulladder dfa161 (.DATA_A (LATCHED_PP[236]), .DATA_B (LATCHED_PP[237]), .DATA_C (LATCHED_PP[238]), .SAVE (INT_SUM[231]), .CARRY (INT_CARRY[188]) ); smffa dla294 (.D(SUMMAND[239]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[239]) ); assign INT_SUM[232] = LATCHED_PP[239]; smfulladder dfa162 (.DATA_A (INT_SUM[227]), .DATA_B (INT_SUM[228]), .DATA_C (INT_SUM[229]), .SAVE (INT_SUM[233]), .CARRY (INT_CARRY[189]) ); smfulladder dfa163 (.DATA_A (INT_SUM[230]), .DATA_B (INT_SUM[231]), .DATA_C (INT_SUM[232]), .SAVE (INT_SUM[234]), .CARRY (INT_CARRY[190]) ); smfulladder dfa164 (.DATA_A (INT_CARRY[171]), .DATA_B (INT_CARRY[172]), .DATA_C (INT_CARRY[173]), .SAVE (INT_SUM[235]), .CARRY (INT_CARRY[191]) ); assign INT_SUM[236] = INT_CARRY[174]; assign INT_SUM[237] = INT_CARRY[175]; smfulladder dfa165 (.DATA_A (INT_SUM[233]), .DATA_B (INT_SUM[234]), .DATA_C (INT_SUM[235]), .SAVE (INT_SUM[238]), .CARRY (INT_CARRY[192]) ); smfulladder dfa166 (.DATA_A (INT_SUM[236]), .DATA_B (INT_SUM[237]), .DATA_C (INT_CARRY[176]), .SAVE (INT_SUM[239]), .CARRY (INT_CARRY[193]) ); assign INT_SUM[240] = INT_CARRY[177]; assign INT_SUM[241] = INT_CARRY[178]; smfulladder dfa167 (.DATA_A (INT_SUM[238]), .DATA_B (INT_SUM[239]), .DATA_C (INT_SUM[240]), .SAVE (INT_SUM[242]), .CARRY (INT_CARRY[194]) ); smfulladder dfa168 (.DATA_A (INT_SUM[241]), .DATA_B (INT_CARRY[179]), .DATA_C (INT_CARRY[180]), .SAVE (INT_SUM[243]), .CARRY (INT_CARRY[195]) ); smfulladder dfa169 (.DATA_A (INT_SUM[242]), .DATA_B (INT_SUM[243]), .DATA_C (INT_CARRY[181]), .SAVE (INT_SUM[244]), .CARRY (INT_CARRY[196]) ); smhalfadder dha26 (.DATA_A (INT_SUM[244]), .DATA_B (INT_CARRY[182]), .SAVE (INT_SUM[245]), .CARRY (INT_CARRY[183]) ); smffb dla295 (.D(INT_SUM[245]), .clk(clk), .en_d2(en_d2), .Q(SUM[28]) ); smffb dla296 (.D(INT_CARRY[183]), .clk(clk), .en_d2(en_d2), .Q(CARRY[28]) ); smffa dla297 (.D(SUMMAND[240]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[240]) ); smffa dla298 (.D(SUMMAND[241]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[241]) ); smffa dla299 (.D(SUMMAND[242]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[242]) ); smfulladder dfa170 (.DATA_A (LATCHED_PP[240]), .DATA_B (LATCHED_PP[241]), .DATA_C (LATCHED_PP[242]), .SAVE (INT_SUM[246]), .CARRY (INT_CARRY[198]) ); smffa dla300 (.D(SUMMAND[243]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[243]) ); smffa dla301 (.D(SUMMAND[244]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[244]) ); smffa dla302 (.D(SUMMAND[245]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[245]) ); smfulladder dfa171 (.DATA_A (LATCHED_PP[243]), .DATA_B (LATCHED_PP[244]), .DATA_C (LATCHED_PP[245]), .SAVE (INT_SUM[247]), .CARRY (INT_CARRY[199]) ); smffa dla303 (.D(SUMMAND[246]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[246]) ); smffa dla304 (.D(SUMMAND[247]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[247]) ); smffa dla305 (.D(SUMMAND[248]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[248]) ); smfulladder dfa172 (.DATA_A (LATCHED_PP[246]), .DATA_B (LATCHED_PP[247]), .DATA_C (LATCHED_PP[248]), .SAVE (INT_SUM[248]), .CARRY (INT_CARRY[200]) ); smffa dla306 (.D(SUMMAND[249]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[249]) ); smffa dla307 (.D(SUMMAND[250]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[250]) ); smffa dla308 (.D(SUMMAND[251]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[251]) ); smfulladder dfa173 (.DATA_A (LATCHED_PP[249]), .DATA_B (LATCHED_PP[250]), .DATA_C (LATCHED_PP[251]), .SAVE (INT_SUM[249]), .CARRY (INT_CARRY[201]) ); smffa dla309 (.D(SUMMAND[252]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[252]) ); smffa dla310 (.D(SUMMAND[253]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[253]) ); smffa dla311 (.D(SUMMAND[254]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[254]) ); smfulladder dfa174 (.DATA_A (LATCHED_PP[252]), .DATA_B (LATCHED_PP[253]), .DATA_C (LATCHED_PP[254]), .SAVE (INT_SUM[250]), .CARRY (INT_CARRY[202]) ); smfulladder dfa175 (.DATA_A (INT_SUM[246]), .DATA_B (INT_SUM[247]), .DATA_C (INT_SUM[248]), .SAVE (INT_SUM[251]), .CARRY (INT_CARRY[203]) ); smfulladder dfa176 (.DATA_A (INT_SUM[249]), .DATA_B (INT_SUM[250]), .DATA_C (INT_CARRY[184]), .SAVE (INT_SUM[252]), .CARRY (INT_CARRY[204]) ); smfulladder dfa177 (.DATA_A (INT_CARRY[185]), .DATA_B (INT_CARRY[186]), .DATA_C (INT_CARRY[187]), .SAVE (INT_SUM[253]), .CARRY (INT_CARRY[205]) ); assign INT_SUM[254] = INT_CARRY[188]; smfulladder dfa178 (.DATA_A (INT_SUM[251]), .DATA_B (INT_SUM[252]), .DATA_C (INT_SUM[253]), .SAVE (INT_SUM[255]), .CARRY (INT_CARRY[206]) ); smfulladder dfa179 (.DATA_A (INT_SUM[254]), .DATA_B (INT_CARRY[189]), .DATA_C (INT_CARRY[190]), .SAVE (INT_SUM[256]), .CARRY (INT_CARRY[207]) ); assign INT_SUM[257] = INT_CARRY[191]; smfulladder dfa180 (.DATA_A (INT_SUM[255]), .DATA_B (INT_SUM[256]), .DATA_C (INT_SUM[257]), .SAVE (INT_SUM[258]), .CARRY (INT_CARRY[208]) ); smhalfadder dha27 (.DATA_A (INT_CARRY[192]), .DATA_B (INT_CARRY[193]), .SAVE (INT_SUM[259]), .CARRY (INT_CARRY[209]) ); smfulladder dfa181 (.DATA_A (INT_SUM[258]), .DATA_B (INT_SUM[259]), .DATA_C (INT_CARRY[194]), .SAVE (INT_SUM[260]), .CARRY (INT_CARRY[210]) ); assign INT_SUM[261] = INT_CARRY[195]; smfulladder dfa182 (.DATA_A (INT_SUM[260]), .DATA_B (INT_SUM[261]), .DATA_C (INT_CARRY[196]), .SAVE (INT_SUM[262]), .CARRY (INT_CARRY[197]) ); smffb dla312 (.D(INT_SUM[262]), .clk(clk), .en_d2(en_d2), .Q(SUM[29]) ); smffb dla313 (.D(INT_CARRY[197]), .clk(clk), .en_d2(en_d2), .Q(CARRY[29]) ); smffa dla314 (.D(SUMMAND[255]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[255]) ); smffa dla315 (.D(SUMMAND[256]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[256]) ); smffa dla316 (.D(SUMMAND[257]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[257]) ); smfulladder dfa183 (.DATA_A (LATCHED_PP[255]), .DATA_B (LATCHED_PP[256]), .DATA_C (LATCHED_PP[257]), .SAVE (INT_SUM[263]), .CARRY (INT_CARRY[212]) ); smffa dla317 (.D(SUMMAND[258]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[258]) ); smffa dla318 (.D(SUMMAND[259]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[259]) ); smffa dla319 (.D(SUMMAND[260]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[260]) ); smfulladder dfa184 (.DATA_A (LATCHED_PP[258]), .DATA_B (LATCHED_PP[259]), .DATA_C (LATCHED_PP[260]), .SAVE (INT_SUM[264]), .CARRY (INT_CARRY[213]) ); smffa dla320 (.D(SUMMAND[261]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[261]) ); smffa dla321 (.D(SUMMAND[262]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[262]) ); smffa dla322 (.D(SUMMAND[263]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[263]) ); smfulladder dfa185 (.DATA_A (LATCHED_PP[261]), .DATA_B (LATCHED_PP[262]), .DATA_C (LATCHED_PP[263]), .SAVE (INT_SUM[265]), .CARRY (INT_CARRY[214]) ); smffa dla323 (.D(SUMMAND[264]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[264]) ); smffa dla324 (.D(SUMMAND[265]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[265]) ); smffa dla325 (.D(SUMMAND[266]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[266]) ); smfulladder dfa186 (.DATA_A (LATCHED_PP[264]), .DATA_B (LATCHED_PP[265]), .DATA_C (LATCHED_PP[266]), .SAVE (INT_SUM[266]), .CARRY (INT_CARRY[215]) ); smffa dla326 (.D(SUMMAND[267]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[267]) ); smffa dla327 (.D(SUMMAND[268]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[268]) ); smffa dla328 (.D(SUMMAND[269]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[269]) ); smfulladder dfa187 (.DATA_A (LATCHED_PP[267]), .DATA_B (LATCHED_PP[268]), .DATA_C (LATCHED_PP[269]), .SAVE (INT_SUM[267]), .CARRY (INT_CARRY[216]) ); smffa dla329 (.D(SUMMAND[270]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[270]) ); assign INT_SUM[268] = LATCHED_PP[270]; smffa dla330 (.D(SUMMAND[271]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[271]) ); assign INT_SUM[269] = LATCHED_PP[271]; smfulladder dfa188 (.DATA_A (INT_SUM[263]), .DATA_B (INT_SUM[264]), .DATA_C (INT_SUM[265]), .SAVE (INT_SUM[270]), .CARRY (INT_CARRY[217]) ); smfulladder dfa189 (.DATA_A (INT_SUM[266]), .DATA_B (INT_SUM[267]), .DATA_C (INT_SUM[268]), .SAVE (INT_SUM[271]), .CARRY (INT_CARRY[218]) ); smfulladder dfa190 (.DATA_A (INT_SUM[269]), .DATA_B (INT_CARRY[198]), .DATA_C (INT_CARRY[199]), .SAVE (INT_SUM[272]), .CARRY (INT_CARRY[219]) ); smfulladder dfa191 (.DATA_A (INT_CARRY[200]), .DATA_B (INT_CARRY[201]), .DATA_C (INT_CARRY[202]), .SAVE (INT_SUM[273]), .CARRY (INT_CARRY[220]) ); smfulladder dfa192 (.DATA_A (INT_SUM[270]), .DATA_B (INT_SUM[271]), .DATA_C (INT_SUM[272]), .SAVE (INT_SUM[274]), .CARRY (INT_CARRY[221]) ); smfulladder dfa193 (.DATA_A (INT_SUM[273]), .DATA_B (INT_CARRY[203]), .DATA_C (INT_CARRY[204]), .SAVE (INT_SUM[275]), .CARRY (INT_CARRY[222]) ); assign INT_SUM[276] = INT_CARRY[205]; smfulladder dfa194 (.DATA_A (INT_SUM[274]), .DATA_B (INT_SUM[275]), .DATA_C (INT_SUM[276]), .SAVE (INT_SUM[277]), .CARRY (INT_CARRY[223]) ); smhalfadder dha28 (.DATA_A (INT_CARRY[206]), .DATA_B (INT_CARRY[207]), .SAVE (INT_SUM[278]), .CARRY (INT_CARRY[224]) ); smfulladder dfa195 (.DATA_A (INT_SUM[277]), .DATA_B (INT_SUM[278]), .DATA_C (INT_CARRY[208]), .SAVE (INT_SUM[279]), .CARRY (INT_CARRY[225]) ); assign INT_SUM[280] = INT_CARRY[209]; smfulladder dfa196 (.DATA_A (INT_SUM[279]), .DATA_B (INT_SUM[280]), .DATA_C (INT_CARRY[210]), .SAVE (INT_SUM[281]), .CARRY (INT_CARRY[211]) ); smffb dla331 (.D(INT_SUM[281]), .clk(clk), .en_d2(en_d2), .Q(SUM[30]) ); smffb dla332 (.D(INT_CARRY[211]), .clk(clk), .en_d2(en_d2), .Q(CARRY[30]) ); smffa dla333 (.D(SUMMAND[272]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[272]) ); smffa dla334 (.D(SUMMAND[273]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[273]) ); smffa dla335 (.D(SUMMAND[274]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[274]) ); smfulladder dfa197 (.DATA_A (LATCHED_PP[272]), .DATA_B (LATCHED_PP[273]), .DATA_C (LATCHED_PP[274]), .SAVE (INT_SUM[282]), .CARRY (INT_CARRY[227]) ); smffa dla336 (.D(SUMMAND[275]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[275]) ); smffa dla337 (.D(SUMMAND[276]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[276]) ); smffa dla338 (.D(SUMMAND[277]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[277]) ); smfulladder dfa198 (.DATA_A (LATCHED_PP[275]), .DATA_B (LATCHED_PP[276]), .DATA_C (LATCHED_PP[277]), .SAVE (INT_SUM[283]), .CARRY (INT_CARRY[228]) ); smffa dla339 (.D(SUMMAND[278]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[278]) ); smffa dla340 (.D(SUMMAND[279]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[279]) ); smffa dla341 (.D(SUMMAND[280]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[280]) ); smfulladder dfa199 (.DATA_A (LATCHED_PP[278]), .DATA_B (LATCHED_PP[279]), .DATA_C (LATCHED_PP[280]), .SAVE (INT_SUM[284]), .CARRY (INT_CARRY[229]) ); smffa dla342 (.D(SUMMAND[281]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[281]) ); smffa dla343 (.D(SUMMAND[282]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[282]) ); smffa dla344 (.D(SUMMAND[283]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[283]) ); smfulladder dfa200 (.DATA_A (LATCHED_PP[281]), .DATA_B (LATCHED_PP[282]), .DATA_C (LATCHED_PP[283]), .SAVE (INT_SUM[285]), .CARRY (INT_CARRY[230]) ); smffa dla345 (.D(SUMMAND[284]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[284]) ); smffa dla346 (.D(SUMMAND[285]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[285]) ); smffa dla347 (.D(SUMMAND[286]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[286]) ); smfulladder dfa201 (.DATA_A (LATCHED_PP[284]), .DATA_B (LATCHED_PP[285]), .DATA_C (LATCHED_PP[286]), .SAVE (INT_SUM[286]), .CARRY (INT_CARRY[231]) ); smffa dla348 (.D(SUMMAND[287]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[287]) ); assign INT_SUM[287] = LATCHED_PP[287]; smfulladder dfa202 (.DATA_A (INT_SUM[282]), .DATA_B (INT_SUM[283]), .DATA_C (INT_SUM[284]), .SAVE (INT_SUM[288]), .CARRY (INT_CARRY[232]) ); smfulladder dfa203 (.DATA_A (INT_SUM[285]), .DATA_B (INT_SUM[286]), .DATA_C (INT_SUM[287]), .SAVE (INT_SUM[289]), .CARRY (INT_CARRY[233]) ); smfulladder dfa204 (.DATA_A (INT_CARRY[212]), .DATA_B (INT_CARRY[213]), .DATA_C (INT_CARRY[214]), .SAVE (INT_SUM[290]), .CARRY (INT_CARRY[234]) ); assign INT_SUM[291] = INT_CARRY[215]; assign INT_SUM[292] = INT_CARRY[216]; smfulladder dfa205 (.DATA_A (INT_SUM[288]), .DATA_B (INT_SUM[289]), .DATA_C (INT_SUM[290]), .SAVE (INT_SUM[293]), .CARRY (INT_CARRY[235]) ); smfulladder dfa206 (.DATA_A (INT_SUM[291]), .DATA_B (INT_SUM[292]), .DATA_C (INT_CARRY[217]), .SAVE (INT_SUM[294]), .CARRY (INT_CARRY[236]) ); smfulladder dfa207 (.DATA_A (INT_CARRY[218]), .DATA_B (INT_CARRY[219]), .DATA_C (INT_CARRY[220]), .SAVE (INT_SUM[295]), .CARRY (INT_CARRY[237]) ); smfulladder dfa208 (.DATA_A (INT_SUM[293]), .DATA_B (INT_SUM[294]), .DATA_C (INT_SUM[295]), .SAVE (INT_SUM[296]), .CARRY (INT_CARRY[238]) ); smhalfadder dha29 (.DATA_A (INT_CARRY[221]), .DATA_B (INT_CARRY[222]), .SAVE (INT_SUM[297]), .CARRY (INT_CARRY[239]) ); smfulladder dfa209 (.DATA_A (INT_SUM[296]), .DATA_B (INT_SUM[297]), .DATA_C (INT_CARRY[223]), .SAVE (INT_SUM[298]), .CARRY (INT_CARRY[240]) ); assign INT_SUM[299] = INT_CARRY[224]; smfulladder dfa210 (.DATA_A (INT_SUM[298]), .DATA_B (INT_SUM[299]), .DATA_C (INT_CARRY[225]), .SAVE (INT_SUM[300]), .CARRY (INT_CARRY[226]) ); smffb dla349 (.D(INT_SUM[300]), .clk(clk), .en_d2(en_d2), .Q(SUM[31]) ); smffb dla350 (.D(INT_CARRY[226]), .clk(clk), .en_d2(en_d2), .Q(CARRY[31]) ); smffa dla351 (.D(SUMMAND[288]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[288]) ); smffa dla352 (.D(SUMMAND[289]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[289]) ); smffa dla353 (.D(SUMMAND[290]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[290]) ); smfulladder dfa211 (.DATA_A (LATCHED_PP[288]), .DATA_B (LATCHED_PP[289]), .DATA_C (LATCHED_PP[290]), .SAVE (INT_SUM[301]), .CARRY (INT_CARRY[242]) ); smffa dla354 (.D(SUMMAND[291]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[291]) ); smffa dla355 (.D(SUMMAND[292]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[292]) ); smffa dla356 (.D(SUMMAND[293]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[293]) ); smfulladder dfa212 (.DATA_A (LATCHED_PP[291]), .DATA_B (LATCHED_PP[292]), .DATA_C (LATCHED_PP[293]), .SAVE (INT_SUM[302]), .CARRY (INT_CARRY[243]) ); smffa dla357 (.D(SUMMAND[294]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[294]) ); smffa dla358 (.D(SUMMAND[295]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[295]) ); smffa dla359 (.D(SUMMAND[296]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[296]) ); smfulladder dfa213 (.DATA_A (LATCHED_PP[294]), .DATA_B (LATCHED_PP[295]), .DATA_C (LATCHED_PP[296]), .SAVE (INT_SUM[303]), .CARRY (INT_CARRY[244]) ); smffa dla360 (.D(SUMMAND[297]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[297]) ); smffa dla361 (.D(SUMMAND[298]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[298]) ); smffa dla362 (.D(SUMMAND[299]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[299]) ); smfulladder dfa214 (.DATA_A (LATCHED_PP[297]), .DATA_B (LATCHED_PP[298]), .DATA_C (LATCHED_PP[299]), .SAVE (INT_SUM[304]), .CARRY (INT_CARRY[245]) ); smffa dla363 (.D(SUMMAND[300]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[300]) ); smffa dla364 (.D(SUMMAND[301]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[301]) ); smffa dla365 (.D(SUMMAND[302]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[302]) ); smfulladder dfa215 (.DATA_A (LATCHED_PP[300]), .DATA_B (LATCHED_PP[301]), .DATA_C (LATCHED_PP[302]), .SAVE (INT_SUM[305]), .CARRY (INT_CARRY[246]) ); smffa dla366 (.D(SUMMAND[303]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[303]) ); smffa dla367 (.D(SUMMAND[304]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[304]) ); smffa dla368 (.D(SUMMAND[305]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[305]) ); smfulladder dfa216 (.DATA_A (LATCHED_PP[303]), .DATA_B (LATCHED_PP[304]), .DATA_C (LATCHED_PP[305]), .SAVE (INT_SUM[306]), .CARRY (INT_CARRY[247]) ); smfulladder dfa217 (.DATA_A (INT_SUM[301]), .DATA_B (INT_SUM[302]), .DATA_C (INT_SUM[303]), .SAVE (INT_SUM[307]), .CARRY (INT_CARRY[248]) ); smfulladder dfa218 (.DATA_A (INT_SUM[304]), .DATA_B (INT_SUM[305]), .DATA_C (INT_SUM[306]), .SAVE (INT_SUM[308]), .CARRY (INT_CARRY[249]) ); smfulladder dfa219 (.DATA_A (INT_CARRY[227]), .DATA_B (INT_CARRY[228]), .DATA_C (INT_CARRY[229]), .SAVE (INT_SUM[309]), .CARRY (INT_CARRY[250]) ); smhalfadder dha30 (.DATA_A (INT_CARRY[230]), .DATA_B (INT_CARRY[231]), .SAVE (INT_SUM[310]), .CARRY (INT_CARRY[251]) ); smfulladder dfa220 (.DATA_A (INT_SUM[307]), .DATA_B (INT_SUM[308]), .DATA_C (INT_SUM[309]), .SAVE (INT_SUM[311]), .CARRY (INT_CARRY[252]) ); smfulladder dfa221 (.DATA_A (INT_SUM[310]), .DATA_B (INT_CARRY[232]), .DATA_C (INT_CARRY[233]), .SAVE (INT_SUM[312]), .CARRY (INT_CARRY[253]) ); assign INT_SUM[313] = INT_CARRY[234]; smfulladder dfa222 (.DATA_A (INT_SUM[311]), .DATA_B (INT_SUM[312]), .DATA_C (INT_SUM[313]), .SAVE (INT_SUM[314]), .CARRY (INT_CARRY[254]) ); smfulladder dfa223 (.DATA_A (INT_CARRY[235]), .DATA_B (INT_CARRY[236]), .DATA_C (INT_CARRY[237]), .SAVE (INT_SUM[315]), .CARRY (INT_CARRY[255]) ); smfulladder dfa224 (.DATA_A (INT_SUM[314]), .DATA_B (INT_SUM[315]), .DATA_C (INT_CARRY[238]), .SAVE (INT_SUM[316]), .CARRY (INT_CARRY[256]) ); assign INT_SUM[317] = INT_CARRY[239]; smfulladder dfa225 (.DATA_A (INT_SUM[316]), .DATA_B (INT_SUM[317]), .DATA_C (INT_CARRY[240]), .SAVE (INT_SUM[318]), .CARRY (INT_CARRY[241]) ); smffb dla369 (.D(INT_SUM[318]), .clk(clk), .en_d2(en_d2), .Q(SUM[32]) ); smffb dla370 (.D(INT_CARRY[241]), .clk(clk), .en_d2(en_d2), .Q(CARRY[32]) ); smffa dla371 (.D(SUMMAND[306]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[306]) ); smffa dla372 (.D(SUMMAND[307]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[307]) ); smffa dla373 (.D(SUMMAND[308]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[308]) ); smfulladder dfa226 (.DATA_A (LATCHED_PP[306]), .DATA_B (LATCHED_PP[307]), .DATA_C (LATCHED_PP[308]), .SAVE (INT_SUM[319]), .CARRY (INT_CARRY[258]) ); smffa dla374 (.D(SUMMAND[309]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[309]) ); smffa dla375 (.D(SUMMAND[310]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[310]) ); smffa dla376 (.D(SUMMAND[311]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[311]) ); smfulladder dfa227 (.DATA_A (LATCHED_PP[309]), .DATA_B (LATCHED_PP[310]), .DATA_C (LATCHED_PP[311]), .SAVE (INT_SUM[320]), .CARRY (INT_CARRY[259]) ); smffa dla377 (.D(SUMMAND[312]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[312]) ); smffa dla378 (.D(SUMMAND[313]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[313]) ); smffa dla379 (.D(SUMMAND[314]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[314]) ); smfulladder dfa228 (.DATA_A (LATCHED_PP[312]), .DATA_B (LATCHED_PP[313]), .DATA_C (LATCHED_PP[314]), .SAVE (INT_SUM[321]), .CARRY (INT_CARRY[260]) ); smffa dla380 (.D(SUMMAND[315]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[315]) ); smffa dla381 (.D(SUMMAND[316]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[316]) ); smffa dla382 (.D(SUMMAND[317]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[317]) ); smfulladder dfa229 (.DATA_A (LATCHED_PP[315]), .DATA_B (LATCHED_PP[316]), .DATA_C (LATCHED_PP[317]), .SAVE (INT_SUM[322]), .CARRY (INT_CARRY[261]) ); smffa dla383 (.D(SUMMAND[318]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[318]) ); smffa dla384 (.D(SUMMAND[319]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[319]) ); smffa dla385 (.D(SUMMAND[320]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[320]) ); smfulladder dfa230 (.DATA_A (LATCHED_PP[318]), .DATA_B (LATCHED_PP[319]), .DATA_C (LATCHED_PP[320]), .SAVE (INT_SUM[323]), .CARRY (INT_CARRY[262]) ); smffa dla386 (.D(SUMMAND[321]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[321]) ); assign INT_SUM[324] = LATCHED_PP[321]; smffa dla387 (.D(SUMMAND[322]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[322]) ); assign INT_SUM[325] = LATCHED_PP[322]; smfulladder dfa231 (.DATA_A (INT_SUM[319]), .DATA_B (INT_SUM[320]), .DATA_C (INT_SUM[321]), .SAVE (INT_SUM[326]), .CARRY (INT_CARRY[263]) ); smfulladder dfa232 (.DATA_A (INT_SUM[322]), .DATA_B (INT_SUM[323]), .DATA_C (INT_SUM[324]), .SAVE (INT_SUM[327]), .CARRY (INT_CARRY[264]) ); smfulladder dfa233 (.DATA_A (INT_SUM[325]), .DATA_B (INT_CARRY[242]), .DATA_C (INT_CARRY[243]), .SAVE (INT_SUM[328]), .CARRY (INT_CARRY[265]) ); smfulladder dfa234 (.DATA_A (INT_CARRY[244]), .DATA_B (INT_CARRY[245]), .DATA_C (INT_CARRY[246]), .SAVE (INT_SUM[329]), .CARRY (INT_CARRY[266]) ); assign INT_SUM[330] = INT_CARRY[247]; smfulladder dfa235 (.DATA_A (INT_SUM[326]), .DATA_B (INT_SUM[327]), .DATA_C (INT_SUM[328]), .SAVE (INT_SUM[331]), .CARRY (INT_CARRY[267]) ); smfulladder dfa236 (.DATA_A (INT_SUM[329]), .DATA_B (INT_SUM[330]), .DATA_C (INT_CARRY[248]), .SAVE (INT_SUM[332]), .CARRY (INT_CARRY[268]) ); smfulladder dfa237 (.DATA_A (INT_CARRY[249]), .DATA_B (INT_CARRY[250]), .DATA_C (INT_CARRY[251]), .SAVE (INT_SUM[333]), .CARRY (INT_CARRY[269]) ); smfulladder dfa238 (.DATA_A (INT_SUM[331]), .DATA_B (INT_SUM[332]), .DATA_C (INT_SUM[333]), .SAVE (INT_SUM[334]), .CARRY (INT_CARRY[270]) ); smhalfadder dha31 (.DATA_A (INT_CARRY[252]), .DATA_B (INT_CARRY[253]), .SAVE (INT_SUM[335]), .CARRY (INT_CARRY[271]) ); smfulladder dfa239 (.DATA_A (INT_SUM[334]), .DATA_B (INT_SUM[335]), .DATA_C (INT_CARRY[254]), .SAVE (INT_SUM[336]), .CARRY (INT_CARRY[272]) ); assign INT_SUM[337] = INT_CARRY[255]; smfulladder dfa240 (.DATA_A (INT_SUM[336]), .DATA_B (INT_SUM[337]), .DATA_C (INT_CARRY[256]), .SAVE (INT_SUM[338]), .CARRY (INT_CARRY[257]) ); smffb dla388 (.D(INT_SUM[338]), .clk(clk), .en_d2(en_d2), .Q(SUM[33]) ); smffb dla389 (.D(INT_CARRY[257]), .clk(clk), .en_d2(en_d2), .Q(CARRY[33]) ); smffa dla390 (.D(SUMMAND[323]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[323]) ); smffa dla391 (.D(SUMMAND[324]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[324]) ); smffa dla392 (.D(SUMMAND[325]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[325]) ); smfulladder dfa241 (.DATA_A (LATCHED_PP[323]), .DATA_B (LATCHED_PP[324]), .DATA_C (LATCHED_PP[325]), .SAVE (INT_SUM[339]), .CARRY (INT_CARRY[274]) ); smffa dla393 (.D(SUMMAND[326]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[326]) ); smffa dla394 (.D(SUMMAND[327]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[327]) ); smffa dla395 (.D(SUMMAND[328]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[328]) ); smfulladder dfa242 (.DATA_A (LATCHED_PP[326]), .DATA_B (LATCHED_PP[327]), .DATA_C (LATCHED_PP[328]), .SAVE (INT_SUM[340]), .CARRY (INT_CARRY[275]) ); smffa dla396 (.D(SUMMAND[329]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[329]) ); smffa dla397 (.D(SUMMAND[330]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[330]) ); smffa dla398 (.D(SUMMAND[331]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[331]) ); smfulladder dfa243 (.DATA_A (LATCHED_PP[329]), .DATA_B (LATCHED_PP[330]), .DATA_C (LATCHED_PP[331]), .SAVE (INT_SUM[341]), .CARRY (INT_CARRY[276]) ); smffa dla399 (.D(SUMMAND[332]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[332]) ); smffa dla400 (.D(SUMMAND[333]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[333]) ); smffa dla401 (.D(SUMMAND[334]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[334]) ); smfulladder dfa244 (.DATA_A (LATCHED_PP[332]), .DATA_B (LATCHED_PP[333]), .DATA_C (LATCHED_PP[334]), .SAVE (INT_SUM[342]), .CARRY (INT_CARRY[277]) ); smffa dla402 (.D(SUMMAND[335]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[335]) ); smffa dla403 (.D(SUMMAND[336]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[336]) ); smffa dla404 (.D(SUMMAND[337]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[337]) ); smfulladder dfa245 (.DATA_A (LATCHED_PP[335]), .DATA_B (LATCHED_PP[336]), .DATA_C (LATCHED_PP[337]), .SAVE (INT_SUM[343]), .CARRY (INT_CARRY[278]) ); smffa dla405 (.D(SUMMAND[338]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[338]) ); smffa dla406 (.D(SUMMAND[339]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[339]) ); smffa dla407 (.D(SUMMAND[340]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[340]) ); smfulladder dfa246 (.DATA_A (LATCHED_PP[338]), .DATA_B (LATCHED_PP[339]), .DATA_C (LATCHED_PP[340]), .SAVE (INT_SUM[344]), .CARRY (INT_CARRY[279]) ); smfulladder dfa247 (.DATA_A (INT_SUM[339]), .DATA_B (INT_SUM[340]), .DATA_C (INT_SUM[341]), .SAVE (INT_SUM[345]), .CARRY (INT_CARRY[280]) ); smfulladder dfa248 (.DATA_A (INT_SUM[342]), .DATA_B (INT_SUM[343]), .DATA_C (INT_SUM[344]), .SAVE (INT_SUM[346]), .CARRY (INT_CARRY[281]) ); smfulladder dfa249 (.DATA_A (INT_CARRY[258]), .DATA_B (INT_CARRY[259]), .DATA_C (INT_CARRY[260]), .SAVE (INT_SUM[347]), .CARRY (INT_CARRY[282]) ); assign INT_SUM[348] = INT_CARRY[261]; assign INT_SUM[349] = INT_CARRY[262]; smfulladder dfa250 (.DATA_A (INT_SUM[345]), .DATA_B (INT_SUM[346]), .DATA_C (INT_SUM[347]), .SAVE (INT_SUM[350]), .CARRY (INT_CARRY[283]) ); smfulladder dfa251 (.DATA_A (INT_SUM[348]), .DATA_B (INT_SUM[349]), .DATA_C (INT_CARRY[263]), .SAVE (INT_SUM[351]), .CARRY (INT_CARRY[284]) ); smfulladder dfa252 (.DATA_A (INT_CARRY[264]), .DATA_B (INT_CARRY[265]), .DATA_C (INT_CARRY[266]), .SAVE (INT_SUM[352]), .CARRY (INT_CARRY[285]) ); smfulladder dfa253 (.DATA_A (INT_SUM[350]), .DATA_B (INT_SUM[351]), .DATA_C (INT_SUM[352]), .SAVE (INT_SUM[353]), .CARRY (INT_CARRY[286]) ); smfulladder dfa254 (.DATA_A (INT_CARRY[267]), .DATA_B (INT_CARRY[268]), .DATA_C (INT_CARRY[269]), .SAVE (INT_SUM[354]), .CARRY (INT_CARRY[287]) ); smfulladder dfa255 (.DATA_A (INT_SUM[353]), .DATA_B (INT_SUM[354]), .DATA_C (INT_CARRY[270]), .SAVE (INT_SUM[355]), .CARRY (INT_CARRY[288]) ); assign INT_SUM[356] = INT_CARRY[271]; smfulladder dfa256 (.DATA_A (INT_SUM[355]), .DATA_B (INT_SUM[356]), .DATA_C (INT_CARRY[272]), .SAVE (INT_SUM[357]), .CARRY (INT_CARRY[273]) ); smffb dla408 (.D(INT_SUM[357]), .clk(clk), .en_d2(en_d2), .Q(SUM[34]) ); smffb dla409 (.D(INT_CARRY[273]), .clk(clk), .en_d2(en_d2), .Q(CARRY[34]) ); smffa dla410 (.D(SUMMAND[341]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[341]) ); smffa dla411 (.D(SUMMAND[342]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[342]) ); smffa dla412 (.D(SUMMAND[343]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[343]) ); smfulladder dfa257 (.DATA_A (LATCHED_PP[341]), .DATA_B (LATCHED_PP[342]), .DATA_C (LATCHED_PP[343]), .SAVE (INT_SUM[358]), .CARRY (INT_CARRY[290]) ); smffa dla413 (.D(SUMMAND[344]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[344]) ); smffa dla414 (.D(SUMMAND[345]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[345]) ); smffa dla415 (.D(SUMMAND[346]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[346]) ); smfulladder dfa258 (.DATA_A (LATCHED_PP[344]), .DATA_B (LATCHED_PP[345]), .DATA_C (LATCHED_PP[346]), .SAVE (INT_SUM[359]), .CARRY (INT_CARRY[291]) ); smffa dla416 (.D(SUMMAND[347]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[347]) ); smffa dla417 (.D(SUMMAND[348]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[348]) ); smffa dla418 (.D(SUMMAND[349]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[349]) ); smfulladder dfa259 (.DATA_A (LATCHED_PP[347]), .DATA_B (LATCHED_PP[348]), .DATA_C (LATCHED_PP[349]), .SAVE (INT_SUM[360]), .CARRY (INT_CARRY[292]) ); smffa dla419 (.D(SUMMAND[350]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[350]) ); smffa dla420 (.D(SUMMAND[351]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[351]) ); smffa dla421 (.D(SUMMAND[352]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[352]) ); smfulladder dfa260 (.DATA_A (LATCHED_PP[350]), .DATA_B (LATCHED_PP[351]), .DATA_C (LATCHED_PP[352]), .SAVE (INT_SUM[361]), .CARRY (INT_CARRY[293]) ); smffa dla422 (.D(SUMMAND[353]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[353]) ); smffa dla423 (.D(SUMMAND[354]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[354]) ); smffa dla424 (.D(SUMMAND[355]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[355]) ); smfulladder dfa261 (.DATA_A (LATCHED_PP[353]), .DATA_B (LATCHED_PP[354]), .DATA_C (LATCHED_PP[355]), .SAVE (INT_SUM[362]), .CARRY (INT_CARRY[294]) ); smffa dla425 (.D(SUMMAND[356]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[356]) ); smffa dla426 (.D(SUMMAND[357]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[357]) ); smhalfadder dha32 (.DATA_A (LATCHED_PP[356]), .DATA_B (LATCHED_PP[357]), .SAVE (INT_SUM[363]), .CARRY (INT_CARRY[295]) ); smfulladder dfa262 (.DATA_A (INT_SUM[358]), .DATA_B (INT_SUM[359]), .DATA_C (INT_SUM[360]), .SAVE (INT_SUM[364]), .CARRY (INT_CARRY[296]) ); smfulladder dfa263 (.DATA_A (INT_SUM[361]), .DATA_B (INT_SUM[362]), .DATA_C (INT_SUM[363]), .SAVE (INT_SUM[365]), .CARRY (INT_CARRY[297]) ); smfulladder dfa264 (.DATA_A (INT_CARRY[274]), .DATA_B (INT_CARRY[275]), .DATA_C (INT_CARRY[276]), .SAVE (INT_SUM[366]), .CARRY (INT_CARRY[298]) ); smfulladder dfa265 (.DATA_A (INT_CARRY[277]), .DATA_B (INT_CARRY[278]), .DATA_C (INT_CARRY[279]), .SAVE (INT_SUM[367]), .CARRY (INT_CARRY[299]) ); smfulladder dfa266 (.DATA_A (INT_SUM[364]), .DATA_B (INT_SUM[365]), .DATA_C (INT_SUM[366]), .SAVE (INT_SUM[368]), .CARRY (INT_CARRY[300]) ); smfulladder dfa267 (.DATA_A (INT_SUM[367]), .DATA_B (INT_CARRY[280]), .DATA_C (INT_CARRY[281]), .SAVE (INT_SUM[369]), .CARRY (INT_CARRY[301]) ); assign INT_SUM[370] = INT_CARRY[282]; smfulladder dfa268 (.DATA_A (INT_SUM[368]), .DATA_B (INT_SUM[369]), .DATA_C (INT_SUM[370]), .SAVE (INT_SUM[371]), .CARRY (INT_CARRY[302]) ); smfulladder dfa269 (.DATA_A (INT_CARRY[283]), .DATA_B (INT_CARRY[284]), .DATA_C (INT_CARRY[285]), .SAVE (INT_SUM[372]), .CARRY (INT_CARRY[303]) ); smfulladder dfa270 (.DATA_A (INT_SUM[371]), .DATA_B (INT_SUM[372]), .DATA_C (INT_CARRY[286]), .SAVE (INT_SUM[373]), .CARRY (INT_CARRY[304]) ); assign INT_SUM[374] = INT_CARRY[287]; smfulladder dfa271 (.DATA_A (INT_SUM[373]), .DATA_B (INT_SUM[374]), .DATA_C (INT_CARRY[288]), .SAVE (INT_SUM[375]), .CARRY (INT_CARRY[289]) ); smffb dla427 (.D(INT_SUM[375]), .clk(clk), .en_d2(en_d2), .Q(SUM[35]) ); smffb dla428 (.D(INT_CARRY[289]), .clk(clk), .en_d2(en_d2), .Q(CARRY[35]) ); smffa dla429 (.D(SUMMAND[358]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[358]) ); smffa dla430 (.D(SUMMAND[359]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[359]) ); smffa dla431 (.D(SUMMAND[360]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[360]) ); smfulladder dfa272 (.DATA_A (LATCHED_PP[358]), .DATA_B (LATCHED_PP[359]), .DATA_C (LATCHED_PP[360]), .SAVE (INT_SUM[376]), .CARRY (INT_CARRY[306]) ); smffa dla432 (.D(SUMMAND[361]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[361]) ); smffa dla433 (.D(SUMMAND[362]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[362]) ); smffa dla434 (.D(SUMMAND[363]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[363]) ); smfulladder dfa273 (.DATA_A (LATCHED_PP[361]), .DATA_B (LATCHED_PP[362]), .DATA_C (LATCHED_PP[363]), .SAVE (INT_SUM[377]), .CARRY (INT_CARRY[307]) ); smffa dla435 (.D(SUMMAND[364]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[364]) ); smffa dla436 (.D(SUMMAND[365]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[365]) ); smffa dla437 (.D(SUMMAND[366]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[366]) ); smfulladder dfa274 (.DATA_A (LATCHED_PP[364]), .DATA_B (LATCHED_PP[365]), .DATA_C (LATCHED_PP[366]), .SAVE (INT_SUM[378]), .CARRY (INT_CARRY[308]) ); smffa dla438 (.D(SUMMAND[367]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[367]) ); smffa dla439 (.D(SUMMAND[368]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[368]) ); smffa dla440 (.D(SUMMAND[369]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[369]) ); smfulladder dfa275 (.DATA_A (LATCHED_PP[367]), .DATA_B (LATCHED_PP[368]), .DATA_C (LATCHED_PP[369]), .SAVE (INT_SUM[379]), .CARRY (INT_CARRY[309]) ); smffa dla441 (.D(SUMMAND[370]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[370]) ); smffa dla442 (.D(SUMMAND[371]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[371]) ); smffa dla443 (.D(SUMMAND[372]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[372]) ); smfulladder dfa276 (.DATA_A (LATCHED_PP[370]), .DATA_B (LATCHED_PP[371]), .DATA_C (LATCHED_PP[372]), .SAVE (INT_SUM[380]), .CARRY (INT_CARRY[310]) ); smffa dla444 (.D(SUMMAND[373]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[373]) ); assign INT_SUM[381] = LATCHED_PP[373]; smfulladder dfa277 (.DATA_A (INT_SUM[376]), .DATA_B (INT_SUM[377]), .DATA_C (INT_SUM[378]), .SAVE (INT_SUM[382]), .CARRY (INT_CARRY[311]) ); smfulladder dfa278 (.DATA_A (INT_SUM[379]), .DATA_B (INT_SUM[380]), .DATA_C (INT_SUM[381]), .SAVE (INT_SUM[383]), .CARRY (INT_CARRY[312]) ); smfulladder dfa279 (.DATA_A (INT_CARRY[290]), .DATA_B (INT_CARRY[291]), .DATA_C (INT_CARRY[292]), .SAVE (INT_SUM[384]), .CARRY (INT_CARRY[313]) ); smfulladder dfa280 (.DATA_A (INT_CARRY[293]), .DATA_B (INT_CARRY[294]), .DATA_C (INT_CARRY[295]), .SAVE (INT_SUM[385]), .CARRY (INT_CARRY[314]) ); smfulladder dfa281 (.DATA_A (INT_SUM[382]), .DATA_B (INT_SUM[383]), .DATA_C (INT_SUM[384]), .SAVE (INT_SUM[386]), .CARRY (INT_CARRY[315]) ); smfulladder dfa282 (.DATA_A (INT_SUM[385]), .DATA_B (INT_CARRY[296]), .DATA_C (INT_CARRY[297]), .SAVE (INT_SUM[387]), .CARRY (INT_CARRY[316]) ); assign INT_SUM[388] = INT_CARRY[298]; assign INT_SUM[389] = INT_CARRY[299]; smfulladder dfa283 (.DATA_A (INT_SUM[386]), .DATA_B (INT_SUM[387]), .DATA_C (INT_SUM[388]), .SAVE (INT_SUM[390]), .CARRY (INT_CARRY[317]) ); smfulladder dfa284 (.DATA_A (INT_SUM[389]), .DATA_B (INT_CARRY[300]), .DATA_C (INT_CARRY[301]), .SAVE (INT_SUM[391]), .CARRY (INT_CARRY[318]) ); smfulladder dfa285 (.DATA_A (INT_SUM[390]), .DATA_B (INT_SUM[391]), .DATA_C (INT_CARRY[302]), .SAVE (INT_SUM[392]), .CARRY (INT_CARRY[319]) ); assign INT_SUM[393] = INT_CARRY[303]; smfulladder dfa286 (.DATA_A (INT_SUM[392]), .DATA_B (INT_SUM[393]), .DATA_C (INT_CARRY[304]), .SAVE (INT_SUM[394]), .CARRY (INT_CARRY[305]) ); smffb dla445 (.D(INT_SUM[394]), .clk(clk), .en_d2(en_d2), .Q(SUM[36]) ); smffb dla446 (.D(INT_CARRY[305]), .clk(clk), .en_d2(en_d2), .Q(CARRY[36]) ); smffa dla447 (.D(SUMMAND[374]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[374]) ); smffa dla448 (.D(SUMMAND[375]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[375]) ); smffa dla449 (.D(SUMMAND[376]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[376]) ); smfulladder dfa287 (.DATA_A (LATCHED_PP[374]), .DATA_B (LATCHED_PP[375]), .DATA_C (LATCHED_PP[376]), .SAVE (INT_SUM[395]), .CARRY (INT_CARRY[321]) ); smffa dla450 (.D(SUMMAND[377]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[377]) ); smffa dla451 (.D(SUMMAND[378]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[378]) ); smffa dla452 (.D(SUMMAND[379]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[379]) ); smfulladder dfa288 (.DATA_A (LATCHED_PP[377]), .DATA_B (LATCHED_PP[378]), .DATA_C (LATCHED_PP[379]), .SAVE (INT_SUM[396]), .CARRY (INT_CARRY[322]) ); smffa dla453 (.D(SUMMAND[380]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[380]) ); smffa dla454 (.D(SUMMAND[381]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[381]) ); smffa dla455 (.D(SUMMAND[382]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[382]) ); smfulladder dfa289 (.DATA_A (LATCHED_PP[380]), .DATA_B (LATCHED_PP[381]), .DATA_C (LATCHED_PP[382]), .SAVE (INT_SUM[397]), .CARRY (INT_CARRY[323]) ); smffa dla456 (.D(SUMMAND[383]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[383]) ); smffa dla457 (.D(SUMMAND[384]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[384]) ); smffa dla458 (.D(SUMMAND[385]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[385]) ); smfulladder dfa290 (.DATA_A (LATCHED_PP[383]), .DATA_B (LATCHED_PP[384]), .DATA_C (LATCHED_PP[385]), .SAVE (INT_SUM[398]), .CARRY (INT_CARRY[324]) ); smffa dla459 (.D(SUMMAND[386]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[386]) ); smffa dla460 (.D(SUMMAND[387]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[387]) ); smffa dla461 (.D(SUMMAND[388]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[388]) ); smfulladder dfa291 (.DATA_A (LATCHED_PP[386]), .DATA_B (LATCHED_PP[387]), .DATA_C (LATCHED_PP[388]), .SAVE (INT_SUM[399]), .CARRY (INT_CARRY[325]) ); smffa dla462 (.D(SUMMAND[389]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[389]) ); assign INT_SUM[400] = LATCHED_PP[389]; smfulladder dfa292 (.DATA_A (INT_SUM[395]), .DATA_B (INT_SUM[396]), .DATA_C (INT_SUM[397]), .SAVE (INT_SUM[401]), .CARRY (INT_CARRY[326]) ); smfulladder dfa293 (.DATA_A (INT_SUM[398]), .DATA_B (INT_SUM[399]), .DATA_C (INT_SUM[400]), .SAVE (INT_SUM[402]), .CARRY (INT_CARRY[327]) ); smfulladder dfa294 (.DATA_A (INT_CARRY[306]), .DATA_B (INT_CARRY[307]), .DATA_C (INT_CARRY[308]), .SAVE (INT_SUM[403]), .CARRY (INT_CARRY[328]) ); assign INT_SUM[404] = INT_CARRY[309]; assign INT_SUM[405] = INT_CARRY[310]; smfulladder dfa295 (.DATA_A (INT_SUM[401]), .DATA_B (INT_SUM[402]), .DATA_C (INT_SUM[403]), .SAVE (INT_SUM[406]), .CARRY (INT_CARRY[329]) ); smfulladder dfa296 (.DATA_A (INT_SUM[404]), .DATA_B (INT_SUM[405]), .DATA_C (INT_CARRY[311]), .SAVE (INT_SUM[407]), .CARRY (INT_CARRY[330]) ); smfulladder dfa297 (.DATA_A (INT_CARRY[312]), .DATA_B (INT_CARRY[313]), .DATA_C (INT_CARRY[314]), .SAVE (INT_SUM[408]), .CARRY (INT_CARRY[331]) ); smfulladder dfa298 (.DATA_A (INT_SUM[406]), .DATA_B (INT_SUM[407]), .DATA_C (INT_SUM[408]), .SAVE (INT_SUM[409]), .CARRY (INT_CARRY[332]) ); smhalfadder dha33 (.DATA_A (INT_CARRY[315]), .DATA_B (INT_CARRY[316]), .SAVE (INT_SUM[410]), .CARRY (INT_CARRY[333]) ); smfulladder dfa299 (.DATA_A (INT_SUM[409]), .DATA_B (INT_SUM[410]), .DATA_C (INT_CARRY[317]), .SAVE (INT_SUM[411]), .CARRY (INT_CARRY[334]) ); assign INT_SUM[412] = INT_CARRY[318]; smfulladder dfa300 (.DATA_A (INT_SUM[411]), .DATA_B (INT_SUM[412]), .DATA_C (INT_CARRY[319]), .SAVE (INT_SUM[413]), .CARRY (INT_CARRY[320]) ); smffb dla463 (.D(INT_SUM[413]), .clk(clk), .en_d2(en_d2), .Q(SUM[37]) ); smffb dla464 (.D(INT_CARRY[320]), .clk(clk), .en_d2(en_d2), .Q(CARRY[37]) ); smffa dla465 (.D(SUMMAND[390]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[390]) ); smffa dla466 (.D(SUMMAND[391]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[391]) ); smffa dla467 (.D(SUMMAND[392]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[392]) ); smfulladder dfa301 (.DATA_A (LATCHED_PP[390]), .DATA_B (LATCHED_PP[391]), .DATA_C (LATCHED_PP[392]), .SAVE (INT_SUM[414]), .CARRY (INT_CARRY[336]) ); smffa dla468 (.D(SUMMAND[393]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[393]) ); smffa dla469 (.D(SUMMAND[394]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[394]) ); smffa dla470 (.D(SUMMAND[395]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[395]) ); smfulladder dfa302 (.DATA_A (LATCHED_PP[393]), .DATA_B (LATCHED_PP[394]), .DATA_C (LATCHED_PP[395]), .SAVE (INT_SUM[415]), .CARRY (INT_CARRY[337]) ); smffa dla471 (.D(SUMMAND[396]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[396]) ); smffa dla472 (.D(SUMMAND[397]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[397]) ); smffa dla473 (.D(SUMMAND[398]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[398]) ); smfulladder dfa303 (.DATA_A (LATCHED_PP[396]), .DATA_B (LATCHED_PP[397]), .DATA_C (LATCHED_PP[398]), .SAVE (INT_SUM[416]), .CARRY (INT_CARRY[338]) ); smffa dla474 (.D(SUMMAND[399]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[399]) ); smffa dla475 (.D(SUMMAND[400]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[400]) ); smffa dla476 (.D(SUMMAND[401]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[401]) ); smfulladder dfa304 (.DATA_A (LATCHED_PP[399]), .DATA_B (LATCHED_PP[400]), .DATA_C (LATCHED_PP[401]), .SAVE (INT_SUM[417]), .CARRY (INT_CARRY[339]) ); smffa dla477 (.D(SUMMAND[402]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[402]) ); smffa dla478 (.D(SUMMAND[403]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[403]) ); smffa dla479 (.D(SUMMAND[404]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[404]) ); smfulladder dfa305 (.DATA_A (LATCHED_PP[402]), .DATA_B (LATCHED_PP[403]), .DATA_C (LATCHED_PP[404]), .SAVE (INT_SUM[418]), .CARRY (INT_CARRY[340]) ); smfulladder dfa306 (.DATA_A (INT_SUM[414]), .DATA_B (INT_SUM[415]), .DATA_C (INT_SUM[416]), .SAVE (INT_SUM[419]), .CARRY (INT_CARRY[341]) ); smfulladder dfa307 (.DATA_A (INT_SUM[417]), .DATA_B (INT_SUM[418]), .DATA_C (INT_CARRY[321]), .SAVE (INT_SUM[420]), .CARRY (INT_CARRY[342]) ); smfulladder dfa308 (.DATA_A (INT_CARRY[322]), .DATA_B (INT_CARRY[323]), .DATA_C (INT_CARRY[324]), .SAVE (INT_SUM[421]), .CARRY (INT_CARRY[343]) ); assign INT_SUM[422] = INT_CARRY[325]; smfulladder dfa309 (.DATA_A (INT_SUM[419]), .DATA_B (INT_SUM[420]), .DATA_C (INT_SUM[421]), .SAVE (INT_SUM[423]), .CARRY (INT_CARRY[344]) ); smfulladder dfa310 (.DATA_A (INT_SUM[422]), .DATA_B (INT_CARRY[326]), .DATA_C (INT_CARRY[327]), .SAVE (INT_SUM[424]), .CARRY (INT_CARRY[345]) ); assign INT_SUM[425] = INT_CARRY[328]; smfulladder dfa311 (.DATA_A (INT_SUM[423]), .DATA_B (INT_SUM[424]), .DATA_C (INT_SUM[425]), .SAVE (INT_SUM[426]), .CARRY (INT_CARRY[346]) ); smfulladder dfa312 (.DATA_A (INT_CARRY[329]), .DATA_B (INT_CARRY[330]), .DATA_C (INT_CARRY[331]), .SAVE (INT_SUM[427]), .CARRY (INT_CARRY[347]) ); smfulladder dfa313 (.DATA_A (INT_SUM[426]), .DATA_B (INT_SUM[427]), .DATA_C (INT_CARRY[332]), .SAVE (INT_SUM[428]), .CARRY (INT_CARRY[348]) ); assign INT_SUM[429] = INT_CARRY[333]; smfulladder dfa314 (.DATA_A (INT_SUM[428]), .DATA_B (INT_SUM[429]), .DATA_C (INT_CARRY[334]), .SAVE (INT_SUM[430]), .CARRY (INT_CARRY[335]) ); smffb dla480 (.D(INT_SUM[430]), .clk(clk), .en_d2(en_d2), .Q(SUM[38]) ); smffb dla481 (.D(INT_CARRY[335]), .clk(clk), .en_d2(en_d2), .Q(CARRY[38]) ); smffa dla482 (.D(SUMMAND[405]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[405]) ); smffa dla483 (.D(SUMMAND[406]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[406]) ); smffa dla484 (.D(SUMMAND[407]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[407]) ); smfulladder dfa315 (.DATA_A (LATCHED_PP[405]), .DATA_B (LATCHED_PP[406]), .DATA_C (LATCHED_PP[407]), .SAVE (INT_SUM[431]), .CARRY (INT_CARRY[350]) ); smffa dla485 (.D(SUMMAND[408]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[408]) ); smffa dla486 (.D(SUMMAND[409]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[409]) ); smffa dla487 (.D(SUMMAND[410]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[410]) ); smfulladder dfa316 (.DATA_A (LATCHED_PP[408]), .DATA_B (LATCHED_PP[409]), .DATA_C (LATCHED_PP[410]), .SAVE (INT_SUM[432]), .CARRY (INT_CARRY[351]) ); smffa dla488 (.D(SUMMAND[411]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[411]) ); smffa dla489 (.D(SUMMAND[412]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[412]) ); smffa dla490 (.D(SUMMAND[413]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[413]) ); smfulladder dfa317 (.DATA_A (LATCHED_PP[411]), .DATA_B (LATCHED_PP[412]), .DATA_C (LATCHED_PP[413]), .SAVE (INT_SUM[433]), .CARRY (INT_CARRY[352]) ); smffa dla491 (.D(SUMMAND[414]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[414]) ); smffa dla492 (.D(SUMMAND[415]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[415]) ); smffa dla493 (.D(SUMMAND[416]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[416]) ); smfulladder dfa318 (.DATA_A (LATCHED_PP[414]), .DATA_B (LATCHED_PP[415]), .DATA_C (LATCHED_PP[416]), .SAVE (INT_SUM[434]), .CARRY (INT_CARRY[353]) ); smffa dla494 (.D(SUMMAND[417]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[417]) ); smffa dla495 (.D(SUMMAND[418]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[418]) ); smffa dla496 (.D(SUMMAND[419]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[419]) ); smfulladder dfa319 (.DATA_A (LATCHED_PP[417]), .DATA_B (LATCHED_PP[418]), .DATA_C (LATCHED_PP[419]), .SAVE (INT_SUM[435]), .CARRY (INT_CARRY[354]) ); smfulladder dfa320 (.DATA_A (INT_SUM[431]), .DATA_B (INT_SUM[432]), .DATA_C (INT_SUM[433]), .SAVE (INT_SUM[436]), .CARRY (INT_CARRY[355]) ); smfulladder dfa321 (.DATA_A (INT_SUM[434]), .DATA_B (INT_SUM[435]), .DATA_C (INT_CARRY[336]), .SAVE (INT_SUM[437]), .CARRY (INT_CARRY[356]) ); smfulladder dfa322 (.DATA_A (INT_CARRY[337]), .DATA_B (INT_CARRY[338]), .DATA_C (INT_CARRY[339]), .SAVE (INT_SUM[438]), .CARRY (INT_CARRY[357]) ); assign INT_SUM[439] = INT_CARRY[340]; smfulladder dfa323 (.DATA_A (INT_SUM[436]), .DATA_B (INT_SUM[437]), .DATA_C (INT_SUM[438]), .SAVE (INT_SUM[440]), .CARRY (INT_CARRY[358]) ); smfulladder dfa324 (.DATA_A (INT_SUM[439]), .DATA_B (INT_CARRY[341]), .DATA_C (INT_CARRY[342]), .SAVE (INT_SUM[441]), .CARRY (INT_CARRY[359]) ); assign INT_SUM[442] = INT_CARRY[343]; smfulladder dfa325 (.DATA_A (INT_SUM[440]), .DATA_B (INT_SUM[441]), .DATA_C (INT_SUM[442]), .SAVE (INT_SUM[443]), .CARRY (INT_CARRY[360]) ); smhalfadder dha34 (.DATA_A (INT_CARRY[344]), .DATA_B (INT_CARRY[345]), .SAVE (INT_SUM[444]), .CARRY (INT_CARRY[361]) ); smfulladder dfa326 (.DATA_A (INT_SUM[443]), .DATA_B (INT_SUM[444]), .DATA_C (INT_CARRY[346]), .SAVE (INT_SUM[445]), .CARRY (INT_CARRY[362]) ); assign INT_SUM[446] = INT_CARRY[347]; smfulladder dfa327 (.DATA_A (INT_SUM[445]), .DATA_B (INT_SUM[446]), .DATA_C (INT_CARRY[348]), .SAVE (INT_SUM[447]), .CARRY (INT_CARRY[349]) ); smffb dla497 (.D(INT_SUM[447]), .clk(clk), .en_d2(en_d2), .Q(SUM[39]) ); smffb dla498 (.D(INT_CARRY[349]), .clk(clk), .en_d2(en_d2), .Q(CARRY[39]) ); smffa dla499 (.D(SUMMAND[420]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[420]) ); smffa dla500 (.D(SUMMAND[421]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[421]) ); smffa dla501 (.D(SUMMAND[422]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[422]) ); smfulladder dfa328 (.DATA_A (LATCHED_PP[420]), .DATA_B (LATCHED_PP[421]), .DATA_C (LATCHED_PP[422]), .SAVE (INT_SUM[448]), .CARRY (INT_CARRY[364]) ); smffa dla502 (.D(SUMMAND[423]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[423]) ); smffa dla503 (.D(SUMMAND[424]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[424]) ); smffa dla504 (.D(SUMMAND[425]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[425]) ); smfulladder dfa329 (.DATA_A (LATCHED_PP[423]), .DATA_B (LATCHED_PP[424]), .DATA_C (LATCHED_PP[425]), .SAVE (INT_SUM[449]), .CARRY (INT_CARRY[365]) ); smffa dla505 (.D(SUMMAND[426]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[426]) ); smffa dla506 (.D(SUMMAND[427]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[427]) ); smffa dla507 (.D(SUMMAND[428]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[428]) ); smfulladder dfa330 (.DATA_A (LATCHED_PP[426]), .DATA_B (LATCHED_PP[427]), .DATA_C (LATCHED_PP[428]), .SAVE (INT_SUM[450]), .CARRY (INT_CARRY[366]) ); smffa dla508 (.D(SUMMAND[429]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[429]) ); smffa dla509 (.D(SUMMAND[430]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[430]) ); smffa dla510 (.D(SUMMAND[431]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[431]) ); smfulladder dfa331 (.DATA_A (LATCHED_PP[429]), .DATA_B (LATCHED_PP[430]), .DATA_C (LATCHED_PP[431]), .SAVE (INT_SUM[451]), .CARRY (INT_CARRY[367]) ); smffa dla511 (.D(SUMMAND[432]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[432]) ); smffa dla512 (.D(SUMMAND[433]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[433]) ); smhalfadder dha35 (.DATA_A (LATCHED_PP[432]), .DATA_B (LATCHED_PP[433]), .SAVE (INT_SUM[452]), .CARRY (INT_CARRY[368]) ); smfulladder dfa332 (.DATA_A (INT_SUM[448]), .DATA_B (INT_SUM[449]), .DATA_C (INT_SUM[450]), .SAVE (INT_SUM[453]), .CARRY (INT_CARRY[369]) ); smfulladder dfa333 (.DATA_A (INT_SUM[451]), .DATA_B (INT_SUM[452]), .DATA_C (INT_CARRY[350]), .SAVE (INT_SUM[454]), .CARRY (INT_CARRY[370]) ); smfulladder dfa334 (.DATA_A (INT_CARRY[351]), .DATA_B (INT_CARRY[352]), .DATA_C (INT_CARRY[353]), .SAVE (INT_SUM[455]), .CARRY (INT_CARRY[371]) ); assign INT_SUM[456] = INT_CARRY[354]; smfulladder dfa335 (.DATA_A (INT_SUM[453]), .DATA_B (INT_SUM[454]), .DATA_C (INT_SUM[455]), .SAVE (INT_SUM[457]), .CARRY (INT_CARRY[372]) ); smfulladder dfa336 (.DATA_A (INT_SUM[456]), .DATA_B (INT_CARRY[355]), .DATA_C (INT_CARRY[356]), .SAVE (INT_SUM[458]), .CARRY (INT_CARRY[373]) ); assign INT_SUM[459] = INT_CARRY[357]; smfulladder dfa337 (.DATA_A (INT_SUM[457]), .DATA_B (INT_SUM[458]), .DATA_C (INT_SUM[459]), .SAVE (INT_SUM[460]), .CARRY (INT_CARRY[374]) ); smhalfadder dha36 (.DATA_A (INT_CARRY[358]), .DATA_B (INT_CARRY[359]), .SAVE (INT_SUM[461]), .CARRY (INT_CARRY[375]) ); smfulladder dfa338 (.DATA_A (INT_SUM[460]), .DATA_B (INT_SUM[461]), .DATA_C (INT_CARRY[360]), .SAVE (INT_SUM[462]), .CARRY (INT_CARRY[376]) ); assign INT_SUM[463] = INT_CARRY[361]; smfulladder dfa339 (.DATA_A (INT_SUM[462]), .DATA_B (INT_SUM[463]), .DATA_C (INT_CARRY[362]), .SAVE (INT_SUM[464]), .CARRY (INT_CARRY[363]) ); smffb dla513 (.D(INT_SUM[464]), .clk(clk), .en_d2(en_d2), .Q(SUM[40]) ); smffb dla514 (.D(INT_CARRY[363]), .clk(clk), .en_d2(en_d2), .Q(CARRY[40]) ); smffa dla515 (.D(SUMMAND[434]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[434]) ); smffa dla516 (.D(SUMMAND[435]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[435]) ); smffa dla517 (.D(SUMMAND[436]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[436]) ); smfulladder dfa340 (.DATA_A (LATCHED_PP[434]), .DATA_B (LATCHED_PP[435]), .DATA_C (LATCHED_PP[436]), .SAVE (INT_SUM[465]), .CARRY (INT_CARRY[378]) ); smffa dla518 (.D(SUMMAND[437]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[437]) ); smffa dla519 (.D(SUMMAND[438]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[438]) ); smffa dla520 (.D(SUMMAND[439]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[439]) ); smfulladder dfa341 (.DATA_A (LATCHED_PP[437]), .DATA_B (LATCHED_PP[438]), .DATA_C (LATCHED_PP[439]), .SAVE (INT_SUM[466]), .CARRY (INT_CARRY[379]) ); smffa dla521 (.D(SUMMAND[440]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[440]) ); smffa dla522 (.D(SUMMAND[441]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[441]) ); smffa dla523 (.D(SUMMAND[442]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[442]) ); smfulladder dfa342 (.DATA_A (LATCHED_PP[440]), .DATA_B (LATCHED_PP[441]), .DATA_C (LATCHED_PP[442]), .SAVE (INT_SUM[467]), .CARRY (INT_CARRY[380]) ); smffa dla524 (.D(SUMMAND[443]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[443]) ); smffa dla525 (.D(SUMMAND[444]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[444]) ); smffa dla526 (.D(SUMMAND[445]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[445]) ); smfulladder dfa343 (.DATA_A (LATCHED_PP[443]), .DATA_B (LATCHED_PP[444]), .DATA_C (LATCHED_PP[445]), .SAVE (INT_SUM[468]), .CARRY (INT_CARRY[381]) ); smffa dla527 (.D(SUMMAND[446]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[446]) ); smffa dla528 (.D(SUMMAND[447]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[447]) ); smhalfadder dha37 (.DATA_A (LATCHED_PP[446]), .DATA_B (LATCHED_PP[447]), .SAVE (INT_SUM[469]), .CARRY (INT_CARRY[382]) ); smfulladder dfa344 (.DATA_A (INT_SUM[465]), .DATA_B (INT_SUM[466]), .DATA_C (INT_SUM[467]), .SAVE (INT_SUM[470]), .CARRY (INT_CARRY[383]) ); smfulladder dfa345 (.DATA_A (INT_SUM[468]), .DATA_B (INT_SUM[469]), .DATA_C (INT_CARRY[364]), .SAVE (INT_SUM[471]), .CARRY (INT_CARRY[384]) ); smfulladder dfa346 (.DATA_A (INT_CARRY[365]), .DATA_B (INT_CARRY[366]), .DATA_C (INT_CARRY[367]), .SAVE (INT_SUM[472]), .CARRY (INT_CARRY[385]) ); assign INT_SUM[473] = INT_CARRY[368]; smfulladder dfa347 (.DATA_A (INT_SUM[470]), .DATA_B (INT_SUM[471]), .DATA_C (INT_SUM[472]), .SAVE (INT_SUM[474]), .CARRY (INT_CARRY[386]) ); smfulladder dfa348 (.DATA_A (INT_SUM[473]), .DATA_B (INT_CARRY[369]), .DATA_C (INT_CARRY[370]), .SAVE (INT_SUM[475]), .CARRY (INT_CARRY[387]) ); assign INT_SUM[476] = INT_CARRY[371]; smfulladder dfa349 (.DATA_A (INT_SUM[474]), .DATA_B (INT_SUM[475]), .DATA_C (INT_SUM[476]), .SAVE (INT_SUM[477]), .CARRY (INT_CARRY[388]) ); smhalfadder dha38 (.DATA_A (INT_CARRY[372]), .DATA_B (INT_CARRY[373]), .SAVE (INT_SUM[478]), .CARRY (INT_CARRY[389]) ); smfulladder dfa350 (.DATA_A (INT_SUM[477]), .DATA_B (INT_SUM[478]), .DATA_C (INT_CARRY[374]), .SAVE (INT_SUM[479]), .CARRY (INT_CARRY[390]) ); assign INT_SUM[480] = INT_CARRY[375]; smfulladder dfa351 (.DATA_A (INT_SUM[479]), .DATA_B (INT_SUM[480]), .DATA_C (INT_CARRY[376]), .SAVE (INT_SUM[481]), .CARRY (INT_CARRY[377]) ); smffb dla529 (.D(INT_SUM[481]), .clk(clk), .en_d2(en_d2), .Q(SUM[41]) ); smffb dla530 (.D(INT_CARRY[377]), .clk(clk), .en_d2(en_d2), .Q(CARRY[41]) ); smffa dla531 (.D(SUMMAND[448]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[448]) ); smffa dla532 (.D(SUMMAND[449]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[449]) ); smffa dla533 (.D(SUMMAND[450]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[450]) ); smfulladder dfa352 (.DATA_A (LATCHED_PP[448]), .DATA_B (LATCHED_PP[449]), .DATA_C (LATCHED_PP[450]), .SAVE (INT_SUM[482]), .CARRY (INT_CARRY[392]) ); smffa dla534 (.D(SUMMAND[451]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[451]) ); smffa dla535 (.D(SUMMAND[452]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[452]) ); smffa dla536 (.D(SUMMAND[453]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[453]) ); smfulladder dfa353 (.DATA_A (LATCHED_PP[451]), .DATA_B (LATCHED_PP[452]), .DATA_C (LATCHED_PP[453]), .SAVE (INT_SUM[483]), .CARRY (INT_CARRY[393]) ); smffa dla537 (.D(SUMMAND[454]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[454]) ); smffa dla538 (.D(SUMMAND[455]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[455]) ); smffa dla539 (.D(SUMMAND[456]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[456]) ); smfulladder dfa354 (.DATA_A (LATCHED_PP[454]), .DATA_B (LATCHED_PP[455]), .DATA_C (LATCHED_PP[456]), .SAVE (INT_SUM[484]), .CARRY (INT_CARRY[394]) ); smffa dla540 (.D(SUMMAND[457]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[457]) ); smffa dla541 (.D(SUMMAND[458]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[458]) ); smffa dla542 (.D(SUMMAND[459]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[459]) ); smfulladder dfa355 (.DATA_A (LATCHED_PP[457]), .DATA_B (LATCHED_PP[458]), .DATA_C (LATCHED_PP[459]), .SAVE (INT_SUM[485]), .CARRY (INT_CARRY[395]) ); smffa dla543 (.D(SUMMAND[460]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[460]) ); assign INT_SUM[486] = LATCHED_PP[460]; smfulladder dfa356 (.DATA_A (INT_SUM[482]), .DATA_B (INT_SUM[483]), .DATA_C (INT_SUM[484]), .SAVE (INT_SUM[487]), .CARRY (INT_CARRY[396]) ); smfulladder dfa357 (.DATA_A (INT_SUM[485]), .DATA_B (INT_SUM[486]), .DATA_C (INT_CARRY[378]), .SAVE (INT_SUM[488]), .CARRY (INT_CARRY[397]) ); smfulladder dfa358 (.DATA_A (INT_CARRY[379]), .DATA_B (INT_CARRY[380]), .DATA_C (INT_CARRY[381]), .SAVE (INT_SUM[489]), .CARRY (INT_CARRY[398]) ); assign INT_SUM[490] = INT_CARRY[382]; smfulladder dfa359 (.DATA_A (INT_SUM[487]), .DATA_B (INT_SUM[488]), .DATA_C (INT_SUM[489]), .SAVE (INT_SUM[491]), .CARRY (INT_CARRY[399]) ); smfulladder dfa360 (.DATA_A (INT_SUM[490]), .DATA_B (INT_CARRY[383]), .DATA_C (INT_CARRY[384]), .SAVE (INT_SUM[492]), .CARRY (INT_CARRY[400]) ); assign INT_SUM[493] = INT_CARRY[385]; smfulladder dfa361 (.DATA_A (INT_SUM[491]), .DATA_B (INT_SUM[492]), .DATA_C (INT_SUM[493]), .SAVE (INT_SUM[494]), .CARRY (INT_CARRY[401]) ); smhalfadder dha39 (.DATA_A (INT_CARRY[386]), .DATA_B (INT_CARRY[387]), .SAVE (INT_SUM[495]), .CARRY (INT_CARRY[402]) ); smfulladder dfa362 (.DATA_A (INT_SUM[494]), .DATA_B (INT_SUM[495]), .DATA_C (INT_CARRY[388]), .SAVE (INT_SUM[496]), .CARRY (INT_CARRY[403]) ); assign INT_SUM[497] = INT_CARRY[389]; smfulladder dfa363 (.DATA_A (INT_SUM[496]), .DATA_B (INT_SUM[497]), .DATA_C (INT_CARRY[390]), .SAVE (INT_SUM[498]), .CARRY (INT_CARRY[391]) ); smffb dla544 (.D(INT_SUM[498]), .clk(clk), .en_d2(en_d2), .Q(SUM[42]) ); smffb dla545 (.D(INT_CARRY[391]), .clk(clk), .en_d2(en_d2), .Q(CARRY[42]) ); smffa dla546 (.D(SUMMAND[461]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[461]) ); smffa dla547 (.D(SUMMAND[462]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[462]) ); smffa dla548 (.D(SUMMAND[463]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[463]) ); smfulladder dfa364 (.DATA_A (LATCHED_PP[461]), .DATA_B (LATCHED_PP[462]), .DATA_C (LATCHED_PP[463]), .SAVE (INT_SUM[499]), .CARRY (INT_CARRY[405]) ); smffa dla549 (.D(SUMMAND[464]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[464]) ); smffa dla550 (.D(SUMMAND[465]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[465]) ); smffa dla551 (.D(SUMMAND[466]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[466]) ); smfulladder dfa365 (.DATA_A (LATCHED_PP[464]), .DATA_B (LATCHED_PP[465]), .DATA_C (LATCHED_PP[466]), .SAVE (INT_SUM[500]), .CARRY (INT_CARRY[406]) ); smffa dla552 (.D(SUMMAND[467]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[467]) ); smffa dla553 (.D(SUMMAND[468]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[468]) ); smffa dla554 (.D(SUMMAND[469]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[469]) ); smfulladder dfa366 (.DATA_A (LATCHED_PP[467]), .DATA_B (LATCHED_PP[468]), .DATA_C (LATCHED_PP[469]), .SAVE (INT_SUM[501]), .CARRY (INT_CARRY[407]) ); smffa dla555 (.D(SUMMAND[470]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[470]) ); smffa dla556 (.D(SUMMAND[471]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[471]) ); smffa dla557 (.D(SUMMAND[472]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[472]) ); smfulladder dfa367 (.DATA_A (LATCHED_PP[470]), .DATA_B (LATCHED_PP[471]), .DATA_C (LATCHED_PP[472]), .SAVE (INT_SUM[502]), .CARRY (INT_CARRY[408]) ); smffa dla558 (.D(SUMMAND[473]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[473]) ); smfulladder dfa368 (.DATA_A (LATCHED_PP[473]), .DATA_B (INT_CARRY[392]), .DATA_C (INT_CARRY[393]), .SAVE (INT_SUM[503]), .CARRY (INT_CARRY[409]) ); assign INT_SUM[504] = INT_CARRY[394]; assign INT_SUM[505] = INT_CARRY[395]; smfulladder dfa369 (.DATA_A (INT_SUM[499]), .DATA_B (INT_SUM[500]), .DATA_C (INT_SUM[501]), .SAVE (INT_SUM[506]), .CARRY (INT_CARRY[410]) ); smfulladder dfa370 (.DATA_A (INT_SUM[502]), .DATA_B (INT_SUM[503]), .DATA_C (INT_SUM[504]), .SAVE (INT_SUM[507]), .CARRY (INT_CARRY[411]) ); smfulladder dfa371 (.DATA_A (INT_SUM[505]), .DATA_B (INT_CARRY[396]), .DATA_C (INT_CARRY[397]), .SAVE (INT_SUM[508]), .CARRY (INT_CARRY[412]) ); assign INT_SUM[509] = INT_CARRY[398]; smfulladder dfa372 (.DATA_A (INT_SUM[506]), .DATA_B (INT_SUM[507]), .DATA_C (INT_SUM[508]), .SAVE (INT_SUM[510]), .CARRY (INT_CARRY[413]) ); smfulladder dfa373 (.DATA_A (INT_SUM[509]), .DATA_B (INT_CARRY[399]), .DATA_C (INT_CARRY[400]), .SAVE (INT_SUM[511]), .CARRY (INT_CARRY[414]) ); smfulladder dfa374 (.DATA_A (INT_SUM[510]), .DATA_B (INT_SUM[511]), .DATA_C (INT_CARRY[401]), .SAVE (INT_SUM[512]), .CARRY (INT_CARRY[415]) ); assign INT_SUM[513] = INT_CARRY[402]; smfulladder dfa375 (.DATA_A (INT_SUM[512]), .DATA_B (INT_SUM[513]), .DATA_C (INT_CARRY[403]), .SAVE (INT_SUM[514]), .CARRY (INT_CARRY[404]) ); smffb dla559 (.D(INT_SUM[514]), .clk(clk), .en_d2(en_d2), .Q(SUM[43]) ); smffb dla560 (.D(INT_CARRY[404]), .clk(clk), .en_d2(en_d2), .Q(CARRY[43]) ); smffa dla561 (.D(SUMMAND[474]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[474]) ); smffa dla562 (.D(SUMMAND[475]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[475]) ); smffa dla563 (.D(SUMMAND[476]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[476]) ); smfulladder dfa376 (.DATA_A (LATCHED_PP[474]), .DATA_B (LATCHED_PP[475]), .DATA_C (LATCHED_PP[476]), .SAVE (INT_SUM[515]), .CARRY (INT_CARRY[417]) ); smffa dla564 (.D(SUMMAND[477]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[477]) ); smffa dla565 (.D(SUMMAND[478]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[478]) ); smffa dla566 (.D(SUMMAND[479]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[479]) ); smfulladder dfa377 (.DATA_A (LATCHED_PP[477]), .DATA_B (LATCHED_PP[478]), .DATA_C (LATCHED_PP[479]), .SAVE (INT_SUM[516]), .CARRY (INT_CARRY[418]) ); smffa dla567 (.D(SUMMAND[480]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[480]) ); smffa dla568 (.D(SUMMAND[481]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[481]) ); smffa dla569 (.D(SUMMAND[482]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[482]) ); smfulladder dfa378 (.DATA_A (LATCHED_PP[480]), .DATA_B (LATCHED_PP[481]), .DATA_C (LATCHED_PP[482]), .SAVE (INT_SUM[517]), .CARRY (INT_CARRY[419]) ); smffa dla570 (.D(SUMMAND[483]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[483]) ); smffa dla571 (.D(SUMMAND[484]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[484]) ); smffa dla572 (.D(SUMMAND[485]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[485]) ); smfulladder dfa379 (.DATA_A (LATCHED_PP[483]), .DATA_B (LATCHED_PP[484]), .DATA_C (LATCHED_PP[485]), .SAVE (INT_SUM[518]), .CARRY (INT_CARRY[420]) ); smfulladder dfa380 (.DATA_A (INT_SUM[515]), .DATA_B (INT_SUM[516]), .DATA_C (INT_SUM[517]), .SAVE (INT_SUM[519]), .CARRY (INT_CARRY[421]) ); smfulladder dfa381 (.DATA_A (INT_SUM[518]), .DATA_B (INT_CARRY[405]), .DATA_C (INT_CARRY[406]), .SAVE (INT_SUM[520]), .CARRY (INT_CARRY[422]) ); smfulladder dfa382 (.DATA_A (INT_CARRY[407]), .DATA_B (INT_CARRY[408]), .DATA_C (INT_CARRY[409]), .SAVE (INT_SUM[521]), .CARRY (INT_CARRY[423]) ); smfulladder dfa383 (.DATA_A (INT_SUM[519]), .DATA_B (INT_SUM[520]), .DATA_C (INT_SUM[521]), .SAVE (INT_SUM[522]), .CARRY (INT_CARRY[424]) ); smfulladder dfa384 (.DATA_A (INT_CARRY[410]), .DATA_B (INT_CARRY[411]), .DATA_C (INT_CARRY[412]), .SAVE (INT_SUM[523]), .CARRY (INT_CARRY[425]) ); smfulladder dfa385 (.DATA_A (INT_SUM[522]), .DATA_B (INT_SUM[523]), .DATA_C (INT_CARRY[413]), .SAVE (INT_SUM[524]), .CARRY (INT_CARRY[426]) ); assign INT_SUM[525] = INT_CARRY[414]; smfulladder dfa386 (.DATA_A (INT_SUM[524]), .DATA_B (INT_SUM[525]), .DATA_C (INT_CARRY[415]), .SAVE (INT_SUM[526]), .CARRY (INT_CARRY[416]) ); smffb dla573 (.D(INT_SUM[526]), .clk(clk), .en_d2(en_d2), .Q(SUM[44]) ); smffb dla574 (.D(INT_CARRY[416]), .clk(clk), .en_d2(en_d2), .Q(CARRY[44]) ); smffa dla575 (.D(SUMMAND[486]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[486]) ); smffa dla576 (.D(SUMMAND[487]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[487]) ); smffa dla577 (.D(SUMMAND[488]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[488]) ); smfulladder dfa387 (.DATA_A (LATCHED_PP[486]), .DATA_B (LATCHED_PP[487]), .DATA_C (LATCHED_PP[488]), .SAVE (INT_SUM[527]), .CARRY (INT_CARRY[428]) ); smffa dla578 (.D(SUMMAND[489]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[489]) ); smffa dla579 (.D(SUMMAND[490]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[490]) ); smffa dla580 (.D(SUMMAND[491]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[491]) ); smfulladder dfa388 (.DATA_A (LATCHED_PP[489]), .DATA_B (LATCHED_PP[490]), .DATA_C (LATCHED_PP[491]), .SAVE (INT_SUM[528]), .CARRY (INT_CARRY[429]) ); smffa dla581 (.D(SUMMAND[492]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[492]) ); smffa dla582 (.D(SUMMAND[493]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[493]) ); smffa dla583 (.D(SUMMAND[494]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[494]) ); smfulladder dfa389 (.DATA_A (LATCHED_PP[492]), .DATA_B (LATCHED_PP[493]), .DATA_C (LATCHED_PP[494]), .SAVE (INT_SUM[529]), .CARRY (INT_CARRY[430]) ); smffa dla584 (.D(SUMMAND[495]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[495]) ); smffa dla585 (.D(SUMMAND[496]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[496]) ); smffa dla586 (.D(SUMMAND[497]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[497]) ); smfulladder dfa390 (.DATA_A (LATCHED_PP[495]), .DATA_B (LATCHED_PP[496]), .DATA_C (LATCHED_PP[497]), .SAVE (INT_SUM[530]), .CARRY (INT_CARRY[431]) ); smfulladder dfa391 (.DATA_A (INT_SUM[527]), .DATA_B (INT_SUM[528]), .DATA_C (INT_SUM[529]), .SAVE (INT_SUM[531]), .CARRY (INT_CARRY[432]) ); smfulladder dfa392 (.DATA_A (INT_SUM[530]), .DATA_B (INT_CARRY[417]), .DATA_C (INT_CARRY[418]), .SAVE (INT_SUM[532]), .CARRY (INT_CARRY[433]) ); smhalfadder dha40 (.DATA_A (INT_CARRY[419]), .DATA_B (INT_CARRY[420]), .SAVE (INT_SUM[533]), .CARRY (INT_CARRY[434]) ); smfulladder dfa393 (.DATA_A (INT_SUM[531]), .DATA_B (INT_SUM[532]), .DATA_C (INT_SUM[533]), .SAVE (INT_SUM[534]), .CARRY (INT_CARRY[435]) ); smfulladder dfa394 (.DATA_A (INT_CARRY[421]), .DATA_B (INT_CARRY[422]), .DATA_C (INT_CARRY[423]), .SAVE (INT_SUM[535]), .CARRY (INT_CARRY[436]) ); smfulladder dfa395 (.DATA_A (INT_SUM[534]), .DATA_B (INT_SUM[535]), .DATA_C (INT_CARRY[424]), .SAVE (INT_SUM[536]), .CARRY (INT_CARRY[437]) ); assign INT_SUM[537] = INT_CARRY[425]; smfulladder dfa396 (.DATA_A (INT_SUM[536]), .DATA_B (INT_SUM[537]), .DATA_C (INT_CARRY[426]), .SAVE (INT_SUM[538]), .CARRY (INT_CARRY[427]) ); smffb dla587 (.D(INT_SUM[538]), .clk(clk), .en_d2(en_d2), .Q(SUM[45]) ); smffb dla588 (.D(INT_CARRY[427]), .clk(clk), .en_d2(en_d2), .Q(CARRY[45]) ); smffa dla589 (.D(SUMMAND[498]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[498]) ); smffa dla590 (.D(SUMMAND[499]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[499]) ); smffa dla591 (.D(SUMMAND[500]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[500]) ); smfulladder dfa397 (.DATA_A (LATCHED_PP[498]), .DATA_B (LATCHED_PP[499]), .DATA_C (LATCHED_PP[500]), .SAVE (INT_SUM[539]), .CARRY (INT_CARRY[439]) ); smffa dla592 (.D(SUMMAND[501]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[501]) ); smffa dla593 (.D(SUMMAND[502]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[502]) ); smffa dla594 (.D(SUMMAND[503]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[503]) ); smfulladder dfa398 (.DATA_A (LATCHED_PP[501]), .DATA_B (LATCHED_PP[502]), .DATA_C (LATCHED_PP[503]), .SAVE (INT_SUM[540]), .CARRY (INT_CARRY[440]) ); smffa dla595 (.D(SUMMAND[504]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[504]) ); smffa dla596 (.D(SUMMAND[505]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[505]) ); smffa dla597 (.D(SUMMAND[506]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[506]) ); smfulladder dfa399 (.DATA_A (LATCHED_PP[504]), .DATA_B (LATCHED_PP[505]), .DATA_C (LATCHED_PP[506]), .SAVE (INT_SUM[541]), .CARRY (INT_CARRY[441]) ); smffa dla598 (.D(SUMMAND[507]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[507]) ); assign INT_SUM[542] = LATCHED_PP[507]; smffa dla599 (.D(SUMMAND[508]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[508]) ); assign INT_SUM[543] = LATCHED_PP[508]; smfulladder dfa400 (.DATA_A (INT_SUM[539]), .DATA_B (INT_SUM[540]), .DATA_C (INT_SUM[541]), .SAVE (INT_SUM[544]), .CARRY (INT_CARRY[442]) ); smfulladder dfa401 (.DATA_A (INT_SUM[542]), .DATA_B (INT_SUM[543]), .DATA_C (INT_CARRY[428]), .SAVE (INT_SUM[545]), .CARRY (INT_CARRY[443]) ); smfulladder dfa402 (.DATA_A (INT_CARRY[429]), .DATA_B (INT_CARRY[430]), .DATA_C (INT_CARRY[431]), .SAVE (INT_SUM[546]), .CARRY (INT_CARRY[444]) ); smfulladder dfa403 (.DATA_A (INT_SUM[544]), .DATA_B (INT_SUM[545]), .DATA_C (INT_SUM[546]), .SAVE (INT_SUM[547]), .CARRY (INT_CARRY[445]) ); smfulladder dfa404 (.DATA_A (INT_CARRY[432]), .DATA_B (INT_CARRY[433]), .DATA_C (INT_CARRY[434]), .SAVE (INT_SUM[548]), .CARRY (INT_CARRY[446]) ); smfulladder dfa405 (.DATA_A (INT_SUM[547]), .DATA_B (INT_SUM[548]), .DATA_C (INT_CARRY[435]), .SAVE (INT_SUM[549]), .CARRY (INT_CARRY[447]) ); assign INT_SUM[550] = INT_CARRY[436]; smfulladder dfa406 (.DATA_A (INT_SUM[549]), .DATA_B (INT_SUM[550]), .DATA_C (INT_CARRY[437]), .SAVE (INT_SUM[551]), .CARRY (INT_CARRY[438]) ); smffb dla600 (.D(INT_SUM[551]), .clk(clk), .en_d2(en_d2), .Q(SUM[46]) ); smffb dla601 (.D(INT_CARRY[438]), .clk(clk), .en_d2(en_d2), .Q(CARRY[46]) ); smffa dla602 (.D(SUMMAND[509]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[509]) ); smffa dla603 (.D(SUMMAND[510]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[510]) ); smffa dla604 (.D(SUMMAND[511]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[511]) ); smfulladder dfa407 (.DATA_A (LATCHED_PP[509]), .DATA_B (LATCHED_PP[510]), .DATA_C (LATCHED_PP[511]), .SAVE (INT_SUM[552]), .CARRY (INT_CARRY[449]) ); smffa dla605 (.D(SUMMAND[512]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[512]) ); smffa dla606 (.D(SUMMAND[513]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[513]) ); smffa dla607 (.D(SUMMAND[514]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[514]) ); smfulladder dfa408 (.DATA_A (LATCHED_PP[512]), .DATA_B (LATCHED_PP[513]), .DATA_C (LATCHED_PP[514]), .SAVE (INT_SUM[553]), .CARRY (INT_CARRY[450]) ); smffa dla608 (.D(SUMMAND[515]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[515]) ); smffa dla609 (.D(SUMMAND[516]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[516]) ); smffa dla610 (.D(SUMMAND[517]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[517]) ); smfulladder dfa409 (.DATA_A (LATCHED_PP[515]), .DATA_B (LATCHED_PP[516]), .DATA_C (LATCHED_PP[517]), .SAVE (INT_SUM[554]), .CARRY (INT_CARRY[451]) ); smffa dla611 (.D(SUMMAND[518]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[518]) ); smffa dla612 (.D(SUMMAND[519]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[519]) ); smhalfadder dha41 (.DATA_A (LATCHED_PP[518]), .DATA_B (LATCHED_PP[519]), .SAVE (INT_SUM[555]), .CARRY (INT_CARRY[452]) ); smfulladder dfa410 (.DATA_A (INT_SUM[552]), .DATA_B (INT_SUM[553]), .DATA_C (INT_SUM[554]), .SAVE (INT_SUM[556]), .CARRY (INT_CARRY[453]) ); smfulladder dfa411 (.DATA_A (INT_SUM[555]), .DATA_B (INT_CARRY[439]), .DATA_C (INT_CARRY[440]), .SAVE (INT_SUM[557]), .CARRY (INT_CARRY[454]) ); assign INT_SUM[558] = INT_CARRY[441]; smfulladder dfa412 (.DATA_A (INT_SUM[556]), .DATA_B (INT_SUM[557]), .DATA_C (INT_SUM[558]), .SAVE (INT_SUM[559]), .CARRY (INT_CARRY[455]) ); smfulladder dfa413 (.DATA_A (INT_CARRY[442]), .DATA_B (INT_CARRY[443]), .DATA_C (INT_CARRY[444]), .SAVE (INT_SUM[560]), .CARRY (INT_CARRY[456]) ); smfulladder dfa414 (.DATA_A (INT_SUM[559]), .DATA_B (INT_SUM[560]), .DATA_C (INT_CARRY[445]), .SAVE (INT_SUM[561]), .CARRY (INT_CARRY[457]) ); assign INT_SUM[562] = INT_CARRY[446]; smfulladder dfa415 (.DATA_A (INT_SUM[561]), .DATA_B (INT_SUM[562]), .DATA_C (INT_CARRY[447]), .SAVE (INT_SUM[563]), .CARRY (INT_CARRY[448]) ); smffb dla613 (.D(INT_SUM[563]), .clk(clk), .en_d2(en_d2), .Q(SUM[47]) ); smffb dla614 (.D(INT_CARRY[448]), .clk(clk), .en_d2(en_d2), .Q(CARRY[47]) ); smffa dla615 (.D(SUMMAND[520]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[520]) ); smffa dla616 (.D(SUMMAND[521]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[521]) ); smffa dla617 (.D(SUMMAND[522]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[522]) ); smfulladder dfa416 (.DATA_A (LATCHED_PP[520]), .DATA_B (LATCHED_PP[521]), .DATA_C (LATCHED_PP[522]), .SAVE (INT_SUM[564]), .CARRY (INT_CARRY[459]) ); smffa dla618 (.D(SUMMAND[523]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[523]) ); smffa dla619 (.D(SUMMAND[524]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[524]) ); smffa dla620 (.D(SUMMAND[525]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[525]) ); smfulladder dfa417 (.DATA_A (LATCHED_PP[523]), .DATA_B (LATCHED_PP[524]), .DATA_C (LATCHED_PP[525]), .SAVE (INT_SUM[565]), .CARRY (INT_CARRY[460]) ); smffa dla621 (.D(SUMMAND[526]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[526]) ); smffa dla622 (.D(SUMMAND[527]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[527]) ); smffa dla623 (.D(SUMMAND[528]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[528]) ); smfulladder dfa418 (.DATA_A (LATCHED_PP[526]), .DATA_B (LATCHED_PP[527]), .DATA_C (LATCHED_PP[528]), .SAVE (INT_SUM[566]), .CARRY (INT_CARRY[461]) ); smffa dla624 (.D(SUMMAND[529]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[529]) ); assign INT_SUM[567] = LATCHED_PP[529]; smfulladder dfa419 (.DATA_A (INT_SUM[564]), .DATA_B (INT_SUM[565]), .DATA_C (INT_SUM[566]), .SAVE (INT_SUM[568]), .CARRY (INT_CARRY[462]) ); smfulladder dfa420 (.DATA_A (INT_SUM[567]), .DATA_B (INT_CARRY[449]), .DATA_C (INT_CARRY[450]), .SAVE (INT_SUM[569]), .CARRY (INT_CARRY[463]) ); assign INT_SUM[570] = INT_CARRY[451]; assign INT_SUM[571] = INT_CARRY[452]; smfulladder dfa421 (.DATA_A (INT_SUM[568]), .DATA_B (INT_SUM[569]), .DATA_C (INT_SUM[570]), .SAVE (INT_SUM[572]), .CARRY (INT_CARRY[464]) ); smfulladder dfa422 (.DATA_A (INT_SUM[571]), .DATA_B (INT_CARRY[453]), .DATA_C (INT_CARRY[454]), .SAVE (INT_SUM[573]), .CARRY (INT_CARRY[465]) ); smfulladder dfa423 (.DATA_A (INT_SUM[572]), .DATA_B (INT_SUM[573]), .DATA_C (INT_CARRY[455]), .SAVE (INT_SUM[574]), .CARRY (INT_CARRY[466]) ); assign INT_SUM[575] = INT_CARRY[456]; smfulladder dfa424 (.DATA_A (INT_SUM[574]), .DATA_B (INT_SUM[575]), .DATA_C (INT_CARRY[457]), .SAVE (INT_SUM[576]), .CARRY (INT_CARRY[458]) ); smffb dla625 (.D(INT_SUM[576]), .clk(clk), .en_d2(en_d2), .Q(SUM[48]) ); smffb dla626 (.D(INT_CARRY[458]), .clk(clk), .en_d2(en_d2), .Q(CARRY[48]) ); smffa dla627 (.D(SUMMAND[530]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[530]) ); smffa dla628 (.D(SUMMAND[531]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[531]) ); smffa dla629 (.D(SUMMAND[532]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[532]) ); smfulladder dfa425 (.DATA_A (LATCHED_PP[530]), .DATA_B (LATCHED_PP[531]), .DATA_C (LATCHED_PP[532]), .SAVE (INT_SUM[577]), .CARRY (INT_CARRY[468]) ); smffa dla630 (.D(SUMMAND[533]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[533]) ); smffa dla631 (.D(SUMMAND[534]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[534]) ); smffa dla632 (.D(SUMMAND[535]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[535]) ); smfulladder dfa426 (.DATA_A (LATCHED_PP[533]), .DATA_B (LATCHED_PP[534]), .DATA_C (LATCHED_PP[535]), .SAVE (INT_SUM[578]), .CARRY (INT_CARRY[469]) ); smffa dla633 (.D(SUMMAND[536]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[536]) ); smffa dla634 (.D(SUMMAND[537]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[537]) ); smffa dla635 (.D(SUMMAND[538]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[538]) ); smfulladder dfa427 (.DATA_A (LATCHED_PP[536]), .DATA_B (LATCHED_PP[537]), .DATA_C (LATCHED_PP[538]), .SAVE (INT_SUM[579]), .CARRY (INT_CARRY[470]) ); smffa dla636 (.D(SUMMAND[539]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[539]) ); assign INT_SUM[580] = LATCHED_PP[539]; smfulladder dfa428 (.DATA_A (INT_SUM[577]), .DATA_B (INT_SUM[578]), .DATA_C (INT_SUM[579]), .SAVE (INT_SUM[581]), .CARRY (INT_CARRY[471]) ); smfulladder dfa429 (.DATA_A (INT_SUM[580]), .DATA_B (INT_CARRY[459]), .DATA_C (INT_CARRY[460]), .SAVE (INT_SUM[582]), .CARRY (INT_CARRY[472]) ); assign INT_SUM[583] = INT_CARRY[461]; smfulladder dfa430 (.DATA_A (INT_SUM[581]), .DATA_B (INT_SUM[582]), .DATA_C (INT_SUM[583]), .SAVE (INT_SUM[584]), .CARRY (INT_CARRY[473]) ); smhalfadder dha42 (.DATA_A (INT_CARRY[462]), .DATA_B (INT_CARRY[463]), .SAVE (INT_SUM[585]), .CARRY (INT_CARRY[474]) ); smfulladder dfa431 (.DATA_A (INT_SUM[584]), .DATA_B (INT_SUM[585]), .DATA_C (INT_CARRY[464]), .SAVE (INT_SUM[586]), .CARRY (INT_CARRY[475]) ); assign INT_SUM[587] = INT_CARRY[465]; smfulladder dfa432 (.DATA_A (INT_SUM[586]), .DATA_B (INT_SUM[587]), .DATA_C (INT_CARRY[466]), .SAVE (INT_SUM[588]), .CARRY (INT_CARRY[467]) ); smffb dla637 (.D(INT_SUM[588]), .clk(clk), .en_d2(en_d2), .Q(SUM[49]) ); smffb dla638 (.D(INT_CARRY[467]), .clk(clk), .en_d2(en_d2), .Q(CARRY[49]) ); smffa dla639 (.D(SUMMAND[540]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[540]) ); smffa dla640 (.D(SUMMAND[541]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[541]) ); smffa dla641 (.D(SUMMAND[542]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[542]) ); smfulladder dfa433 (.DATA_A (LATCHED_PP[540]), .DATA_B (LATCHED_PP[541]), .DATA_C (LATCHED_PP[542]), .SAVE (INT_SUM[589]), .CARRY (INT_CARRY[477]) ); smffa dla642 (.D(SUMMAND[543]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[543]) ); smffa dla643 (.D(SUMMAND[544]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[544]) ); smffa dla644 (.D(SUMMAND[545]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[545]) ); smfulladder dfa434 (.DATA_A (LATCHED_PP[543]), .DATA_B (LATCHED_PP[544]), .DATA_C (LATCHED_PP[545]), .SAVE (INT_SUM[590]), .CARRY (INT_CARRY[478]) ); smffa dla645 (.D(SUMMAND[546]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[546]) ); smffa dla646 (.D(SUMMAND[547]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[547]) ); smffa dla647 (.D(SUMMAND[548]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[548]) ); smfulladder dfa435 (.DATA_A (LATCHED_PP[546]), .DATA_B (LATCHED_PP[547]), .DATA_C (LATCHED_PP[548]), .SAVE (INT_SUM[591]), .CARRY (INT_CARRY[479]) ); smfulladder dfa436 (.DATA_A (INT_SUM[589]), .DATA_B (INT_SUM[590]), .DATA_C (INT_SUM[591]), .SAVE (INT_SUM[592]), .CARRY (INT_CARRY[480]) ); smfulladder dfa437 (.DATA_A (INT_CARRY[468]), .DATA_B (INT_CARRY[469]), .DATA_C (INT_CARRY[470]), .SAVE (INT_SUM[593]), .CARRY (INT_CARRY[481]) ); smfulladder dfa438 (.DATA_A (INT_SUM[592]), .DATA_B (INT_SUM[593]), .DATA_C (INT_CARRY[471]), .SAVE (INT_SUM[594]), .CARRY (INT_CARRY[482]) ); assign INT_SUM[595] = INT_CARRY[472]; smfulladder dfa439 (.DATA_A (INT_SUM[594]), .DATA_B (INT_SUM[595]), .DATA_C (INT_CARRY[473]), .SAVE (INT_SUM[596]), .CARRY (INT_CARRY[483]) ); assign INT_SUM[597] = INT_CARRY[474]; smfulladder dfa440 (.DATA_A (INT_SUM[596]), .DATA_B (INT_SUM[597]), .DATA_C (INT_CARRY[475]), .SAVE (INT_SUM[598]), .CARRY (INT_CARRY[476]) ); smffb dla648 (.D(INT_SUM[598]), .clk(clk), .en_d2(en_d2), .Q(SUM[50]) ); smffb dla649 (.D(INT_CARRY[476]), .clk(clk), .en_d2(en_d2), .Q(CARRY[50]) ); smffa dla650 (.D(SUMMAND[549]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[549]) ); smffa dla651 (.D(SUMMAND[550]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[550]) ); smffa dla652 (.D(SUMMAND[551]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[551]) ); smfulladder dfa441 (.DATA_A (LATCHED_PP[549]), .DATA_B (LATCHED_PP[550]), .DATA_C (LATCHED_PP[551]), .SAVE (INT_SUM[599]), .CARRY (INT_CARRY[485]) ); smffa dla653 (.D(SUMMAND[552]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[552]) ); smffa dla654 (.D(SUMMAND[553]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[553]) ); smffa dla655 (.D(SUMMAND[554]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[554]) ); smfulladder dfa442 (.DATA_A (LATCHED_PP[552]), .DATA_B (LATCHED_PP[553]), .DATA_C (LATCHED_PP[554]), .SAVE (INT_SUM[600]), .CARRY (INT_CARRY[486]) ); smffa dla656 (.D(SUMMAND[555]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[555]) ); smffa dla657 (.D(SUMMAND[556]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[556]) ); smffa dla658 (.D(SUMMAND[557]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[557]) ); smfulladder dfa443 (.DATA_A (LATCHED_PP[555]), .DATA_B (LATCHED_PP[556]), .DATA_C (LATCHED_PP[557]), .SAVE (INT_SUM[601]), .CARRY (INT_CARRY[487]) ); smfulladder dfa444 (.DATA_A (INT_SUM[599]), .DATA_B (INT_SUM[600]), .DATA_C (INT_SUM[601]), .SAVE (INT_SUM[602]), .CARRY (INT_CARRY[488]) ); smfulladder dfa445 (.DATA_A (INT_CARRY[477]), .DATA_B (INT_CARRY[478]), .DATA_C (INT_CARRY[479]), .SAVE (INT_SUM[603]), .CARRY (INT_CARRY[489]) ); smfulladder dfa446 (.DATA_A (INT_SUM[602]), .DATA_B (INT_SUM[603]), .DATA_C (INT_CARRY[480]), .SAVE (INT_SUM[604]), .CARRY (INT_CARRY[490]) ); assign INT_SUM[605] = INT_CARRY[481]; smfulladder dfa447 (.DATA_A (INT_SUM[604]), .DATA_B (INT_SUM[605]), .DATA_C (INT_CARRY[482]), .SAVE (INT_SUM[606]), .CARRY (INT_CARRY[491]) ); smhalfadder dha43 (.DATA_A (INT_SUM[606]), .DATA_B (INT_CARRY[483]), .SAVE (INT_SUM[607]), .CARRY (INT_CARRY[484]) ); smffb dla659 (.D(INT_SUM[607]), .clk(clk), .en_d2(en_d2), .Q(SUM[51]) ); smffb dla660 (.D(INT_CARRY[484]), .clk(clk), .en_d2(en_d2), .Q(CARRY[51]) ); smffa dla661 (.D(SUMMAND[558]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[558]) ); smffa dla662 (.D(SUMMAND[559]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[559]) ); smffa dla663 (.D(SUMMAND[560]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[560]) ); smfulladder dfa448 (.DATA_A (LATCHED_PP[558]), .DATA_B (LATCHED_PP[559]), .DATA_C (LATCHED_PP[560]), .SAVE (INT_SUM[608]), .CARRY (INT_CARRY[493]) ); smffa dla664 (.D(SUMMAND[561]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[561]) ); smffa dla665 (.D(SUMMAND[562]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[562]) ); smffa dla666 (.D(SUMMAND[563]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[563]) ); smfulladder dfa449 (.DATA_A (LATCHED_PP[561]), .DATA_B (LATCHED_PP[562]), .DATA_C (LATCHED_PP[563]), .SAVE (INT_SUM[609]), .CARRY (INT_CARRY[494]) ); smffa dla667 (.D(SUMMAND[564]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[564]) ); smffa dla668 (.D(SUMMAND[565]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[565]) ); smfulladder dfa450 (.DATA_A (LATCHED_PP[564]), .DATA_B (LATCHED_PP[565]), .DATA_C (INT_CARRY[485]), .SAVE (INT_SUM[610]), .CARRY (INT_CARRY[495]) ); smhalfadder dha44 (.DATA_A (INT_CARRY[486]), .DATA_B (INT_CARRY[487]), .SAVE (INT_SUM[611]), .CARRY (INT_CARRY[496]) ); smfulladder dfa451 (.DATA_A (INT_SUM[608]), .DATA_B (INT_SUM[609]), .DATA_C (INT_SUM[610]), .SAVE (INT_SUM[612]), .CARRY (INT_CARRY[497]) ); smfulladder dfa452 (.DATA_A (INT_SUM[611]), .DATA_B (INT_CARRY[488]), .DATA_C (INT_CARRY[489]), .SAVE (INT_SUM[613]), .CARRY (INT_CARRY[498]) ); smfulladder dfa453 (.DATA_A (INT_SUM[612]), .DATA_B (INT_SUM[613]), .DATA_C (INT_CARRY[490]), .SAVE (INT_SUM[614]), .CARRY (INT_CARRY[499]) ); smhalfadder dha45 (.DATA_A (INT_SUM[614]), .DATA_B (INT_CARRY[491]), .SAVE (INT_SUM[615]), .CARRY (INT_CARRY[492]) ); smffb dla669 (.D(INT_SUM[615]), .clk(clk), .en_d2(en_d2), .Q(SUM[52]) ); smffb dla670 (.D(INT_CARRY[492]), .clk(clk), .en_d2(en_d2), .Q(CARRY[52]) ); smffa dla671 (.D(SUMMAND[566]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[566]) ); smffa dla672 (.D(SUMMAND[567]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[567]) ); smffa dla673 (.D(SUMMAND[568]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[568]) ); smfulladder dfa454 (.DATA_A (LATCHED_PP[566]), .DATA_B (LATCHED_PP[567]), .DATA_C (LATCHED_PP[568]), .SAVE (INT_SUM[616]), .CARRY (INT_CARRY[501]) ); smffa dla674 (.D(SUMMAND[569]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[569]) ); smffa dla675 (.D(SUMMAND[570]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[570]) ); smffa dla676 (.D(SUMMAND[571]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[571]) ); smfulladder dfa455 (.DATA_A (LATCHED_PP[569]), .DATA_B (LATCHED_PP[570]), .DATA_C (LATCHED_PP[571]), .SAVE (INT_SUM[617]), .CARRY (INT_CARRY[502]) ); smffa dla677 (.D(SUMMAND[572]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[572]) ); assign INT_SUM[618] = LATCHED_PP[572]; smffa dla678 (.D(SUMMAND[573]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[573]) ); assign INT_SUM[619] = LATCHED_PP[573]; smfulladder dfa456 (.DATA_A (INT_SUM[616]), .DATA_B (INT_SUM[617]), .DATA_C (INT_SUM[618]), .SAVE (INT_SUM[620]), .CARRY (INT_CARRY[503]) ); assign INT_SUM[621] = INT_SUM[619]; smfulladder dfa457 (.DATA_A (INT_SUM[620]), .DATA_B (INT_SUM[621]), .DATA_C (INT_CARRY[493]), .SAVE (INT_SUM[622]), .CARRY (INT_CARRY[504]) ); smfulladder dfa458 (.DATA_A (INT_CARRY[494]), .DATA_B (INT_CARRY[495]), .DATA_C (INT_CARRY[496]), .SAVE (INT_SUM[623]), .CARRY (INT_CARRY[505]) ); smfulladder dfa459 (.DATA_A (INT_SUM[622]), .DATA_B (INT_SUM[623]), .DATA_C (INT_CARRY[497]), .SAVE (INT_SUM[624]), .CARRY (INT_CARRY[506]) ); assign INT_SUM[625] = INT_CARRY[498]; smfulladder dfa460 (.DATA_A (INT_SUM[624]), .DATA_B (INT_SUM[625]), .DATA_C (INT_CARRY[499]), .SAVE (INT_SUM[626]), .CARRY (INT_CARRY[500]) ); smffb dla679 (.D(INT_SUM[626]), .clk(clk), .en_d2(en_d2), .Q(SUM[53]) ); smffb dla680 (.D(INT_CARRY[500]), .clk(clk), .en_d2(en_d2), .Q(CARRY[53]) ); smffa dla681 (.D(SUMMAND[574]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[574]) ); smffa dla682 (.D(SUMMAND[575]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[575]) ); smffa dla683 (.D(SUMMAND[576]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[576]) ); smfulladder dfa461 (.DATA_A (LATCHED_PP[574]), .DATA_B (LATCHED_PP[575]), .DATA_C (LATCHED_PP[576]), .SAVE (INT_SUM[627]), .CARRY (INT_CARRY[508]) ); smffa dla684 (.D(SUMMAND[577]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[577]) ); smffa dla685 (.D(SUMMAND[578]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[578]) ); smffa dla686 (.D(SUMMAND[579]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[579]) ); smfulladder dfa462 (.DATA_A (LATCHED_PP[577]), .DATA_B (LATCHED_PP[578]), .DATA_C (LATCHED_PP[579]), .SAVE (INT_SUM[628]), .CARRY (INT_CARRY[509]) ); smffa dla687 (.D(SUMMAND[580]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[580]) ); smfulladder dfa463 (.DATA_A (LATCHED_PP[580]), .DATA_B (INT_CARRY[501]), .DATA_C (INT_CARRY[502]), .SAVE (INT_SUM[629]), .CARRY (INT_CARRY[510]) ); smfulladder dfa464 (.DATA_A (INT_SUM[627]), .DATA_B (INT_SUM[628]), .DATA_C (INT_SUM[629]), .SAVE (INT_SUM[630]), .CARRY (INT_CARRY[511]) ); assign INT_SUM[631] = INT_CARRY[503]; smfulladder dfa465 (.DATA_A (INT_SUM[630]), .DATA_B (INT_SUM[631]), .DATA_C (INT_CARRY[504]), .SAVE (INT_SUM[632]), .CARRY (INT_CARRY[512]) ); assign INT_SUM[633] = INT_CARRY[505]; smfulladder dfa466 (.DATA_A (INT_SUM[632]), .DATA_B (INT_SUM[633]), .DATA_C (INT_CARRY[506]), .SAVE (INT_SUM[634]), .CARRY (INT_CARRY[507]) ); smffb dla688 (.D(INT_SUM[634]), .clk(clk), .en_d2(en_d2), .Q(SUM[54]) ); smffb dla689 (.D(INT_CARRY[507]), .clk(clk), .en_d2(en_d2), .Q(CARRY[54]) ); smffa dla690 (.D(SUMMAND[581]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[581]) ); smffa dla691 (.D(SUMMAND[582]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[582]) ); smffa dla692 (.D(SUMMAND[583]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[583]) ); smfulladder dfa467 (.DATA_A (LATCHED_PP[581]), .DATA_B (LATCHED_PP[582]), .DATA_C (LATCHED_PP[583]), .SAVE (INT_SUM[635]), .CARRY (INT_CARRY[514]) ); smffa dla693 (.D(SUMMAND[584]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[584]) ); smffa dla694 (.D(SUMMAND[585]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[585]) ); smffa dla695 (.D(SUMMAND[586]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[586]) ); smfulladder dfa468 (.DATA_A (LATCHED_PP[584]), .DATA_B (LATCHED_PP[585]), .DATA_C (LATCHED_PP[586]), .SAVE (INT_SUM[636]), .CARRY (INT_CARRY[515]) ); smffa dla696 (.D(SUMMAND[587]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[587]) ); assign INT_SUM[637] = LATCHED_PP[587]; smfulladder dfa469 (.DATA_A (INT_SUM[635]), .DATA_B (INT_SUM[636]), .DATA_C (INT_SUM[637]), .SAVE (INT_SUM[638]), .CARRY (INT_CARRY[516]) ); smfulladder dfa470 (.DATA_A (INT_CARRY[508]), .DATA_B (INT_CARRY[509]), .DATA_C (INT_CARRY[510]), .SAVE (INT_SUM[639]), .CARRY (INT_CARRY[517]) ); smfulladder dfa471 (.DATA_A (INT_SUM[638]), .DATA_B (INT_SUM[639]), .DATA_C (INT_CARRY[511]), .SAVE (INT_SUM[640]), .CARRY (INT_CARRY[518]) ); smhalfadder dha46 (.DATA_A (INT_SUM[640]), .DATA_B (INT_CARRY[512]), .SAVE (INT_SUM[641]), .CARRY (INT_CARRY[513]) ); smffb dla697 (.D(INT_SUM[641]), .clk(clk), .en_d2(en_d2), .Q(SUM[55]) ); smffb dla698 (.D(INT_CARRY[513]), .clk(clk), .en_d2(en_d2), .Q(CARRY[55]) ); smffa dla699 (.D(SUMMAND[588]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[588]) ); smffa dla700 (.D(SUMMAND[589]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[589]) ); smffa dla701 (.D(SUMMAND[590]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[590]) ); smfulladder dfa472 (.DATA_A (LATCHED_PP[588]), .DATA_B (LATCHED_PP[589]), .DATA_C (LATCHED_PP[590]), .SAVE (INT_SUM[642]), .CARRY (INT_CARRY[520]) ); smffa dla702 (.D(SUMMAND[591]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[591]) ); smffa dla703 (.D(SUMMAND[592]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[592]) ); smffa dla704 (.D(SUMMAND[593]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[593]) ); smfulladder dfa473 (.DATA_A (LATCHED_PP[591]), .DATA_B (LATCHED_PP[592]), .DATA_C (LATCHED_PP[593]), .SAVE (INT_SUM[643]), .CARRY (INT_CARRY[521]) ); smfulladder dfa474 (.DATA_A (INT_SUM[642]), .DATA_B (INT_SUM[643]), .DATA_C (INT_CARRY[514]), .SAVE (INT_SUM[644]), .CARRY (INT_CARRY[522]) ); assign INT_SUM[645] = INT_CARRY[515]; smfulladder dfa475 (.DATA_A (INT_SUM[644]), .DATA_B (INT_SUM[645]), .DATA_C (INT_CARRY[516]), .SAVE (INT_SUM[646]), .CARRY (INT_CARRY[523]) ); assign INT_SUM[647] = INT_CARRY[517]; smfulladder dfa476 (.DATA_A (INT_SUM[646]), .DATA_B (INT_SUM[647]), .DATA_C (INT_CARRY[518]), .SAVE (INT_SUM[648]), .CARRY (INT_CARRY[519]) ); smffb dla705 (.D(INT_SUM[648]), .clk(clk), .en_d2(en_d2), .Q(SUM[56]) ); smffb dla706 (.D(INT_CARRY[519]), .clk(clk), .en_d2(en_d2), .Q(CARRY[56]) ); smffa dla707 (.D(SUMMAND[594]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[594]) ); smffa dla708 (.D(SUMMAND[595]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[595]) ); smffa dla709 (.D(SUMMAND[596]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[596]) ); smfulladder dfa477 (.DATA_A (LATCHED_PP[594]), .DATA_B (LATCHED_PP[595]), .DATA_C (LATCHED_PP[596]), .SAVE (INT_SUM[649]), .CARRY (INT_CARRY[525]) ); smffa dla710 (.D(SUMMAND[597]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[597]) ); smffa dla711 (.D(SUMMAND[598]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[598]) ); smffa dla712 (.D(SUMMAND[599]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[599]) ); smfulladder dfa478 (.DATA_A (LATCHED_PP[597]), .DATA_B (LATCHED_PP[598]), .DATA_C (LATCHED_PP[599]), .SAVE (INT_SUM[650]), .CARRY (INT_CARRY[526]) ); smfulladder dfa479 (.DATA_A (INT_SUM[649]), .DATA_B (INT_SUM[650]), .DATA_C (INT_CARRY[520]), .SAVE (INT_SUM[651]), .CARRY (INT_CARRY[527]) ); assign INT_SUM[652] = INT_CARRY[521]; smfulladder dfa480 (.DATA_A (INT_SUM[651]), .DATA_B (INT_SUM[652]), .DATA_C (INT_CARRY[522]), .SAVE (INT_SUM[653]), .CARRY (INT_CARRY[528]) ); smhalfadder dha47 (.DATA_A (INT_SUM[653]), .DATA_B (INT_CARRY[523]), .SAVE (INT_SUM[654]), .CARRY (INT_CARRY[524]) ); smffb dla713 (.D(INT_SUM[654]), .clk(clk), .en_d2(en_d2), .Q(SUM[57]) ); smffb dla714 (.D(INT_CARRY[524]), .clk(clk), .en_d2(en_d2), .Q(CARRY[57]) ); smffa dla715 (.D(SUMMAND[600]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[600]) ); smffa dla716 (.D(SUMMAND[601]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[601]) ); smffa dla717 (.D(SUMMAND[602]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[602]) ); smfulladder dfa481 (.DATA_A (LATCHED_PP[600]), .DATA_B (LATCHED_PP[601]), .DATA_C (LATCHED_PP[602]), .SAVE (INT_SUM[655]), .CARRY (INT_CARRY[530]) ); smffa dla718 (.D(SUMMAND[603]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[603]) ); smffa dla719 (.D(SUMMAND[604]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[604]) ); smhalfadder dha48 (.DATA_A (LATCHED_PP[603]), .DATA_B (LATCHED_PP[604]), .SAVE (INT_SUM[656]), .CARRY (INT_CARRY[531]) ); smfulladder dfa482 (.DATA_A (INT_SUM[655]), .DATA_B (INT_SUM[656]), .DATA_C (INT_CARRY[525]), .SAVE (INT_SUM[657]), .CARRY (INT_CARRY[532]) ); assign INT_SUM[658] = INT_CARRY[526]; smfulladder dfa483 (.DATA_A (INT_SUM[657]), .DATA_B (INT_SUM[658]), .DATA_C (INT_CARRY[527]), .SAVE (INT_SUM[659]), .CARRY (INT_CARRY[533]) ); smhalfadder dha49 (.DATA_A (INT_SUM[659]), .DATA_B (INT_CARRY[528]), .SAVE (INT_SUM[660]), .CARRY (INT_CARRY[529]) ); smffb dla720 (.D(INT_SUM[660]), .clk(clk), .en_d2(en_d2), .Q(SUM[58]) ); smffb dla721 (.D(INT_CARRY[529]), .clk(clk), .en_d2(en_d2), .Q(CARRY[58]) ); smffa dla722 (.D(SUMMAND[605]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[605]) ); smffa dla723 (.D(SUMMAND[606]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[606]) ); smffa dla724 (.D(SUMMAND[607]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[607]) ); smfulladder dfa484 (.DATA_A (LATCHED_PP[605]), .DATA_B (LATCHED_PP[606]), .DATA_C (LATCHED_PP[607]), .SAVE (INT_SUM[661]), .CARRY (INT_CARRY[535]) ); smffa dla725 (.D(SUMMAND[608]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[608]) ); smffa dla726 (.D(SUMMAND[609]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[609]) ); smhalfadder dha50 (.DATA_A (LATCHED_PP[608]), .DATA_B (LATCHED_PP[609]), .SAVE (INT_SUM[662]), .CARRY (INT_CARRY[536]) ); smfulladder dfa485 (.DATA_A (INT_SUM[661]), .DATA_B (INT_SUM[662]), .DATA_C (INT_CARRY[530]), .SAVE (INT_SUM[663]), .CARRY (INT_CARRY[537]) ); assign INT_SUM[664] = INT_CARRY[531]; smfulladder dfa486 (.DATA_A (INT_SUM[663]), .DATA_B (INT_SUM[664]), .DATA_C (INT_CARRY[532]), .SAVE (INT_SUM[665]), .CARRY (INT_CARRY[538]) ); smhalfadder dha51 (.DATA_A (INT_SUM[665]), .DATA_B (INT_CARRY[533]), .SAVE (INT_SUM[666]), .CARRY (INT_CARRY[534]) ); smffb dla727 (.D(INT_SUM[666]), .clk(clk), .en_d2(en_d2), .Q(SUM[59]) ); smffb dla728 (.D(INT_CARRY[534]), .clk(clk), .en_d2(en_d2), .Q(CARRY[59]) ); smffa dla729 (.D(SUMMAND[610]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[610]) ); smffa dla730 (.D(SUMMAND[611]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[611]) ); smffa dla731 (.D(SUMMAND[612]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[612]) ); smfulladder dfa487 (.DATA_A (LATCHED_PP[610]), .DATA_B (LATCHED_PP[611]), .DATA_C (LATCHED_PP[612]), .SAVE (INT_SUM[667]), .CARRY (INT_CARRY[540]) ); smffa dla732 (.D(SUMMAND[613]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[613]) ); smfulladder dfa488 (.DATA_A (LATCHED_PP[613]), .DATA_B (INT_CARRY[535]), .DATA_C (INT_CARRY[536]), .SAVE (INT_SUM[668]), .CARRY (INT_CARRY[541]) ); smfulladder dfa489 (.DATA_A (INT_SUM[667]), .DATA_B (INT_SUM[668]), .DATA_C (INT_CARRY[537]), .SAVE (INT_SUM[669]), .CARRY (INT_CARRY[542]) ); smhalfadder dha52 (.DATA_A (INT_SUM[669]), .DATA_B (INT_CARRY[538]), .SAVE (INT_SUM[670]), .CARRY (INT_CARRY[539]) ); smffb dla733 (.D(INT_SUM[670]), .clk(clk), .en_d2(en_d2), .Q(SUM[60]) ); smffb dla734 (.D(INT_CARRY[539]), .clk(clk), .en_d2(en_d2), .Q(CARRY[60]) ); smffa dla735 (.D(SUMMAND[614]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[614]) ); smffa dla736 (.D(SUMMAND[615]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[615]) ); smffa dla737 (.D(SUMMAND[616]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[616]) ); smfulladder dfa490 (.DATA_A (LATCHED_PP[614]), .DATA_B (LATCHED_PP[615]), .DATA_C (LATCHED_PP[616]), .SAVE (INT_SUM[671]), .CARRY (INT_CARRY[544]) ); smffa dla738 (.D(SUMMAND[617]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[617]) ); assign INT_SUM[672] = LATCHED_PP[617]; smfulladder dfa491 (.DATA_A (INT_SUM[671]), .DATA_B (INT_SUM[672]), .DATA_C (INT_CARRY[540]), .SAVE (INT_SUM[673]), .CARRY (INT_CARRY[545]) ); assign INT_SUM[674] = INT_CARRY[541]; smfulladder dfa492 (.DATA_A (INT_SUM[673]), .DATA_B (INT_SUM[674]), .DATA_C (INT_CARRY[542]), .SAVE (INT_SUM[675]), .CARRY (INT_CARRY[543]) ); smffb dla739 (.D(INT_SUM[675]), .clk(clk), .en_d2(en_d2), .Q(SUM[61]) ); smffb dla740 (.D(INT_CARRY[543]), .clk(clk), .en_d2(en_d2), .Q(CARRY[61]) ); smffa dla741 (.D(SUMMAND[618]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[618]) ); smffa dla742 (.D(SUMMAND[619]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[619]) ); smffa dla743 (.D(SUMMAND[620]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[620]) ); smfulladder dfa493 (.DATA_A (LATCHED_PP[618]), .DATA_B (LATCHED_PP[619]), .DATA_C (LATCHED_PP[620]), .SAVE (INT_SUM[676]), .CARRY (INT_CARRY[547]) ); assign INT_SUM[677] = INT_SUM[676]; assign INT_SUM[678] = INT_CARRY[544]; smfulladder dfa494 (.DATA_A (INT_SUM[677]), .DATA_B (INT_SUM[678]), .DATA_C (INT_CARRY[545]), .SAVE (INT_SUM[679]), .CARRY (INT_CARRY[546]) ); smffb dla744 (.D(INT_SUM[679]), .clk(clk), .en_d2(en_d2), .Q(SUM[62]) ); smffb dla745 (.D(INT_CARRY[546]), .clk(clk), .en_d2(en_d2), .Q(CARRY[62]) ); smffa dla746 (.D(SUMMAND[621]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[621]) ); smffa dla747 (.D(SUMMAND[622]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[622]) ); smffa dla748 (.D(SUMMAND[623]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[623]) ); smfulladder dfa495 (.DATA_A (LATCHED_PP[621]), .DATA_B (LATCHED_PP[622]), .DATA_C (LATCHED_PP[623]), .SAVE (INT_SUM[680]), .CARRY (INT_CARRY[549]) ); assign INT_SUM[681] = INT_CARRY[547]; smhalfadder dha53 (.DATA_A (INT_SUM[680]), .DATA_B (INT_SUM[681]), .SAVE (INT_SUM[682]), .CARRY (INT_CARRY[548]) ); smffb dla749 (.D(INT_SUM[682]), .clk(clk), .en_d2(en_d2), .Q(SUM[63]) ); smffb dla750 (.D(INT_CARRY[548]), .clk(clk), .en_d2(en_d2), .Q(CARRY[63]) ); smffa dla751 (.D(SUMMAND[624]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[624]) ); assign INT_SUM[683] = LATCHED_PP[624]; smffa dla752 (.D(SUMMAND[625]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[625]) ); assign INT_SUM[684] = LATCHED_PP[625]; smfulladder dfa496 (.DATA_A (INT_SUM[683]), .DATA_B (INT_SUM[684]), .DATA_C (INT_CARRY[549]), .SAVE (INT_SUM[685]), .CARRY (INT_CARRY[550]) ); smffb dla753 (.D(INT_SUM[685]), .clk(clk), .en_d2(en_d2), .Q(SUM[64]) ); smffb dla754 (.D(INT_CARRY[550]), .clk(clk), .en_d2(en_d2), .Q(CARRY[64]) ); smffa dla755 (.D(SUMMAND[626]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[626]) ); smffa dla756 (.D(SUMMAND[627]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[627]) ); smhalfadder dha54 (.DATA_A (LATCHED_PP[626]), .DATA_B (LATCHED_PP[627]), .SAVE (INT_SUM[686]), .CARRY (INT_CARRY[551]) ); smffb dla757 (.D(INT_SUM[686]), .clk(clk), .en_d2(en_d2), .Q(SUM[65]) ); smffb dla758 (.D(INT_CARRY[551]), .clk(clk), .en_d2(en_d2), .Q(CARRY[65]) ); smffa dla759 (.D(SUMMAND[628]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[628]) ); assign INT_SUM[687] = LATCHED_PP[628]; smffb dla760 (.D(INT_SUM[687]), .clk(clk), .en_d2(en_d2), .Q(SUM[66]) ); endmodule module smprestage_128 (A, B, CIN, POUT, GOUT); input [63:0] A; input [63:0] B; input CIN; output [63:0] POUT; output [63:0] GOUT; smblock0 d10 (A[0], B[0], POUT[0], GOUT[1] ); smblock0 d11 (A[1], B[1], POUT[1], GOUT[2] ); smblock0 d12 (A[2], B[2], POUT[2], GOUT[3] ); smblock0 d13 (A[3], B[3], POUT[3], GOUT[4] ); smblock0 d14 (A[4], B[4], POUT[4], GOUT[5] ); smblock0 d15 (A[5], B[5], POUT[5], GOUT[6] ); smblock0 d16 (A[6], B[6], POUT[6], GOUT[7] ); smblock0 d17 (A[7], B[7], POUT[7], GOUT[8] ); smblock0 d18 (A[8], B[8], POUT[8], GOUT[9] ); smblock0 d19 (A[9], B[9], POUT[9], GOUT[10] ); smblock0 d110 (A[10], B[10], POUT[10], GOUT[11] ); smblock0 d111 (A[11], B[11], POUT[11], GOUT[12] ); smblock0 d112 (A[12], B[12], POUT[12], GOUT[13] ); smblock0 d113 (A[13], B[13], POUT[13], GOUT[14] ); smblock0 d114 (A[14], B[14], POUT[14], GOUT[15] ); smblock0 d115 (A[15], B[15], POUT[15], GOUT[16] ); smblock0 d116 (A[16], B[16], POUT[16], GOUT[17] ); smblock0 d117 (A[17], B[17], POUT[17], GOUT[18] ); smblock0 d118 (A[18], B[18], POUT[18], GOUT[19] ); smblock0 d119 (A[19], B[19], POUT[19], GOUT[20] ); smblock0 d120 (A[20], B[20], POUT[20], GOUT[21] ); smblock0 d121 (A[21], B[21], POUT[21], GOUT[22] ); smblock0 d122 (A[22], B[22], POUT[22], GOUT[23] ); smblock0 d123 (A[23], B[23], POUT[23], GOUT[24] ); smblock0 d124 (A[24], B[24], POUT[24], GOUT[25] ); smblock0 d125 (A[25], B[25], POUT[25], GOUT[26] ); smblock0 d126 (A[26], B[26], POUT[26], GOUT[27] ); smblock0 d127 (A[27], B[27], POUT[27], GOUT[28] ); smblock0 d128 (A[28], B[28], POUT[28], GOUT[29] ); smblock0 d129 (A[29], B[29], POUT[29], GOUT[30] ); smblock0 d130 (A[30], B[30], POUT[30], GOUT[31] ); smblock0 d131 (A[31], B[31], POUT[31], GOUT[32] ); smblock0 d132 (A[32], B[32], POUT[32], GOUT[33] ); smblock0 d133 (A[33], B[33], POUT[33], GOUT[34] ); smblock0 d134 (A[34], B[34], POUT[34], GOUT[35] ); smblock0 d135 (A[35], B[35], POUT[35], GOUT[36] ); smblock0 d136 (A[36], B[36], POUT[36], GOUT[37] ); smblock0 d137 (A[37], B[37], POUT[37], GOUT[38] ); smblock0 d138 (A[38], B[38], POUT[38], GOUT[39] ); smblock0 d139 (A[39], B[39], POUT[39], GOUT[40] ); smblock0 d140 (A[40], B[40], POUT[40], GOUT[41] ); smblock0 d141 (A[41], B[41], POUT[41], GOUT[42] ); smblock0 d142 (A[42], B[42], POUT[42], GOUT[43] ); smblock0 d143 (A[43], B[43], POUT[43], GOUT[44] ); smblock0 d144 (A[44], B[44], POUT[44], GOUT[45] ); smblock0 d145 (A[45], B[45], POUT[45], GOUT[46] ); smblock0 d146 (A[46], B[46], POUT[46], GOUT[47] ); smblock0 d147 (A[47], B[47], POUT[47], GOUT[48] ); smblock0 d148 (A[48], B[48], POUT[48], GOUT[49] ); smblock0 d149 (A[49], B[49], POUT[49], GOUT[50] ); smblock0 d150 (A[50], B[50], POUT[50], GOUT[51] ); smblock0 d151 (A[51], B[51], POUT[51], GOUT[52] ); smblock0 d152 (A[52], B[52], POUT[52], GOUT[53] ); smblock0 d153 (A[53], B[53], POUT[53], GOUT[54] ); smblock0 d154 (A[54], B[54], POUT[54], GOUT[55] ); smblock0 d155 (A[55], B[55], POUT[55], GOUT[56] ); smblock0 d156 (A[56], B[56], POUT[56], GOUT[57] ); smblock0 d157 (A[57], B[57], POUT[57], GOUT[58] ); smblock0 d158 (A[58], B[58], POUT[58], GOUT[59] ); smblock0 d159 (A[59], B[59], POUT[59], GOUT[60] ); smblock0 d160 (A[60], B[60], POUT[60], GOUT[61] ); smblock0 d161 (A[61], B[61], POUT[61], GOUT[62] ); smblock0 d162 (A[62], B[62], POUT[62], GOUT[63] ); sminvblock d2 (CIN, GOUT[0] ); endmodule module smdblc_0_128 (PIN, GIN, POUT, GOUT); input [63:0] PIN; input [63:0] GIN; output [63:0] POUT; output [63:0] GOUT; sminvblock d10 (GIN[0], GOUT[0] ); smblock1a d21 (PIN[0], GIN[0], GIN[1], GOUT[1] ); smblock1 d32 (PIN[0], PIN[1], GIN[1], GIN[2], POUT[0], GOUT[2] ); smblock1 d33 (PIN[1], PIN[2], GIN[2], GIN[3], POUT[1], GOUT[3] ); smblock1 d34 (PIN[2], PIN[3], GIN[3], GIN[4], POUT[2], GOUT[4] ); smblock1 d35 (PIN[3], PIN[4], GIN[4], GIN[5], POUT[3], GOUT[5] ); smblock1 d36 (PIN[4], PIN[5], GIN[5], GIN[6], POUT[4], GOUT[6] ); smblock1 d37 (PIN[5], PIN[6], GIN[6], GIN[7], POUT[5], GOUT[7] ); smblock1 d38 (PIN[6], PIN[7], GIN[7], GIN[8], POUT[6], GOUT[8] ); smblock1 d39 (PIN[7], PIN[8], GIN[8], GIN[9], POUT[7], GOUT[9] ); smblock1 d310 (PIN[8], PIN[9], GIN[9], GIN[10], POUT[8], GOUT[10] ); smblock1 d311 (PIN[9], PIN[10], GIN[10], GIN[11], POUT[9], GOUT[11] ); smblock1 d312 (PIN[10], PIN[11], GIN[11], GIN[12], POUT[10], GOUT[12] ); smblock1 d313 (PIN[11], PIN[12], GIN[12], GIN[13], POUT[11], GOUT[13] ); smblock1 d314 (PIN[12], PIN[13], GIN[13], GIN[14], POUT[12], GOUT[14] ); smblock1 d315 (PIN[13], PIN[14], GIN[14], GIN[15], POUT[13], GOUT[15] ); smblock1 d316 (PIN[14], PIN[15], GIN[15], GIN[16], POUT[14], GOUT[16] ); smblock1 d317 (PIN[15], PIN[16], GIN[16], GIN[17], POUT[15], GOUT[17] ); smblock1 d318 (PIN[16], PIN[17], GIN[17], GIN[18], POUT[16], GOUT[18] ); smblock1 d319 (PIN[17], PIN[18], GIN[18], GIN[19], POUT[17], GOUT[19] ); smblock1 d320 (PIN[18], PIN[19], GIN[19], GIN[20], POUT[18], GOUT[20] ); smblock1 d321 (PIN[19], PIN[20], GIN[20], GIN[21], POUT[19], GOUT[21] ); smblock1 d322 (PIN[20], PIN[21], GIN[21], GIN[22], POUT[20], GOUT[22] ); smblock1 d323 (PIN[21], PIN[22], GIN[22], GIN[23], POUT[21], GOUT[23] ); smblock1 d324 (PIN[22], PIN[23], GIN[23], GIN[24], POUT[22], GOUT[24] ); smblock1 d325 (PIN[23], PIN[24], GIN[24], GIN[25], POUT[23], GOUT[25] ); smblock1 d326 (PIN[24], PIN[25], GIN[25], GIN[26], POUT[24], GOUT[26] ); smblock1 d327 (PIN[25], PIN[26], GIN[26], GIN[27], POUT[25], GOUT[27] ); smblock1 d328 (PIN[26], PIN[27], GIN[27], GIN[28], POUT[26], GOUT[28] ); smblock1 d329 (PIN[27], PIN[28], GIN[28], GIN[29], POUT[27], GOUT[29] ); smblock1 d330 (PIN[28], PIN[29], GIN[29], GIN[30], POUT[28], GOUT[30] ); smblock1 d331 (PIN[29], PIN[30], GIN[30], GIN[31], POUT[29], GOUT[31] ); smblock1 d332 (PIN[30], PIN[31], GIN[31], GIN[32], POUT[30], GOUT[32] ); smblock1 d333 (PIN[31], PIN[32], GIN[32], GIN[33], POUT[31], GOUT[33] ); smblock1 d334 (PIN[32], PIN[33], GIN[33], GIN[34], POUT[32], GOUT[34] ); smblock1 d335 (PIN[33], PIN[34], GIN[34], GIN[35], POUT[33], GOUT[35] ); smblock1 d336 (PIN[34], PIN[35], GIN[35], GIN[36], POUT[34], GOUT[36] ); smblock1 d337 (PIN[35], PIN[36], GIN[36], GIN[37], POUT[35], GOUT[37] ); smblock1 d338 (PIN[36], PIN[37], GIN[37], GIN[38], POUT[36], GOUT[38] ); smblock1 d339 (PIN[37], PIN[38], GIN[38], GIN[39], POUT[37], GOUT[39] ); smblock1 d340 (PIN[38], PIN[39], GIN[39], GIN[40], POUT[38], GOUT[40] ); smblock1 d341 (PIN[39], PIN[40], GIN[40], GIN[41], POUT[39], GOUT[41] ); smblock1 d342 (PIN[40], PIN[41], GIN[41], GIN[42], POUT[40], GOUT[42] ); smblock1 d343 (PIN[41], PIN[42], GIN[42], GIN[43], POUT[41], GOUT[43] ); smblock1 d344 (PIN[42], PIN[43], GIN[43], GIN[44], POUT[42], GOUT[44] ); smblock1 d345 (PIN[43], PIN[44], GIN[44], GIN[45], POUT[43], GOUT[45] ); smblock1 d346 (PIN[44], PIN[45], GIN[45], GIN[46], POUT[44], GOUT[46] ); smblock1 d347 (PIN[45], PIN[46], GIN[46], GIN[47], POUT[45], GOUT[47] ); smblock1 d348 (PIN[46], PIN[47], GIN[47], GIN[48], POUT[46], GOUT[48] ); smblock1 d349 (PIN[47], PIN[48], GIN[48], GIN[49], POUT[47], GOUT[49] ); smblock1 d350 (PIN[48], PIN[49], GIN[49], GIN[50], POUT[48], GOUT[50] ); smblock1 d351 (PIN[49], PIN[50], GIN[50], GIN[51], POUT[49], GOUT[51] ); smblock1 d352 (PIN[50], PIN[51], GIN[51], GIN[52], POUT[50], GOUT[52] ); smblock1 d353 (PIN[51], PIN[52], GIN[52], GIN[53], POUT[51], GOUT[53] ); smblock1 d354 (PIN[52], PIN[53], GIN[53], GIN[54], POUT[52], GOUT[54] ); smblock1 d355 (PIN[53], PIN[54], GIN[54], GIN[55], POUT[53], GOUT[55] ); smblock1 d356 (PIN[54], PIN[55], GIN[55], GIN[56], POUT[54], GOUT[56] ); smblock1 d357 (PIN[55], PIN[56], GIN[56], GIN[57], POUT[55], GOUT[57] ); smblock1 d358 (PIN[56], PIN[57], GIN[57], GIN[58], POUT[56], GOUT[58] ); smblock1 d359 (PIN[57], PIN[58], GIN[58], GIN[59], POUT[57], GOUT[59] ); smblock1 d360 (PIN[58], PIN[59], GIN[59], GIN[60], POUT[58], GOUT[60] ); smblock1 d361 (PIN[59], PIN[60], GIN[60], GIN[61], POUT[59], GOUT[61] ); smblock1 d362 (PIN[60], PIN[61], GIN[61], GIN[62], POUT[60], GOUT[62] ); smblock1 d363 (PIN[61], PIN[62], GIN[62], GIN[63], POUT[61], GOUT[63] ); endmodule module smdblc_1_128 (PIN, GIN, POUT, GOUT); input [63:0] PIN; input [63:0] GIN; output [63:0] POUT; output [63:0] GOUT; sminvblock d10 (GIN[0], GOUT[0] ); sminvblock d11 (GIN[1], GOUT[1] ); smblock2a d22 (PIN[0], GIN[0], GIN[2], GOUT[2] ); smblock2a d23 (PIN[1], GIN[1], GIN[3], GOUT[3] ); smblock2 d34 (PIN[0], PIN[2], GIN[2], GIN[4], POUT[0], GOUT[4] ); smblock2 d35 (PIN[1], PIN[3], GIN[3], GIN[5], POUT[1], GOUT[5] ); smblock2 d36 (PIN[2], PIN[4], GIN[4], GIN[6], POUT[2], GOUT[6] ); smblock2 d37 (PIN[3], PIN[5], GIN[5], GIN[7], POUT[3], GOUT[7] ); smblock2 d38 (PIN[4], PIN[6], GIN[6], GIN[8], POUT[4], GOUT[8] ); smblock2 d39 (PIN[5], PIN[7], GIN[7], GIN[9], POUT[5], GOUT[9] ); smblock2 d310 (PIN[6], PIN[8], GIN[8], GIN[10], POUT[6], GOUT[10] ); smblock2 d311 (PIN[7], PIN[9], GIN[9], GIN[11], POUT[7], GOUT[11] ); smblock2 d312 (PIN[8], PIN[10], GIN[10], GIN[12], POUT[8], GOUT[12] ); smblock2 d313 (PIN[9], PIN[11], GIN[11], GIN[13], POUT[9], GOUT[13] ); smblock2 d314 (PIN[10], PIN[12], GIN[12], GIN[14], POUT[10], GOUT[14] ); smblock2 d315 (PIN[11], PIN[13], GIN[13], GIN[15], POUT[11], GOUT[15] ); smblock2 d316 (PIN[12], PIN[14], GIN[14], GIN[16], POUT[12], GOUT[16] ); smblock2 d317 (PIN[13], PIN[15], GIN[15], GIN[17], POUT[13], GOUT[17] ); smblock2 d318 (PIN[14], PIN[16], GIN[16], GIN[18], POUT[14], GOUT[18] ); smblock2 d319 (PIN[15], PIN[17], GIN[17], GIN[19], POUT[15], GOUT[19] ); smblock2 d320 (PIN[16], PIN[18], GIN[18], GIN[20], POUT[16], GOUT[20] ); smblock2 d321 (PIN[17], PIN[19], GIN[19], GIN[21], POUT[17], GOUT[21] ); smblock2 d322 (PIN[18], PIN[20], GIN[20], GIN[22], POUT[18], GOUT[22] ); smblock2 d323 (PIN[19], PIN[21], GIN[21], GIN[23], POUT[19], GOUT[23] ); smblock2 d324 (PIN[20], PIN[22], GIN[22], GIN[24], POUT[20], GOUT[24] ); smblock2 d325 (PIN[21], PIN[23], GIN[23], GIN[25], POUT[21], GOUT[25] ); smblock2 d326 (PIN[22], PIN[24], GIN[24], GIN[26], POUT[22], GOUT[26] ); smblock2 d327 (PIN[23], PIN[25], GIN[25], GIN[27], POUT[23], GOUT[27] ); smblock2 d328 (PIN[24], PIN[26], GIN[26], GIN[28], POUT[24], GOUT[28] ); smblock2 d329 (PIN[25], PIN[27], GIN[27], GIN[29], POUT[25], GOUT[29] ); smblock2 d330 (PIN[26], PIN[28], GIN[28], GIN[30], POUT[26], GOUT[30] ); smblock2 d331 (PIN[27], PIN[29], GIN[29], GIN[31], POUT[27], GOUT[31] ); smblock2 d332 (PIN[28], PIN[30], GIN[30], GIN[32], POUT[28], GOUT[32] ); smblock2 d333 (PIN[29], PIN[31], GIN[31], GIN[33], POUT[29], GOUT[33] ); smblock2 d334 (PIN[30], PIN[32], GIN[32], GIN[34], POUT[30], GOUT[34] ); smblock2 d335 (PIN[31], PIN[33], GIN[33], GIN[35], POUT[31], GOUT[35] ); smblock2 d336 (PIN[32], PIN[34], GIN[34], GIN[36], POUT[32], GOUT[36] ); smblock2 d337 (PIN[33], PIN[35], GIN[35], GIN[37], POUT[33], GOUT[37] ); smblock2 d338 (PIN[34], PIN[36], GIN[36], GIN[38], POUT[34], GOUT[38] ); smblock2 d339 (PIN[35], PIN[37], GIN[37], GIN[39], POUT[35], GOUT[39] ); smblock2 d340 (PIN[36], PIN[38], GIN[38], GIN[40], POUT[36], GOUT[40] ); smblock2 d341 (PIN[37], PIN[39], GIN[39], GIN[41], POUT[37], GOUT[41] ); smblock2 d342 (PIN[38], PIN[40], GIN[40], GIN[42], POUT[38], GOUT[42] ); smblock2 d343 (PIN[39], PIN[41], GIN[41], GIN[43], POUT[39], GOUT[43] ); smblock2 d344 (PIN[40], PIN[42], GIN[42], GIN[44], POUT[40], GOUT[44] ); smblock2 d345 (PIN[41], PIN[43], GIN[43], GIN[45], POUT[41], GOUT[45] ); smblock2 d346 (PIN[42], PIN[44], GIN[44], GIN[46], POUT[42], GOUT[46] ); smblock2 d347 (PIN[43], PIN[45], GIN[45], GIN[47], POUT[43], GOUT[47] ); smblock2 d348 (PIN[44], PIN[46], GIN[46], GIN[48], POUT[44], GOUT[48] ); smblock2 d349 (PIN[45], PIN[47], GIN[47], GIN[49], POUT[45], GOUT[49] ); smblock2 d350 (PIN[46], PIN[48], GIN[48], GIN[50], POUT[46], GOUT[50] ); smblock2 d351 (PIN[47], PIN[49], GIN[49], GIN[51], POUT[47], GOUT[51] ); smblock2 d352 (PIN[48], PIN[50], GIN[50], GIN[52], POUT[48], GOUT[52] ); smblock2 d353 (PIN[49], PIN[51], GIN[51], GIN[53], POUT[49], GOUT[53] ); smblock2 d354 (PIN[50], PIN[52], GIN[52], GIN[54], POUT[50], GOUT[54] ); smblock2 d355 (PIN[51], PIN[53], GIN[53], GIN[55], POUT[51], GOUT[55] ); smblock2 d356 (PIN[52], PIN[54], GIN[54], GIN[56], POUT[52], GOUT[56] ); smblock2 d357 (PIN[53], PIN[55], GIN[55], GIN[57], POUT[53], GOUT[57] ); smblock2 d358 (PIN[54], PIN[56], GIN[56], GIN[58], POUT[54], GOUT[58] ); smblock2 d359 (PIN[55], PIN[57], GIN[57], GIN[59], POUT[55], GOUT[59] ); smblock2 d360 (PIN[56], PIN[58], GIN[58], GIN[60], POUT[56], GOUT[60] ); smblock2 d361 (PIN[57], PIN[59], GIN[59], GIN[61], POUT[57], GOUT[61] ); smblock2 d362 (PIN[58], PIN[60], GIN[60], GIN[62], POUT[58], GOUT[62] ); smblock2 d363 (PIN[59], PIN[61], GIN[61], GIN[63], POUT[59], GOUT[63] ); endmodule module smdblc_2_128 (PIN, GIN, POUT, GOUT); input [63:0] PIN; input [63:0] GIN; output [63:0] POUT; output [63:0] GOUT; sminvblock d10 (GIN[0], GOUT[0] ); sminvblock d11 (GIN[1], GOUT[1] ); sminvblock d12 (GIN[2], GOUT[2] ); sminvblock d13 (GIN[3], GOUT[3] ); smblock1a d24 (PIN[0], GIN[0], GIN[4], GOUT[4] ); smblock1a d25 (PIN[1], GIN[1], GIN[5], GOUT[5] ); smblock1a d26 (PIN[2], GIN[2], GIN[6], GOUT[6] ); smblock1a d27 (PIN[3], GIN[3], GIN[7], GOUT[7] ); smblock1 d38 (PIN[0], PIN[4], GIN[4], GIN[8], POUT[0], GOUT[8] ); smblock1 d39 (PIN[1], PIN[5], GIN[5], GIN[9], POUT[1], GOUT[9] ); smblock1 d310 (PIN[2], PIN[6], GIN[6], GIN[10], POUT[2], GOUT[10] ); smblock1 d311 (PIN[3], PIN[7], GIN[7], GIN[11], POUT[3], GOUT[11] ); smblock1 d312 (PIN[4], PIN[8], GIN[8], GIN[12], POUT[4], GOUT[12] ); smblock1 d313 (PIN[5], PIN[9], GIN[9], GIN[13], POUT[5], GOUT[13] ); smblock1 d314 (PIN[6], PIN[10], GIN[10], GIN[14], POUT[6], GOUT[14] ); smblock1 d315 (PIN[7], PIN[11], GIN[11], GIN[15], POUT[7], GOUT[15] ); smblock1 d316 (PIN[8], PIN[12], GIN[12], GIN[16], POUT[8], GOUT[16] ); smblock1 d317 (PIN[9], PIN[13], GIN[13], GIN[17], POUT[9], GOUT[17] ); smblock1 d318 (PIN[10], PIN[14], GIN[14], GIN[18], POUT[10], GOUT[18] ); smblock1 d319 (PIN[11], PIN[15], GIN[15], GIN[19], POUT[11], GOUT[19] ); smblock1 d320 (PIN[12], PIN[16], GIN[16], GIN[20], POUT[12], GOUT[20] ); smblock1 d321 (PIN[13], PIN[17], GIN[17], GIN[21], POUT[13], GOUT[21] ); smblock1 d322 (PIN[14], PIN[18], GIN[18], GIN[22], POUT[14], GOUT[22] ); smblock1 d323 (PIN[15], PIN[19], GIN[19], GIN[23], POUT[15], GOUT[23] ); smblock1 d324 (PIN[16], PIN[20], GIN[20], GIN[24], POUT[16], GOUT[24] ); smblock1 d325 (PIN[17], PIN[21], GIN[21], GIN[25], POUT[17], GOUT[25] ); smblock1 d326 (PIN[18], PIN[22], GIN[22], GIN[26], POUT[18], GOUT[26] ); smblock1 d327 (PIN[19], PIN[23], GIN[23], GIN[27], POUT[19], GOUT[27] ); smblock1 d328 (PIN[20], PIN[24], GIN[24], GIN[28], POUT[20], GOUT[28] ); smblock1 d329 (PIN[21], PIN[25], GIN[25], GIN[29], POUT[21], GOUT[29] ); smblock1 d330 (PIN[22], PIN[26], GIN[26], GIN[30], POUT[22], GOUT[30] ); smblock1 d331 (PIN[23], PIN[27], GIN[27], GIN[31], POUT[23], GOUT[31] ); smblock1 d332 (PIN[24], PIN[28], GIN[28], GIN[32], POUT[24], GOUT[32] ); smblock1 d333 (PIN[25], PIN[29], GIN[29], GIN[33], POUT[25], GOUT[33] ); smblock1 d334 (PIN[26], PIN[30], GIN[30], GIN[34], POUT[26], GOUT[34] ); smblock1 d335 (PIN[27], PIN[31], GIN[31], GIN[35], POUT[27], GOUT[35] ); smblock1 d336 (PIN[28], PIN[32], GIN[32], GIN[36], POUT[28], GOUT[36] ); smblock1 d337 (PIN[29], PIN[33], GIN[33], GIN[37], POUT[29], GOUT[37] ); smblock1 d338 (PIN[30], PIN[34], GIN[34], GIN[38], POUT[30], GOUT[38] ); smblock1 d339 (PIN[31], PIN[35], GIN[35], GIN[39], POUT[31], GOUT[39] ); smblock1 d340 (PIN[32], PIN[36], GIN[36], GIN[40], POUT[32], GOUT[40] ); smblock1 d341 (PIN[33], PIN[37], GIN[37], GIN[41], POUT[33], GOUT[41] ); smblock1 d342 (PIN[34], PIN[38], GIN[38], GIN[42], POUT[34], GOUT[42] ); smblock1 d343 (PIN[35], PIN[39], GIN[39], GIN[43], POUT[35], GOUT[43] ); smblock1 d344 (PIN[36], PIN[40], GIN[40], GIN[44], POUT[36], GOUT[44] ); smblock1 d345 (PIN[37], PIN[41], GIN[41], GIN[45], POUT[37], GOUT[45] ); smblock1 d346 (PIN[38], PIN[42], GIN[42], GIN[46], POUT[38], GOUT[46] ); smblock1 d347 (PIN[39], PIN[43], GIN[43], GIN[47], POUT[39], GOUT[47] ); smblock1 d348 (PIN[40], PIN[44], GIN[44], GIN[48], POUT[40], GOUT[48] ); smblock1 d349 (PIN[41], PIN[45], GIN[45], GIN[49], POUT[41], GOUT[49] ); smblock1 d350 (PIN[42], PIN[46], GIN[46], GIN[50], POUT[42], GOUT[50] ); smblock1 d351 (PIN[43], PIN[47], GIN[47], GIN[51], POUT[43], GOUT[51] ); smblock1 d352 (PIN[44], PIN[48], GIN[48], GIN[52], POUT[44], GOUT[52] ); smblock1 d353 (PIN[45], PIN[49], GIN[49], GIN[53], POUT[45], GOUT[53] ); smblock1 d354 (PIN[46], PIN[50], GIN[50], GIN[54], POUT[46], GOUT[54] ); smblock1 d355 (PIN[47], PIN[51], GIN[51], GIN[55], POUT[47], GOUT[55] ); smblock1 d356 (PIN[48], PIN[52], GIN[52], GIN[56], POUT[48], GOUT[56] ); smblock1 d357 (PIN[49], PIN[53], GIN[53], GIN[57], POUT[49], GOUT[57] ); smblock1 d358 (PIN[50], PIN[54], GIN[54], GIN[58], POUT[50], GOUT[58] ); smblock1 d359 (PIN[51], PIN[55], GIN[55], GIN[59], POUT[51], GOUT[59] ); smblock1 d360 (PIN[52], PIN[56], GIN[56], GIN[60], POUT[52], GOUT[60] ); smblock1 d361 (PIN[53], PIN[57], GIN[57], GIN[61], POUT[53], GOUT[61] ); smblock1 d362 (PIN[54], PIN[58], GIN[58], GIN[62], POUT[54], GOUT[62] ); smblock1 d363 (PIN[55], PIN[59], GIN[59], GIN[63], POUT[55], GOUT[63] ); endmodule module smdblc_3_128 (PIN, GIN, POUT, GOUT); input [63:0] PIN; input [63:0] GIN; output [63:0] POUT; output [63:0] GOUT; sminvblock d10 (GIN[0], GOUT[0] ); sminvblock d11 (GIN[1], GOUT[1] ); sminvblock d12 (GIN[2], GOUT[2] ); sminvblock d13 (GIN[3], GOUT[3] ); sminvblock d14 (GIN[4], GOUT[4] ); sminvblock d15 (GIN[5], GOUT[5] ); sminvblock d16 (GIN[6], GOUT[6] ); sminvblock d17 (GIN[7], GOUT[7] ); smblock2a d28 (PIN[0], GIN[0], GIN[8], GOUT[8] ); smblock2a d29 (PIN[1], GIN[1], GIN[9], GOUT[9] ); smblock2a d210 (PIN[2], GIN[2], GIN[10], GOUT[10] ); smblock2a d211 (PIN[3], GIN[3], GIN[11], GOUT[11] ); smblock2a d212 (PIN[4], GIN[4], GIN[12], GOUT[12] ); smblock2a d213 (PIN[5], GIN[5], GIN[13], GOUT[13] ); smblock2a d214 (PIN[6], GIN[6], GIN[14], GOUT[14] ); smblock2a d215 (PIN[7], GIN[7], GIN[15], GOUT[15] ); smblock2 d316 (PIN[0], PIN[8], GIN[8], GIN[16], POUT[0], GOUT[16] ); smblock2 d317 (PIN[1], PIN[9], GIN[9], GIN[17], POUT[1], GOUT[17] ); smblock2 d318 (PIN[2], PIN[10], GIN[10], GIN[18], POUT[2], GOUT[18] ); smblock2 d319 (PIN[3], PIN[11], GIN[11], GIN[19], POUT[3], GOUT[19] ); smblock2 d320 (PIN[4], PIN[12], GIN[12], GIN[20], POUT[4], GOUT[20] ); smblock2 d321 (PIN[5], PIN[13], GIN[13], GIN[21], POUT[5], GOUT[21] ); smblock2 d322 (PIN[6], PIN[14], GIN[14], GIN[22], POUT[6], GOUT[22] ); smblock2 d323 (PIN[7], PIN[15], GIN[15], GIN[23], POUT[7], GOUT[23] ); smblock2 d324 (PIN[8], PIN[16], GIN[16], GIN[24], POUT[8], GOUT[24] ); smblock2 d325 (PIN[9], PIN[17], GIN[17], GIN[25], POUT[9], GOUT[25] ); smblock2 d326 (PIN[10], PIN[18], GIN[18], GIN[26], POUT[10], GOUT[26] ); smblock2 d327 (PIN[11], PIN[19], GIN[19], GIN[27], POUT[11], GOUT[27] ); smblock2 d328 (PIN[12], PIN[20], GIN[20], GIN[28], POUT[12], GOUT[28] ); smblock2 d329 (PIN[13], PIN[21], GIN[21], GIN[29], POUT[13], GOUT[29] ); smblock2 d330 (PIN[14], PIN[22], GIN[22], GIN[30], POUT[14], GOUT[30] ); smblock2 d331 (PIN[15], PIN[23], GIN[23], GIN[31], POUT[15], GOUT[31] ); smblock2 d332 (PIN[16], PIN[24], GIN[24], GIN[32], POUT[16], GOUT[32] ); smblock2 d333 (PIN[17], PIN[25], GIN[25], GIN[33], POUT[17], GOUT[33] ); smblock2 d334 (PIN[18], PIN[26], GIN[26], GIN[34], POUT[18], GOUT[34] ); smblock2 d335 (PIN[19], PIN[27], GIN[27], GIN[35], POUT[19], GOUT[35] ); smblock2 d336 (PIN[20], PIN[28], GIN[28], GIN[36], POUT[20], GOUT[36] ); smblock2 d337 (PIN[21], PIN[29], GIN[29], GIN[37], POUT[21], GOUT[37] ); smblock2 d338 (PIN[22], PIN[30], GIN[30], GIN[38], POUT[22], GOUT[38] ); smblock2 d339 (PIN[23], PIN[31], GIN[31], GIN[39], POUT[23], GOUT[39] ); smblock2 d340 (PIN[24], PIN[32], GIN[32], GIN[40], POUT[24], GOUT[40] ); smblock2 d341 (PIN[25], PIN[33], GIN[33], GIN[41], POUT[25], GOUT[41] ); smblock2 d342 (PIN[26], PIN[34], GIN[34], GIN[42], POUT[26], GOUT[42] ); smblock2 d343 (PIN[27], PIN[35], GIN[35], GIN[43], POUT[27], GOUT[43] ); smblock2 d344 (PIN[28], PIN[36], GIN[36], GIN[44], POUT[28], GOUT[44] ); smblock2 d345 (PIN[29], PIN[37], GIN[37], GIN[45], POUT[29], GOUT[45] ); smblock2 d346 (PIN[30], PIN[38], GIN[38], GIN[46], POUT[30], GOUT[46] ); smblock2 d347 (PIN[31], PIN[39], GIN[39], GIN[47], POUT[31], GOUT[47] ); smblock2 d348 (PIN[32], PIN[40], GIN[40], GIN[48], POUT[32], GOUT[48] ); smblock2 d349 (PIN[33], PIN[41], GIN[41], GIN[49], POUT[33], GOUT[49] ); smblock2 d350 (PIN[34], PIN[42], GIN[42], GIN[50], POUT[34], GOUT[50] ); smblock2 d351 (PIN[35], PIN[43], GIN[43], GIN[51], POUT[35], GOUT[51] ); smblock2 d352 (PIN[36], PIN[44], GIN[44], GIN[52], POUT[36], GOUT[52] ); smblock2 d353 (PIN[37], PIN[45], GIN[45], GIN[53], POUT[37], GOUT[53] ); smblock2 d354 (PIN[38], PIN[46], GIN[46], GIN[54], POUT[38], GOUT[54] ); smblock2 d355 (PIN[39], PIN[47], GIN[47], GIN[55], POUT[39], GOUT[55] ); smblock2 d356 (PIN[40], PIN[48], GIN[48], GIN[56], POUT[40], GOUT[56] ); smblock2 d357 (PIN[41], PIN[49], GIN[49], GIN[57], POUT[41], GOUT[57] ); smblock2 d358 (PIN[42], PIN[50], GIN[50], GIN[58], POUT[42], GOUT[58] ); smblock2 d359 (PIN[43], PIN[51], GIN[51], GIN[59], POUT[43], GOUT[59] ); smblock2 d360 (PIN[44], PIN[52], GIN[52], GIN[60], POUT[44], GOUT[60] ); smblock2 d361 (PIN[45], PIN[53], GIN[53], GIN[61], POUT[45], GOUT[61] ); smblock2 d362 (PIN[46], PIN[54], GIN[54], GIN[62], POUT[46], GOUT[62] ); smblock2 d363 (PIN[47], PIN[55], GIN[55], GIN[63], POUT[47], GOUT[63] ); endmodule module smdblc_4_128 (PIN, GIN, POUT, GOUT); input [63:0] PIN; input [63:0] GIN; output [63:0] POUT; output [63:0] GOUT; sminvblock d10 (GIN[0], GOUT[0] ); sminvblock d11 (GIN[1], GOUT[1] ); sminvblock d12 (GIN[2], GOUT[2] ); sminvblock d13 (GIN[3], GOUT[3] ); sminvblock d14 (GIN[4], GOUT[4] ); sminvblock d15 (GIN[5], GOUT[5] ); sminvblock d16 (GIN[6], GOUT[6] ); sminvblock d17 (GIN[7], GOUT[7] ); sminvblock d18 (GIN[8], GOUT[8] ); sminvblock d19 (GIN[9], GOUT[9] ); sminvblock d110 (GIN[10], GOUT[10] ); sminvblock d111 (GIN[11], GOUT[11] ); sminvblock d112 (GIN[12], GOUT[12] ); sminvblock d113 (GIN[13], GOUT[13] ); sminvblock d114 (GIN[14], GOUT[14] ); sminvblock d115 (GIN[15], GOUT[15] ); smblock1a d216 (PIN[0], GIN[0], GIN[16], GOUT[16] ); smblock1a d217 (PIN[1], GIN[1], GIN[17], GOUT[17] ); smblock1a d218 (PIN[2], GIN[2], GIN[18], GOUT[18] ); smblock1a d219 (PIN[3], GIN[3], GIN[19], GOUT[19] ); smblock1a d220 (PIN[4], GIN[4], GIN[20], GOUT[20] ); smblock1a d221 (PIN[5], GIN[5], GIN[21], GOUT[21] ); smblock1a d222 (PIN[6], GIN[6], GIN[22], GOUT[22] ); smblock1a d223 (PIN[7], GIN[7], GIN[23], GOUT[23] ); smblock1a d224 (PIN[8], GIN[8], GIN[24], GOUT[24] ); smblock1a d225 (PIN[9], GIN[9], GIN[25], GOUT[25] ); smblock1a d226 (PIN[10], GIN[10], GIN[26], GOUT[26] ); smblock1a d227 (PIN[11], GIN[11], GIN[27], GOUT[27] ); smblock1a d228 (PIN[12], GIN[12], GIN[28], GOUT[28] ); smblock1a d229 (PIN[13], GIN[13], GIN[29], GOUT[29] ); smblock1a d230 (PIN[14], GIN[14], GIN[30], GOUT[30] ); smblock1a d231 (PIN[15], GIN[15], GIN[31], GOUT[31] ); smblock1 d332 (PIN[0], PIN[16], GIN[16], GIN[32], POUT[0], GOUT[32] ); smblock1 d333 (PIN[1], PIN[17], GIN[17], GIN[33], POUT[1], GOUT[33] ); smblock1 d334 (PIN[2], PIN[18], GIN[18], GIN[34], POUT[2], GOUT[34] ); smblock1 d335 (PIN[3], PIN[19], GIN[19], GIN[35], POUT[3], GOUT[35] ); smblock1 d336 (PIN[4], PIN[20], GIN[20], GIN[36], POUT[4], GOUT[36] ); smblock1 d337 (PIN[5], PIN[21], GIN[21], GIN[37], POUT[5], GOUT[37] ); smblock1 d338 (PIN[6], PIN[22], GIN[22], GIN[38], POUT[6], GOUT[38] ); smblock1 d339 (PIN[7], PIN[23], GIN[23], GIN[39], POUT[7], GOUT[39] ); smblock1 d340 (PIN[8], PIN[24], GIN[24], GIN[40], POUT[8], GOUT[40] ); smblock1 d341 (PIN[9], PIN[25], GIN[25], GIN[41], POUT[9], GOUT[41] ); smblock1 d342 (PIN[10], PIN[26], GIN[26], GIN[42], POUT[10], GOUT[42] ); smblock1 d343 (PIN[11], PIN[27], GIN[27], GIN[43], POUT[11], GOUT[43] ); smblock1 d344 (PIN[12], PIN[28], GIN[28], GIN[44], POUT[12], GOUT[44] ); smblock1 d345 (PIN[13], PIN[29], GIN[29], GIN[45], POUT[13], GOUT[45] ); smblock1 d346 (PIN[14], PIN[30], GIN[30], GIN[46], POUT[14], GOUT[46] ); smblock1 d347 (PIN[15], PIN[31], GIN[31], GIN[47], POUT[15], GOUT[47] ); smblock1 d348 (PIN[16], PIN[32], GIN[32], GIN[48], POUT[16], GOUT[48] ); smblock1 d349 (PIN[17], PIN[33], GIN[33], GIN[49], POUT[17], GOUT[49] ); smblock1 d350 (PIN[18], PIN[34], GIN[34], GIN[50], POUT[18], GOUT[50] ); smblock1 d351 (PIN[19], PIN[35], GIN[35], GIN[51], POUT[19], GOUT[51] ); smblock1 d352 (PIN[20], PIN[36], GIN[36], GIN[52], POUT[20], GOUT[52] ); smblock1 d353 (PIN[21], PIN[37], GIN[37], GIN[53], POUT[21], GOUT[53] ); smblock1 d354 (PIN[22], PIN[38], GIN[38], GIN[54], POUT[22], GOUT[54] ); smblock1 d355 (PIN[23], PIN[39], GIN[39], GIN[55], POUT[23], GOUT[55] ); smblock1 d356 (PIN[24], PIN[40], GIN[40], GIN[56], POUT[24], GOUT[56] ); smblock1 d357 (PIN[25], PIN[41], GIN[41], GIN[57], POUT[25], GOUT[57] ); smblock1 d358 (PIN[26], PIN[42], GIN[42], GIN[58], POUT[26], GOUT[58] ); smblock1 d359 (PIN[27], PIN[43], GIN[43], GIN[59], POUT[27], GOUT[59] ); smblock1 d360 (PIN[28], PIN[44], GIN[44], GIN[60], POUT[28], GOUT[60] ); smblock1 d361 (PIN[29], PIN[45], GIN[45], GIN[61], POUT[29], GOUT[61] ); smblock1 d362 (PIN[30], PIN[46], GIN[46], GIN[62], POUT[30], GOUT[62] ); smblock1 d363 (PIN[31], PIN[47], GIN[47], GIN[63], POUT[31], GOUT[63] ); endmodule module smxorstage_128 (A, B, PBIT, CARRY, SUM); input [63:0] A; input [63:0] B; input PBIT; input [63:0] CARRY; output [63:0] SUM; smxxor1 d20 (A[0], B[0], CARRY[0], SUM[0] ); smxxor1 d21 (A[1], B[1], CARRY[1], SUM[1] ); smxxor1 d22 (A[2], B[2], CARRY[2], SUM[2] ); smxxor1 d23 (A[3], B[3], CARRY[3], SUM[3] ); smxxor1 d24 (A[4], B[4], CARRY[4], SUM[4] ); smxxor1 d25 (A[5], B[5], CARRY[5], SUM[5] ); smxxor1 d26 (A[6], B[6], CARRY[6], SUM[6] ); smxxor1 d27 (A[7], B[7], CARRY[7], SUM[7] ); smxxor1 d28 (A[8], B[8], CARRY[8], SUM[8] ); smxxor1 d29 (A[9], B[9], CARRY[9], SUM[9] ); smxxor1 d210 (A[10], B[10], CARRY[10], SUM[10] ); smxxor1 d211 (A[11], B[11], CARRY[11], SUM[11] ); smxxor1 d212 (A[12], B[12], CARRY[12], SUM[12] ); smxxor1 d213 (A[13], B[13], CARRY[13], SUM[13] ); smxxor1 d214 (A[14], B[14], CARRY[14], SUM[14] ); smxxor1 d215 (A[15], B[15], CARRY[15], SUM[15] ); smxxor1 d216 (A[16], B[16], CARRY[16], SUM[16] ); smxxor1 d217 (A[17], B[17], CARRY[17], SUM[17] ); smxxor1 d218 (A[18], B[18], CARRY[18], SUM[18] ); smxxor1 d219 (A[19], B[19], CARRY[19], SUM[19] ); smxxor1 d220 (A[20], B[20], CARRY[20], SUM[20] ); smxxor1 d221 (A[21], B[21], CARRY[21], SUM[21] ); smxxor1 d222 (A[22], B[22], CARRY[22], SUM[22] ); smxxor1 d223 (A[23], B[23], CARRY[23], SUM[23] ); smxxor1 d224 (A[24], B[24], CARRY[24], SUM[24] ); smxxor1 d225 (A[25], B[25], CARRY[25], SUM[25] ); smxxor1 d226 (A[26], B[26], CARRY[26], SUM[26] ); smxxor1 d227 (A[27], B[27], CARRY[27], SUM[27] ); smxxor1 d228 (A[28], B[28], CARRY[28], SUM[28] ); smxxor1 d229 (A[29], B[29], CARRY[29], SUM[29] ); smxxor1 d230 (A[30], B[30], CARRY[30], SUM[30] ); smxxor1 d231 (A[31], B[31], CARRY[31], SUM[31] ); smxxor1 d232 (A[32], B[32], CARRY[32], SUM[32] ); smxxor1 d233 (A[33], B[33], CARRY[33], SUM[33] ); smxxor1 d234 (A[34], B[34], CARRY[34], SUM[34] ); smxxor1 d235 (A[35], B[35], CARRY[35], SUM[35] ); smxxor1 d236 (A[36], B[36], CARRY[36], SUM[36] ); smxxor1 d237 (A[37], B[37], CARRY[37], SUM[37] ); smxxor1 d238 (A[38], B[38], CARRY[38], SUM[38] ); smxxor1 d239 (A[39], B[39], CARRY[39], SUM[39] ); smxxor1 d240 (A[40], B[40], CARRY[40], SUM[40] ); smxxor1 d241 (A[41], B[41], CARRY[41], SUM[41] ); smxxor1 d242 (A[42], B[42], CARRY[42], SUM[42] ); smxxor1 d243 (A[43], B[43], CARRY[43], SUM[43] ); smxxor1 d244 (A[44], B[44], CARRY[44], SUM[44] ); smxxor1 d245 (A[45], B[45], CARRY[45], SUM[45] ); smxxor1 d246 (A[46], B[46], CARRY[46], SUM[46] ); smxxor1 d247 (A[47], B[47], CARRY[47], SUM[47] ); smxxor1 d248 (A[48], B[48], CARRY[48], SUM[48] ); smxxor1 d249 (A[49], B[49], CARRY[49], SUM[49] ); smxxor1 d250 (A[50], B[50], CARRY[50], SUM[50] ); smxxor1 d251 (A[51], B[51], CARRY[51], SUM[51] ); smxxor1 d252 (A[52], B[52], CARRY[52], SUM[52] ); smxxor1 d253 (A[53], B[53], CARRY[53], SUM[53] ); smxxor1 d254 (A[54], B[54], CARRY[54], SUM[54] ); smxxor1 d255 (A[55], B[55], CARRY[55], SUM[55] ); smxxor1 d256 (A[56], B[56], CARRY[56], SUM[56] ); smxxor1 d257 (A[57], B[57], CARRY[57], SUM[57] ); smxxor1 d258 (A[58], B[58], CARRY[58], SUM[58] ); smxxor1 d259 (A[59], B[59], CARRY[59], SUM[59] ); smxxor1 d260 (A[60], B[60], CARRY[60], SUM[60] ); smxxor1 d261 (A[61], B[61], CARRY[61], SUM[61] ); smxxor1 d262 (A[62], B[62], CARRY[62], SUM[62] ); smxxor1 d263 (A[63], B[63], CARRY[63], SUM[63] ); endmodule module smdblc_5_128 (PIN, GIN, POUT, GOUT); input [63:0] PIN; input [63:0] GIN; output [63:0] POUT; output [63:0] GOUT; sminvblock d10 (GIN[0], GOUT[0] ); sminvblock d11 (GIN[1], GOUT[1] ); sminvblock d12 (GIN[2], GOUT[2] ); sminvblock d13 (GIN[3], GOUT[3] ); sminvblock d14 (GIN[4], GOUT[4] ); sminvblock d15 (GIN[5], GOUT[5] ); sminvblock d16 (GIN[6], GOUT[6] ); sminvblock d17 (GIN[7], GOUT[7] ); sminvblock d18 (GIN[8], GOUT[8] ); sminvblock d19 (GIN[9], GOUT[9] ); sminvblock d110 (GIN[10], GOUT[10] ); sminvblock d111 (GIN[11], GOUT[11] ); sminvblock d112 (GIN[12], GOUT[12] ); sminvblock d113 (GIN[13], GOUT[13] ); sminvblock d114 (GIN[14], GOUT[14] ); sminvblock d115 (GIN[15], GOUT[15] ); sminvblock d116 (GIN[16], GOUT[16] ); sminvblock d117 (GIN[17], GOUT[17] ); sminvblock d118 (GIN[18], GOUT[18] ); sminvblock d119 (GIN[19], GOUT[19] ); sminvblock d120 (GIN[20], GOUT[20] ); sminvblock d121 (GIN[21], GOUT[21] ); sminvblock d122 (GIN[22], GOUT[22] ); sminvblock d123 (GIN[23], GOUT[23] ); sminvblock d124 (GIN[24], GOUT[24] ); sminvblock d125 (GIN[25], GOUT[25] ); sminvblock d126 (GIN[26], GOUT[26] ); sminvblock d127 (GIN[27], GOUT[27] ); sminvblock d128 (GIN[28], GOUT[28] ); sminvblock d129 (GIN[29], GOUT[29] ); sminvblock d130 (GIN[30], GOUT[30] ); sminvblock d131 (GIN[31], GOUT[31] ); smblock2a d232 (PIN[0], GIN[0], GIN[32], GOUT[32] ); smblock2a d233 (PIN[1], GIN[1], GIN[33], GOUT[33] ); smblock2a d234 (PIN[2], GIN[2], GIN[34], GOUT[34] ); smblock2a d235 (PIN[3], GIN[3], GIN[35], GOUT[35] ); smblock2a d236 (PIN[4], GIN[4], GIN[36], GOUT[36] ); smblock2a d237 (PIN[5], GIN[5], GIN[37], GOUT[37] ); smblock2a d238 (PIN[6], GIN[6], GIN[38], GOUT[38] ); smblock2a d239 (PIN[7], GIN[7], GIN[39], GOUT[39] ); smblock2a d240 (PIN[8], GIN[8], GIN[40], GOUT[40] ); smblock2a d241 (PIN[9], GIN[9], GIN[41], GOUT[41] ); smblock2a d242 (PIN[10], GIN[10], GIN[42], GOUT[42] ); smblock2a d243 (PIN[11], GIN[11], GIN[43], GOUT[43] ); smblock2a d244 (PIN[12], GIN[12], GIN[44], GOUT[44] ); smblock2a d245 (PIN[13], GIN[13], GIN[45], GOUT[45] ); smblock2a d246 (PIN[14], GIN[14], GIN[46], GOUT[46] ); smblock2a d247 (PIN[15], GIN[15], GIN[47], GOUT[47] ); smblock2a d248 (PIN[16], GIN[16], GIN[48], GOUT[48] ); smblock2a d249 (PIN[17], GIN[17], GIN[49], GOUT[49] ); smblock2a d250 (PIN[18], GIN[18], GIN[50], GOUT[50] ); smblock2a d251 (PIN[19], GIN[19], GIN[51], GOUT[51] ); smblock2a d252 (PIN[20], GIN[20], GIN[52], GOUT[52] ); smblock2a d253 (PIN[21], GIN[21], GIN[53], GOUT[53] ); smblock2a d254 (PIN[22], GIN[22], GIN[54], GOUT[54] ); smblock2a d255 (PIN[23], GIN[23], GIN[55], GOUT[55] ); smblock2a d256 (PIN[24], GIN[24], GIN[56], GOUT[56] ); smblock2a d257 (PIN[25], GIN[25], GIN[57], GOUT[57] ); smblock2a d258 (PIN[26], GIN[26], GIN[58], GOUT[58] ); smblock2a d259 (PIN[27], GIN[27], GIN[59], GOUT[59] ); smblock2a d260 (PIN[28], GIN[28], GIN[60], GOUT[60] ); smblock2a d261 (PIN[29], GIN[29], GIN[61], GOUT[61] ); smblock2a d262 (PIN[30], GIN[30], GIN[62], GOUT[62] ); smblock2a d263 (PIN[31], GIN[31], GIN[63], GOUT[63] ); endmodule module smdblc_6_128 (PIN, GIN, POUT, GOUT); input [63:0] PIN; input [63:0] GIN; output [0:0] POUT; output [63:0] GOUT; assign GOUT[63:0] = GIN[63:0]; endmodule module smboothcoder_34_34 (OPA, OPB, SUMMAND); input [33:0] OPA; input [33:0] OPB; output [628:0] SUMMAND; wire [33:0] OPA_; wire [67:0] INT_MULTIPLIER; wire LOGIC_ONE, LOGIC_ZERO; assign LOGIC_ONE = 1'b1; assign LOGIC_ZERO = 1'b0; smdecoder dDEC0 (.INA (LOGIC_ZERO), .INB (OPB[0]), .INC (OPB[1]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]) ); assign OPA_ = ~ OPA; smpp_low dPPL0 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[0]) ); smr_gate dRGATE0 (.INA (LOGIC_ZERO), .INB (OPB[0]), .INC (OPB[1]), .PPBIT (SUMMAND[1]) ); smpp_middle dPPM0 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[2]) ); smpp_middle dPPM1 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[3]) ); smpp_middle dPPM2 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[6]) ); smpp_middle dPPM3 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[8]) ); smpp_middle dPPM4 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[12]) ); smpp_middle dPPM5 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[15]) ); smpp_middle dPPM6 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[20]) ); smpp_middle dPPM7 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[24]) ); smpp_middle dPPM8 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[30]) ); smpp_middle dPPM9 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[35]) ); smpp_middle dPPM10 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[42]) ); smpp_middle dPPM11 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[48]) ); smpp_middle dPPM12 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[56]) ); smpp_middle dPPM13 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[63]) ); smpp_middle dPPM14 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[72]) ); smpp_middle dPPM15 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[80]) ); smpp_middle dPPM16 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[90]) ); smpp_middle dPPM17 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[99]) ); smpp_middle dPPM18 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[110]) ); smpp_middle dPPM19 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[120]) ); smpp_middle dPPM20 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[132]) ); smpp_middle dPPM21 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[143]) ); smpp_middle dPPM22 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[156]) ); smpp_middle dPPM23 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[168]) ); smpp_middle dPPM24 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[182]) ); smpp_middle dPPM25 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[195]) ); smpp_middle dPPM26 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[210]) ); smpp_middle dPPM27 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[224]) ); smpp_middle dPPM28 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[240]) ); smpp_middle dPPM29 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[255]) ); smpp_middle dPPM30 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[272]) ); smpp_middle dPPM31 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[288]) ); smpp_middle dPPM32 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[306]) ); smpp_high dPPH0 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[323]) ); assign SUMMAND[324] = 1'b1; smdecoder dDEC1 (.INA (OPB[1]), .INB (OPB[2]), .INC (OPB[3]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]) ); smpp_low dPPL1 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[4]) ); smr_gate dRGATE1 (.INA (OPB[1]), .INB (OPB[2]), .INC (OPB[3]), .PPBIT (SUMMAND[5]) ); smpp_middle dPPM33 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[7]) ); smpp_middle dPPM34 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[9]) ); smpp_middle dPPM35 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[13]) ); smpp_middle dPPM36 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[16]) ); smpp_middle dPPM37 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[21]) ); smpp_middle dPPM38 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[25]) ); smpp_middle dPPM39 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[31]) ); smpp_middle dPPM40 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[36]) ); smpp_middle dPPM41 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[43]) ); smpp_middle dPPM42 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[49]) ); smpp_middle dPPM43 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[57]) ); smpp_middle dPPM44 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[64]) ); smpp_middle dPPM45 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[73]) ); smpp_middle dPPM46 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[81]) ); smpp_middle dPPM47 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[91]) ); smpp_middle dPPM48 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[100]) ); smpp_middle dPPM49 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[111]) ); smpp_middle dPPM50 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[121]) ); smpp_middle dPPM51 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[133]) ); smpp_middle dPPM52 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[144]) ); smpp_middle dPPM53 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[157]) ); smpp_middle dPPM54 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[169]) ); smpp_middle dPPM55 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[183]) ); smpp_middle dPPM56 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[196]) ); smpp_middle dPPM57 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[211]) ); smpp_middle dPPM58 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[225]) ); smpp_middle dPPM59 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[241]) ); smpp_middle dPPM60 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[256]) ); smpp_middle dPPM61 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[273]) ); smpp_middle dPPM62 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[289]) ); smpp_middle dPPM63 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[307]) ); smpp_middle dPPM64 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[325]) ); smpp_middle dPPM65 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[341]) ); assign SUMMAND[342] = LOGIC_ONE; smpp_high dPPH1 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[358]) ); smdecoder dDEC2 (.INA (OPB[3]), .INB (OPB[4]), .INC (OPB[5]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]) ); smpp_low dPPL2 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[10]) ); smr_gate dRGATE2 (.INA (OPB[3]), .INB (OPB[4]), .INC (OPB[5]), .PPBIT (SUMMAND[11]) ); smpp_middle dPPM66 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[14]) ); smpp_middle dPPM67 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[17]) ); smpp_middle dPPM68 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[22]) ); smpp_middle dPPM69 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[26]) ); smpp_middle dPPM70 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[32]) ); smpp_middle dPPM71 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[37]) ); smpp_middle dPPM72 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[44]) ); smpp_middle dPPM73 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[50]) ); smpp_middle dPPM74 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[58]) ); smpp_middle dPPM75 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[65]) ); smpp_middle dPPM76 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[74]) ); smpp_middle dPPM77 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[82]) ); smpp_middle dPPM78 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[92]) ); smpp_middle dPPM79 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[101]) ); smpp_middle dPPM80 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[112]) ); smpp_middle dPPM81 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[122]) ); smpp_middle dPPM82 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[134]) ); smpp_middle dPPM83 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[145]) ); smpp_middle dPPM84 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[158]) ); smpp_middle dPPM85 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[170]) ); smpp_middle dPPM86 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[184]) ); smpp_middle dPPM87 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[197]) ); smpp_middle dPPM88 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[212]) ); smpp_middle dPPM89 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[226]) ); smpp_middle dPPM90 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[242]) ); smpp_middle dPPM91 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[257]) ); smpp_middle dPPM92 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[274]) ); smpp_middle dPPM93 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[290]) ); smpp_middle dPPM94 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[308]) ); smpp_middle dPPM95 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[326]) ); smpp_middle dPPM96 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[343]) ); smpp_middle dPPM97 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[359]) ); smpp_middle dPPM98 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[374]) ); assign SUMMAND[375] = LOGIC_ONE; smpp_high dPPH2 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[390]) ); smdecoder dDEC3 (.INA (OPB[5]), .INB (OPB[6]), .INC (OPB[7]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]) ); smpp_low dPPL3 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[18]) ); smr_gate dRGATE3 (.INA (OPB[5]), .INB (OPB[6]), .INC (OPB[7]), .PPBIT (SUMMAND[19]) ); smpp_middle dPPM99 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[23]) ); smpp_middle dPPM100 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[27]) ); smpp_middle dPPM101 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[33]) ); smpp_middle dPPM102 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[38]) ); smpp_middle dPPM103 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[45]) ); smpp_middle dPPM104 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[51]) ); smpp_middle dPPM105 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[59]) ); smpp_middle dPPM106 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[66]) ); smpp_middle dPPM107 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[75]) ); smpp_middle dPPM108 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[83]) ); smpp_middle dPPM109 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[93]) ); smpp_middle dPPM110 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[102]) ); smpp_middle dPPM111 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[113]) ); smpp_middle dPPM112 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[123]) ); smpp_middle dPPM113 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[135]) ); smpp_middle dPPM114 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[146]) ); smpp_middle dPPM115 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[159]) ); smpp_middle dPPM116 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[171]) ); smpp_middle dPPM117 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[185]) ); smpp_middle dPPM118 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[198]) ); smpp_middle dPPM119 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[213]) ); smpp_middle dPPM120 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[227]) ); smpp_middle dPPM121 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[243]) ); smpp_middle dPPM122 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[258]) ); smpp_middle dPPM123 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[275]) ); smpp_middle dPPM124 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[291]) ); smpp_middle dPPM125 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[309]) ); smpp_middle dPPM126 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[327]) ); smpp_middle dPPM127 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[344]) ); smpp_middle dPPM128 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[360]) ); smpp_middle dPPM129 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[376]) ); smpp_middle dPPM130 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[391]) ); smpp_middle dPPM131 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[405]) ); assign SUMMAND[406] = LOGIC_ONE; smpp_high dPPH3 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[420]) ); smdecoder dDEC4 (.INA (OPB[7]), .INB (OPB[8]), .INC (OPB[9]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]) ); smpp_low dPPL4 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[28]) ); smr_gate dRGATE4 (.INA (OPB[7]), .INB (OPB[8]), .INC (OPB[9]), .PPBIT (SUMMAND[29]) ); smpp_middle dPPM132 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[34]) ); smpp_middle dPPM133 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[39]) ); smpp_middle dPPM134 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[46]) ); smpp_middle dPPM135 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[52]) ); smpp_middle dPPM136 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[60]) ); smpp_middle dPPM137 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[67]) ); smpp_middle dPPM138 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[76]) ); smpp_middle dPPM139 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[84]) ); smpp_middle dPPM140 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[94]) ); smpp_middle dPPM141 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[103]) ); smpp_middle dPPM142 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[114]) ); smpp_middle dPPM143 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[124]) ); smpp_middle dPPM144 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[136]) ); smpp_middle dPPM145 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[147]) ); smpp_middle dPPM146 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[160]) ); smpp_middle dPPM147 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[172]) ); smpp_middle dPPM148 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[186]) ); smpp_middle dPPM149 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[199]) ); smpp_middle dPPM150 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[214]) ); smpp_middle dPPM151 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[228]) ); smpp_middle dPPM152 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[244]) ); smpp_middle dPPM153 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[259]) ); smpp_middle dPPM154 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[276]) ); smpp_middle dPPM155 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[292]) ); smpp_middle dPPM156 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[310]) ); smpp_middle dPPM157 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[328]) ); smpp_middle dPPM158 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[345]) ); smpp_middle dPPM159 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[361]) ); smpp_middle dPPM160 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[377]) ); smpp_middle dPPM161 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[392]) ); smpp_middle dPPM162 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[407]) ); smpp_middle dPPM163 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[421]) ); smpp_middle dPPM164 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[434]) ); assign SUMMAND[435] = LOGIC_ONE; smpp_high dPPH4 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[448]) ); smdecoder dDEC5 (.INA (OPB[9]), .INB (OPB[10]), .INC (OPB[11]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]) ); smpp_low dPPL5 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[40]) ); smr_gate dRGATE5 (.INA (OPB[9]), .INB (OPB[10]), .INC (OPB[11]), .PPBIT (SUMMAND[41]) ); smpp_middle dPPM165 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[47]) ); smpp_middle dPPM166 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[53]) ); smpp_middle dPPM167 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[61]) ); smpp_middle dPPM168 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[68]) ); smpp_middle dPPM169 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[77]) ); smpp_middle dPPM170 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[85]) ); smpp_middle dPPM171 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[95]) ); smpp_middle dPPM172 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[104]) ); smpp_middle dPPM173 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[115]) ); smpp_middle dPPM174 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[125]) ); smpp_middle dPPM175 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[137]) ); smpp_middle dPPM176 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[148]) ); smpp_middle dPPM177 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[161]) ); smpp_middle dPPM178 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[173]) ); smpp_middle dPPM179 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[187]) ); smpp_middle dPPM180 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[200]) ); smpp_middle dPPM181 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[215]) ); smpp_middle dPPM182 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[229]) ); smpp_middle dPPM183 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[245]) ); smpp_middle dPPM184 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[260]) ); smpp_middle dPPM185 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[277]) ); smpp_middle dPPM186 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[293]) ); smpp_middle dPPM187 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[311]) ); smpp_middle dPPM188 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[329]) ); smpp_middle dPPM189 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[346]) ); smpp_middle dPPM190 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[362]) ); smpp_middle dPPM191 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[378]) ); smpp_middle dPPM192 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[393]) ); smpp_middle dPPM193 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[408]) ); smpp_middle dPPM194 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[422]) ); smpp_middle dPPM195 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[436]) ); smpp_middle dPPM196 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[449]) ); smpp_middle dPPM197 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[461]) ); assign SUMMAND[462] = LOGIC_ONE; smpp_high dPPH5 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[474]) ); smdecoder dDEC6 (.INA (OPB[11]), .INB (OPB[12]), .INC (OPB[13]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]) ); smpp_low dPPL6 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[54]) ); smr_gate dRGATE6 (.INA (OPB[11]), .INB (OPB[12]), .INC (OPB[13]), .PPBIT (SUMMAND[55]) ); smpp_middle dPPM198 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[62]) ); smpp_middle dPPM199 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[69]) ); smpp_middle dPPM200 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[78]) ); smpp_middle dPPM201 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[86]) ); smpp_middle dPPM202 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[96]) ); smpp_middle dPPM203 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[105]) ); smpp_middle dPPM204 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[116]) ); smpp_middle dPPM205 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[126]) ); smpp_middle dPPM206 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[138]) ); smpp_middle dPPM207 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[149]) ); smpp_middle dPPM208 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[162]) ); smpp_middle dPPM209 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[174]) ); smpp_middle dPPM210 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[188]) ); smpp_middle dPPM211 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[201]) ); smpp_middle dPPM212 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[216]) ); smpp_middle dPPM213 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[230]) ); smpp_middle dPPM214 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[246]) ); smpp_middle dPPM215 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[261]) ); smpp_middle dPPM216 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[278]) ); smpp_middle dPPM217 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[294]) ); smpp_middle dPPM218 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[312]) ); smpp_middle dPPM219 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[330]) ); smpp_middle dPPM220 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[347]) ); smpp_middle dPPM221 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[363]) ); smpp_middle dPPM222 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[379]) ); smpp_middle dPPM223 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[394]) ); smpp_middle dPPM224 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[409]) ); smpp_middle dPPM225 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[423]) ); smpp_middle dPPM226 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[437]) ); smpp_middle dPPM227 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[450]) ); smpp_middle dPPM228 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[463]) ); smpp_middle dPPM229 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[475]) ); smpp_middle dPPM230 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[486]) ); assign SUMMAND[487] = LOGIC_ONE; smpp_high dPPH6 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[498]) ); smdecoder dDEC7 (.INA (OPB[13]), .INB (OPB[14]), .INC (OPB[15]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]) ); smpp_low dPPL7 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[70]) ); smr_gate dRGATE7 (.INA (OPB[13]), .INB (OPB[14]), .INC (OPB[15]), .PPBIT (SUMMAND[71]) ); smpp_middle dPPM231 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[79]) ); smpp_middle dPPM232 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[87]) ); smpp_middle dPPM233 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[97]) ); smpp_middle dPPM234 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[106]) ); smpp_middle dPPM235 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[117]) ); smpp_middle dPPM236 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[127]) ); smpp_middle dPPM237 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[139]) ); smpp_middle dPPM238 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[150]) ); smpp_middle dPPM239 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[163]) ); smpp_middle dPPM240 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[175]) ); smpp_middle dPPM241 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[189]) ); smpp_middle dPPM242 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[202]) ); smpp_middle dPPM243 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[217]) ); smpp_middle dPPM244 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[231]) ); smpp_middle dPPM245 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[247]) ); smpp_middle dPPM246 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[262]) ); smpp_middle dPPM247 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[279]) ); smpp_middle dPPM248 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[295]) ); smpp_middle dPPM249 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[313]) ); smpp_middle dPPM250 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[331]) ); smpp_middle dPPM251 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[348]) ); smpp_middle dPPM252 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[364]) ); smpp_middle dPPM253 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[380]) ); smpp_middle dPPM254 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[395]) ); smpp_middle dPPM255 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[410]) ); smpp_middle dPPM256 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[424]) ); smpp_middle dPPM257 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[438]) ); smpp_middle dPPM258 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[451]) ); smpp_middle dPPM259 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[464]) ); smpp_middle dPPM260 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[476]) ); smpp_middle dPPM261 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[488]) ); smpp_middle dPPM262 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[499]) ); smpp_middle dPPM263 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[509]) ); assign SUMMAND[510] = LOGIC_ONE; smpp_high dPPH7 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[520]) ); smdecoder dDEC8 (.INA (OPB[15]), .INB (OPB[16]), .INC (OPB[17]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]) ); smpp_low dPPL8 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[88]) ); smr_gate dRGATE8 (.INA (OPB[15]), .INB (OPB[16]), .INC (OPB[17]), .PPBIT (SUMMAND[89]) ); smpp_middle dPPM264 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[98]) ); smpp_middle dPPM265 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[107]) ); smpp_middle dPPM266 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[118]) ); smpp_middle dPPM267 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[128]) ); smpp_middle dPPM268 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[140]) ); smpp_middle dPPM269 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[151]) ); smpp_middle dPPM270 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[164]) ); smpp_middle dPPM271 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[176]) ); smpp_middle dPPM272 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[190]) ); smpp_middle dPPM273 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[203]) ); smpp_middle dPPM274 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[218]) ); smpp_middle dPPM275 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[232]) ); smpp_middle dPPM276 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[248]) ); smpp_middle dPPM277 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[263]) ); smpp_middle dPPM278 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[280]) ); smpp_middle dPPM279 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[296]) ); smpp_middle dPPM280 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[314]) ); smpp_middle dPPM281 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[332]) ); smpp_middle dPPM282 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[349]) ); smpp_middle dPPM283 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[365]) ); smpp_middle dPPM284 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[381]) ); smpp_middle dPPM285 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[396]) ); smpp_middle dPPM286 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[411]) ); smpp_middle dPPM287 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[425]) ); smpp_middle dPPM288 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[439]) ); smpp_middle dPPM289 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[452]) ); smpp_middle dPPM290 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[465]) ); smpp_middle dPPM291 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[477]) ); smpp_middle dPPM292 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[489]) ); smpp_middle dPPM293 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[500]) ); smpp_middle dPPM294 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[511]) ); smpp_middle dPPM295 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[521]) ); smpp_middle dPPM296 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[530]) ); assign SUMMAND[531] = LOGIC_ONE; smpp_high dPPH8 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[540]) ); smdecoder dDEC9 (.INA (OPB[17]), .INB (OPB[18]), .INC (OPB[19]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]) ); smpp_low dPPL9 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[108]) ); smr_gate dRGATE9 (.INA (OPB[17]), .INB (OPB[18]), .INC (OPB[19]), .PPBIT (SUMMAND[109]) ); smpp_middle dPPM297 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[119]) ); smpp_middle dPPM298 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[129]) ); smpp_middle dPPM299 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[141]) ); smpp_middle dPPM300 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[152]) ); smpp_middle dPPM301 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[165]) ); smpp_middle dPPM302 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[177]) ); smpp_middle dPPM303 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[191]) ); smpp_middle dPPM304 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[204]) ); smpp_middle dPPM305 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[219]) ); smpp_middle dPPM306 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[233]) ); smpp_middle dPPM307 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[249]) ); smpp_middle dPPM308 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[264]) ); smpp_middle dPPM309 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[281]) ); smpp_middle dPPM310 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[297]) ); smpp_middle dPPM311 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[315]) ); smpp_middle dPPM312 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[333]) ); smpp_middle dPPM313 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[350]) ); smpp_middle dPPM314 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[366]) ); smpp_middle dPPM315 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[382]) ); smpp_middle dPPM316 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[397]) ); smpp_middle dPPM317 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[412]) ); smpp_middle dPPM318 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[426]) ); smpp_middle dPPM319 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[440]) ); smpp_middle dPPM320 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[453]) ); smpp_middle dPPM321 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[466]) ); smpp_middle dPPM322 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[478]) ); smpp_middle dPPM323 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[490]) ); smpp_middle dPPM324 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[501]) ); smpp_middle dPPM325 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[512]) ); smpp_middle dPPM326 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[522]) ); smpp_middle dPPM327 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[532]) ); smpp_middle dPPM328 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[541]) ); smpp_middle dPPM329 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[549]) ); assign SUMMAND[550] = LOGIC_ONE; smpp_high dPPH9 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[558]) ); smdecoder dDEC10 (.INA (OPB[19]), .INB (OPB[20]), .INC (OPB[21]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]) ); smpp_low dPPL10 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[130]) ); smr_gate dRGATE10 (.INA (OPB[19]), .INB (OPB[20]), .INC (OPB[21]), .PPBIT (SUMMAND[131]) ); smpp_middle dPPM330 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[142]) ); smpp_middle dPPM331 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[153]) ); smpp_middle dPPM332 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[166]) ); smpp_middle dPPM333 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[178]) ); smpp_middle dPPM334 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[192]) ); smpp_middle dPPM335 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[205]) ); smpp_middle dPPM336 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[220]) ); smpp_middle dPPM337 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[234]) ); smpp_middle dPPM338 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[250]) ); smpp_middle dPPM339 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[265]) ); smpp_middle dPPM340 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[282]) ); smpp_middle dPPM341 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[298]) ); smpp_middle dPPM342 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[316]) ); smpp_middle dPPM343 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[334]) ); smpp_middle dPPM344 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[351]) ); smpp_middle dPPM345 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[367]) ); smpp_middle dPPM346 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[383]) ); smpp_middle dPPM347 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[398]) ); smpp_middle dPPM348 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[413]) ); smpp_middle dPPM349 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[427]) ); smpp_middle dPPM350 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[441]) ); smpp_middle dPPM351 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[454]) ); smpp_middle dPPM352 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[467]) ); smpp_middle dPPM353 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[479]) ); smpp_middle dPPM354 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[491]) ); smpp_middle dPPM355 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[502]) ); smpp_middle dPPM356 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[513]) ); smpp_middle dPPM357 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[523]) ); smpp_middle dPPM358 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[533]) ); smpp_middle dPPM359 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[542]) ); smpp_middle dPPM360 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[551]) ); smpp_middle dPPM361 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[559]) ); smpp_middle dPPM362 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[566]) ); assign SUMMAND[567] = LOGIC_ONE; smpp_high dPPH10 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[574]) ); smdecoder dDEC11 (.INA (OPB[21]), .INB (OPB[22]), .INC (OPB[23]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]) ); smpp_low dPPL11 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[154]) ); smr_gate dRGATE11 (.INA (OPB[21]), .INB (OPB[22]), .INC (OPB[23]), .PPBIT (SUMMAND[155]) ); smpp_middle dPPM363 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[167]) ); smpp_middle dPPM364 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[179]) ); smpp_middle dPPM365 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[193]) ); smpp_middle dPPM366 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[206]) ); smpp_middle dPPM367 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[221]) ); smpp_middle dPPM368 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[235]) ); smpp_middle dPPM369 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[251]) ); smpp_middle dPPM370 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[266]) ); smpp_middle dPPM371 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[283]) ); smpp_middle dPPM372 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[299]) ); smpp_middle dPPM373 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[317]) ); smpp_middle dPPM374 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[335]) ); smpp_middle dPPM375 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[352]) ); smpp_middle dPPM376 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[368]) ); smpp_middle dPPM377 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[384]) ); smpp_middle dPPM378 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[399]) ); smpp_middle dPPM379 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[414]) ); smpp_middle dPPM380 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[428]) ); smpp_middle dPPM381 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[442]) ); smpp_middle dPPM382 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[455]) ); smpp_middle dPPM383 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[468]) ); smpp_middle dPPM384 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[480]) ); smpp_middle dPPM385 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[492]) ); smpp_middle dPPM386 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[503]) ); smpp_middle dPPM387 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[514]) ); smpp_middle dPPM388 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[524]) ); smpp_middle dPPM389 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[534]) ); smpp_middle dPPM390 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[543]) ); smpp_middle dPPM391 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[552]) ); smpp_middle dPPM392 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[560]) ); smpp_middle dPPM393 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[568]) ); smpp_middle dPPM394 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[575]) ); smpp_middle dPPM395 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[581]) ); assign SUMMAND[582] = LOGIC_ONE; smpp_high dPPH11 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[588]) ); smdecoder dDEC12 (.INA (OPB[23]), .INB (OPB[24]), .INC (OPB[25]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]) ); smpp_low dPPL12 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[180]) ); smr_gate dRGATE12 (.INA (OPB[23]), .INB (OPB[24]), .INC (OPB[25]), .PPBIT (SUMMAND[181]) ); smpp_middle dPPM396 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[194]) ); smpp_middle dPPM397 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[207]) ); smpp_middle dPPM398 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[222]) ); smpp_middle dPPM399 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[236]) ); smpp_middle dPPM400 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[252]) ); smpp_middle dPPM401 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[267]) ); smpp_middle dPPM402 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[284]) ); smpp_middle dPPM403 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[300]) ); smpp_middle dPPM404 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[318]) ); smpp_middle dPPM405 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[336]) ); smpp_middle dPPM406 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[353]) ); smpp_middle dPPM407 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[369]) ); smpp_middle dPPM408 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[385]) ); smpp_middle dPPM409 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[400]) ); smpp_middle dPPM410 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[415]) ); smpp_middle dPPM411 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[429]) ); smpp_middle dPPM412 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[443]) ); smpp_middle dPPM413 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[456]) ); smpp_middle dPPM414 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[469]) ); smpp_middle dPPM415 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[481]) ); smpp_middle dPPM416 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[493]) ); smpp_middle dPPM417 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[504]) ); smpp_middle dPPM418 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[515]) ); smpp_middle dPPM419 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[525]) ); smpp_middle dPPM420 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[535]) ); smpp_middle dPPM421 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[544]) ); smpp_middle dPPM422 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[553]) ); smpp_middle dPPM423 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[561]) ); smpp_middle dPPM424 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[569]) ); smpp_middle dPPM425 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[576]) ); smpp_middle dPPM426 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[583]) ); smpp_middle dPPM427 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[589]) ); smpp_middle dPPM428 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[594]) ); assign SUMMAND[595] = LOGIC_ONE; smpp_high dPPH12 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[600]) ); smdecoder dDEC13 (.INA (OPB[25]), .INB (OPB[26]), .INC (OPB[27]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]) ); smpp_low dPPL13 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[208]) ); smr_gate dRGATE13 (.INA (OPB[25]), .INB (OPB[26]), .INC (OPB[27]), .PPBIT (SUMMAND[209]) ); smpp_middle dPPM429 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[223]) ); smpp_middle dPPM430 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[237]) ); smpp_middle dPPM431 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[253]) ); smpp_middle dPPM432 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[268]) ); smpp_middle dPPM433 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[285]) ); smpp_middle dPPM434 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[301]) ); smpp_middle dPPM435 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[319]) ); smpp_middle dPPM436 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[337]) ); smpp_middle dPPM437 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[354]) ); smpp_middle dPPM438 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[370]) ); smpp_middle dPPM439 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[386]) ); smpp_middle dPPM440 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[401]) ); smpp_middle dPPM441 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[416]) ); smpp_middle dPPM442 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[430]) ); smpp_middle dPPM443 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[444]) ); smpp_middle dPPM444 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[457]) ); smpp_middle dPPM445 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[470]) ); smpp_middle dPPM446 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[482]) ); smpp_middle dPPM447 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[494]) ); smpp_middle dPPM448 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[505]) ); smpp_middle dPPM449 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[516]) ); smpp_middle dPPM450 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[526]) ); smpp_middle dPPM451 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[536]) ); smpp_middle dPPM452 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[545]) ); smpp_middle dPPM453 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[554]) ); smpp_middle dPPM454 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[562]) ); smpp_middle dPPM455 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[570]) ); smpp_middle dPPM456 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[577]) ); smpp_middle dPPM457 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[584]) ); smpp_middle dPPM458 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[590]) ); smpp_middle dPPM459 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[596]) ); smpp_middle dPPM460 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[601]) ); smpp_middle dPPM461 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[605]) ); assign SUMMAND[606] = LOGIC_ONE; smpp_high dPPH13 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[610]) ); smdecoder dDEC14 (.INA (OPB[27]), .INB (OPB[28]), .INC (OPB[29]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]) ); smpp_low dPPL14 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[238]) ); smr_gate dRGATE14 (.INA (OPB[27]), .INB (OPB[28]), .INC (OPB[29]), .PPBIT (SUMMAND[239]) ); smpp_middle dPPM462 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[254]) ); smpp_middle dPPM463 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[269]) ); smpp_middle dPPM464 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[286]) ); smpp_middle dPPM465 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[302]) ); smpp_middle dPPM466 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[320]) ); smpp_middle dPPM467 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[338]) ); smpp_middle dPPM468 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[355]) ); smpp_middle dPPM469 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[371]) ); smpp_middle dPPM470 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[387]) ); smpp_middle dPPM471 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[402]) ); smpp_middle dPPM472 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[417]) ); smpp_middle dPPM473 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[431]) ); smpp_middle dPPM474 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[445]) ); smpp_middle dPPM475 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[458]) ); smpp_middle dPPM476 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[471]) ); smpp_middle dPPM477 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[483]) ); smpp_middle dPPM478 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[495]) ); smpp_middle dPPM479 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[506]) ); smpp_middle dPPM480 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[517]) ); smpp_middle dPPM481 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[527]) ); smpp_middle dPPM482 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[537]) ); smpp_middle dPPM483 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[546]) ); smpp_middle dPPM484 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[555]) ); smpp_middle dPPM485 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[563]) ); smpp_middle dPPM486 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[571]) ); smpp_middle dPPM487 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[578]) ); smpp_middle dPPM488 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[585]) ); smpp_middle dPPM489 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[591]) ); smpp_middle dPPM490 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[597]) ); smpp_middle dPPM491 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[602]) ); smpp_middle dPPM492 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[607]) ); smpp_middle dPPM493 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[611]) ); smpp_middle dPPM494 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[614]) ); assign SUMMAND[615] = LOGIC_ONE; smpp_high dPPH14 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[618]) ); smdecoder dDEC15 (.INA (OPB[29]), .INB (OPB[30]), .INC (OPB[31]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]) ); smpp_low dPPL15 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[270]) ); smr_gate dRGATE15 (.INA (OPB[29]), .INB (OPB[30]), .INC (OPB[31]), .PPBIT (SUMMAND[271]) ); smpp_middle dPPM495 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[287]) ); smpp_middle dPPM496 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[303]) ); smpp_middle dPPM497 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[321]) ); smpp_middle dPPM498 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[339]) ); smpp_middle dPPM499 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[356]) ); smpp_middle dPPM500 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[372]) ); smpp_middle dPPM501 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[388]) ); smpp_middle dPPM502 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[403]) ); smpp_middle dPPM503 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[418]) ); smpp_middle dPPM504 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[432]) ); smpp_middle dPPM505 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[446]) ); smpp_middle dPPM506 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[459]) ); smpp_middle dPPM507 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[472]) ); smpp_middle dPPM508 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[484]) ); smpp_middle dPPM509 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[496]) ); smpp_middle dPPM510 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[507]) ); smpp_middle dPPM511 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[518]) ); smpp_middle dPPM512 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[528]) ); smpp_middle dPPM513 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[538]) ); smpp_middle dPPM514 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[547]) ); smpp_middle dPPM515 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[556]) ); smpp_middle dPPM516 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[564]) ); smpp_middle dPPM517 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[572]) ); smpp_middle dPPM518 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[579]) ); smpp_middle dPPM519 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[586]) ); smpp_middle dPPM520 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[592]) ); smpp_middle dPPM521 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[598]) ); smpp_middle dPPM522 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[603]) ); smpp_middle dPPM523 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[608]) ); smpp_middle dPPM524 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[612]) ); smpp_middle dPPM525 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[616]) ); smpp_middle dPPM526 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[619]) ); smpp_middle dPPM527 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[621]) ); assign SUMMAND[622] = LOGIC_ONE; smpp_high dPPH15 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[624]) ); smdecoder dDEC16 (.INA (OPB[31]), .INB (OPB[32]), .INC (OPB[33]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]) ); smpp_low dPPL16 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[304]) ); smr_gate dRGATE16 (.INA (OPB[31]), .INB (OPB[32]), .INC (OPB[33]), .PPBIT (SUMMAND[305]) ); smpp_middle dPPM528 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[322]) ); smpp_middle dPPM529 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[340]) ); smpp_middle dPPM530 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[357]) ); smpp_middle dPPM531 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[373]) ); smpp_middle dPPM532 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[389]) ); smpp_middle dPPM533 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[404]) ); smpp_middle dPPM534 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[419]) ); smpp_middle dPPM535 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[433]) ); smpp_middle dPPM536 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[447]) ); smpp_middle dPPM537 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[460]) ); smpp_middle dPPM538 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[473]) ); smpp_middle dPPM539 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[485]) ); smpp_middle dPPM540 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[497]) ); smpp_middle dPPM541 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[508]) ); smpp_middle dPPM542 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[519]) ); smpp_middle dPPM543 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[529]) ); smpp_middle dPPM544 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[539]) ); smpp_middle dPPM545 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[548]) ); smpp_middle dPPM546 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[557]) ); smpp_middle dPPM547 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[565]) ); smpp_middle dPPM548 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[573]) ); smpp_middle dPPM549 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[580]) ); smpp_middle dPPM550 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[587]) ); smpp_middle dPPM551 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[593]) ); smpp_middle dPPM552 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[599]) ); smpp_middle dPPM553 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[604]) ); smpp_middle dPPM554 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[609]) ); smpp_middle dPPM555 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[613]) ); smpp_middle dPPM556 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[617]) ); smpp_middle dPPM557 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[620]) ); smpp_middle dPPM558 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[623]) ); smpp_middle dPPM559 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[625]) ); smpp_middle dPPM560 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[626]) ); assign SUMMAND[627] = LOGIC_ONE; smpp_high dPPH16 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[628]) ); endmodule // Simple cells module smpp_low (ONEPOS, ONENEG, TWONEG, INA, INB, PPBIT); input ONEPOS; input ONENEG; input TWONEG; input INA; input INB; output PPBIT; assign PPBIT = (ONEPOS & INA) | (ONENEG & INB) | TWONEG; endmodule module smpp_middle (ONEPOS, ONENEG, TWOPOS, TWONEG, INA, INB, INC, IND, PPBIT); input ONEPOS; input ONENEG; input TWOPOS; input TWONEG; input INA; input INB; input INC; input IND; output PPBIT; assign PPBIT = ~ ((~ (INA & TWOPOS)) & (~ (INB & TWONEG)) & (~ (INC & ONEPOS)) & (~ (IND & ONENEG))); endmodule module smpp_high (ONEPOS, ONENEG, TWOPOS, TWONEG, INA, INB, PPBIT); input ONEPOS; input ONENEG; input TWOPOS; input TWONEG; input INA; input INB; output PPBIT; assign PPBIT = ~ ((INA & ONEPOS) | (INB & ONENEG) | (INA & TWOPOS) | (INB & TWONEG)); endmodule module smr_gate (INA, INB, INC, PPBIT); input INA; input INB; input INC; output PPBIT; assign PPBIT = (~ (INA & INB)) & INC; endmodule module smdecoder (INA, INB, INC, TWOPOS, TWONEG, ONEPOS, ONENEG); input INA; input INB; input INC; output TWOPOS; output TWONEG; output ONEPOS; output ONENEG; assign TWOPOS = ~ (~ (INA & INB & (~ INC))); assign TWONEG = ~ (~ ((~ INA) & (~ INB) & INC)); assign ONEPOS = ((~ INA) & INB & (~ INC)) | ((~ INC) & (~ INB) & INA); assign ONENEG = (INA & (~ INB) & INC) | (INC & INB & (~ INA)); endmodule module smfulladder (DATA_A, DATA_B, DATA_C, SAVE, CARRY); input DATA_A; input DATA_B; input DATA_C; output SAVE; output CARRY; wire TMP; assign TMP = DATA_A ^ DATA_B; assign SAVE = TMP ^ DATA_C; assign CARRY = ~ ((~ (TMP & DATA_C)) & (~ (DATA_A & DATA_B))); endmodule module smhalfadder (DATA_A, DATA_B, SAVE, CARRY); input DATA_A; input DATA_B; output SAVE; output CARRY; assign SAVE = DATA_A ^ DATA_B; assign CARRY = DATA_A & DATA_B; endmodule module smffa ( input clk, input en_d1, input D, output reg Q ); always @ (posedge clk) begin Q <= D; end endmodule module smffb ( input clk, input en_d2, input D, output reg Q ); always @ (posedge clk) begin Q <= D; end endmodule module sminvblock (GIN, GOUT); input GIN; output GOUT; assign GOUT = ~ GIN; endmodule module smxxor1 (A, B, GIN, SUM); input A; input B; input GIN; output SUM; assign SUM = (~ (A ^ B)) ^ GIN; endmodule module smblock0 (A, B, POUT, GOUT); input A; input B; output POUT; output GOUT; assign POUT = ~ (A | B); assign GOUT = ~ (A & B); endmodule module smblock1 (PIN1, PIN2, GIN1, GIN2, POUT, GOUT); input PIN1; input PIN2; input GIN1; input GIN2; output POUT; output GOUT; assign POUT = ~ (PIN1 | PIN2); assign GOUT = ~ (GIN2 & (PIN2 | GIN1)); endmodule module smblock2 (PIN1, PIN2, GIN1, GIN2, POUT, GOUT); input PIN1; input PIN2; input GIN1; input GIN2; output POUT; output GOUT; assign POUT = ~ (PIN1 & PIN2); assign GOUT = ~ (GIN2 | (PIN2 & GIN1)); endmodule module smblock1a (PIN2, GIN1, GIN2, GOUT); input PIN2; input GIN1; input GIN2; output GOUT; assign GOUT = ~ (GIN2 & (PIN2 | GIN1)); endmodule module smblock2a (PIN2, GIN1, GIN2, GOUT); input PIN2; input GIN1; input GIN2; output GOUT; assign GOUT = ~ (GIN2 | (PIN2 & GIN1)); endmodule // verilog_format: on // Local Variables: // compile-command: "vlint --brief --nowarn=MULTMF,MODLNM t_math_wallace_mul.v" // End: verilator-5.044/test_regress/t/t_enum_param_class2.py0000755000542200017500000000073415125463617023400 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_class_assign_cond.py0000755000542200017500000000073415125463617023461 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_assert_synth.v0000644000542200017500000000521515125463617022344 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg a; initial a = 1'b1; reg b_fc; initial b_fc = 1'b0; reg b_pc; initial b_pc = 1'b0; reg b_oh; initial b_oh = 1'b0; reg b_oc; initial b_oc = 1'b0; wire a_l = ~a; wire b_oc_l = ~b_oc; // Note we must ensure that full, parallel, etc, only fire during // edges (not mid-cycle), and must provide a way to turn them off. // SystemVerilog provides: $asserton and $assertoff. // verilator lint_off CASEINCOMPLETE always @* begin // Note not all tools support directives on casez's `ifdef ATTRIBUTES case ({a,b_fc}) // synopsys full_case `else case ({a,b_fc}) `endif 2'b0_0: ; 2'b0_1: ; 2'b1_0: ; // Note no default endcase priority case ({a,b_fc}) 2'b0_0: ; 2'b0_1: ; 2'b1_0: ; // Note no default endcase end always @* begin `ifdef ATTRIBUTES case (1'b1) // synopsys full_case parallel_case `else `ifdef FAILING_FULL case (1'b1) // synopsys parallel_case `else case (1'b1) // synopsys parallel_full `endif `endif a: ; b_pc: ; endcase end `ifdef NOT_YET_VERILATOR // Unsupported // ambit synthesis one_hot "a, b_oh" // cadence one_cold "a_l, b_oc_l" `endif integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin a <= 1'b1; b_fc <= 1'b0; b_pc <= 1'b0; b_oh <= 1'b0; b_oc <= 1'b0; end if (cyc==2) begin a <= 1'b0; b_fc <= 1'b1; b_pc <= 1'b1; b_oh <= 1'b1; b_oc <= 1'b1; end if (cyc==3) begin a <= 1'b1; b_fc <= 1'b0; b_pc <= 1'b0; b_oh <= 1'b0; b_oc <= 1'b0; end if (cyc==4) begin `ifdef FAILING_FULL b_fc <= 1'b1; `endif `ifdef FAILING_PARALLEL b_pc <= 1'b1; `endif `ifdef FAILING_OH b_oh <= 1'b1; `endif `ifdef FAILING_OC b_oc <= 1'b1; `endif end if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end initial begin : test_info $info ("Start of $info test"); $info ("Middle of $info test"); $info ("End of $info test"); end : test_info endmodule verilator-5.044/test_regress/t/t_func_nansi_dup_bad.py0000755000542200017500000000076615125463617023613 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_concat_large_bad.v0000644000542200017500000000046715125463617023051 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2015 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; wire [32767:0] a = {32768{1'b1}}; initial begin $stop; end endmodule verilator-5.044/test_regress/t/t_semaphore_bad.py0000755000542200017500000000076315125463617022600 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_fork_delay.py0000755000542200017500000000077115125463617022125 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--timing"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_flag_hier1_bad.out0000644000542200017500000000043715125463617022770 0ustar mahmoudyfreeshell%Error: --hierarchical must not be set with --hierarchical-child or --hierarchical-block ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: --hierarchical-block must be set when --hierarchical-child is set %Error: Exiting due to verilator-5.044/test_regress/t/t_dynarray_init.v0000644000542200017500000000161015125463617022465 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t; int a1[] = '{12, 13}; int a2[] = {14, 15}; int a3[] = '{16}; int a4[] = {17}; int a5[] = {}; initial begin `checkh(a1.size, 2); `checkh(a1[0], 12); `checkh(a1[1], 13); `checkh(a2.size, 2); `checkh(a2[0], 14); `checkh(a2[1], 15); `checkh(a3.size, 1); `checkh(a3[0], 16); `checkh(a4.size, 1); `checkh(a4[0], 17); `checkh(a5.size, 0); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_assert_ctl_arg_unsup.v0000644000542200017500000000076115125463617024045 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; let OFF = 4; let EXPECT = 16; let UNIQUE = 32; let UNIQUE0 = 64; let PRIORITY = 128; initial begin $assertcontrol(OFF, EXPECT); $assertcontrol(OFF, UNIQUE); $assertcontrol(OFF, UNIQUE0); $assertcontrol(OFF, PRIORITY); end endmodule verilator-5.044/test_regress/t/t_lint_colonplus_bad.py0000755000542200017500000000076315125463617023661 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_union_hard_bad.py0000755000542200017500000000076315125463617022743 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_lib.py0000755000542200017500000000351515125463617020553 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt', 'xsim') test.top_filename = "t/t_lib_prot.v" if test.benchmark: test.sim_time = test.benchmark * 100 trace_opt = "" if re.search(r'--no-trace', ' '.join(test.driver_verilator_flags)) else "-trace" secret_prefix = "secret" secret_dir = test.obj_dir + "/" + secret_prefix test.mkdir_ok(secret_dir) while True: # Always compile the secret file with Verilator no matter what simulator # we are testing with test.run(logfile=secret_dir + "/vlt_compile.log", cmd=["perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", '--no-timing', trace_opt, "--prefix", "Vt_lib_prot_secret", "-cc", "-Mdir", secret_dir, "--lib-create", secret_prefix, "t/t_lib_prot_secret.v"], verilator_run=True) # yapf:disable test.run(logfile=secret_dir + "/secret_gcc.log", cmd=[os.environ["MAKE"], "-C", secret_dir, "-f", "Vt_lib_prot_secret.mk"]) test.compile(verilator_flags2=['--no-timing', trace_opt, "-LDFLAGS", secret_prefix + "/libsecret.a", secret_dir + "/secret.sv"], xsim_flags2=[secret_dir + "/secret.sv"]) # yapf:disable test.execute(xsim_run_flags2=["--sv_lib", secret_dir + "/libsecret", "--dpi_absolute"]) test.passes() break verilator-5.044/test_regress/t/t_assert_clock_event_unsup.v0000644000542200017500000000142015125463617024717 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ clk ); input clk; int cyc = 0; logic val = 0; always @(posedge clk) begin cyc <= cyc + 1; val = ~val; end property check(int cyc_mod_2, logic expected); @(posedge clk) cyc % 2 == cyc_mod_2 |=> val == expected; endproperty property check_if_1(int cyc_mod_2); @(negedge clk) check(cyc_mod_2, 1); endproperty assert property(check_if_1(1)) else begin // Assertion should fail $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_disable_inside.py0000755000542200017500000000101315125463617022732 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(timing_loop=True, verilator_flags2=["--timing"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_unroll_pragma.v0000644000542200017500000000202015125463617022447 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifdef TEST_DISABLE `define PRAGMA /*verilator unroll_disable*/ `elsif TEST_FULL `define PRAGMA /*verilator unroll_full*/ `elsif TEST_NONE `define PRAGMA `endif module t; int i, j; // This must always unroll for (genvar g = 0; g < 10; ++g) begin initial $c("gened();"); end initial begin // Test a loop equal to --unroll-count - should unroll without pragma `PRAGMA for (i = 0; i < 4; ++i) begin `PRAGMA for (j = 0; j < 4; ++j) begin $c("small();"); end end // Test a loop larger than --unroll-count `PRAGMA for (i = 0; i < 5; ++i) begin `PRAGMA for (j = 0; j < 5; ++j) begin $c("large();"); end end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_struct_unpacked_init.v0000644000542200017500000000101415125463617024030 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; parameter P = 4'h5; struct { // Can't legally be packed bit [3:0] m_lo = P; bit [3:0] m_hi; } s; initial begin s.m_hi = 4'ha; if (s.m_lo != 4'h5) $stop; if (s.m_hi != 4'ha) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_dynarray_method.v0000644000542200017500000001210115125463617022777 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); module t; string s[] = { "hello", "sad", "sad", "world" }; initial begin int d[]; int de[]; // Empty int qv[$]; // Value returns int qvunused[$]; // Value returns (unused) int qi[$]; // Index returns int i; d = '{1, 2, 2, 4, 3}; `checkp(d, "'{'h1, 'h2, 'h2, 'h4, 'h3}"); d = {1, 2, 2, 4, 3}; `checkp(d, "'{'h1, 'h2, 'h2, 'h4, 'h3}"); // sort/rsort with clause is the field to use for the sorting d.sort; `checkp(d, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); d.sort with (10 - item); `checkp(d, "'{'h4, 'h3, 'h2, 'h2, 'h1}"); d.sort(x) with (10 - x); `checkp(d, "'{'h4, 'h3, 'h2, 'h2, 'h1}"); de.sort(x) with (10 - x); `checkp(de, "'{}"); d.rsort; `checkp(d, "'{'h4, 'h3, 'h2, 'h2, 'h1}"); d.rsort with (10 - item); `checkp(d, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); de.rsort(x) with (10 - x); `checkp(d, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); d = '{2, 2, 4, 1, 3}; qv = d.unique; `checkp(qv, "'{'h2, 'h4, 'h1, 'h3}"); qv = de.unique; `checkh(qv.size(), 0); qi = d.unique_index; qv.sort; `checkp(qi, "'{'h0, 'h2, 'h3, 'h4}"); qi = de.unique_index; `checkh(qi.size(), 0); d.reverse; `checkp(d, "'{'h3, 'h1, 'h4, 'h2, 'h2}"); de.reverse; `checkh(de.size(), 0); d.shuffle(); d.sort; `checkp(d, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); de.shuffle(); `checkh(de.size(), 0); // These require an with clause or are illegal // TODO add a lint check that with clause is provided qv = d.find with (item == 2); `checkp(qv, "'{'h2, 'h2}"); qv = d.find_first with (item == 2); `checkp(qv, "'{'h2}"); qv = d.find_last with (item == 2); `checkp(qv, "'{'h2}"); qv = d.find with (item == 20); `checkh(qv.size, 0); qv = d.find_first with (item == 20); `checkh(qv.size, 0); qv = d.find_last with (item == 20); `checkh(qv.size, 0); // Check gate eater with Lambda variable removal qvunused = d.find with (item == 20); qi = d.find_index with (item == 2); qi.sort; `checkp(qi, "'{'h1, 'h2}"); qi = d.find_first_index with (item == 2); `checkp(qi, "'{'h1}"); qi = d.find_last_index with (item == 2); `checkp(qi, "'{'h2}"); i = 2; qi = d.find_index with (item == i); qi.sort; `checkp(qi, "'{'h1, 'h2}"); qi = d.find_index with (item == 20); qi.sort; `checkh(qi.size, 0); qi = d.find_first_index with (item == 20); `checkh(qi.size, 0); qi = d.find_last_index with (item == 20); `checkh(qi.size, 0); qi = d.find_index with (item.index == 2); `checkp(qi, "'{'h2}"); qv = d.min; `checkp(qv, "'{'h1}"); qv = d.max; `checkp(qv, "'{'h4}"); qv = de.min; `checkp(qv, "'{}"); qv = de.max; `checkp(qv, "'{}"); // Reduction methods i = d.sum; `checkh(i, 32'hc); i = d.sum with (item + 1); `checkh(i, 32'h11); i = d.sum(myi) with (myi + 1); `checkh(i, 32'h11); i = d.sum with (1); // unused 'index' `checkh(i, 32'h5); i = d.sum(unused) with (1); // unused 'unused' `checkh(i, 32'h5); i = d.product; `checkh(i, 32'h30); i = d.product with (item + 1); `checkh(i, 32'h168); i = de.sum; `checkh(i, 32'h0); i = de.product; `checkh(i, 32'h0); d = '{32'b1100, 32'b1010}; i = d.and; `checkh(i, 32'b1000); i = d.and with (item + 1); `checkh(i, 32'b1001); i = d.or; `checkh(i, 32'b1110); i = d.or with (item + 1); `checkh(i, 32'b1111); i = d.xor; `checkh(i, 32'b0110); i = d.xor with (item + 1); `checkh(i, 32'b0110); i = de.and; `checkh(i, 32'b0); i = de.or; `checkh(i, 32'b0); i = de.xor; `checkh(i, 32'b0); `checks(s[1], "sad"); qi = s.find_first_index with (item == "sad"); `checkh(qi.size, 1); `checkh(qi[0], 1); qi = s.find_last_index with (item == "sad"); `checkh(qi.size, 1); `checkh(qi[0], 2); d = '{1, 2}; de = '{1, 2}; `checkh(d == de, 1'b1); `checkh(d != de, 1'b0); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_assert_basic_cover.py0000755000542200017500000000150215125463617023637 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_assert_basic.v" test.compile(verilator_flags2=['--assert --cc --coverage-user']) test.execute() #Needs work print("-Info: NOT checking for coverage") #test.file_grep(test.coverage_filename, r't=>'psl_cover',o=>'cover',c=>2\);') #test.file_grep(test.coverage_filename, r'DefaultClock.*,c=>1\);') #test.file_grep(test.coverage_filename, r'ToggleLogIf.*,c=>9\);') test.passes() verilator-5.044/test_regress/t/t_typename.py0000755000542200017500000000100315125463617021615 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_struct_nest_uarray.v0000644000542200017500000000174615125463617023563 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); typedef struct { struct { struct { logic [31:0] next; } val; } el[1]; } pstr_t; module t; typedef struct { struct { struct { logic [31:0] next; } val; } el[1]; } str_t; str_t str; pstr_t pstr; initial begin str.el[0].val.next = 6; `checkp(str, "'{el:'{'{val:'{next:'h6}}}}"); pstr.el[0].val.next = 6; `checkp(str, "'{el:'{'{val:'{next:'h6}}}}"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_cover_main.out0000644000542200017500000000014015125463617022272 0ustar mahmoudyfreeshell# SystemC::Coverage-3 C 'ft/t_cover_main.vl9n4tlinepagev_line/toblockS9-11ht' 1 verilator-5.044/test_regress/t/t_user_type_xassign.py0000755000542200017500000000073415125463617023560 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg2.py0000755000542200017500000000077115125463617031512 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_if_deep.v0000644000542200017500000001357315125463617021217 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[31:0]), // Inputs .clk (clk), .in (in[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; // What checksum will we end up with `define EXPECTED_SUM 64'h966e272fd829e672 // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs clk, in ); input clk; input [31:0] in; output [31:0] out; /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) reg [31:0] out; // End of automatics `ifdef verilator `define dontOptimize $c1("1") `else `define dontOptimize 1'b1 `endif always @(posedge clk) begin out <= in; // verilog_format: off if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (in[0]) out <= ~in; // verilog_format: on end endmodule verilator-5.044/test_regress/t/t_enum_overlap_bad.out0000644000542200017500000000065315125463617023463 0ustar mahmoudyfreeshell%Error: t/t_enum_overlap_bad.v:12:11: Overlapping enumeration value: 'e1b' : ... note: In instance 't' 12 | e1b=1 | ^~~ t/t_enum_overlap_bad.v:10:11: ... Location of original declaration 10 | e1, | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_time_stamp64.py0000755000542200017500000000116215125463617022315 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') # Verilator before 4.033 had 'double sc_time_stamp()', make sure new form compiles test.vl_time_stamp64 = True test.compile(verilator_flags2=['-DVL_TIME_STAMP64=1']) test.execute() test.passes() verilator-5.044/test_regress/t/t_fallback_bad.py0000755000542200017500000000076615125463617022357 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_wrapper_reuse_context_bad.out0000644000542200017500000000021315125463617025406 0ustar mahmoudyfreeshell%Error: Adding model 'TOP' when time is non-zero. ... Suggest check time(), or for restarting model use a new VerilatedContext Aborting... verilator-5.044/test_regress/t/t_clocking_virtual.py0000755000542200017500000000077115125463617023345 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_assert_sampled.py0000755000542200017500000000077115125463617023014 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert']) test.execute() test.passes() verilator-5.044/test_regress/t/t_randomize_method_nclass_bad.v0000644000542200017500000000045015125463617025313 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin randomize(1); srandom(1); end endmodule verilator-5.044/test_regress/t/t_covergroup_unsup_ign.py0000755000542200017500000000110615125463617024261 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_covergroup_unsup.v" test.lint(verilator_flags2=['--assert --coverage --Wno-COVERIGN +define+T_COVERGROUP_UNSUP_IGN']) test.passes() verilator-5.044/test_regress/t/t_class_extends_int_param_bad.out0000644000542200017500000000055315125463617025657 0ustar mahmoudyfreeshell%Error: t/t_class_extends_int_param_bad.v:9:23: Attempting to extend using non-class : ... note: In instance 't' 9 | class Bar #(type T=int) extends T; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_var_pins_bad.py0000755000542200017500000000107215125463617022430 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = 't/t_EXAMPLE.v' test.lint(verilator_flags2=["--pins-bv 99"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_assert_synth_parallel.py0000755000542200017500000000133615125463617024406 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_assert_synth.v" test.compile(v_flags2=['+define+FAILING_PARALLEL', '+define+ATTRIBUTES'], verilator_flags2=['--assert'], nc_flags2=['+assert']) test.execute(check_finished=False, fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_param_named.py0000755000542200017500000000073415125463617022251 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_case_enum_incomplete_bad.py0000755000542200017500000000102515125463617024763 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--assert'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_lparam_assign_iface_typedef_nested2.py0000755000542200017500000000077115125463617027121 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_gen_defparam_nfound_bad.out0000644000542200017500000000041115125463617024740 0ustar mahmoudyfreeshell%Error: t/t_gen_defparam_nfound_bad.v:9:17: In defparam, instance z never declared 9 | defparam z.W = 3; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_preproc_defarg_bad.out0000644000542200017500000000116315125463617023746 0ustar mahmoudyfreeshell%Error: t/t_preproc_defarg_bad.v:13:4: Illegal text before '(' that starts define arguments ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_preproc_defarg_bad.v:13:8: Define passed too many arguments: A1 %Error: t/t_preproc_defarg_bad.v:15:4: Illegal text before '(' that starts define arguments %Error: t/t_preproc_defarg_bad.v:16:10: Define passed too many arguments: A2 %Error: t/t_preproc_defarg_bad.v:21:1: EOF in define argument list %Error: t/t_preproc_defarg_bad.v:21:1: Expecting ( to begin argument list for define reference `A2 %Error: Exiting due to verilator-5.044/test_regress/t/t_expect.py0000755000542200017500000000102215125463617021264 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) test.passes() verilator-5.044/test_regress/t/t_display_wide.py0000755000542200017500000000100015125463617022445 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_pp_circdef_bad.v0000644000542200017500000000070315125463617022517 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // // bug445 `define WIDTH 12 `define SEL_NUM_BITS `WIDTH-`SEL_NUM_BITS +: `SEL_NUM_BITS `define SEL_BITS `WIDTH-`SEL_NUM_BITS +: `SEL_NUM_BITS `define ADDR_BITS 0 +: `WIDTH-`SEL_NUM_BITS typedef logic [`SEL_NUM_BITS-1:0] d_t; verilator-5.044/test_regress/t/t_case_orig.py0000755000542200017500000000073415125463617021740 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_var_ref_bad3.py0000755000542200017500000000076315125463617022324 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_select_plusloop.py0000755000542200017500000000073415125463617023221 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_udp_bad_multi_output.py0000755000542200017500000000076615125463617024242 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_interface_generic_modport_bad3.v0000644000542200017500000000106615125463617025707 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; int v; int o; modport mp ( input o ); endinterface module GenericModule (interface.mp a); initial begin #1; if (a.v != 7) $stop; end endmodule module t; inf inf_inst(); GenericModule genericModule (inf_inst); initial begin inf_inst.v = 7; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_param_implicit_bad.py0000755000542200017500000000076615125463617023612 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_flag_values_bad.out0000644000542200017500000000045715125463617023261 0ustar mahmoudyfreeshell%Error: --output-split-cfuncs must be >= 0: -1 ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: --output-split-ctrace must be >= 0: -1 %Error: --preproc-token-limit must be > 0: 0 %Error: --reloop-limit must be >= 2: -1 %Error: Exiting due to verilator-5.044/test_regress/t/t_class_builtin_bad.py0000755000542200017500000000076615125463617023453 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_gen_cond_bitrange.py0000755000542200017500000000073415125463617023434 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_langext_3.py0000755000542200017500000000100715125463617021663 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') # This is a compile only test. test.compile(v_flags2=["+1364-2005ext+v"]) test.passes() verilator-5.044/test_regress/t/t_timing_wait2.v0000644000542200017500000000117715125463617022216 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; bit s[3:0] = {0, 0, 0, 0}; initial begin wait (s[1]); s[0] = 1; $display("0"); end initial begin wait (s[2]); s[1] = 1; $display("1"); #1 $write("*-* All Finished *-*\n"); $finish; end initial begin wait (s[3]); s[2] = 1; $display("2"); end initial begin s[3] = 1; end initial #2 $stop; // timeout endmodule verilator-5.044/test_regress/t/t_class_super_bad3.out0000644000542200017500000000042215125463617023367 0ustar mahmoudyfreeshell%Error: t/t_class_super_bad3.v:10:5: Syntax error: 'super' must be first name component, or after 'this.' 10 | i.super.i = 1; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_cover_lib__4.out0000644000542200017500000000002615125463617022501 0ustar mahmoudyfreeshell# SystemC::Coverage-3 verilator-5.044/test_regress/t/t_force_port_inline.py0000755000542200017500000000076715125463617023513 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.044/test_regress/t/t_class_extends2.v0000644000542200017500000000521115125463617022533 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package Pkg; class Base0; class BaseInnerOnly; int inneronly; function new(); inneronly = 10; if (inneronly != 10) $stop; endfunction endclass class BaseInnerOver; int innerover; function new(); innerover = 10; if (innerover != 10) $stop; endfunction endclass int baseonly; int baseover; BaseInnerOnly inneronly = new; BaseInnerOver innerover = new; function void b_set_bo(int v); baseover = v; endfunction function int b_get_bo(); return baseover; endfunction function int get_bo(); return baseover; endfunction function void b_set_io(int v); innerover.innerover = v; endfunction function int b_get_io(); return innerover.innerover; endfunction function int get_io(); return innerover.innerover; endfunction endclass endpackage // We need to import Base0, as verilator currently doesn't support // multiple `::` references, but we would need to do that to reference // `BaseInnerOnly` class inside `Ext` class. import Pkg::Base0; class Ext extends Pkg::Base0; class BaseInnerOver; int innerover; function new(); innerover = 20; if (innerover != 20) $stop; endfunction endclass int baseover; int extonly; BaseInnerOnly inneronly = new; BaseInnerOver innerover = new; function void e_set_bo(int v); baseover = v; endfunction function int e_get_bo(); return baseover; endfunction function int get_bo(); return baseover; endfunction function void e_set_io(int v); innerover.innerover = v; endfunction function int e_get_io(); return innerover.innerover; endfunction function int get_io(); return innerover.innerover; endfunction endclass module t; initial begin Ext c; c = new; c.baseonly = 10; c.baseover = 20; c.extonly = 30; c.inneronly.inneronly = 40; c.innerover.innerover = 50; if (c.baseonly != 10) $stop; if (c.baseover != 20) $stop; if (c.extonly != 30) $stop; if (c.inneronly.inneronly != 40) $stop; if (c.innerover.innerover != 50) $stop; c.b_set_bo(100); c.e_set_bo(200); c.b_set_io(300); c.e_set_io(400); if (c.b_get_bo() != 100) $stop; if (c.e_get_bo() != 200) $stop; if (c.get_bo() != 200) $stop; if (c.b_get_io() != 300) $stop; if (c.e_get_io() != 400) $stop; if (c.get_io() != 400) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_forceable_public_flat.py0000755000542200017500000000126115125463617024267 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() files = test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.h") test.file_grep_any(files, r' u_sub__DOT__a__VforceRd') test.file_grep_any(files, r' u_sub__DOT__a__VforceEn') test.file_grep_any(files, r' u_sub__DOT__a__VforceVal') test.passes() verilator-5.044/test_regress/t/t_implements_collision_bad.py0000755000542200017500000000076615125463617025050 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_struct_unaligned.py0000755000542200017500000000107515125463617023356 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') # Note: need to run at a higher optimization level to reproduce the issue test.benchmark = True test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_vpi_const_type.v0000644000542200017500000000207615125463617022665 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import "DPI-C" context function int mon_check(); module t (/*AUTOARG*/ ); /*verilator public_module*/ parameter int intParam /*verilator public_flat_rd*/ = 5; parameter real realParam /*verilator public_flat_rd*/ = 2.3; parameter time timeParam /*verilator public_flat_rd*/ = 0; parameter string strParam /*verilator public_flat_rd*/ = "abc"; logic [31:0] signal_rw /*verilator public_flat_rw*/; logic [31:0] signal_rd /*verilator public_flat_rd*/; int status; initial begin status = mon_check(); if (status!=0) begin $write("%%Error: t_vpi_const_type.cpp:%0d: C Test failed\n", status); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule : t verilator-5.044/test_regress/t/t_class_func_nvoid_bad.v0000644000542200017500000000307115125463617023741 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; function int fi(); return 10; endfunction function void fv(); endfunction task t(); endtask static function int sfi(); return 10; endfunction static function void sfv(); endfunction static task st(); endtask endclass module t; function int mod_fi(); return 10; endfunction function void mod_fv(); endfunction task mod_t(); endtask initial begin Cls c; c = new; // For test of calling function in void context, see t_func_void_bad.v // Module if (mod_fi() != 10) $stop; // OK void'(mod_fi()); // OK mod_fv(); // Warn IGNOREDRETURN void'(mod_fv()); // OK if (mod_fv() == 10) $stop; // Bad call of task as function mod_t(); // OK if (mod_t() == 10) $stop; // Bad call of task as function // Member functions if (c.fi() != 10) $stop; // OK void'(c.fi()); // OK c.fv(); // Ok void'(c.fv()); // OK if (c.fv() == 10) $stop; // Bad c.t(); // OK if (c.t() == 10) $stop; // Bad // Static member functions if (c.sfi() != 10) $stop; // OK void'(c.sfi()); // OK c.sfv(); // Ok void'(c.sfv()); // OK if (c.sfv() == 10) $stop; // Bad c.st(); // OK if (c.st() == 10) $stop; // Bad $stop; end endmodule verilator-5.044/test_regress/t/t_const_overflow_bad.py0000755000542200017500000000076615125463617023671 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_cover_assert.out0000644000542200017500000000226215125463617022656 0ustar mahmoudyfreeshell%Warning-PROCASSINIT: t/t_cover_assert.v:13:18: Procedural assignment to declaration with initial value: 'cyc' : ... note: In instance 't' : ... Location of variable initialization 13 | integer cyc = 0; | ^ t/t_cover_assert.v:19:7: ... Location of variable process write : ... Perhaps should initialize instead using a reset in this process 19 | cyc <= cyc + 1; | ^~~ ... For warning description see https://verilator.org/warn/PROCASSINIT?v=latest ... Use "/* verilator lint_off PROCASSINIT */" and lint_on around source to disable this message. %Error-UNSUPPORTED: t/t_cover_assert.v:39:11: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2023 16.14.6) : ... note: In instance 't' 39 | C1: cover property(a) | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.044/test_regress/t/t_inst_darray.py0000755000542200017500000000073415125463617022324 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_var_sc_bv.v0000644000542200017500000001403615125463617021563 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2008 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs o_29,o_29_old, o_30,o_30_old, o_31,o_31_old, o_32,o_32_old, o_59,o_59_old, o_60,o_60_old, o_62,o_62_old, o_64,o_64_old, o_119,o_119_old, o_120,o_120_old, o_121,o_121_old, o_127,o_127_old, o_128,o_128_old, o_255,o_255_old, o_256,o_256_old, // Inputs i_29,i_29_old, i_30,i_30_old, i_31,i_31_old, i_32,i_32_old, i_59,i_59_old, i_60,i_60_old, i_62,i_62_old, i_64,i_64_old, i_119,i_119_old, i_120,i_120_old, i_121,i_121_old, i_127,i_127_old, i_128,i_128_old, i_255,i_255_old, i_256,i_256_old ); input [255:0] i_29; output wire [255:0] o_29; input [255:0] i_29_old; output wire [255:0] o_29_old; input [255:0] i_30; output wire [255:0] o_30; input [255:0] i_30_old; output wire [255:0] o_30_old; input [255:0] i_31; output wire [255:0] o_31; input [255:0] i_31_old; output wire [255:0] o_31_old; input [255:0] i_32; output wire [255:0] o_32; input [255:0] i_32_old; output wire [255:0] o_32_old; input [255:0] i_59; output wire [255:0] o_59; input [255:0] i_59_old; output wire [255:0] o_59_old; input [255:0] i_60; output wire [255:0] o_60; input [255:0] i_60_old; output wire [255:0] o_60_old; input [255:0] i_62; output wire [255:0] o_62; input [255:0] i_62_old; output wire [255:0] o_62_old; input [255:0] i_64; output wire [255:0] o_64; input [255:0] i_64_old; output wire [255:0] o_64_old; input [255:0] i_119; output wire [255:0] o_119; input [255:0] i_119_old; output wire [255:0] o_119_old; input [255:0] i_120; output wire [255:0] o_120; input [255:0] i_120_old; output wire [255:0] o_120_old; input [255:0] i_121; output wire [255:0] o_121; input [255:0] i_121_old; output wire [255:0] o_121_old; input [255:0] i_127; output wire [255:0] o_127; input [255:0] i_127_old; output wire [255:0] o_127_old; input [255:0] i_128; output wire [255:0] o_128; input [255:0] i_128_old; output wire [255:0] o_128_old; input [255:0] i_255; output wire [255:0] o_255; input [255:0] i_255_old; output wire [255:0] o_255_old; input [255:0] i_256; output wire [255:0] o_256; input [255:0] i_256_old; output wire [255:0] o_256_old; sub sub (.*); endmodule module sub (/*AUTOARG*/ // Outputs o_29,o_29_old, o_30,o_30_old, o_31,o_31_old, o_32,o_32_old, o_59,o_59_old, o_60,o_60_old, o_62,o_62_old, o_64,o_64_old, o_119,o_119_old, o_120,o_120_old, o_121,o_121_old, o_127,o_127_old, o_128,o_128_old, o_255,o_255_old, o_256,o_256_old, // Inputs i_29,i_29_old, i_30,i_30_old, i_31,i_31_old, i_32,i_32_old, i_59,i_59_old, i_60,i_60_old, i_62,i_62_old, i_64,i_64_old, i_119,i_119_old, i_120,i_120_old, i_121,i_121_old, i_127,i_127_old, i_128,i_128_old, i_255,i_255_old, i_256,i_256_old ); input [255:0] i_29; output wire [255:0] o_29; input [255:0] i_29_old; output wire [255:0] o_29_old; input [255:0] i_30; output wire [255:0] o_30; input [255:0] i_30_old; output wire [255:0] o_30_old; input [255:0] i_31; output wire [255:0] o_31; input [255:0] i_31_old; output wire [255:0] o_31_old; input [255:0] i_32; output wire [255:0] o_32; input [255:0] i_32_old; output wire [255:0] o_32_old; input [255:0] i_59; output wire [255:0] o_59; input [255:0] i_59_old; output wire [255:0] o_59_old; input [255:0] i_60; output wire [255:0] o_60; input [255:0] i_60_old; output wire [255:0] o_60_old; input [255:0] i_62; output wire [255:0] o_62; input [255:0] i_62_old; output wire [255:0] o_62_old; input [255:0] i_64; output wire [255:0] o_64; input [255:0] i_64_old; output wire [255:0] o_64_old; input [255:0] i_119; output wire [255:0] o_119; input [255:0] i_119_old; output wire [255:0] o_119_old; input [255:0] i_120; output wire [255:0] o_120; input [255:0] i_120_old; output wire [255:0] o_120_old; input [255:0] i_121; output wire [255:0] o_121; input [255:0] i_121_old; output wire [255:0] o_121_old; input [255:0] i_127; output wire [255:0] o_127; input [255:0] i_127_old; output wire [255:0] o_127_old; input [255:0] i_128; output wire [255:0] o_128; input [255:0] i_128_old; output wire [255:0] o_128_old; input [255:0] i_255; output wire [255:0] o_255; input [255:0] i_255_old; output wire [255:0] o_255_old; input [255:0] i_256; output wire [255:0] o_256; input [255:0] i_256_old; output wire [255:0] o_256_old; assign o_29 = i_29; assign o_29_old = i_29_old; assign o_30 = i_30; assign o_30_old = i_30_old; assign o_31 = i_31; assign o_31_old = i_31_old; assign o_32 = i_32; assign o_32_old = i_32_old; assign o_59 = i_59; assign o_59_old = i_59_old; assign o_60 = i_60; assign o_60_old = i_60_old; assign o_62 = i_62; assign o_62_old = i_62_old; assign o_64 = i_64; assign o_64_old = i_64_old; assign o_119 = i_119; assign o_119_old = i_119_old; assign o_120 = i_120; assign o_120_old = i_120_old; assign o_121 = i_121; assign o_121_old = i_121_old; assign o_127 = i_127; assign o_127_old = i_127_old; assign o_128 = i_128; assign o_128_old = i_128_old; assign o_255 = i_255; assign o_255_old = i_255_old; assign o_256 = i_256; assign o_256_old = i_256_old; endmodule verilator-5.044/test_regress/t/t_split_var_4.py0000755000542200017500000000133015125463617022224 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--stats', '-DENABLE_SPLIT_VAR=1', "-fno-dfg"]) test.execute() test.file_grep(test.stats, r'SplitVar,\s+packed variables split due to attribute\s+(\d+)', 1) test.file_grep(test.stats, r'SplitVar,\s+unpacked arrays split due to attribute\s+(\d+)', 0) test.passes() verilator-5.044/test_regress/t/t_class_scope_import_bad.py0000755000542200017500000000076615125463617024510 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_trace_dumpvars_dyn_fst_0.py0000755000542200017500000000130315125463617024762 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_trace_dumpvars_dyn.cpp" test.top_filename = "t/t_trace_dumpvars_dyn.v" test.compile(make_main=False, verilator_flags2=["--trace-fst --exe", test.pli_filename]) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_class_static_order.py0000755000542200017500000000073415125463617023654 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_unroll_unopt_io.v0000644000542200017500000000105115125463617023037 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Outputs zeros, // Inputs num ); parameter WIDTH = 1; input logic [WIDTH-1:0] num; output logic [$clog2(WIDTH+1)-1:0] zeros; integer i; always_comb begin i = 0; while ((i < WIDTH) & ~num[WIDTH-1-i]) i = i + 1; zeros = i[$clog2(WIDTH+1) - 1 : 0]; end endmodule verilator-5.044/test_regress/t/t_class_param_subtype_bad_paren.out0000644000542200017500000000055015125463617026210 0ustar mahmoudyfreeshell%Error: t/t_class_param_subtype.v:32:5: Reference to parameterized class without #() (IEEE 1800-2023 8.25.1) : ... Suggest use 'CParam#()' 32 | CParam::type_t val_0 = 100; | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_incr_void.v0000644000542200017500000000233115125463617021566 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Drew Ranck. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc = 0; always @ (posedge clk) begin : main cyc <= cyc + 1; if (cyc > 100) begin $write("*-* All Finished *-*\n"); $finish(); end end logic [3:0] count_d; logic [3:0] count_q = '0; logic [3:0] want_count_d; logic [3:0] want_count_q = '0; always_ff @(posedge clk) begin : flops count_q <= count_d; want_count_q <= want_count_d; end always @(posedge clk) begin : simple_check if (cyc > 0) begin if (count_q !== want_count_q) begin $error("%m: cyc=%0d, count_q (%0d) !== want_count_q (%0d)", cyc, count_q, want_count_q); $stop; // don't finish to fail the test. end end end always_comb begin : update_golden_counts want_count_d = want_count_q; want_count_d += 1'b1; end // make sure an implicit void cast on n++ works as expected. always_comb begin : update_counts count_d = count_q; count_d++; end endmodule verilator-5.044/test_regress/t/t_class_func_static_bad.v0000644000542200017500000000103015125463617024102 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; class C; task static task_st(int x); // BAD - methods have automatic lifetime int y; y = 2 * x; endtask function static int func_st(int x); // BAD - methods have automatic lifetime int y; y = 2 * x; return y; endfunction endclass initial $stop; endmodule verilator-5.044/test_regress/t/t_package_dup_bad2.v0000644000542200017500000000055415125463617022752 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package Pkg; endpackage module t; IOBUF iocell ( .O(in), .IO(pad), .I('0), .T(~oe) ); endmodule package Pkg; endpackage verilator-5.044/test_regress/t/t_opt_assemble_cellarray_off.py0000755000542200017500000000115215125463617025345 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.top_filename = "t/t_opt_life.v" test.compile(verilator_flags2=['--stats', '-fno-assemble']) test.file_grep_not(test.stats, r'Optimizations, Concat merges\s+(\d+)') test.passes() verilator-5.044/test_regress/t/t_case_onehot.py0000755000542200017500000000073415125463617022274 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_class_extern_bad.out0000644000542200017500000000167215125463617023463 0ustar mahmoudyfreeshell%Error: t/t_class_extern_bad.v:9:15: Duplicate declaration of task: 'extern nodef' 9 | extern task nodef(); | ^~~~~ t/t_class_extern_bad.v:8:15: ... Location of original declaration 8 | extern task nodef(); | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error-PROTOTYPEMIS: t/t_class_extern_bad.v:8:15: Definition not found for extern prototype 'nodef' 8 | extern task nodef(); | ^~~~~ ... For error description see https://verilator.org/warn/PROTOTYPEMIS?v=latest %Error-PROTOTYPEMIS: t/t_class_extern_bad.v:9:15: Definition not found for extern prototype 'nodef' 9 | extern task nodef(); | ^~~~~ %Error: t/t_class_extern_bad.v:12:6: extern not found that declares 'noproto' 12 | task Base1::noproto(); | ^~~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_init_concat.v0000644000542200017500000000443515125463617022113 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [31:0] wr_data; reg wr_en; wire [31:0] rd_data; wire [1:0] rd_guards; wire [1:0] rd_guardsok; regfile regfile (/*AUTOINST*/ // Outputs .rd_data (rd_data[31:0]), .rd_guards (rd_guards[1:0]), .rd_guardsok (rd_guardsok[1:0]), // Inputs .wr_data (wr_data[31:0]), .wr_en (wr_en), .clk (clk)); initial wr_en = 0; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin if (!rd_guards[0]) $stop; if (!rd_guardsok[0]) $stop; wr_en <= 1'b1; wr_data <= 32'hfeedf; end if (cyc==2) begin wr_en <= 0; end if (cyc==3) begin wr_en <= 0; if (rd_data != 32'hfeedf) $stop; if (rd_guards != 2'b11) $stop; if (rd_guardsok != 2'b11) $stop; end if (cyc==4) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module regfile ( input [31:0] wr_data, input wr_en, output reg [31:0] rd_data, output [1:0] rd_guards /*verilator public*/, output [1:0] rd_guardsok /*verilator public*/, input clk ); always @(posedge clk) begin if (wr_en) begin rd_data <= wr_data; end end // this initial statement will induce correct initialize behavior // initial rd_guards= { 2'b11 }; assign rd_guards= { rd_data[0], 1'b1 }; assign rd_guardsok[0] = 1'b1; assign rd_guardsok[1] = rd_data[0]; endmodule // regfile verilator-5.044/test_regress/t/t_class_param_nconst_bad.v0000644000542200017500000000051115125463617024267 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls #(parameter PARAM = 12); endclass module t; Cls #(.PARAM($random)) c; // Bad param name endmodule verilator-5.044/test_regress/t/t_dfg_multidriver_dfg_bad.py0000755000542200017500000000111315125463617024611 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["-fdfg-synthesize-all", "-fno-const-before-dfg"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_runflag_quiet.v0000644000542200017500000000054615125463617022465 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 timeunit 1us; timeprecision 1ns; module t; initial begin #10; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_var_nonamebegin__log.out0000644000542200017500000000050715125463617024311 0ustar mahmoudyfreeshellingen: {mod}.genblk1 top.t.genblk1 d3a: {mod}.d3nameda top.t.unnamedblk1.d3nameda b2: {mod} top.t.unnamedblk2 b3n: {mod}.b3named: top.t.unnamedblk2.b3named b3: {mod} top.t.unnamedblk2.unnamedblk3 b4: {mod} top.t.unnamedblk2.unnamedblk3.unnamedblk4 t1 {mod}.tsk top.t.tsk t2 {mod}.tsk top.t.tsk.unnamedblk7 *-* All Finished *-* verilator-5.044/test_regress/t/t_randomize_method_with.v0000644000542200017500000001057015125463617024201 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define check_rand(cl, field) \ begin \ longint prev_result; \ int ok = 0; \ void'(cl.randomize()); \ prev_result = longint'(field); \ repeat(9) begin \ longint result; \ void'(cl.randomize()); \ result = longint'(field); \ if (result != prev_result) ok = 1; \ prev_result = result; \ end \ if (ok != 1) $stop; \ end class Boo; function new(); boo = 6; endfunction int unsigned boo; endclass class Foo extends Boo; rand int unsigned a; rand int unsigned b; int x; function new(int x); this.x = x; endfunction constraint constr1_c { b < x; } function bit test_this_randomize; return this.randomize() with { a <= boo; } == 1; endfunction endclass // Current AstWith representation makes VARs of caller indistinguishable from VARs of randomized // object if both the caller and callee are the same module, but different instances. // That's why for the purpose of this test, the caller derives a different class class Bar extends Boo; // Give the local variables a different scope by defining the functino under Bar static function bit test_local_constrdep(Foo foo, int c); return foo.randomize() with { a <= c; a > 1; x % a == 0; } == 1; endfunction function bit test_capture_of_callers_derived_var(Foo foo); boo = 4; foo.a = 3; return (foo.randomize() with { a == local::boo; } == 1) && (foo.a == 4); endfunction static function bit test_capture_of_callees_derived_var(Foo foo); foo.a = 5; return (foo.randomize() with { a == boo; } == 1) && (foo.a == 6); endfunction static function bit test_capture_of_local_qualifier(Foo foo); foo.a = 5; return (foo.randomize() with { a == boo; } == 1) && (foo.a == 6); endfunction endclass class Baz; rand int v; endclass class Baz2; rand int v; function bit test_this_randomize; return this.randomize() with { v == 5; } == 1; endfunction endclass module submodule(); int sub_var = 7; endmodule function automatic int return_2(); return 2; endfunction class Cls; rand int a; rand int b; endclass class Cls2 extends Cls; rand int c; endclass module mwith(); submodule sub1(); submodule sub2(); function automatic int return_3(); return 3; endfunction initial begin int c = 30; Foo foo = new(c); Baz baz = new; typedef Baz baz_t; baz_t baz1 = new; Baz2 baz2 = new; Bar bar = new; Cls2 cls2 = new; Cls cls = cls2; $display("foo.x = %d", foo.x); $display("-----------------"); repeat (20) begin if (Bar::test_local_constrdep(foo, 5)) begin $display("foo.a = %d", foo.a); $display("foo.b = %d", foo.b); $display("-----------------"); if (!(foo.a inside {2, 3, 5})) $stop; if (foo.b >= foo.x) $stop; if (foo.a > c) $stop; if (foo.a <= 1) $stop; sub1.sub_var = foo.a; end else $display("Failed to randomize foo with inline constraints"); end if (cls.randomize() with { b == 1;} != 1) $stop; if (cls.b != 1) $stop; `check_rand(cls2, cls2.a); `check_rand(cls2, cls2.c); // Check randomize as a task // verilator lint_off IGNOREDRETURN cls.randomize() with { b == 2;}; // verilator lint_on IGNOREDRETURN if (cls.b != 2) $stop; // Check capture of a static variable if (foo.randomize() with { a > sub1.sub_var; } != 1) $stop; // Check reference to a function if (foo.randomize() with { a > return_2(); } != 1) $stop; // Check randomization of class with no constraints if (baz.randomize() with { v inside {[2:10]}; } != 1) $stop; if (baz1.randomize() with { v inside {[2:10]}; } != 1) $stop; // Check randomization with captured non-static variable from different AstNodeModule if (!bar.test_capture_of_callers_derived_var(foo)) $stop; // Check randomization with non-captured non-static variable from different AstNodeModule if (!Bar::test_capture_of_callees_derived_var(foo)) $stop; // Check this.randomize() if (!foo.test_this_randomize()) $stop; // Check this.randomize() with no constraints if (!baz2.test_this_randomize()) $stop; $write("*-* All Finished *-*\n"); $finish(); end endmodule verilator-5.044/test_regress/t/t_sys_readmem_s.mem0000644000542200017500000000055715125463617022765 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @4 654 @a 65a 65b 65c verilator-5.044/test_regress/t/t_class_method_str_literal.py0000755000542200017500000000073415125463617025056 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_class_local_typedef_bad.out0000644000542200017500000000141115125463617024757 0ustar mahmoudyfreeshell%Error-ENCAPSULATED: t/t_class_local_typedef_bad.v:13:8: 't1' is hidden as 'local' within this context (IEEE 1800-2023 8.18) 13 | Cls::t1 var1; | ^~ t/t_class_local_typedef_bad.v:13:8: ... Location of definition 9 | local typedef bit t1; | ^~ ... For error description see https://verilator.org/warn/ENCAPSULATED?v=latest %Error-ENCAPSULATED: t/t_class_local_typedef_bad.v:14:8: 't2' is hidden as 'protected' within this context (IEEE 1800-2023 8.18) 14 | Cls::t2 var2; | ^~ t/t_class_local_typedef_bad.v:14:8: ... Location of definition 10 | protected typedef bit t2; | ^~ %Error: Exiting due to verilator-5.044/test_regress/t/t_class_extern_typeref.py0000755000542200017500000000073415125463617024235 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_cast_param_logic.v0000644000542200017500000000065615125463617023111 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t #( parameter type data_t = logic ) ( input data_t[7:0] in_data ); typedef data_t[7:0] in_data_t; in_data_t out_data; always_comb out_data = in_data_t'(in_data); endmodule verilator-5.044/test_regress/t/t_assoc2.v0000644000542200017500000000244015125463617021005 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; int imap[int]; // associative array of an associative array logic [31:0] a [logic [31:0]][logic [63:0]]; task static disp(); int i = 60; imap[i++] = 600; imap[i++] = 601; foreach (imap[k]) $display("imap[%0d] = %0d", k, imap[k]); endtask always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 1) begin a[5][8] = 8; a[5][9] = 9; imap[10] = 100; imap[11] = 101; end else if (cyc == 2) begin `checkh(a[5][8], 8); `checkh(a[5][9], 9); disp(); $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.044/test_regress/t/t_preproc_eof1_bad.out0000644000542200017500000000030115125463617023341 0ustar mahmoudyfreeshell%Error: t/t_preproc_eof1_bad.v:9:1: EOF in '/* ... */' block comment ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_enum_int.v0000644000542200017500000000555715125463617021445 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; enum integer { EP_State_IDLE , EP_State_CMDSHIFT0 , EP_State_CMDSHIFT13 , EP_State_CMDSHIFT14 , EP_State_CMDSHIFT15 , EP_State_CMDSHIFT16 , EP_State_DWAIT , EP_State_DSHIFT0 , EP_State_DSHIFT1 , EP_State_DSHIFT15 } m_state_xr, m_state2_xr; // Beginning of automatic ASCII enum decoding reg [79:0] m_stateAscii_xr; // Decode of m_state_xr always @(m_state_xr) begin case ({m_state_xr}) EP_State_IDLE: m_stateAscii_xr = "idle "; EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 "; EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13"; EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14"; EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15"; EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16"; EP_State_DWAIT: m_stateAscii_xr = "dwait "; EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 "; EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 "; EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 "; default: m_stateAscii_xr = "%Error "; endcase end // End of automatics integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; //$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b); if (cyc==1) begin m_state_xr <= EP_State_IDLE; m_state2_xr <= EP_State_IDLE; end if (cyc==2) begin if (m_stateAscii_xr != "idle ") $stop; m_state_xr <= EP_State_CMDSHIFT13; if (m_state2_xr != EP_State_IDLE) $stop; m_state2_xr <= EP_State_CMDSHIFT13; end if (cyc==3) begin if (m_stateAscii_xr != "cmdshift13") $stop; m_state_xr <= EP_State_CMDSHIFT16; if (m_state2_xr != EP_State_CMDSHIFT13) $stop; m_state2_xr <= EP_State_CMDSHIFT16; end if (cyc==4) begin if (m_stateAscii_xr != "cmdshift16") $stop; m_state_xr <= EP_State_DWAIT; if (m_state2_xr != EP_State_CMDSHIFT16) $stop; m_state2_xr <= EP_State_DWAIT; end if (cyc==9) begin if (m_stateAscii_xr != "dwait ") $stop; if (m_state2_xr != EP_State_DWAIT) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.044/test_regress/t/t_inst_sv.py0000755000542200017500000000073415125463617021472 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_case_write2.v0000644000542200017500000000215315125463617022023 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [63:0] crc; integer fd; integer fdtmp; t_case_write2_tasks tasks (); integer cyc; initial cyc = 0; always @ (posedge clk) begin $fwrite(fd, "[%0d] crc=%x ", cyc, crc); tasks.big_case(fd, crc[31:0]); $fwrite(fd, "\n"); end always @ (posedge clk) begin //$write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc); cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; if (cyc==1) begin crc <= 64'h00000000_00000097; $write("%s", {"Open ", `STRINGIFY(`TEST_OBJ_DIR), "/t_case_write2_logger.log\n"}); fdtmp = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/t_case_write2_logger.log"}, "w"); fd <= fdtmp; end if (cyc==90) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.044/test_regress/t/t_queue_unknown_sel.py0000755000542200017500000000071415125463617023551 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.044/test_regress/t/t_sys_writemem.gold2.mem0000644000542200017500000000003015125463617023652 0ustar mahmoudyfreeshell10 11 12 13 14 15 16 17 verilator-5.044/test_regress/t/t_embed1_wrap.v0000644000542200017500000000531715125463617022007 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_embed1_wrap (/*AUTOARG*/ // Outputs bit_out, vec_out, wide_out, did_init_out, // Inputs clk, bit_in, vec_in, wide_in, is_ref ); /*AUTOINOUTMODULE("t_embed1_child")*/ // Beginning of automatic in/out/inouts (from specific module) output bit bit_out; output bit [30:0] vec_out; output bit [123:0] wide_out; output bit did_init_out; input clk; input bit_in; input [30:0] vec_in; input [123:0] wide_in; input is_ref; // End of automatics `ifdef verilator // Import $t_embed_child__initial etc as a DPI function `endif //TODO would like __'s as in {PREFIX}__initial but presently illegal for users to do this import "DPI-C" context function void t_embed_child_initial(); import "DPI-C" context function void t_embed_child_final(); import "DPI-C" context function void t_embed_child_eval(); import "DPI-C" context function void t_embed_child_io_eval ( //TODO we support bit, but not logic input bit clk, input bit bit_in, input bit [30:0] vec_in, input bit [123:0] wide_in, input bit is_ref, output bit bit_out, output bit [30:0] vec_out, output bit [123:0] wide_out, output bit did_init_out); initial begin // Load all values t_embed_child_initial(); end // Only if system verilog, and if a "final" block in the code final begin t_embed_child_final(); end bit _temp_bit_out; bit _temp_did_init_out; bit [30:0] _temp_vec_out; bit [123:0] _temp_wide_out; always @* begin t_embed_child_io_eval( clk, bit_in, vec_in, wide_in, is_ref, _temp_bit_out, _temp_vec_out, _temp_wide_out, _temp_did_init_out ); // TODO might eliminate these temporaries bit_out = _temp_bit_out; did_init_out = _temp_did_init_out; end // Send all variables every cycle, // or have a sensitivity routine for each? // How to make sure we call eval at end of variable changes? // #0 (though not verilator compatible!) // TODO for now, we know what changes when always @ (posedge clk) begin vec_out <= _temp_vec_out; wide_out <= _temp_wide_out; end endmodule verilator-5.044/test_regress/t/t_covergroup_option_bad2.v0000644000542200017500000000070615125463617024271 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Verilator lint_off COVERIGN module t; // verilator lint_off COVERIGN covergroup cg(); endgroup cg cov1; initial begin cov1 = new; cov1.not_an_option.name = "new_cov1_name"; // <--- Bad $finish; end endmodule verilator-5.044/test_regress/t/t_time_vpi_1us1ns.py0000755000542200017500000000140215125463617023024 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.pli_filename = "t/t_time_vpi_c.cpp" test.top_filename = "t/t_time_vpi.v" test.main_time_multiplier = 1e-6 / 1e-9 test.compile( v_flags2=['+define+time_scale_units=1us +define+time_scale_prec=1ns', test.pli_filename], verilator_flags2=['--vpi --trace-vcd']) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_pp_underline_bad.v0000644000542200017500000000062215125463617023105 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // verilator_no_inline_module initial begin case (1'b1) // synopsys_full_case 1'b0: $stop; endcase $stop; // Should have failed end endmodule verilator-5.044/test_regress/t/t_event_method_bad.v0000644000542200017500000000045115125463617023102 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; event e1; initial begin e1.bad_method(); end endmodule verilator-5.044/test_regress/t/t_class_defaultparam_import.v0000644000542200017500000000045715125463617025045 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 package foo; class bar #( type T = int ); endclass endpackage ; import foo::bar; verilator-5.044/test_regress/t/t_func_public.v0000644000542200017500000001436215125463617022112 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; tpub p1 (.clk(clk), .i(32'd1)); tpub p2 (.clk(clk), .i(32'd2)); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin `ifdef verilator $c("this->publicTop();"); `endif end if (cyc==20) begin $write("*-* All Finished *-*\n"); $finish; end end end task publicTop; // verilator public // We have different optimizations if only one of something, so try it out. $write("Hello in publicTop\n"); endtask task test_task(input [19:0] in [2], output [19:0] out [2]); // Issue 3316 // verilator public out[0] = in[1]; out[1] = in[0]; endtask endmodule module tpub ( input clk, input [31:0] i); reg [23:0] var_long; reg [59:0] var_quad; reg [71:0] var_wide; reg var_bool; // verilator lint_off BLKANDNBLK reg [11:0] var_flop; // verilator lint_on BLKANDNBLK reg [23:0] got_long /*verilator public*/; reg [59:0] got_quad /*verilator public*/; reg [71:0] got_wide /*verilator public*/; reg got_bool /*verilator public*/; integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; // cyc==1 is in top level if (cyc==2) begin publicNoArgs; publicSetBool(1'b1); publicSetLong(24'habca); publicSetQuad(60'h4444_3333_2222); publicSetWide(72'h12_5678_9123_1245_2352); var_flop <= 12'habe; end if (cyc==3) begin if (1'b1 != publicGetSetBool(1'b0)) $stop; if (24'habca != publicGetSetLong(24'h1234)) $stop; if (60'h4444_3333_2222 != publicGetSetQuad(60'h123_4567_89ab)) $stop; if (72'h12_5678_9123_1245_2352 != publicGetSetWide(72'hac_abca_aaaa_bbbb_1234)) $stop; end if (cyc==4) begin publicGetBool(got_bool); if (1'b0 != got_bool) $stop; publicGetLong(got_long); if (24'h1234 != got_long) $stop; publicGetQuad(got_quad); if (60'h123_4567_89ab != got_quad) $stop; publicGetWide(got_wide); if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop; end // `ifdef VERILATOR_PUBLIC_TASKS if (cyc==11) begin $c("this->publicNoArgs();"); $c("this->publicSetBool(true);"); $c("this->publicSetLong(0x11bca);"); $c("this->publicSetQuad(0x66655554444ULL);"); $c("this->publicSetFlop(0x321);"); //Unsupported: $c("WData w[3] = {0x12, 0x5678_9123, 0x1245_2352}; publicSetWide(w);"); end if (cyc==12) begin $c("this->got_bool = this->publicGetSetBool(true);"); $c("this->got_long = this->publicGetSetLong(0x11bca);"); $c("this->got_quad = this->publicGetSetQuad(0xaaaabbbbccccULL);"); end if (cyc==13) begin $c("{ bool gb; this->publicGetBool(gb); this->got_bool=gb; }"); if (1'b1 != got_bool) $stop; $c("this->publicGetLong(this->got_long);"); if (24'h11bca != got_long) $stop; $c("{ uint64_t qq; this->publicGetQuad(qq); this->got_quad=qq; }"); if (60'haaaa_bbbb_cccc != got_quad) $stop; $c("{ WData gw[3]; this->publicGetWide(gw); VL_ASSIGN_W(72,this->got_wide,gw); }"); if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop; //Below doesn't work, because we're calling it inside the loop that sets var_flop // if (12'h321 != var_flop) $stop; end if (cyc==14) begin if ($c32("this->publicInstNum()") != i) $stop; end `endif end end task publicEmpty; // verilator public begin end endtask task publicNoArgs; // verilator public $write("Hello in publicNoArgs\n"); endtask task publicSetBool; // verilator public input in_bool; var_bool = in_bool; endtask task publicSetLong; // verilator public input [23:0] in_long; reg [23:0] not_long; begin not_long = ~in_long; // Test that we can have local variables var_long = ~not_long; end endtask task publicSetQuad; // verilator public input [59:0] in_quad; var_quad = in_quad; endtask task publicSetFlop; // verilator public input [11:0] in_flop; var_flop = in_flop; endtask task publicSetWide; // verilator public input [71:0] in_wide; var_wide = in_wide; endtask task publicGetBool; // verilator public output out_bool; out_bool = var_bool; endtask task publicGetLong; // verilator public output [23:0] out_long; out_long = var_long; endtask task publicGetQuad; // verilator public output [59:0] out_quad; out_quad = var_quad; endtask task publicGetWide; // verilator public output [71:0] out_wide; out_wide = var_wide; endtask function publicGetSetBool; // verilator public input in_bool; begin publicGetSetBool = var_bool; var_bool = in_bool; end endfunction function [23:0] publicGetSetLong; // verilator public input [23:0] in_long; begin publicGetSetLong = var_long; var_long = in_long; end endfunction function [59:0] publicGetSetQuad; // verilator public input [59:0] in_quad; begin publicGetSetQuad = var_quad; var_quad = in_quad; end endfunction function [71:0] publicGetSetWide; // Can't be public, as no wide return types in C++ input [71:0] in_wide; begin publicGetSetWide = var_wide; var_wide = in_wide; end endfunction `ifdef VERILATOR_PUBLIC_TASKS function [31:0] publicInstNum; // verilator public publicInstNum = i; endfunction `endif endmodule verilator-5.044/test_regress/t/t_dpi_var.v0000644000542200017500000000715115125463617021243 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; wire monclk = ~clk; int in; int in_a; int in_b; int fr_a; int fr_b; int fr_a2; int fr_b2; int fr_chk; sub sub (.*); // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d in=%x sub.in_a=%x sub.in_b=%x fr_a=%x fr_b=%x fr_a2=%x fr_b2=%x fr_chk=%x\n", $time, cyc, in, sub.in_a, sub.in_b, fr_a, fr_b, fr_a2, fr_b2, fr_chk); `endif cyc <= cyc + 1; in <= {in[30:0], in[31]^in[2]^in[0]}; // The inputs to sub will be updated externally on the neg-edge so these // don't matter for the result in_a <= in_a + 1; in_b <= in_b + 1; if (cyc==0) begin // Setup in <= 32'hd70a4497; in_a <= 0; in_b <= 0; end else if (cyc<3) begin end else if (cyc<10) begin if (fr_chk != fr_a) $stop; if (fr_chk != fr_b) $stop; if (fr_chk != fr_a2) $stop; if (fr_chk != fr_b2) $stop; end else if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end always @(posedge t.monclk) begin mon_eval(); end endmodule `ifdef ATTRIBUTES import "DPI-C" context function void mon_scope_name (input string formatted /*verilator sformat*/ ); `else import "DPI-C" context function void mon_scope_name (input string formatted); `endif import "DPI-C" context function void mon_register_b(string name, int isOut, int n, int addend); import "DPI-C" context function void mon_register_done(); import "DPI-C" context function void mon_eval(); module sub (/*AUTOARG*/ // Outputs fr_a, fr_b, fr_a2, fr_b2, fr_chk, // Inputs in, in_a, in_b ); `systemc_imp_header void mon_class_name(const char* namep); void mon_register_a(const char* namep, void* sigp, bool isOut, int n, int addend); `verilog /* verilator lint_off ASSIGNIN */ `ifdef ATTRIBUTES // Sensitivity list accepted for backward compatibility but ignored input int in /*verilator public_flat_rd*/; input int in_a /*verilator public_flat_rw @(posedge t.monclk)*/; input int in_b /*verilator public_flat_rw*/; output int fr_a /*verilator public_flat_rw @(posedge t.monclk)*/; output int fr_b /*verilator public_flat_rw*/; `else input int in; input int in_a; input int in_b; output int fr_a; output int fr_b; `endif output int fr_a2; output int fr_b2; output int fr_chk; /* verilator lint_on ASSIGNIN */ always @* fr_a2 = in_a + 1; always @* fr_b2 = in_b + 1; always @* fr_chk = in + 1; initial begin // Test the naming $c("mon_class_name(this->vlNamep);"); mon_scope_name("%m"); // Scheme A - pass pointer directly $c("mon_register_a(\"in\", &", in, ", false, 0, 1);"); $c("mon_register_a(\"fr_a\", &", fr_a, ", true, 0, 1);"); $c("mon_register_a(\"in\", &", in, ", false, 1, 0);"); $c("mon_register_a(\"in_a\", &", in_a, ", true, 1, 0);"); // Scheme B - use VPIish callbacks to see what signals exist mon_register_b("in", 0, 2, 1); mon_register_b("fr_b", 1, 2, 1); mon_register_b("in", 0, 3, 0); mon_register_b("in_b", 1, 3, 0); mon_register_done(); end endmodule verilator-5.044/test_regress/t/t_impure_cond_empty_if.v0000644000542200017500000000115715125463617024017 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class uvm_component; int x; function void set_x(); x = 1; endfunction function new(); if(call_set_return_false()); endfunction function bit call_set_return_false; set_x(); return 0; endfunction endclass module t; initial begin automatic uvm_component a = new; if (a.x != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_param_if_blk.v0000644000542200017500000000640615125463617022227 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013. // SPDX-License-Identifier: CC0-1.0 // bug648 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [7:0] datai = crc[7:0]; wire enable = crc[8]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) logic [7:0] datao; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .datao (datao[7:0]), // Inputs .clk (clk), .datai (datai[7:0]), .enable (enable)); // Aggregate outputs into a single result vector wire [63:0] result = {56'h0, datao}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h9d550d82d38926fa if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule `define FAIL 1 module Nested ( input logic clk, input logic x, output logic y ); logic t; always_comb t = x ^ 1'b1; always_ff @(posedge clk) begin if (clk) y <= t; end endmodule module Test ( input logic clk, input logic [7:0] datai, input logic enable, output logic [7:0] datao ); logic [7:0] datat; for (genvar i = 0; i < 8; i++) begin if (i%4 != 3) begin `ifndef FAIL logic t; always_comb begin t = datai[i] ^ 1'b1; end always_ff @(posedge clk) begin if (clk) datat[i] <= t; end `else Nested nested_i ( .clk(clk), .x(datai[i]), .y(datat[i]) //<== via Vcellout wire ); `endif always_comb begin casez (enable) 1'b1: datao[i] = datat[i]; 1'b0: datao[i] = '0; default: datao[i] = 'x; endcase end end else begin always_ff @(posedge clk) begin if (clk) datat[i] <= 0; //<== assign delayed end always_comb begin casez (enable) 1'b1: datao[i] = datat[i] ^ 1'b1; 1'b0: datao[i] = '1; default: datao[i] = 'x; endcase end end end endmodule verilator-5.044/test_regress/t/t_assign_expr.py0000755000542200017500000000073415125463617022327 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_while_cond_is_stmt.v0000644000542200017500000000142415125463617023471 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test of select from constant // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; function int unsigned nth_power_of_2(input int unsigned n); nth_power_of_2 = 1; while (n != 0) begin n = n - 1; nth_power_of_2 = nth_power_of_2 << 1; end endfunction initial begin // Evaluating the function call in the loop condition used // to cause an infinite loop at run-time while (nth_power_of_2(8) != 256) begin $display("2**8 != 256 ?!"); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_cover_expr_max.out0000644000542200017500000011312715125463617023203 0ustar mahmoudyfreeshell// // verilator_coverage annotation // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class cls; rand int x; endclass module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; logic [63:32] cyc2; always_comb cyc2 = cyc; integer some_int; integer other_int; logic some_bool; wire t1 = cyc[0]; wire t2 = cyc[1]; wire t3 = cyc[2]; wire t4 = cyc[3]; localparam bit ONE = 1'b1; localparam bit ZERO = 1'b0; function automatic bit invert(bit x); %000005 return ~x; -000004 point: comment=(x==0) => 1 hier=top.t -000005 point: comment=(x==1) => 0 hier=top.t endfunction function automatic bit and_oper(bit a, bit b); %000005 return a & b; -000004 point: comment=(a==0) => 0 hier=top.t -000002 point: comment=(a==1 && b==1) => 1 hier=top.t -000005 point: comment=(b==0) => 0 hier=top.t endfunction localparam int NUM_INTFS = 4; intf the_intfs [NUM_INTFS-1:0] (); genvar intf_i; for (intf_i = 0; intf_i < NUM_INTFS; intf_i++) begin always_comb the_intfs[intf_i].t = cyc[intf_i]; end always @ (posedge clk) begin cyc <= cyc + 1; %000004 if ((~cyc[0] && cyc[1]) || (~cyc[2] && cyc[3])) $write(""); -000002 point: comment=(cyc[0]==0 && cyc[1]==1) => 1 hier=top.t -000002 point: comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t -000004 point: comment=(cyc[0]==1 && cyc[3]==0) => 0 hier=top.t -000002 point: comment=(cyc[1]==0 && cyc[2]==1) => 0 hier=top.t -000003 point: comment=(cyc[1]==0 && cyc[3]==0) => 0 hier=top.t -000002 point: comment=(cyc[2]==0 && cyc[3]==1) => 1 hier=top.t %000004 if ((~cyc2[32] && cyc2[33]) || (~cyc2[34] && cyc2[35])) $write(""); -000002 point: comment=(cyc2[32]==0 && cyc2[33]==1) => 1 hier=top.t -000002 point: comment=(cyc2[32]==1 && cyc2[34]==1) => 0 hier=top.t -000004 point: comment=(cyc2[32]==1 && cyc2[35]==0) => 0 hier=top.t -000002 point: comment=(cyc2[33]==0 && cyc2[34]==1) => 0 hier=top.t -000003 point: comment=(cyc2[33]==0 && cyc2[35]==0) => 0 hier=top.t -000002 point: comment=(cyc2[34]==0 && cyc2[35]==1) => 1 hier=top.t %000004 if ((~the_intfs[0].t && the_intfs[1].t) || (~the_intfs[2].t && the_intfs[3].t)) $write(""); -000002 point: comment=(the_intfs[0].t==0 && the_intfs[1].t==1) => 1 hier=top.t -000002 point: comment=(the_intfs[0].t==1 && the_intfs[2].t==1) => 0 hier=top.t -000004 point: comment=(the_intfs[0].t==1 && the_intfs[3].t==0) => 0 hier=top.t -000002 point: comment=(the_intfs[1].t==0 && the_intfs[2].t==1) => 0 hier=top.t -000003 point: comment=(the_intfs[1].t==0 && the_intfs[3].t==0) => 0 hier=top.t -000002 point: comment=(the_intfs[2].t==0 && the_intfs[3].t==1) => 1 hier=top.t %000004 if ((~t1 && t2) || (~t3 && t4)) $write(""); -000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t -000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t -000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t -000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t -000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t -000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t %000005 if (t3 && (t1 == t2)) $write(""); -000005 point: comment=((t1 == t2)==0) => 0 hier=top.t -000005 point: comment=(t3==0) => 0 hier=top.t -000002 point: comment=(t3==1 && (t1 == t2)==1) => 1 hier=top.t %000005 if (123 == (124 - 32'(t1 || t2))) $write(""); -000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t -000005 point: comment=(t1==1) => 1 hier=top.t -000004 point: comment=(t2==1) => 1 hier=top.t %000004 some_int <= (t2 || t3) ? 345 : 567; -000003 point: comment=(t2==0 && t3==0) => 0 hier=top.t -000004 point: comment=(t2==1) => 1 hier=top.t -000004 point: comment=(t3==1) => 1 hier=top.t %000005 some_bool <= t1 && t2; -000004 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000005 if (t1 & t2) $write(""); -000004 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000004 if ((!t1 && t2) | (~t3 && t4)) $write(""); -000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t -000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t -000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t -000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t -000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t -000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t %000003 if (t1 ^ t2) $write(""); -000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t -000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t -000003 point: comment=(t1==1 && t2==0) => 1 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 0 hier=top.t %000005 if (~(t1 & t2)) $write(""); -000004 point: comment=(t1==0) => 1 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 0 hier=top.t -000005 point: comment=(t2==0) => 1 hier=top.t %000004 if (t1 -> t2) $write(""); -000004 point: comment=(t1==0) => 1 hier=top.t -000003 point: comment=(t1==1 && t2==0) => 0 hier=top.t -000004 point: comment=(t2==1) => 1 hier=top.t %000003 if (t1 <-> t2) $write(""); -000002 point: comment=(t1==0 && t2==0) => 1 hier=top.t -000002 point: comment=(t1==0 && t2==1) => 0 hier=top.t -000003 point: comment=(t1==1 && t2==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t %000005 if (&cyc[2:0]) $write(""); -000004 point: comment=(cyc[2:0][0]==0) => 0 hier=top.t -000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t -000005 point: comment=(cyc[2:0][1]==0) => 0 hier=top.t -000005 point: comment=(cyc[2:0][2]==0) => 0 hier=top.t %000007 if (&cyc[3:2]) $write(""); -000005 point: comment=(cyc[3:2][0]==0) => 0 hier=top.t -000000 point: comment=(cyc[3:2][0]==1 && cyc[3:2][1]==1) => 1 hier=top.t -000007 point: comment=(cyc[3:2][1]==0) => 0 hier=top.t %000005 if (|cyc[2:0]) $write(""); -000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t -000005 point: comment=(cyc[2:0][0]==1) => 1 hier=top.t -000004 point: comment=(cyc[2:0][1]==1) => 1 hier=top.t -000004 point: comment=(cyc[2:0][2]==1) => 1 hier=top.t %000002 if (^cyc[2:0]) $write(""); -000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t -000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 1 hier=top.t -000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 1 hier=top.t -000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 0 hier=top.t -000002 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 1 hier=top.t -000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 0 hier=top.t -000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 0 hier=top.t -000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t %000005 if (|cyc[2:0] || cyc[3]) $write(""); -000000 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0 && cyc[3]==0) => 0 hier=top.t -000005 point: comment=(cyc[2:0][0]==1) => 1 hier=top.t -000004 point: comment=(cyc[2:0][1]==1) => 1 hier=top.t -000004 point: comment=(cyc[2:0][2]==1) => 1 hier=top.t -000002 point: comment=(cyc[3]==1) => 1 hier=top.t %000005 if (t1 & t2 & 1'b1) $write(""); -000000 point: comment=(1'h1==0) => 0 hier=top.t -000004 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1 && 1'h1==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000009 if (t1 & t2 & 1'b0) $write(""); -000009 point: comment=(1'h0==0) => 0 hier=top.t -000004 point: comment=(t1==0) => 0 hier=top.t -000000 point: comment=(t1==1 && t2==1 && 1'h0==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000005 if (t1 & t2 & ONE) $write(""); -000000 point: comment=(ONE==0) => 0 hier=top.t -000004 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1 && ONE==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000009 if (t1 & t2 & ZERO) $write(""); -000009 point: comment=(ZERO==0) => 0 hier=top.t -000004 point: comment=(t1==0) => 0 hier=top.t -000000 point: comment=(t1==1 && t2==1 && ZERO==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000005 if (t1 && t2) begin -000004 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t $write(""); %000003 end else if (t1 || t2) begin -000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t -000003 point: comment=(t1==1) => 1 hier=top.t -000002 point: comment=(t2==1) => 1 hier=top.t $write(""); end %000005 if (invert(t1) && t2) $write(""); -000005 point: comment=(invert(t1)==0) => 0 hier=top.t -000002 point: comment=(invert(t1)==1 && t2==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t if (and_oper(t1, t2)) $write(""); %000005 if (t2 && t3) begin -000005 point: comment=(t2==0) => 0 hier=top.t -000002 point: comment=(t2==1 && t3==1) => 1 hier=top.t -000005 point: comment=(t3==0) => 0 hier=top.t %000001 if (t1 && t2) $write(""); -000001 point: comment=(t1==0) => 0 hier=top.t -000001 point: comment=(t1==1 && t2==1) => 1 hier=top.t -000000 point: comment=(t2==0) => 0 hier=top.t end if (0 == 1) begin for (int loop_var = 0; loop_var < 1; loop_var++) begin %000000 if (cyc[loop_var] && t2) $write(""); -000000 point: comment=(cyc[loop_var[4:0]+:1]==0) => 0 hier=top.t -000000 point: comment=(cyc[loop_var[4:0]+:1]==1 && t2==1) => 1 hier=top.t -000000 point: comment=(t2==0) => 0 hier=top.t end end // stop at the first layer even if there's more to find %000007 if ((cyc[3+32'(t1 && t2)+:2] == cyc[5+32'(t3 || t4)+:2]) || cyc[31]) $write(""); -000002 point: comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==0 && cyc[31]==0) => 0 hier=top.t -000007 point: comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==1) => 1 hier=top.t -000000 point: comment=(cyc[31]==1) => 1 hier=top.t // impossible branches and redundant terms %000005 if ((t1 && t2) && ~(t1 && t3) && (t1 || t4)) $write(""); -000003 point: comment=(t1==0 && t4==0) => 0 hier=top.t -000004 point: comment=(t1==0) => 0 hier=top.t -000000 point: comment=(t1==1 && t2==1 && t3==0 && t4==1) => 1 hier=top.t -000001 point: comment=(t1==1 && t2==1 && t3==0) => 1 hier=top.t -000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000005 if ((cyc[0] && cyc[1]) && ~(cyc[0] && cyc[2]) && (cyc[0] || cyc[3])) $write(""); -000003 point: comment=(cyc[0]==0 && cyc[3]==0) => 0 hier=top.t -000004 point: comment=(cyc[0]==0) => 0 hier=top.t -000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t -000001 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0) => 1 hier=top.t -000002 point: comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t -000005 point: comment=(cyc[1]==0) => 0 hier=top.t // demonstrate current limitations of term matching scheme %000005 if ((cyc[0] && cyc[1]) && ~(cyc[1-1] && cyc[2]) && (cyc[2-2] || cyc[3])) $write(""); -000002 point: comment=(cyc[(32'sh1 - 32'sh1)[4:0]+:1]==1 && cyc[2]==1) => 0 hier=top.t -000003 point: comment=(cyc[(32'sh2 - 32'sh2)[4:0]+:1]==0 && cyc[3]==0) => 0 hier=top.t -000004 point: comment=(cyc[0]==0) => 0 hier=top.t -000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[(32'sh1 - 32'sh1)[4:0]+:1]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t -000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[(32'sh1 - 32'sh1)[4:0]+:1]==0 && cyc[3]==1) => 1 hier=top.t -000001 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t -000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t -000005 point: comment=(cyc[1]==0) => 0 hier=top.t //verilator coverage_off if (t1 && t2) $write(""); //verilator coverage_on if ((~t1 && t2) %000004 || -000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t -000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t -000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t -000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t -000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t -000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t (~t3 && t4)) $write(""); // intentionally testing wonkified expression terms if ( cyc[ 0 %000005 ] & -000004 point: comment=(cyc[0]==0) => 0 hier=top.t -000002 point: comment=(cyc[0]==1 && cyc[1]==1) => 1 hier=top.t -000005 point: comment=(cyc[1]==0) => 0 hier=top.t cyc [1]) $write(""); // for now each ternary condition is considered in isolation %000005 other_int <= t1 ? t2 ? 1 : 2 : 3; -000004 point: comment=(t1==0) => 0 hier=top.t -000005 point: comment=(t1==1) => 1 hier=top.t // no expression coverage for multi-bit expressions if ((cyc[1:0] & cyc[3:2]) == 2'b11) $write(""); // truth table is too large %000001 if (^cyc[6:0]) $write(""); -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000001 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000001 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000001 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000001 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000001 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000001 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000001 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000001 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000001 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t // this one is too big even for t_cover_expr_max if (^cyc) $write(""); if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end always_comb begin %000005 if (t1 && t2) $write(""); -000005 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t end logic ta, tb, tc; initial begin cls obj = new; cls null_obj = null; int q[5]; int qv[$]; q = '{1, 2, 2, 4, 3}; // lambas not handled // NB: there is a bug w/ tracing find_first (maybe lambdas in general?) // tracing_off does not work around the bug qv = q.find_first with (item[0] & item[1]); ta = '1; tb = '0; tc = '0; %000001 while (ta || tb || tc) begin -000001 point: comment=(ta==0 && tb==0 && tc==0) => 0 hier=top.t -000000 point: comment=(ta==1) => 1 hier=top.t -000000 point: comment=(tb==1) => 1 hier=top.t -000000 point: comment=(tc==1) => 1 hier=top.t tc = tb; tb = ta; ta = '0; end if (!bit'(obj.randomize() with {x < 100;})) $write(""); if (null_obj != null && null_obj.x == 5) $write(""); end sub the_sub_1 (.p(t1), .q(t2)); sub the_sub_2 (.p(t3), .q(t4)); // TODO -- non-process expressions sub the_sub_3 (.p(t1 ? t2 : t3), .q(t4)); // TODO // pragma for expr coverage off / on // investigate cover point sorting in annotated source // consider reporting don't care terms // // Branches which are statically impossible to reach are still reported. // E.g. // -000000 point: comment=(t1=1 && t2=1 && 1'h0=1) => 1 hier=top.t // These could potentially be pruned, but they currently follow suit for // what branch coverage does. Perhaps a switch should be added to not // count statically impossible things. endmodule module sub ( input p, input q ); always_comb begin ~000019 if (p && q) $write(""); +000017 point: comment=(p==0) => 0 hier=top.t.the_sub_* -000002 point: comment=(p==1 && q==1) => 1 hier=top.t.the_sub_* +000019 point: comment=(q==0) => 0 hier=top.t.the_sub_* end endmodule interface intf(); logic t; endinterface verilator-5.044/test_regress/t/t_class_param_extends.py0000755000542200017500000000073415125463617024024 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_lint_iface_array_topmodule_bad.py0000755000542200017500000000076615125463617026203 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_typedef_iface_typedef7.v0000644000542200017500000000174015125463617024213 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // // Chained typedef aliases from an interface typedef // verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0h exp=%0h\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on interface x_if #( parameter int p_awidth = 4 ) (); typedef struct packed {logic [p_awidth-1:0] addr;} rq_t; endinterface module top (); x_if #(.p_awidth(16)) if0 (); // First alias of interface typedef typedef if0.rq_t my_rq_t; // Second alias of the alias typedef my_rq_t my_rq2_t; my_rq2_t rq; always_comb begin rq.addr = 'h1234; end initial begin #1; `checkh(rq.addr, 16'h1234); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_dpi_arg_output_type.cpp0000644000542200017500000006107015125463617024222 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2020 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include // clang-format off #if defined(NCSC) // Used by NC's svdpi.h to pick up svLogicVecVal with _.aval and _.bval fields, // rather than the IEEE 1800-2005 version which has _.a and _.b fields. # define DPI_COMPATIBILITY_VERSION_1800v2012 #endif #include "svdpi.h" #if defined(VERILATOR) // Verilator # include "Vt_dpi_arg_output_type__Dpi.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_SHORTREAL #elif defined(VCS) // VCS # include "../vc_hdrs.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_TIME #elif defined(NCSC) // NC # include "dpi-exp.h" # include "dpi-imp.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_TIME # define NO_INTEGER # define NO_SHORTREAL #elif defined(MS) // ModelSim # include "dpi.h" typedef int64_t sv_longint_t; typedef uint64_t sv_longint_unsigned_t; # else # error "Unknown simulator for DPI test" #endif // clang-format on //====================================================================== // Implementations of imported functions //====================================================================== void set_bvals(svLogicVecVal* v, unsigned n); void set_bvals(svLogicVecVal* v, unsigned n) { for (unsigned i = 0; i < n; i++) v[i].bval = 0; } // Basic types as per IEEE 1800-2023 35.5.6 void i_byte(char* o) { static int n = 0; *o = 10 - n++; } void i_byte_unsigned(unsigned char* o) { static int n = 0; *o = 20 - n++; } void i_shortint(short* o) { static int n = 0; *o = 30 - n++; } void i_shortint_unsigned(unsigned short* o) { static int n = 0; *o = 40 - n++; } void i_int(int* o) { static int n = 0; *o = 50 - n++; } void i_int_unsigned(unsigned* o) { static int n = 0; *o = 60 - n++; } void i_longint(sv_longint_t* o) { static int n = 0; *o = 70 - n++; } void i_longint_unsigned(sv_longint_unsigned_t* o) { static int n = 0; *o = 80 - n++; } #ifndef NO_TIME void i_time(svLogicVecVal* o) { static int n = 0; o[0].aval = 90 - n++; o[1].aval = 0; set_bvals(o, 2); } #endif #ifndef NO_INTEGER void i_integer(svLogicVecVal* o) { static int n = 0; o->aval = 100 - n++; set_bvals(o, 1); } #endif void i_real(double* o) { static int n = 0; *o = (-2.0 * n++ - 1.0) / 2.0; } #ifndef NO_SHORTREAL void i_shortreal(float* o) { static int n = 0; *o = (-4.0f * n++ - 1.0f) / 4.0f; } #endif void i_chandle(void** o) { static int n = 0; printf("i_chandle %d\n", n); *o = (n++ % 2) ? reinterpret_cast(&i_chandle) : NULL; } void i_string(const char** o) { static int n = 0; printf("i_string %d\n", n); *o = (n++ % 2) ? "Hello" : "World"; } void i_bit(svBit* o) { static int n = 0; printf("i_bit %d\n", n); *o = !(n++ % 2); } void i_logic(svLogic* o) { static int n = 0; printf("i_logic %d\n", n); *o = n++ % 2; } // Basic types via typedefs void i_byte_t(char* o) { static int n = 0; const char r = 10 - n; n += 2; *o = r; } void i_byte_unsigned_t(unsigned char* o) { static int n = 0; const unsigned char r = 20 - n; n += 2; *o = r; } void i_shortint_t(short* o) { static int n = 0; const short r = 30 - n; n += 2; *o = r; } void i_shortint_unsigned_t(unsigned short* o) { static int n = 0; const unsigned short r = 40 - n; n += 2; *o = r; } void i_int_t(int* o) { static int n = 0; const int r = 50 - n; n += 2; *o = r; } void i_int_unsigned_t(unsigned* o) { static int n = 0; const unsigned r = 60 - n; n += 2; *o = r; } void i_longint_t(sv_longint_t* o) { static int n = 0; const long long r = 70 - n; n += 2; *o = r; } void i_longint_unsigned_t(sv_longint_unsigned_t* o) { static int n = 0; const unsigned long long r = 80 - n; n += 2; *o = r; } #ifndef NO_TIME void i_time_t(svLogicVecVal* o) { static int n = 0; o[0].aval = 90 - n; o[1].aval = 0; set_bvals(o, 2); n += 2; } #endif #ifndef NO_INTEGER void i_integer_t(svLogicVecVal* o) { static int n = 0; o->aval = 100 - n; set_bvals(o, 1); n += 2; } #endif void i_real_t(double* o) { static int n = 0; const double r = (-2.0 * n - 1.0) / 2.0; n += 2; *o = r; } #ifndef NO_SHORTREAL void i_shortreal_t(float* o) { static int n = 0; const float r = (-4.0f * n - 1.0f) / 4.0f; n += 2; *o = r; } #endif void i_chandle_t(void** o) { static int n = 0; printf("i_chandle_t %d\n", n); *o = (n++ % 2) ? reinterpret_cast(&i_chandle) : NULL; } void i_string_t(const char** o) { static int n = 0; printf("i_string_t %d\n", n); *o = (n++ % 2) ? "Hello" : "World"; } void i_bit_t(svBit* o) { static int n = 0; printf("i_bit_t %d\n", n); *o = !(n++ % 2); } void i_logic_t(svLogic* o) { static int n = 0; printf("i_logic_t %d\n", n); *o = n++ % 2; } // 2-state packed arrays void i_array_2_state_1(svBitVecVal* o) { static int n = 0; printf("i_array_2_state_1 %d\n", n); *o = !(n++ % 2); } void i_array_2_state_32(svBitVecVal* o) { static int n = 0; printf("i_array_2_state_32 %d\n", n); *o = 0xffffffffU << n++; } void i_array_2_state_33(svBitVecVal* o) { static int n = 0; printf("i_array_2_state_33 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = 1; } void i_array_2_state_64(svBitVecVal* o) { static int n = 0; printf("i_array_2_state_64 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = -1; } void i_array_2_state_65(svBitVecVal* o) { static int n = 0; printf("i_array_2_state_65 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = -1; o[2] = 1; } void i_array_2_state_128(svBitVecVal* o) { static int n = 0; printf("i_array_2_state_128 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = -1; o[2] = -1; o[3] = -1; } // 2-state packed structures void i_struct_2_state_1(svBitVecVal* o) { static int n = 0; printf("i_struct_2_state_1 %d\n", n); *o = !(n++ % 2); } void i_struct_2_state_32(svBitVecVal* o) { static int n = 0; printf("i_struct_2_state_32 %d\n", n); *o = 0xffffffffU << n++; } void i_struct_2_state_33(svBitVecVal* o) { static int n = 0; printf("i_struct_2_state_33 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = 1; } void i_struct_2_state_64(svBitVecVal* o) { static int n = 0; printf("i_struct_2_state_64 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = -1; } void i_struct_2_state_65(svBitVecVal* o) { static int n = 0; printf("i_struct_2_state_65 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = -1; o[2] = 1; } void i_struct_2_state_128(svBitVecVal* o) { static int n = 0; printf("i_struct_2_state_128 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = -1; o[2] = -1; o[3] = -1; } // 2-state packed unions void i_union_2_state_1(svBitVecVal* o) { static int n = 0; printf("i_union_2_state_1 %d\n", n); *o = !(n++ % 2); } void i_union_2_state_32(svBitVecVal* o) { static int n = 0; printf("i_union_2_state_32 %d\n", n); *o = 0xffffffffU << n++; } void i_union_2_state_33(svBitVecVal* o) { static int n = 0; printf("i_union_2_state_33 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = 1; } void i_union_2_state_64(svBitVecVal* o) { static int n = 0; printf("i_union_2_state_64 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = -1; } void i_union_2_state_65(svBitVecVal* o) { static int n = 0; printf("i_union_2_state_65 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = -1; o[2] = 1; } void i_union_2_state_128(svBitVecVal* o) { static int n = 0; printf("i_union_2_state_128 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = -1; o[2] = -1; o[3] = -1; } // 4-state packed arrays void i_array_4_state_1(svLogicVecVal* o) { static int n = 0; printf("i_array_4_state_1 %d\n", n); o->aval = !(n++ % 2); set_bvals(o, 1); } void i_array_4_state_32(svLogicVecVal* o) { static int n = 0; printf("i_array_4_state_32 %d\n", n); o->aval = 0xffffffffU << n++; set_bvals(o, 1); } void i_array_4_state_33(svLogicVecVal* o) { static int n = 0; printf("i_array_4_state_33 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = 1; set_bvals(o, 2); } void i_array_4_state_64(svLogicVecVal* o) { static int n = 0; printf("i_array_4_state_64 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = -1; set_bvals(o, 2); } void i_array_4_state_65(svLogicVecVal* o) { static int n = 0; printf("i_array_4_state_65 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = -1; o[2].aval = 1; set_bvals(o, 3); } void i_array_4_state_128(svLogicVecVal* o) { static int n = 0; printf("i_array_4_state_128 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = -1; o[2].aval = -1; o[3].aval = -1; set_bvals(o, 4); } // 4-state packed structures void i_struct_4_state_1(svLogicVecVal* o) { static int n = 0; printf("i_struct_4_state_1 %d\n", n); o->aval = !(n++ % 2); set_bvals(o, 1); } void i_struct_4_state_32(svLogicVecVal* o) { static int n = 0; printf("i_struct_4_state_32 %d\n", n); o->aval = 0xffffffffU << n++; set_bvals(o, 1); } void i_struct_4_state_33(svLogicVecVal* o) { static int n = 0; printf("i_struct_4_state_33 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = 1; set_bvals(o, 2); } void i_struct_4_state_64(svLogicVecVal* o) { static int n = 0; printf("i_struct_4_state_64 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = -1; set_bvals(o, 2); } void i_struct_4_state_65(svLogicVecVal* o) { static int n = 0; printf("i_struct_4_state_65 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = -1; o[2].aval = 1; set_bvals(o, 3); } void i_struct_4_state_128(svLogicVecVal* o) { static int n = 0; printf("i_struct_4_state_128 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = -1; o[2].aval = -1; o[3].aval = -1; set_bvals(o, 4); } // 4-state packed unions void i_union_4_state_1(svLogicVecVal* o) { static int n = 0; printf("i_union_4_state_1 %d\n", n); o->aval = !(n++ % 2); set_bvals(o, 1); } void i_union_4_state_32(svLogicVecVal* o) { static int n = 0; printf("i_union_4_state_32 %d\n", n); o->aval = 0xffffffffU << n++; set_bvals(o, 1); } void i_union_4_state_33(svLogicVecVal* o) { static int n = 0; printf("i_union_4_state_33 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = 1; set_bvals(o, 2); } void i_union_4_state_64(svLogicVecVal* o) { static int n = 0; printf("i_union_4_state_64 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = -1; set_bvals(o, 2); } void i_union_4_state_65(svLogicVecVal* o) { static int n = 0; printf("i_union_4_state_65 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = -1; o[2].aval = 1; set_bvals(o, 3); } void i_union_4_state_128(svLogicVecVal* o) { static int n = 0; printf("i_union_4_state_128 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = -1; o[2].aval = -1; o[3].aval = -1; set_bvals(o, 4); } //====================================================================== // Check exported functions //====================================================================== #define stop() \ do { \ printf(__FILE__ ":%d Bad value\n", __LINE__); \ abort(); \ } while (0) void check_bvals(const svLogicVecVal* v, unsigned n); void check_bvals(const svLogicVecVal* v, unsigned n) { for (unsigned i = 0; i < n; i++) { if (v[i].bval != 0) { printf(__FILE__ ":%d Bad svLogicVecVal bval\n", __LINE__); abort(); } } } void check_exports() { static unsigned n = 0; char x_byte; unsigned char x_byte_unsigned; short x_shortint; unsigned short x_shortint_unsigned; int x_int; unsigned x_int_unsigned; sv_longint_t x_longint; sv_longint_unsigned_t x_longint_unsigned; #ifndef NO_TIME svLogicVecVal x_time[2]; #endif #ifndef NO_INTEGER svLogicVecVal x_integer[1]; #endif double x_real; #ifndef NO_SHORTREAL float x_shortreal; #endif void* x_chandle; const char* x_string; svBit x_bit; svLogic x_logic; char x_byte_t; unsigned char x_byte_unsigned_t; short x_shortint_t; unsigned short x_shortint_unsigned_t; int x_int_t; unsigned x_int_unsigned_t; sv_longint_t x_longint_t; sv_longint_unsigned_t x_longint_unsigned_t; #ifndef NO_TIME svLogicVecVal x_time_t[2]; #endif #ifndef NO_INTEGER svLogicVecVal x_integer_t[1]; #endif double x_real_t; #ifndef NO_SHORTREAL float x_shortreal_t; #endif void* x_chandle_t; const char* x_string_t; svBit x_bit_t; svLogic x_logic_t; svBitVecVal x_array_2_state_1[1]; svBitVecVal x_array_2_state_32[1]; svBitVecVal x_array_2_state_33[2]; svBitVecVal x_array_2_state_64[2]; svBitVecVal x_array_2_state_65[3]; svBitVecVal x_array_2_state_128[4]; svBitVecVal x_struct_2_state_1[1]; svBitVecVal x_struct_2_state_32[1]; svBitVecVal x_struct_2_state_33[2]; svBitVecVal x_struct_2_state_64[2]; svBitVecVal x_struct_2_state_65[3]; svBitVecVal x_struct_2_state_128[4]; svBitVecVal x_union_2_state_1[1]; svBitVecVal x_union_2_state_32[1]; svBitVecVal x_union_2_state_33[2]; svBitVecVal x_union_2_state_64[2]; svBitVecVal x_union_2_state_65[3]; svBitVecVal x_union_2_state_128[4]; svLogicVecVal x_array_4_state_1[1]; svLogicVecVal x_array_4_state_32[1]; svLogicVecVal x_array_4_state_33[2]; svLogicVecVal x_array_4_state_64[2]; svLogicVecVal x_array_4_state_65[3]; svLogicVecVal x_array_4_state_128[4]; svLogicVecVal x_struct_4_state_1[1]; svLogicVecVal x_struct_4_state_32[1]; svLogicVecVal x_struct_4_state_33[2]; svLogicVecVal x_struct_4_state_64[2]; svLogicVecVal x_struct_4_state_65[3]; svLogicVecVal x_struct_4_state_128[4]; svLogicVecVal x_union_4_state_1[1]; svLogicVecVal x_union_4_state_32[1]; svLogicVecVal x_union_4_state_33[2]; svLogicVecVal x_union_4_state_64[2]; svLogicVecVal x_union_4_state_65[3]; svLogicVecVal x_union_4_state_128[4]; // Basic types as per IEEE 1800-2023 35.5.6 e_byte(&x_byte); if (x_byte != 10 + n) stop(); e_byte_unsigned(&x_byte_unsigned); if (x_byte_unsigned != 20 + n) stop(); e_shortint(&x_shortint); if (x_shortint != 30 + n) stop(); e_shortint_unsigned(&x_shortint_unsigned); if (x_shortint_unsigned != 40 + n) stop(); e_int(&x_int); if (x_int != 50 + n) stop(); e_int_unsigned(&x_int_unsigned); if (x_int_unsigned != 60 + n) stop(); e_longint(&x_longint); if (x_longint != 70 + n) stop(); e_longint_unsigned(&x_longint_unsigned); if (x_longint_unsigned != 80 + n) stop(); #ifndef NO_TIME e_time(x_time); if (x_time[0].aval != 90 + n || x_time[1].aval != 0) stop(); check_bvals(x_time, 2); #endif #ifndef NO_INTEGER e_integer(x_integer); if (x_integer[0].aval != 100 + n) stop(); check_bvals(x_integer, 1); #endif e_real(&x_real); if (x_real != 1.0 * n + 0.5) stop(); #ifndef NO_SHORTREAL e_shortreal(&x_shortreal); if (x_shortreal != 1.0f * n + 0.25f) stop(); #endif e_chandle(&x_chandle); if (x_chandle != NULL) stop(); e_string(&x_string); if ((n % 2) == 0) { if (std::strcmp(x_string, "Hello") != 0) stop(); } else { if (std::strcmp(x_string, "World") != 0) stop(); } e_bit(&x_bit); if (x_bit != (n % 2)) stop(); e_logic(&x_logic); if (x_logic != !(n % 2)) stop(); // Basic types via tyepdef e_byte_t(&x_byte_t); if (x_byte_t != 10 + 2 * n) stop(); e_byte_unsigned_t(&x_byte_unsigned_t); if (x_byte_unsigned_t != 20 + 2 * n) stop(); e_shortint_t(&x_shortint_t); if (x_shortint_t != 30 + 2 * n) stop(); e_shortint_unsigned_t(&x_shortint_unsigned_t); if (x_shortint_unsigned_t != 40 + 2 * n) stop(); e_int_t(&x_int_t); if (x_int_t != 50 + 2 * n) stop(); e_int_unsigned_t(&x_int_unsigned_t); if (x_int_unsigned_t != 60 + 2 * n) stop(); e_longint_t(&x_longint_t); if (x_longint_t != 70 + 2 * n) stop(); e_longint_unsigned_t(&x_longint_unsigned_t); if (x_longint_unsigned_t != 80 + 2 * n) stop(); #ifndef NO_TIME e_time_t(x_time_t); if (x_time_t[0].aval != 90 + 2 * n || x_time_t[1].aval != 0) stop(); check_bvals(x_time_t, 2); #endif #ifndef NO_INTEGER e_integer_t(x_integer_t); if (x_integer_t[0].aval != 100 + 2 * n) stop(); check_bvals(x_integer_t, 1); #endif e_real_t(&x_real_t); if (x_real_t != 1.0 * (2 * n) + 0.5) stop(); #ifndef NO_SHORTREAL e_shortreal_t(&x_shortreal_t); if (x_shortreal_t != 1.0f * (2 * n) + 0.25f) stop(); #endif e_chandle_t(&x_chandle_t); if (x_chandle_t != NULL) stop(); e_string_t(&x_string_t); if ((n % 2) == 0) { if (std::strcmp(x_string_t, "Hello") != 0) stop(); } else { if (std::strcmp(x_string_t, "World") != 0) stop(); } e_bit_t(&x_bit_t); if (x_bit_t != (n % 2)) stop(); e_logic_t(&x_logic_t); if (x_logic_t != !(n % 2)) stop(); const int m = n == 0 ? 0 : n - 1; // 2-state packed arrays e_array_2_state_1(x_array_2_state_1); if (x_array_2_state_1[0] != (n % 2)) stop(); e_array_2_state_32(x_array_2_state_32); if (x_array_2_state_32[0] != 0xffffffff >> n) stop(); e_array_2_state_33(x_array_2_state_33); if (x_array_2_state_33[1] != 1 >> n) stop(); if (x_array_2_state_33[0] != 0xffffffff >> m) stop(); e_array_2_state_64(x_array_2_state_64); if (x_array_2_state_64[1] != 0xffffffff >> n) stop(); if (x_array_2_state_64[0] != 0xffffffff) stop(); e_array_2_state_65(x_array_2_state_65); if (x_array_2_state_65[2] != 1 >> n) stop(); if (x_array_2_state_65[1] != 0xffffffff >> m) stop(); if (x_array_2_state_65[0] != 0xffffffff) stop(); e_array_2_state_128(x_array_2_state_128); if (x_array_2_state_128[3] != 0xffffffff >> n) stop(); if (x_array_2_state_128[2] != 0xffffffff) stop(); if (x_array_2_state_128[1] != 0xffffffff) stop(); if (x_array_2_state_64[0] != 0xffffffff) stop(); // 2-state packed structures e_struct_2_state_1(x_struct_2_state_1); if (x_struct_2_state_1[0] != (n % 2)) stop(); e_struct_2_state_32(x_struct_2_state_32); if (x_struct_2_state_32[0] != 0xffffffff >> n) stop(); e_struct_2_state_33(x_struct_2_state_33); if (x_struct_2_state_33[1] != 1 >> n) stop(); if (x_struct_2_state_33[0] != 0xffffffff >> m) stop(); e_struct_2_state_64(x_struct_2_state_64); if (x_struct_2_state_64[1] != 0xffffffff >> n) stop(); if (x_struct_2_state_64[0] != 0xffffffff) stop(); e_struct_2_state_65(x_struct_2_state_65); if (x_struct_2_state_65[2] != 1 >> n) stop(); if (x_struct_2_state_65[1] != 0xffffffff >> m) stop(); if (x_struct_2_state_65[0] != 0xffffffff) stop(); e_struct_2_state_128(x_struct_2_state_128); if (x_struct_2_state_128[3] != 0xffffffff >> n) stop(); if (x_struct_2_state_128[2] != 0xffffffff) stop(); if (x_struct_2_state_128[1] != 0xffffffff) stop(); if (x_struct_2_state_64[0] != 0xffffffff) stop(); // 2-state packed unions e_union_2_state_1(x_union_2_state_1); if (x_union_2_state_1[0] != (n % 2)) stop(); e_union_2_state_32(x_union_2_state_32); if (x_union_2_state_32[0] != 0xffffffff >> n) stop(); e_union_2_state_33(x_union_2_state_33); if (x_union_2_state_33[1] != 1 >> n) stop(); if (x_union_2_state_33[0] != 0xffffffff >> m) stop(); e_union_2_state_64(x_union_2_state_64); if (x_union_2_state_64[1] != 0xffffffff >> n) stop(); if (x_union_2_state_64[0] != 0xffffffff) stop(); e_union_2_state_65(x_union_2_state_65); if (x_union_2_state_65[2] != 1 >> n) stop(); if (x_union_2_state_65[1] != 0xffffffff >> m) stop(); if (x_union_2_state_65[0] != 0xffffffff) stop(); e_union_2_state_128(x_union_2_state_128); if (x_union_2_state_128[3] != 0xffffffff >> n) stop(); if (x_union_2_state_128[2] != 0xffffffff) stop(); if (x_union_2_state_128[1] != 0xffffffff) stop(); if (x_union_2_state_64[0] != 0xffffffff) stop(); // 4-state packed arrays e_array_4_state_1(x_array_4_state_1); if (x_array_4_state_1[0].aval != (n % 2)) stop(); e_array_4_state_32(x_array_4_state_32); if (x_array_4_state_32[0].aval != 0xffffffff >> n) stop(); e_array_4_state_33(x_array_4_state_33); if (x_array_4_state_33[1].aval != 1 >> n) stop(); if (x_array_4_state_33[0].aval != 0xffffffff >> m) stop(); e_array_4_state_64(x_array_4_state_64); if (x_array_4_state_64[1].aval != 0xffffffff >> n) stop(); if (x_array_4_state_64[0].aval != 0xffffffff) stop(); e_array_4_state_65(x_array_4_state_65); if (x_array_4_state_65[2].aval != 1 >> n) stop(); if (x_array_4_state_65[1].aval != 0xffffffff >> m) stop(); if (x_array_4_state_65[0].aval != 0xffffffff) stop(); e_array_4_state_128(x_array_4_state_128); if (x_array_4_state_128[3].aval != 0xffffffff >> n) stop(); if (x_array_4_state_128[2].aval != 0xffffffff) stop(); if (x_array_4_state_128[1].aval != 0xffffffff) stop(); if (x_array_4_state_64[0].aval != 0xffffffff) stop(); check_bvals(x_array_4_state_1, 1); check_bvals(x_array_4_state_32, 1); check_bvals(x_array_4_state_33, 2); check_bvals(x_array_4_state_64, 2); check_bvals(x_array_4_state_65, 3); check_bvals(x_array_4_state_128, 4); // 4-state packed structures e_struct_4_state_1(x_struct_4_state_1); if (x_struct_4_state_1[0].aval != (n % 2)) stop(); e_struct_4_state_32(x_struct_4_state_32); if (x_struct_4_state_32[0].aval != 0xffffffff >> n) stop(); e_struct_4_state_33(x_struct_4_state_33); if (x_struct_4_state_33[1].aval != 1 >> n) stop(); if (x_struct_4_state_33[0].aval != 0xffffffff >> m) stop(); e_struct_4_state_64(x_struct_4_state_64); if (x_struct_4_state_64[1].aval != 0xffffffff >> n) stop(); if (x_struct_4_state_64[0].aval != 0xffffffff) stop(); e_struct_4_state_65(x_struct_4_state_65); if (x_struct_4_state_65[2].aval != 1 >> n) stop(); if (x_struct_4_state_65[1].aval != 0xffffffff >> m) stop(); if (x_struct_4_state_65[0].aval != 0xffffffff) stop(); e_struct_4_state_128(x_struct_4_state_128); if (x_struct_4_state_128[3].aval != 0xffffffff >> n) stop(); if (x_struct_4_state_128[2].aval != 0xffffffff) stop(); if (x_struct_4_state_128[1].aval != 0xffffffff) stop(); if (x_struct_4_state_64[0].aval != 0xffffffff) stop(); check_bvals(x_struct_4_state_1, 1); check_bvals(x_struct_4_state_32, 1); check_bvals(x_struct_4_state_33, 2); check_bvals(x_struct_4_state_64, 2); check_bvals(x_struct_4_state_65, 3); check_bvals(x_struct_4_state_128, 4); // 4-state packed unions e_union_4_state_1(x_union_4_state_1); if (x_union_4_state_1[0].aval != (n % 2)) stop(); e_union_4_state_32(x_union_4_state_32); if (x_union_4_state_32[0].aval != 0xffffffff >> n) stop(); e_union_4_state_33(x_union_4_state_33); if (x_union_4_state_33[1].aval != 1 >> n) stop(); if (x_union_4_state_33[0].aval != 0xffffffff >> m) stop(); e_union_4_state_64(x_union_4_state_64); if (x_union_4_state_64[1].aval != 0xffffffff >> n) stop(); if (x_union_4_state_64[0].aval != 0xffffffff) stop(); e_union_4_state_65(x_union_4_state_65); if (x_union_4_state_65[2].aval != 1 >> n) stop(); if (x_union_4_state_65[1].aval != 0xffffffff >> m) stop(); if (x_union_4_state_65[0].aval != 0xffffffff) stop(); e_union_4_state_128(x_union_4_state_128); if (x_union_4_state_128[3].aval != 0xffffffff >> n) stop(); if (x_union_4_state_128[2].aval != 0xffffffff) stop(); if (x_union_4_state_128[1].aval != 0xffffffff) stop(); if (x_union_4_state_64[0].aval != 0xffffffff) stop(); check_bvals(x_union_4_state_1, 1); check_bvals(x_union_4_state_32, 1); check_bvals(x_union_4_state_33, 2); check_bvals(x_union_4_state_64, 2); check_bvals(x_union_4_state_65, 3); check_bvals(x_union_4_state_128, 4); n++; } verilator-5.044/test_regress/t/t_sys_readmem_bad_addr.v0000644000542200017500000000061315125463617023723 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [175:0] hex [15:0]; initial begin $readmemh("t/t_sys_readmem_bad_addr.mem", hex); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_module_input_default_value_noinl.py0000755000542200017500000000105315125463617026603 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_module_input_default_value.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_mem_fifo.py0000755000542200017500000000073415125463617021566 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_math_synmul.py0000755000542200017500000000102515125463617022337 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-Wno-UNOPTTHREADS"]) test.execute(check_finished=True) test.passes() verilator-5.044/test_regress/t/t_case_zx_bad.v0000644000542200017500000000070015125463617022052 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs value ); input [3:0] value; always @ (/*AS*/value) begin casez (value) 4'b0000: $stop; 4'b1xxx: $stop; default: $stop; endcase end endmodule verilator-5.044/test_regress/t/t_math_signed6.v0000644000542200017500000000171615125463617022170 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t; // signed source logic signed [8-1:0] src; // destination structure struct packed { logic signed [16-1:0] s; logic unsigned [16-1:0] u; } dst; initial begin // bug882 // verilator lint_off WIDTH src = 8'sh05; dst = '{s: src, u: src}; `checkh (dst.s, 16'h0005); `checkh (dst.u, 16'h0005); src = 8'shf5; dst = '{s: src, u: src}; `checkh (dst.s, 16'hfff5); `checkh (dst.u, 16'hfff5); // verilator lint_on WIDTH $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.044/test_regress/t/t_const_number_bad.out0000644000542200017500000000273115125463617023464 0ustar mahmoudyfreeshell%Error: t/t_const_number_bad.v:9:29: Number is missing value digits: 32'd 9 | parameter integer FOO2 = 32'd-6; | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_const_number_bad.v:10:29: Number is missing value digits: 32'd 10 | parameter integer FOO3 = 32'd; | ^~~~ %Error: t/t_const_number_bad.v:11:29: Number is missing value digits: 32'h 11 | parameter integer FOO4 = 32'h; | ^~~~ %Error: t/t_const_number_bad.v:13:29: Illegal character in binary constant: 2 13 | parameter integer FOO5 = 32'b2; | ^~~~~ %Error: t/t_const_number_bad.v:14:29: Illegal character in octal constant 14 | parameter integer FOO6 = 32'o8; | ^~~~~ %Error: t/t_const_number_bad.v:17:33: Illegal character in binary constant: 4 17 | parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; | ^~~~~~ %Error: t/t_const_number_bad.v:17:33: Too many digits for 1 bit number: '1'b1?4' 17 | parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; | ^~~~~~ %Error: t/t_const_number_bad.v:17:39: syntax error, unexpected INTEGER NUMBER, expecting ';' 17 | parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; | ^~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_trace_two_hdrfst_cc.py0000755000542200017500000000246215125463617024013 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test tracing with two models instanced import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t_trace_two_a.v" test.pli_filename = "t/t_trace_two_cc.cpp" test.compile(make_main=False, verilator_make_gmake=False, top_filename='t_trace_two_b.v', vm_prefix='Vt_trace_two_b', verilator_flags2=['--trace-fst --trace-threads 1']) test.run(logfile=test.obj_dir + "/make_first_ALL.log", cmd=[ os.environ["MAKE"], "-C", "" + test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp" ]) test.compile( make_main=False, top_filename='t_trace_two_a.v', make_flags=['CPPFLAGS_ADD="-DTEST_HDR_TRACE=1 -DTEST_FST=1"'], verilator_flags2=['-exe', '--trace-fst --trace-threads 1', '-DTEST_FST', test.pli_filename]) test.execute() if test.vlt_all: test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_langext_order_sub.v0000644000542200017500000000055215125463617023323 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // A test of the +verilog2001ext+ and +verilog2005ext+ flags. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off SYMRSVDWORD module t_langext_order_sub(input do); endmodule verilator-5.044/test_regress/t/t_queue_method_bad.py0000755000542200017500000000076315125463617023301 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.044/test_regress/t/t_flag_language_bad.out0000644000542200017500000000025015125463617023534 0ustar mahmoudyfreeshell%Error: Unknown language specified: 1-2-3-4 ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.044/test_regress/t/t_queue_void_ops.py0000755000542200017500000000073415125463617023033 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.044/test_regress/t/t_disable_fork_notiming.out0000644000542200017500000000054415125463617024510 0ustar mahmoudyfreeshell%Error-NOTIMING: t/t_disable_fork_notiming.v:8:12: Support for disable fork statement requires --timing : ... note: In instance 't' 8 | initial disable fork; | ^~~~~~~ ... For error description see https://verilator.org/warn/NOTIMING?v=latest %Error: Exiting due to verilator-5.044/test_regress/t/t_lint_vcmarker_bad.out0000644000542200017500000000075715125463617023634 0ustar mahmoudyfreeshell%Error: t/t_lint_vcmarker_bad.v:9:1: Version control conflict marker in file 9 | <<<<<<< HEAD | ^~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_lint_vcmarker_bad.v:11:1: Version control conflict marker in file 11 | ======= | ^~~~~~~~~~~ %Error: t/t_lint_vcmarker_bad.v:13:1: Version control conflict marker in file 13 | >>>>>>> MERGE | ^~~~~~~~~~~~~~~~ %Error: Exiting due to verilator-5.044/test_regress/t/t_class_nested.py0000755000542200017500000000077515125463617022461 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--exe --main"]) test.execute() test.passes() verilator-5.044/test_regress/t/t_timing_always.v0000644000542200017500000000201615125463617022461 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `ifdef TEST_VERBOSE `define WRITE_VERBOSE(args) $write args `else `define WRITE_VERBOSE(args) `endif module t; bit clk = 0; always #3 clk = ~clk; bit flag_a; bit flag_b; always @(posedge clk) begin `WRITE_VERBOSE(("[%0t] b <= 0\n", $time)); flag_b <= 1'b0; #2 `WRITE_VERBOSE(("[%0t] a <= 1\n", $time)); flag_a <= 1'b1; #2 `WRITE_VERBOSE(("[%0t] b <= 1\n", $time)); flag_b <= 1'b1; end always @(flag_a) if ($time > 0) begin #1 `WRITE_VERBOSE(("[%0t] Checking if b == 0\n", $time)); if (flag_b !== 1'b0) $stop; #2 `WRITE_VERBOSE(("[%0t] Checking if b == 1\n", $time)); if (flag_b !== 1'b1) $stop; #10 $write("*-* All Finished *-*\n"); $finish; end initial #20 $stop; // timeout endmodule verilator-5.044/test_regress/t/t_timing_trace_fst.py0000755000542200017500000000117715125463617023330 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_timing_trace.v" test.compile(verilator_flags2=["--binary --trace-fst -Wno-MINTYPMAXDLY"]) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.044/test_regress/t/uvm/0000755000542200017500000000000015125463617017710 5ustar mahmoudyfreeshellverilator-5.044/test_regress/t/uvm/uvm_pkg_all_v2017_1_0_nodpi.svh0000644000542200017500000566545715125463617025455 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Concatenated UVM header for internal testing // SPDX-License-Identifier: Apache-2.0 //---------------------------------------------------------------------- // To recreate: // Using verilator_ext_tests: // t_uvm_hello_v2017_1_0_nodpi --gold // //---------------------------------------------------------------------- // Copyright 2007-2011 Mentor Graphics Corporation // Copyright 2011 Synopsys, Inc. // Copyright 2007-2018 Cadence Design Systems, Inc. // Copyright 2013 NVIDIA Corporation // All Rights Reserved Worldwide // // Licensed under the Apache License, Version 2.0 (the // "License"); you may not use this file except in // compliance with the License. You may obtain a copy of // the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in // writing, software distributed under the License is // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See // the License for the specific language governing // permissions and limitations under the License. //---------------------------------------------------------------------- `define UVM_NO_DPI `define UVM_PKG_SV `define UVM_MACROS_SVH `define UVM_STRING_QUEUE_STREAMING_PACK(q) uvm_pkg::m_uvm_string_queue_join(q) `define uvm_typename(X) $typename(X) `define uvm_delay(TIME) #(TIME); `define UVM_VERSION_DEFINES_SVH `define UVM_VERSION 2016 `define UVM_GLOBAL_DEFINES_SVH `define UVM_MAX_STREAMBITS 4096 `define UVM_PACKER_MAX_BYTES `UVM_MAX_STREAMBITS `define UVM_DEFAULT_TIMEOUT 9200s `define UVM_MESSAGE_DEFINES_SVH `define UVM_LINE_WIDTH 120 `define UVM_NUM_LINES 120 `define uvm_file `__FILE__ `define uvm_line `__LINE__ `define uvm_info(ID, MSG, VERBOSITY) \ begin \ if (uvm_report_enabled(VERBOSITY,UVM_INFO,ID)) \ uvm_report_info (ID, MSG, VERBOSITY, `uvm_file, `uvm_line, "", 1); \ end `define uvm_warning(ID, MSG) \ begin \ if (uvm_report_enabled(UVM_NONE,UVM_WARNING,ID)) \ uvm_report_warning (ID, MSG, UVM_NONE, `uvm_file, `uvm_line, "", 1); \ end `define uvm_error(ID, MSG) \ begin \ if (uvm_report_enabled(UVM_NONE,UVM_ERROR,ID)) \ uvm_report_error (ID, MSG, UVM_NONE, `uvm_file, `uvm_line, "", 1); \ end `define uvm_fatal(ID, MSG) \ begin \ if (uvm_report_enabled(UVM_NONE,UVM_FATAL,ID)) \ uvm_report_fatal (ID, MSG, UVM_NONE, `uvm_file, `uvm_line, "", 1); \ end `define uvm_info_context(ID, MSG, VERBOSITY, RO) \ begin \ if (RO.uvm_report_enabled(VERBOSITY,UVM_INFO,ID)) \ RO.uvm_report_info (ID, MSG, VERBOSITY, `uvm_file, `uvm_line, "", 1); \ end `define uvm_warning_context(ID, MSG, RO) \ begin \ if (RO.uvm_report_enabled(UVM_NONE,UVM_WARNING,ID)) \ RO.uvm_report_warning (ID, MSG, UVM_NONE, `uvm_file, `uvm_line, "", 1); \ end `define uvm_error_context(ID, MSG, RO) \ begin \ if (RO.uvm_report_enabled(UVM_NONE,UVM_ERROR,ID)) \ RO.uvm_report_error (ID, MSG, UVM_NONE, `uvm_file, `uvm_line, "", 1); \ end `define uvm_fatal_context(ID, MSG, RO) \ begin \ if (RO.uvm_report_enabled(UVM_NONE,UVM_FATAL,ID)) \ RO.uvm_report_fatal (ID, MSG, UVM_NONE, `uvm_file, `uvm_line, "", 1); \ end `define uvm_message_begin(SEVERITY, ID, MSG, VERBOSITY, FILE, LINE, RM) \ begin \ if (uvm_report_enabled(VERBOSITY,SEVERITY,ID)) begin \ uvm_report_message __uvm_msg; \ if (RM == null) RM = uvm_report_message::new_report_message(); \ __uvm_msg = RM; \ __uvm_msg.set_report_message(SEVERITY, ID, MSG, VERBOSITY, FILE, LINE, ""); `define uvm_message_end \ uvm_process_report_message(__uvm_msg); \ end \ end `define uvm_message_context_begin(SEVERITY, ID, MSG, VERBOSITY, FILE, LINE, RO, RM) \ begin \ uvm_report_object __report_object; \ __report_object = RO; \ if (__report_object.uvm_report_enabled(VERBOSITY,SEVERITY,ID)) begin \ uvm_report_message __uvm_msg; \ if (RM == null) RM = uvm_report_message::new_report_message(); \ __uvm_msg = RM; \ __uvm_msg.set_report_message(SEVERITY, ID, MSG, VERBOSITY, FILE, LINE, ""); `define uvm_message_context_end \ __report_object.uvm_process_report_message(__uvm_msg); \ end \ end `define uvm_info_begin(ID, MSG, VERBOSITY, RM = __uvm_msg) \ `uvm_message_begin(UVM_INFO, ID, MSG, VERBOSITY, `uvm_file, `uvm_line, RM) `define uvm_info_end \ `uvm_message_end `define uvm_warning_begin(ID, MSG, RM = __uvm_msg) \ `uvm_message_begin(UVM_WARNING, ID, MSG, UVM_NONE, `uvm_file, `uvm_line, RM) `define uvm_warning_end \ `uvm_message_end `define uvm_error_begin(ID, MSG, RM = __uvm_msg) \ `uvm_message_begin(UVM_ERROR, ID, MSG, UVM_NONE, `uvm_file, `uvm_line, RM) `define uvm_error_end \ `uvm_message_end `define uvm_fatal_begin(ID, MSG, RM = __uvm_msg) \ `uvm_message_begin(UVM_FATAL, ID, MSG, UVM_NONE, `uvm_file, `uvm_line, RM) `define uvm_fatal_end \ `uvm_message_end `define uvm_info_context_begin(ID, MSG, VERBOSITY, RO, RM = __uvm_msg) \ `uvm_message_context_begin(UVM_INFO, ID, MSG, VERBOSITY, `uvm_file, `uvm_line, RO, RM) `define uvm_info_context_end \ `uvm_message_context_end `define uvm_warning_context_begin(ID, MSG, RO, RM = __uvm_msg) \ `uvm_message_context_begin(UVM_WARNING, ID, MSG, UVM_NONE, `uvm_file, `uvm_line, RO, RM) `define uvm_warning_context_end \ `uvm_message_context_end `define uvm_error_context_begin(ID, MSG, RO, RM = __uvm_msg) \ `uvm_message_context_begin(UVM_ERROR, ID, MSG, UVM_NONE, `uvm_file, `uvm_line, RO, RM) `define uvm_error_context_end \ `uvm_message_context_end `define uvm_fatal_context_begin(ID, MSG, RO, RM = __uvm_msg) \ `uvm_message_context_begin(UVM_FATAL, ID, MSG, UVM_NONE, `uvm_file, `uvm_line, RO, RM) `define uvm_fatal_context_end \ `uvm_message_context_end `define uvm_message_add_tag(NAME, VALUE, ACTION=(UVM_LOG|UVM_RM_RECORD)) \ __uvm_msg.add_string(NAME, VALUE, ACTION); `define uvm_message_add_int(VAR, RADIX, LABEL="", ACTION=(UVM_LOG|UVM_RM_RECORD)) \ if (LABEL == "") \ __uvm_msg.add_int(`"VAR`", VAR, $bits(VAR), RADIX, ACTION); \ else \ __uvm_msg.add_int(LABEL, VAR, $bits(VAR), RADIX, ACTION); `define uvm_message_add_string(VAR, LABEL="", ACTION=(UVM_LOG|UVM_RM_RECORD)) \ if (LABEL == "") \ __uvm_msg.add_string(`"VAR`", VAR, ACTION); \ else \ __uvm_msg.add_string(LABEL, VAR, ACTION); `define uvm_message_add_object(VAR, LABEL="", ACTION=(UVM_LOG|UVM_RM_RECORD)) \ if (LABEL == "") \ __uvm_msg.add_object(`"VAR`", VAR, ACTION); \ else \ __uvm_msg.add_object(LABEL, VAR, ACTION); `define UVM_PHASE_DEFINES_SVH `define m_uvm_task_phase(PHASE,COMP,PREFIX) \ class PREFIX``PHASE``_phase extends uvm_task_phase; \ virtual task exec_task(uvm_component comp, uvm_phase phase); \ COMP comp_; \ if ($cast(comp_,comp)) \ comp_.``PHASE``_phase(phase); \ endtask \ local static PREFIX``PHASE``_phase m_inst; \ `uvm_type_name_decl(`"PREFIX``PHASE``_phase`") \ static function PREFIX``PHASE``_phase get(); \ if(m_inst == null) begin \ m_inst = new; \ end \ return m_inst; \ endfunction \ protected function new(string name=`"PHASE`"); \ super.new(name); \ endfunction \ endclass \ `define m_uvm_topdown_phase(PHASE,COMP,PREFIX) \ class PREFIX``PHASE``_phase extends uvm_topdown_phase; \ virtual function void exec_func(uvm_component comp, uvm_phase phase); \ COMP comp_; \ if ($cast(comp_,comp)) \ comp_.``PHASE``_phase(phase); \ endfunction \ local static PREFIX``PHASE``_phase m_inst; \ `uvm_type_name_decl(`"PREFIX``PHASE``_phase`") \ static function PREFIX``PHASE``_phase get(); \ if(m_inst == null) begin \ m_inst = new(); \ end \ return m_inst; \ endfunction \ protected function new(string name=`"PHASE`"); \ super.new(name); \ endfunction \ endclass \ `define m_uvm_bottomup_phase(PHASE,COMP,PREFIX) \ class PREFIX``PHASE``_phase extends uvm_bottomup_phase; \ virtual function void exec_func(uvm_component comp, uvm_phase phase); \ COMP comp_; \ if ($cast(comp_,comp)) \ comp_.``PHASE``_phase(phase); \ endfunction \ static PREFIX``PHASE``_phase m_inst; \ `uvm_type_name_decl(`"PREFIX``PHASE``_phase`") \ static function PREFIX``PHASE``_phase get(); \ if(m_inst == null) begin \ m_inst = new(); \ end \ return m_inst; \ endfunction \ protected function new(string name=`"PHASE`"); \ super.new(name); \ endfunction \ endclass \ `define uvm_builtin_task_phase(PHASE) \ `m_uvm_task_phase(PHASE,uvm_component,uvm_) `define uvm_builtin_topdown_phase(PHASE) \ `m_uvm_topdown_phase(PHASE,uvm_component,uvm_) `define uvm_builtin_bottomup_phase(PHASE) \ `m_uvm_bottomup_phase(PHASE,uvm_component,uvm_) `define uvm_user_task_phase(PHASE,COMP,PREFIX) \ `m_uvm_task_phase(PHASE,COMP,PREFIX) `define uvm_user_topdown_phase(PHASE,COMP,PREFIX) \ `m_uvm_topdown_phase(PHASE,COMP,PREFIX) `define uvm_user_bottomup_phase(PHASE,COMP,PREFIX) \ `m_uvm_bottomup_phase(PHASE,COMP,PREFIX) `define UVM_PRINTER_DEFINES_SVH `define uvm_print_int(VALUE, SIZE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ `uvm_print_named_int(`"VALUE`", VALUE, SIZE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_named_int(NAME, VALUE, SIZE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ if (SIZE > 64) \ PRINTER.print_field(NAME, VALUE, SIZE, RADIX, ".", `"VALUE_TYPE`"); \ else \ PRINTER.print_field_int(NAME, VALUE, SIZE, RADIX, ".", `"VALUE_TYPE`"); `define uvm_print_real(VALUE, PRINTER=printer) \ `uvm_print_named_real(`"VALUE`", VALUE, PRINTER) `define uvm_print_named_real(NAME, VALUE, PRINTER=printer) \ PRINTER.print_real(NAME, VALUE); `define uvm_print_enum(TYPE, VALUE, PRINTER=printer) \ `uvm_print_named_enum(TYPE, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_enum(TYPE, NAME, VALUE, PRINTER=printer) \ if (VALUE.name() == "") \ `uvm_print_named_int(NAME, VALUE, $bits(VALUE), UVM_NORADIX, TYPE, PRINTER) \ else \ PRINTER.print_generic(NAME, `"TYPE`", $bits(VALUE), VALUE.name()); `define uvm_print_object(VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ `uvm_print_named_object(`"VALUE`", VALUE, RECURSION_POLICY, PRINTER) `define uvm_print_named_object(NAME, VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ if ((RECURSION_POLICY != UVM_DEFAULT_POLICY) && \ (RECURSION_POLICY != PRINTER.get_recursion_policy())) begin \ uvm_recursion_policy_enum __saved_recursion_policy = PRINTER.get_recursion_policy(); \ PRINTER.set_recursion_policy(RECURSION_POLICY); \ `m_uvm_print_named_object(NAME, VALUE, PRINTER) \ PRINTER.set_recursion_policy(__saved_recursion_policy); \ end \ else begin \ `m_uvm_print_named_object(NAME, VALUE, PRINTER) \ end `define m_uvm_print_named_object(NAME, VALUE, PRINTER) \ if (PRINTER.object_printed(VALUE, PRINTER.get_recursion_policy()) != uvm_policy::NEVER) begin \ uvm_recursion_policy_enum __saved_recursion_policy = PRINTER.get_recursion_policy(); \ PRINTER.set_recursion_policy(UVM_REFERENCE); \ PRINTER.print_object(NAME, VALUE); \ PRINTER.set_recursion_policy(__saved_recursion_policy); \ end \ else begin \ PRINTER.print_object(NAME, VALUE); \ end `define uvm_print_string(VALUE, PRINTER=printer) \ `uvm_print_named_string(`"VALUE`", VALUE, PRINTER) `define uvm_print_named_string(NAME, VALUE, PRINTER=printer) \ PRINTER.print_string(NAME, VALUE); `define uvm_print_qda_int(ARRAY_TYPE, VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ `uvm_print_named_qda_int(ARRAY_TYPE, `"VALUE`", VALUE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_named_qda_int(ARRAY_TYPE, NAME, VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ begin \ int __tmp_max = $right(VALUE) + 1; \ PRINTER.print_array_header(NAME, \ __tmp_max, \ `"ARRAY_TYPE``(``VALUE_TYPE``)`"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ int __tmp_begin_elements, __tmp_end_elements; \ __tmp_begin_elements = PRINTER.get_begin_elements(); \ __tmp_end_elements = PRINTER.get_end_elements(); \ /* Fast Bypass */ \ if (__tmp_begin_elements == -1 || __tmp_end_elements == -1) begin \ foreach (VALUE[__tmp_index]) begin \ `uvm_print_named_int($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ $bits(VALUE[__tmp_index]), \ RADIX, \ VALUE_TYPE, \ PRINTER) \ end \ end \ else begin \ int __tmp_curr; \ foreach(VALUE[__tmp_index]) begin \ if (__tmp_curr < __tmp_begin_elements) begin \ `uvm_print_named_int($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ $bits(VALUE[__tmp_index]), \ RADIX, \ VALUE_TYPE, \ PRINTER) \ end \ else \ break; \ __tmp_curr++; \ end \ if (__tmp_curr < __tmp_max ) begin \ if ((__tmp_max - __tmp_end_elements) > __tmp_curr) \ __tmp_curr = __tmp_max - __tmp_end_elements; \ if (__tmp_curr < __tmp_begin_elements) \ __tmp_curr = __tmp_begin_elements; \ else \ PRINTER.print_array_range(__tmp_begin_elements, __tmp_curr-1); \ while (__tmp_curr < __tmp_max) begin \ `uvm_print_named_int($sformatf("[%0d]", __tmp_curr), \ VALUE[__tmp_curr], \ $bits(VALUE[__tmp_curr]), \ RADIX, \ VALUE_TYPE, \ PRINTER) \ __tmp_curr++; \ end \ end \ end \ end \ PRINTER.print_array_footer(__tmp_max); \ end `define uvm_print_array_int(VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ `uvm_print_named_qda_int(da, `"VALUE`", VALUE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_named_array_int(NAME, VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ `uvm_print_named_qda_int(da, NAME, VALUE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_sarray_int(VALUE, RADIX=UVM_RADIX, VALUE_TYPE=integral, PRINTER=printer) \ `uvm_print_named_qda_int(sa, `"VALUE`", VALUE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_named_sarray_int(NAME, VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ `uvm_print_named_qda_int(sa, NAME, VALUE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_queue_int(VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ `uvm_print_named_qda_int(queue, `"VALUE`", VALUE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_named_queue_int(NAME, VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ `uvm_print_named_qda_int(queue, NAME, VALUE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_qda_real(ARRAY_TYPE, VALUE, PRINTER=printer) \ `uvm_print_named_qda_real(ARRAY_TYPE, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_qda_real(ARRAY_TYPE, NAME, VALUE, PRINTER=printer) \ begin \ int __tmp_max = $right(VALUE) + 1; \ PRINTER.print_array_header(NAME, \ __tmp_max, \ `"ARRAY_TYPE``(real)`"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ int __tmp_begin_elements, __tmp_end_elements; \ __tmp_begin_elements = PRINTER.get_begin_elements(); \ __tmp_end_elements = PRINTER.get_end_elements(); \ /* Fast Bypass */ \ if (__tmp_begin_elements == -1 || __tmp_end_elements == -1) begin \ foreach (VALUE[__tmp_index]) begin \ `uvm_print_named_real($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER) \ end \ end \ else begin \ int __tmp_curr; \ foreach(VALUE[__tmp_index]) begin \ if (__tmp_curr < __tmp_begin_elements) begin \ `uvm_print_named_real($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER) \ end \ else \ break; \ __tmp_curr++; \ end \ if (__tmp_curr < __tmp_max ) begin \ if ((__tmp_max - __tmp_end_elements) > __tmp_curr) \ __tmp_curr = __tmp_max - __tmp_end_elements; \ if (__tmp_curr < __tmp_begin_elements) \ __tmp_curr = __tmp_begin_elements; \ else \ PRINTER.print_array_range(__tmp_begin_elements, __tmp_curr-1); \ while (__tmp_curr < __tmp_max) begin \ `uvm_print_named_real($sformatf("[%0d]", __tmp_curr), \ VALUE[__tmp_curr], \ PRINTER) \ __tmp_curr++; \ end \ end \ end \ end \ PRINTER.print_array_footer(__tmp_max); \ end `define uvm_print_array_real(VALUE, PRINTER=printer) \ `uvm_print_named_qda_real(da, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_array_real(NAME, VALUE, PRINTER=printer) \ `uvm_print_named_qda_real(da, NAME, VALUE, PRINTER) `define uvm_print_sarray_real(VALUE, PRINTER=printer) \ `uvm_print_named_qda_real(sa, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_sarray_real(NAME, VALUE, PRINTER=printer) \ `uvm_print_named_qda_real(sa, NAME, VALUE, PRINTER) `define uvm_print_queue_real(VALUE,PRINTER=printer) \ `uvm_print_named_qda_real(queue, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_queue_real(NAME, VALUE, PRINTER=printer) \ `uvm_print_named_qda_real(queue, NAME, VALUE, PRINTER) `define uvm_print_qda_enum(ARRAY_TYPE, TYPE, VALUE, PRINTER=printer) \ `uvm_print_named_qda_enum(ARRAY_TYPE, TYPE, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_qda_enum(ARRAY_TYPE, TYPE, NAME, VALUE, PRINTER=printer) \ begin \ int __tmp_max = $right(VALUE) + 1; \ PRINTER.print_array_header(NAME, \ __tmp_max, \ {`"ARRAY_TYPE``(`", `"TYPE`", ")"}); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ int __tmp_begin_elements, __tmp_end_elements; \ __tmp_begin_elements = PRINTER.get_begin_elements(); \ __tmp_end_elements = PRINTER.get_end_elements(); \ /* Fast Bypass */ \ if (__tmp_begin_elements == -1 || __tmp_end_elements == -1) begin \ foreach (VALUE[__tmp_index]) begin \ `uvm_print_named_enum(TYPE, \ $sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER) \ end \ end \ else begin \ int __tmp_curr; \ foreach(VALUE[__tmp_index]) begin \ if (__tmp_curr < __tmp_begin_elements) begin \ `uvm_print_named_enum(TYPE, \ $sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER) \ end \ else \ break; \ __tmp_curr++; \ end \ if (__tmp_curr < __tmp_max ) begin \ if ((__tmp_max - __tmp_end_elements) > __tmp_curr) \ __tmp_curr = __tmp_max - __tmp_end_elements; \ if (__tmp_curr < __tmp_begin_elements) \ __tmp_curr = __tmp_begin_elements; \ else \ PRINTER.print_array_range(__tmp_begin_elements, __tmp_curr-1); \ while (__tmp_curr < __tmp_max) begin \ `uvm_print_named_enum(TYPE, \ $sformatf("[%0d]", __tmp_curr), \ VALUE[__tmp_curr], \ PRINTER) \ __tmp_curr++; \ end \ end \ end \ end \ PRINTER.print_array_footer(__tmp_max); \ end `define uvm_print_array_enum(TYPE, VALUE, PRINTER=printer) \ `uvm_print_named_qda_enum(da, `"VALUE`", TYPE, VALUE, PRINTER) `define uvm_print_named_array_enum(TYPE, NAME, VALUE, PRINTER=printer) \ `uvm_print_named_qda_enum(da, TYPE, NAME, VALUE, PRINTER) `define uvm_print_sarray_enum(TYPE, VALUE, PRINTER=printer) \ `uvm_print_named_qda_enum(sa, TYPE, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_sarray_enum(TYPE, NAME, VALUE, PRINTER=printer) \ `uvm_print_named_qda_enum(sa, TYPE, NAME, VALUE, PRINTER) `define uvm_print_queue_enum(TYPE, VALUE, PRINTER=printer) \ `uvm_print_named_qda_enum(queue, TYPE, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_queue_enum(TYPE, NAME, VALUE, PRINTER=printer) \ `uvm_print_named_qda_enum(queue, TYPE, NAME, VALUE, PRINTER) `define uvm_print_qda_object(ARRAY_TYPE, VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ `uvm_print_named_qda_object(ARRAY_TYPE, `"VALUE`", VALUE, RECURSION_POLICY, PRINTER) `define uvm_print_named_qda_object(ARRAY_TYPE, NAME, VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ begin \ int __tmp_max = $right(VALUE) + 1; \ PRINTER.print_array_header(NAME, \ __tmp_max, \ `"ARRAY_TYPE``(object)`"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ uvm_recursion_policy_enum __tmp_recursion_policy; \ int __tmp_begin_elements, __tmp_end_elements; \ __tmp_begin_elements = PRINTER.get_begin_elements(); \ __tmp_end_elements = PRINTER.get_end_elements(); \ __tmp_recursion_policy = PRINTER.get_recursion_policy(); \ if ((RECURSION_POLICY != UVM_DEFAULT_POLICY) && \ (__tmp_recursion_policy != RECURSION_POLICY)) \ PRINTER.set_recursion_policy(RECURSION_POLICY); \ /* Fast Bypass */ \ if (__tmp_begin_elements == -1 || __tmp_end_elements == -1) begin \ foreach (VALUE[__tmp_index]) begin \ `m_uvm_print_named_object($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER) \ end \ end \ else begin \ int __tmp_curr; \ foreach(VALUE[__tmp_index]) begin \ if (__tmp_curr < __tmp_begin_elements) begin \ `m_uvm_print_named_object($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER) \ end \ else \ break; \ __tmp_curr++; \ end \ if (__tmp_curr < __tmp_max ) begin \ if ((__tmp_max - __tmp_end_elements) > __tmp_curr) \ __tmp_curr = __tmp_max - __tmp_end_elements; \ if (__tmp_curr < __tmp_begin_elements) \ __tmp_curr = __tmp_begin_elements; \ else \ PRINTER.print_array_range(__tmp_begin_elements, __tmp_curr-1); \ while (__tmp_curr < __tmp_max) begin \ `m_uvm_print_named_object($sformatf("[%0d]", __tmp_curr), \ VALUE[__tmp_curr], \ PRINTER) \ __tmp_curr++; \ end \ end \ end \ if ((RECURSION_POLICY != UVM_DEFAULT_POLICY) && \ (__tmp_recursion_policy != RECURSION_POLICY)) \ PRINTER.set_recursion_policy(__tmp_recursion_policy); \ end \ PRINTER.print_array_footer(__tmp_max); \ end `define uvm_print_array_object(VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ `uvm_print_named_qda_object(da, `"VALUE`", VALUE, RECURSION_POLICY, PRINTER) `define uvm_print_named_array_object(NAME, VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ `uvm_print_named_qda_object(da, NAME, VALUE, RECURSION_POLICY, PRINTER) `define uvm_print_sarray_object(VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ `uvm_print_named_qda_object(sa, `"VALUE`", VALUE, RECURSION_POLICY, PRINTER) `define uvm_print_named_sarray_object(NAME, VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ `uvm_print_named_qda_object(sa, NAME, VALUE, RECURSION_POLICY, PRINTER) `define uvm_print_queue_object(VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ `uvm_print_named_qda_object(queue, `"VALUE`", VALUE, RECURSION_POLICY, PRINTER) `define uvm_print_named_queue_object(NAME, VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ `uvm_print_named_qda_object(queue, NAME, VALUE, RECURSION_POLICY, PRINTER) `define uvm_print_qda_string(ARRAY_TYPE, VALUE, PRINTER=printer) \ `uvm_print_named_qda_string(ARRAY_TYPE, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_qda_string(ARRAY_TYPE, NAME, VALUE, PRINTER=printer) \ begin \ int __tmp_max = $right(VALUE) + 1; \ PRINTER.print_array_header(NAME, \ __tmp_max, \ `"ARRAY_TYPE``(string)`"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ int __tmp_begin_elements, __tmp_end_elements; \ __tmp_begin_elements = PRINTER.get_begin_elements(); \ __tmp_end_elements = PRINTER.get_end_elements(); \ /* Fast Bypass */ \ if (__tmp_begin_elements == -1 || __tmp_end_elements == -1) begin \ foreach (VALUE[__tmp_index]) begin \ `uvm_print_named_string($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER) \ end \ end \ else begin \ int __tmp_curr; \ foreach(VALUE[__tmp_index]) begin \ if (__tmp_curr < __tmp_begin_elements) begin \ `uvm_print_named_string($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER) \ end \ else \ break; \ __tmp_curr++; \ end \ if (__tmp_curr < __tmp_max ) begin \ if ((__tmp_max - __tmp_end_elements) > __tmp_curr) \ __tmp_curr = __tmp_max - __tmp_end_elements; \ if (__tmp_curr < __tmp_begin_elements) \ __tmp_curr = __tmp_begin_elements; \ else \ PRINTER.print_array_range(__tmp_begin_elements, __tmp_curr-1); \ while (__tmp_curr < __tmp_max) begin \ `uvm_print_named_string($sformatf("[%0d]", __tmp_curr), \ VALUE[__tmp_curr], \ PRINTER) \ __tmp_curr++; \ end \ end \ end \ end \ PRINTER.print_array_footer(__tmp_max); \ end `define uvm_print_array_string(VALUE, PRINTER=printer) \ `uvm_print_named_qda_string(da, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_array_string(NAME, VALUE, PRINTER=printer) \ `uvm_print_named_qda_string(da, NAME, VALUE, PRINTER) `define uvm_print_sarray_string(VALUE, PRINTER=printer) \ `uvm_print_named_qda_string(sa, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_sarray_string(NAME, VALUE, PRINTER=printer) \ `uvm_print_named_qda_string(sa, NAME, VALUE, PRINTER) `define uvm_print_queue_string(VALUE, PRINTER=printer) \ `uvm_print_named_qda_string(queue, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_queue_string(NAME, VALUE, PRINTER=printer) \ `uvm_print_named_qda_string(queue, NAME, VALUE, PRINTER) `define uvm_print_aa_int_string(VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ `uvm_print_named_aa_int_string(`"VALUE`", VALUE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_named_aa_int_string(NAME, VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ begin \ PRINTER.print_array_header(NAME, \ VALUE.num(), \ `"aa(``VALUE_TYPE``,string)`"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ foreach(VALUE[__tmp_index]) \ `uvm_print_named_int($sformatf("[%s]", __tmp_index), \ VALUE[__tmp_index], \ $bits(VALUE[__tmp_index]), \ RADIX, \ VALUE_TYPE, \ PRINTER ) \ end \ PRINTER.print_array_footer(VALUE.num()); \ end `define uvm_print_aa_object_string(VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ `uvm_print_named_aa_object_string(`"VALUE`", VALUE, RECURSION_POLICY, PRINTER) `define uvm_print_named_aa_object_string(NAME, VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ begin \ PRINTER.print_array_header(NAME, \ VALUE.num(), \ "aa(object,string)"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ uvm_recursion_policy_enum __tmp_recursion_policy; \ __tmp_recursion_policy = PRINTER.get_recursion_policy(); \ if ((RECURSION_POLICY != UVM_DEFAULT_POLICY) && \ (__tmp_recursion_policy != RECURSION_POLICY)) \ PRINTER.set_recursion_policy(RECURSION_POLICY); \ foreach(VALUE[__tmp_index]) \ `m_uvm_print_named_object($sformatf("[%s]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER ) \ if ((RECURSION_POLICY != UVM_DEFAULT_POLICY) && \ (__tmp_recursion_policy != RECURSION_POLICY)) \ PRINTER.set_recursion_policy(__tmp_recursion_policy); \ end \ PRINTER.print_array_footer(VALUE.num()); \ end `define uvm_print_aa_string_string(VALUE, PRINTER=printer) \ `uvm_print_named_aa_string_string(`"VALUE`", VALUE, PRINTER) `define uvm_print_named_aa_string_string(NAME, VALUE, PRINTER=printer) \ begin \ PRINTER.print_array_header(NAME, \ VALUE.num(), \ "aa(string,string)"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ foreach(VALUE[__tmp_index]) \ `uvm_print_named_string($sformatf("[%s]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER ) \ end \ PRINTER.print_array_footer(VALUE.num()); \ end `define uvm_print_aa_int_int(VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=int, INDEX_TYPE=int, PRINTER=printer) \ `uvm_print_named_aa_int_int(`"VALUE`", VALUE, RADIX, VALUE_TYPE, INDEX_TYPE, PRINTER) `define uvm_print_named_aa_int_int(NAME, VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=int, INDEX_TYPE=int, PRINTER=printer) \ begin \ PRINTER.print_array_header(NAME, \ VALUE.num(), \ `"aa(``VALUE_TYPE``,``INDEX_TYPE``)`"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ foreach(VALUE[__tmp_index]) \ `uvm_print_named_int($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ $bits(VALUE[__tmp_index]), \ RADIX, \ VALUE_TYPE, \ PRINTER ) \ end \ PRINTER.print_array_footer(VALUE.num()); \ end `define uvm_print_aa_object_int(VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, INDEX_TYPE=int, PRINTER=printer) \ `uvm_print_named_aa_object_int(`"VALUE`", VALUE, RECURSION_POLICY, INDEX_TYPE, PRINTER) `define uvm_print_named_aa_object_int(NAME, VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, INDEX_TYPE=int, PRINTER=printer) \ begin \ PRINTER.print_array_header(NAME, \ VALUE.num(), \ `"aa(object,``INDEX_TYPE``)`"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ uvm_recursion_policy_enum __tmp_recursion_policy; \ __tmp_recursion_policy = PRINTER.get_recursion_policy(); \ if ((RECURSION_POLICY != UVM_DEFAULT_POLICY) && \ (__tmp_recursion_policy != RECURSION_POLICY)) \ PRINTER.set_recursion_policy(RECURSION_POLICY); \ foreach(VALUE[__tmp_index]) \ `m_uvm_print_named_object($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER ) \ if ((RECURSION_POLICY != UVM_DEFAULT_POLICY) && \ (__tmp_recursion_policy != RECURSION_POLICY)) \ PRINTER.set_recursion_policy(__tmp_recursion_policy); \ end \ PRINTER.print_array_footer(VALUE.num()); \ end `define uvm_print_aa_string_int(VALUE, INDEX_TYPE=int, PRINTER=printer) \ `uvm_print_named_aa_string_int(`"VALUE`", VALUE, INDEX_TYPE, PRINTER) `define uvm_print_named_aa_string_int(NAME, VALUE, INDEX_TYPE=int, PRINTER=printer) \ begin \ PRINTER.print_array_header(NAME, \ VALUE.num(), \ `"aa(string,``INDEX_TYPE``)`"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ foreach(VALUE[__tmp_index]) \ `uvm_print_named_string($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER ) \ end \ PRINTER.print_array_footer(VALUE.num()); \ end `define uvm_print_aa_int_enum(ENUM_TYPE, VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=int, PRINTER=printer) \ `uvm_print_named_aa_int_enum(`"VALUE`", ENUM_TYPE, VALUE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_named_aa_int_enum(NAME, ENUM_TYPE, VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=int, PRINTER=printer) \ begin \ PRINTER.print_array_header(NAME, \ VALUE.num(), \ `"aa(``VALUE_TYPE``,``ENUM_TYPE``)`"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ foreach(VALUE[__tmp_index]) \ `uvm_print_named_int((__tmp_index.name() == "") ? $sformatf("[%s'(%0d)]", `"ENUM_TYPE`",__tmp_index) \ : $sformatf("[%s]", __tmp_index.name()), \ VALUE[__tmp_index], \ $bits(VALUE[__tmp_index]), \ RADIX, \ VALUE_TYPE, \ PRINTER ) \ end \ PRINTER.print_array_footer(VALUE.num()); \ end `define UVM_COMPARER_DEFINES_SVH `define m_uvm_compare_threshold_begin(COMPARER) \ if ((!COMPARER.get_threshold() || \ (COMPARER.get_result() < COMPARER.get_threshold()))) begin \ `define m_uvm_compare_threshold_end \ end `define m_uvm_compare_begin(LVALUE, RVALUE, COMPARER=comparer) \ `m_uvm_compare_threshold_begin(COMPARER) \ if ((LVALUE) !== (RVALUE)) begin \ `define m_uvm_compare_end \ end \ `m_uvm_compare_threshold_end `define uvm_compare_int(LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `uvm_compare_named_int(`"LVALUE`", LVALUE, RVALUE, RADIX, COMPARER) `define uvm_compare_named_int(NAME, LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ if ($bits(LVALUE) <= 64) \ void'(COMPARER.compare_field_int(NAME , LVALUE, RVALUE, $bits(LVALUE), RADIX)); \ else \ void'(COMPARER.compare_field(NAME , LVALUE, RVALUE, $bits(LVALUE), RADIX)); \ `m_uvm_compare_end `define uvm_compare_enum(LVALUE, RVALUE, TYPE, COMPARER=comparer) \ `uvm_compare_named_enum(`"LVALUE`", LVALUE, RVALUE, TYPE, COMPARER) `define uvm_compare_named_enum(NAME, LVALUE, RVALUE, TYPE, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ void'(COMPARER.compare_string(NAME , \ $sformatf("%s'(%s)", `"TYPE`", LVALUE.name()), \ $sformatf("%s'(%s)", `"TYPE`", RVALUE.name())) ); \ `m_uvm_compare_end `define uvm_compare_real(LVALUE, RVALUE, COMPARER=comparer) \ `uvm_compare_named_real(`"LVALUE`", LVALUE, RVALUE, COMPARER) `define uvm_compare_named_real(NAME, LVALUE, RVALUE, COMPARER=comparer) \ `m_uvm_compare_threshold_begin(COMPARER) \ if ((LVALUE) != (RVALUE)) begin \ void'(COMPARER.compare_field_real(NAME , LVALUE, RVALUE)); \ end \ `m_uvm_compare_threshold_end `define uvm_compare_object(LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `uvm_compare_named_object(`"LVALUE`", LVALUE, RVALUE, POLICY, COMPARER) `define uvm_compare_named_object(NAME, LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ uvm_recursion_policy_enum prev_rec__; \ prev_rec__ = COMPARER.get_recursion_policy(); \ if (POLICY != UVM_DEFAULT_POLICY) \ COMPARER.set_recursion_policy(POLICY); \ `m_uvm_compare_named_object(NAME, LVALUE, RVALUE, COMPARER) \ if (POLICY != UVM_DEFAULT_POLICY) \ COMPARER.set_recursion_policy(prev_rec__); \ `m_uvm_compare_end `define m_uvm_compare_named_object(NAME, LVALUE, RVALUE, COMPARER) \ if (COMPARER.get_recursion_policy() != UVM_REFERENCE) begin \ bit rv; \ uvm_policy::recursion_state_e state; \ state = COMPARER.object_compared(LVALUE, RVALUE, COMPARER.get_recursion_policy(), rv); \ if ((state == uvm_policy::FINISHED) && \ !rv) \ COMPARER.print_msg($sformatf("'%s' miscompared using saved return value", NAME)); \ else if (state == uvm_policy::NEVER) \ void'(COMPARER.compare_object(NAME, LVALUE, RVALUE)); \ /* else skip to avoid infinite loop */ \ end \ else begin \ void'(COMPARER.compare_object(NAME, LVALUE, RVALUE)); \ end `define uvm_compare_string(LVALUE, RVALUE, COMPARER=comparer) \ `uvm_compare_named_string(`"LVALUE`", LVALUE, RVALUE, COMPARER) `define uvm_compare_named_string(NAME, LVALUE, RVALUE, COMPARER=comparer) \ `m_uvm_compare_threshold_begin(COMPARER) \ if ((LVALUE) != (RVALUE)) begin \ void'(COMPARER.compare_string(NAME , LVALUE, RVALUE)); \ end \ `m_uvm_compare_threshold_end `define uvm_compare_sarray_int(LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `uvm_compare_named_sarray_int(`"LVALUE`", LVALUE, RVALUE, RADIX, COMPARER) `define uvm_compare_named_sarray_int(NAME, LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ foreach (LVALUE[i]) begin \ `uvm_compare_named_int($sformatf("%s[%0d]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ RADIX, \ COMPARER) \ end \ `m_uvm_compare_end `define uvm_compare_qda_int(LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `uvm_compare_named_qda_int(`"LVALUE`", LVALUE, RVALUE, RADIX, COMPARER) `define uvm_compare_named_qda_int(NAME, LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ `uvm_compare_named_int($sformatf("%s.size()", NAME), \ LVALUE.size(), \ RVALUE.size(), \ UVM_DEC, \ COMPARER) \ `uvm_compare_named_sarray_int(NAME, LVALUE, RVALUE, RADIX, COMPARER) \ `m_uvm_compare_end `define uvm_compare_sarray_real(LVALUE, RVALUE, COMPARER=comparer) \ `uvm_compare_named_sarray_real(`"LVALUE`", LVALUE, RVALUE,COMPARER) `define uvm_compare_named_sarray_real(NAME, LVALUE, RVALUE, COMPARER=comparer) \ `m_uvm_compare_threshold_begin(COMPARER) \ if ((LVALUE) != (RVALUE)) begin \ foreach (LVALUE[i]) begin \ `uvm_compare_named_real($sformatf("%s[%0d]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ COMPARER) \ end \ end \ `m_uvm_compare_threshold_end `define uvm_compare_qda_real(LVALUE, RVALUE, COMPARER=comparer) \ `uvm_compare_named_qda_real(`"LVALUE`", LVALUE, RVALUE, COMPARER) `define uvm_compare_named_qda_real(NAME, LVALUE, RVALUE, COMPARER=comparer) \ `m_uvm_compare_threshold_begin(COMPARER) \ `uvm_compare_named_real($sformatf("%s.size()", NAME), \ LVALUE.size(), \ RVALUE.size(), \ COMPARER) \ `uvm_compare_named_sarray_real(NAME, LVALUE, RVALUE, COMPARER) \ `m_uvm_compare_threshold_end `define uvm_compare_sarray_enum(LVALUE, RVALUE, TYPE, COMPARER=comparer) \ `uvm_compare_named_sarray_enum(`"LVALUE`", LVALUE, RVALUE, TYPE, COMPARER) `define uvm_compare_named_sarray_enum(NAME, LVALUE, RVALUE, TYPE, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ foreach (LVALUE[i]) begin \ `uvm_compare_named_enum($sformatf("%s[%0d]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ TYPE, \ COMPARER) \ end \ `m_uvm_compare_end `define uvm_compare_qda_enum(LVALUE, RVALUE, TYPE, COMPARER=comparer) \ `uvm_compare_named_qda_enum(`"LVALUE`", LVALUE, RVALUE, TYPE, COMPARER) `define uvm_compare_named_qda_enum(NAME, LVALUE, RVALUE, TYPE, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ `uvm_compare_named_int($sformatf("%s.size()", NAME), \ LVALUE.size(), \ RVALUE.size(), \ UVM_DEC, \ COMPARER) \ `uvm_compare_named_sarray_enum(NAME, LVALUE, RVALUE, TYPE, COMPARER) \ `m_uvm_compare_end `define uvm_compare_sarray_object(LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `uvm_compare_named_sarray_object(`"LVALUE`", LVALUE, RVALUE, POLICY, COMPARER) `define uvm_compare_named_sarray_object(NAME, LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ uvm_recursion_policy_enum prev_rec__; \ prev_rec__ = COMPARER.get_recursion_policy(); \ if (POLICY != UVM_DEFAULT_POLICY) \ COMPARER.set_recursion_policy(POLICY); \ foreach (LVALUE[i]) begin \ `m_uvm_compare_named_object($sformatf("%s[%0d]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ COMPARER) \ end \ if (POLICY != UVM_DEFAULT_POLICY) \ COMPARER.set_recursion_policy(prev_rec__); \ `m_uvm_compare_end `define uvm_compare_qda_object(LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `uvm_compare_named_qda_object(`"LVALUE`", LVALUE, RVALUE, POLICY, COMPARER) `define uvm_compare_named_qda_object(NAME, LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ `uvm_compare_named_int($sformatf("%s.size()", NAME), \ LVALUE.size(), \ RVALUE.size(), \ UVM_DEC, \ COMPARER) \ `uvm_compare_named_sarray_object(NAME, LVALUE, RVALUE, POLICY, COMPARER) \ `m_uvm_compare_end `define uvm_compare_sarray_string(LVALUE, RVALUE, COMPARER=comparer) \ `uvm_compare_named_sarray_string(`"LVALUE`", LVALUE, RVALUE, COMPARER) `define uvm_compare_named_sarray_string(NAME, LVALUE, RVALUE, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ foreach (LVALUE[i]) begin \ `uvm_compare_named_string($sformatf("%s[%0d]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ COMPARER) \ end \ `m_uvm_compare_end `define uvm_compare_qda_string(LVALUE, RVALUE, COMPARER=comparer) \ `uvm_compare_named_qda_string(`"LVALUE`", LVALUE, RVALUE, COMPARER) `define uvm_compare_named_qda_string(NAME, LVALUE, RVALUE, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ `uvm_compare_named_int($sformatf("%s.size()", NAME), \ LVALUE.size(), \ RVALUE.size(), \ UVM_DEC, \ COMPARER) \ `uvm_compare_named_sarray_string(NAME, LVALUE, RVALUE, COMPARER) \ `m_uvm_compare_end `define uvm_compare_aa_int_string(LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `uvm_compare_named_aa_int_string(`"LVALUE`", LVALUE, RVALUE, RADIX, COMPARER) `define uvm_compare_named_aa_int_string(NAME, LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ foreach(LVALUE[i]) begin \ if (!RVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%s' not in RHS", NAME, i)); \ end \ else begin \ `uvm_compare_named_int($sformatf("%s[%s]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ RADIX, \ COMPARER) \ end \ end \ foreach(RVALUE[i]) begin \ if(!LVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%s' not in LHS", NAME, i)); \ end \ end \ `m_uvm_compare_end `define uvm_compare_aa_object_string(LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `uvm_compare_named_aa_object_string(`"LVALUE`", LVALUE, RVALUE, POLICY, COMPARER) `define uvm_compare_named_aa_object_string(NAME, LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ uvm_recursion_policy_enum prev_rec__; \ prev_rec__ = COMPARER.get_recursion_policy(); \ if (POLICY != UVM_DEFAULT_POLICY) \ COMPARER.set_recursion_policy(POLICY); \ foreach(LVALUE[i]) begin \ if (!RVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%s' not in RHS", NAME, i)); \ end \ else begin \ `m_uvm_compare_named_object($sformatf("%s[%s]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ COMPARER) \ end \ end \ foreach(RVALUE[i]) begin \ if(!LVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%s' not in LHS", NAME, i)); \ end \ end \ if (POLICY != UVM_DEFAULT_POLICY) \ COMPARER.set_recursion_policy(prev_rec__); \ `m_uvm_compare_end `define uvm_compare_aa_string_string(LVALUE, RVALUE, COMPARER=comparer) \ `uvm_compare_named_aa_string_string(`"LVALUE`", LVALUE, RVALUE, COMPARER) `define uvm_compare_named_aa_string_string(NAME, LVALUE, RVALUE, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ foreach(LVALUE[i]) begin \ if (!RVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%s' not in RHS", NAME, i)); \ end \ else begin \ `uvm_compare_named_string($sformatf("%s[%s]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ COMPARER) \ end \ end \ foreach(RVALUE[i]) begin \ if(!LVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%s' not in LHS", NAME, i)); \ end \ end \ `m_uvm_compare_end `define uvm_compare_aa_int_int(LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `uvm_compare_named_aa_int_int(`"LVALUE`", LVALUE, RVALUE, RADIX, COMPARER) `define uvm_compare_named_aa_int_int(NAME, LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ foreach(LVALUE[i]) begin \ if (!RVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%0d' not in RHS", NAME, i)); \ end \ else begin \ `uvm_compare_named_int($sformatf("%s[%d]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ RADIX, \ COMPARER) \ end \ end \ foreach(RVALUE[i]) begin \ if(!LVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%0d' not in LHS", NAME, i)); \ end \ end \ `m_uvm_compare_end `define uvm_compare_aa_object_int(LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `uvm_compare_named_aa_object_int(`"LVALUE`", LVALUE, RVALUE, POLICY, COMPARER) `define uvm_compare_named_aa_object_int(NAME, LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ uvm_recursion_policy_enum prev_rec__; \ prev_rec__ = COMPARER.get_recursion_policy(); \ if (POLICY != UVM_DEFAULT_POLICY) \ COMPARER.set_recursion_policy(POLICY); \ foreach(LVALUE[i]) begin \ if (!RVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%0d' not in RHS", NAME, i)); \ end \ else begin \ `m_uvm_compare_named_object($sformatf("%s[%s]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ COMPARER) \ end \ end \ foreach(RVALUE[i]) begin \ if(!LVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%0d' not in LHS", NAME, i)); \ end \ end \ if (POLICY != UVM_DEFAULT_POLICY) \ COMPARER.set_recursion_policy(prev_rec__); \ `m_uvm_compare_end `define uvm_compare_aa_string_int(LVALUE, RVALUE, COMPARER=comparer) \ `uvm_compare_named_aa_string_int(`"LVALUE`", LVALUE, RVALUE, COMPARER) `define uvm_compare_named_aa_string_int(NAME, LVALUE, RVALUE, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ foreach(LVALUE[i]) begin \ if (!RVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%d' not in RHS", NAME, i)); \ end \ else begin \ `uvm_compare_named_string($sformatf("%s[%d]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ COMPARER) \ end \ end \ foreach(RVALUE[i]) begin \ if(!LVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%d' not in LHS", NAME, i)); \ end \ end \ `m_uvm_compare_end `define UVM_RECORDER_DEFINES_SVH `define uvm_record_attribute(TR_HANDLE,NAME,VALUE,RECORDER=recorder) \ RECORDER.record_generic(NAME, $sformatf("%p", VALUE)); `define uvm_record_int(NAME,VALUE,SIZE,RADIX = UVM_NORADIX,RECORDER=recorder) \ if (RECORDER != null && RECORDER.is_open()) begin \ if (RECORDER.use_record_attribute()) \ `uvm_record_attribute(RECORDER.get_record_attribute_handle(),NAME,VALUE,RECORDER) \ else \ if (SIZE > 64) \ RECORDER.record_field(NAME, VALUE, SIZE, RADIX); \ else \ RECORDER.record_field_int(NAME, VALUE, SIZE, RADIX); \ end `define uvm_record_string(NAME,VALUE,RECORDER=recorder) \ if (RECORDER != null && RECORDER.is_open()) begin \ if (RECORDER.use_record_attribute()) \ `uvm_record_attribute(RECORDER.get_record_attribute_handle(),NAME,VALUE,RECORDER) \ else \ RECORDER.record_string(NAME,VALUE); \ end `define uvm_record_time(NAME,VALUE,RECORDER=recorder) \ if (RECORDER != null && RECORDER.is_open()) begin \ if (RECORDER.use_record_attribute()) \ `uvm_record_attribute(RECORDER.get_record_attribute_handle(),NAME,VALUE,RECORDER) \ else \ RECORDER.record_time(NAME,VALUE); \ end `define uvm_record_real(NAME,VALUE,RECORDER=recorder) \ if (RECORDER != null && RECORDER.is_open()) begin \ if (RECORDER.use_record_attribute()) \ `uvm_record_attribute(RECORDER.get_record_attribute_handle(),NAME,VALUE,RECORDER) \ else \ RECORDER.record_field_real(NAME,VALUE); \ end `define uvm_record_field(NAME,VALUE,RECORDER=recorder) \ if (RECORDER != null && RECORDER.is_open()) begin \ if (RECORDER.use_record_attribute()) begin \ `uvm_record_attribute(RECORDER.get_record_attribute_handle(),NAME,VALUE,RECORDER) \ end \ else \ RECORDER.record_generic(NAME, $sformatf("%p", VALUE)); \ end `define uvm_record_enum(NAME,VALUE,TYPE,RECORDER=recorder) \ if (RECORDER != null && RECORDER.is_open()) begin \ if (RECORDER.use_record_attribute()) begin \ `uvm_record_attribute(RECORDER.get_record_attribute_handle(),NAME,VALUE,RECORDER) \ end \ else begin \ if (VALUE.name() == "") \ RECORDER.record_generic(NAME, $sformatf("%0d", VALUE), `"TYPE`"); \ else \ RECORDER.record_generic(NAME, VALUE.name(), `"TYPE`"); \ end \ end `define uvm_record_qda_int(ARG, RADIX,RECORDER=recorder) \ begin \ int sz__ = $size(ARG); \ if(sz__ == 0) begin \ `uvm_record_int(`"ARG`", 0, 32, UVM_DEC,RECORDER) \ end \ else if(sz__ < 10) begin \ foreach(ARG[i]) begin \ string nm__ = $sformatf("%s[%0d]", `"ARG`", i); \ `uvm_record_int(nm__, ARG[i], $bits(ARG[i]), RADIX, RECORDER) \ end \ end \ else begin \ for(int i=0; i<5; ++i) begin \ string nm__ = $sformatf("%s[%0d]", `"ARG`", i); \ `uvm_record_int(nm__, ARG[i], $bits(ARG[i]), RADIX, RECORDER) \ end \ for(int i=sz__-5; i sz__) \ void'(VAR.pop_back()); \ for (int i=0; i tmp_size__) \ void'(VAR.pop_back()); \ for (int i = 0; i < tmp_size__; i++) \ `uvm_unpack_real(VAR[i], PACKER) \ end `define UVM_COPIER_DEFINES_SVH `define uvm_copy_object(LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COPIER=copier) \ if (LVALUE != RVALUE) begin \ if ((RVALUE == null) || \ (POLICY == UVM_REFERENCE) || \ ((POLICY == UVM_DEFAULT_POLICY) && \ (COPIER.get_recursion_policy() == UVM_REFERENCE))) begin \ LVALUE = RVALUE; \ end \ else begin \ uvm_object lvalue_ref__; \ if (!COPIER.get_first_copy(RVALUE,lvalue_ref__) || !$cast(LVALUE,lvalue_ref__)) begin \ uvm_recursion_policy_enum prev_pol__ = COPIER.get_recursion_policy(); \ uvm_recursion_policy_enum curr_pol__; \ if (POLICY != UVM_DEFAULT_POLICY) \ COPIER.set_recursion_policy(POLICY); \ curr_pol__ = COPIER.get_recursion_policy(); \ if (LVALUE == null) begin \ if (($cast(LVALUE, RVALUE.create(RVALUE.get_name())) == 0) || \ (LVALUE == null)) begin \ `uvm_fatal("UVM/COPY/NULL_CREATE", \ {"Could not create '", RVALUE.get_full_name(), \ "' of type '", RVALUE.get_type_name(), \ "', into '", `"LVALUE`", "'."}) \ end \ else begin \ COPIER.copy_object(LVALUE, RVALUE); \ end \ end \ else begin \ if (COPIER.object_copied(LVALUE, RVALUE, curr_pol__) == uvm_policy::STARTED) begin \ `uvm_warning("UVM/COPY/LOOP", \ {"Loop detected in copy operation (LHS:'", \ LVALUE.get_full_name(), \ "', RHS:'", \ RVALUE.get_full_name(), \ "')"}) \ end \ else begin \ COPIER.copy_object(LVALUE, RVALUE); \ end \ end \ if (POLICY != UVM_DEFAULT_POLICY) \ COPIER.set_recursion_policy(prev_pol__); \ end \ end \ end `define uvm_copy_aa_object(LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COPIER=copier) \ if ((POLICY == UVM_REFERENCE) || !RVALUE.size()) \ LVALUE = RVALUE; \ else begin \ LVALUE.delete(); \ foreach(RVALUE[i]) \ `uvm_copy_object(LVALUE[i], RVALUE[i], POLICY, COPIER) \ end `define uvm_copier_get_function(FUNCTION) \ function int get_``FUNCTION``_copy(uvm_object rhs, ref uvm_object lhs); \ if (m_recur_states.exists(rhs)) \ return m_recur_states[rhs].FUNCTION(lhs); \ return 0; \ endfunction : get_``FUNCTION``_copy `define UVM_OBJECT_DEFINES_SVH `define UVM_FIELD_FLAG_SIZE UVM_FIELD_FLAG_RESERVED_BITS `define uvm_field_utils_begin(T) \ function void do_execute_op( uvm_field_op op ); \ super.do_execute_op(op); \ __m_uvm_execute_field_op(op); \ endfunction : do_execute_op \ local function void __m_uvm_execute_field_op( uvm_field_op __local_op__ ); \ uvm_field_flag_t local_op_type__; /* Used to avoid re-querying */ \ T local_rhs__; /* Used for $casting copy and compare */ \ uvm_resource_base local_rsrc__; /* Used for UVM_SET ops */ \ string local_rsrc_name__; \ uvm_object local_obj__; /* Used when trying to read uvm_object resources */ \ bit local_success__; /* Used when trying to read resources */ \ typedef T __local_type__; /* Used for referring to type T in field macros */ \ int local_size__; /* Used when unpacking size values */ \ /* All possible policy classes */ \ /* Using the same name as the do_* methods, allows macro reuse */ \ uvm_printer __local_printer__; \ uvm_comparer __local_comparer__; \ uvm_recorder __local_recorder__; \ uvm_packer __local_packer__; \ uvm_copier __local_copier__; \ void'($cast(local_rhs__, __local_op__.get_rhs())); \ if (($cast(local_rsrc__, __local_op__.get_rhs())) && \ (local_rsrc__ != null)) \ local_rsrc_name__ = local_rsrc__.get_name(); \ local_op_type__ = __local_op__.get_op_type(); \ case (local_op_type__) \ UVM_PRINT: begin \ $cast(__local_printer__, __local_op__.get_policy()); \ end \ UVM_COMPARE: begin \ if (local_rhs__ == null) return; \ $cast(__local_comparer__, __local_op__.get_policy()); \ end \ UVM_RECORD: begin \ $cast(__local_recorder__, __local_op__.get_policy()); \ end \ UVM_PACK, UVM_UNPACK: begin \ $cast(__local_packer__, __local_op__.get_policy()); \ end \ UVM_COPY: begin \ if (local_rhs__ == null) return; \ $cast(__local_copier__, __local_op__.get_policy()); \ end \ UVM_SET: begin \ if (local_rsrc__ == null) return; \ end \ default: \ return; /* unknown op, just return */ \ endcase \ `define uvm_field_utils_end \ endfunction : __m_uvm_execute_field_op `define uvm_object_utils(T) \ `m_uvm_object_registry_internal(T,T) \ `m_uvm_object_create_func(T) \ `uvm_type_name_decl(`"T`") `define uvm_object_param_utils(T) \ `m_uvm_object_registry_param(T) \ `m_uvm_object_create_func(T) `define uvm_object_utils_begin(T) \ `uvm_object_utils(T) \ `uvm_field_utils_begin(T) `define uvm_object_param_utils_begin(T) \ `uvm_object_param_utils(T) \ `uvm_field_utils_begin(T) `define uvm_object_abstract_utils(T) \ `m_uvm_object_abstract_registry_internal(T,T) \ `uvm_type_name_decl(`"T`") `define uvm_object_abstract_param_utils(T) \ `m_uvm_object_abstract_registry_param(T) `define uvm_object_abstract_utils_begin(T) \ `uvm_object_abstract_utils(T) \ `uvm_field_utils_begin(T) `define uvm_object_abstract_param_utils_begin(T) \ `uvm_object_abstract_param_utils(T) \ `uvm_field_utils_begin(T) `define uvm_object_utils_end \ `uvm_field_utils_end `define uvm_component_utils(T) \ `m_uvm_component_registry_internal(T,T) \ `uvm_type_name_decl(`"T`") \ `define uvm_component_param_utils(T) \ `m_uvm_component_registry_param(T) \ `define uvm_component_utils_begin(T) \ `uvm_component_utils(T) \ `uvm_field_utils_begin(T) `define uvm_component_param_utils_begin(T) \ `uvm_component_param_utils(T) \ `uvm_field_utils_begin(T) `define uvm_component_abstract_utils(T) \ `m_uvm_component_abstract_registry_internal(T,T) \ `uvm_type_name_decl(`"T`") \ `define uvm_component_abstract_param_utils(T) \ `m_uvm_component_abstract_registry_param(T) \ `define uvm_component_abstract_utils_begin(T) \ `uvm_component_abstract_utils(T) \ `uvm_field_utils_begin(T) `define uvm_component_abstract_param_utils_begin(T) \ `uvm_component_abstract_param_utils(T) \ `uvm_field_utils_begin(T) `define uvm_component_utils_end \ `uvm_field_utils_end `define uvm_object_registry(T,S) \ typedef uvm_object_registry#(T,S) type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define uvm_component_registry(T,S) \ typedef uvm_component_registry #(T,S) type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define uvm_declare_type_alias(TYPE,NAME,SFX=) \ static bit m__alias_declared``SFX = TYPE::type_id::set_type_alias(NAME); `define uvm_new_func \ function new (string name, uvm_component parent); \ super.new(name, parent); \ endfunction `define m_uvm_object_create_func(T) \ function uvm_object create (string name=""); \ T tmp; \ if (name=="") tmp = new(); \ else tmp = new(name); \ return tmp; \ endfunction `define uvm_type_name_decl(TNAME_STRING) \ static function string type_name(); \ return TNAME_STRING; \ endfunction : type_name \ virtual function string get_type_name(); \ return TNAME_STRING; \ endfunction : get_type_name `define m_uvm_object_registry_internal(T,S) \ typedef uvm_object_registry#(T,`"S`") type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define m_uvm_object_registry_param(T) \ typedef uvm_object_registry #(T) type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define m_uvm_object_abstract_registry_internal(T,S) \ typedef uvm_abstract_object_registry#(T,`"S`") type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define m_uvm_object_abstract_registry_param(T) \ typedef uvm_abstract_object_registry #(T) type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define m_uvm_component_registry_internal(T,S) \ typedef uvm_component_registry #(T,`"S`") type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define m_uvm_component_registry_param(T) \ typedef uvm_component_registry #(T) type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define m_uvm_component_abstract_registry_internal(T,S) \ typedef uvm_abstract_component_registry #(T,`"S`") type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define m_uvm_component_abstract_registry_param(T) \ typedef uvm_abstract_component_registry #(T) type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define m_uvm_field_radix(FLAG) uvm_radix_enum'((FLAG)&(UVM_RADIX)) `define m_uvm_field_recursion(FLAG) uvm_recursion_policy_enum'((FLAG)&(UVM_RECURSION)) `define m_uvm_field_begin(ARG, FLAG) \ begin \ case (local_op_type__) `define m_uvm_field_end(ARG) \ endcase \ end `define m_uvm_field_op_begin(OP, FLAG) \ UVM_``OP: \ if (!((FLAG)&UVM_NO``OP)) begin `define m_uvm_field_op_end(OP) \ end `define uvm_field_int(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_int(ARG, local_rhs__.ARG, `m_uvm_field_radix(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_int(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_int(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_int(`"ARG`", \ ARG, \ $bits(ARG), \ `m_uvm_field_radix(FLAG), \ __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_int(ARG, $bits(ARG), `m_uvm_field_radix(FLAG),,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_builtin_int_read(local_success__, \ local_rsrc__, \ ARG, \ this) \ /* TODO if(local_success__ && printing matches) */ \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_object(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ `uvm_copy_object(ARG, local_rhs__.ARG, `m_uvm_field_recursion(FLAG), __local_copier__) \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_object(ARG, local_rhs__.ARG, `m_uvm_field_recursion(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ if (`m_uvm_field_recursion(FLAG) != UVM_REFERENCE) \ `uvm_pack_object(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ if (`m_uvm_field_recursion(FLAG) != UVM_REFERENCE) \ `uvm_unpack_object(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ __local_recorder__.record_object(`"ARG`", ARG); \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_object(ARG, `m_uvm_field_recursion(FLAG),__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_read(local_success__, \ local_rsrc__, \ uvm_object, \ local_obj__, \ this) \ if (local_success__) begin \ if (local_obj__ == null) begin \ ARG = null; \ end else if (!$cast(ARG, local_obj__)) begin \ `uvm_warning("UVM/FIELDS/OBJ_TYPE", $sformatf("Can't set field '%s' on '%s' with '%s' type", \ `"ARG`", \ this.get_full_name(), \ local_obj__.get_type_name())) \ end \ /* TODO if(local_success__ && printing matches) */ \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_string(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_string(ARG, local_rhs__.ARG, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_string(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_string(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_string(`"ARG`", ARG, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ __local_printer__.print_string(`"ARG`", ARG); \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_read(local_success__, \ local_rsrc__, \ string, \ ARG, \ this) \ /* TODO if(local_success__ && printing matches) */ \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_enum(T,ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_enum(ARG, local_rhs__.ARG, T, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_enum(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_enum(ARG, T, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_enum(`"ARG`", ARG, T, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ if (`m_uvm_field_radix(FLAG) inside {UVM_NORADIX, UVM_ENUM, UVM_STRING}) \ `uvm_print_enum(T, ARG,__local_printer__) \ else \ `uvm_print_int(ARG, $bits(ARG), `m_uvm_field_radix(FLAG),T,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_enum_read(local_success__, \ local_rsrc__, \ T, \ ARG, \ this) \ /* TODO if(local_success__ && printing matches) */ \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_real(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_real(ARG, local_rhs__.ARG, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_real(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_real(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_real(`"ARG`", ARG, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ __local_printer__.print_real(`"ARG`", ARG); \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_real_read(local_success__, \ local_rsrc__, \ ARG, \ this) \ /* TODO if(local_success__ && printing matches) */ \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_event(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `m_uvm_compare_begin(ARG, local_rhs__.ARG, __local_comparer__) \ __local_comparer__.print_msg({`"ARG`", " event miscompare"}); \ `m_uvm_compare_end \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ __local_printer__.print_generic(`"ARG`", "event", -1, ""); \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_sarray_int(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_sarray_int(ARG, local_rhs__.ARG, `m_uvm_field_radix(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_sarray(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_sarray(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_int(ARG, `m_uvm_field_radix(FLAG), __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_sarray_int(ARG, \ `m_uvm_field_radix(FLAG),, \ __local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/SARRAY_SIZE", $sformatf("Static array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if ((local_index__ >= $size(ARG)) || (local_index__ < 0)) begin \ `uvm_warning("UVM/FIELDS/SARRAY_IDX", $sformatf("Index '%d' is not valid for static array '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ $size(ARG))) \ end \ else begin \ `uvm_resource_builtin_int_read(local_success__, \ local_rsrc__, \ ARG[local_index__], \ this) \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_sarray_object(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ foreach(ARG[i]) begin \ `uvm_copy_object(ARG[i], local_rhs__.ARG[i], `m_uvm_field_recursion(FLAG), __local_copier__) \ end \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_sarray_object(ARG, local_rhs__.ARG, `m_uvm_field_recursion(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ if (`m_uvm_field_recursion(FLAG) != UVM_REFERENCE) \ foreach(ARG[i]) \ `uvm_pack_object(ARG[i], __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ if (`m_uvm_field_recursion(FLAG) != UVM_REFERENCE) \ foreach(ARG[i]) \ `uvm_unpack_object(ARG[i], __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_object(ARG, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_sarray_object(ARG, `m_uvm_field_recursion(FLAG), __local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/SARRAY_SIZE", $sformatf("Static array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if ((local_index__ >= $size(ARG)) || (local_index__ < 0)) begin \ `uvm_warning("UVM/FIELDS/SARRAY_IDX", $sformatf("Index '%d' is not valid for static array '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ $size(ARG))) \ end \ else begin \ `uvm_resource_read(local_success__, \ local_rsrc__, \ uvm_object, \ local_obj__, \ this) \ if (local_success__) begin \ if (local_obj__ == null) begin \ ARG[local_index__] = null; \ end else if (!$cast(ARG[local_index__], local_obj__)) begin \ `uvm_warning("UVM/FIELDS/OBJ_TYPE", $sformatf("Can't set field '%s[%d]' on '%s' with '%s' type", \ `"ARG`", \ local_index__, \ this.get_full_name(), \ local_obj__.get_type_name())) \ end \ end \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_sarray_string(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_sarray_string(ARG, local_rhs__.ARG, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ foreach(ARG[i]) \ `uvm_pack_string(ARG[i], __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ foreach(ARG[i]) \ `uvm_unpack_string(ARG[i], __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_string(ARG, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_sarray_string(ARG,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/SARRAY_SIZE", $sformatf("Static array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if ((local_index__ >= $size(ARG)) || (local_index__ < 0)) begin \ `uvm_warning("UVM/FIELDS/SARRAY_IDX", $sformatf("Index '%d' is not valid for static array '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ $size(ARG))) \ end \ else begin \ `uvm_resource_read(local_success__, \ local_rsrc__, \ string, \ ARG[local_index__], \ this) \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_sarray_enum(T,ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_sarray_enum(ARG, local_rhs__.ARG, T, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ foreach (ARG[i]) \ `uvm_pack_enumN(ARG[i], $bits(T), __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ foreach (ARG[i]) \ `uvm_unpack_enumN(ARG[i], $bits(T), T, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_enum(ARG, T, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_sarray_enum(T, ARG ,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/SARRAY_SIZE", $sformatf("Static array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if ((local_index__ >= $size(ARG)) || (local_index__ < 0)) begin \ `uvm_warning("UVM/FIELDS/SARRAY_IDX", $sformatf("Index '%d' is not valid for static array '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ $size(ARG))) \ end \ else begin \ `uvm_resource_enum_read(local_success__, \ local_rsrc__, \ T, \ ARG[local_index__], \ this) \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define m_uvm_queue_resize(ARG, SZ) \ if (ARG.size() > SZ) \ ARG = ARG[0:SZ-1]; \ else \ while (ARG.size() < SZ) ARG.push_back(ARG[SZ]); `define m_uvm_da_resize(ARG, SZ) \ if (ARG.size() != SZ) ARG = new[SZ](ARG); `define m_uvm_field_qda_int(TYPE,ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_qda_int(ARG, local_rhs__.ARG, `m_uvm_field_radix(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_``TYPE``(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_``TYPE``(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_int(ARG, `m_uvm_field_radix(FLAG), __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_qda_int(TYPE, ARG, `m_uvm_field_radix(FLAG),,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_builtin_int_read(local_success__, \ local_rsrc__, \ local_size__, \ this) \ if (local_success__) \ `m_uvm_``TYPE``_resize(ARG, local_size__) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if (local_index__ < 0) begin \ `uvm_warning("UVM/FIELDS/QDA_IDX", $sformatf("Index '%0d' is not valid for field '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ ARG.size() ) ) \ end \ else begin \ bit tmp_stream__[]; \ `uvm_resource_builtin_int_read(local_success__, \ local_rsrc__, \ { << bit { tmp_stream__ }}, \ this) \ if (local_success__) begin \ if (local_index__ >= ARG.size()) \ `m_uvm_``TYPE``_resize(ARG, local_index__ + 1) \ tmp_stream__ = new[$bits(ARG[local_index__])] (tmp_stream__); \ ARG[local_index__] = { << bit { tmp_stream__ }}; \ end \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_array_int(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_qda_int(da,ARG,FLAG) `define m_uvm_field_qda_object(TYPE,ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ if ((`m_uvm_field_recursion(FLAG) == UVM_REFERENCE) || !local_rhs__.ARG.size()) \ ARG = local_rhs__.ARG; \ else begin \ `m_uvm_``TYPE``_resize(ARG, local_rhs__.ARG.size()) \ foreach (ARG[i]) \ `uvm_copy_object(ARG[i], local_rhs__.ARG[i], `m_uvm_field_recursion(FLAG), __local_copier__) \ end \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_qda_object(ARG, local_rhs__.ARG, `m_uvm_field_recursion(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ __local_packer__.pack_field_int(ARG.size(), 32); \ foreach (ARG[i]) \ `uvm_pack_object(ARG[i], __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ local_size__ = __local_packer__.unpack_field_int(32); \ `m_uvm_``TYPE``_resize(ARG, local_size__); \ foreach (ARG[i]) \ `uvm_unpack_object(ARG[i], __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_object(ARG, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_qda_object(TYPE, ARG, `m_uvm_field_recursion(FLAG),__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_builtin_int_read(local_success__, \ local_rsrc__, \ local_size__, \ this) \ if (local_success__) \ `m_uvm_``TYPE``_resize(ARG, local_size__) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if (local_index__ < 0) begin \ `uvm_warning("UVM/FIELDS/QDA_IDX", $sformatf("Index '%0d' is not valid for field '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ ARG.size() ) ) \ end \ else begin \ `uvm_resource_read(local_success__, \ local_rsrc__, \ uvm_object, \ local_obj__, \ this) \ if (local_success__) begin \ if (local_index__ >= ARG.size()) \ `m_uvm_``TYPE``_resize(ARG, local_index__ + 1) \ if (local_obj__ == null) begin \ ARG[local_index__] = null; \ end else if (!$cast(ARG[local_index__], local_obj__)) begin \ `uvm_error("UVM/FIELDS/QDA_OBJ_TYPE", \ $sformatf("Can't set field '%s[%0d]' on '%s' with '%s' type", \ `"ARG`", \ local_index__, \ this.get_full_name(), \ local_obj__.get_type_name())) \ end \ end \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_array_object(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_qda_object(da,ARG,FLAG) `define uvm_field_array_string(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_qda_string(da,ARG,FLAG) `define m_uvm_field_qda_string(TYPE,ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_qda_string(ARG, local_rhs__.ARG, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ __local_packer__.pack_field_int(ARG.size(), 32); \ foreach (ARG[i]) \ `uvm_pack_string(ARG[i], __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ local_size__ = __local_packer__.unpack_field_int(32); \ `m_uvm_``TYPE``_resize(ARG, local_size__) \ foreach (ARG[i]) \ `uvm_unpack_string(ARG[i], __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_string(ARG, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_qda_string(TYPE, ARG,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_builtin_int_read(local_success__, \ local_rsrc__, \ local_size__, \ this) \ if (local_success__) \ `m_uvm_``TYPE``_resize(ARG, local_size__) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if (local_index__ < 0) begin \ `uvm_warning("UVM/FIELDS/QDA_IDX", $sformatf("Index '%0d' is not valid for field '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ ARG.size() ) ) \ end \ else begin \ string tmp_string__; \ `uvm_resource_read(local_success__, \ local_rsrc__, \ string, \ tmp_string__, \ this) \ if (local_success__) begin \ if (local_index__ >= ARG.size()) \ `m_uvm_``TYPE``_resize(ARG, local_index__ + 1) \ ARG[local_index__] = tmp_string__; \ end \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_array_enum(T,ARG,FLAG=UVM_DEFAULT) \ `m_field_qda_enum(da,T,ARG,FLAG) `define m_field_qda_enum(TYPE,T,ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_qda_enum(ARG, local_rhs__.ARG, T, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ __local_packer__.pack_field_int(ARG.size(), 32); \ foreach (ARG[i]) \ `uvm_pack_enumN(ARG[i], $bits(T), __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ local_size__ = __local_packer__.unpack_field_int(32); \ `m_uvm_``TYPE``_resize(ARG, local_size__) \ foreach (ARG[i]) \ `uvm_unpack_enumN(ARG[i], $bits(T), T, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_enum(ARG, T, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_qda_enum(TYPE, T, ARG,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_builtin_int_read(local_success__, \ local_rsrc__, \ local_size__, \ this) \ if (local_success__) \ `m_uvm_``TYPE``_resize(ARG, local_size__) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if (local_index__ < 0) begin \ `uvm_warning("UVM/FIELDS/QDA_IDX", $sformatf("Index '%0d' is not valid for field '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ ARG.size() ) ) \ end \ else begin \ T tmp_enum__; \ `uvm_resource_enum_read(local_success__, \ local_rsrc__, \ T, \ tmp_enum__, \ this) \ if (local_success__) begin \ if (local_index__ >= ARG.size()) \ `m_uvm_``TYPE``_resize(ARG, local_index__ + 1) \ ARG[local_index__] = tmp_enum__; \ end \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_queue_int(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_qda_int(queue,ARG,FLAG) `define uvm_field_queue_object(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_qda_object(queue,ARG,FLAG) `define uvm_field_queue_string(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_qda_string(queue,ARG,FLAG) `define uvm_field_queue_enum(T,ARG,FLAG=UVM_DEFAULT) \ `m_field_qda_enum(queue,T,ARG,FLAG) `define uvm_field_aa_int_string(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_aa_int_string(ARG, local_rhs__.ARG, `m_uvm_field_radix(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_aa_int_string(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_aa_int_string(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_aa_int_string(ARG, `m_uvm_field_radix(FLAG), int, __local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/AA_SIZE", $sformatf("Associative array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ `uvm_resource_builtin_int_read(local_success__, \ local_rsrc__, \ ARG[local_index__], \ this) \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_aa_object_string(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ `uvm_copy_aa_object(ARG, local_rhs__.ARG, `m_uvm_field_recursion(FLAG), __local_copier__) \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_aa_object_string(ARG, local_rhs__.ARG, `m_uvm_field_recursion(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ if (`m_uvm_field_recursion(FLAG) != UVM_REFERENCE) \ `uvm_pack_aa_object_string(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ if (`m_uvm_field_recursion(FLAG) != UVM_REFERENCE) \ `uvm_unpack_aa_object_string(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_aa_object_string(ARG, `m_uvm_field_recursion(FLAG),__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/AA_SIZE", $sformatf("Associative array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ `uvm_resource_read(local_success__, \ local_rsrc__, \ uvm_object, \ local_obj__, \ this) \ if (local_success__) begin \ if (local_obj__ == null) begin \ ARG[local_index__] = null; \ end else if (!$cast(ARG[local_index__], local_obj__)) begin \ `uvm_warning("UVM/FIELDS/OBJ_TYPE", $sformatf("Can't set field '%s[%s]' on '%s' with '%s' type", \ `"ARG`", \ local_index__, \ this.get_full_name(), \ local_obj__.get_type_name())) \ end \ end \ /* TODO if(local_success__ && printing matches) */ \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_aa_string_string(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_aa_string_string(ARG, local_rhs__.ARG, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_aa_string_string(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_aa_string_string(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_aa_string_string(ARG,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/AA_SIZE", $sformatf("Associative array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ `uvm_resource_read(local_success__, \ local_rsrc__, \ string, \ ARG[local_index__], \ this) \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_aa_object_int(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_object_key(int, ARG, FLAG) `define uvm_field_aa_object_key(KEY, ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ `uvm_copy_aa_object(ARG, local_rhs__.ARG, `m_uvm_field_recursion(FLAG), __local_copier__) \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_aa_object_int(ARG, local_rhs__.ARG, `m_uvm_field_recursion(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ if (`m_uvm_field_recursion(FLAG) != UVM_REFERENCE) \ `uvm_pack_aa_object_intN(ARG, $bits(KEY), __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ if (`m_uvm_field_recursion(FLAG) != UVM_REFERENCE) \ `uvm_unpack_aa_object_intN(ARG, $bits(KEY), __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_aa_object_int(ARG, `m_uvm_field_recursion(FLAG), KEY,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/SARRAY_SIZE", $sformatf("Static array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ KEY local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ `uvm_resource_read(local_success__, \ local_rsrc__, \ uvm_object, \ local_obj__, \ this) \ if (local_success__) begin \ if (local_obj__ == null) begin \ ARG[local_index__] = null; \ end else if (!$cast(ARG[local_index__], local_obj__)) begin \ `uvm_warning("UVM/FIELDS/OBJ_TYPE", $sformatf("Can't set field '%s[%d]' on '%s' with '%s' type", \ `"ARG`", \ local_index__, \ this.get_full_name(), \ local_obj__.get_type_name())) \ end \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_aa_string_int(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_string_key(int, ARG, FLAG) `define uvm_field_aa_string_key(KEY, ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_aa_string_int(ARG, local_rhs__.ARG, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_aa_string_intN(ARG, $bits(KEY), __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_aa_string_intN(ARG, $bits(KEY), __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(PRINT,FLAG) \ /* TODO */ \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/SARRAY_SIZE", $sformatf("Static array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ KEY local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ `uvm_resource_read(local_success__, \ local_rsrc__, \ string, \ ARG[local_index__], \ this) \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_aa_int_int(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(int, ARG, FLAG) \ `define uvm_field_aa_int_int_unsigned(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(int unsigned, ARG, FLAG) `define uvm_field_aa_int_integer(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(integer, ARG, FLAG) `define uvm_field_aa_int_integer_unsigned(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(integer unsigned, ARG, FLAG) `define uvm_field_aa_int_byte(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(byte, ARG, FLAG) `define uvm_field_aa_int_byte_unsigned(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(byte unsigned, ARG, FLAG) `define uvm_field_aa_int_shortint(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(shortint, ARG, FLAG) `define uvm_field_aa_int_shortint_unsigned(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(shortint unsigned, ARG, FLAG) `define uvm_field_aa_int_longint(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(longint, ARG, FLAG) `define uvm_field_aa_int_longint_unsigned(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(longint unsigned, ARG, FLAG) `define uvm_field_aa_int_key(KEY, ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_aa_int_int(ARG, local_rhs__.ARG, `m_uvm_field_radix(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_aa_int_intN(ARG, $bits(KEY), __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_aa_int_intN(ARG, $bits(KEY), __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_aa_int_int(ARG, `m_uvm_field_radix(FLAG), , KEY,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/AA_SIZE", $sformatf("Associative array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ KEY local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ `uvm_resource_int_read(local_success__, \ local_rsrc__, \ KEY, \ ARG[local_index__], \ this) \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_aa_int_enumkey(KEY, ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_aa_int_int(ARG, local_rhs__.ARG, `m_uvm_field_radix(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_aa_int_enum(ARG, KEY, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_aa_int_enum(ARG, KEY, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_aa_int_enum(KEY, ARG, `m_uvm_field_radix(FLAG),,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/AA_SIZE", $sformatf("Associative array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ KEY local_index__; \ bit[$bits(KEY)-1:0] local_bit_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_bit_index__); \ if (local_code__ > 0) begin \ local_index__ = KEY'(local_bit_index__); \ `uvm_resource_int_read(local_success__, \ local_rsrc__, \ KEY, \ ARG[local_index__], \ this) \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_sarray_real(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_sarray_real(ARG, local_rhs__.ARG, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_sarray_real(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_sarray_real(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_real(ARG, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_sarray_real(ARG,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/SARRAY_SIZE", $sformatf("Static array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if ((local_index__ >= $size(ARG)) || (local_index__ < 0)) begin \ `uvm_warning("UVM/FIELDS/SARRAY_IDX", $sformatf("Index '%d' is not valid for static array '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ $size(ARG))) \ end \ else begin \ `uvm_resource_real_read(local_success__, \ local_rsrc__, \ ARG[local_index__], \ this) \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define m_uvm_field_qda_real(TYPE,ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_qda_real(ARG, local_rhs__.ARG, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_``TYPE``_real(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_``TYPE``_real(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_real(ARG, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_qda_real(TYPE, ARG,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_real_read(local_success__, \ local_rsrc__, \ local_size__, \ this) \ if (local_success__) \ `m_uvm_``TYPE``_resize(ARG, local_size__) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if (local_index__ < 0) begin \ `uvm_warning("UVM/FIELDS/QDA_IDX", $sformatf("Index '%0d' is not valid for field '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ ARG.size() ) ) \ end \ else begin \ real tmp_real__; \ `uvm_resource_real_read(local_success__, \ local_rsrc__, \ tmp_real__, \ this) \ if (local_success__) begin \ if (local_index__ >= ARG.size()) \ `m_uvm_``TYPE``_resize(ARG, local_index__ + 1) \ ARG[local_index__] = tmp_real__; \ end \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_array_real(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_qda_real(da,ARG,FLAG) `define uvm_field_queue_real(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_qda_real(queue,ARG,FLAG) `define uvm_blocking_put_imp_decl(SFX) \ class uvm_blocking_put_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_BLOCKING_PUT_MASK,`"uvm_blocking_put_imp``SFX`",IMP) \ `UVM_BLOCKING_PUT_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_nonblocking_put_imp_decl(SFX) \ class uvm_nonblocking_put_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_NONBLOCKING_PUT_MASK,`"uvm_nonblocking_put_imp``SFX`",IMP) \ `UVM_NONBLOCKING_PUT_IMP_SFX( SFX, m_imp, T, t) \ endclass `define uvm_put_imp_decl(SFX) \ class uvm_put_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_PUT_MASK,`"uvm_put_imp``SFX`",IMP) \ `UVM_BLOCKING_PUT_IMP_SFX(SFX, m_imp, T, t) \ `UVM_NONBLOCKING_PUT_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_blocking_get_imp_decl(SFX) \ class uvm_blocking_get_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_BLOCKING_GET_MASK,`"uvm_blocking_get_imp``SFX`",IMP) \ `UVM_BLOCKING_GET_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_nonblocking_get_imp_decl(SFX) \ class uvm_nonblocking_get_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_NONBLOCKING_GET_MASK,`"uvm_nonblocking_get_imp``SFX`",IMP) \ `UVM_NONBLOCKING_GET_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_get_imp_decl(SFX) \ class uvm_get_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_GET_MASK,`"uvm_get_imp``SFX`",IMP) \ `UVM_BLOCKING_GET_IMP_SFX(SFX, m_imp, T, t) \ `UVM_NONBLOCKING_GET_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_blocking_peek_imp_decl(SFX) \ class uvm_blocking_peek_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_BLOCKING_PEEK_MASK,`"uvm_blocking_peek_imp``SFX`",IMP) \ `UVM_BLOCKING_PEEK_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_nonblocking_peek_imp_decl(SFX) \ class uvm_nonblocking_peek_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_NONBLOCKING_PEEK_MASK,`"uvm_nonblocking_peek_imp``SFX`",IMP) \ `UVM_NONBLOCKING_PEEK_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_peek_imp_decl(SFX) \ class uvm_peek_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_PEEK_MASK,`"uvm_peek_imp``SFX`",IMP) \ `UVM_BLOCKING_PEEK_IMP_SFX(SFX, m_imp, T, t) \ `UVM_NONBLOCKING_PEEK_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_blocking_get_peek_imp_decl(SFX) \ class uvm_blocking_get_peek_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_BLOCKING_GET_PEEK_MASK,`"uvm_blocking_get_peek_imp``SFX`",IMP) \ `UVM_BLOCKING_GET_IMP_SFX(SFX, m_imp, T, t) \ `UVM_BLOCKING_PEEK_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_nonblocking_get_peek_imp_decl(SFX) \ class uvm_nonblocking_get_peek_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_NONBLOCKING_GET_PEEK_MASK,`"uvm_nonblocking_get_peek_imp``SFX`",IMP) \ `UVM_NONBLOCKING_GET_IMP_SFX(SFX, m_imp, T, t) \ `UVM_NONBLOCKING_PEEK_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_get_peek_imp_decl(SFX) \ class uvm_get_peek_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_GET_PEEK_MASK,`"uvm_get_peek_imp``SFX`",IMP) \ `UVM_BLOCKING_GET_IMP_SFX(SFX, m_imp, T, t) \ `UVM_NONBLOCKING_GET_IMP_SFX(SFX, m_imp, T, t) \ `UVM_BLOCKING_PEEK_IMP_SFX(SFX, m_imp, T, t) \ `UVM_NONBLOCKING_PEEK_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_blocking_master_imp_decl(SFX) \ class uvm_blocking_master_imp``SFX #(type REQ=int, type RSP=int, type IMP=int, \ type REQ_IMP=IMP, type RSP_IMP=IMP) \ extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); \ typedef IMP this_imp_type; \ typedef REQ_IMP this_req_type; \ typedef RSP_IMP this_rsp_type; \ `UVM_MS_IMP_COMMON(`UVM_TLM_BLOCKING_MASTER_MASK,`"uvm_blocking_master_imp``SFX`") \ \ `UVM_BLOCKING_PUT_IMP_SFX(SFX, m_req_imp, REQ, t) \ \ `UVM_BLOCKING_GET_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ `UVM_BLOCKING_PEEK_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ \ endclass `define uvm_nonblocking_master_imp_decl(SFX) \ class uvm_nonblocking_master_imp``SFX #(type REQ=int, type RSP=int, type IMP=int, \ type REQ_IMP=IMP, type RSP_IMP=IMP) \ extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); \ typedef IMP this_imp_type; \ typedef REQ_IMP this_req_type; \ typedef RSP_IMP this_rsp_type; \ `UVM_MS_IMP_COMMON(`UVM_TLM_NONBLOCKING_MASTER_MASK,`"uvm_nonblocking_master_imp``SFX`") \ \ `UVM_NONBLOCKING_PUT_IMP_SFX(SFX, m_req_imp, REQ, t) \ \ `UVM_NONBLOCKING_GET_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ `UVM_NONBLOCKING_PEEK_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ \ endclass `define uvm_master_imp_decl(SFX) \ class uvm_master_imp``SFX #(type REQ=int, type RSP=int, type IMP=int, \ type REQ_IMP=IMP, type RSP_IMP=IMP) \ extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); \ typedef IMP this_imp_type; \ typedef REQ_IMP this_req_type; \ typedef RSP_IMP this_rsp_type; \ `UVM_MS_IMP_COMMON(`UVM_TLM_MASTER_MASK,`"uvm_master_imp``SFX`") \ \ `UVM_BLOCKING_PUT_IMP_SFX(SFX, m_req_imp, REQ, t) \ `UVM_NONBLOCKING_PUT_IMP_SFX(SFX, m_req_imp, REQ, t) \ \ `UVM_BLOCKING_GET_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ `UVM_BLOCKING_PEEK_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ `UVM_NONBLOCKING_GET_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ `UVM_NONBLOCKING_PEEK_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ \ endclass `define uvm_blocking_slave_imp_decl(SFX) \ class uvm_blocking_slave_imp``SFX #(type REQ=int, type RSP=int, type IMP=int, \ type REQ_IMP=IMP, type RSP_IMP=IMP) \ extends uvm_port_base #(uvm_tlm_if_base #(RSP, REQ)); \ typedef IMP this_imp_type; \ typedef REQ_IMP this_req_type; \ typedef RSP_IMP this_rsp_type; \ `UVM_MS_IMP_COMMON(`UVM_TLM_BLOCKING_SLAVE_MASK,`"uvm_blocking_slave_imp``SFX`") \ \ `UVM_BLOCKING_PUT_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ \ `UVM_BLOCKING_GET_IMP_SFX(SFX, m_req_imp, REQ, t) \ `UVM_BLOCKING_PEEK_IMP_SFX(SFX, m_req_imp, REQ, t) \ \ endclass `define uvm_nonblocking_slave_imp_decl(SFX) \ class uvm_nonblocking_slave_imp``SFX #(type REQ=int, type RSP=int, type IMP=int, \ type REQ_IMP=IMP, type RSP_IMP=IMP) \ extends uvm_port_base #(uvm_tlm_if_base #(RSP, REQ)); \ typedef IMP this_imp_type; \ typedef REQ_IMP this_req_type; \ typedef RSP_IMP this_rsp_type; \ `UVM_MS_IMP_COMMON(`UVM_TLM_NONBLOCKING_SLAVE_MASK,`"uvm_nonblocking_slave_imp``SFX`") \ \ `UVM_NONBLOCKING_PUT_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ \ `UVM_NONBLOCKING_GET_IMP_SFX(SFX, m_req_imp, REQ, t) \ `UVM_NONBLOCKING_PEEK_IMP_SFX(SFX, m_req_imp, REQ, t) \ \ endclass `define uvm_slave_imp_decl(SFX) \ class uvm_slave_imp``SFX #(type REQ=int, type RSP=int, type IMP=int, \ type REQ_IMP=IMP, type RSP_IMP=IMP) \ extends uvm_port_base #(uvm_tlm_if_base #(RSP, REQ)); \ typedef IMP this_imp_type; \ typedef REQ_IMP this_req_type; \ typedef RSP_IMP this_rsp_type; \ `UVM_MS_IMP_COMMON(`UVM_TLM_SLAVE_MASK,`"uvm_slave_imp``SFX`") \ \ `UVM_BLOCKING_PUT_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ `UVM_NONBLOCKING_PUT_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ \ `UVM_BLOCKING_GET_IMP_SFX(SFX, m_req_imp, REQ, t) \ `UVM_BLOCKING_PEEK_IMP_SFX(SFX, m_req_imp, REQ, t) \ `UVM_NONBLOCKING_GET_IMP_SFX(SFX, m_req_imp, REQ, t) \ `UVM_NONBLOCKING_PEEK_IMP_SFX(SFX, m_req_imp, REQ, t) \ \ endclass `define uvm_blocking_transport_imp_decl(SFX) \ class uvm_blocking_transport_imp``SFX #(type REQ=int, type RSP=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); \ `UVM_IMP_COMMON(`UVM_TLM_BLOCKING_TRANSPORT_MASK,`"uvm_blocking_transport_imp``SFX`",IMP) \ `UVM_BLOCKING_TRANSPORT_IMP_SFX(SFX, m_imp, REQ, RSP, req, rsp) \ endclass `define uvm_nonblocking_transport_imp_decl(SFX) \ class uvm_nonblocking_transport_imp``SFX #(type REQ=int, type RSP=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); \ `UVM_IMP_COMMON(`UVM_TLM_NONBLOCKING_TRANSPORT_MASK,`"uvm_nonblocking_transport_imp``SFX`",IMP) \ `UVM_NONBLOCKING_TRANSPORT_IMP_SFX(SFX, m_imp, REQ, RSP, req, rsp) \ endclass `define uvm_non_blocking_transport_imp_decl(SFX) \ `uvm_nonblocking_transport_imp_decl(SFX) `define uvm_transport_imp_decl(SFX) \ class uvm_transport_imp``SFX #(type REQ=int, type RSP=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); \ `UVM_IMP_COMMON(`UVM_TLM_TRANSPORT_MASK,`"uvm_transport_imp``SFX`",IMP) \ `UVM_BLOCKING_TRANSPORT_IMP_SFX(SFX, m_imp, REQ, RSP, req, rsp) \ `UVM_NONBLOCKING_TRANSPORT_IMP_SFX(SFX, m_imp, REQ, RSP, req, rsp) \ endclass `define uvm_analysis_imp_decl(SFX) \ class uvm_analysis_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_ANALYSIS_MASK,`"uvm_analysis_imp``SFX`",IMP) \ function void write( input T t); \ m_imp.write``SFX( t); \ endfunction \ \ endclass `define UVM_BLOCKING_PUT_IMP_SFX(SFX, imp, TYPE, arg) \ task put( input TYPE arg); imp.put``SFX( arg); endtask `define UVM_BLOCKING_GET_IMP_SFX(SFX, imp, TYPE, arg) \ task get( output TYPE arg); imp.get``SFX( arg); endtask `define UVM_BLOCKING_PEEK_IMP_SFX(SFX, imp, TYPE, arg) \ task peek( output TYPE arg);imp.peek``SFX( arg); endtask `define UVM_NONBLOCKING_PUT_IMP_SFX(SFX, imp, TYPE, arg) \ function bit try_put( input TYPE arg); \ if( !imp.try_put``SFX( arg)) return 0; \ return 1; \ endfunction \ function bit can_put(); return imp.can_put``SFX(); endfunction `define UVM_NONBLOCKING_GET_IMP_SFX(SFX, imp, TYPE, arg) \ function bit try_get( output TYPE arg); \ if( !imp.try_get``SFX( arg)) return 0; \ return 1; \ endfunction \ function bit can_get(); return imp.can_get``SFX(); endfunction `define UVM_NONBLOCKING_PEEK_IMP_SFX(SFX, imp, TYPE, arg) \ function bit try_peek( output TYPE arg); \ if( !imp.try_peek``SFX( arg)) return 0; \ return 1; \ endfunction \ function bit can_peek(); return imp.can_peek``SFX(); endfunction `define UVM_BLOCKING_TRANSPORT_IMP_SFX(SFX, imp, REQ, RSP, req_arg, rsp_arg) \ task transport( input REQ req_arg, output RSP rsp_arg); \ imp.transport``SFX(req_arg, rsp_arg); \ endtask `define UVM_NONBLOCKING_TRANSPORT_IMP_SFX(SFX, imp, REQ, RSP, req_arg, rsp_arg) \ function bit nb_transport( input REQ req_arg, output RSP rsp_arg); \ if(imp) return imp.nb_transport``SFX(req_arg, rsp_arg); \ endfunction `define UVM_SEQ_ITEM_PULL_IMP(imp, REQ, RSP, req_arg, rsp_arg) \ function void disable_auto_item_recording(); imp.disable_auto_item_recording(); endfunction \ function bit is_auto_item_recording_enabled(); return imp.is_auto_item_recording_enabled(); endfunction \ task get_next_item(output REQ req_arg); imp.get_next_item(req_arg); endtask \ task try_next_item(output REQ req_arg); imp.try_next_item(req_arg); endtask \ function void item_done(input RSP rsp_arg = null); imp.item_done(rsp_arg); endfunction \ task wait_for_sequences(); imp.wait_for_sequences(); endtask \ function bit has_do_available(); return imp.has_do_available(); endfunction \ function void put_response(input RSP rsp_arg); imp.put_response(rsp_arg); endfunction \ task get(output REQ req_arg); imp.get(req_arg); endtask \ task peek(output REQ req_arg); imp.peek(req_arg); endtask \ task put(input RSP rsp_arg); imp.put(rsp_arg); endtask `define UVM_TLM_BLOCKING_PUT_MASK (1<<0) `define UVM_TLM_BLOCKING_GET_MASK (1<<1) `define UVM_TLM_BLOCKING_PEEK_MASK (1<<2) `define UVM_TLM_BLOCKING_TRANSPORT_MASK (1<<3) `define UVM_TLM_NONBLOCKING_PUT_MASK (1<<4) `define UVM_TLM_NONBLOCKING_GET_MASK (1<<5) `define UVM_TLM_NONBLOCKING_PEEK_MASK (1<<6) `define UVM_TLM_NONBLOCKING_TRANSPORT_MASK (1<<7) `define UVM_TLM_ANALYSIS_MASK (1<<8) `define UVM_TLM_MASTER_BIT_MASK (1<<9) `define UVM_TLM_SLAVE_BIT_MASK (1<<10) `define UVM_TLM_PUT_MASK (`UVM_TLM_BLOCKING_PUT_MASK | `UVM_TLM_NONBLOCKING_PUT_MASK) `define UVM_TLM_GET_MASK (`UVM_TLM_BLOCKING_GET_MASK | `UVM_TLM_NONBLOCKING_GET_MASK) `define UVM_TLM_PEEK_MASK (`UVM_TLM_BLOCKING_PEEK_MASK | `UVM_TLM_NONBLOCKING_PEEK_MASK) `define UVM_TLM_BLOCKING_GET_PEEK_MASK (`UVM_TLM_BLOCKING_GET_MASK | `UVM_TLM_BLOCKING_PEEK_MASK) `define UVM_TLM_BLOCKING_MASTER_MASK (`UVM_TLM_BLOCKING_PUT_MASK | `UVM_TLM_BLOCKING_GET_MASK | `UVM_TLM_BLOCKING_PEEK_MASK | `UVM_TLM_MASTER_BIT_MASK) `define UVM_TLM_BLOCKING_SLAVE_MASK (`UVM_TLM_BLOCKING_PUT_MASK | `UVM_TLM_BLOCKING_GET_MASK | `UVM_TLM_BLOCKING_PEEK_MASK | `UVM_TLM_SLAVE_BIT_MASK) `define UVM_TLM_NONBLOCKING_GET_PEEK_MASK (`UVM_TLM_NONBLOCKING_GET_MASK | `UVM_TLM_NONBLOCKING_PEEK_MASK) `define UVM_TLM_NONBLOCKING_MASTER_MASK (`UVM_TLM_NONBLOCKING_PUT_MASK | `UVM_TLM_NONBLOCKING_GET_MASK | `UVM_TLM_NONBLOCKING_PEEK_MASK | `UVM_TLM_MASTER_BIT_MASK) `define UVM_TLM_NONBLOCKING_SLAVE_MASK (`UVM_TLM_NONBLOCKING_PUT_MASK | `UVM_TLM_NONBLOCKING_GET_MASK | `UVM_TLM_NONBLOCKING_PEEK_MASK | `UVM_TLM_SLAVE_BIT_MASK) `define UVM_TLM_GET_PEEK_MASK (`UVM_TLM_GET_MASK | `UVM_TLM_PEEK_MASK) `define UVM_TLM_MASTER_MASK (`UVM_TLM_BLOCKING_MASTER_MASK | `UVM_TLM_NONBLOCKING_MASTER_MASK) `define UVM_TLM_SLAVE_MASK (`UVM_TLM_BLOCKING_SLAVE_MASK | `UVM_TLM_NONBLOCKING_SLAVE_MASK) `define UVM_TLM_TRANSPORT_MASK (`UVM_TLM_BLOCKING_TRANSPORT_MASK | `UVM_TLM_NONBLOCKING_TRANSPORT_MASK) `define UVM_SEQ_ITEM_GET_NEXT_ITEM_MASK (1<<0) `define UVM_SEQ_ITEM_TRY_NEXT_ITEM_MASK (1<<1) `define UVM_SEQ_ITEM_ITEM_DONE_MASK (1<<2) `define UVM_SEQ_ITEM_HAS_DO_AVAILABLE_MASK (1<<3) `define UVM_SEQ_ITEM_WAIT_FOR_SEQUENCES_MASK (1<<4) `define UVM_SEQ_ITEM_PUT_RESPONSE_MASK (1<<5) `define UVM_SEQ_ITEM_PUT_MASK (1<<6) `define UVM_SEQ_ITEM_GET_MASK (1<<7) `define UVM_SEQ_ITEM_PEEK_MASK (1<<8) `define UVM_SEQ_ITEM_PULL_MASK (`UVM_SEQ_ITEM_GET_NEXT_ITEM_MASK | `UVM_SEQ_ITEM_TRY_NEXT_ITEM_MASK | \ `UVM_SEQ_ITEM_ITEM_DONE_MASK | `UVM_SEQ_ITEM_HAS_DO_AVAILABLE_MASK | \ `UVM_SEQ_ITEM_WAIT_FOR_SEQUENCES_MASK | `UVM_SEQ_ITEM_PUT_RESPONSE_MASK | \ `UVM_SEQ_ITEM_PUT_MASK | `UVM_SEQ_ITEM_GET_MASK | `UVM_SEQ_ITEM_PEEK_MASK) `define UVM_SEQ_ITEM_UNI_PULL_MASK (`UVM_SEQ_ITEM_GET_NEXT_ITEM_MASK | `UVM_SEQ_ITEM_TRY_NEXT_ITEM_MASK | \ `UVM_SEQ_ITEM_ITEM_DONE_MASK | `UVM_SEQ_ITEM_HAS_DO_AVAILABLE_MASK | \ `UVM_SEQ_ITEM_WAIT_FOR_SEQUENCES_MASK | `UVM_SEQ_ITEM_GET_MASK | \ `UVM_SEQ_ITEM_PEEK_MASK) `define UVM_SEQ_ITEM_PUSH_MASK (`UVM_SEQ_ITEM_PUT_MASK) `define UVM_TLM_IMPS_SVH `define UVM_BLOCKING_PUT_IMP(imp, TYPE, arg) \ task put (TYPE arg); \ imp.put(arg); \ endtask `define UVM_NONBLOCKING_PUT_IMP(imp, TYPE, arg) \ function bit try_put (TYPE arg); \ return imp.try_put(arg); \ endfunction \ function bit can_put(); \ return imp.can_put(); \ endfunction `define UVM_BLOCKING_GET_IMP(imp, TYPE, arg) \ task get (output TYPE arg); \ imp.get(arg); \ endtask `define UVM_NONBLOCKING_GET_IMP(imp, TYPE, arg) \ function bit try_get (output TYPE arg); \ return imp.try_get(arg); \ endfunction \ function bit can_get(); \ return imp.can_get(); \ endfunction `define UVM_BLOCKING_PEEK_IMP(imp, TYPE, arg) \ task peek (output TYPE arg); \ imp.peek(arg); \ endtask `define UVM_NONBLOCKING_PEEK_IMP(imp, TYPE, arg) \ function bit try_peek (output TYPE arg); \ return imp.try_peek(arg); \ endfunction \ function bit can_peek(); \ return imp.can_peek(); \ endfunction `define UVM_BLOCKING_TRANSPORT_IMP(imp, REQ, RSP, req_arg, rsp_arg) \ task transport (REQ req_arg, output RSP rsp_arg); \ imp.transport(req_arg, rsp_arg); \ endtask `define UVM_NONBLOCKING_TRANSPORT_IMP(imp, REQ, RSP, req_arg, rsp_arg) \ function bit nb_transport (REQ req_arg, output RSP rsp_arg); \ return imp.nb_transport(req_arg, rsp_arg); \ endfunction `define UVM_PUT_IMP(imp, TYPE, arg) \ `UVM_BLOCKING_PUT_IMP(imp, TYPE, arg) \ `UVM_NONBLOCKING_PUT_IMP(imp, TYPE, arg) `define UVM_GET_IMP(imp, TYPE, arg) \ `UVM_BLOCKING_GET_IMP(imp, TYPE, arg) \ `UVM_NONBLOCKING_GET_IMP(imp, TYPE, arg) `define UVM_PEEK_IMP(imp, TYPE, arg) \ `UVM_BLOCKING_PEEK_IMP(imp, TYPE, arg) \ `UVM_NONBLOCKING_PEEK_IMP(imp, TYPE, arg) `define UVM_BLOCKING_GET_PEEK_IMP(imp, TYPE, arg) \ `UVM_BLOCKING_GET_IMP(imp, TYPE, arg) \ `UVM_BLOCKING_PEEK_IMP(imp, TYPE, arg) `define UVM_NONBLOCKING_GET_PEEK_IMP(imp, TYPE, arg) \ `UVM_NONBLOCKING_GET_IMP(imp, TYPE, arg) \ `UVM_NONBLOCKING_PEEK_IMP(imp, TYPE, arg) `define UVM_GET_PEEK_IMP(imp, TYPE, arg) \ `UVM_BLOCKING_GET_PEEK_IMP(imp, TYPE, arg) \ `UVM_NONBLOCKING_GET_PEEK_IMP(imp, TYPE, arg) `define UVM_TRANSPORT_IMP(imp, REQ, RSP, req_arg, rsp_arg) \ `UVM_BLOCKING_TRANSPORT_IMP(imp, REQ, RSP, req_arg, rsp_arg) \ `UVM_NONBLOCKING_TRANSPORT_IMP(imp, REQ, RSP, req_arg, rsp_arg) `define UVM_TLM_GET_TYPE_NAME(NAME) \ virtual function string get_type_name(); \ return NAME; \ endfunction `define UVM_PORT_COMMON(MASK,TYPE_NAME) \ function new (string name, uvm_component parent, \ int min_size=1, int max_size=1); \ super.new (name, parent, UVM_PORT, min_size, max_size); \ m_if_mask = MASK; \ endfunction \ `UVM_TLM_GET_TYPE_NAME(TYPE_NAME) `define UVM_SEQ_PORT(MASK,TYPE_NAME) \ function new (string name, uvm_component parent, \ int min_size=0, int max_size=1); \ super.new (name, parent, UVM_PORT, min_size, max_size); \ m_if_mask = MASK; \ endfunction \ `UVM_TLM_GET_TYPE_NAME(TYPE_NAME) `define UVM_EXPORT_COMMON(MASK,TYPE_NAME) \ function new (string name, uvm_component parent, \ int min_size=1, int max_size=1); \ super.new (name, parent, UVM_EXPORT, min_size, max_size); \ m_if_mask = MASK; \ endfunction \ `UVM_TLM_GET_TYPE_NAME(TYPE_NAME) `define UVM_IMP_COMMON(MASK,TYPE_NAME,IMP) \ local IMP m_imp; \ function new (string name, IMP imp); \ super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); \ m_imp = imp; \ m_if_mask = MASK; \ endfunction \ `UVM_TLM_GET_TYPE_NAME(TYPE_NAME) `define UVM_MS_IMP_COMMON(MASK,TYPE_NAME) \ local this_req_type m_req_imp; \ local this_rsp_type m_rsp_imp; \ function new (string name, this_imp_type imp, \ this_req_type req_imp = null, this_rsp_type rsp_imp = null); \ super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); \ if(req_imp==null) $cast(req_imp, imp); \ if(rsp_imp==null) $cast(rsp_imp, imp); \ m_req_imp = req_imp; \ m_rsp_imp = rsp_imp; \ m_if_mask = MASK; \ endfunction \ `UVM_TLM_GET_TYPE_NAME(TYPE_NAME) `define uvm_create(SEQ_OR_ITEM, SEQR=get_sequencer()) \ begin \ uvm_object_wrapper w_; \ w_ = SEQ_OR_ITEM.get_type(); \ $cast(SEQ_OR_ITEM , create_item(w_, SEQR, `"SEQ_OR_ITEM`"));\ end `define uvm_do(SEQ_OR_ITEM, SEQR=get_sequencer(), PRIORITY=-1, CONSTRAINTS={}) \ begin \ `uvm_create(SEQ_OR_ITEM, SEQR) \ `uvm_rand_send(SEQ_OR_ITEM, PRIORITY, CONSTRAINTS) \ end `define uvm_send(SEQ_OR_ITEM, PRIORITY=-1) \ begin \ uvm_sequence_base __seq; \ if (!$cast(__seq,SEQ_OR_ITEM)) begin \ start_item(SEQ_OR_ITEM, PRIORITY);\ finish_item(SEQ_OR_ITEM, PRIORITY);\ end \ else __seq.start(__seq.get_sequencer(), this, PRIORITY, 0);\ end `define uvm_rand_send(SEQ_OR_ITEM, PRIORITY=-1, CONSTRAINTS={}) \ begin \ uvm_sequence_base __seq; \ if ( SEQ_OR_ITEM.is_item() ) begin \ start_item(SEQ_OR_ITEM, PRIORITY);\ if ( ! SEQ_OR_ITEM.randomize() with CONSTRAINTS ) begin \ `uvm_warning("RNDFLD", "Randomization failed in uvm_rand_send action") \ end\ finish_item(SEQ_OR_ITEM, PRIORITY);\ end \ else if ( $cast( __seq, SEQ_OR_ITEM ) ) begin \ __seq.set_item_context(this,SEQ_OR_ITEM.get_sequencer()); \ if ( __seq.get_randomize_enabled() ) begin \ if ( ! SEQ_OR_ITEM.randomize() with CONSTRAINTS ) begin \ `uvm_warning("RNDFLD", "Randomization failed in uvm_rand_send action") \ end \ end \ __seq.start(__seq.get_sequencer(), this, PRIORITY, 0);\ end \ else begin \ `uvm_warning("NOT_SEQ_OR_ITEM", "Object passed uvm_rand_send appears to be neither a sequence or item." ) \ end \ end `define uvm_add_to_seq_lib(TYPE,LIBTYPE) \ static bit add_``TYPE``_to_seq_lib_``LIBTYPE =\ LIBTYPE::m_add_typewide_sequence(TYPE::get_type()); `define uvm_sequence_library_utils(TYPE) \ \ static protected uvm_object_wrapper m_typewide_sequences[$]; \ \ function void init_sequence_library(); \ foreach (TYPE::m_typewide_sequences[i]) \ sequences.push_back(TYPE::m_typewide_sequences[i]); \ endfunction \ \ static function void add_typewide_sequence(uvm_object_wrapper seq_type); \ if (m_static_check(seq_type)) \ TYPE::m_typewide_sequences.push_back(seq_type); \ endfunction \ \ static function void add_typewide_sequences(uvm_object_wrapper seq_types[$]); \ foreach (seq_types[i]) \ TYPE::add_typewide_sequence(seq_types[i]); \ endfunction \ \ static function bit m_add_typewide_sequence(uvm_object_wrapper seq_type); \ TYPE::add_typewide_sequence(seq_type); \ return 1; \ endfunction `define uvm_declare_p_sequencer(SEQUENCER) \ SEQUENCER p_sequencer;\ virtual function void m_set_p_sequencer();\ super.m_set_p_sequencer(); \ if( !$cast(p_sequencer, m_sequencer)) \ `uvm_fatal("DCLPSQ", \ $sformatf("%m %s Error casting p_sequencer, please verify that this sequence/sequence item is intended to execute on this type of sequencer", get_full_name())) \ endfunction `define UVM_CB_MACROS_SVH `define uvm_register_cb(T,CB) \ static local bit m_register_cb_``CB = uvm_callbacks#(T,CB)::m_register_pair(`"T`",`"CB`"); `define uvm_set_super_type(T,ST) \ static local bit m_register_``T``ST = uvm_derived_callbacks#(T,ST)::register_super_type(`"T`",`"ST`"); `define uvm_do_callbacks(T,CB,METHOD) \ `uvm_do_obj_callbacks(T,CB,this,METHOD) `define uvm_do_obj_callbacks(T,CB,OBJ,METHOD) \ begin \ uvm_callback_iter#(T,CB) iter = new(OBJ); \ CB cb = iter.first(); \ while(cb != null) begin \ `uvm_cb_trace_noobj(cb,$sformatf(`"Executing callback method 'METHOD' for callback %s (CB) from %s (T)`",cb.get_name(), OBJ.get_full_name())) \ cb.METHOD; \ cb = iter.next(); \ end \ end `define uvm_do_callbacks_exit_on(T,CB,METHOD,VAL) \ `uvm_do_obj_callbacks_exit_on(T,CB,this,METHOD,VAL) \ `define uvm_do_obj_callbacks_exit_on(T,CB,OBJ,METHOD,VAL) \ begin \ uvm_callback_iter#(T,CB) iter = new(OBJ); \ CB cb = iter.first(); \ while(cb != null) begin \ if (cb.METHOD == VAL) begin \ `uvm_cb_trace_noobj(cb,$sformatf(`"Executed callback method 'METHOD' for callback %s (CB) from %s (T) : returned value VAL (other callbacks will be ignored)`",cb.get_name(), OBJ.get_full_name())) \ return VAL; \ end \ `uvm_cb_trace_noobj(cb,$sformatf(`"Executed callback method 'METHOD' for callback %s (CB) from %s (T) : did not return value VAL`",cb.get_name(), OBJ.get_full_name())) \ cb = iter.next(); \ end \ return 1-VAL; \ end `define uvm_cb_trace_noobj(CB,OPER) /* null */ `define uvm_cb_trace(OBJ,CB,OPER) /* null */ `define UVM_REG_ADDR_WIDTH 64 `define UVM_REG_DATA_WIDTH 64 `define UVM_REG_BYTENABLE_WIDTH ((`UVM_REG_DATA_WIDTH-1)/8+1) `define UVM_REG_CVR_WIDTH 32 package uvm_pkg; `define UVM_DPI_SVH `define UVM_HDL_NO_DPI `define UVM_REGEX_NO_DPI `define UVM_CMDLINE_NO_DPI `define UVM_HDL__SVH `define UVM_HDL_MAX_WIDTH 1024 parameter int UVM_HDL_MAX_WIDTH = 1024; typedef logic [UVM_HDL_MAX_WIDTH-1:0] uvm_hdl_data_t; function int uvm_hdl_check_path(string path); uvm_report_fatal("UVM_HDL_CHECK_PATH", $sformatf("uvm_hdl DPI routines are compiled off. Recompile without +define+UVM_HDL_NO_DPI")); return 0; endfunction function int uvm_hdl_deposit(string path, uvm_hdl_data_t value); uvm_report_fatal("UVM_HDL_DEPOSIT", $sformatf("uvm_hdl DPI routines are compiled off. Recompile without +define+UVM_HDL_NO_DPI")); return 0; endfunction function int uvm_hdl_force(string path, uvm_hdl_data_t value); uvm_report_fatal("UVM_HDL_FORCE", $sformatf("uvm_hdl DPI routines are compiled off. Recompile without +define+UVM_HDL_NO_DPI")); return 0; endfunction task uvm_hdl_force_time(string path, uvm_hdl_data_t value, time force_time=0); uvm_report_fatal("UVM_HDL_FORCE_TIME", $sformatf("uvm_hdl DPI routines are compiled off. Recompile without +define+UVM_HDL_NO_DPI")); endtask function int uvm_hdl_release(string path, output uvm_hdl_data_t value); uvm_report_fatal("UVM_HDL_RELEASE", $sformatf("uvm_hdl DPI routines are compiled off. Recompile without +define+UVM_HDL_NO_DPI")); return 0; endfunction function int uvm_hdl_read(string path, output uvm_hdl_data_t value); uvm_report_fatal("UVM_HDL_READ", $sformatf("uvm_hdl DPI routines are compiled off. Recompile without +define+UVM_HDL_NO_DPI")); return 0; endfunction function string uvm_dpi_get_next_arg(int init=0); return ""; endfunction function string uvm_dpi_get_tool_name(); return "?"; endfunction function string uvm_dpi_get_tool_version(); return "?"; endfunction function chandle uvm_dpi_regcomp(string regex); return null; endfunction function int uvm_dpi_regexec(chandle preg, string str); return 0; endfunction function void uvm_dpi_regfree(chandle preg); endfunction function int uvm_re_match(string re, string str); int e, es, s, ss; string tmp; e = 0; s = 0; es = 0; ss = 0; if(re.len() == 0) return 0; if(re[0] == "^") re = re.substr(1, re.len()-1); while (s != str.len() && re.getc(e) != "*") begin if ((re.getc(e) != str.getc(s)) && (re.getc(e) != "?")) return 1; e++; s++; end while (s != str.len()) begin if (re.getc(e) == "*") begin e++; if (e == re.len()) begin return 0; end es = e; ss = s+1; end else if (re.getc(e) == str.getc(s) || re.getc(e) == "?") begin e++; s++; end else begin e = es; s = ss++; end end while (e < re.len() && re.getc(e) == "*") e++; if(e == re.len()) begin return 0; end else begin return 1; end endfunction function string uvm_glob_to_re(string glob); return glob; endfunction `define UVM_BASE_SVH typedef class uvm_cmdline_processor; `define UVM_VERSION_SVH parameter string UVM_VERSION_STRING = "Accellera:1800.2-2017:UVM:1.0"; function string uvm_revision_string(); return UVM_VERSION_STRING; endfunction parameter UVM_STREAMBITS = 4096; typedef logic signed [UVM_STREAMBITS-1:0] uvm_bitstream_t; typedef logic signed [63:0] uvm_integral_t; parameter UVM_FIELD_FLAG_RESERVED_BITS = 28; typedef bit [UVM_FIELD_FLAG_RESERVED_BITS-1 : 0] uvm_field_flag_t; typedef enum uvm_field_flag_t { UVM_BIN = 'h1000000, UVM_DEC = 'h2000000, UVM_UNSIGNED = 'h3000000, UVM_UNFORMAT2 = 'h4000000, UVM_UNFORMAT4 = 'h5000000, UVM_OCT = 'h6000000, UVM_HEX = 'h7000000, UVM_STRING = 'h8000000, UVM_TIME = 'h9000000, UVM_ENUM = 'ha000000, UVM_REAL = 'hb000000, UVM_REAL_DEC = 'hc000000, UVM_REAL_EXP = 'hd000000, UVM_NORADIX = 0 } uvm_radix_enum; parameter UVM_RADIX = 'hf000000; function string uvm_radix_to_string(uvm_radix_enum radix); case(radix) UVM_BIN: return "b"; UVM_OCT: return "o"; UVM_DEC: return "d"; UVM_HEX: return "h"; UVM_UNSIGNED: return "u"; UVM_UNFORMAT2: return "u"; UVM_UNFORMAT4: return "z"; UVM_STRING: return "s"; UVM_TIME: return "t"; UVM_ENUM: return "s"; UVM_REAL: return "g"; UVM_REAL_DEC: return "f"; UVM_REAL_EXP: return "e"; default: return "x"; endcase endfunction typedef enum uvm_field_flag_t { UVM_DEFAULT_POLICY = 0, UVM_DEEP = (1<<16), UVM_SHALLOW = (1<<17), UVM_REFERENCE = (1<<18) } uvm_recursion_policy_enum; parameter UVM_RECURSION = (UVM_DEEP|UVM_SHALLOW|UVM_REFERENCE); typedef enum bit { UVM_PASSIVE=0, UVM_ACTIVE=1 } uvm_active_passive_enum; parameter uvm_field_flag_t UVM_MACRO_NUMFLAGS = 19; parameter uvm_field_flag_t UVM_DEFAULT = 'b000010101010101; parameter uvm_field_flag_t UVM_ALL_ON = 'b000000101010101; parameter uvm_field_flag_t UVM_FLAGS_ON = 'b000000101010101; parameter uvm_field_flag_t UVM_FLAGS_OFF = 0; parameter uvm_field_flag_t UVM_COPY = (1<<0); parameter uvm_field_flag_t UVM_NOCOPY = (1<<1); parameter uvm_field_flag_t UVM_COMPARE = (1<<2); parameter uvm_field_flag_t UVM_NOCOMPARE = (1<<3); parameter uvm_field_flag_t UVM_PRINT = (1<<4); parameter uvm_field_flag_t UVM_NOPRINT = (1<<5); parameter uvm_field_flag_t UVM_RECORD = (1<<6); parameter uvm_field_flag_t UVM_NORECORD = (1<<7); parameter uvm_field_flag_t UVM_PACK = (1<<8); parameter uvm_field_flag_t UVM_NOPACK = (1<<9); parameter uvm_field_flag_t UVM_UNPACK = (1<<10); parameter uvm_field_flag_t UVM_NOUNPACK = UVM_NOPACK; parameter uvm_field_flag_t UVM_SET = (1<<11); parameter uvm_field_flag_t UVM_NOSET = (1<<12); parameter uvm_field_flag_t UVM_NODEFPRINT = (1<<15); parameter uvm_field_flag_t UVM_MACRO_EXTRAS = (1<"; uvm_object_value_str.itoa(v.get_inst_id()); uvm_object_value_str = {"@",uvm_object_value_str}; endfunction function string uvm_leaf_scope (string full_name, byte scope_separator = "."); byte bracket_match; int pos; int bmatches; bmatches = 0; case(scope_separator) "[": bracket_match = "]"; "(": bracket_match = ")"; "<": bracket_match = ">"; "{": bracket_match = "}"; default: bracket_match = ""; endcase if(bracket_match != "" && bracket_match != full_name[full_name.len()-1]) bracket_match = ""; for(pos=full_name.len()-1; pos>0; --pos) begin if(full_name[pos] == bracket_match) bmatches++; else if(full_name[pos] == scope_separator) begin bmatches--; if(!bmatches || (bracket_match == "")) break; end end if(pos) begin if(scope_separator != ".") pos--; uvm_leaf_scope = full_name.substr(pos+1,full_name.len()-1); end else begin uvm_leaf_scope = full_name; end endfunction function string uvm_bitstream_to_string (uvm_bitstream_t value, int size, uvm_radix_enum radix=UVM_NORADIX, string radix_str=""); if (radix == UVM_DEC && value[size-1] === 1) return $sformatf("%0d", value); if($isunknown(value)) begin uvm_bitstream_t _t; _t=0; for(int idx=0;idx 0 && (arg[i] != "[")) begin --i; if((arg[i] == "*") || (arg[i] == "?")) i=0; else if((arg[i] < "0") || (arg[i] > "9") && (arg[i] != "[")) begin uvm_get_array_index_int = -1; i=0; end end else begin is_wildcard = 0; return 0; end if(i>0) begin arg = arg.substr(i+1, arg.len()-2); uvm_get_array_index_int = arg.atoi(); is_wildcard = 0; end endfunction function string uvm_get_array_index_string(string arg, output bit is_wildcard); int i; uvm_get_array_index_string = ""; is_wildcard = 1; i = arg.len() - 1; if(arg[i] == "]") while(i > 0 && (arg[i] != "[")) begin if((arg[i] == "*") || (arg[i] == "?")) i=0; --i; end if(i>0) begin uvm_get_array_index_string = arg.substr(i+1, arg.len()-2); is_wildcard = 0; end endfunction function bit uvm_is_array(string arg); return arg[arg.len()-1] == "]"; endfunction function automatic bit uvm_has_wildcard (string arg); uvm_has_wildcard = 0; if( (arg.len() > 1) && (arg[0] == "/") && (arg[arg.len()-1] == "/") ) return 1; foreach(arg[i]) if( (arg[i] == "*") || (arg[i] == "+") || (arg[i] == "?") ) uvm_has_wildcard = 1; endfunction typedef class uvm_component; typedef class uvm_root; typedef class uvm_report_object; function automatic string m_uvm_string_queue_join(ref string i[$]); m_uvm_string_queue_join = {>>{i}}; endfunction typedef class uvm_factory; typedef class uvm_default_factory; typedef class uvm_report_server; typedef class uvm_default_report_server; typedef class uvm_root; typedef class uvm_visitor; typedef class uvm_component_name_check_visitor; typedef class uvm_component; typedef class uvm_comparer; typedef class uvm_copier; typedef class uvm_packer; typedef class uvm_printer; typedef class uvm_table_printer; typedef class uvm_tr_database; typedef class uvm_text_tr_database; typedef class uvm_resource_pool; typedef class uvm_default_coreservice_t; virtual class uvm_coreservice_t; pure virtual function uvm_factory get_factory(); pure virtual function void set_factory(uvm_factory f); pure virtual function uvm_report_server get_report_server(); pure virtual function void set_report_server(uvm_report_server server); pure virtual function uvm_tr_database get_default_tr_database(); pure virtual function void set_default_tr_database(uvm_tr_database db); pure virtual function void set_component_visitor(uvm_visitor#(uvm_component) v); pure virtual function uvm_visitor#(uvm_component) get_component_visitor(); pure virtual function uvm_root get_root(); pure virtual function void set_phase_max_ready_to_end(int max); pure virtual function int get_phase_max_ready_to_end(); pure virtual function void set_default_printer(uvm_printer printer); pure virtual function uvm_printer get_default_printer(); pure virtual function void set_default_packer(uvm_packer packer); pure virtual function uvm_packer get_default_packer(); pure virtual function void set_default_comparer(uvm_comparer comparer); pure virtual function uvm_comparer get_default_comparer(); pure virtual function int unsigned get_global_seed(); pure virtual function void set_default_copier(uvm_copier copier); pure virtual function uvm_copier get_default_copier(); pure virtual function bit get_uvm_seeding(); pure virtual function void set_uvm_seeding(bit enable); pure virtual function void set_resource_pool (uvm_resource_pool pool); pure virtual function uvm_resource_pool get_resource_pool(); pure virtual function void set_resource_pool_default_precedence(int unsigned precedence); pure virtual function int unsigned get_resource_pool_default_precedence(); local static uvm_coreservice_t inst; static function uvm_coreservice_t get(); if(inst==null) uvm_init(null); return inst; endfunction static function void set(uvm_coreservice_t cs); inst=cs; endfunction endclass class uvm_default_coreservice_t extends uvm_coreservice_t; local uvm_factory factory; virtual function uvm_factory get_factory(); if(factory==null) begin uvm_default_factory f; f=new; factory=f; end return factory; endfunction virtual function void set_factory(uvm_factory f); factory = f; endfunction local uvm_tr_database tr_database; virtual function uvm_tr_database get_default_tr_database(); if (tr_database == null) begin process p = process::self(); uvm_text_tr_database tx_db; string s; if(p != null) s = p.get_randstate(); tx_db = new("default_tr_database"); tr_database = tx_db; if(p != null) p.set_randstate(s); end return tr_database; endfunction : get_default_tr_database virtual function void set_default_tr_database(uvm_tr_database db); tr_database = db; endfunction : set_default_tr_database local uvm_report_server report_server; virtual function uvm_report_server get_report_server(); if(report_server==null) begin uvm_default_report_server f; f=new; report_server=f; end return report_server; endfunction virtual function void set_report_server(uvm_report_server server); report_server=server; endfunction virtual function uvm_root get_root(); return uvm_root::m_uvm_get_root(); endfunction local uvm_visitor#(uvm_component) _visitor; virtual function void set_component_visitor(uvm_visitor#(uvm_component) v); _visitor=v; endfunction virtual function uvm_visitor#(uvm_component) get_component_visitor(); if(_visitor==null) begin uvm_component_name_check_visitor v = new("name-check-visitor"); _visitor=v; end return _visitor; endfunction local uvm_printer m_printer ; virtual function void set_default_printer(uvm_printer printer); m_printer = printer ; endfunction virtual function uvm_printer get_default_printer(); if (m_printer == null) begin m_printer = uvm_table_printer::get_default() ; end return m_printer ; endfunction local uvm_packer m_packer ; virtual function void set_default_packer(uvm_packer packer); m_packer = packer ; endfunction virtual function uvm_packer get_default_packer(); if (m_packer == null) begin m_packer = new("uvm_default_packer") ; end return m_packer ; endfunction local uvm_comparer m_comparer ; virtual function void set_default_comparer(uvm_comparer comparer); m_comparer = comparer ; endfunction virtual function uvm_comparer get_default_comparer(); if (m_comparer == null) begin m_comparer = new("uvm_default_comparer") ; end return m_comparer ; endfunction local int m_default_max_ready_to_end_iters = 20; virtual function void set_phase_max_ready_to_end(int max); m_default_max_ready_to_end_iters = max; endfunction virtual function int get_phase_max_ready_to_end(); return m_default_max_ready_to_end_iters; endfunction local uvm_resource_pool m_rp ; virtual function void set_resource_pool (uvm_resource_pool pool); m_rp = pool; endfunction virtual function uvm_resource_pool get_resource_pool(); if(m_rp == null) m_rp = new(); return m_rp; endfunction local int unsigned m_default_precedence = 1000; virtual function void set_resource_pool_default_precedence(int unsigned precedence); m_default_precedence = precedence; endfunction virtual function int unsigned get_resource_pool_default_precedence(); return m_default_precedence; endfunction local int unsigned m_uvm_global_seed = $urandom; virtual function int unsigned get_global_seed(); return m_uvm_global_seed; endfunction local bit m_use_uvm_seeding = 1; virtual function bit get_uvm_seeding(); return m_use_uvm_seeding; endfunction : get_uvm_seeding virtual function void set_uvm_seeding(bit enable); m_use_uvm_seeding = enable; endfunction : set_uvm_seeding local uvm_copier m_copier ; virtual function void set_default_copier(uvm_copier copier); m_copier = copier ; endfunction virtual function uvm_copier get_default_copier(); if (m_copier == null) begin m_copier = new("uvm_default_copier") ; end return m_copier ; endfunction endclass typedef class uvm_root; typedef class uvm_report_object; typedef class uvm_report_message; task run_test (string test_name=""); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); top.run_test(test_name); endtask function uvm_report_object uvm_get_report_object(); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); return top; endfunction function int uvm_report_enabled (int verbosity, uvm_severity severity=UVM_INFO, string id=""); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); return top.uvm_report_enabled(verbosity,severity,id); endfunction function void uvm_report( uvm_severity severity, string id, string message, int verbosity = (severity == uvm_severity'(UVM_ERROR)) ? UVM_LOW : (severity == uvm_severity'(UVM_FATAL)) ? UVM_NONE : UVM_MEDIUM, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); top.uvm_report(severity, id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction export "DPI-C" function m__uvm_report_dpi; function void m__uvm_report_dpi(int severity, string id, string message, int verbosity, string filename, int line); uvm_report(uvm_severity'(severity), id, message, verbosity, filename, line); endfunction : m__uvm_report_dpi function void uvm_report_info(string id, string message, int verbosity = UVM_MEDIUM, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); top.uvm_report_info(id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction function void uvm_report_warning(string id, string message, int verbosity = UVM_MEDIUM, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); top.uvm_report_warning(id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction function void uvm_report_error(string id, string message, int verbosity = UVM_NONE, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); top.uvm_report_error(id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction function void uvm_report_fatal(string id, string message, int verbosity = UVM_NONE, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); top.uvm_report_fatal(id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction function void uvm_process_report_message(uvm_report_message report_message); uvm_root top; uvm_coreservice_t cs; process p; p = process::self(); cs = uvm_coreservice_t::get(); top = cs.get_root(); top.uvm_process_report_message(report_message); endfunction function bit uvm_string_to_severity (string sev_str, output uvm_severity sev); case (sev_str) "UVM_INFO": sev = UVM_INFO; "UVM_WARNING": sev = UVM_WARNING; "UVM_ERROR": sev = UVM_ERROR; "UVM_FATAL": sev = UVM_FATAL; default: return 0; endcase return 1; endfunction function automatic bit uvm_string_to_action (string action_str, output uvm_action action); string actions[$]; uvm_split_string(action_str,"|",actions); uvm_string_to_action = 1; action = 0; foreach(actions[i]) begin case (actions[i]) "UVM_NO_ACTION": action |= UVM_NO_ACTION; "UVM_DISPLAY": action |= UVM_DISPLAY; "UVM_LOG": action |= UVM_LOG; "UVM_COUNT": action |= UVM_COUNT; "UVM_EXIT": action |= UVM_EXIT; "UVM_CALL_HOOK": action |= UVM_CALL_HOOK; "UVM_STOP": action |= UVM_STOP; "UVM_RM_RECORD": action |= UVM_RM_RECORD; default: uvm_string_to_action = 0; endcase end endfunction function bit uvm_is_match (string expr, string str); string s; s = uvm_glob_to_re(expr); return (uvm_re_match(s, str) == 0); endfunction parameter UVM_LINE_WIDTH = 120; parameter UVM_NUM_LINES = 120; parameter UVM_SMALL_STRING = UVM_LINE_WIDTH*8-1; parameter UVM_LARGE_STRING = UVM_LINE_WIDTH*UVM_NUM_LINES*8-1; function logic[UVM_LARGE_STRING:0] uvm_string_to_bits(string str); $swrite(uvm_string_to_bits, "%0s", str); endfunction function uvm_core_state get_core_state(); return m_uvm_core_state; endfunction function void uvm_init(uvm_coreservice_t cs=null); uvm_default_coreservice_t dcs; if(get_core_state()!=UVM_CORE_UNINITIALIZED) begin if (get_core_state() == UVM_CORE_PRE_INIT) begin dcs = new(); uvm_coreservice_t::set(dcs); begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"UVM/INIT/MULTI")) uvm_report_fatal ("UVM/INIT/MULTI", "Non-recoverable race during uvm_init", UVM_NONE, "t/uvm/src/base/uvm_globals.svh", 335, "", 1); end end else begin uvm_coreservice_t actual; actual = uvm_coreservice_t::get(); if ((cs != actual) && (cs != null)) begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/INIT/MULTI")) uvm_report_warning ("UVM/INIT/MULTI", "uvm_init() called after library has already completed initialization, subsequent calls are ignored!", UVM_NONE, "t/uvm/src/base/uvm_globals.svh", 344, "", 1); end end return; end m_uvm_core_state=UVM_CORE_PRE_INIT; if(cs == null) begin dcs = new(); cs = dcs; end uvm_coreservice_t::set(cs); m_uvm_core_state=UVM_CORE_INITIALIZING; foreach(uvm_deferred_init[idx]) begin uvm_deferred_init[idx].initialize(); end uvm_deferred_init.delete(); begin uvm_root top; top = uvm_root::get(); top.report_header(); top.m_check_uvm_field_flag_size(); top.m_check_verbosity(); end m_uvm_core_state=UVM_CORE_INITIALIZED; endfunction function string uvm_bits_to_string(logic [UVM_LARGE_STRING:0] str); $swrite(uvm_bits_to_string, "%0s", str); endfunction task uvm_wait_for_nba_region; int nba; int next_nba; next_nba++; nba <= next_nba; @(nba); endtask function automatic void uvm_split_string (string str, byte sep, ref string values[$]); int s = 0, e = 0; values.delete(); while(e < str.len()) begin for(s=e; e"; endfunction virtual function uvm_object create (string name=""); return null; endfunction extern virtual function uvm_object clone (); extern function void print (uvm_printer printer=null); extern function string sprint (uvm_printer printer=null); extern virtual function void do_print (uvm_printer printer); extern virtual function string convert2string(); extern function void record (uvm_recorder recorder=null); extern virtual function void do_record (uvm_recorder recorder); extern function void copy (uvm_object rhs, uvm_copier copier=null); extern virtual function void do_copy (uvm_object rhs); extern function bit compare (uvm_object rhs, uvm_comparer comparer=null); extern virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); extern function int pack (ref bit bitstream[], input uvm_packer packer=null); extern function int pack_bytes (ref byte unsigned bytestream[], input uvm_packer packer=null); extern function int pack_ints (ref int unsigned intstream[], input uvm_packer packer=null); extern function int pack_longints (ref longint unsigned longintstream[], input uvm_packer packer=null); extern virtual function void do_pack (uvm_packer packer); extern function int unpack (ref bit bitstream[], input uvm_packer packer=null); extern function int unpack_bytes (ref byte unsigned bytestream[], input uvm_packer packer=null); extern function int unpack_ints (ref int unsigned intstream[], input uvm_packer packer=null); extern function int unpack_longints (ref longint unsigned longintstream[], input uvm_packer packer=null); extern virtual function void do_unpack (uvm_packer packer); extern virtual function void do_execute_op ( uvm_field_op op); extern virtual function void set_local(uvm_resource_base rsrc) ; extern local function void m_pack (inout uvm_packer packer); extern local function void m_unpack_pre (inout uvm_packer packer); extern local function int m_unpack_post (uvm_packer packer); extern virtual function void m_unsupported_set_local(uvm_resource_base rsrc); local string m_leaf_name; local int m_inst_id; static protected int m_inst_count; extern virtual function void __m_uvm_field_automation (uvm_object tmp_data__, uvm_field_flag_t what__, string str__); extern protected virtual function uvm_report_object m_get_report_object(); endclass function uvm_object::new (string name=""); m_inst_id = m_inst_count++; m_leaf_name = name; endfunction function bit uvm_object::get_uvm_seeding(); uvm_coreservice_t cs = uvm_coreservice_t::get(); return cs.get_uvm_seeding(); endfunction function void uvm_object::set_uvm_seeding(bit enable); uvm_coreservice_t cs = uvm_coreservice_t::get(); cs.set_uvm_seeding(enable); endfunction function void uvm_object::reseed (); if(get_uvm_seeding()) this.srandom(uvm_create_random_seed(get_type_name(), get_full_name())); endfunction function uvm_object_wrapper uvm_object::get_type(); uvm_report_error("NOTYPID", "get_type not implemented in derived class.", UVM_NONE); return null; endfunction function int uvm_object::get_inst_id(); return m_inst_id; endfunction function uvm_object_wrapper uvm_object::get_object_type(); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); if(get_type_name() == "") return null; return factory.find_wrapper_by_name(get_type_name()); endfunction function int uvm_object::get_inst_count(); return m_inst_count; endfunction function string uvm_object::get_name (); return m_leaf_name; endfunction function string uvm_object::get_full_name (); return get_name(); endfunction function void uvm_object::set_name (string name); m_leaf_name = name; endfunction function void uvm_object::print(uvm_printer printer=null); if (printer==null) printer = uvm_printer::get_default(); $fwrite(printer.get_file(),sprint(printer)); endfunction function string uvm_object::sprint(uvm_printer printer=null); string name; if(printer==null) printer = uvm_printer::get_default(); if (printer.get_active_object_depth() == 0) begin printer.flush() ; name = printer.get_root_enabled() ? get_full_name() : get_name(); end else begin name = get_name(); end printer.print_object(name,this); return printer.emit(); endfunction function string uvm_object::convert2string(); return ""; endfunction function void uvm_object::set_local(uvm_resource_base rsrc) ; if(rsrc==null) begin return ; end else begin begin uvm_field_op op; op = uvm_field_op::m_get_available_op(); op.set(UVM_SET,null,rsrc); this.do_execute_op(op); op.m_recycle(); end end endfunction function void uvm_object::m_unsupported_set_local(uvm_resource_base rsrc); return; endfunction function uvm_object uvm_object::clone(); uvm_object tmp; tmp = this.create(get_name()); if(tmp == null) uvm_report_warning("CRFLD", $sformatf("The create method failed for %s, object cannot be cloned", get_name()), UVM_NONE); else tmp.copy(this); return(tmp); endfunction function void uvm_object::copy (uvm_object rhs, uvm_copier copier=null); uvm_coreservice_t coreservice ; uvm_copier m_copier; if(rhs == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"OBJ/COPY")) uvm_report_error ("OBJ/COPY", "Passing a null object to be copied", UVM_NONE, "t/uvm/src/base/uvm_object.svh", 1138, "", 1); end return; end if(copier == null) begin coreservice = uvm_coreservice_t::get() ; m_copier = coreservice.get_default_copier() ; end else m_copier = copier; if(m_copier.get_active_object_depth() == 0) m_copier.flush(); m_copier.copy_object(this,rhs); endfunction function void uvm_object::do_copy (uvm_object rhs); return; endfunction function bit uvm_object::compare (uvm_object rhs, uvm_comparer comparer=null); if (comparer == null) comparer = uvm_comparer::get_default(); if (comparer.get_active_object_depth() == 0) comparer.flush() ; compare = comparer.compare_object(get_name(),this,rhs); endfunction function bit uvm_object::do_compare (uvm_object rhs, uvm_comparer comparer); return 1; endfunction function void uvm_object::__m_uvm_field_automation (uvm_object tmp_data__, uvm_field_flag_t what__, string str__ ); return; endfunction function void uvm_object::do_print(uvm_printer printer); return; endfunction function void uvm_object::m_pack (inout uvm_packer packer); if (packer == null) packer = uvm_packer::get_default(); if(packer.get_active_object_depth() == 0) packer.flush(); packer.pack_object(this); endfunction function int uvm_object::pack (ref bit bitstream [], input uvm_packer packer =null ); m_pack(packer); packer.get_packed_bits(bitstream); return packer.get_packed_size(); endfunction function int uvm_object::pack_bytes (ref byte unsigned bytestream [], input uvm_packer packer=null ); m_pack(packer); packer.get_packed_bytes(bytestream); return packer.get_packed_size(); endfunction function int uvm_object::pack_ints (ref int unsigned intstream [], input uvm_packer packer=null ); m_pack(packer); packer.get_packed_ints(intstream); return packer.get_packed_size(); endfunction function int uvm_object::pack_longints (ref longint unsigned longintstream [], input uvm_packer packer=null ); m_pack(packer); packer.get_packed_longints(longintstream); return packer.get_packed_size(); endfunction function void uvm_object::do_pack (uvm_packer packer ); if (packer == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/OBJ/PACK/NULL")) uvm_report_error ("UVM/OBJ/PACK/NULL", "uvm_object::do_pack called with null packer!", UVM_NONE, "t/uvm/src/base/uvm_object.svh", 1265, "", 1); end return; endfunction function void uvm_object::m_unpack_pre (inout uvm_packer packer); if (packer == null) packer = uvm_packer::get_default(); if(packer.get_active_object_depth() == 0) packer.flush(); endfunction function int uvm_object::m_unpack_post (uvm_packer packer); int size_before_unpack = packer.get_packed_size(); packer.unpack_object(this); return size_before_unpack - packer.get_packed_size(); endfunction function int uvm_object::unpack (ref bit bitstream [], input uvm_packer packer=null); m_unpack_pre(packer); packer.set_packed_bits(bitstream); return m_unpack_post(packer); endfunction function int uvm_object::unpack_bytes (ref byte unsigned bytestream [], input uvm_packer packer=null); m_unpack_pre(packer); packer.set_packed_bytes(bytestream); return m_unpack_post(packer); endfunction function int uvm_object::unpack_ints (ref int unsigned intstream [], input uvm_packer packer=null); m_unpack_pre(packer); packer.set_packed_ints(intstream); return m_unpack_post(packer); endfunction function int uvm_object::unpack_longints (ref longint unsigned longintstream [], input uvm_packer packer=null); m_unpack_pre(packer); packer.set_packed_longints(longintstream); return m_unpack_post(packer); endfunction function void uvm_object::do_execute_op ( uvm_field_op op); endfunction function void uvm_object::do_unpack (uvm_packer packer); if (packer == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/OBJ/UNPACK/NULL")) uvm_report_error ("UVM/OBJ/UNPACK/NULL", "uvm_object::do_unpack called with null packer!", UVM_NONE, "t/uvm/src/base/uvm_object.svh", 1345, "", 1); end return; endfunction function void uvm_object::record (uvm_recorder recorder=null); if(recorder == null) return; recorder.record_object(get_name(), this); endfunction function void uvm_object::do_record (uvm_recorder recorder); return; endfunction function uvm_report_object uvm_object::m_get_report_object(); return null; endfunction typedef class uvm_object; typedef class uvm_component; typedef class uvm_object_wrapper; typedef class uvm_factory_override; typedef struct {uvm_object_wrapper m_type; string m_type_name;} m_uvm_factory_type_pair_t; class uvm_factory_queue_class; uvm_factory_override queue[$]; endclass virtual class uvm_factory; static function uvm_factory get(); uvm_coreservice_t s; s = uvm_coreservice_t::get(); return s.get_factory(); endfunction static function void set(uvm_factory f); uvm_coreservice_t s; s = uvm_coreservice_t::get(); s.set_factory(f); endfunction pure virtual function void register (uvm_object_wrapper obj); pure virtual function void set_inst_override_by_type (uvm_object_wrapper original_type, uvm_object_wrapper override_type, string full_inst_path); pure virtual function void set_inst_override_by_name (string original_type_name, string override_type_name, string full_inst_path); pure virtual function void set_type_override_by_type (uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace=1); pure virtual function void set_type_override_by_name (string original_type_name, string override_type_name, bit replace=1); pure virtual function uvm_object create_object_by_type (uvm_object_wrapper requested_type, string parent_inst_path="", string name=""); pure virtual function uvm_component create_component_by_type (uvm_object_wrapper requested_type, string parent_inst_path="", string name, uvm_component parent); pure virtual function uvm_object create_object_by_name (string requested_type_name, string parent_inst_path="", string name=""); pure virtual function bit is_type_name_registered (string type_name); pure virtual function bit is_type_registered (uvm_object_wrapper obj); pure virtual function uvm_component create_component_by_name (string requested_type_name, string parent_inst_path="", string name, uvm_component parent); pure virtual function void set_type_alias(string alias_type_name, uvm_object_wrapper original_type); pure virtual function void set_inst_alias(string alias_type_name, uvm_object_wrapper original_type, string full_inst_path); pure virtual function void debug_create_by_type (uvm_object_wrapper requested_type, string parent_inst_path="", string name=""); pure virtual function void debug_create_by_name (string requested_type_name, string parent_inst_path="", string name=""); pure virtual function uvm_object_wrapper find_override_by_type (uvm_object_wrapper requested_type, string full_inst_path); pure virtual function uvm_object_wrapper find_override_by_name (string requested_type_name, string full_inst_path); pure virtual function uvm_object_wrapper find_wrapper_by_name (string type_name); pure virtual function void print (int all_types=1); endclass class uvm_default_factory extends uvm_factory; extern virtual function void register (uvm_object_wrapper obj); extern virtual function void set_inst_override_by_type (uvm_object_wrapper original_type, uvm_object_wrapper override_type, string full_inst_path); extern virtual function void set_inst_override_by_name (string original_type_name, string override_type_name, string full_inst_path); extern virtual function void set_type_override_by_type (uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace=1); extern virtual function void set_type_override_by_name (string original_type_name, string override_type_name, bit replace=1); extern virtual function void set_type_alias(string alias_type_name, uvm_object_wrapper original_type); extern virtual function void set_inst_alias(string alias_type_name, uvm_object_wrapper original_type, string full_inst_path); extern virtual function uvm_object create_object_by_type (uvm_object_wrapper requested_type, string parent_inst_path="", string name=""); extern virtual function uvm_component create_component_by_type (uvm_object_wrapper requested_type, string parent_inst_path="", string name, uvm_component parent); extern virtual function uvm_object create_object_by_name (string requested_type_name, string parent_inst_path="", string name=""); extern virtual function uvm_component create_component_by_name (string requested_type_name, string parent_inst_path="", string name, uvm_component parent); extern virtual function bit is_type_name_registered (string type_name); extern virtual function bit is_type_registered (uvm_object_wrapper obj); extern virtual function void debug_create_by_type (uvm_object_wrapper requested_type, string parent_inst_path="", string name=""); extern virtual function void debug_create_by_name (string requested_type_name, string parent_inst_path="", string name=""); extern virtual function uvm_object_wrapper find_override_by_type (uvm_object_wrapper requested_type, string full_inst_path); extern virtual function uvm_object_wrapper find_override_by_name (string requested_type_name, string full_inst_path); extern virtual function uvm_object_wrapper find_wrapper_by_name (string type_name); extern virtual function void print (int all_types=1); extern protected function void m_debug_create (string requested_type_name, uvm_object_wrapper requested_type, string parent_inst_path, string name); extern protected function void m_debug_display(string requested_type_name, uvm_object_wrapper result, string full_inst_path); extern function uvm_object_wrapper m_resolve_type_name(string requested_type_name); extern function uvm_object_wrapper m_resolve_type_name_by_inst(string requested_type_name, string full_inst_path); extern function bit m_matches_type_pair(m_uvm_factory_type_pair_t match_type_pair, uvm_object_wrapper requested_type, string requested_type_name); extern function bit m_matches_type_override(uvm_factory_override override, uvm_object_wrapper requested_type, string requested_type_name, string full_inst_path="", bit match_original_type = 1, bit resolve_null_type_by_inst=0); extern function bit m_matches_inst_override(uvm_factory_override override, uvm_object_wrapper requested_type, string requested_type_name, string full_inst_path=""); typedef struct { m_uvm_factory_type_pair_t orig; string alias_type_name; string full_inst_path; } m_inst_typename_alias_t; protected bit m_types[uvm_object_wrapper]; protected bit m_lookup_strs[string]; protected uvm_object_wrapper m_type_names[string]; protected m_inst_typename_alias_t m_inst_aliases[$]; protected uvm_factory_override m_type_overrides[$]; protected uvm_factory_override m_inst_overrides[$]; local uvm_factory_override m_override_info[$]; local static bit m_debug_pass; extern function bit check_inst_override_exists (uvm_object_wrapper original_type, string original_type_name, uvm_object_wrapper override_type, string override_type_name, string full_inst_path); endclass virtual class uvm_object_wrapper; virtual function uvm_object create_object (string name=""); return null; endfunction virtual function uvm_component create_component (string name, uvm_component parent); return null; endfunction pure virtual function string get_type_name(); virtual function void initialize(); endfunction endclass class uvm_factory_override; string full_inst_path; m_uvm_factory_type_pair_t orig; m_uvm_factory_type_pair_t ovrd; bit replace; bit selected; int unsigned used; bit has_wildcard; function new (string full_inst_path="", string orig_type_name="", uvm_object_wrapper orig_type=null, uvm_object_wrapper ovrd_type, string ovrd_type_name="", bit replace=0); this.full_inst_path= full_inst_path; this.orig.m_type_name = orig_type_name; this.orig.m_type = orig_type; this.ovrd.m_type_name = ovrd_type_name; this.ovrd.m_type = ovrd_type; this.replace = replace; this.has_wildcard = m_has_wildcard(full_inst_path); endfunction function bit m_has_wildcard(string nm); foreach (nm[i]) if(nm[i] == "*" || nm[i] == "?") return 1; return 0; endfunction endclass function void uvm_default_factory::register (uvm_object_wrapper obj); if (obj == null) begin uvm_report_fatal ("NULLWR", "Attempting to register a null object with the factory", UVM_NONE); end if (obj.get_type_name() != "" && obj.get_type_name() != "") begin if (m_type_names.exists(obj.get_type_name())) uvm_report_warning("TPRGED", {"Type name '",obj.get_type_name(), "' already registered with factory. No string-based lookup ", "support for multiple types with the same type name."}, UVM_NONE); else m_type_names[obj.get_type_name()] = obj; end if (m_types.exists(obj)) begin if (obj.get_type_name() != "" && obj.get_type_name() != "") uvm_report_warning("TPRGED", {"Object type '",obj.get_type_name(), "' already registered with factory. "}, UVM_NONE); end else begin uvm_factory_override overrides[$]; m_types[obj] = 1; overrides = {m_type_overrides, m_inst_overrides}; foreach (overrides[index]) begin if(m_matches_type_pair(.match_type_pair(overrides[index].orig), .requested_type(null), .requested_type_name(obj.get_type_name()))) begin overrides[index].orig.m_type = obj; end if(m_matches_type_pair(.match_type_pair(overrides[index].ovrd), .requested_type(null), .requested_type_name(obj.get_type_name()))) begin overrides[index].ovrd.m_type = obj; end end end endfunction function void uvm_default_factory::set_type_override_by_type (uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace=1); bit replaced; if (original_type == override_type) begin if (original_type.get_type_name() == "" || original_type.get_type_name() == "") uvm_report_warning("TYPDUP", {"Original and override type ", "arguments are identical"}, UVM_NONE); else uvm_report_warning("TYPDUP", {"Original and override type ", "arguments are identical: ", original_type.get_type_name()}, UVM_NONE); end if (!m_types.exists(original_type)) register(original_type); if (!m_types.exists(override_type)) register(override_type); foreach (m_type_overrides[index]) begin if(m_matches_type_override(.override(m_type_overrides[index]), .requested_type(original_type), .requested_type_name(original_type.get_type_name()))) begin string msg; msg = {"Original object type '",original_type.get_type_name(), "' already registered to produce '", m_type_overrides[index].ovrd.m_type_name,"'"}; if (!replace) begin msg = {msg, ". Set 'replace' argument to replace the existing entry."}; uvm_report_info("TPREGD", msg, UVM_MEDIUM); return; end msg = {msg, ". Replacing with override to produce type '", override_type.get_type_name(),"'."}; uvm_report_info("TPREGR", msg, UVM_MEDIUM); replaced = 1; m_type_overrides[index].orig.m_type = original_type; m_type_overrides[index].orig.m_type_name = original_type.get_type_name(); m_type_overrides[index].ovrd.m_type = override_type; m_type_overrides[index].ovrd.m_type_name = override_type.get_type_name(); m_type_overrides[index].replace = replace; end else if (m_type_overrides[index].orig.m_type == null) begin break; end end if (!replaced) begin uvm_factory_override override; override = new(.orig_type(original_type), .orig_type_name(original_type.get_type_name()), .ovrd_type(override_type), .ovrd_type_name(override_type.get_type_name()), .replace(replace)); m_type_overrides.push_front(override); end endfunction function void uvm_default_factory::set_type_override_by_name (string original_type_name, string override_type_name, bit replace=1); bit replaced; uvm_object_wrapper original_type; uvm_object_wrapper override_type; if(m_type_names.exists(original_type_name)) original_type = m_type_names[original_type_name]; if(m_type_names.exists(override_type_name)) override_type = m_type_names[override_type_name]; if (original_type_name == override_type_name) begin uvm_report_warning("TYPDUP", {"Requested and actual type name ", " arguments are identical: ",original_type_name,". Ignoring this override."}, UVM_NONE); return; end foreach (m_type_overrides[index]) begin if(m_matches_type_override(.override(m_type_overrides[index]), .requested_type(original_type), .requested_type_name(original_type_name))) begin if (!replace) begin uvm_report_info("TPREGD", {"Original type '",original_type_name, "'/'",m_type_overrides[index].orig.m_type_name, "' already registered to produce '",m_type_overrides[index].ovrd.m_type_name, "'. Set 'replace' argument to replace the existing entry."}, UVM_MEDIUM); return; end uvm_report_info("TPREGR", {"Original object type '",original_type_name, "'/'",m_type_overrides[index].orig.m_type_name, "' already registered to produce '",m_type_overrides[index].ovrd.m_type_name, "'. Replacing with override to produce type '",override_type_name,"'."}, UVM_MEDIUM); replaced = 1; m_type_overrides[index].ovrd.m_type = override_type; m_type_overrides[index].ovrd.m_type_name = override_type_name; m_type_overrides[index].replace = replace; end else if ((m_type_overrides[index].orig.m_type == null) || (original_type == null)) begin break; end end if (original_type == null) m_lookup_strs[original_type_name] = 1; if (!replaced) begin uvm_factory_override override; override = new(.orig_type(original_type), .orig_type_name(original_type_name), .ovrd_type(override_type), .ovrd_type_name(override_type_name), .replace(replace) ); m_type_overrides.push_front(override); end endfunction function bit uvm_default_factory::check_inst_override_exists (uvm_object_wrapper original_type, string original_type_name, uvm_object_wrapper override_type, string override_type_name, string full_inst_path); uvm_factory_override override; foreach (m_inst_overrides[i]) begin override = m_inst_overrides[i]; if (override.full_inst_path == full_inst_path && override.orig.m_type == original_type && override.orig.m_type_name == original_type_name && override.ovrd.m_type == override_type && override.ovrd.m_type_name == override_type_name) begin uvm_report_info("DUPOVRD",{"Instance override for '", original_type_name,"' already exists: override type '", override_type_name,"' with full_inst_path '", full_inst_path,"'"},UVM_HIGH); return 1; end end return 0; endfunction function void uvm_default_factory::set_inst_override_by_type (uvm_object_wrapper original_type, uvm_object_wrapper override_type, string full_inst_path); uvm_factory_override override; if (!m_types.exists(original_type)) register(original_type); if (!m_types.exists(override_type)) register(override_type); if (check_inst_override_exists(original_type, original_type.get_type_name(), override_type, override_type.get_type_name(), full_inst_path)) return; override = new(.full_inst_path(full_inst_path), .orig_type(original_type), .orig_type_name(original_type.get_type_name()), .ovrd_type(override_type), .ovrd_type_name(override_type.get_type_name())); m_inst_overrides.push_back(override); endfunction function void uvm_default_factory::set_inst_override_by_name (string original_type_name, string override_type_name, string full_inst_path); uvm_factory_override override; uvm_object_wrapper original_type; uvm_object_wrapper override_type; if(m_type_names.exists(original_type_name)) original_type = m_type_names[original_type_name]; if(m_type_names.exists(override_type_name)) override_type = m_type_names[override_type_name]; if (original_type == null) m_lookup_strs[original_type_name] = 1; override = new(.full_inst_path(full_inst_path), .orig_type(original_type), .orig_type_name(original_type_name), .ovrd_type(override_type), .ovrd_type_name(override_type_name)); if (check_inst_override_exists(original_type, original_type_name, override_type, override_type_name, full_inst_path)) return; m_inst_overrides.push_back(override); endfunction function void uvm_default_factory::set_type_alias(string alias_type_name, uvm_object_wrapper original_type); if (!is_type_registered(original_type)) uvm_report_warning("BDTYP",{"Cannot define alias of type '", original_type.get_type_name(),"' because it is not registered with the factory."}, UVM_NONE); else begin if (!m_type_names.exists(alias_type_name)) begin uvm_factory_override overrides[$]; m_type_names[alias_type_name] = original_type; overrides = {m_type_overrides, m_inst_overrides}; foreach (overrides[index]) begin if(m_matches_type_pair(.match_type_pair(overrides[index].orig), .requested_type(null), .requested_type_name(alias_type_name))) begin overrides[index].orig.m_type = original_type; end if(m_matches_type_pair(.match_type_pair(overrides[index].ovrd), .requested_type(null), .requested_type_name(alias_type_name))) begin overrides[index].ovrd.m_type = original_type; end end end end endfunction function void uvm_default_factory::set_inst_alias(string alias_type_name, uvm_object_wrapper original_type, string full_inst_path); string original_type_name; m_inst_typename_alias_t orig_type_alias_per_inst; original_type_name = original_type.get_type_name(); if (!is_type_registered(original_type)) uvm_report_warning("BDTYP",{"Cannot define alias of type '", original_type_name,"' because it is not registered with the factory."}, UVM_NONE); else begin orig_type_alias_per_inst.alias_type_name = alias_type_name; orig_type_alias_per_inst.full_inst_path = full_inst_path; orig_type_alias_per_inst.orig.m_type_name = original_type_name; orig_type_alias_per_inst.orig.m_type = original_type; m_inst_aliases.push_back(orig_type_alias_per_inst); end endfunction function uvm_object uvm_default_factory::create_object_by_name (string requested_type_name, string parent_inst_path="", string name=""); uvm_object_wrapper wrapper; string inst_path; if (parent_inst_path == "") inst_path = name; else if (name != "") inst_path = {parent_inst_path,".",name}; else inst_path = parent_inst_path; m_override_info.delete(); wrapper = find_override_by_name(requested_type_name, inst_path); if (wrapper==null) begin wrapper = m_resolve_type_name_by_inst(requested_type_name,inst_path); if(wrapper == null) begin uvm_report_warning("BDTYP",{"Cannot create an object of type '", requested_type_name,"' because it is not registered with the factory."}, UVM_NONE); return null; end end return wrapper.create_object(name); endfunction function uvm_object uvm_default_factory::create_object_by_type (uvm_object_wrapper requested_type, string parent_inst_path="", string name=""); string full_inst_path; if (parent_inst_path == "") full_inst_path = name; else if (name != "") full_inst_path = {parent_inst_path,".",name}; else full_inst_path = parent_inst_path; m_override_info.delete(); requested_type = find_override_by_type(requested_type, full_inst_path); return requested_type.create_object(name); endfunction function bit uvm_default_factory::is_type_name_registered (string type_name); return (m_type_names.exists(type_name)); endfunction function bit uvm_default_factory::is_type_registered (uvm_object_wrapper obj); return (m_types.exists(obj)); endfunction function uvm_component uvm_default_factory::create_component_by_name (string requested_type_name, string parent_inst_path="", string name, uvm_component parent); uvm_object_wrapper wrapper; string inst_path; if (parent_inst_path == "") inst_path = name; else if (name != "") inst_path = {parent_inst_path,".",name}; else inst_path = parent_inst_path; m_override_info.delete(); wrapper = find_override_by_name(requested_type_name, inst_path); if (wrapper == null) begin if(!m_type_names.exists(requested_type_name)) begin uvm_report_warning("BDTYP",{"Cannot create a component of type '", requested_type_name,"' because it is not registered with the factory."}, UVM_NONE); return null; end wrapper = m_type_names[requested_type_name]; end return wrapper.create_component(name, parent); endfunction function uvm_component uvm_default_factory::create_component_by_type (uvm_object_wrapper requested_type, string parent_inst_path="", string name, uvm_component parent); string full_inst_path; if (parent_inst_path == "") full_inst_path = name; else if (name != "") full_inst_path = {parent_inst_path,".",name}; else full_inst_path = parent_inst_path; m_override_info.delete(); requested_type = find_override_by_type(requested_type, full_inst_path); return requested_type.create_component(name, parent); endfunction function uvm_object_wrapper uvm_default_factory::find_wrapper_by_name(string type_name); uvm_object_wrapper wrapper = m_resolve_type_name(type_name); if (wrapper != null) return wrapper; uvm_report_warning("UnknownTypeName", {"find_wrapper_by_name: Type name '",type_name, "' not registered with the factory."}, UVM_NONE); endfunction function uvm_object_wrapper uvm_default_factory::find_override_by_name (string requested_type_name, string full_inst_path); uvm_object_wrapper rtype; uvm_factory_override lindex; rtype = m_resolve_type_name_by_inst(requested_type_name,full_inst_path); if(full_inst_path != "") begin foreach(m_inst_overrides[i]) begin if(m_matches_inst_override(.override(m_inst_overrides[i]), .requested_type(rtype), .requested_type_name(requested_type_name), .full_inst_path(full_inst_path))) begin m_override_info.push_back(m_inst_overrides[i]); if (lindex == null) begin lindex = m_inst_overrides[i]; if (!m_debug_pass) begin break; end end end end end if ((lindex == null) || m_debug_pass) begin uvm_factory_override matched_overrides[$]; foreach (m_type_overrides[index]) begin if(m_matches_type_override(.override(m_type_overrides[index]), .requested_type(rtype), .requested_type_name(requested_type_name), .full_inst_path(full_inst_path), .resolve_null_type_by_inst(1))) begin matched_overrides.push_back(m_type_overrides[index]); if ((lindex == null) || (lindex.replace == 0)) begin lindex = m_type_overrides[index]; if (!m_debug_pass && lindex.replace) begin break; end end end end if(matched_overrides.size() != 0) begin if (m_debug_pass) begin m_override_info = {m_override_info,matched_overrides}; end else begin m_override_info.push_back(matched_overrides[$]); end end end if (lindex != null) begin uvm_object_wrapper override = lindex.ovrd.m_type; lindex.used++; if (m_debug_pass) begin lindex.selected = 1; end if(!m_matches_type_override(.override(lindex), .requested_type(rtype), .requested_type_name(requested_type_name), .full_inst_path(full_inst_path), .match_original_type(0), .resolve_null_type_by_inst(1))) begin if(override == null) begin override = find_override_by_name(lindex.ovrd.m_type_name,full_inst_path); end else begin override = find_override_by_type(override,full_inst_path); end end else if(override == null) begin override = m_resolve_type_name_by_inst(lindex.ovrd.m_type_name,full_inst_path); end if(override == null) begin uvm_report_error("TYPNTF", {"Cannot resolve override for original type '", lindex.orig.m_type_name,"' because the override type '", lindex.ovrd.m_type_name, "' is not registered with the factory."}, UVM_NONE); end return override; end return null; endfunction function uvm_object_wrapper uvm_default_factory::find_override_by_type(uvm_object_wrapper requested_type, string full_inst_path); uvm_object_wrapper override; uvm_factory_override lindex; uvm_factory_queue_class qc; foreach (m_override_info[index]) begin if ( m_override_info[index].orig.m_type == requested_type) begin uvm_report_error("OVRDLOOP", "Recursive loop detected while finding override.", UVM_NONE); m_override_info[index].used++; if (!m_debug_pass) debug_create_by_type (requested_type, full_inst_path); return requested_type; end end if(full_inst_path != "") begin foreach(m_inst_overrides[i]) begin if(m_matches_inst_override(.override(m_inst_overrides[i]), .requested_type(requested_type), .requested_type_name(requested_type.get_type_name()), .full_inst_path(full_inst_path))) begin m_override_info.push_back(m_inst_overrides[i]); if (lindex == null) begin lindex = m_inst_overrides[i]; if (!m_debug_pass) begin break; end end end end end if ((lindex == null) || m_debug_pass) begin uvm_factory_override matched_overrides[$]; foreach (m_type_overrides[index]) begin if(m_matches_type_override(.override(m_type_overrides[index]), .requested_type(requested_type), .requested_type_name(requested_type.get_type_name()), .full_inst_path(full_inst_path), .resolve_null_type_by_inst(1))) begin matched_overrides.push_back(m_type_overrides[index]); if ((lindex == null) || (lindex.replace == 0)) begin lindex = m_type_overrides[index]; if (!m_debug_pass && lindex.replace) begin break; end end end end if(matched_overrides.size() != 0) begin if (m_debug_pass) begin m_override_info = {m_override_info,matched_overrides}; end else begin m_override_info.push_back(matched_overrides[$]); end end end if (lindex != null) begin uvm_object_wrapper override = lindex.ovrd.m_type; lindex.used++; if (m_debug_pass) begin lindex.selected = 1; end if(!m_matches_type_override(.override(lindex), .requested_type(requested_type), .requested_type_name(requested_type.get_type_name()), .full_inst_path(full_inst_path), .match_original_type(0), .resolve_null_type_by_inst(1))) begin if(override == null) begin override = find_override_by_name(lindex.ovrd.m_type_name,full_inst_path); end else begin override = find_override_by_type(override,full_inst_path); end end else if(override == null) begin override = m_resolve_type_name_by_inst(lindex.ovrd.m_type_name,full_inst_path); end if(override == null) begin uvm_report_error("TYPNTF", {"Cannot resolve override for original type '", lindex.orig.m_type_name,"' because the override type '", lindex.ovrd.m_type_name, "' is not registered with the factory."}, UVM_NONE); end return override; end return requested_type; endfunction function void uvm_default_factory::print (int all_types=1); string key; string qs[$]; qs.push_back("\n#### Factory Configuration (*)\n\n"); if(!m_type_overrides.size() && !m_inst_overrides.size()) qs.push_back(" No instance or type overrides are registered with this factory\n"); else begin int max1,max2,max3; string dash = "---------------------------------------------------------------------------------------------------"; string space= " "; if(!m_inst_overrides.size()) qs.push_back("No instance overrides are registered with this factory\n"); else begin foreach(m_inst_overrides[j]) begin if (m_inst_overrides[j].orig.m_type_name.len() > max1) max1=m_inst_overrides[j].orig.m_type_name.len(); if (m_inst_overrides[j].full_inst_path.len() > max2) max2=m_inst_overrides[j].full_inst_path.len(); if (m_inst_overrides[j].ovrd.m_type_name.len() > max3) max3=m_inst_overrides[j].ovrd.m_type_name.len(); end if (max1 < 14) max1 = 14; if (max2 < 13) max2 = 13; if (max3 < 13) max3 = 13; qs.push_back("Instance Overrides:\n\n"); qs.push_back($sformatf(" %0s%0s %0s%0s %0s%0s\n","Requested Type",space.substr(1,max1-14), "Override Path", space.substr(1,max2-13), "Override Type", space.substr(1,max3-13))); qs.push_back($sformatf(" %0s %0s %0s\n",dash.substr(1,max1), dash.substr(1,max2), dash.substr(1,max3))); foreach(m_inst_overrides[j]) begin qs.push_back($sformatf(" %0s%0s %0s%0s",m_inst_overrides[j].orig.m_type_name, space.substr(1,max1-m_inst_overrides[j].orig.m_type_name.len()), m_inst_overrides[j].full_inst_path, space.substr(1,max2-m_inst_overrides[j].full_inst_path.len()))); qs.push_back($sformatf(" %0s\n", m_inst_overrides[j].ovrd.m_type_name)); end end if (!m_type_overrides.size()) qs.push_back("\nNo type overrides are registered with this factory\n"); else begin if (max1 < 14) max1 = 14; if (max2 < 13) max2 = 13; if (max3 < 13) max3 = 13; foreach (m_type_overrides[i]) begin if (m_type_overrides[i].orig.m_type_name.len() > max1) max1=m_type_overrides[i].orig.m_type_name.len(); if (m_type_overrides[i].ovrd.m_type_name.len() > max2) max2=m_type_overrides[i].ovrd.m_type_name.len(); end if (max1 < 14) max1 = 14; if (max2 < 13) max2 = 13; qs.push_back("\nType Overrides:\n\n"); qs.push_back($sformatf(" %0s%0s %0s%0s\n","Requested Type",space.substr(1,max1-14), "Override Type", space.substr(1,max2-13))); qs.push_back($sformatf(" %0s %0s\n",dash.substr(1,max1), dash.substr(1,max2))); for (int index=m_type_overrides.size()-1; index>=0; index--) qs.push_back($sformatf(" %0s%0s %0s\n", m_type_overrides[index].orig.m_type_name, space.substr(1,max1-m_type_overrides[index].orig.m_type_name.len()), m_type_overrides[index].ovrd.m_type_name)); end end if (all_types >= 1 && m_type_names.first(key)) begin bit banner; qs.push_back($sformatf("\nAll types registered with the factory: %0d total\n",m_types.num())); do begin if (!(all_types < 2 && uvm_is_match("uvm_*", m_type_names[key].get_type_name())) && key == m_type_names[key].get_type_name()) begin if (!banner) begin qs.push_back(" Type Name\n"); qs.push_back(" ---------\n"); banner=1; end qs.push_back($sformatf(" %s\n", m_type_names[key].get_type_name())); end end while(m_type_names.next(key)); end qs.push_back("(*) Types with no associated type name will be printed as \n\n####\n\n"); begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"UVM/FACTORY/PRINT")) uvm_report_info ("UVM/FACTORY/PRINT", uvm_pkg::m_uvm_string_queue_join(qs), UVM_NONE, "t/uvm/src/base/uvm_factory.svh", 1875, "", 1); end endfunction function void uvm_default_factory::debug_create_by_name (string requested_type_name, string parent_inst_path="", string name=""); m_debug_create(requested_type_name, null, parent_inst_path, name); endfunction function void uvm_default_factory::debug_create_by_type (uvm_object_wrapper requested_type, string parent_inst_path="", string name=""); m_debug_create("", requested_type, parent_inst_path, name); endfunction function void uvm_default_factory::m_debug_create (string requested_type_name, uvm_object_wrapper requested_type, string parent_inst_path, string name); string full_inst_path; uvm_object_wrapper result; if (parent_inst_path == "") full_inst_path = name; else if (name != "") full_inst_path = {parent_inst_path,".",name}; else full_inst_path = parent_inst_path; m_override_info.delete(); if (requested_type == null) begin if (!m_type_names.exists(requested_type_name) && !m_lookup_strs.exists(requested_type_name)) begin uvm_report_warning("Factory Warning", {"The factory does not recognize '", requested_type_name,"' as a registered type."}, UVM_NONE); return; end m_debug_pass = 1; result = find_override_by_name(requested_type_name,full_inst_path); end else begin m_debug_pass = 1; if (!m_types.exists(requested_type)) register(requested_type); result = find_override_by_type(requested_type,full_inst_path); if (requested_type_name == "") requested_type_name = requested_type.get_type_name(); end m_debug_display(requested_type_name, result, full_inst_path); m_debug_pass = 0; foreach (m_override_info[index]) m_override_info[index].selected = 0; endfunction function void uvm_default_factory::m_debug_display (string requested_type_name, uvm_object_wrapper result, string full_inst_path); int max1,max2,max3; string dash = "---------------------------------------------------------------------------------------------------"; string space= " "; string qs[$]; qs.push_back("\n#### Factory Override Information (*)\n\n"); qs.push_back( $sformatf("Given a request for an object of type '%s' with an instance\npath of '%s' the factory encountered\n\n", requested_type_name,full_inst_path)); if (m_override_info.size() == 0) qs.push_back("no relevant overrides.\n\n"); else begin qs.push_back("the following relevant overrides. An 'x' next to a match indicates a\nmatch that was ignored.\n\n"); foreach (m_override_info[i]) begin if (m_override_info[i].orig.m_type_name.len() > max1) max1=m_override_info[i].orig.m_type_name.len(); if (m_override_info[i].full_inst_path.len() > max2) max2=m_override_info[i].full_inst_path.len(); if (m_override_info[i].ovrd.m_type_name.len() > max3) max3=m_override_info[i].ovrd.m_type_name.len(); end if (max1 < 13) max1 = 13; if (max2 < 13) max2 = 13; if (max3 < 13) max3 = 13; qs.push_back($sformatf("Original Type%0s Instance Path%0s Override Type%0s\n", space.substr(1,max1-13),space.substr(1,max2-13),space.substr(1,max3-13))); qs.push_back($sformatf(" %0s %0s %0s\n",dash.substr(1,max1), dash.substr(1,max2), dash.substr(1,max3))); foreach (m_override_info[i]) begin qs.push_back($sformatf("%s%0s%0s\n", m_override_info[i].selected ? " " : "x ", m_override_info[i].orig.m_type_name, space.substr(1,max1-m_override_info[i].orig.m_type_name.len()))); qs.push_back($sformatf(" %0s%0s", m_override_info[i].full_inst_path, space.substr(1,max2-m_override_info[i].full_inst_path.len()))); qs.push_back($sformatf(" %0s%0s", m_override_info[i].ovrd.m_type_name, space.substr(1,max3-m_override_info[i].ovrd.m_type_name.len()))); if (m_override_info[i].full_inst_path == "*") qs.push_back(" "); else qs.push_back("\n"); end qs.push_back("\n"); end qs.push_back("Result:\n\n"); qs.push_back($sformatf(" The factory will produce an object of type '%0s'\n", result == null ? requested_type_name : result.get_type_name())); qs.push_back("\n(*) Types with no associated type name will be printed as \n\n####\n\n"); begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"UVM/FACTORY/DUMP")) uvm_report_info ("UVM/FACTORY/DUMP", uvm_pkg::m_uvm_string_queue_join(qs), UVM_NONE, "t/uvm/src/base/uvm_factory.svh", 2015, "", 1); end endfunction function uvm_object_wrapper uvm_default_factory::m_resolve_type_name(string requested_type_name); uvm_object_wrapper wrapper=null; if(m_type_names.exists(requested_type_name)) wrapper = m_type_names[requested_type_name]; return wrapper; endfunction function uvm_object_wrapper uvm_default_factory::m_resolve_type_name_by_inst(string requested_type_name, string full_inst_path); uvm_object_wrapper wrapper=null; m_inst_typename_alias_t type_alias_inst[$]; type_alias_inst = m_inst_aliases.find(i) with ((i.alias_type_name == requested_type_name) && uvm_is_match(i.full_inst_path,full_inst_path)); if (type_alias_inst.size() > 0) begin wrapper = type_alias_inst[0].orig.m_type; end else begin wrapper = m_resolve_type_name(requested_type_name); end return wrapper; endfunction function bit uvm_default_factory::m_matches_type_pair(m_uvm_factory_type_pair_t match_type_pair, uvm_object_wrapper requested_type, string requested_type_name); return ((match_type_pair.m_type != null) && (match_type_pair.m_type == requested_type) || (match_type_pair.m_type_name != "" && match_type_pair.m_type_name != "" && match_type_pair.m_type_name == requested_type_name)); endfunction function bit uvm_default_factory::m_matches_inst_override(uvm_factory_override override, uvm_object_wrapper requested_type, string requested_type_name, string full_inst_path=""); m_uvm_factory_type_pair_t match_type_pair = override.orig ; if(match_type_pair.m_type == null) begin match_type_pair.m_type = m_resolve_type_name_by_inst(match_type_pair.m_type_name, full_inst_path); end if (m_matches_type_pair(.match_type_pair(match_type_pair), .requested_type(requested_type), .requested_type_name(requested_type_name))) begin if(override.has_wildcard) begin return (override.full_inst_path == "*" || uvm_is_match(override.full_inst_path,full_inst_path)); end else begin return (override.full_inst_path == full_inst_path); end end return 0; endfunction function bit uvm_default_factory::m_matches_type_override(uvm_factory_override override, uvm_object_wrapper requested_type, string requested_type_name, string full_inst_path="", bit match_original_type = 1, bit resolve_null_type_by_inst=0); m_uvm_factory_type_pair_t match_type_pair = match_original_type ? override.orig : override.ovrd; if(match_type_pair.m_type == null) begin if(resolve_null_type_by_inst) begin match_type_pair.m_type = m_resolve_type_name_by_inst(match_type_pair.m_type_name,full_inst_path); end else begin match_type_pair.m_type = m_resolve_type_name(match_type_pair.m_type_name); end end return m_matches_type_pair(.match_type_pair(match_type_pair), .requested_type(requested_type), .requested_type_name(requested_type_name)); endfunction `define UVM_REGISTRY_SVH typedef class uvm_registry_common; typedef class uvm_registry_component_creator; typedef class uvm_registry_object_creator; class uvm_component_registry #(type T=uvm_component, string Tname="") extends uvm_object_wrapper; typedef uvm_component_registry #(T,Tname) this_type; typedef uvm_registry_common#( this_type, uvm_registry_component_creator, T, Tname ) common_type; virtual function uvm_component create_component (string name, uvm_component parent); T obj; obj = new(name, parent); return obj; endfunction static function string type_name(); return common_type::type_name(); endfunction : type_name virtual function string get_type_name(); common_type common = common_type::get(); return common.get_type_name(); endfunction static function this_type get(); static this_type m_inst; if (m_inst == null) m_inst = new(); return m_inst; endfunction virtual function void initialize(); common_type common = common_type::get(); common.initialize(); endfunction static function T create(string name, uvm_component parent, string contxt=""); return common_type::create( name, parent, contxt ); endfunction static function void set_type_override (uvm_object_wrapper override_type, bit replace=1); common_type::set_type_override( override_type, replace ); endfunction static function void set_inst_override(uvm_object_wrapper override_type, string inst_path, uvm_component parent=null); common_type::set_inst_override( override_type, inst_path, parent ); endfunction static function bit set_type_alias(string alias_name); common_type::set_type_alias( alias_name ); return 1; endfunction endclass class uvm_object_registry #(type T=uvm_object, string Tname="") extends uvm_object_wrapper; typedef uvm_object_registry #(T,Tname) this_type; typedef uvm_registry_common#( this_type, uvm_registry_object_creator, T, Tname ) common_type; virtual function uvm_object create_object(string name=""); T obj; if (name=="") obj = new(); else obj = new(name); return obj; endfunction static function string type_name(); return common_type::type_name(); endfunction : type_name virtual function string get_type_name(); common_type common = common_type::get(); return common.get_type_name(); endfunction static function this_type get(); static this_type m_inst; if (m_inst == null) m_inst = new(); return m_inst; endfunction static function T create (string name="", uvm_component parent=null, string contxt=""); return common_type::create( name, parent, contxt ); endfunction static function void set_type_override (uvm_object_wrapper override_type, bit replace=1); common_type::set_type_override( override_type, replace ); endfunction static function void set_inst_override(uvm_object_wrapper override_type, string inst_path, uvm_component parent=null); common_type::set_inst_override( override_type, inst_path, parent ); endfunction static function bit set_type_alias(string alias_name); common_type::set_type_alias( alias_name ); return 1; endfunction virtual function void initialize(); common_type common = common_type::get(); common.initialize(); endfunction endclass class uvm_abstract_component_registry #(type T=uvm_component, string Tname="") extends uvm_object_wrapper; typedef uvm_abstract_component_registry #(T,Tname) this_type; typedef uvm_registry_common#( this_type, uvm_registry_component_creator, T, Tname ) common_type; virtual function uvm_component create_component (string name, uvm_component parent); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/ABST_RGTRY/CREATE_ABSTRACT_CMPNT")) uvm_report_error ("UVM/ABST_RGTRY/CREATE_ABSTRACT_CMPNT", $sformatf( "Cannot create an instance of abstract class %s (with name %s and parent %s). Check for missing factory overrides for %s.", this.get_type_name(), name, parent.get_full_name(), this.get_type_name() ), UVM_NONE, "t/uvm/src/base/uvm_registry.svh", 308, "", 1); end return null; endfunction static function string type_name(); return common_type::type_name(); endfunction : type_name virtual function string get_type_name(); common_type common = common_type::get(); return common.get_type_name(); endfunction static function this_type get(); static this_type m_inst; if (m_inst == null) m_inst = new(); return m_inst; endfunction static function T create(string name, uvm_component parent, string contxt=""); return common_type::create( name, parent, contxt ); endfunction static function void set_type_override (uvm_object_wrapper override_type, bit replace=1); common_type::set_type_override( override_type, replace ); endfunction static function void set_inst_override(uvm_object_wrapper override_type, string inst_path, uvm_component parent=null); common_type::set_inst_override( override_type, inst_path, parent ); endfunction static function bit set_type_alias(string alias_name); common_type::set_type_alias( alias_name ); return 1; endfunction virtual function void initialize(); common_type common = common_type::get(); common.initialize(); endfunction endclass class uvm_abstract_object_registry #(type T=uvm_object, string Tname="") extends uvm_object_wrapper; typedef uvm_abstract_object_registry #(T,Tname) this_type; typedef uvm_registry_common#( this_type, uvm_registry_object_creator, T, Tname ) common_type; virtual function uvm_object create_object(string name=""); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/ABST_RGTRY/CREATE_ABSTRACT_OBJ")) uvm_report_error ("UVM/ABST_RGTRY/CREATE_ABSTRACT_OBJ", $sformatf( "Cannot create an instance of abstract class %s (with name %s). Check for missing factory overrides for %s.", this.get_type_name(), name, this.get_type_name() ), UVM_NONE, "t/uvm/src/base/uvm_registry.svh", 428, "", 1); end return null; endfunction static function string type_name(); return common_type::type_name(); endfunction : type_name virtual function string get_type_name(); common_type common = common_type::get(); return common.get_type_name(); endfunction static function this_type get(); static this_type m_inst; if (m_inst == null) m_inst = new(); return m_inst; endfunction static function T create (string name="", uvm_component parent=null, string contxt=""); return common_type::create( name, parent, contxt ); endfunction static function void set_type_override (uvm_object_wrapper override_type, bit replace=1); common_type::set_type_override( override_type, replace ); endfunction static function void set_inst_override(uvm_object_wrapper override_type, string inst_path, uvm_component parent=null); common_type::set_inst_override( override_type, inst_path, parent ); endfunction static function bit set_type_alias(string alias_name); common_type::set_type_alias( alias_name ); return 1; endfunction virtual function void initialize(); common_type common = common_type::get(); common.initialize(); endfunction endclass class uvm_registry_common #( type Tregistry=int, type Tcreator=int, type Tcreated=int, string Tname="" ); typedef uvm_registry_common#(Tregistry,Tcreator,Tcreated,Tname) this_type; local static string m__type_aliases[$]; static function string type_name(); if((Tname == "") && (m__type_aliases.size() != 0)) begin return m__type_aliases[0]; end return Tname; endfunction : type_name virtual function string get_type_name(); return type_name(); endfunction static function this_type get(); static this_type m_inst; if (m_inst == null) m_inst = new(); return m_inst; endfunction : get static function Tcreated create(string name, uvm_component parent, string contxt); uvm_object obj; if (contxt == "" && parent != null) contxt = parent.get_full_name(); obj = Tcreator::create_by_type( Tregistry::get(), contxt, name, parent ); if (!$cast(create, obj)) begin string msg; msg = {"Factory did not return a ", Tcreator::base_type_name(), " of type '",Tregistry::type_name, "'. A component of type '",obj == null ? "null" : obj.get_type_name(), "' was returned instead. Name=",name," Parent=", parent==null?"null":parent.get_type_name()," contxt=",contxt}; uvm_report_fatal("FCTTYP", msg, UVM_NONE); end endfunction static function void set_type_override (uvm_object_wrapper override_type, bit replace); uvm_factory factory=uvm_factory::get(); factory.set_type_override_by_type(Tregistry::get(),override_type,replace); endfunction static function void set_inst_override(uvm_object_wrapper override_type, string inst_path, uvm_component parent); string full_inst_path; uvm_factory factory=uvm_factory::get(); if (parent != null) begin if (inst_path == "") inst_path = parent.get_full_name(); else inst_path = {parent.get_full_name(),".",inst_path}; end factory.set_inst_override_by_type(Tregistry::get(),override_type,inst_path); endfunction static function void set_type_alias(string alias_name); m__type_aliases.push_back(alias_name); m__type_aliases.sort(); if (uvm_pkg::get_core_state() != UVM_CORE_UNINITIALIZED) begin uvm_factory factory = uvm_factory::get(); Tregistry rgtry = Tregistry::get(); if (factory.is_type_registered(rgtry)) begin factory.set_type_alias(alias_name,rgtry); end end endfunction static function bit __deferred_init(); Tregistry rgtry = Tregistry::get(); if (uvm_pkg::get_core_state() == UVM_CORE_UNINITIALIZED) begin uvm_pkg::uvm_deferred_init.push_back(rgtry); end else begin rgtry.initialize(); end return 1; endfunction local static bit m__initialized=__deferred_init(); virtual function void initialize(); uvm_factory factory =uvm_factory::get(); Tregistry rgtry = Tregistry::get(); factory.register(rgtry); foreach(m__type_aliases[i]) begin factory.set_type_alias(m__type_aliases[i],rgtry); end endfunction endclass virtual class uvm_registry_component_creator; static function uvm_component create_by_type( uvm_object_wrapper obj_wrpr, string contxt, string name, uvm_component parent ); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory = cs.get_factory(); return factory.create_component_by_type( obj_wrpr, contxt, name, parent ); endfunction static function string base_type_name(); return "component"; endfunction endclass virtual class uvm_registry_object_creator; static function uvm_object create_by_type( uvm_object_wrapper obj_wrpr, string contxt, string name, uvm_object unused ); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory = cs.get_factory(); unused = unused; return factory.create_object_by_type( obj_wrpr, contxt, name ); endfunction static function string base_type_name(); return "object"; endfunction endclass class uvm_pool #(type KEY=int, T=uvm_void) extends uvm_object; typedef uvm_pool #(KEY,T) this_type; static protected this_type m_global_pool; protected T pool[KEY]; typedef uvm_object_registry #(uvm_pool #(KEY,T)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_pool #(KEY,T) tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_pool"; endfunction : type_name virtual function string get_type_name(); return "uvm_pool"; endfunction : get_type_name function new (string name=""); super.new(name); endfunction static function this_type get_global_pool (); if (m_global_pool==null) m_global_pool = new("pool"); return m_global_pool; endfunction static function T get_global (KEY key); this_type gpool; gpool = get_global_pool(); return gpool.get(key); endfunction virtual function T get (KEY key); if (!pool.exists(key)) begin T default_value; pool[key] = default_value; end return pool[key]; endfunction virtual function void add (KEY key, T item); pool[key] = item; endfunction virtual function int num (); return pool.num(); endfunction virtual function void delete (KEY key); if (!exists(key)) begin uvm_report_warning("POOLDEL", $sformatf("delete: pool key doesn't exist. Ignoring delete request")); return; end pool.delete(key); endfunction virtual function int exists (KEY key); return pool.exists(key); endfunction virtual function int first (ref KEY key); return pool.first(key); endfunction virtual function int last (ref KEY key); return pool.last(key); endfunction virtual function int next (ref KEY key); return pool.next(key); endfunction virtual function int prev (ref KEY key); return pool.prev(key); endfunction virtual function void do_copy (uvm_object rhs); this_type p; KEY key; super.do_copy(rhs); if (rhs==null || !$cast(p, rhs)) return; pool = p.pool; endfunction virtual function void do_print (uvm_printer printer); string v; int cnt; string item; KEY key; printer.print_array_header("pool",pool.num(),"aa_object_string"); if (pool.first(key)) do begin item.itoa(cnt); item = {"[-key",item,"--]"}; $swrite(v,pool[key]); printer.print_generic(item,"",-1,v,"["); end while (pool.next(key)); printer.print_array_footer(); endfunction endclass class uvm_object_string_pool #(type T=uvm_object) extends uvm_pool #(string,T); typedef uvm_object_string_pool #(T) this_type; static protected this_type m_global_pool; typedef uvm_object_registry #(uvm_object_string_pool#(T)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_object_string_pool#(T) tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_obj_str_pool"; endfunction : type_name virtual function string get_type_name(); return "uvm_obj_str_pool"; endfunction : get_type_name function new (string name=""); super.new(name); endfunction static function this_type get_global_pool (); if (m_global_pool==null) m_global_pool = new("global_pool"); return m_global_pool; endfunction static function T get_global (string key); this_type gpool; gpool = get_global_pool(); return gpool.get(key); endfunction virtual function T get (string key); if (!pool.exists(key)) pool[key] = new (key); return pool[key]; endfunction virtual function void delete (string key); if (!exists(key)) begin uvm_report_warning("POOLDEL", $sformatf("delete: key '%s' doesn't exist", key)); return; end pool.delete(key); endfunction virtual function void do_print (uvm_printer printer); string key; printer.print_array_header("pool",pool.num(),"aa_object_string"); if (pool.first(key)) do printer.print_object({"[",key,"]"}, pool[key],"["); while (pool.next(key)); printer.print_array_footer(); endfunction endclass typedef class uvm_barrier; typedef class uvm_event; typedef uvm_object_string_pool #(uvm_barrier) uvm_barrier_pool ; typedef uvm_object_string_pool #(uvm_event#(uvm_object)) uvm_event_pool ; `define UVM_QUEUE_SVH class uvm_queue #(type T=int) extends uvm_object; typedef uvm_queue #(T) this_type; typedef uvm_object_registry #(uvm_queue#(T)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_queue#(T) tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_queue"; endfunction : type_name virtual function string get_type_name(); return "uvm_queue"; endfunction : get_type_name static local this_type m_global_queue; protected T queue[$]; function new (string name=""); super.new(name); endfunction static function this_type get_global_queue (); if (m_global_queue==null) m_global_queue = new("global_queue"); return m_global_queue; endfunction static function T get_global (int index); this_type gqueue; gqueue = get_global_queue(); return gqueue.get(index); endfunction virtual function T get (int index); T default_value; if (index >= size() || index < 0) begin uvm_report_warning("QUEUEGET", $sformatf("get: given index out of range for queue of size %0d. Ignoring get request",size())); return default_value; end return queue[index]; endfunction virtual function int size (); return queue.size(); endfunction virtual function void insert (int index, T item); if (index >= size() || index < 0) begin uvm_report_warning("QUEUEINS", $sformatf("insert: given index out of range for queue of size %0d. Ignoring insert request",size())); return; end queue.insert(index,item); endfunction virtual function void delete (int index=-1); if (index >= size() || index < -1) begin uvm_report_warning("QUEUEDEL", $sformatf("delete: given index out of range for queue of size %0d. Ignoring delete request",size())); return; end if (index == -1) queue.delete(); else queue.delete(index); endfunction virtual function T pop_front(); return queue.pop_front(); endfunction virtual function T pop_back(); return queue.pop_back(); endfunction virtual function void push_front(T item); queue.push_front(item); endfunction virtual function void push_back(T item); queue.push_back(item); endfunction virtual task wait_until_not_empty(); wait(queue.size() > 0); endtask virtual function void do_copy (uvm_object rhs); this_type p; super.do_copy(rhs); if (rhs == null || !$cast(p, rhs)) return; queue = p.queue; endfunction virtual function string convert2string(); return $sformatf("%p",queue); endfunction endclass class uvm_spell_chkr #(type T=int); typedef T tab_t[string]; static const int unsigned max = '1; static function bit check ( ref tab_t strtab, input string s); string key; int distance; int unsigned min; string min_key[$]; if(strtab.exists(s)) begin return 1; end min = max; foreach(strtab[key]) begin distance = levenshtein_distance(key, s); if(distance < 0) continue; if(distance < min) begin min = distance; min_key.delete(); min_key.push_back(key); continue; end if(distance == min) begin min_key.push_back(key); end end if(min == max) begin begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"UVM/CONFIGDB/SPELLCHK")) uvm_report_info ("UVM/CONFIGDB/SPELLCHK", $sformatf("%s not located, no alternatives to suggest", s), UVM_NONE, "t/uvm/src/base/uvm_spell_chkr.svh", 110, "", 1); end end else begin string q[$]; foreach(min_key[i]) begin q.push_back(min_key[i]); q.push_back("|"); end if(q.size()) void'(q.pop_back()); begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"UVM/CONFIGDB/SPELLCHK")) uvm_report_info ("UVM/CONFIGDB/SPELLCHK", $sformatf("%s not located, did you mean %s", s, uvm_pkg::m_uvm_string_queue_join(q)), UVM_NONE, "t/uvm/src/base/uvm_spell_chkr.svh", 124, "", 1); end end return 0; endfunction static local function int levenshtein_distance(string s, string t); int k, i, j, n, m, cost, distance; int d[]; n = s.len() + 1; m = t.len() + 1; if(n == 1 || m == 1) return -1; d = new[m*n]; for(k = 0; k < n; k++) d[k] = k; for(k = 0; k < m; k++) d[k*n] = k; for(i = 1; i < n; i++) begin for(j = 1; j < m; j++) begin cost = !(s[i-1] == t[j-1]); d[j*n+i] = minimum(d[(j-1)*n+i]+1, d[j*n+i-1]+1, d[(j-1)*n+i-1]+cost); end end distance = d[n*m-1]; return distance; endfunction static local function int minimum(int a, int b, int c); int min = a; if(b < min) min = b; if(c < min) min = c; return min; endfunction endclass typedef class uvm_resource_base; class uvm_resource_types; typedef bit[1:0] override_t; typedef enum override_t { TYPE_OVERRIDE = 2'b01, NAME_OVERRIDE = 2'b10 } override_e; typedef uvm_queue#(uvm_resource_base) rsrc_q_t; typedef enum { PRI_HIGH, PRI_LOW } priority_e; typedef struct { time read_time; time write_time; int unsigned read_count; int unsigned write_count; } access_t; endclass class uvm_resource_options; static local bit auditing = 1; static function void turn_on_auditing(); auditing = 1; endfunction static function void turn_off_auditing(); auditing = 0; endfunction static function bit is_auditing(); return auditing; endfunction endclass virtual class uvm_resource_base extends uvm_object; protected bit modified; protected bit read_only; uvm_resource_types::access_t access[string]; function new(string name = ""); super.new(name); modified = 0; read_only = 0; endfunction pure virtual function uvm_resource_base get_type_handle(); function void set_read_only(); read_only = 1; endfunction function void set_read_write(); read_only = 0; endfunction function bit is_read_only(); return read_only; endfunction task wait_modified(); wait (modified == 1); modified = 0; endtask function string convert2string(); return $sformatf("(%s) %s", m_value_type_name(), m_value_as_string()); endfunction pure virtual function string m_value_type_name(); pure virtual function string m_value_as_string(); function void do_print(uvm_printer printer); super.do_print(printer); printer.print_generic_element("val", m_value_type_name(), "", m_value_as_string()); endfunction : do_print function void record_read_access(uvm_object accessor = null); string str; uvm_resource_types::access_t access_record; if(!uvm_resource_options::is_auditing()) return; if(accessor != null) str = accessor.get_full_name(); else str = ""; if(access.exists(str)) access_record = access[str]; else init_access_record(access_record); access_record.read_count++; access_record.read_time = $realtime; access[str] = access_record; endfunction function void record_write_access(uvm_object accessor = null); string str; if(uvm_resource_options::is_auditing()) begin if(accessor != null) begin uvm_resource_types::access_t access_record; string str; str = accessor.get_full_name(); if(access.exists(str)) access_record = access[str]; else init_access_record(access_record); access_record.write_count++; access_record.write_time = $realtime; access[str] = access_record; end end endfunction virtual function void print_accessors(); string str; uvm_component comp; uvm_resource_types::access_t access_record; string qs[$]; if(access.num() == 0) return; foreach (access[i]) begin str = i; access_record = access[str]; qs.push_back($sformatf("%s reads: %0d @ %0t writes: %0d @ %0t\n",str, access_record.read_count, access_record.read_time, access_record.write_count, access_record.write_time)); end begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"UVM/RESOURCE/ACCESSOR")) uvm_report_info ("UVM/RESOURCE/ACCESSOR", uvm_pkg::m_uvm_string_queue_join(qs), UVM_NONE, "t/uvm/src/base/uvm_resource_base.svh", 532, "", 1); end endfunction function void init_access_record (inout uvm_resource_types::access_t access_record); access_record.read_time = 0; access_record.write_time = 0; access_record.read_count = 0; access_record.write_count = 0; endfunction endclass class get_t; string name; string scope; uvm_resource_base rsrc; time t; endclass typedef class uvm_tree_printer ; class uvm_resource_pool; uvm_resource_types::rsrc_q_t rtab [string]; uvm_resource_types::rsrc_q_t ttab [uvm_resource_base]; typedef struct { string scope ; int unsigned precedence; } rsrc_info_t ; static rsrc_info_t ri_tab [uvm_resource_base]; get_t get_record [$]; function new(); endfunction static function uvm_resource_pool get(); uvm_resource_pool t_rp; uvm_coreservice_t cs = uvm_coreservice_t::get(); t_rp = cs.get_resource_pool(); return t_rp; endfunction function bit spell_check(string s); return uvm_spell_chkr#(uvm_resource_types::rsrc_q_t)::check(rtab, s); endfunction function void set_scope (uvm_resource_base rsrc, string scope); uvm_resource_types::rsrc_q_t rq; string name; uvm_resource_base type_handle; uvm_resource_base r; int unsigned i; if(rsrc == null) begin uvm_report_warning("NULLRASRC", "attempting to set scope of a null resource"); return; end name = rsrc.get_name(); if ((name != "") && rtab.exists(name)) begin rq = rtab[name]; for(i = 0; i < rq.size(); i++) begin r = rq.get(i); if(r == rsrc) begin ri_tab[rsrc].scope = uvm_glob_to_re(scope); return ; end end end if (rq == null) rq = new(name); rq.push_back(rsrc); rtab[name] = rq; type_handle = rsrc.get_type_handle(); if(ttab.exists(type_handle)) rq = ttab[type_handle]; else rq = new(); rq.push_back(rsrc); ttab[type_handle] = rq; ri_tab[rsrc].scope = uvm_glob_to_re(scope); ri_tab[rsrc].precedence = get_default_precedence(); endfunction function void set_override(uvm_resource_base rsrc, string scope = ""); string s = scope; set_scope(rsrc, s); set_priority(rsrc, uvm_resource_types::PRI_HIGH); endfunction function void set_name_override(uvm_resource_base rsrc, string scope = ""); string s = scope; set_scope(rsrc, s); set_priority_name(rsrc, uvm_resource_types::PRI_HIGH); endfunction function void set_type_override(uvm_resource_base rsrc, string scope = ""); string s = scope; set_scope(rsrc, s); set_priority_type(rsrc, uvm_resource_types::PRI_HIGH); endfunction virtual function bit get_scope(uvm_resource_base rsrc, output string scope); uvm_resource_types::rsrc_q_t rq; string name; uvm_resource_base r; int unsigned i; if(rsrc == null) return 0; name = rsrc.get_name(); if((name != "") && rtab.exists(name)) begin rq = rtab[name]; for(i = 0; i < rq.size(); i++) begin r = rq.get(i); if(r == rsrc) begin scope = ri_tab[rsrc].scope; return 1; end end end scope = ""; return 0; endfunction virtual function void delete ( uvm_resource_base rsrc ); string name; uvm_resource_base type_handle; if (rsrc != null) begin name = rsrc.get_name(); if(name != "") begin if(rtab.exists(name)) rtab.delete(name); end type_handle = rsrc.get_type_handle(); if(ttab.exists(type_handle)) begin int q_size = ttab[type_handle].size(); if (q_size == 1) ttab.delete(type_handle); else begin int i; for (i=0; i prec) begin rsrc = r; prec = c_prec; end end return rsrc; endfunction static function void sort_by_precedence(ref uvm_resource_types::rsrc_q_t q); uvm_resource_types::rsrc_q_t all[int]; uvm_resource_base r; int unsigned prec; for(int i=0; i", scope, null); return null; end rsrc = q.get(0); push_get_record("", scope, rsrc); return rsrc; endfunction function uvm_resource_types::rsrc_q_t lookup_regex_names(string scope, string name, uvm_resource_base type_handle = null); return lookup_name(scope, name, type_handle, 0); endfunction function uvm_resource_types::rsrc_q_t lookup_regex(string re, scope); uvm_resource_types::rsrc_q_t rq; uvm_resource_types::rsrc_q_t result_q; int unsigned i; uvm_resource_base r; string s; result_q = new(); foreach (rtab[name]) begin if ( ! uvm_is_match(re, name) ) continue; rq = rtab[name]; for(i = 0; i < rq.size(); i++) begin r = rq.get(i); if(ri_tab.exists(r) && uvm_is_match(ri_tab[r].scope, scope)) result_q.push_back(r); end end return result_q; endfunction function uvm_resource_types::rsrc_q_t lookup_scope(string scope); uvm_resource_types::rsrc_q_t rq; uvm_resource_base r; int unsigned i; int unsigned err; uvm_resource_types::rsrc_q_t q = new(); string name; if(rtab.last(name)) begin do begin rq = rtab[name]; for(int i = 0; i < rq.size(); ++i) begin r = rq.get(i); if(ri_tab.exists(r) && uvm_is_match(ri_tab[r].scope, scope)) begin q.push_back(r); end end end while(rtab.prev(name)); end return q; endfunction local function void set_priority_queue(uvm_resource_base rsrc, ref uvm_resource_types::rsrc_q_t q, uvm_resource_types::priority_e pri); uvm_resource_base r; int unsigned i; string msg; string name = rsrc.get_name(); for(i = 0; i < q.size(); i++) begin r = q.get(i); if(r == rsrc) break; end if(r != rsrc) begin $sformat(msg, "Handle for resource named %s is not in the name name; cannot change its priority", name); uvm_report_error("NORSRC", msg); return; end q.delete(i); case(pri) uvm_resource_types::PRI_HIGH: q.push_front(rsrc); uvm_resource_types::PRI_LOW: q.push_back(rsrc); endcase endfunction function void set_priority_type(uvm_resource_base rsrc, uvm_resource_types::priority_e pri); uvm_resource_base type_handle; string msg; uvm_resource_types::rsrc_q_t q; if(rsrc == null) begin uvm_report_warning("NULLRASRC", "attempting to change the serach priority of a null resource"); return; end type_handle = rsrc.get_type_handle(); if(!ttab.exists(type_handle)) begin $sformat(msg, "Type handle for resrouce named %s not found in type map; cannot change its search priority", rsrc.get_name()); uvm_report_error("RNFTYPE", msg); return; end q = ttab[type_handle]; set_priority_queue(rsrc, q, pri); endfunction function void set_priority_name(uvm_resource_base rsrc, uvm_resource_types::priority_e pri); string name; string msg; uvm_resource_types::rsrc_q_t q; if(rsrc == null) begin uvm_report_warning("NULLRASRC", "attempting to change the serach priority of a null resource"); return; end name = rsrc.get_name(); if(!rtab.exists(name)) begin $sformat(msg, "Resrouce named %s not found in name map; cannot change its search priority", name); uvm_report_error("RNFNAME", msg); return; end q = rtab[name]; set_priority_queue(rsrc, q, pri); endfunction function void set_priority (uvm_resource_base rsrc, uvm_resource_types::priority_e pri); set_priority_type(rsrc, pri); set_priority_name(rsrc, pri); endfunction static function void set_default_precedence( int unsigned precedence); uvm_coreservice_t cs = uvm_coreservice_t::get(); cs.set_resource_pool_default_precedence(precedence); endfunction static function int unsigned get_default_precedence(); uvm_coreservice_t cs = uvm_coreservice_t::get(); return cs.get_resource_pool_default_precedence(); endfunction virtual function void set_precedence(uvm_resource_base r, int unsigned p=uvm_resource_pool::get_default_precedence()); uvm_resource_types::rsrc_q_t q; string name; int unsigned i; uvm_resource_base rsrc; if(r == null) begin uvm_report_warning("NULLRASRC", "attempting to set precedence of a null resource"); return; end name = r.get_name(); if(rtab.exists(name)) begin q = rtab[name]; for(i = 0; i < q.size(); i++) begin rsrc = q.get(i); if(rsrc == r) break; end end if(r != rsrc) begin uvm_report_warning("NORSRC", $sformatf("resource named %s is not placed within the pool", name)); return; end ri_tab[r].precedence = p; endfunction virtual function int unsigned get_precedence(uvm_resource_base r); uvm_resource_types::rsrc_q_t q; string name; int unsigned i; uvm_resource_base rsrc; if(r == null) begin uvm_report_warning("NULLRASRC", "attempting to get precedence of a null resource"); return uvm_resource_pool::get_default_precedence(); end name = r.get_name(); if(rtab.exists(name)) begin q = rtab[name]; for(i = 0; i < q.size(); i++) begin rsrc = q.get(i); if(rsrc == r) break; end end if(r != rsrc) begin uvm_report_warning("NORSRC", $sformatf("resource named %s is not placed within the pool", name)); return uvm_resource_pool::get_default_precedence(); end return ri_tab[r].precedence; endfunction function void m_print_resources(uvm_printer printer, uvm_resource_types::rsrc_q_t rq, bit audit = 0); printer.push_element(rq.get_name(), "uvm_queue#(uvm_resource_base)", $sformatf("%0d",rq.size()), uvm_object_value_str(rq)); for(int i=0; i"); else m_print_resources(printer, rq, audit); begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"UVM/RESOURCE_POOL/PRINT_QUEUE")) uvm_report_info ("UVM/RESOURCE_POOL/PRINT_QUEUE", printer.emit(), UVM_NONE, "t/uvm/src/base/uvm_resource.svh", 1071, "", 1); end endfunction function void dump(bit audit = 0, uvm_printer printer = null); string name; static uvm_tree_printer m_printer; if (m_printer == null) begin m_printer = new(); m_printer.set_type_name_enabled(1); end if (printer == null) printer = m_printer; printer.flush(); printer.push_element("uvm_resource_pool", "", $sformatf("%0d",rtab.size()), ""); foreach (rtab[name]) begin m_print_resources(printer, rtab[name], audit); end printer.pop_element(); begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"UVM/RESOURCE/DUMP")) uvm_report_info ("UVM/RESOURCE/DUMP", printer.emit(), UVM_NONE, "t/uvm/src/base/uvm_resource.svh", 1108, "", 1); end endfunction endclass class uvm_resource #(type T=int) extends uvm_resource_base; typedef uvm_resource#(T) this_type; static this_type my_type = get_type(); protected T val; typedef uvm_object_registry#(this_type) type_id; virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction : get_object_type virtual function uvm_object create (string name=""); this_type tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction : create static function string type_name(); return $sformatf("uvm_resource#(%s)", $typename(T)); endfunction : type_name virtual function string get_type_name(); return $sformatf("uvm_resource#(%s)", $typename(T)); endfunction : get_type_name function new(string name=""); super.new(name); endfunction virtual function string m_value_type_name(); return $typename(T); endfunction : m_value_type_name virtual function string m_value_as_string(); return $sformatf("%0p", val); endfunction : m_value_as_string static function this_type get_type(); if(my_type == null) my_type = new(); return my_type; endfunction function uvm_resource_base get_type_handle(); return get_type(); endfunction function T read(uvm_object accessor = null); record_read_access(accessor); return val; endfunction function void write(T t, uvm_object accessor = null); if(is_read_only()) begin uvm_report_error("resource", $sformatf("resource %s is read only -- cannot modify", get_name())); return; end if(val == t) return; record_write_access(accessor); val = t; modified = 1; endfunction static function this_type get_highest_precedence(ref uvm_resource_types::rsrc_q_t q); this_type rsrc; this_type r; uvm_resource_types::rsrc_q_t tq; uvm_resource_base rb; uvm_resource_pool rp = uvm_resource_pool::get(); if(q.size() == 0) return null; tq = new(); rsrc = null; for(int i = 0; i < q.size(); ++i) begin if($cast(r, q.get(i))) begin tq.push_back(r) ; end end rb = rp.get_highest_precedence(tq); if (!$cast(rsrc, rb)) return null; return rsrc; endfunction endclass `define UVM_RESOURCE_GET_FCNS(base_type) \ static function this_subtype get_by_name(string scope, string name, bit rpterr = 1); \ this_subtype t; \ uvm_resource_base b = uvm_resource#(base_type)::get_by_name(scope, name, rpterr); \ if(!$cast(t, b)) \ `uvm_fatal("BADCAST", "cannot cast resource to resource subtype") \ return t; \ endfunction \ \ static function this_subtype get_by_type(string scope = "", \ uvm_resource_base type_handle); \ this_subtype t; \ uvm_resource_base b = uvm_resource#(base_type)::get_by_type(scope, type_handle); \ if(!$cast(t, b)) \ `uvm_fatal("BADCAST", "cannot cast resource to resource subtype") \ return t; \ endfunction class uvm_int_rsrc extends uvm_resource #(int); typedef uvm_int_rsrc this_subtype; function new(string name, string s = "*"); uvm_resource_pool rp; super.new(name); rp = uvm_resource_pool::get(); rp.set_scope(this, s); endfunction function string convert2string(); string s; $sformat(s, "%0d", read()); return s; endfunction endclass class uvm_string_rsrc extends uvm_resource #(string); typedef uvm_string_rsrc this_subtype; function new(string name, string s = "*"); uvm_resource_pool rp; super.new(name); rp = uvm_resource_pool::get(); rp.set_scope(this, s); endfunction function string convert2string(); return read(); endfunction endclass class uvm_obj_rsrc extends uvm_resource #(uvm_object); typedef uvm_obj_rsrc this_subtype; function new(string name, string s = "*"); uvm_resource_pool rp; super.new(name); rp = uvm_resource_pool::get(); rp.set_scope(this, s); endfunction endclass class uvm_bit_rsrc #(int unsigned N=1) extends uvm_resource #(bit[N-1:0]); typedef uvm_bit_rsrc#(N) this_subtype; function new(string name, string s = "*"); uvm_resource_pool rp; super.new(name); rp = uvm_resource_pool::get(); rp.set_scope(this, s); endfunction function string convert2string(); string s; $sformat(s, "%0b", read()); return s; endfunction endclass class uvm_byte_rsrc #(int unsigned N=1) extends uvm_resource #(bit[7:0][N-1:0]); typedef uvm_byte_rsrc#(N) this_subtype; function new(string name, string s = "*"); uvm_resource_pool rp; super.new(name); rp = uvm_resource_pool::get(); rp.set_scope(this, s); endfunction function string convert2string(); string s; $sformat(s, "%0x", read()); return s; endfunction endclass typedef class uvm_resource_db_options; typedef class uvm_cmdline_processor; class uvm_resource_db #(type T=uvm_object); typedef uvm_resource #(T) rsrc_t; protected function new(); endfunction static function rsrc_t get_by_type(string scope); uvm_resource_pool rp = uvm_resource_pool::get(); uvm_resource_base rsrc_base; rsrc_t rsrc; string msg; uvm_resource_base type_handle = rsrc_t::get_type(); if(type_handle == null) return null; rsrc_base = rp.get_by_type(scope, type_handle); if(!$cast(rsrc, rsrc_base)) begin $sformat(msg, "Resource with specified type handle in scope %s was not located", scope); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RSRCNF")) uvm_report_warning ("RSRCNF", msg, UVM_NONE, "t/uvm/src/base/uvm_resource_db.svh", 84, "", 1); end return null; end return rsrc; endfunction static function rsrc_t get_by_name(string scope, string name, bit rpterr=1); uvm_resource_pool rp = uvm_resource_pool::get(); uvm_resource_base rsrc_base; rsrc_t rsrc; string msg; rsrc_base = rp.get_by_name(scope, name, rsrc_t::get_type(), rpterr); if(rsrc_base == null) return null; if(!$cast(rsrc, rsrc_base)) begin if(rpterr) begin $sformat(msg, "Resource with name %s in scope %s has incorrect type", name, scope); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RSRCTYPE")) uvm_report_warning ("RSRCTYPE", msg, UVM_NONE, "t/uvm/src/base/uvm_resource_db.svh", 115, "", 1); end end return null; end return rsrc; endfunction static function rsrc_t set_default(string scope, string name); rsrc_t r; uvm_resource_pool rp = uvm_resource_pool::get(); r = new(name); rp.set_scope(r, scope); return r; endfunction protected static function void m_show_msg( input string id, input string rtype, input string action, input string scope, input string name, input uvm_object accessor, input rsrc_t rsrc); T foo; string msg=$typename(foo); $sformat(msg, "%s scope='%s' name='%s' (type %s) %s accessor=%s = %s", rtype,scope,name, msg,action, (accessor != null) ? accessor.get_full_name() : "", rsrc==null?"null (failed lookup)":rsrc.convert2string()); begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,id)) uvm_report_info (id, msg, UVM_LOW, "t/uvm/src/base/uvm_resource_db.svh", 161, "", 1); end endfunction static function void set(input string scope, input string name, T val, input uvm_object accessor = null); uvm_resource_pool rp = uvm_resource_pool::get(); rsrc_t rsrc = new(name); rsrc.write(val, accessor); rp.set_scope(rsrc, scope); if(uvm_resource_db_options::is_tracing()) m_show_msg("RSRCDB/SET", "Resource","set", scope, name, accessor, rsrc); endfunction static function void set_anonymous(input string scope, T val, input uvm_object accessor = null); uvm_resource_pool rp = uvm_resource_pool::get(); rsrc_t rsrc = new(""); rsrc.write(val, accessor); rp.set_scope(rsrc, scope); if(uvm_resource_db_options::is_tracing()) m_show_msg("RSRCDB/SETANON","Resource", "set", scope, "", accessor, rsrc); endfunction static function void set_override(input string scope, input string name, T val, uvm_object accessor = null); uvm_resource_pool rp = uvm_resource_pool::get(); rsrc_t rsrc = new(name); rsrc.write(val, accessor); rp.set_override(rsrc, scope); if(uvm_resource_db_options::is_tracing()) m_show_msg("RSRCDB/SETOVRD", "Resource","set", scope, name, accessor, rsrc); endfunction static function void set_override_type(input string scope, input string name, T val, uvm_object accessor = null); uvm_resource_pool rp = uvm_resource_pool::get(); rsrc_t rsrc = new(name); rsrc.write(val, accessor); rp.set_type_override(rsrc, scope); if(uvm_resource_db_options::is_tracing()) m_show_msg("RSRCDB/SETOVRDTYP","Resource", "set", scope, name, accessor, rsrc); endfunction static function void set_override_name(input string scope, input string name, T val, uvm_object accessor = null); uvm_resource_pool rp = uvm_resource_pool::get(); rsrc_t rsrc = new(name); rsrc.write(val, accessor); rp.set_name_override(rsrc, scope); if(uvm_resource_db_options::is_tracing()) m_show_msg("RSRCDB/SETOVRDNAM","Resource", "set", scope, name, accessor, rsrc); endfunction static function bit read_by_name(input string scope, input string name, inout T val, input uvm_object accessor = null); rsrc_t rsrc = get_by_name(scope, name); if(uvm_resource_db_options::is_tracing()) m_show_msg("RSRCDB/RDBYNAM","Resource", "read", scope, name, accessor, rsrc); if(rsrc == null) return 0; val = rsrc.read(accessor); return 1; endfunction static function bit read_by_type(input string scope, inout T val, input uvm_object accessor = null); rsrc_t rsrc = get_by_type(scope); if(uvm_resource_db_options::is_tracing()) m_show_msg("RSRCDB/RDBYTYP", "Resource","read", scope, "", accessor, rsrc); if(rsrc == null) return 0; val = rsrc.read(accessor); return 1; endfunction static function bit write_by_name(input string scope, input string name, input T val, input uvm_object accessor = null); rsrc_t rsrc = get_by_name(scope, name); if(uvm_resource_db_options::is_tracing()) m_show_msg("RSRCDB/WR","Resource", "written", scope, name, accessor, rsrc); if(rsrc == null) return 0; rsrc.write(val, accessor); return 1; endfunction static function bit write_by_type(input string scope, input T val, input uvm_object accessor = null); rsrc_t rsrc = get_by_type(scope); if(uvm_resource_db_options::is_tracing()) m_show_msg("RSRCDB/WRTYP", "Resource","written", scope, "", accessor, rsrc); if(rsrc == null) return 0; rsrc.write(val, accessor); return 1; endfunction static function void dump(); uvm_resource_pool rp = uvm_resource_pool::get(); rp.dump(); endfunction endclass class uvm_resource_db_options; static local bit ready; static local bit tracing; static function void turn_on_tracing(); if (!ready) init(); tracing = 1; endfunction static function void turn_off_tracing(); if (!ready) init(); tracing = 0; endfunction static function bit is_tracing(); if (!ready) init(); return tracing; endfunction static local function void init(); uvm_cmdline_processor clp; string trace_args[$]; clp = uvm_cmdline_processor::get_inst(); if (clp.get_arg_matches("+UVM_RESOURCE_DB_TRACE", trace_args)) begin tracing = 1; end ready = 1; endfunction endclass typedef class uvm_phase; class m_uvm_waiter; string inst_name; string field_name; event trigger; function new (string inst_name, string field_name); this.inst_name = inst_name; this.field_name = field_name; endfunction endclass typedef class uvm_root; typedef class uvm_config_db_options; class uvm_config_db#(type T=int) extends uvm_resource_db#(T); static uvm_pool#(string,uvm_resource#(T)) m_rsc[uvm_component]; static local uvm_queue#(m_uvm_waiter) m_waiters[string]; static function bit get(uvm_component cntxt, string inst_name, string field_name, inout T value); uvm_resource#(T) r; uvm_resource_pool rp = uvm_resource_pool::get(); uvm_resource_types::rsrc_q_t rq; uvm_coreservice_t cs = uvm_coreservice_t::get(); if(cntxt == null) cntxt = cs.get_root(); if(inst_name == "") inst_name = cntxt.get_full_name(); else if(cntxt.get_full_name() != "") inst_name = {cntxt.get_full_name(), ".", inst_name}; rq = rp.lookup_regex_names(inst_name, field_name, uvm_resource#(T)::get_type()); r = uvm_resource#(T)::get_highest_precedence(rq); if(uvm_config_db_options::is_tracing()) m_show_msg("CFGDB/GET", "Configuration","read", inst_name, field_name, cntxt, r); if(r == null) return 0; value = r.read(cntxt); return 1; endfunction static function void set(uvm_component cntxt, string inst_name, string field_name, T value); uvm_root top; uvm_phase curr_phase; uvm_resource#(T) r; bit exists; string lookup; uvm_pool#(string,uvm_resource#(T)) pool; string rstate; uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_resource_pool rp = cs.get_resource_pool(); int unsigned precedence; process p = process::self(); if(p != null) rstate = p.get_randstate(); top = cs.get_root(); curr_phase = top.m_current_phase; if(cntxt == null) cntxt = top; if(inst_name == "") inst_name = cntxt.get_full_name(); else if(cntxt.get_full_name() != "") inst_name = {cntxt.get_full_name(), ".", inst_name}; if(!m_rsc.exists(cntxt)) begin m_rsc[cntxt] = new; end pool = m_rsc[cntxt]; lookup = {inst_name, "__M_UVM__", field_name}; if(!pool.exists(lookup)) begin r = new(field_name); rp.set_scope(r, inst_name); pool.add(lookup, r); end else begin r = pool.get(lookup); exists = 1; end if(curr_phase != null && curr_phase.get_name() == "build") precedence = cs.get_resource_pool_default_precedence() - (cntxt.get_depth()); else precedence = cs.get_resource_pool_default_precedence(); rp.set_precedence(r, precedence); r.write(value, cntxt); rp.set_priority_name(r, uvm_resource_types::PRI_HIGH); if(m_waiters.exists(field_name)) begin m_uvm_waiter w; for(int i=0; iw.trigger; end end if(p != null) p.set_randstate(rstate); if(uvm_config_db_options::is_tracing()) m_show_msg("CFGDB/SET", "Configuration","set", inst_name, field_name, cntxt, r); endfunction static function bit exists(uvm_component cntxt, string inst_name, string field_name, bit spell_chk=0); uvm_coreservice_t cs = uvm_coreservice_t::get(); if(cntxt == null) cntxt = cs.get_root(); if(inst_name == "") inst_name = cntxt.get_full_name(); else if(cntxt.get_full_name() != "") inst_name = {cntxt.get_full_name(), ".", inst_name}; return (uvm_resource_db#(T)::get_by_name(inst_name,field_name,spell_chk) != null); endfunction static task wait_modified(uvm_component cntxt, string inst_name, string field_name); process p = process::self(); string rstate = p.get_randstate(); m_uvm_waiter waiter; uvm_coreservice_t cs = uvm_coreservice_t::get(); if(cntxt == null) cntxt = cs.get_root(); if(cntxt != cs.get_root()) begin if(inst_name != "") inst_name = {cntxt.get_full_name(),".",inst_name}; else inst_name = cntxt.get_full_name(); end waiter = new(inst_name, field_name); if(!m_waiters.exists(field_name)) m_waiters[field_name] = new; m_waiters[field_name].push_back(waiter); p.set_randstate(rstate); @waiter.trigger; for(int i=0; i 1) begin string msg_queue[$]; msg_queue.push_back("("); foreach (matching_ops[i]) begin msg_queue.push_back(matching_ops[i]); if (i != matching_ops.size() - 1) msg_queue.push_back(","); end msg_queue.push_back(")"); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/FIELD_OP/SET_BAD_OP_TYPE")) uvm_report_error ("UVM/FIELD_OP/SET_BAD_OP_TYPE", {"set() was passed op_type matching multiple operations: ", uvm_pkg::m_uvm_string_queue_join(msg_queue)}, UVM_NONE, "t/uvm/src/base/uvm_field_op.svh", 88, "", 1); end end if(m_is_set == 0) begin m_op_type = op_type; m_policy = policy; m_object = rhs; m_is_set = 1'b1; end else begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/FIELD_OP/SET")) uvm_report_error ("UVM/FIELD_OP/SET", "Attempting to set values in policy without flushing", UVM_NONE, "t/uvm/src/base/uvm_field_op.svh", 98, "", 1); end endfunction virtual function string get_op_name(); case(m_op_type) UVM_COPY : return "copy"; UVM_COMPARE : return "compare"; UVM_PRINT : return "print"; UVM_RECORD : return "record"; UVM_PACK : return "pack"; UVM_UNPACK : return "unpack"; UVM_SET : return "set"; default: return ""; endcase endfunction virtual function uvm_field_flag_t get_op_type(); if(m_is_set == 1'b1) return m_op_type; else begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/FIELD_OP/GET_OP_TYPE")) uvm_report_error ("UVM/FIELD_OP/GET_OP_TYPE", "Calling get_op_type() before calling set() is not allowed", UVM_NONE, "t/uvm/src/base/uvm_field_op.svh", 120, "", 1); end endfunction virtual function uvm_policy get_policy(); if(m_is_set == 1'b1) return m_policy; else begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/FIELD_OP/GET_POLICY")) uvm_report_error ("UVM/FIELD_OP/GET_POLICY", "Attempting to call get_policy() before calling set() is not allowed", UVM_NONE, "t/uvm/src/base/uvm_field_op.svh", 129, "", 1); end endfunction virtual function uvm_object get_rhs(); if(m_is_set == 1'b1) return m_object; else begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/FIELD_OP/GET_RHS")) uvm_report_error ("UVM/FIELD_OP/GET_RHS", "Calling get_rhs() before calling set() is not allowed", UVM_NONE, "t/uvm/src/base/uvm_field_op.svh", 137, "", 1); end endfunction function bit user_hook_enabled(); if(m_is_set == 1'b1) return m_user_hook; else begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/FIELD_OP/GET_USER_HOOK")) uvm_report_error ("UVM/FIELD_OP/GET_USER_HOOK", "Attempting to get_user_hook before calling set() is not allowed", UVM_NONE, "t/uvm/src/base/uvm_field_op.svh", 145, "", 1); end endfunction function void disable_user_hook(); m_user_hook = 1'b0; endfunction static uvm_field_op m_recycled_op[$] ; virtual function void flush(); m_policy = null; m_object = null; m_user_hook = 1'b1; m_is_set = 0; endfunction function void m_recycle(); this.flush(); m_recycled_op.push_back(this); endfunction : m_recycle static function uvm_field_op m_get_available_op() ; uvm_field_op field_op ; if (m_recycled_op.size() > 0) field_op = m_recycled_op.pop_back() ; else field_op = uvm_field_op::type_id::create("field_op"); return field_op ; endfunction endclass class uvm_copier extends uvm_policy; typedef uvm_object_registry#(uvm_copier,"uvm_copier") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_copier tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_copier"; endfunction : type_name virtual function string get_type_name(); return "uvm_copier"; endfunction : get_type_name uvm_recursion_policy_enum policy = UVM_DEFAULT_POLICY; function new(string name="uvm_copier") ; super.new(name); endfunction recursion_state_e m_recur_states[uvm_object ][uvm_object ][uvm_recursion_policy_enum ]; virtual function void copy_object ( uvm_object lhs, uvm_object rhs); uvm_field_op field_op; if (get_recursion_policy() == UVM_REFERENCE) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM_COPY_POLICY")) uvm_report_error ("UVM_COPY_POLICY", "Attempting to make a copy of a object which is a reference", UVM_NONE, "t/uvm/src/base/uvm_copier.svh", 82, "", 1); end return; end if (rhs == null || lhs == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM_COPY_NULL_OBJ")) uvm_report_error ("UVM_COPY_NULL_OBJ", "Attempting to make a copy of a object with null src/target", UVM_NONE, "t/uvm/src/base/uvm_copier.svh", 87, "", 1); end return; end push_active_object(lhs); m_recur_states[rhs][lhs][get_recursion_policy()] = uvm_policy::STARTED; field_op = uvm_field_op::m_get_available_op() ; field_op.set(UVM_COPY,this,rhs); lhs.do_execute_op(field_op); if (field_op.user_hook_enabled()) begin lhs.do_copy(rhs); end field_op.m_recycle(); m_recur_states[rhs][lhs][get_recursion_policy()] = uvm_policy::FINISHED; void'(pop_active_object()); endfunction virtual function recursion_state_e object_copied( uvm_object lhs, uvm_object rhs, uvm_recursion_policy_enum recursion ); if (!m_recur_states.exists(rhs)) return NEVER ; else if (!m_recur_states[rhs].exists(lhs)) return NEVER ; else if (!m_recur_states[rhs][lhs].exists(recursion)) return NEVER ; else begin return m_recur_states[rhs][lhs][recursion]; end endfunction function void flush(); m_recur_states.delete(); endfunction virtual function void set_recursion_policy (uvm_recursion_policy_enum policy); this.policy = policy; endfunction virtual function uvm_recursion_policy_enum get_recursion_policy(); return policy; endfunction function int unsigned get_num_copies(uvm_object rhs); if (m_recur_states.exists(rhs)) return m_recur_states[rhs].size(); return 0; endfunction : get_num_copies function int get_first_copy(uvm_object rhs, ref uvm_object lhs); if (m_recur_states.exists(rhs)) return m_recur_states[rhs].first(lhs); return 0; endfunction : get_first_copy function int get_next_copy(uvm_object rhs, ref uvm_object lhs); if (m_recur_states.exists(rhs)) return m_recur_states[rhs].next(lhs); return 0; endfunction : get_next_copy function int get_last_copy(uvm_object rhs, ref uvm_object lhs); if (m_recur_states.exists(rhs)) return m_recur_states[rhs].last(lhs); return 0; endfunction : get_last_copy function int get_prev_copy(uvm_object rhs, ref uvm_object lhs); if (m_recur_states.exists(rhs)) return m_recur_states[rhs].prev(lhs); return 0; endfunction : get_prev_copy static function void set_default (uvm_copier copier) ; uvm_coreservice_t coreservice ; coreservice = uvm_coreservice_t::get() ; coreservice.set_default_copier(copier) ; endfunction static function uvm_copier get_default () ; uvm_coreservice_t coreservice ; coreservice = uvm_coreservice_t::get() ; return coreservice.get_default_copier() ; endfunction endclass typedef class m_uvm_printer_knobs; typedef class uvm_printer_element; typedef class uvm_structure_proxy; virtual class uvm_printer extends uvm_policy; typedef uvm_abstract_object_registry#(uvm_printer,"uvm_printer") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_printer"; endfunction : type_name virtual function string get_type_name(); return "uvm_printer"; endfunction : get_type_name extern function new(string name="") ; bit m_flushed ; local m_uvm_printer_knobs knobs ; protected function m_uvm_printer_knobs get_knobs() ; return knobs; endfunction extern static function void set_default(uvm_printer printer) ; extern static function uvm_printer get_default() ; extern virtual function void print_field (string name, uvm_bitstream_t value, int size, uvm_radix_enum radix=UVM_NORADIX, byte scope_separator=".", string type_name=""); extern virtual function void print_field_int (string name, uvm_integral_t value, int size, uvm_radix_enum radix=UVM_NORADIX, byte scope_separator=".", string type_name=""); extern virtual function void print_object (string name, uvm_object value, byte scope_separator="."); extern virtual function void print_object_header (string name, uvm_object value, byte scope_separator="."); extern virtual function void print_string (string name, string value, byte scope_separator="."); uvm_policy::recursion_state_e m_recur_states[uvm_object][uvm_recursion_policy_enum ] ; extern virtual function uvm_policy::recursion_state_e object_printed ( uvm_object value, uvm_recursion_policy_enum recursion); extern virtual function void print_time (string name, time value, byte scope_separator="."); extern virtual function void print_real (string name, real value, byte scope_separator="."); extern virtual function void print_generic (string name, string type_name, int size, string value, byte scope_separator="."); extern virtual function void print_generic_element (string name, string type_name, string size, string value); extern virtual function string emit (); extern virtual function void flush (); extern virtual function void set_name_enabled (bit enabled); extern virtual function bit get_name_enabled (); extern virtual function void set_type_name_enabled (bit enabled); extern virtual function bit get_type_name_enabled (); extern virtual function void set_size_enabled (bit enabled); extern virtual function bit get_size_enabled (); extern virtual function void set_id_enabled (bit enabled); extern virtual function bit get_id_enabled (); extern virtual function void set_radix_enabled (bit enabled); extern virtual function bit get_radix_enabled (); extern virtual function void set_radix_string (uvm_radix_enum radix, string prefix); extern virtual function string get_radix_string (uvm_radix_enum radix); extern virtual function void set_default_radix (uvm_radix_enum radix); extern virtual function uvm_radix_enum get_default_radix (); extern virtual function void set_root_enabled (bit enabled); extern virtual function bit get_root_enabled (); extern virtual function void set_recursion_policy (uvm_recursion_policy_enum policy); extern virtual function uvm_recursion_policy_enum get_recursion_policy (); extern virtual function void set_max_depth (int depth); extern virtual function int get_max_depth (); extern virtual function void set_file (UVM_FILE fl); extern virtual function UVM_FILE get_file (); extern virtual function void set_line_prefix (string prefix); extern virtual function string get_line_prefix (); extern virtual function void set_begin_elements (int elements = 5); extern virtual function int get_begin_elements (); extern virtual function void set_end_elements (int elements = 5); extern virtual function int get_end_elements (); local uvm_printer_element m_element_stack[$] ; protected function int m_get_stack_size(); return m_element_stack.size(); endfunction extern protected virtual function uvm_printer_element get_bottom_element (); extern protected virtual function uvm_printer_element get_top_element (); extern virtual function void push_element ( string name, string type_name, string size, string value="" ); extern virtual function void pop_element (); extern function uvm_printer_element get_unused_element() ; uvm_printer_element m_recycled_elements[$]; extern virtual function void print_array_header(string name, int size, string arraytype="array", byte scope_separator="."); extern virtual function void print_array_range (int min, int max); extern virtual function void print_array_footer (int size = 0); extern function bit istop (); extern function string index_string (int index, string name=""); string m_string; endclass class uvm_printer_element extends uvm_object; extern function new (string name=""); extern virtual function void set (string element_name = "", string element_type_name = "", string element_size = "", string element_value = "" ); extern virtual function void set_element_name (string element_name); extern virtual function string get_element_name (); extern virtual function void set_element_type_name (string element_type_name); extern virtual function string get_element_type_name (); extern virtual function void set_element_size (string element_size); extern virtual function string get_element_size (); extern virtual function void set_element_value (string element_value); extern virtual function string get_element_value (); extern function void add_child(uvm_printer_element child) ; extern function void get_children(ref uvm_printer_element children[$], input bit recurse) ; extern function void clear_children() ; local string m_name ; local string m_type_name ; local string m_size ; local string m_value ; local uvm_printer_element m_children[$] ; endclass class uvm_printer_element_proxy extends uvm_structure_proxy#(uvm_printer_element); extern function new (string name=""); extern virtual function void get_immediate_children(uvm_printer_element s, ref uvm_printer_element children[$]); endclass : uvm_printer_element_proxy class uvm_table_printer extends uvm_printer; typedef uvm_object_registry#(uvm_table_printer,"uvm_table_printer") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_table_printer tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_table_printer"; endfunction : type_name virtual function string get_type_name(); return "uvm_table_printer"; endfunction : get_type_name extern function new(string name=""); extern virtual function string emit(); extern virtual function string m_emit_element(uvm_printer_element element, int unsigned level); local static uvm_table_printer m_default_table_printer ; local static string m_space ; extern static function void set_default(uvm_table_printer printer) ; extern static function uvm_table_printer get_default() ; extern virtual function void set_indent(int indent) ; extern virtual function int get_indent() ; extern virtual function void flush() ; protected int m_max_name=4; protected int m_max_type=4; protected int m_max_size=4; protected int m_max_value=5; extern virtual function void pop_element(); endclass class uvm_tree_printer extends uvm_printer; protected string m_newline = "\n"; protected string m_linefeed ; typedef uvm_object_registry#(uvm_tree_printer,"uvm_tree_printer") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_tree_printer tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_tree_printer"; endfunction : type_name virtual function string get_type_name(); return "uvm_tree_printer"; endfunction : get_type_name extern function new(string name=""); local static uvm_tree_printer m_default_tree_printer ; extern static function void set_default(uvm_tree_printer printer) ; extern static function uvm_tree_printer get_default() ; extern virtual function void set_indent(int indent) ; extern virtual function int get_indent() ; extern virtual function void set_separators(string separators) ; extern virtual function string get_separators() ; extern virtual function void flush() ; extern virtual function string emit(); extern virtual function string m_emit_element(uvm_printer_element element, int unsigned level); endclass class uvm_line_printer extends uvm_tree_printer; typedef uvm_object_registry#(uvm_line_printer,"uvm_line_printer") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_line_printer tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_line_printer"; endfunction : type_name virtual function string get_type_name(); return "uvm_line_printer"; endfunction : get_type_name extern function new(string name=""); local static uvm_line_printer m_default_line_printer ; extern static function void set_default(uvm_line_printer printer) ; extern static function uvm_line_printer get_default() ; extern virtual function void set_separators(string separators) ; extern virtual function string get_separators() ; extern virtual function void flush() ; endclass class m_uvm_printer_knobs; bit identifier = 1; bit type_name = 1; bit size = 1; int depth = -1; bit reference = 1; int begin_elements = 5; int end_elements = 5; string prefix = ""; int indent = 2; bit show_root = 0; int mcd = UVM_STDOUT; string separator = "{}"; bit show_radix = 1; uvm_radix_enum default_radix = UVM_HEX; string dec_radix = "'d"; string bin_radix = "'b"; string oct_radix = "'o"; string unsigned_radix = "'d"; string hex_radix = "'h"; uvm_recursion_policy_enum recursion_policy ; endclass function uvm_printer::new(string name=""); super.new(name); knobs = new ; flush(); endfunction function void uvm_printer::set_default(uvm_printer printer) ; uvm_coreservice_t coreservice ; coreservice = uvm_coreservice_t::get() ; coreservice.set_default_printer(printer) ; endfunction function uvm_printer uvm_printer::get_default() ; uvm_coreservice_t coreservice ; coreservice = uvm_coreservice_t::get() ; return coreservice.get_default_printer() ; endfunction function void uvm_printer::print_field (string name, uvm_bitstream_t value, int size, uvm_radix_enum radix=UVM_NORADIX, byte scope_separator=".", string type_name=""); string sz_str, val_str; if(type_name == "") begin if(radix == UVM_TIME) type_name ="time"; else if(radix == UVM_STRING) type_name ="string"; else type_name ="integral"; end sz_str.itoa(size); if(radix == UVM_NORADIX) radix = get_default_radix(); val_str = uvm_bitstream_to_string (value, size, radix, get_radix_string(radix)); name = uvm_leaf_scope(name,scope_separator); push_element(name,type_name,sz_str,val_str); pop_element() ; endfunction function void uvm_printer::print_field_int (string name, uvm_integral_t value, int size, uvm_radix_enum radix=UVM_NORADIX, byte scope_separator=".", string type_name=""); string sz_str, val_str; if(type_name == "") begin if(radix == UVM_TIME) type_name ="time"; else if(radix == UVM_STRING) type_name ="string"; else type_name ="integral"; end sz_str.itoa(size); if(radix == UVM_NORADIX) radix = get_default_radix(); val_str = uvm_integral_to_string (value, size, radix, get_radix_string(radix)); name = uvm_leaf_scope(name,scope_separator); push_element(name,type_name,sz_str,val_str); pop_element() ; endfunction function string uvm_printer::emit (); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"NO_OVERRIDE")) uvm_report_error ("NO_OVERRIDE", "emit() method not overridden in printer subtype", UVM_NONE, "t/uvm/src/base/uvm_printer.svh", 999, "", 1); end return ""; endfunction function void uvm_printer::flush (); uvm_printer_element element = get_bottom_element() ; uvm_printer_element all_descendent_elements[$] ; element = get_bottom_element() ; if (element != null) begin element.get_children(all_descendent_elements,1) ; foreach (all_descendent_elements[i]) begin m_recycled_elements.push_back(all_descendent_elements[i]) ; all_descendent_elements[i].clear_children() ; end element.clear_children(); m_recycled_elements.push_back(element) ; m_element_stack.delete() ; end m_recur_states.delete(); m_flushed = 1 ; endfunction function void uvm_printer::set_name_enabled (bit enabled); knobs.identifier = enabled ; endfunction function bit uvm_printer::get_name_enabled (); return knobs.identifier ; endfunction function void uvm_printer::set_type_name_enabled (bit enabled); knobs.type_name = enabled ; endfunction function bit uvm_printer::get_type_name_enabled (); return knobs.type_name ; endfunction function void uvm_printer::set_size_enabled (bit enabled); knobs.size = enabled ; endfunction function bit uvm_printer::get_size_enabled (); return knobs.size ; endfunction function void uvm_printer::set_id_enabled (bit enabled); knobs.reference = enabled ; endfunction function bit uvm_printer::get_id_enabled (); return knobs.reference ; endfunction function void uvm_printer::set_radix_enabled (bit enabled); knobs.show_radix = enabled ; endfunction function bit uvm_printer::get_radix_enabled (); return knobs.show_radix ; endfunction function void uvm_printer::set_radix_string (uvm_radix_enum radix, string prefix); if (radix == UVM_DEC) knobs.dec_radix = prefix ; else if (radix == UVM_BIN) knobs.bin_radix = prefix ; else if (radix == UVM_OCT) knobs.oct_radix = prefix ; else if (radix == UVM_UNSIGNED) knobs.unsigned_radix = prefix ; else if (radix == UVM_HEX) knobs.hex_radix = prefix ; else begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"PRINTER_UNKNOWN_RADIX")) uvm_report_warning ("PRINTER_UNKNOWN_RADIX", $sformatf("set_radix_string called with unsupported radix %s",radix), UVM_NONE, "t/uvm/src/base/uvm_printer.svh", 1065, "", 1); end endfunction function string uvm_printer::get_radix_string (uvm_radix_enum radix); if (radix == UVM_DEC) return knobs.dec_radix ; else if (radix == UVM_BIN) return knobs.bin_radix ; else if (radix == UVM_OCT) return knobs.oct_radix ; else if (radix == UVM_UNSIGNED) return knobs.unsigned_radix ; else if (radix == UVM_HEX) return knobs.hex_radix ; else return ""; endfunction function void uvm_printer::set_default_radix (uvm_radix_enum radix); knobs.default_radix = radix ; endfunction function uvm_radix_enum uvm_printer::get_default_radix (); return knobs.default_radix ; endfunction function void uvm_printer::set_root_enabled (bit enabled); knobs.show_root = enabled ; endfunction function bit uvm_printer::get_root_enabled (); return knobs.show_root ; endfunction function void uvm_printer::set_recursion_policy (uvm_recursion_policy_enum policy); knobs.recursion_policy = policy ; endfunction function uvm_recursion_policy_enum uvm_printer::get_recursion_policy (); return knobs.recursion_policy ; endfunction function void uvm_printer::set_max_depth (int depth); knobs.depth = depth ; endfunction function int uvm_printer::get_max_depth (); return knobs.depth ; endfunction function void uvm_printer::set_file (UVM_FILE fl); knobs.mcd = fl ; endfunction function UVM_FILE uvm_printer::get_file (); return knobs.mcd ; endfunction function void uvm_printer::set_line_prefix (string prefix); knobs.prefix = prefix ; endfunction function string uvm_printer::get_line_prefix (); return knobs.prefix ; endfunction function void uvm_printer::set_begin_elements (int elements = 5); knobs.begin_elements = elements ; endfunction function int uvm_printer::get_begin_elements (); return knobs.begin_elements ; endfunction function void uvm_printer::set_end_elements (int elements = 5); knobs.end_elements = elements ; endfunction function int uvm_printer::get_end_elements (); return knobs.end_elements ; endfunction function uvm_printer_element uvm_printer::get_bottom_element (); if (m_element_stack.size() > 0) return m_element_stack[0] ; else return null ; endfunction function uvm_printer_element uvm_printer::get_top_element (); if (m_element_stack.size() > 0) return m_element_stack[$] ; else return null ; endfunction function uvm_printer_element_proxy::new (string name=""); super.new(name) ; endfunction function void uvm_printer_element_proxy::get_immediate_children(uvm_printer_element s, ref uvm_printer_element children[$]); s.get_children(children,0) ; endfunction function void uvm_printer::push_element ( string name, string type_name, string size, string value=""); uvm_printer_element element ; uvm_printer_element parent ; element = get_unused_element() ; parent = get_top_element() ; element.set(name,type_name,size,value); if (parent != null) parent.add_child(element) ; m_element_stack.push_back(element) ; endfunction function void uvm_printer::pop_element (); if (m_element_stack.size() > 1) begin void'(m_element_stack.pop_back()); end endfunction function uvm_printer_element uvm_printer::get_unused_element() ; uvm_printer_element element ; if (m_recycled_elements.size() > 0) begin element = m_recycled_elements.pop_back() ; end else begin element = new() ; end return element ; endfunction function void uvm_printer::print_array_header (string name, int size, string arraytype="array", byte scope_separator="."); push_element(name,arraytype,$sformatf("%0d",size),"-"); endfunction function void uvm_printer::print_array_footer (int size=0); pop_element() ; endfunction function void uvm_printer::print_array_range(int min, int max); string tmpstr; if(min == -1 && max == -1) return; if(min == -1) min = max; if(max == -1) max = min; if(max < min) return; print_generic_element("...", "...", "...", "..."); endfunction function void uvm_printer::print_object_header (string name, uvm_object value, byte scope_separator="."); if(name == "") name = ""; push_element(name, (value != null) ? value.get_type_name() : "object", "-", get_id_enabled() ? uvm_object_value_str(value) : "-"); endfunction function void uvm_printer::print_object (string name, uvm_object value, byte scope_separator="."); uvm_component comp, child_comp; uvm_field_op field_op ; uvm_recursion_policy_enum recursion_policy; recursion_policy = get_recursion_policy(); if ((value == null) || (recursion_policy == UVM_REFERENCE) || (get_max_depth() == get_active_object_depth())) begin print_object_header(name,value,scope_separator); pop_element(); end else begin push_active_object(value); m_recur_states[value][recursion_policy] = uvm_policy::STARTED ; print_object_header(name,value,scope_separator); if($cast(comp, value)) begin string name; if (comp.get_first_child(name)) do begin child_comp = comp.get_child(name); if(child_comp.print_enabled) this.print_object(name,child_comp); end while (comp.get_next_child(name)); end field_op = uvm_field_op::m_get_available_op() ; field_op.set(UVM_PRINT,this,null); value.do_execute_op(field_op); if (field_op.user_hook_enabled()) value.do_print(this); field_op.m_recycle(); pop_element() ; m_recur_states[value][recursion_policy] = uvm_policy::FINISHED ; void'(pop_active_object()); end endfunction function bit uvm_printer::istop (); return (get_active_object_depth() == 0); endfunction function void uvm_printer::print_generic (string name, string type_name, int size, string value, byte scope_separator="."); push_element(name, type_name, (size == -2 ? "..." : $sformatf("%0d",size)), value); pop_element(); endfunction function void uvm_printer::print_generic_element (string name, string type_name, string size, string value); push_element(name,type_name,size,value); pop_element() ; endfunction function void uvm_printer::print_time (string name, time value, byte scope_separator="."); print_field_int(name, value, 64, UVM_TIME, scope_separator); endfunction function void uvm_printer::print_string (string name, string value, byte scope_separator="."); push_element(name, "string", $sformatf("%0d",value.len()), (value == "" ? "\"\"" : value)); pop_element() ; endfunction function uvm_policy::recursion_state_e uvm_printer::object_printed (uvm_object value, uvm_recursion_policy_enum recursion); if (!m_recur_states.exists(value)) return NEVER ; if (!m_recur_states[value].exists(recursion)) return NEVER ; else return m_recur_states[value][recursion] ; endfunction function void uvm_printer::print_real (string name, real value, byte scope_separator="."); push_element(name,"real","64",$sformatf("%f",value)); pop_element() ; endfunction function string uvm_printer::index_string(int index, string name=""); index_string.itoa(index); index_string = { name, "[", index_string, "]" }; endfunction function uvm_printer_element::new (string name = ""); super.new(name) ; endfunction function void uvm_printer_element::set (string element_name = "", string element_type_name = "", string element_size = "", string element_value = "" ); m_name = element_name ; m_type_name = element_type_name ; m_size = element_size ; m_value = element_value ; endfunction function void uvm_printer_element::set_element_name (string element_name); m_name = element_name ; endfunction function string uvm_printer_element::get_element_name (); return m_name ; endfunction function void uvm_printer_element::set_element_type_name (string element_type_name); m_type_name = element_type_name ; endfunction function string uvm_printer_element::get_element_type_name (); return m_type_name ; endfunction function void uvm_printer_element::set_element_size (string element_size); m_size = element_size ; endfunction function string uvm_printer_element::get_element_size (); return m_size ; endfunction function void uvm_printer_element::set_element_value (string element_value); m_value = element_value ; endfunction function string uvm_printer_element::get_element_value (); return m_value ; endfunction function void uvm_printer_element::add_child(uvm_printer_element child) ; m_children.push_back(child) ; endfunction function void uvm_printer_element::get_children(ref uvm_printer_element children[$], input bit recurse) ; foreach (m_children[i]) begin children.push_back(m_children[i]) ; if (recurse) begin m_children[i].get_children(children,1) ; end end endfunction function void uvm_printer_element::clear_children() ; m_children.delete() ; endfunction function uvm_table_printer::new(string name=""); super.new(name); endfunction function void uvm_table_printer::pop_element(); int name_len; int level ; uvm_printer_element popped ; string name_str ; string type_name_str ; string size_str ; string value_str ; popped = get_top_element() ; level = m_get_stack_size() - 1 ; name_str = popped.get_element_name() ; type_name_str = popped.get_element_type_name() ; size_str = popped.get_element_size() ; value_str = popped.get_element_value() ; if ((name_str.len() + (get_indent() * level)) > m_max_name) m_max_name = (name_str.len() + (get_indent() * level)); if (type_name_str.len() > m_max_type) m_max_type = type_name_str.len(); if (size_str.len() > m_max_size) m_max_size = size_str.len(); if (value_str.len() > m_max_value) m_max_value = value_str.len(); super.pop_element() ; endfunction function string uvm_table_printer::emit(); string s; string user_format; static string dash; string dashes; string linefeed; if (!m_flushed) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/PRINT/NO_FLUSH")) uvm_report_error ("UVM/PRINT/NO_FLUSH", "printer emit() method called twice without intervening uvm_printer::flush()", UVM_NONE, "t/uvm/src/base/uvm_printer.svh", 1516, "", 1); end end else m_flushed = 0 ; linefeed = {"\n", get_line_prefix()}; begin int q[5]; int m; int qq[$]; q = '{m_max_name,m_max_type,m_max_size,m_max_value,100}; qq = q.max; m = qq[0]; if(dash.len() 0) && (value_str[0] == "@")) result = {result,"(",element.get_element_type_name(),value_str,") "}; else if (get_type_name_enabled() && (element.get_element_type_name() != "" || element.get_element_type_name() != "-" || element.get_element_type_name() != "...")) result = {result,"(",element.get_element_type_name(),") "}; if (get_size_enabled()) begin if (element.get_element_size() != "" || element.get_element_size() != "-") result = {result,"(",element.get_element_size(),") "}; end if (element_children.size() > 0) begin result = {result, string'(separators[0]), m_linefeed}; end else result = {result, value_str, " ", m_linefeed}; foreach (element_children[i]) begin result = {result, m_emit_element(element_children[i],level+1)} ; end if (element_children.size() > 0) begin result = {result, indent_str, string'(separators[1]), m_linefeed}; end end return result ; endfunction : m_emit_element function void uvm_table_printer::set_default(uvm_table_printer printer) ; m_default_table_printer = printer ; endfunction function uvm_table_printer uvm_table_printer::get_default() ; if (m_default_table_printer == null) begin m_default_table_printer = new("uvm_default_table_printer") ; end return m_default_table_printer ; endfunction function void uvm_table_printer::set_indent(int indent) ; m_uvm_printer_knobs _knobs = get_knobs(); _knobs.indent = indent ; endfunction function int uvm_table_printer::get_indent() ; m_uvm_printer_knobs _knobs = get_knobs(); return _knobs.indent ; endfunction function void uvm_table_printer::flush() ; super.flush() ; m_max_name=4; m_max_type=4; m_max_size=4; m_max_value=5; endfunction function void uvm_tree_printer::set_default(uvm_tree_printer printer) ; m_default_tree_printer = printer ; endfunction function uvm_tree_printer uvm_tree_printer::get_default() ; if (m_default_tree_printer == null) begin m_default_tree_printer = new("uvm_default_tree_printer") ; end return m_default_tree_printer ; endfunction function uvm_line_printer::new(string name="") ; super.new(name); m_newline = " "; set_indent(0); endfunction function void uvm_line_printer::set_default(uvm_line_printer printer) ; m_default_line_printer = printer ; endfunction function uvm_line_printer uvm_line_printer::get_default() ; if (m_default_line_printer == null) begin m_default_line_printer = new("uvm_default_line_printer") ; end return m_default_line_printer ; endfunction function void uvm_line_printer::set_separators(string separators) ; m_uvm_printer_knobs _knobs = get_knobs(); if (separators.len() < 2) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/PRINT/SHORT_SEP")) uvm_report_error ("UVM/PRINT/SHORT_SEP", $sformatf("Bad call: set_separators(%s) (Argument must have at least 2 characters)",separators), UVM_NONE, "t/uvm/src/base/uvm_printer.svh", 1888, "", 1); end end _knobs.separator = separators ; endfunction function string uvm_line_printer::get_separators() ; m_uvm_printer_knobs _knobs = get_knobs(); return _knobs.separator ; endfunction function void uvm_line_printer::flush() ; super.flush() ; endfunction class uvm_comparer extends uvm_policy; typedef uvm_object_registry#(uvm_comparer,"uvm_comparer") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_comparer tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_comparer"; endfunction : type_name virtual function string get_type_name(); return "uvm_comparer"; endfunction : get_type_name extern virtual function void flush(); extern virtual function uvm_policy::recursion_state_e object_compared( uvm_object lhs, uvm_object rhs, uvm_recursion_policy_enum recursion, output bit ret_val ); extern virtual function string get_miscompares(); extern virtual function int unsigned get_result(); extern virtual function void set_result(int unsigned result) ; extern virtual function void set_recursion_policy( uvm_recursion_policy_enum policy); extern virtual function uvm_recursion_policy_enum get_recursion_policy(); extern virtual function void set_check_type( bit enabled ); extern virtual function bit get_check_type(); extern virtual function void set_show_max (int unsigned show_max); extern virtual function int unsigned get_show_max (); extern virtual function void set_verbosity (int unsigned verbosity); extern virtual function int unsigned get_verbosity (); extern virtual function void set_severity (uvm_severity severity); extern virtual function uvm_severity get_severity (); extern virtual function void set_threshold (int unsigned threshold); extern virtual function int unsigned get_threshold (); typedef struct { recursion_state_e state; bit ret_val; } state_info_t ; state_info_t m_recur_states[uvm_object ][uvm_object ][uvm_recursion_policy_enum ]; local uvm_recursion_policy_enum policy = UVM_DEFAULT_POLICY; local int unsigned show_max = 1; local int unsigned verbosity = UVM_LOW; local uvm_severity sev = UVM_INFO; local string miscompares = ""; local bit check_type = 1; local int unsigned result = 0; local int unsigned m_threshold; function new(string name=""); super.new(name); m_threshold = 1; endfunction static function void set_default (uvm_comparer comparer) ; uvm_coreservice_t coreservice ; coreservice = uvm_coreservice_t::get() ; coreservice.set_default_comparer(comparer) ; endfunction static function uvm_comparer get_default () ; uvm_coreservice_t coreservice ; coreservice = uvm_coreservice_t::get() ; return coreservice.get_default_comparer() ; endfunction virtual function bit compare_field (string name, uvm_bitstream_t lhs, uvm_bitstream_t rhs, int size, uvm_radix_enum radix=UVM_NORADIX); uvm_bitstream_t mask; string msg; if(size <= 64) return compare_field_int(name, lhs, rhs, size, radix); mask = -1; mask >>= (UVM_STREAMBITS-size); if((lhs & mask) !== (rhs & mask)) begin case (radix) UVM_BIN: begin $swrite(msg, "%s: lhs = 'b%0b : rhs = 'b%0b", name, lhs&mask, rhs&mask); end UVM_OCT: begin $swrite(msg, "%s: lhs = 'o%0o : rhs = 'o%0o", name, lhs&mask, rhs&mask); end UVM_DEC: begin $swrite(msg, "%s: lhs = %0d : rhs = %0d", name, lhs&mask, rhs&mask); end UVM_TIME: begin $swrite(msg, "%s: lhs = %0t : rhs = %0t", name, lhs&mask, rhs&mask); end UVM_STRING: begin $swrite(msg, "%s: lhs = %0s : rhs = %0s", name, lhs&mask, rhs&mask); end UVM_ENUM: begin $swrite(msg, "%s: lhs = %0d : rhs = %0d", name, lhs&mask, rhs&mask); end default: begin $swrite(msg, "%s: lhs = 'h%0x : rhs = 'h%0x", name, lhs&mask, rhs&mask); end endcase print_msg(msg); return 0; end return 1; endfunction virtual function bit compare_field_int (string name, uvm_integral_t lhs, uvm_integral_t rhs, int size, uvm_radix_enum radix=UVM_NORADIX); logic [63:0] mask; string msg; mask = -1; mask >>= (64-size); if((lhs & mask) !== (rhs & mask)) begin case (radix) UVM_BIN: begin $swrite(msg, "%s: lhs = 'b%0b : rhs = 'b%0b", name, lhs&mask, rhs&mask); end UVM_OCT: begin $swrite(msg, "%s: lhs = 'o%0o : rhs = 'o%0o", name, lhs&mask, rhs&mask); end UVM_DEC: begin $swrite(msg, "%s: lhs = %0d : rhs = %0d", name, lhs&mask, rhs&mask); end UVM_TIME: begin $swrite(msg, "%s: lhs = %0t : rhs = %0t", name, lhs&mask, rhs&mask); end UVM_STRING: begin $swrite(msg, "%s: lhs = %0s : rhs = %0s", name, lhs&mask, rhs&mask); end UVM_ENUM: begin $swrite(msg, "%s: lhs = %0d : rhs = %0d", name, lhs&mask, rhs&mask); end default: begin $swrite(msg, "%s: lhs = 'h%0x : rhs = 'h%0x", name, lhs&mask, rhs&mask); end endcase print_msg(msg); return 0; end return 1; endfunction virtual function bit compare_field_real (string name, real lhs, real rhs); string msg; if(lhs != rhs) begin $swrite(msg, name, ": lhs = ", lhs, " : rhs = ", rhs); print_msg(msg); return 0; end return 1; endfunction local string m_object_names[$]; local function string m_current_context(string name=""); if (m_object_names.size() == 0) return name; else if ((m_object_names.size() == 1) && (name=="")) return m_object_names[0]; else begin string full_name; foreach(m_object_names[i]) begin if (i == m_object_names.size() - 1) full_name = {full_name, m_object_names[i]}; else full_name = {full_name, m_object_names[i], "."}; end if (name != "") return {full_name, ".", name}; else return full_name; end endfunction : m_current_context virtual function bit compare_object (string name, uvm_object lhs, uvm_object rhs); int old_result ; uvm_field_op field_op ; uvm_policy::recursion_state_e prev_state; bit ret_val = 1; if (rhs == lhs) return ret_val; m_object_names.push_back(name); if (policy == UVM_REFERENCE && lhs != rhs) begin print_msg_object(lhs, rhs); ret_val = 0; end if (ret_val && (rhs == null || lhs == null)) begin print_msg_object(lhs, rhs); ret_val = 0; end if (ret_val) begin prev_state = object_compared(lhs,rhs,get_recursion_policy(),ret_val); if (prev_state != uvm_policy::NEVER) begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/COPIER/LOOP")) uvm_report_warning ("UVM/COPIER/LOOP", {"Possible loop when comparing '", lhs.get_full_name(), "' to '", rhs.get_full_name(), "'"}, UVM_NONE, "t/uvm/src/base/uvm_comparer.svh", 465, "", 1); end push_active_object(lhs); m_recur_states[lhs][rhs][get_recursion_policy()] = '{uvm_policy::STARTED,0}; old_result = get_result(); if (get_check_type() && (lhs.get_object_type() != rhs.get_object_type())) begin if(lhs.get_type_name() != rhs.get_type_name()) begin print_msg({"type: lhs = \"", lhs.get_type_name(), "\" : rhs = \"", rhs.get_type_name(), "\""}); end else begin print_msg({"get_object_type() for ",lhs.get_name()," does not match get_object_type() for ",rhs.get_name()}); end end field_op = uvm_field_op::m_get_available_op(); field_op.set(UVM_COMPARE,this,rhs); lhs.do_execute_op(field_op); if (field_op.user_hook_enabled()) begin ret_val = lhs.do_compare(rhs,this); end field_op.m_recycle(); if (ret_val && (get_result() > old_result)) ret_val = 0; m_recur_states[lhs][rhs][get_recursion_policy()] = '{uvm_policy::FINISHED,ret_val}; void'(pop_active_object()); end void'(m_object_names.pop_back()); if (!ret_val && (get_active_object_depth() == 0)) begin string msg ; if(get_result()) begin if (get_show_max() && (get_show_max() < get_result())) $swrite(msg, "%0d Miscompare(s) (%0d shown) for object ", result, show_max); else $swrite(msg, "%0d Miscompare(s) for object ", result); end uvm_pkg::uvm_report(sev, "MISCMP", $sformatf("%s%s@%0d vs. %s@%0d", msg, (lhs == null) ? "" : lhs.get_name(), (lhs == null) ? 0 : lhs.get_inst_id(), (rhs == null) ? "" : rhs.get_name(), (rhs == null) ? 0 : rhs.get_inst_id()), get_verbosity(), "t/uvm/src/base/uvm_comparer.svh", 525); end return ret_val; endfunction virtual function bit compare_string (string name, string lhs, string rhs); string msg; if(lhs != rhs) begin msg = { name, ": lhs = \"", lhs, "\" : rhs = \"", rhs, "\""}; print_msg(msg); return 0; end return 1; endfunction function void print_msg (string msg); string tmp = m_current_context(msg); result++; if((get_show_max() == 0) || (get_result() <= get_show_max())) begin msg = {"Miscompare for ", tmp}; uvm_pkg::uvm_report(sev, "MISCMP", msg, get_verbosity(), "t/uvm/src/base/uvm_comparer.svh", 573); end miscompares = { miscompares, tmp, "\n" }; endfunction function void print_msg_object(uvm_object lhs, uvm_object rhs); string tmp = $sformatf("%s: lhs = @%0d : rhs = @%0d", m_current_context(), (lhs != null ? lhs.get_inst_id() : 0), (rhs != null ? rhs.get_inst_id() : 0)); result++; if((get_show_max() == 0) || (get_result() <= get_show_max())) begin uvm_pkg::uvm_report(sev, "MISCMP", {"Miscompare for ", tmp}, get_verbosity(), "t/uvm/src/base/uvm_comparer.svh", 599); end miscompares = { miscompares, tmp, "\n" }; endfunction int depth; bit compare_map[uvm_object][uvm_object]; endclass function void uvm_comparer::flush(); miscompares = "" ; check_type = 1 ; result = 0 ; m_recur_states.delete(); endfunction function uvm_policy::recursion_state_e uvm_comparer::object_compared( uvm_object lhs, uvm_object rhs, uvm_recursion_policy_enum recursion, output bit ret_val ); if (!m_recur_states.exists(lhs)) return NEVER ; else if (!m_recur_states[lhs].exists(rhs)) return NEVER ; else if (!m_recur_states[lhs][rhs].exists(recursion)) return NEVER ; else begin if (m_recur_states[lhs][rhs][recursion].state == FINISHED) ret_val = m_recur_states[lhs][rhs][recursion].ret_val; return m_recur_states[lhs][rhs][recursion].state ; end endfunction function string uvm_comparer::get_miscompares(); return miscompares ; endfunction function int unsigned uvm_comparer::get_result(); return result ; endfunction function void uvm_comparer::set_result(int unsigned result); this.result = result ; endfunction function void uvm_comparer::set_recursion_policy( uvm_recursion_policy_enum policy); this.policy = policy ; endfunction function uvm_recursion_policy_enum uvm_comparer::get_recursion_policy(); return policy ; endfunction function void uvm_comparer::set_check_type( bit enabled ); check_type = enabled ; endfunction function bit uvm_comparer::get_check_type(); return check_type ; endfunction function void uvm_comparer::set_show_max (int unsigned show_max); this.show_max = show_max ; endfunction function int unsigned uvm_comparer::get_show_max(); return show_max ; endfunction function void uvm_comparer::set_verbosity (int unsigned verbosity); this.verbosity = verbosity ; endfunction function int unsigned uvm_comparer::get_verbosity(); return verbosity ; endfunction function void uvm_comparer::set_severity (uvm_severity severity); sev = severity ; endfunction function uvm_severity uvm_comparer::get_severity(); return sev ; endfunction function void uvm_comparer::set_threshold (int unsigned threshold); m_threshold = threshold; endfunction function int unsigned uvm_comparer::get_threshold(); return m_threshold; endfunction typedef bit signed [(4096*8)-1:0] uvm_pack_bitstream_t; class uvm_packer extends uvm_policy; typedef uvm_object_registry#(uvm_packer,"uvm_packer") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_packer tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_packer"; endfunction : type_name virtual function string get_type_name(); return "uvm_packer"; endfunction : get_type_name uvm_factory m_factory; local uvm_object m_object_references[int]; extern virtual function void set_packed_bits (ref bit unsigned stream[]); extern virtual function void set_packed_bytes (ref byte unsigned stream[]); extern virtual function void set_packed_ints (ref int unsigned stream[]); extern virtual function void set_packed_longints (ref longint unsigned stream[]); extern virtual function void get_packed_bits (ref bit unsigned stream[]); extern virtual function void get_packed_bytes (ref byte unsigned stream[]); extern virtual function void get_packed_ints (ref int unsigned stream[]); extern virtual function void get_packed_longints (ref longint unsigned stream[]); static function void set_default (uvm_packer packer) ; uvm_coreservice_t coreservice ; coreservice = uvm_coreservice_t::get() ; coreservice.set_default_packer(packer) ; endfunction static function uvm_packer get_default () ; uvm_coreservice_t coreservice ; coreservice = uvm_coreservice_t::get() ; return coreservice.get_default_packer() ; endfunction extern virtual function void flush (); extern virtual function void pack_field (uvm_bitstream_t value, int size); extern function new(string name=""); extern virtual function void pack_field_int (uvm_integral_t value, int size); extern virtual function void pack_bits(ref bit value[], input int size = -1); extern virtual function void pack_bytes(ref byte value[], input int size = -1); extern virtual function void pack_ints(ref int value[], input int size = -1); extern virtual function void pack_string (string value); extern virtual function void pack_time (time value); extern virtual function void pack_real (real value); extern virtual function void pack_object (uvm_object value); extern virtual function void pack_object_with_meta (uvm_object value); extern virtual function void pack_object_wrapper (uvm_object_wrapper value); extern virtual function bit is_null (); extern virtual function bit is_object_wrapper(); extern virtual function uvm_bitstream_t unpack_field (int size); extern virtual function uvm_integral_t unpack_field_int (int size); extern virtual function void unpack_bits(ref bit value[], input int size = -1); extern virtual function void unpack_bytes(ref byte value[], input int size = -1); extern virtual function void unpack_ints(ref int value[], input int size = -1); extern virtual function string unpack_string (); extern virtual function time unpack_time (); extern virtual function real unpack_real (); extern virtual function void unpack_object (uvm_object value); extern virtual function void unpack_object_with_meta (inout uvm_object value); extern virtual function uvm_object_wrapper unpack_object_wrapper(); extern virtual function int get_packed_size(); static bit bitstream[]; static bit fabitstream[]; int m_pack_iter; int m_unpack_iter; bit reverse_order; byte byte_size = 8; int word_size = 16; bit nopack; uvm_pack_bitstream_t m_bits; extern function void index_error(int index, string id, int sz); extern function bit enough_bits(int needed, string id); endclass function void uvm_packer::index_error(int index, string id, int sz); uvm_report_error("PCKIDX", $sformatf("index %0d for get_%0s too large; valid index range is 0-%0d.", index,id,((m_pack_iter+sz-1)/sz)-1), UVM_NONE); endfunction function bit uvm_packer::enough_bits(int needed, string id); if ((m_pack_iter - m_unpack_iter) < needed) begin uvm_report_error("PCKSZ", $sformatf("%0d bits needed to unpack %0s, yet only %0d available.", needed, id, (m_pack_iter - m_unpack_iter)), UVM_NONE); return 0; end return 1; endfunction function int uvm_packer::get_packed_size(); return m_pack_iter - m_unpack_iter; endfunction function void uvm_packer::flush(); m_pack_iter = 64; m_unpack_iter = 64; m_bits = 0; m_object_references.delete(); m_object_references[0] = null; m_factory = null; super.flush(); endfunction : flush function void uvm_packer::get_packed_bits(ref bit unsigned stream[]); stream = new[m_pack_iter]; m_bits[31:0] = m_pack_iter; m_bits[63:32] = m_unpack_iter; for (int i=0;i> ($bits(T)-(m_pack_iter%$bits(T)))); \ stream[i] = v; \ end \ endfunction function void uvm_packer::get_packed_bytes (ref byte unsigned stream[] ); int sz; byte v; sz = (m_pack_iter + $high(v)) / $bits(byte); m_bits[31:0] = m_pack_iter; m_bits[63:32] = m_unpack_iter; stream = new[sz]; foreach (stream[i]) begin if (i != sz-1 || (m_pack_iter % $bits(byte)) == 0) v = m_bits[ i* $bits(byte) +: $bits(byte) ]; else v = m_bits[ i* $bits(byte) +: $bits(byte) ] & ({$bits(byte){1'b1}} >> ($bits(byte)-(m_pack_iter%$bits(byte)))); stream[i] = v; end endfunction function void uvm_packer::get_packed_ints (ref int unsigned stream[] ); int sz; int v; sz = (m_pack_iter + $high(v)) / $bits(int); m_bits[31:0] = m_pack_iter; m_bits[63:32] = m_unpack_iter; stream = new[sz]; foreach (stream[i]) begin if (i != sz-1 || (m_pack_iter % $bits(int)) == 0) v = m_bits[ i* $bits(int) +: $bits(int) ]; else v = m_bits[ i* $bits(int) +: $bits(int) ] & ({$bits(int){1'b1}} >> ($bits(int)-(m_pack_iter%$bits(int)))); stream[i] = v; end endfunction function void uvm_packer::get_packed_longints (ref longint unsigned stream[] ); int sz; longint v; sz = (m_pack_iter + $high(v)) / $bits(longint); m_bits[31:0] = m_pack_iter; m_bits[63:32] = m_unpack_iter; stream = new[sz]; foreach (stream[i]) begin if (i != sz-1 || (m_pack_iter % $bits(longint)) == 0) v = m_bits[ i* $bits(longint) +: $bits(longint) ]; else v = m_bits[ i* $bits(longint) +: $bits(longint) ] & ({$bits(longint){1'b1}} >> ($bits(longint)-(m_pack_iter%$bits(longint)))); stream[i] = v; end endfunction `undef M__UVM_GET_PACKED function void uvm_packer::set_packed_bits (ref bit stream []); int bit_size; bit_size = stream.size(); for (int i=0;i value.size()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/BASE/PACKER/BAD_SIZE")) uvm_report_error ("UVM/BASE/PACKER/BAD_SIZE", $sformatf("pack_bits called with size '%0d', which exceeds value.size() of '%0d'", size, value.size()), UVM_NONE, "t/uvm/src/base/uvm_packer.svh", 797, "", 1); end return; end for (int i=0; i max_size) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/BASE/PACKER/BAD_SIZE")) uvm_report_error ("UVM/BASE/PACKER/BAD_SIZE", $sformatf("pack_bytes called with size '%0d', which exceeds value size of '%0d'", size, max_size), UVM_NONE, "t/uvm/src/base/uvm_packer.svh", 824, "", 1); end return; end else begin int idx_select; for (int i=0; i max_size) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/BASE/PACKER/BAD_SIZE")) uvm_report_error ("UVM/BASE/PACKER/BAD_SIZE", $sformatf("pack_ints called with size '%0d', which exceeds value size of '%0d'", size, max_size), UVM_NONE, "t/uvm/src/base/uvm_packer.svh", 858, "", 1); end return; end else begin int idx_select; for (int i=0; i value.size()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/BASE/PACKER/BAD_SIZE")) uvm_report_error ("UVM/BASE/PACKER/BAD_SIZE", $sformatf("unpack_bits called with size '%0d', which exceeds value.size() of '%0d'", size, value.size()), UVM_NONE, "t/uvm/src/base/uvm_packer.svh", 1076, "", 1); end return; end if (enough_bits(size, "integral")) begin m_unpack_iter += size; for (int i=0; i max_size) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/BASE/PACKER/BAD_SIZE")) uvm_report_error ("UVM/BASE/PACKER/BAD_SIZE", $sformatf("unpack_bytes called with size '%0d', which exceeds value size of '%0d'", size, value.size()), UVM_NONE, "t/uvm/src/base/uvm_packer.svh", 1104, "", 1); end return; end else begin if (enough_bits(size, "integral")) begin m_unpack_iter += size; for (int i=0; i max_size) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/BASE/PACKER/BAD_SIZE")) uvm_report_error ("UVM/BASE/PACKER/BAD_SIZE", $sformatf("unpack_ints called with size '%0d', which exceeds value size of '%0d'", size, value.size()), UVM_NONE, "t/uvm/src/base/uvm_packer.svh", 1136, "", 1); end return; end else begin if (enough_bits(size, "integral")) begin m_unpack_iter += size; for (int i=0; i' is not supported in links for 'uvm_tr_database'", UVM_NONE, "t/uvm/src/base/uvm_tr_database.svh", 158, "", 1); end return; end if (rhs == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/TR_DB/BAD_LINK")) uvm_report_warning ("UVM/TR_DB/BAD_LINK", "right hand side '' is not supported in links for 'uvm_tr_database'", UVM_NONE, "t/uvm/src/base/uvm_tr_database.svh", 163, "", 1); end return; end if (!$cast(s_lhs, lhs) && !$cast(r_lhs, lhs)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/TR_DB/BAD_LINK")) uvm_report_warning ("UVM/TR_DB/BAD_LINK", $sformatf("left hand side of type '%s' not supported in links for 'uvm_tr_database'", lhs.get_type_name()), UVM_NONE, "t/uvm/src/base/uvm_tr_database.svh", 171, "", 1); end return; end if (!$cast(s_rhs, rhs) && !$cast(r_rhs, rhs)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/TR_DB/BAD_LINK")) uvm_report_warning ("UVM/TR_DB/BAD_LINK", $sformatf("right hand side of type '%s' not supported in links for 'uvm_record_datbasae'", rhs.get_type_name()), UVM_NONE, "t/uvm/src/base/uvm_tr_database.svh", 178, "", 1); end return; end if (r_lhs != null) begin s_lhs = r_lhs.get_stream(); end if (r_rhs != null) begin s_rhs = r_rhs.get_stream(); end if ((s_lhs != null) && (s_lhs.get_db() != this)) begin db = s_lhs.get_db(); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/TR_DB/BAD_LINK")) uvm_report_warning ("UVM/TR_DB/BAD_LINK", $sformatf("attempt to link stream from '%s' into '%s'", db.get_name(), this.get_name()), UVM_NONE, "t/uvm/src/base/uvm_tr_database.svh", 193, "", 1); end return; end if ((s_rhs != null) && (s_rhs.get_db() != this)) begin db = s_rhs.get_db(); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/TR_DB/BAD_LINK")) uvm_report_warning ("UVM/TR_DB/BAD_LINK", $sformatf("attempt to link stream from '%s' into '%s'", db.get_name(), this.get_name()), UVM_NONE, "t/uvm/src/base/uvm_tr_database.svh", 200, "", 1); end return; end do_establish_link(link); endfunction : establish_link pure virtual protected function bit do_open_db(); pure virtual protected function bit do_close_db(); pure virtual protected function uvm_tr_stream do_open_stream(string name, string scope, string type_name); pure virtual protected function void do_establish_link(uvm_link_base link); endclass : uvm_tr_database typedef class uvm_recorder; typedef class uvm_tr_stream; typedef class uvm_link_base; typedef class uvm_simple_lock_dap; typedef class uvm_text_tr_stream; class uvm_text_tr_database extends uvm_tr_database; local uvm_simple_lock_dap#(string) m_filename_dap; UVM_FILE m_file; typedef uvm_object_registry#(uvm_text_tr_database,"uvm_text_tr_database") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_text_tr_database tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_text_tr_database"; endfunction : type_name virtual function string get_type_name(); return "uvm_text_tr_database"; endfunction : get_type_name function new(string name="unnamed-uvm_text_tr_database"); super.new(name); m_filename_dap = new("filename_dap"); m_filename_dap.set("tr_db.log"); endfunction : new protected virtual function bit do_open_db(); if (m_file == 0) begin m_file = $fopen(m_filename_dap.get(), "a+"); if (m_file != 0) m_filename_dap.lock(); end return (m_file != 0); endfunction : do_open_db protected virtual function bit do_close_db(); if (m_file != 0) begin fork $fclose(m_file); join_none m_filename_dap.unlock(); end return 1; endfunction : do_close_db protected virtual function uvm_tr_stream do_open_stream(string name, string scope, string type_name); uvm_text_tr_stream m_stream = uvm_text_tr_stream::type_id::create(name); return m_stream; endfunction : do_open_stream protected virtual function void do_establish_link(uvm_link_base link); uvm_recorder r_lhs, r_rhs; uvm_object lhs = link.get_lhs(); uvm_object rhs = link.get_rhs(); void'($cast(r_lhs, lhs)); void'($cast(r_rhs, rhs)); if ((r_lhs == null) || (r_rhs == null)) return; else begin uvm_parent_child_link pc_link; uvm_related_link re_link; if ($cast(pc_link, link)) begin $fdisplay(m_file," LINK @%0t {TXH1:%0d TXH2:%0d RELATION=%0s}", $time, r_lhs.get_handle(), r_rhs.get_handle(), "child"); end else if ($cast(re_link, link)) begin $fdisplay(m_file," LINK @%0t {TXH1:%0d TXH2:%0d RELATION=%0s}", $time, r_lhs.get_handle(), r_rhs.get_handle(), ""); end end endfunction : do_establish_link function void set_file_name(string filename); if (filename == "") begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/TXT_DB/EMPTY_NAME")) uvm_report_warning ("UVM/TXT_DB/EMPTY_NAME", "Ignoring attempt to set file name to ''!", UVM_NONE, "t/uvm/src/base/uvm_text_tr_database.svh", 191, "", 1); end return; end if (!m_filename_dap.try_set(filename)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/TXT_DB/SET_AFTER_OPEN")) uvm_report_warning ("UVM/TXT_DB/SET_AFTER_OPEN", "Ignoring attempt to change file name after opening the db!", UVM_NONE, "t/uvm/src/base/uvm_text_tr_database.svh", 197, "", 1); end return; end endfunction : set_file_name endclass : uvm_text_tr_database class m_uvm_tr_stream_cfg; uvm_tr_database db; string scope; string stream_type_name; endclass : m_uvm_tr_stream_cfg typedef class uvm_set_before_get_dap; typedef class uvm_text_recorder; virtual class uvm_tr_stream extends uvm_object; local uvm_set_before_get_dap#(m_uvm_tr_stream_cfg) m_cfg_dap; local bit m_records[uvm_recorder]; local bit m_warn_null_cfg; local bit m_is_opened; local bit m_is_closed; function new(string name="unnamed-uvm_tr_stream"); super.new(name); m_cfg_dap = new("cfg_dap"); endfunction : new local static int m_ids_by_stream[uvm_tr_stream]; function uvm_tr_database get_db(); m_uvm_tr_stream_cfg m_cfg; if (!m_cfg_dap.try_get(m_cfg)) begin if (m_warn_null_cfg == 1) begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/REC_STR/NO_CFG")) uvm_report_warning ("UVM/REC_STR/NO_CFG", $sformatf("attempt to retrieve DB from '%s' before it was set!", get_name()), UVM_NONE, "t/uvm/src/base/uvm_tr_stream.svh", 94, "", 1); end m_warn_null_cfg = 0; return null; end return m_cfg.db; endfunction : get_db function string get_scope(); m_uvm_tr_stream_cfg m_cfg; if (!m_cfg_dap.try_get(m_cfg)) begin if (m_warn_null_cfg == 1) begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/REC_STR/NO_CFG")) uvm_report_warning ("UVM/REC_STR/NO_CFG", $sformatf("attempt to retrieve scope from '%s' before it was set!", get_name()), UVM_NONE, "t/uvm/src/base/uvm_tr_stream.svh", 109, "", 1); end m_warn_null_cfg = 0; return ""; end return m_cfg.scope; endfunction : get_scope function string get_stream_type_name(); m_uvm_tr_stream_cfg m_cfg; if (!m_cfg_dap.try_get(m_cfg)) begin if (m_warn_null_cfg == 1) begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/REC_STR/NO_CFG")) uvm_report_warning ("UVM/REC_STR/NO_CFG", $sformatf("attempt to retrieve STREAM_TYPE_NAME from '%s' before it was set!", get_name()), UVM_NONE, "t/uvm/src/base/uvm_tr_stream.svh", 124, "", 1); end m_warn_null_cfg = 0; return ""; end return m_cfg.stream_type_name; endfunction : get_stream_type_name function void close(); if (!is_open()) return; do_close(); foreach (m_records[idx]) if (idx.is_open()) idx.close(); m_is_opened = 0; m_is_closed = 1; endfunction : close function void free(); process p; string s; uvm_tr_database db; if (!is_open() && !is_closed()) return; if (is_open()) close(); do_free(); foreach (m_records[idx]) idx.free(); db = get_db(); m_is_closed = 0; p = process::self(); if(p != null) s = p.get_randstate(); m_cfg_dap = new("cfg_dap"); if(p != null) p.set_randstate(s); m_warn_null_cfg = 1; if (m_ids_by_stream.exists(this)) m_free_id(m_ids_by_stream[this]); if (db != null) db.m_free_stream(this); endfunction : free function void m_do_open(uvm_tr_database db, string scope="", string stream_type_name=""); m_uvm_tr_stream_cfg m_cfg; uvm_tr_database m_db; if (db == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/REC_STR/NULL_DB")) uvm_report_error ("UVM/REC_STR/NULL_DB", $sformatf("Illegal attempt to set DB for '%s' to ''", this.get_full_name()), UVM_NONE, "t/uvm/src/base/uvm_tr_stream.svh", 217, "", 1); end return; end if (m_cfg_dap.try_get(m_cfg)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/REC_STR/RE_CFG")) uvm_report_error ("UVM/REC_STR/RE_CFG", $sformatf("Illegal attempt to re-open '%s'", this.get_full_name()), UVM_NONE, "t/uvm/src/base/uvm_tr_stream.svh", 224, "", 1); end end else begin m_cfg = new(); m_cfg.db = db; m_cfg.scope = scope; m_cfg.stream_type_name = stream_type_name; m_cfg_dap.set(m_cfg); m_is_opened = 1; do_open(db, scope, stream_type_name); end endfunction : m_do_open function bit is_open(); return m_is_opened; endfunction : is_open function bit is_closed(); return m_is_closed; endfunction : is_closed function uvm_recorder open_recorder(string name, time open_time = 0, string type_name=""); time m_time = (open_time == 0) ? $time : open_time; if (!is_open()) return null; else begin process p = process::self(); string s; if (p != null) s = p.get_randstate(); open_recorder = do_open_recorder(name, m_time, type_name); if (open_recorder != null) begin m_records[open_recorder] = 1; open_recorder.m_do_open(this, m_time, type_name); end if (p != null) p.set_randstate(s); end endfunction : open_recorder function void m_free_recorder(uvm_recorder recorder); if (m_records.exists(recorder)) m_records.delete(recorder); endfunction : m_free_recorder function unsigned get_recorders(ref uvm_recorder q[$]); q.delete(); foreach (m_records[idx]) q.push_back(idx); return q.size(); endfunction : get_recorders local static uvm_tr_stream m_streams_by_id[int]; function int get_handle(); if (!is_open() && !is_closed()) begin return 0; end else begin int handle = get_inst_id(); if (m_ids_by_stream.exists(this) && m_ids_by_stream[this] != handle) m_streams_by_id.delete(m_ids_by_stream[this]); m_streams_by_id[handle] = this; m_ids_by_stream[this] = handle; return handle; end endfunction : get_handle static function uvm_tr_stream get_stream_from_handle(int id); if (id == 0) return null; if ($isunknown(id) || !m_streams_by_id.exists(id)) return null; return m_streams_by_id[id]; endfunction : get_stream_from_handle static function void m_free_id(int id); uvm_tr_stream stream; if (!$isunknown(id) && m_streams_by_id.exists(id)) stream = m_streams_by_id[id]; if (stream != null) begin m_streams_by_id.delete(id); m_ids_by_stream.delete(stream); end endfunction : m_free_id protected virtual function void do_open(uvm_tr_database db, string scope, string stream_type_name); endfunction : do_open protected virtual function void do_close(); endfunction : do_close protected virtual function void do_free(); endfunction : do_free protected virtual function uvm_recorder do_open_recorder(string name, time open_time, string type_name); return null; endfunction : do_open_recorder endclass : uvm_tr_stream class uvm_text_tr_stream extends uvm_tr_stream; local uvm_text_tr_database m_text_db; typedef uvm_object_registry#(uvm_text_tr_stream,"uvm_text_tr_stream") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_text_tr_stream tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_text_tr_stream"; endfunction : type_name virtual function string get_type_name(); return "uvm_text_tr_stream"; endfunction : get_type_name function void do_execute_op( uvm_field_op op ); super.do_execute_op(op); __m_uvm_execute_field_op(op); endfunction : do_execute_op local function void __m_uvm_execute_field_op( uvm_field_op __local_op__ ); uvm_field_flag_t local_op_type__; uvm_text_tr_stream local_rhs__; uvm_resource_base local_rsrc__; string local_rsrc_name__; uvm_object local_obj__; bit local_success__; typedef uvm_text_tr_stream __local_type__; int local_size__; uvm_printer __local_printer__; uvm_comparer __local_comparer__; uvm_recorder __local_recorder__; uvm_packer __local_packer__; uvm_copier __local_copier__; void'($cast(local_rhs__, __local_op__.get_rhs())); if (($cast(local_rsrc__, __local_op__.get_rhs())) && (local_rsrc__ != null)) local_rsrc_name__ = local_rsrc__.get_name(); local_op_type__ = __local_op__.get_op_type(); case (local_op_type__) UVM_PRINT: begin $cast(__local_printer__, __local_op__.get_policy()); end UVM_COMPARE: begin if (local_rhs__ == null) return; $cast(__local_comparer__, __local_op__.get_policy()); end UVM_RECORD: begin $cast(__local_recorder__, __local_op__.get_policy()); end UVM_PACK, UVM_UNPACK: begin $cast(__local_packer__, __local_op__.get_policy()); end UVM_COPY: begin if (local_rhs__ == null) return; $cast(__local_copier__, __local_op__.get_policy()); end UVM_SET: begin if (local_rsrc__ == null) return; end default: return; endcase endfunction : __m_uvm_execute_field_op function new(string name="unnamed-uvm_text_tr_stream"); super.new(name); endfunction : new protected virtual function void do_open(uvm_tr_database db, string scope, string stream_type_name); $cast(m_text_db, db); if (m_text_db.open_db()) $fdisplay(m_text_db.m_file, " CREATE_STREAM @%0t {NAME:%s T:%s SCOPE:%s STREAM:%0d}", $time, this.get_name(), stream_type_name, scope, this.get_handle()); endfunction : do_open protected virtual function void do_close(); if (m_text_db.open_db()) $fdisplay(m_text_db.m_file, " CLOSE_STREAM @%0t {NAME:%s T:%s SCOPE:%s STREAM:%0d}", $time, this.get_name(), this.get_stream_type_name(), this.get_scope(), this.get_handle()); endfunction : do_close protected virtual function void do_free(); if (m_text_db.open_db()) $fdisplay(m_text_db.m_file, " FREE_STREAM @%0t {NAME:%s T:%s SCOPE:%s STREAM:%0d}", $time, this.get_name(), this.get_stream_type_name(), this.get_scope(), this.get_handle()); m_text_db = null; return; endfunction : do_free protected virtual function uvm_recorder do_open_recorder(string name, time open_time, string type_name); if (m_text_db.open_db()) begin return uvm_text_recorder::type_id::create(name); end return null; endfunction : do_open_recorder endclass : uvm_text_tr_stream typedef class uvm_report_message; virtual class uvm_recorder extends uvm_policy; typedef uvm_abstract_object_registry#(uvm_recorder,"uvm_recorder") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_recorder"; endfunction : type_name virtual function string get_type_name(); return "uvm_recorder"; endfunction : get_type_name local uvm_set_before_get_dap#(uvm_tr_stream) m_stream_dap; local bit m_warn_null_stream; local bit m_is_opened; local bit m_is_closed; local time m_open_time; local time m_close_time; int recording_depth; uvm_radix_enum default_radix = UVM_HEX; bit identifier = 1; local uvm_recursion_policy_enum policy = UVM_DEFAULT_POLICY; virtual function void set_recursion_policy(uvm_recursion_policy_enum policy); this.policy = policy; endfunction : set_recursion_policy virtual function uvm_recursion_policy_enum get_recursion_policy(); return this.policy; endfunction : get_recursion_policy virtual function void flush(); policy = UVM_DEFAULT_POLICY; identifier = 1; free(); endfunction : flush local static int m_ids_by_recorder[uvm_recorder]; function new(string name = "uvm_recorder"); super.new(name); m_stream_dap = new("stream_dap"); m_warn_null_stream = 1; endfunction function uvm_tr_stream get_stream(); if (!m_stream_dap.try_get(get_stream)) begin if (m_warn_null_stream == 1) begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/REC/NO_CFG")) uvm_report_warning ("UVM/REC/NO_CFG", $sformatf("attempt to retrieve STREAM from '%s' before it was set!", get_name()), UVM_NONE, "t/uvm/src/base/uvm_recorder.svh", 178, "", 1); end m_warn_null_stream = 0; end endfunction : get_stream function void close(time close_time = 0); if (close_time == 0) close_time = $realtime; if (!is_open()) return; do_close(close_time); m_is_opened = 0; m_is_closed = 1; m_close_time = close_time; endfunction : close function void free(time close_time = 0); process p=process::self(); string s; uvm_tr_stream stream; if (!is_open() && !is_closed()) return; if (is_open()) begin close(close_time); end do_free(); stream = get_stream(); m_is_closed = 0; if(p != null) s=p.get_randstate(); m_stream_dap = new("stream_dap"); if(p != null) p.set_randstate(s); m_warn_null_stream = 1; if (m_ids_by_recorder.exists(this)) m_free_id(m_ids_by_recorder[this]); if (stream != null) stream.m_free_recorder(this); endfunction : free function bit is_open(); return m_is_opened; endfunction : is_open function time get_open_time(); return m_open_time; endfunction : get_open_time function bit is_closed(); return m_is_closed; endfunction : is_closed function time get_close_time(); return m_close_time; endfunction : get_close_time function void m_do_open(uvm_tr_stream stream, time open_time, string type_name); uvm_tr_stream m_stream; if (stream == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/REC/NULL_STREAM")) uvm_report_error ("UVM/REC/NULL_STREAM", $sformatf("Illegal attempt to set STREAM for '%s' to ''", this.get_name()), UVM_NONE, "t/uvm/src/base/uvm_recorder.svh", 287, "", 1); end return; end if (m_stream_dap.try_get(m_stream)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/REC/RE_INIT")) uvm_report_error ("UVM/REC/RE_INIT", $sformatf("Illegal attempt to re-initialize '%s'", this.get_name()), UVM_NONE, "t/uvm/src/base/uvm_recorder.svh", 294, "", 1); end return; end m_stream_dap.set(stream); m_open_time = open_time; m_is_opened = 1; do_open(stream, open_time, type_name); endfunction : m_do_open local static uvm_recorder m_recorders_by_id[int]; local static int m_id; static function void m_free_id(int id); uvm_recorder recorder; if ((!$isunknown(id)) && (m_recorders_by_id.exists(id))) recorder = m_recorders_by_id[id]; if (recorder != null) begin m_recorders_by_id.delete(id); m_ids_by_recorder.delete(recorder); end endfunction : m_free_id function int get_handle(); if (!is_open() && !is_closed()) begin return 0; end else begin int handle = get_inst_id(); if (m_ids_by_recorder.exists(this) && m_ids_by_recorder[this] != handle) m_recorders_by_id.delete(m_ids_by_recorder[this]); m_recorders_by_id[handle] = this; m_ids_by_recorder[this] = handle; return handle; end endfunction : get_handle static function uvm_recorder get_recorder_from_handle(int id); if (id == 0) return null; if (($isunknown(id)) || (!m_recorders_by_id.exists(id))) return null; return m_recorders_by_id[id]; endfunction : get_recorder_from_handle function void record_field(string name, uvm_bitstream_t value, int size, uvm_radix_enum radix=UVM_NORADIX); if (get_stream() == null) begin return; end do_record_field(name, value, size, radix); endfunction : record_field function void record_field_int(string name, uvm_integral_t value, int size, uvm_radix_enum radix=UVM_NORADIX); if (get_stream() == null) begin return; end do_record_field_int(name, value, size, radix); endfunction : record_field_int function void record_field_real(string name, real value); if (get_stream() == null) begin return; end do_record_field_real(name, value); endfunction : record_field_real function void record_object(string name, uvm_object value); if (get_stream() == null) begin return; end if (value == null) do_record_object(name, value); else begin push_active_object(value); do_record_object(name, value); void'(pop_active_object()); end endfunction : record_object function void record_string(string name, string value); if (get_stream() == null) begin return; end do_record_string(name, value); endfunction : record_string function void record_time(string name, time value); if (get_stream() == null) begin return; end do_record_time(name, value); endfunction : record_time function void record_generic(string name, string value, string type_name=""); if (get_stream() == null) begin return; end do_record_generic(name, value, type_name); endfunction : record_generic virtual function bit use_record_attribute(); return 0; endfunction : use_record_attribute virtual function int get_record_attribute_handle(); return get_handle(); endfunction : get_record_attribute_handle protected virtual function void do_open(uvm_tr_stream stream, time open_time, string type_name); endfunction : do_open protected virtual function void do_close(time close_time); endfunction : do_close protected virtual function void do_free(); endfunction : do_free pure virtual protected function void do_record_field(string name, uvm_bitstream_t value, int size, uvm_radix_enum radix); pure virtual protected function void do_record_field_int(string name, uvm_integral_t value, int size, uvm_radix_enum radix); pure virtual protected function void do_record_field_real(string name, real value); virtual protected function void do_record_object(string name, uvm_object value); if ((get_recursion_policy() != UVM_REFERENCE) && (value != null)) begin uvm_field_op field_op = uvm_field_op::m_get_available_op(); field_op.set(UVM_RECORD, this, null); value.do_execute_op(field_op); if (field_op.user_hook_enabled()) value.do_record(this); field_op.m_recycle(); end endfunction : do_record_object pure virtual protected function void do_record_string(string name, string value); pure virtual protected function void do_record_time(string name, time value); pure virtual protected function void do_record_generic(string name, string value, string type_name); virtual function bit open_file(); return 0; endfunction virtual function int create_stream (string name, string t, string scope); return -1; endfunction virtual function void m_set_attribute (int txh, string nm, string value); endfunction virtual function void set_attribute (int txh, string nm, logic [1023:0] value, uvm_radix_enum radix, int numbits=1024); endfunction virtual function int check_handle_kind (string htype, int handle); return 0; endfunction virtual function int begin_tr(string txtype, int stream, string nm, string label="", string desc="", time begin_time=0); return -1; endfunction virtual function void end_tr (int handle, time end_time=0); endfunction virtual function void link_tr(int h1, int h2, string relation=""); endfunction virtual function void free_tr(int handle); endfunction endclass class uvm_text_recorder extends uvm_recorder; typedef uvm_object_registry#(uvm_text_recorder,"uvm_text_recorder") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_text_recorder tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_text_recorder"; endfunction : type_name virtual function string get_type_name(); return "uvm_text_recorder"; endfunction : get_type_name uvm_text_tr_database m_text_db; function new(string name="unnamed-uvm_text_recorder"); super.new(name); endfunction : new protected virtual function void do_open(uvm_tr_stream stream, time open_time, string type_name); $cast(m_text_db, stream.get_db()); if (m_text_db.open_db()) $fdisplay(m_text_db.m_file, " OPEN_RECORDER @%0t {TXH:%0d STREAM:%0d NAME:%s TIME:%0t TYPE=\"%0s\"}", $realtime, this.get_handle(), stream.get_handle(), this.get_name(), open_time, type_name); endfunction : do_open protected virtual function void do_close(time close_time); if (m_text_db.open_db()) begin $fdisplay(m_text_db.m_file, " CLOSE_RECORDER @%0t {TXH:%0d TIME=%0t}", $realtime, this.get_handle(), close_time); end endfunction : do_close protected virtual function void do_free(); if (m_text_db.open_db()) begin $fdisplay(m_text_db.m_file, " FREE_RECORDER @%0t {TXH:%0d}", $realtime, this.get_handle()); end m_text_db = null; endfunction : do_free protected virtual function void do_record_field(string name, uvm_bitstream_t value, int size, uvm_radix_enum radix); if (!radix) radix = default_radix; write_attribute(m_current_context(name), value, radix, size); endfunction : do_record_field protected virtual function void do_record_field_int(string name, uvm_integral_t value, int size, uvm_radix_enum radix); if (!radix) radix = default_radix; write_attribute_int(m_current_context(name), value, radix, size); endfunction : do_record_field_int protected virtual function void do_record_field_real(string name, real value); bit [63:0] ival = $realtobits(value); write_attribute_int(m_current_context(name), ival, UVM_REAL, 64); endfunction : do_record_field_real local string m_object_names[$]; local function string m_current_context(string name=""); if (m_object_names.size() == 0) return name; else if ((m_object_names.size() == 1) && (name=="")) return m_object_names[0]; else begin string full_name; foreach(m_object_names[i]) begin if (i == m_object_names.size() - 1) full_name = {full_name, m_object_names[i]}; else full_name = {full_name, m_object_names[i], "."}; end if (name != "") return {full_name, ".", name}; else return full_name; end endfunction : m_current_context protected virtual function void do_record_object(string name, uvm_object value); int v; string str; if(identifier) begin if(value != null) begin v = value.get_inst_id(); end write_attribute_int("inst_id", v, UVM_DEC, 32); end if (get_active_object_depth() > 1) m_object_names.push_back(name); super.do_record_object(name, value); if (get_active_object_depth() > 1) void'(m_object_names.pop_back()); endfunction : do_record_object protected virtual function void do_record_string(string name, string value); if (m_text_db.open_db()) begin $fdisplay(m_text_db.m_file, " SET_ATTR @%0t {TXH:%0d NAME:%s VALUE:%s RADIX:%s BITS=%0d}", $realtime, this.get_handle(), m_current_context(name), value, "UVM_STRING", 8+value.len()); end endfunction : do_record_string protected virtual function void do_record_time(string name, time value); write_attribute_int(m_current_context(name), value, UVM_TIME, 64); endfunction : do_record_time protected virtual function void do_record_generic(string name, string value, string type_name); write_attribute(m_current_context(name), uvm_string_to_bits(value), UVM_STRING, 8+value.len()); endfunction : do_record_generic function void write_attribute(string nm, uvm_bitstream_t value, uvm_radix_enum radix, int numbits=$bits(uvm_bitstream_t)); if (m_text_db.open_db()) begin $fdisplay(m_text_db.m_file, " SET_ATTR @%0t {TXH:%0d NAME:%s VALUE:%s RADIX:%s BITS=%0d}", $realtime, this.get_handle(), nm, uvm_bitstream_to_string(value, numbits, radix), radix.name(), numbits); end endfunction : write_attribute function void write_attribute_int(string nm, uvm_integral_t value, uvm_radix_enum radix, int numbits=$bits(uvm_bitstream_t)); if (m_text_db.open_db()) begin $fdisplay(m_text_db.m_file, " SET_ATTR @%0t {TXH:%0d NAME:%s VALUE:%s RADIX:%s BITS=%0d}", $realtime, this.get_handle(), nm, uvm_integral_to_string(value, numbits, radix), radix.name(), numbits); end endfunction : write_attribute_int string filename; bit filename_set; virtual function bit open_file(); if (!filename_set) begin m_text_db.set_file_name(filename); end return m_text_db.open_db(); endfunction virtual function int create_stream (string name, string t, string scope); uvm_text_tr_stream stream; if (open_file()) begin $cast(stream,m_text_db.open_stream(name, scope, t)); return stream.get_handle(); end return 0; endfunction virtual function void m_set_attribute (int txh, string nm, string value); if (open_file()) begin UVM_FILE file = m_text_db.m_file; $fdisplay(file," SET_ATTR @%0t {TXH:%0d NAME:%s VALUE:%s}", $realtime,txh,nm,value); end endfunction virtual function void set_attribute (int txh, string nm, logic [1023:0] value, uvm_radix_enum radix, int numbits=1024); if (open_file()) begin UVM_FILE file = m_text_db.m_file; $fdisplay(file, " SET_ATTR @%0t {TXH:%0d NAME:%s VALUE:%s RADIX:%s BITS=%0d}", $realtime, txh, nm, uvm_bitstream_to_string(value, numbits, radix), radix.name(), numbits); end endfunction virtual function int check_handle_kind (string htype, int handle); return ((uvm_recorder::get_recorder_from_handle(handle) != null) || (uvm_tr_stream::get_stream_from_handle(handle) != null)); endfunction virtual function int begin_tr(string txtype, int stream, string nm, string label="", string desc="", time begin_time=0); if (open_file()) begin uvm_tr_stream stream_obj = uvm_tr_stream::get_stream_from_handle(stream); uvm_recorder recorder; if (stream_obj == null) return -1; recorder = stream_obj.open_recorder(nm, begin_time, txtype); return recorder.get_handle(); end return -1; endfunction virtual function void end_tr (int handle, time end_time=0); if (open_file()) begin uvm_recorder record = uvm_recorder::get_recorder_from_handle(handle); if (record != null) begin record.close(end_time); end end endfunction virtual function void link_tr(int h1, int h2, string relation=""); if (open_file()) $fdisplay(m_text_db.m_file," LINK @%0t {TXH1:%0d TXH2:%0d RELATION=%0s}", $realtime,h1,h2,relation); endfunction virtual function void free_tr(int handle); if (open_file()) begin uvm_recorder record = uvm_recorder::get_recorder_from_handle(handle); if (record != null) begin record.free(); end end endfunction endclass : uvm_text_recorder typedef class uvm_object; typedef class uvm_event; typedef class uvm_callback; typedef class uvm_callbacks; virtual class uvm_event_callback#(type T=uvm_object) extends uvm_callback; function new (string name=""); super.new(name); endfunction virtual function bit pre_trigger (uvm_event#(T) e, T data); return 0; endfunction virtual function void post_trigger (uvm_event#(T) e, T data); return; endfunction virtual function uvm_object create (string name=""); return null; endfunction endclass virtual class uvm_event_base extends uvm_object; typedef uvm_abstract_object_registry#(uvm_event_base,"uvm_event_base") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_event_base"; endfunction : type_name virtual function string get_type_name(); return "uvm_event_base"; endfunction : get_type_name protected event m_event; protected int num_waiters; protected bit on; protected time trigger_time=0; function new (string name=""); super.new(name); endfunction virtual task wait_on (bit delta = 0); if (on) begin if (delta) #0; return; end num_waiters++; @on; endtask virtual task wait_off (bit delta = 0); if (!on) begin if (delta) #0; return; end num_waiters++; @on; endtask virtual task wait_trigger (); num_waiters++; @m_event; endtask virtual task wait_ptrigger (); if (m_event.triggered) return; num_waiters++; @m_event; endtask virtual function time get_trigger_time (); return trigger_time; endfunction virtual function bit is_on (); return (on == 1); endfunction virtual function bit is_off (); return (on == 0); endfunction virtual function void reset (bit wakeup = 0); event e; if (wakeup) ->m_event; m_event = e; num_waiters = 0; on = 0; trigger_time = 0; endfunction virtual function void cancel (); if (num_waiters > 0) num_waiters--; endfunction virtual function int get_num_waiters (); return num_waiters; endfunction virtual function void do_print (uvm_printer printer); printer.print_field_int("num_waiters", num_waiters, $bits(num_waiters), UVM_DEC, ".", "int"); printer.print_field_int("on", on, $bits(on), UVM_BIN, ".", "bit"); printer.print_time("trigger_time", trigger_time); endfunction virtual function void do_copy (uvm_object rhs); uvm_event_base e; super.do_copy(rhs); if(!$cast(e, rhs) || (e==null)) return; m_event = e.m_event; num_waiters = e.num_waiters; on = e.on; trigger_time = e.trigger_time; endfunction endclass class uvm_event#(type T=uvm_object) extends uvm_event_base; typedef uvm_event#(T) this_type; typedef uvm_event_callback#(T) cb_type; typedef uvm_callbacks#(this_type, cb_type) cbs_type; static local function bit m_register_cb(); return uvm_callbacks#(this_type,cb_type)::m_register_pair( "uvm_pkg::uvm_event#(T)", "uvm_pkg::uvm_event_callback#(T)" ); endfunction : m_register_cb static local bit m_cb_registered = m_register_cb(); typedef uvm_object_registry #(this_type) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); this_type tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction virtual function string get_type_name(); return "uvm_pkg::uvm_event#(T)"; endfunction : get_type_name local T trigger_data; local T default_data; function new (string name=""); super.new(name); endfunction virtual task wait_trigger_data (output T data); wait_trigger(); data = get_trigger_data(); endtask virtual task wait_ptrigger_data (output T data); wait_ptrigger(); data = get_trigger_data(); endtask virtual function void trigger (T data=get_default_data()); int skip; cb_type cb_q[$]; skip=0; cbs_type::get_all(cb_q, this); foreach (cb_q[i]) skip += cb_q[i].pre_trigger(this, data); if (skip==0) begin ->m_event; foreach (cb_q[i]) cb_q[i].post_trigger(this, data); num_waiters = 0; on = 1; trigger_time = $realtime; trigger_data = data; end endfunction virtual function T get_trigger_data (); return trigger_data; endfunction virtual function T get_default_data(); return default_data; endfunction : get_default_data virtual function void set_default_data(T data); default_data = data; endfunction : set_default_data virtual function void do_print (uvm_printer printer); uvm_event#(uvm_object) oe; cb_type cb_q[$]; super.do_print(printer); cbs_type::get_all(cb_q, this); printer.print_array_header("callbacks", cb_q.size(), "queue"); foreach(cb_q[e]) printer.print_object($sformatf("[%0d]", e), cb_q[e], "["); printer.print_array_footer(cb_q.size()); if ($cast(oe, this)) begin printer.print_object("trigger_data", oe.get_trigger_data()); end else begin uvm_event#(string) se; if ($cast(se, this)) printer.print_string("trigger_data", se.get_trigger_data()); end endfunction virtual function void do_copy (uvm_object rhs); this_type e; cb_type cb_q[$]; super.do_copy(rhs); if(!$cast(e, rhs) || (e==null)) return; trigger_data = e.trigger_data; begin cbs_type::get_all(cb_q, this); foreach(cb_q[i]) cbs_type::delete(this, cb_q[i]); cb_q.delete(); cbs_type::get_all(cb_q, e); foreach(cb_q[i]) cbs_type::add(this, cb_q[i]); end endfunction endclass class uvm_barrier extends uvm_object; local int threshold; local int num_waiters; local bit at_threshold; local bit auto_reset; local uvm_event#(uvm_object) m_event; typedef uvm_object_registry#(uvm_barrier,"uvm_barrier") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_barrier tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_barrier"; endfunction : type_name virtual function string get_type_name(); return "uvm_barrier"; endfunction : get_type_name function new (string name="", int threshold=0); super.new(name); m_event = new({"barrier_",name}); this.threshold = threshold; num_waiters = 0; auto_reset = 1; at_threshold = 0; endfunction virtual task wait_for(); if (at_threshold) return; num_waiters++; if (num_waiters >= threshold) begin if (!auto_reset) at_threshold=1; m_trigger(); return; end m_event.wait_trigger(); endtask virtual function void reset (bit wakeup=1); at_threshold = 0; if (num_waiters) begin if (wakeup) m_event.trigger(); else m_event.reset(); end num_waiters = 0; endfunction virtual function void set_auto_reset (bit value=1); at_threshold = 0; auto_reset = value; endfunction virtual function void set_threshold (int threshold); this.threshold = threshold; if (threshold <= num_waiters) reset(1); endfunction virtual function int get_threshold (); return threshold; endfunction virtual function int get_num_waiters (); return num_waiters; endfunction virtual function void cancel (); m_event.cancel(); num_waiters = m_event.get_num_waiters(); endfunction local task m_trigger(); m_event.trigger(); num_waiters=0; #0; endtask virtual function void do_print (uvm_printer printer); printer.print_field_int("threshold", threshold, $bits(threshold), UVM_DEC, ".", "int"); printer.print_field_int("num_waiters", num_waiters, $bits(num_waiters), UVM_DEC, ".", "int"); printer.print_field_int("at_threshold", at_threshold, $bits(at_threshold), UVM_BIN, ".", "bit"); printer.print_field_int("auto_reset", auto_reset, $bits(auto_reset), UVM_BIN, ".", "bit"); endfunction virtual function void do_copy (uvm_object rhs); uvm_barrier b; super.do_copy(rhs); if(!$cast(b, rhs) || (b==null)) return; threshold = b.threshold; num_waiters = b.num_waiters; at_threshold = b.at_threshold; auto_reset = b.auto_reset; m_event = b.m_event; endfunction endclass typedef class uvm_root; typedef class uvm_callback; typedef class uvm_callbacks_base; class uvm_typeid_base; static string typename; static uvm_callbacks_base typeid_map[uvm_typeid_base]; static uvm_typeid_base type_map[uvm_callbacks_base]; endclass class uvm_typeid#(type T=uvm_object) extends uvm_typeid_base; static uvm_typeid#(T) m_b_inst; static function uvm_typeid#(T) get(); if(m_b_inst == null) m_b_inst = new; return m_b_inst; endfunction endclass class uvm_callbacks_base extends uvm_object; typedef uvm_callbacks_base this_type; static bit m_tracing = 1; static this_type m_b_inst; static uvm_pool#(uvm_object,uvm_queue#(uvm_callback)) m_pool; static function this_type m_initialize(); if(m_b_inst == null) begin m_b_inst = new; m_pool = new; end return m_b_inst; endfunction this_type m_this_type[$]; uvm_typeid_base m_super_type; uvm_typeid_base m_derived_types[$]; virtual function bit m_am_i_a(uvm_object obj); return 0; endfunction virtual function bit m_is_for_me(uvm_callback cb); return 0; endfunction virtual function bit m_is_registered(uvm_object obj, uvm_callback cb); return 0; endfunction virtual function uvm_queue#(uvm_callback) m_get_tw_cb_q(uvm_object obj); return null; endfunction virtual function void m_add_tw_cbs(uvm_callback cb, uvm_apprepend ordering); endfunction virtual function bit m_delete_tw_cbs(uvm_callback cb); return 0; endfunction function bit check_registration(uvm_object obj, uvm_callback cb); this_type dt; if (m_is_registered(obj,cb)) return 1; foreach(m_this_type[i]) if(m_b_inst != m_this_type[i] && m_this_type[i].m_is_registered(obj,cb)) return 1; if(obj == null) begin foreach(m_derived_types[i]) begin dt = uvm_typeid_base::typeid_map[m_derived_types[i] ]; if(dt != null && dt.check_registration(null,cb)) return 1; end end return 0; endfunction endclass class uvm_typed_callbacks#(type T=uvm_object) extends uvm_callbacks_base; static uvm_queue#(uvm_callback) m_tw_cb_q; static string m_typename; typedef uvm_typed_callbacks#(T) this_type; typedef uvm_callbacks_base super_type; static this_type m_t_inst; static function this_type m_initialize(); if(m_t_inst == null) begin void'(super_type::m_initialize()); m_t_inst = new; m_t_inst.m_tw_cb_q = new("typewide_queue"); end return m_t_inst; endfunction virtual function bit m_am_i_a(uvm_object obj); T this_type; if (obj == null) return 1; return($cast(this_type,obj)); endfunction virtual function uvm_queue#(uvm_callback) m_get_tw_cb_q(uvm_object obj); if(m_am_i_a(obj)) begin foreach(m_derived_types[i]) begin super_type dt; dt = uvm_typeid_base::typeid_map[m_derived_types[i] ]; if(dt != null && dt != this) begin m_get_tw_cb_q = dt.m_get_tw_cb_q(obj); if(m_get_tw_cb_q != null) return m_get_tw_cb_q; end end return m_t_inst.m_tw_cb_q; end else return null; endfunction static function int m_cb_find(uvm_queue#(uvm_callback) q, uvm_callback cb); for(int i=0; i str.len() ? max_cb_name : str.len(); str = "(*)"; max_inst_name = max_inst_name > str.len() ? max_inst_name : str.len(); end if(obj ==null) begin if(m_t_inst.m_pool.first(bobj)) begin do if($cast(me,bobj)) break; while(m_t_inst.m_pool.next(bobj)); end if(me != null || m_t_inst.m_tw_cb_q.size()) begin qs.push_back($sformatf("Registered callbacks for all instances of %s\n", tname)); qs.push_back("---------------------------------------------------------------\n"); end if(me != null) begin do begin if($cast(me,bobj)) begin q = m_t_inst.m_pool.get(bobj); if (q==null) begin q=new; m_t_inst.m_pool.add(bobj,q); end for(int i=0; i str.len() ? max_cb_name : str.len(); str = bobj.get_full_name(); max_inst_name = max_inst_name > str.len() ? max_inst_name : str.len(); end end end while (m_t_inst.m_pool.next(bobj)); end else begin qs.push_back($sformatf("No callbacks registered for any instances of type %s\n", tname)); end end else begin if(m_t_inst.m_pool.exists(bobj) || m_t_inst.m_tw_cb_q.size()) begin qs.push_back($sformatf("Registered callbacks for instance %s of %s\n", obj.get_full_name(), tname)); qs.push_back("---------------------------------------------------------------\n"); end if(m_t_inst.m_pool.exists(bobj)) begin q = m_t_inst.m_pool.get(bobj); if(q==null) begin q=new; m_t_inst.m_pool.add(bobj,q); end for(int i=0; i str.len() ? max_cb_name : str.len(); str = bobj.get_full_name(); max_inst_name = max_inst_name > str.len() ? max_inst_name : str.len(); end end end if(!cbq.size()) begin if(obj == null) str = "*"; else str = obj.get_full_name(); qs.push_back($sformatf("No callbacks registered for instance %s of type %s\n", str, tname)); end foreach (cbq[i]) begin qs.push_back($sformatf("%s %s %s on %s %s\n", cbq[i], blanks.substr(0,max_cb_name-cbq[i].len()-1), inst_q[i], blanks.substr(0,max_inst_name - inst_q[i].len()-1), mode_q[i])); end begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"UVM/CB/DISPLAY")) uvm_report_info ("UVM/CB/DISPLAY", uvm_pkg::m_uvm_string_queue_join(qs), UVM_NONE, "t/uvm/src/base/uvm_callback.svh", 428, "", 1); end m_tracing = 1; endfunction endclass class uvm_callbacks #(type T=uvm_object, type CB=uvm_callback) extends uvm_typed_callbacks#(T); typedef uvm_typed_callbacks#(T) super_type; typedef uvm_callbacks#(T,CB) this_type; local static this_type m_inst; static uvm_typeid_base m_typeid; static uvm_typeid_base m_cb_typeid; static string m_typename; static string m_cb_typename; static uvm_callbacks#(T,uvm_callback) m_base_inst; bit m_registered; static function this_type get(); if (m_inst == null) begin uvm_typeid_base cb_base_type; void'(super_type::m_initialize()); cb_base_type = uvm_typeid#(uvm_callback)::get(); m_cb_typeid = uvm_typeid#(CB)::get(); m_typeid = uvm_typeid#(T)::get(); m_inst = new; if (cb_base_type == m_cb_typeid) begin $cast(m_base_inst, m_inst); m_t_inst = m_base_inst; uvm_typeid_base::typeid_map[m_typeid] = m_inst; uvm_typeid_base::type_map[m_b_inst] = m_typeid; end else begin m_base_inst = uvm_callbacks#(T,uvm_callback)::get(); m_base_inst.m_this_type.push_back(m_inst); end if (m_inst == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"CB/INTERNAL")) uvm_report_fatal ("CB/INTERNAL", "get(): m_inst is null", UVM_NONE, "t/uvm/src/base/uvm_callback.svh", 540, "", 1); end end return m_inst; endfunction static function bit m_register_pair(string tname="", cbname=""); this_type inst = get(); m_typename = tname; super_type::m_typename = tname; m_typeid.typename = tname; m_cb_typename = cbname; m_cb_typeid.typename = cbname; inst.m_registered = 1; return 1; endfunction virtual function bit m_is_registered(uvm_object obj, uvm_callback cb); if(m_is_for_me(cb) && m_am_i_a(obj)) begin return m_registered; end endfunction virtual function bit m_is_for_me(uvm_callback cb); CB this_cb; return($cast(this_cb,cb)); endfunction static function void add(T obj, uvm_callback cb, uvm_apprepend ordering=UVM_APPEND); uvm_queue#(uvm_callback) q; string nm,tnm; void'(get()); if (cb==null) begin if (obj==null) nm = "(*)"; else nm = obj.get_full_name(); if (m_base_inst.m_typename!="") tnm = m_base_inst.m_typename; else if (obj != null) tnm = obj.get_type_name(); else tnm = "uvm_object"; uvm_report_error("CBUNREG", {"Null callback object cannot be registered with object ", nm, " (", tnm, ")"}, UVM_NONE); return; end if (!m_base_inst.check_registration(obj,cb)) begin if (obj==null) nm = "(*)"; else nm = obj.get_full_name(); if (m_base_inst.m_typename!="") tnm = m_base_inst.m_typename; else if(obj != null) tnm = obj.get_type_name(); else tnm = "uvm_object"; uvm_report_warning("CBUNREG", {"Callback ", cb.get_name(), " cannot be registered with object ", nm, " because callback type ", cb.get_type_name(), " is not registered with object type ", tnm }, UVM_NONE); end if(obj == null) begin if (m_cb_find(m_t_inst.m_tw_cb_q,cb) != -1) begin if (m_base_inst.m_typename!="") tnm = m_base_inst.m_typename; else tnm = "uvm_object"; uvm_report_warning("CBPREG", {"Callback object ", cb.get_name(), " is already registered with type ", tnm }, UVM_NONE); end else begin m_t_inst.m_add_tw_cbs(cb,ordering); end end else begin q = m_base_inst.m_pool.get(obj); if (q==null) begin q=new; m_base_inst.m_pool.add(obj,q); end if(q.size() == 0) begin uvm_report_object o; if($cast(o,obj)) begin uvm_queue#(uvm_callback) qr; void'(uvm_callbacks#(uvm_report_object, uvm_callback)::get()); qr = uvm_callbacks#(uvm_report_object,uvm_callback)::m_t_inst.m_tw_cb_q; for(int i=0; i=0; --itr) if ($cast(cb, q.get(itr)) && cb.callback_mode()) return cb; return null; endfunction static function CB get_next (ref int itr, input T obj); uvm_queue#(uvm_callback) q; CB cb; void'(get()); m_get_q(q,obj); for(itr = itr+1; itr= 0; --itr) if($cast(cb, q.get(itr)) && cb.callback_mode()) return cb; return null; endfunction static function void get_all ( ref CB all_callbacks[$], input T obj=null ); uvm_queue#(uvm_callback) q; CB cb; CB callbacks_to_append[$]; CB unique_callbacks_to_append[$]; void'( get() ); if ((obj == null) || (!m_pool.exists(obj))) begin for (int qi=0; qi= m_max_quit_count); endfunction function int get_severity_count(uvm_severity severity); return m_severity_count[severity]; endfunction function void set_severity_count(uvm_severity severity, int count); m_severity_count[severity] = count < 0 ? 0 : count; endfunction function void incr_severity_count(uvm_severity severity); m_severity_count[severity]++; endfunction function void reset_severity_counts(); uvm_severity s; s = s.first(); forever begin m_severity_count[s] = 0; if(s == s.last()) break; s = s.next(); end endfunction function int get_id_count(string id); if(m_id_count.exists(id)) return m_id_count[id]; return 0; endfunction function void set_id_count(string id, int count); m_id_count[id] = count < 0 ? 0 : count; endfunction function void incr_id_count(string id); if(m_id_count.exists(id)) m_id_count[id]++; else m_id_count[id] = 1; endfunction virtual function void set_message_database(uvm_tr_database database); m_message_db = database; endfunction : set_message_database virtual function uvm_tr_database get_message_database(); return m_message_db; endfunction : get_message_database virtual function void get_severity_set(output uvm_severity q[$]); foreach(m_severity_count[idx]) q.push_back(idx); endfunction virtual function void get_id_set(output string q[$]); foreach(m_id_count[idx]) q.push_back(idx); endfunction function void f_display(UVM_FILE file, string str); if (file == 0) $display("%s", str); else $fdisplay(file, "%s", str); endfunction virtual function void process_report_message(uvm_report_message report_message); uvm_report_handler l_report_handler = report_message.get_report_handler(); process p = process::self(); bit report_ok = 1; report_message.set_report_server(this); if(report_ok) report_ok = uvm_report_catcher::process_all_report_catchers(report_message); if(uvm_action_type'(report_message.get_action()) == UVM_NO_ACTION) report_ok = 0; if(report_ok) begin string m; uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_report_server svr = cs.get_report_server(); if (report_message.get_action() & (UVM_LOG|UVM_DISPLAY)) m = svr.compose_report_message(report_message); svr.execute_report_message(report_message, m); end endfunction virtual function void execute_report_message(uvm_report_message report_message, string composed_message); process p = process::self(); incr_severity_count(report_message.get_severity()); incr_id_count(report_message.get_id()); if (record_all_messages) report_message.set_action(report_message.get_action() | UVM_RM_RECORD); if(report_message.get_action() & UVM_RM_RECORD) begin uvm_tr_stream stream; uvm_report_object ro = report_message.get_report_object(); uvm_report_handler rh = report_message.get_report_handler(); if (m_streams.exists(ro.get_name()) && (m_streams[ro.get_name()].exists(rh.get_name()))) stream = m_streams[ro.get_name()][rh.get_name()]; if (stream == null) begin uvm_tr_database db; db = get_message_database(); if (db == null) begin uvm_coreservice_t cs = uvm_coreservice_t::get(); db = cs.get_default_tr_database(); end if (db != null) begin stream = db.open_stream(ro.get_name(), rh.get_name(), "MESSAGES"); m_streams[ro.get_name()][rh.get_name()] = stream; end end if (stream != null) begin uvm_recorder recorder = stream.open_recorder(report_message.get_name(),,report_message.get_type_name()); if (recorder != null) begin report_message.record(recorder); recorder.free(); end end end if(report_message.get_action() & UVM_DISPLAY) $display("%s", composed_message); if(report_message.get_action() & UVM_LOG) if( (report_message.get_file() == 0) || (report_message.get_file() != 32'h8000_0001) ) begin UVM_FILE tmp_file = report_message.get_file(); if((report_message.get_file() & 32'h8000_0000) == 0) begin tmp_file = report_message.get_file() & 32'hffff_fffe; end f_display(tmp_file, composed_message); end if(report_message.get_action() & UVM_COUNT) begin if(get_max_quit_count() != 0) begin incr_quit_count(); if(is_quit_count_reached()) begin report_message.set_action(report_message.get_action() | UVM_EXIT); end end end if(report_message.get_action() & UVM_EXIT) begin uvm_root l_root; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); l_root = cs.get_root(); l_root.die(); end if (report_message.get_action() & UVM_STOP) $stop; endfunction virtual function string compose_report_message(uvm_report_message report_message, string report_object_name = ""); string sev_string; uvm_severity l_severity; uvm_verbosity l_verbosity; string filename_line_string; string time_str; string line_str; string context_str; string verbosity_str; string terminator_str; string msg_body_str; uvm_report_message_element_container el_container; string prefix; uvm_report_handler l_report_handler; l_severity = report_message.get_severity(); sev_string = l_severity.name(); if (report_message.get_filename() != "") begin line_str.itoa(report_message.get_line()); filename_line_string = {report_message.get_filename(), "(", line_str, ") "}; end $swrite(time_str, "%0t", $time); if (report_message.get_context() != "") context_str = {"@@", report_message.get_context()}; if (show_verbosity) begin if ($cast(l_verbosity, report_message.get_verbosity())) verbosity_str = l_verbosity.name(); else verbosity_str.itoa(report_message.get_verbosity()); verbosity_str = {"(", verbosity_str, ")"}; end if (show_terminator) terminator_str = {" -",sev_string}; el_container = report_message.get_element_container(); if (el_container.size() == 0) msg_body_str = report_message.get_message(); else begin uvm_printer uvm_default_printer = uvm_printer::get_default() ; prefix = uvm_default_printer.get_line_prefix(); uvm_default_printer.set_line_prefix(" +"); msg_body_str = {report_message.get_message(), "\n", el_container.sprint()}; uvm_default_printer.set_line_prefix(prefix); end if (report_object_name == "") begin l_report_handler = report_message.get_report_handler(); report_object_name = l_report_handler.get_full_name(); end compose_report_message = {sev_string, verbosity_str, " ", filename_line_string, "@ ", time_str, ": ", report_object_name, context_str, " [", report_message.get_id(), "] ", msg_body_str, terminator_str}; endfunction virtual function void report_summarize(UVM_FILE file = UVM_STDOUT); string id; string name; string output_str; string q[$]; uvm_report_catcher::summarize(); q.push_back("\n--- UVM Report Summary ---\n\n"); if(m_max_quit_count != 0) begin if ( m_quit_count >= m_max_quit_count ) q.push_back("Quit count reached!\n"); q.push_back($sformatf("Quit count : %5d of %5d\n",m_quit_count, m_max_quit_count)); end q.push_back("** Report counts by severity\n"); foreach(m_severity_count[s]) begin q.push_back($sformatf("%s :%5d\n", s.name(), m_severity_count[s])); end if (enable_report_id_count_summary) begin q.push_back("** Report counts by id\n"); foreach(m_id_count[id]) q.push_back($sformatf("[%s] %5d\n", id, m_id_count[id])); end begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"UVM/REPORT/SERVER")) uvm_report_info ("UVM/REPORT/SERVER", uvm_pkg::m_uvm_string_queue_join(q), UVM_NONE, "t/uvm/src/base/uvm_report_server.svh", 864, "", 1); end endfunction endclass `define UVM_REPORT_HANDLER_SVH typedef class uvm_report_object; typedef class uvm_report_server; typedef uvm_pool#(string, uvm_action) uvm_id_actions_array; typedef uvm_pool#(string, UVM_FILE) uvm_id_file_array; typedef uvm_pool#(string, int) uvm_id_verbosities_array; typedef uvm_pool#(uvm_severity, uvm_severity) uvm_sev_override_array; class uvm_report_handler extends uvm_object; int m_max_verbosity_level; uvm_id_verbosities_array id_verbosities; uvm_id_verbosities_array severity_id_verbosities[uvm_severity]; uvm_id_actions_array id_actions; uvm_action severity_actions[uvm_severity]; uvm_id_actions_array severity_id_actions[uvm_severity]; uvm_sev_override_array sev_overrides; uvm_sev_override_array sev_id_overrides [string]; UVM_FILE default_file_handle; uvm_id_file_array id_file_handles; UVM_FILE severity_file_handles[uvm_severity]; uvm_id_file_array severity_id_file_handles[uvm_severity]; typedef uvm_object_registry#(uvm_report_handler,"uvm_report_handler") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_report_handler tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_report_handler"; endfunction : type_name virtual function string get_type_name(); return "uvm_report_handler"; endfunction : get_type_name function new(string name = "uvm_report_handler"); super.new(name); initialize(); endfunction virtual function void do_print (uvm_printer printer); uvm_verbosity l_verbosity; uvm_severity l_severity; string idx; int l_int; if ($cast(l_verbosity, m_max_verbosity_level)) printer.print_generic("max_verbosity_level", "uvm_verbosity", 32, l_verbosity.name()); else printer.print_field("max_verbosity_level", m_max_verbosity_level, 32, UVM_DEC, ".", "int"); if(id_verbosities.first(idx)) begin printer.print_array_header("id_verbosities",id_verbosities.num(), "uvm_pool"); do begin l_int = id_verbosities.get(idx); if ($cast(l_verbosity, l_int)) printer.print_generic($sformatf("[%s]", idx), "uvm_verbosity", 32, l_verbosity.name()); else begin string l_str; l_str.itoa(l_int); printer.print_generic($sformatf("[%s]", idx), "int", 32, l_str); end end while(id_verbosities.next(idx)); printer.print_array_footer(); end if(severity_id_verbosities.size() != 0) begin int _total_cnt; foreach (severity_id_verbosities[l_severity]) _total_cnt += severity_id_verbosities[l_severity].num(); printer.print_array_header("severity_id_verbosities", _total_cnt, "array"); if(severity_id_verbosities.first(l_severity)) begin do begin uvm_id_verbosities_array id_v_ary = severity_id_verbosities[l_severity]; if(id_v_ary.first(idx)) do begin l_int = id_v_ary.get(idx); if ($cast(l_verbosity, l_int)) printer.print_generic($sformatf("[%s:%s]", l_severity.name(), idx), "uvm_verbosity", 32, l_verbosity.name()); else begin string l_str; l_str.itoa(l_int); printer.print_generic($sformatf("[%s:%s]", l_severity.name(), idx), "int", 32, l_str); end end while(id_v_ary.next(idx)); end while(severity_id_verbosities.next(l_severity)); end printer.print_array_footer(); end if(id_actions.first(idx)) begin printer.print_array_header("id_actions",id_actions.num(), "uvm_pool"); do begin l_int = id_actions.get(idx); printer.print_generic($sformatf("[%s]", idx), "uvm_action", 32, format_action(l_int)); end while(id_actions.next(idx)); printer.print_array_footer(); end if(severity_actions.first(l_severity)) begin printer.print_array_header("severity_actions",4,"array"); do begin printer.print_generic($sformatf("[%s]", l_severity.name()), "uvm_action", 32, format_action(severity_actions[l_severity])); end while(severity_actions.next(l_severity)); printer.print_array_footer(); end if(severity_id_actions.size() != 0) begin int _total_cnt; foreach (severity_id_actions[l_severity]) _total_cnt += severity_id_actions[l_severity].num(); printer.print_array_header("severity_id_actions", _total_cnt, "array"); if(severity_id_actions.first(l_severity)) begin do begin uvm_id_actions_array id_a_ary = severity_id_actions[l_severity]; if(id_a_ary.first(idx)) do begin printer.print_generic($sformatf("[%s:%s]", l_severity.name(), idx), "uvm_action", 32, format_action(id_a_ary.get(idx))); end while(id_a_ary.next(idx)); end while(severity_id_actions.next(l_severity)); end printer.print_array_footer(); end if(sev_overrides.first(l_severity)) begin printer.print_array_header("sev_overrides",sev_overrides.num(), "uvm_pool"); do begin uvm_severity l_severity_new = sev_overrides.get(l_severity); printer.print_generic($sformatf("[%s]", l_severity.name()), "uvm_severity", 32, l_severity_new.name()); end while(sev_overrides.next(l_severity)); printer.print_array_footer(); end if(sev_id_overrides.size() != 0) begin int _total_cnt; foreach (sev_id_overrides[idx]) _total_cnt += sev_id_overrides[idx].num(); printer.print_array_header("sev_id_overrides", _total_cnt, "array"); if(sev_id_overrides.first(idx)) begin do begin uvm_sev_override_array sev_o_ary = sev_id_overrides[idx]; if(sev_o_ary.first(l_severity)) do begin uvm_severity new_sev = sev_o_ary.get(l_severity); printer.print_generic($sformatf("[%s:%s]", l_severity.name(), idx), "uvm_severity", 32, new_sev.name()); end while(sev_o_ary.next(l_severity)); end while(sev_id_overrides.next(idx)); end printer.print_array_footer(); end printer.print_field("default_file_handle", default_file_handle, 32, UVM_HEX, ".", "int"); if(id_file_handles.first(idx)) begin printer.print_array_header("id_file_handles",id_file_handles.num(), "uvm_pool"); do begin printer.print_field($sformatf("[%s]", idx), id_file_handles.get(idx), 32, UVM_HEX, ".", "UVM_FILE"); end while(id_file_handles.next(idx)); printer.print_array_footer(); end if(severity_file_handles.first(l_severity)) begin printer.print_array_header("severity_file_handles",4,"array"); do begin printer.print_field($sformatf("[%s]", l_severity.name()), severity_file_handles[l_severity], 32, UVM_HEX, ".", "UVM_FILE"); end while(severity_file_handles.next(l_severity)); printer.print_array_footer(); end if(severity_id_file_handles.size() != 0) begin int _total_cnt; foreach (severity_id_file_handles[l_severity]) _total_cnt += severity_id_file_handles[l_severity].num(); printer.print_array_header("severity_id_file_handles", _total_cnt, "array"); if(severity_id_file_handles.first(l_severity)) begin do begin uvm_id_file_array id_f_ary = severity_id_file_handles[l_severity]; if(id_f_ary.first(idx)) do begin printer.print_field($sformatf("[%s:%s]", l_severity.name(), idx), id_f_ary.get(idx), 32, UVM_HEX, ".", "UVM_FILE"); end while(id_f_ary.next(idx)); end while(severity_id_file_handles.next(l_severity)); end printer.print_array_footer(); end endfunction virtual function void process_report_message(uvm_report_message report_message); process p = process::self(); uvm_report_server srvr = uvm_report_server::get_server(); string id = report_message.get_id(); uvm_severity severity = report_message.get_severity(); if(sev_id_overrides.exists(id)) begin if(sev_id_overrides[id].exists(uvm_severity'(severity))) begin severity = sev_id_overrides[id].get(severity); report_message.set_severity(severity); end end else begin if(sev_overrides.exists(severity)) begin severity = sev_overrides.get(severity); report_message.set_severity(severity); end end report_message.set_file(get_file_handle(severity, id)); report_message.set_report_handler(this); report_message.set_action(get_action(severity, id)); srvr.process_report_message(report_message); endfunction static function string format_action(uvm_action action); string s; if(uvm_action_type'(action) == UVM_NO_ACTION) begin s = "NO ACTION"; end else begin s = ""; if(action & UVM_DISPLAY) s = {s, "DISPLAY "}; if(action & UVM_LOG) s = {s, "LOG "}; if(action & UVM_RM_RECORD) s = {s, "RM_RECORD "}; if(action & UVM_COUNT) s = {s, "COUNT "}; if(action & UVM_CALL_HOOK) s = {s, "CALL_HOOK "}; if(action & UVM_EXIT) s = {s, "EXIT "}; if(action & UVM_STOP) s = {s, "STOP "}; end return s; endfunction function void initialize(); set_default_file(0); m_max_verbosity_level = UVM_MEDIUM; id_actions=new(); id_verbosities=new(); id_file_handles=new(); sev_overrides=new(); set_severity_action(UVM_INFO, UVM_DISPLAY); set_severity_action(UVM_WARNING, UVM_DISPLAY); set_severity_action(UVM_ERROR, UVM_DISPLAY | UVM_COUNT); set_severity_action(UVM_FATAL, UVM_DISPLAY | UVM_EXIT); set_severity_file(UVM_INFO, default_file_handle); set_severity_file(UVM_WARNING, default_file_handle); set_severity_file(UVM_ERROR, default_file_handle); set_severity_file(UVM_FATAL, default_file_handle); endfunction local function UVM_FILE get_severity_id_file(uvm_severity severity, string id); uvm_id_file_array array; if(severity_id_file_handles.exists(severity)) begin array = severity_id_file_handles[severity]; if(array.exists(id)) return array.get(id); end if(id_file_handles.exists(id)) return id_file_handles.get(id); if(severity_file_handles.exists(severity)) return severity_file_handles[severity]; return default_file_handle; endfunction function void set_verbosity_level(int verbosity_level); m_max_verbosity_level = verbosity_level; endfunction function int get_verbosity_level(uvm_severity severity=UVM_INFO, string id="" ); uvm_id_verbosities_array array; if(severity_id_verbosities.exists(severity)) begin array = severity_id_verbosities[severity]; if(array.exists(id)) begin return array.get(id); end end if(id_verbosities.exists(id)) begin return id_verbosities.get(id); end return m_max_verbosity_level; endfunction function uvm_action get_action(uvm_severity severity, string id); uvm_id_actions_array array; if(severity_id_actions.exists(severity)) begin array = severity_id_actions[severity]; if(array.exists(id)) return array.get(id); end if(id_actions.exists(id)) return id_actions.get(id); return severity_actions[severity]; endfunction function UVM_FILE get_file_handle(uvm_severity severity, string id); UVM_FILE file; file = get_severity_id_file(severity, id); if (file != 0) return file; if (id_file_handles.exists(id)) begin file = id_file_handles.get(id); if (file != 0) return file; end if (severity_file_handles.exists(severity)) begin file = severity_file_handles[severity]; if(file != 0) return file; end return default_file_handle; endfunction function void set_severity_action(input uvm_severity severity, input uvm_action action); severity_actions[severity] = action; endfunction function void set_id_action(input string id, input uvm_action action); id_actions.add(id, action); endfunction function void set_severity_id_action(uvm_severity severity, string id, uvm_action action); if(!severity_id_actions.exists(severity)) severity_id_actions[severity] = new; severity_id_actions[severity].add(id,action); endfunction function void set_id_verbosity(input string id, input int verbosity); id_verbosities.add(id, verbosity); endfunction function void set_severity_id_verbosity(uvm_severity severity, string id, int verbosity); if(!severity_id_verbosities.exists(severity)) severity_id_verbosities[severity] = new; severity_id_verbosities[severity].add(id,verbosity); endfunction function void set_default_file (UVM_FILE file); default_file_handle = file; endfunction function void set_severity_file (uvm_severity severity, UVM_FILE file); severity_file_handles[severity] = file; endfunction function void set_id_file (string id, UVM_FILE file); id_file_handles.add(id, file); endfunction function void set_severity_id_file(uvm_severity severity, string id, UVM_FILE file); if(!severity_id_file_handles.exists(severity)) severity_id_file_handles[severity] = new; severity_id_file_handles[severity].add(id, file); endfunction function void set_severity_override(uvm_severity cur_severity, uvm_severity new_severity); sev_overrides.add(cur_severity, new_severity); endfunction function void set_severity_id_override(uvm_severity cur_severity, string id, uvm_severity new_severity); uvm_sev_override_array arr; if(!sev_id_overrides.exists(id)) sev_id_overrides[id] = new; sev_id_overrides[id].add(cur_severity, new_severity); endfunction virtual function void report( uvm_severity severity, string name, string id, string message, int verbosity_level=UVM_MEDIUM, string filename="", int line=0, uvm_report_object client=null ); bit l_report_enabled = 0; uvm_report_message l_report_message; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); if (!uvm_report_enabled(verbosity_level, UVM_INFO, id)) return; if (client==null) client = cs.get_root(); l_report_message = uvm_report_message::new_report_message(); l_report_message.set_report_message(severity, id, message, verbosity_level, filename, line, name); l_report_message.set_report_object(client); l_report_message.set_action(get_action(severity,id)); process_report_message(l_report_message); endfunction endclass : uvm_report_handler `define UVM_REPORT_CLIENT_SVH typedef class uvm_component; typedef class uvm_env; typedef class uvm_root; class uvm_report_object extends uvm_object; uvm_report_handler m_rh; local bit m_rh_set; local function void m_rh_init(); if (!m_rh_set) set_report_handler(uvm_report_handler::type_id::create(get_name())); endfunction : m_rh_init function new(string name = ""); super.new(name); endfunction function uvm_report_object uvm_get_report_object(); return this; endfunction function int uvm_report_enabled(int verbosity, uvm_severity severity = UVM_INFO, string id = ""); if (get_report_verbosity_level(severity, id) < verbosity) return 0; return 1; endfunction virtual function void uvm_report( uvm_severity severity, string id, string message, int verbosity = (severity == uvm_severity'(UVM_ERROR)) ? UVM_LOW : (severity == uvm_severity'(UVM_FATAL)) ? UVM_NONE : UVM_MEDIUM, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked =0); uvm_report_message l_report_message; if ((severity == UVM_INFO) && (report_enabled_checked == 0)) begin if (!uvm_report_enabled(verbosity, severity, id)) return; end l_report_message = uvm_report_message::new_report_message(); l_report_message.set_report_message(severity, id, message, verbosity, filename, line, context_name); uvm_process_report_message(l_report_message); endfunction virtual function void uvm_report_info( string id, string message, int verbosity = UVM_MEDIUM, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_report (UVM_INFO, id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction virtual function void uvm_report_warning( string id, string message, int verbosity = UVM_MEDIUM, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_report (UVM_WARNING, id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction virtual function void uvm_report_error( string id, string message, int verbosity = UVM_NONE, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_report (UVM_ERROR, id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction virtual function void uvm_report_fatal( string id, string message, int verbosity = UVM_NONE, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_report (UVM_FATAL, id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction virtual function void uvm_process_report_message(uvm_report_message report_message); m_rh_init(); report_message.set_report_object(this); m_rh.process_report_message(report_message); endfunction function int get_report_verbosity_level(uvm_severity severity=UVM_INFO, string id=""); m_rh_init(); return m_rh.get_verbosity_level(severity, id); endfunction function int get_report_max_verbosity_level(); m_rh_init(); return m_rh.m_max_verbosity_level; endfunction function void set_report_verbosity_level (int verbosity_level); m_rh_init(); m_rh.set_verbosity_level(verbosity_level); endfunction function void set_report_id_verbosity (string id, int verbosity); m_rh_init(); m_rh.set_id_verbosity(id, verbosity); endfunction function void set_report_severity_id_verbosity (uvm_severity severity, string id, int verbosity); m_rh_init(); m_rh.set_severity_id_verbosity(severity, id, verbosity); endfunction function int get_report_action(uvm_severity severity, string id); m_rh_init(); return m_rh.get_action(severity,id); endfunction function void set_report_severity_action (uvm_severity severity, uvm_action action); m_rh_init(); m_rh.set_severity_action(severity, action); endfunction function void set_report_id_action (string id, uvm_action action); m_rh_init(); m_rh.set_id_action(id, action); endfunction function void set_report_severity_id_action (uvm_severity severity, string id, uvm_action action); m_rh_init(); m_rh.set_severity_id_action(severity, id, action); endfunction function int get_report_file_handle(uvm_severity severity, string id); m_rh_init(); return m_rh.get_file_handle(severity,id); endfunction function void set_report_default_file (UVM_FILE file); m_rh_init(); m_rh.set_default_file(file); endfunction function void set_report_id_file (string id, UVM_FILE file); m_rh_init(); m_rh.set_id_file(id, file); endfunction function void set_report_severity_file (uvm_severity severity, UVM_FILE file); m_rh_init(); m_rh.set_severity_file(severity, file); endfunction function void set_report_severity_id_file (uvm_severity severity, string id, UVM_FILE file); m_rh_init(); m_rh.set_severity_id_file(severity, id, file); endfunction function void set_report_severity_override(uvm_severity cur_severity, uvm_severity new_severity); m_rh_init(); m_rh.set_severity_override(cur_severity, new_severity); endfunction function void set_report_severity_id_override(uvm_severity cur_severity, string id, uvm_severity new_severity); m_rh_init(); m_rh.set_severity_id_override(cur_severity, id, new_severity); endfunction function void set_report_handler(uvm_report_handler handler); m_rh = handler; m_rh_set = 1; endfunction function uvm_report_handler get_report_handler(); m_rh_init(); return m_rh; endfunction function void reset_report_handler; m_rh_init(); m_rh.initialize(); endfunction endclass typedef class uvm_event; typedef class uvm_event_pool; typedef class uvm_component; typedef class uvm_parent_child_link; virtual class uvm_transaction extends uvm_object; extern function new (string name="", uvm_component initiator=null); extern function void accept_tr (time accept_time = 0); extern virtual protected function void do_accept_tr (); extern function int begin_tr (time begin_time = 0); extern function int begin_child_tr (time begin_time = 0, int parent_handle = 0); extern virtual protected function void do_begin_tr (); extern function void end_tr (time end_time=0, bit free_handle=1); extern virtual protected function void do_end_tr (); extern function int get_tr_handle (); extern function void disable_recording (); extern function void enable_recording (uvm_tr_stream stream); extern function bit is_recording_enabled(); extern function bit is_active (); extern function uvm_event_pool get_event_pool (); extern function void set_initiator (uvm_component initiator); extern function uvm_component get_initiator (); extern function time get_accept_time (); extern function time get_begin_time (); extern function time get_end_time (); extern function void set_transaction_id(int id); extern function int get_transaction_id(); const local uvm_event_pool events = new("events"); extern virtual function void do_print (uvm_printer printer); extern virtual function void do_record (uvm_recorder recorder); extern virtual function void do_copy (uvm_object rhs); extern protected function int m_begin_tr (time begin_time=0, int parent_handle=0); local int m_transaction_id = -1; local time begin_time=-1; local time end_time=-1; local time accept_time=-1; local uvm_component initiator; local uvm_tr_stream stream_handle; local uvm_recorder tr_recorder; endclass function uvm_transaction::new (string name="", uvm_component initiator = null); super.new(name); this.initiator = initiator; m_transaction_id = -1; endfunction function void uvm_transaction::set_transaction_id(int id); m_transaction_id = id; endfunction function int uvm_transaction::get_transaction_id(); return (m_transaction_id); endfunction function void uvm_transaction::set_initiator(uvm_component initiator); this.initiator = initiator; endfunction function uvm_component uvm_transaction::get_initiator(); return initiator; endfunction function uvm_event_pool uvm_transaction::get_event_pool(); return events; endfunction function bit uvm_transaction::is_active(); return (end_time == -1); endfunction function time uvm_transaction::get_begin_time (); return begin_time; endfunction function time uvm_transaction::get_end_time (); return end_time; endfunction function time uvm_transaction::get_accept_time (); return accept_time; endfunction function void uvm_transaction::do_accept_tr(); return; endfunction function void uvm_transaction::do_begin_tr(); return; endfunction function void uvm_transaction::do_end_tr(); return; endfunction function void uvm_transaction::do_print (uvm_printer printer); string str; uvm_component tmp_initiator; super.do_print(printer); if(accept_time != -1) printer.print_time("accept_time", accept_time); if(begin_time != -1) printer.print_time("begin_time", begin_time); if(end_time != -1) printer.print_time("end_time", end_time); if(initiator != null) begin tmp_initiator = initiator; $swrite(str,"@%0d", tmp_initiator.get_inst_id()); printer.print_generic("initiator", initiator.get_type_name(), -1, str); end endfunction function void uvm_transaction::do_copy (uvm_object rhs); uvm_transaction txn; super.do_copy(rhs); if(rhs == null) return; if(!$cast(txn, rhs) ) return; accept_time = txn.accept_time; begin_time = txn.begin_time; end_time = txn.end_time; initiator = txn.initiator; stream_handle = txn.stream_handle; tr_recorder = txn.tr_recorder; endfunction function void uvm_transaction::do_record (uvm_recorder recorder); string s; super.do_record(recorder); if(accept_time != -1) recorder.record_field("accept_time", accept_time, $bits(accept_time), UVM_TIME); if(initiator != null) begin uvm_recursion_policy_enum p = recorder.get_recursion_policy(); recorder.set_recursion_policy(UVM_REFERENCE); recorder.record_object("initiator", initiator); recorder.set_recursion_policy(p); end endfunction function int uvm_transaction::get_tr_handle (); if (tr_recorder != null) return tr_recorder.get_handle(); else return 0; endfunction function void uvm_transaction::disable_recording (); this.stream_handle = null; endfunction function void uvm_transaction::enable_recording (uvm_tr_stream stream); this.stream_handle = stream; endfunction : enable_recording function bit uvm_transaction::is_recording_enabled (); return (this.stream_handle != null); endfunction function void uvm_transaction::accept_tr (time accept_time = 0); uvm_event#(uvm_object) e; if(accept_time != 0) this.accept_time = accept_time; else this.accept_time = $realtime; do_accept_tr(); e = events.get("accept"); if(e!=null) e.trigger(); endfunction function int uvm_transaction::begin_tr (time begin_time=0); return m_begin_tr(begin_time); endfunction function int uvm_transaction::begin_child_tr (time begin_time=0, int parent_handle=0); return m_begin_tr(begin_time, parent_handle); endfunction function int uvm_transaction::m_begin_tr (time begin_time=0, int parent_handle=0); time tmp_time = (begin_time == 0) ? $realtime : begin_time; uvm_recorder parent_recorder; if (parent_handle != 0) parent_recorder = uvm_recorder::get_recorder_from_handle(parent_handle); if (tr_recorder != null) end_tr(tmp_time); if(is_recording_enabled()) begin uvm_tr_database db = stream_handle.get_db(); this.end_time = -1; this.begin_time = tmp_time; if(parent_recorder == null) tr_recorder = stream_handle.open_recorder(get_type_name(), this.begin_time, "Begin_No_Parent, Link"); else begin tr_recorder = stream_handle.open_recorder(get_type_name(), this.begin_time, "Begin_End, Link"); if (tr_recorder != null) db.establish_link(uvm_parent_child_link::get_link(parent_recorder, tr_recorder)); end if (tr_recorder != null) m_begin_tr = tr_recorder.get_handle(); else m_begin_tr = 0; end else begin tr_recorder = null; this.end_time = -1; this.begin_time = tmp_time; m_begin_tr = 0; end do_begin_tr(); begin uvm_event#(uvm_object) begin_event ; begin_event = events.get("begin"); begin_event.trigger(); end endfunction function void uvm_transaction::end_tr (time end_time=0, bit free_handle=1); this.end_time = (end_time == 0) ? $realtime : end_time; do_end_tr(); if(is_recording_enabled() && (tr_recorder != null)) begin record(tr_recorder); tr_recorder.close(this.end_time); if(free_handle) begin tr_recorder.free(); end end tr_recorder = null; begin uvm_event#(uvm_object) end_event ; end_event = events.get("end") ; end_event.trigger(); end endfunction typedef class uvm_sequencer_base; typedef class uvm_domain; typedef class uvm_task_phase; typedef class uvm_phase_cb; class uvm_phase extends uvm_object; static local bit m_register_cb_uvm_phase_cb = uvm_callbacks#(uvm_phase,uvm_phase_cb)::m_register_pair("uvm_phase","uvm_phase_cb"); extern function new(string name="uvm_phase", uvm_phase_type phase_type=UVM_PHASE_SCHEDULE, uvm_phase parent=null); extern function uvm_phase_type get_phase_type(); extern virtual function void set_max_ready_to_end_iterations(int max); extern virtual function int get_max_ready_to_end_iterations(); extern static function void set_default_max_ready_to_end_iterations(int max); extern static function int get_default_max_ready_to_end_iterations(); extern function uvm_phase_state get_state(); extern function int get_run_count(); extern function uvm_phase find_by_name(string name, bit stay_in_scope=1); extern function uvm_phase find(uvm_phase phase, bit stay_in_scope=1); extern function bit is(uvm_phase phase); extern function bit is_before(uvm_phase phase); extern function bit is_after(uvm_phase phase); virtual function void exec_func(uvm_component comp, uvm_phase phase); endfunction virtual task exec_task(uvm_component comp, uvm_phase phase); endtask extern function void add(uvm_phase phase, uvm_phase with_phase=null, uvm_phase after_phase=null, uvm_phase before_phase=null, uvm_phase start_with_phase=null, uvm_phase end_with_phase=null ); extern function uvm_phase get_parent(); extern virtual function string get_full_name(); extern function uvm_phase get_schedule(bit hier = 0); extern function string get_schedule_name(bit hier = 0); extern function uvm_domain get_domain(); extern function uvm_phase get_imp(); extern function string get_domain_name(); extern function void get_adjacent_predecessor_nodes(ref uvm_phase pred[]); extern function void get_adjacent_successor_nodes(ref uvm_phase succ[]); extern function void m_report_null_objection(uvm_object obj, string description, int count, string action); extern virtual function void raise_objection (uvm_object obj, string description="", int count=1); extern virtual function void drop_objection (uvm_object obj, string description="", int count=1); extern virtual function int get_objection_count( uvm_object obj=null ); extern function void sync(uvm_domain target, uvm_phase phase=null, uvm_phase with_phase=null); extern function void unsync(uvm_domain target, uvm_phase phase=null, uvm_phase with_phase=null); extern task wait_for_state(uvm_phase_state state, uvm_wait_op op=UVM_EQ); extern function void jump(uvm_phase phase); extern function void set_jump_phase(uvm_phase phase) ; extern function void end_prematurely() ; extern static function void jump_all(uvm_phase phase); extern function uvm_phase get_jump_target(); protected uvm_phase_type m_phase_type; protected uvm_phase m_parent; uvm_phase m_imp; local uvm_phase_state m_state; local int m_run_count; local process m_phase_proc; local static int m_default_max_ready_to_end_iters = 20; local int max_ready_to_end_iters = get_default_max_ready_to_end_iterations(); int m_num_procs_not_yet_returned; extern function uvm_phase m_find_predecessor(uvm_phase phase, bit stay_in_scope=1, uvm_phase orig_phase=null); extern function uvm_phase m_find_successor(uvm_phase phase, bit stay_in_scope=1, uvm_phase orig_phase=null); extern function uvm_phase m_find_predecessor_by_name(string name, bit stay_in_scope=1, uvm_phase orig_phase=null); extern function uvm_phase m_find_successor_by_name(string name, bit stay_in_scope=1, uvm_phase orig_phase=null); extern function void m_print_successors(); virtual function void traverse(uvm_component comp, uvm_phase phase, uvm_phase_state state); endfunction virtual function void execute(uvm_component comp, uvm_phase phase); endfunction protected bit m_predecessors[uvm_phase]; protected bit m_successors[uvm_phase]; protected uvm_phase m_end_node; static protected bit m_executing_phases[uvm_phase]; function uvm_phase get_begin_node(); if (m_imp != null) return this; return null; endfunction function uvm_phase get_end_node(); return m_end_node; endfunction local uvm_phase m_sync[$]; local uvm_objection phase_done; local int unsigned m_ready_to_end_count; function int unsigned get_ready_to_end_count(); return m_ready_to_end_count; endfunction extern local function void get_predecessors_for_successors(output bit pred_of_succ[uvm_phase]); extern local task m_wait_for_pred(); local bit m_jump_bkwd; local bit m_jump_fwd; local uvm_phase m_jump_phase; local bit m_premature_end; extern function void clear(uvm_phase_state state = UVM_PHASE_DORMANT); extern function void clear_successors( uvm_phase_state state = UVM_PHASE_DORMANT, uvm_phase end_state=null); local static mailbox #(uvm_phase) m_phase_hopper = new(); extern static task m_run_phases(); extern local task execute_phase(); extern local function void m_terminate_phase(); extern local function void m_print_termination_state(); extern local task wait_for_self_and_siblings_to_drop(); extern function void kill(); extern function void kill_successors(); protected static bit m_phase_trace; local static bit m_use_ovm_run_semantic; function string convert2string(); string s; s = $sformatf("phase: %s parent=%s pred=%s succ=%s",get_name(), (m_parent==null) ? "null" : get_schedule_name(), m_aa2string(m_predecessors), m_aa2string(m_successors)); return s; endfunction local function string m_aa2string(bit aa[uvm_phase]); string s; int i; s = "'{ "; foreach (aa[ph]) begin uvm_phase n = ph; s = {s, (n == null) ? "null" : n.get_name(), (i == aa.num()-1) ? "" : ", "}; i++; end s = {s, " }"}; return s; endfunction function bit is_domain(); return (m_phase_type == UVM_PHASE_DOMAIN); endfunction virtual function void m_get_transitive_children(ref uvm_phase phases[$]); foreach (m_successors[succ]) begin phases.push_back(succ); succ.m_get_transitive_children(phases); end endfunction function uvm_objection get_objection(); uvm_phase imp; uvm_task_phase tp; imp = get_imp(); if ((get_phase_type() != UVM_PHASE_NODE) || (imp == null) || !$cast(tp, imp)) begin return null; end if (phase_done == null) begin phase_done = uvm_objection::type_id::create({get_name(), "_objection"}); end return phase_done; endfunction endclass class uvm_phase_state_change extends uvm_object; typedef uvm_object_registry#(uvm_phase_state_change,"uvm_phase_state_change") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_phase_state_change tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_phase_state_change"; endfunction : type_name virtual function string get_type_name(); return "uvm_phase_state_change"; endfunction : get_type_name uvm_phase m_phase; uvm_phase_state m_prev_state; uvm_phase m_jump_to; function new(string name = "uvm_phase_state_change"); super.new(name); endfunction virtual function uvm_phase_state get_state(); return m_phase.get_state(); endfunction virtual function uvm_phase_state get_prev_state(); return m_prev_state; endfunction function uvm_phase jump_to(); return m_jump_to; endfunction endclass class uvm_phase_cb extends uvm_callback; function new(string name="unnamed-uvm_phase_cb"); super.new(name); endfunction : new virtual function void phase_state_change(uvm_phase phase, uvm_phase_state_change change); endfunction endclass typedef uvm_callbacks#(uvm_phase, uvm_phase_cb) uvm_phase_cb_pool ; typedef class uvm_cmdline_processor; `define UVM_PH_TRACE(ID,MSG,PH,VERB) \ `uvm_info(ID, {$sformatf("Phase '%0s' (id=%0d) ", \ PH.get_full_name(), PH.get_inst_id()),MSG}, VERB) function uvm_phase::new(string name="uvm_phase", uvm_phase_type phase_type=UVM_PHASE_SCHEDULE, uvm_phase parent=null); super.new(name); m_phase_type = phase_type; if ((name == "common") && (phase_type == UVM_PHASE_DOMAIN)) m_state = UVM_PHASE_DORMANT; m_run_count = 0; m_parent = parent; begin uvm_cmdline_processor clp = uvm_cmdline_processor::get_inst(); string val; if (clp.get_arg_value("+UVM_PHASE_TRACE", val)) m_phase_trace = 1; else m_phase_trace = 0; if (clp.get_arg_value("+UVM_USE_OVM_RUN_SEMANTIC", val)) m_use_ovm_run_semantic = 1; else m_use_ovm_run_semantic = 0; end if (parent == null && (phase_type == UVM_PHASE_SCHEDULE || phase_type == UVM_PHASE_DOMAIN )) begin m_end_node = new({name,"_end"}, UVM_PHASE_TERMINAL, this); this.m_successors[m_end_node] = 1; m_end_node.m_predecessors[this] = 1; end endfunction function void uvm_phase::add(uvm_phase phase, uvm_phase with_phase=null, uvm_phase after_phase=null, uvm_phase before_phase=null, uvm_phase start_with_phase=null, uvm_phase end_with_phase=null ); uvm_phase new_node, begin_node, end_node, tmp_node; uvm_phase_state_change state_chg; if (phase == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH/NULL")) uvm_report_fatal ("PH/NULL", "add: phase argument is null", UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 754, "", 1); end if (with_phase != null && with_phase.get_phase_type() == UVM_PHASE_IMP) begin string nm = with_phase.get_name(); with_phase = find(with_phase); if (with_phase == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BAD_ADD")) uvm_report_fatal ("PH_BAD_ADD", {"cannot find with_phase '",nm,"' within node '",get_name(),"'"}, UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 761, "", 1); end end if (before_phase != null && before_phase.get_phase_type() == UVM_PHASE_IMP) begin string nm = before_phase.get_name(); before_phase = find(before_phase); if (before_phase == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BAD_ADD")) uvm_report_fatal ("PH_BAD_ADD", {"cannot find before_phase '",nm,"' within node '",get_name(),"'"}, UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 769, "", 1); end end if (after_phase != null && after_phase.get_phase_type() == UVM_PHASE_IMP) begin string nm = after_phase.get_name(); after_phase = find(after_phase); if (after_phase == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BAD_ADD")) uvm_report_fatal ("PH_BAD_ADD", {"cannot find after_phase '",nm,"' within node '",get_name(),"'"}, UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 777, "", 1); end end if (start_with_phase != null && start_with_phase.get_phase_type() == UVM_PHASE_IMP) begin string nm = start_with_phase.get_name(); start_with_phase = find(start_with_phase); if (start_with_phase == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BAD_ADD")) uvm_report_fatal ("PH_BAD_ADD", {"cannot find start_with_phase '",nm,"' within node '",get_name(),"'"}, UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 785, "", 1); end end if (end_with_phase != null && end_with_phase.get_phase_type() == UVM_PHASE_IMP) begin string nm = end_with_phase.get_name(); end_with_phase = find(end_with_phase); if (end_with_phase == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BAD_ADD")) uvm_report_fatal ("PH_BAD_ADD", {"cannot find end_with_phase '",nm,"' within node '",get_name(),"'"}, UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 793, "", 1); end end if (((with_phase != null) + (after_phase != null) + (start_with_phase != null)) > 1) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BAD_ADD")) uvm_report_fatal ("PH_BAD_ADD", "only one of with_phase/after_phase/start_with_phase may be specified as they all specify predecessor", UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 798, "", 1); end if (((with_phase != null) + (before_phase != null) + (end_with_phase != null)) > 1) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BAD_ADD")) uvm_report_fatal ("PH_BAD_ADD", "only one of with_phase/before_phase/end_with_phase may be specified as they all specify successor", UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 802, "", 1); end if (before_phase == this || after_phase == m_end_node || with_phase == m_end_node || start_with_phase == m_end_node || end_with_phase == m_end_node) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BAD_ADD")) uvm_report_fatal ("PH_BAD_ADD", "cannot add before begin node, after end node, or with end nodes", UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 810, "", 1); end if (before_phase != null && after_phase != null) begin if (!after_phase.is_before(before_phase)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BAD_ADD")) uvm_report_fatal ("PH_BAD_ADD", {"Phase '",before_phase.get_name(), "' is not before phase '",after_phase.get_name(),"'"}, UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 815, "", 1); end end end if (before_phase != null && start_with_phase != null) begin if (!start_with_phase.is_before(before_phase)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BAD_ADD")) uvm_report_fatal ("PH_BAD_ADD", {"Phase '",before_phase.get_name(), "' is not before phase '",start_with_phase.get_name(),"'"}, UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 822, "", 1); end end end if (end_with_phase != null && after_phase != null) begin if (!after_phase.is_before(end_with_phase)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BAD_ADD")) uvm_report_fatal ("PH_BAD_ADD", {"Phase '",end_with_phase.get_name(), "' is not before phase '",after_phase.get_name(),"'"}, UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 829, "", 1); end end end if (phase.get_phase_type() == UVM_PHASE_IMP) begin uvm_task_phase tp; new_node = new(phase.get_name(),UVM_PHASE_NODE,this); new_node.m_imp = phase; begin_node = new_node; end_node = new_node; end else begin begin_node = phase; end_node = phase.m_end_node; phase.m_parent = this; end if (with_phase==null && after_phase==null && before_phase==null && start_with_phase==null && end_with_phase==null) begin before_phase = m_end_node; end if (m_phase_trace) begin uvm_phase_type typ = phase.get_phase_type(); begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"PH/TRC/ADD_PH")) uvm_report_info ("PH/TRC/ADD_PH", {get_name()," (",m_phase_type.name(),") ADD_PHASE: phase=",phase.get_full_name()," (", typ.name(),", inst_id=",$sformatf("%0d",phase.get_inst_id()),")", " with_phase=", (with_phase == null) ? "null" : with_phase.get_name(), " start_with_phase=", (start_with_phase == null) ? "null" : start_with_phase.get_name(), " end_with_phase=", (end_with_phase == null) ? "null" : end_with_phase.get_name(), " after_phase=", (after_phase == null) ? "null" : after_phase.get_name(), " before_phase=", (before_phase == null) ? "null" : before_phase.get_name(), " new_node=", (new_node == null) ? "null" : {new_node.get_name(), " inst_id=", $sformatf("%0d",new_node.get_inst_id())}, " begin_node=", (begin_node == null) ? "null" : begin_node.get_name(), " end_node=", (end_node == null) ? "null" : end_node.get_name()}, UVM_DEBUG, "t/uvm/src/base/uvm_phase.svh", 878, "", 1); end end if (with_phase != null) begin begin_node.m_predecessors = with_phase.m_predecessors; foreach (with_phase.m_predecessors[pred]) pred.m_successors[begin_node] = 1; end_node.m_successors = with_phase.m_successors; foreach (with_phase.m_successors[succ]) succ.m_predecessors[end_node] = 1; end if (start_with_phase != null) begin begin_node.m_predecessors = start_with_phase.m_predecessors; foreach (start_with_phase.m_predecessors[pred]) begin pred.m_successors[begin_node] = 1; end if (before_phase == null && end_with_phase == null) begin end_node.m_successors = m_end_node.m_successors ; foreach (m_end_node.m_successors[succ]) begin succ.m_predecessors[end_node] = 1; end end end if (end_with_phase != null) begin end_node.m_successors = end_with_phase.m_successors; foreach (end_with_phase.m_successors[succ]) begin succ.m_predecessors[end_node] = 1; end if (after_phase == null && start_with_phase == null) begin begin_node.m_predecessors = this.m_predecessors ; foreach (this.m_predecessors[pred]) begin pred.m_successors[begin_node] = 1; end end end if (before_phase != null) begin if (after_phase == null && start_with_phase == null) begin foreach (before_phase.m_predecessors[pred]) begin pred.m_successors.delete(before_phase); pred.m_successors[begin_node] = 1; end begin_node.m_predecessors = before_phase.m_predecessors; before_phase.m_predecessors.delete(); end else if (before_phase.m_predecessors.exists(after_phase)) begin before_phase.m_predecessors.delete(after_phase); end before_phase.m_predecessors[end_node] = 1; end_node.m_successors.delete() ; end_node.m_successors[before_phase] = 1; end if (after_phase != null) begin if (before_phase == null && end_with_phase == null) begin foreach (after_phase.m_successors[succ]) begin succ.m_predecessors.delete(after_phase); succ.m_predecessors[end_node] = 1; end end_node.m_successors = after_phase.m_successors; after_phase.m_successors.delete(); end else if (after_phase.m_successors.exists(before_phase)) begin after_phase.m_successors.delete(before_phase); end after_phase.m_successors[begin_node] = 1; begin_node.m_predecessors.delete(); begin_node.m_predecessors[after_phase] = 1; end if (new_node == null) tmp_node = phase; else tmp_node = new_node; state_chg = uvm_phase_state_change::type_id::create(tmp_node.get_name()); state_chg.m_phase = tmp_node; state_chg.m_jump_to = null; state_chg.m_prev_state = tmp_node.m_state; tmp_node.m_state = UVM_PHASE_DORMANT; begin uvm_callback_iter#(uvm_phase,uvm_phase_cb) iter = new(this); uvm_phase_cb cb = iter.first(); while(cb != null) begin cb.phase_state_change(tmp_node, state_chg); cb = iter.next(); end end endfunction function uvm_phase uvm_phase::get_parent(); return m_parent; endfunction function uvm_phase uvm_phase::get_imp(); return m_imp; endfunction function uvm_phase uvm_phase::get_schedule(bit hier=0); uvm_phase sched; sched = this; if (hier) while (sched.m_parent != null && (sched.m_parent.get_phase_type() == UVM_PHASE_SCHEDULE)) sched = sched.m_parent; if (sched.m_phase_type == UVM_PHASE_SCHEDULE) return sched; if (sched.m_phase_type == UVM_PHASE_NODE) if (m_parent != null && m_parent.m_phase_type != UVM_PHASE_DOMAIN) return m_parent; return null; endfunction function uvm_domain uvm_phase::get_domain(); uvm_phase phase; phase = this; while (phase != null && phase.m_phase_type != UVM_PHASE_DOMAIN) phase = phase.m_parent; if (phase == null) return null; if(!$cast(get_domain,phase)) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH/INTERNAL")) uvm_report_fatal ("PH/INTERNAL", "get_domain: m_phase_type is DOMAIN but $cast to uvm_domain fails", UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1035, "", 1); end endfunction function string uvm_phase::get_domain_name(); uvm_domain domain; domain = get_domain(); if (domain == null) return "unknown"; return domain.get_name(); endfunction function string uvm_phase::get_schedule_name(bit hier=0); uvm_phase sched; string s; sched = get_schedule(hier); if (sched == null) return ""; s = sched.get_name(); while (sched.m_parent != null && sched.m_parent != sched && (sched.m_parent.get_phase_type() == UVM_PHASE_SCHEDULE)) begin sched = sched.m_parent; s = {sched.get_name(),(s.len()>0?".":""),s}; end return s; endfunction function string uvm_phase::get_full_name(); string dom, sch; if (m_phase_type == UVM_PHASE_IMP) return get_name(); get_full_name = get_domain_name(); sch = get_schedule_name(); if (sch != "") get_full_name = {get_full_name, ".", sch}; if (m_phase_type != UVM_PHASE_DOMAIN && m_phase_type != UVM_PHASE_SCHEDULE) get_full_name = {get_full_name, ".", get_name()}; endfunction function uvm_phase_type uvm_phase::get_phase_type(); return m_phase_type; endfunction function void uvm_phase::set_max_ready_to_end_iterations(int max); max_ready_to_end_iters = max; endfunction function int uvm_phase::get_max_ready_to_end_iterations(); return max_ready_to_end_iters; endfunction function void uvm_phase::set_default_max_ready_to_end_iterations(int max); m_default_max_ready_to_end_iters = max; endfunction function int uvm_phase::get_default_max_ready_to_end_iterations(); return m_default_max_ready_to_end_iters; endfunction function uvm_phase_state uvm_phase::get_state(); return m_state; endfunction function int uvm_phase::get_run_count(); return m_run_count; endfunction function void uvm_phase::m_print_successors(); uvm_phase found; static string spaces = " "; static int level; if (m_phase_type == UVM_PHASE_DOMAIN) level = 0; begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"UVM/PHASE/SUCC")) uvm_report_info ("UVM/PHASE/SUCC", $sformatf("%s%s (%s) id=%0d",spaces.substr(0,level*2),get_name(), m_phase_type.name(),get_inst_id()), UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1150, "", 1); end level++; foreach (m_successors[succ]) begin succ.m_print_successors(); end level--; endfunction function uvm_phase uvm_phase::m_find_predecessor(uvm_phase phase, bit stay_in_scope=1, uvm_phase orig_phase=null); uvm_phase found; if (phase == null) begin return null ; end if (phase == m_imp || phase == this) return this; foreach (m_predecessors[pred]) begin uvm_phase orig; orig = (orig_phase==null) ? this : orig_phase; if (!stay_in_scope || (pred.get_schedule() == orig.get_schedule()) || (pred.get_domain() == orig.get_domain())) begin found = pred.m_find_predecessor(phase,stay_in_scope,orig); if (found != null) return found; end end return null; endfunction function uvm_phase uvm_phase::m_find_predecessor_by_name(string name, bit stay_in_scope=1, uvm_phase orig_phase=null); uvm_phase found; if (get_name() == name) return this; foreach (m_predecessors[pred]) begin uvm_phase orig; orig = (orig_phase==null) ? this : orig_phase; if (!stay_in_scope || (pred.get_schedule() == orig.get_schedule()) || (pred.get_domain() == orig.get_domain())) begin found = pred.m_find_predecessor_by_name(name,stay_in_scope,orig); if (found != null) return found; end end return null; endfunction function uvm_phase uvm_phase::m_find_successor(uvm_phase phase, bit stay_in_scope=1, uvm_phase orig_phase=null); uvm_phase found; if (phase == null) begin return null ; end if (phase == m_imp || phase == this) begin return this; end foreach (m_successors[succ]) begin uvm_phase orig; orig = (orig_phase==null) ? this : orig_phase; if (!stay_in_scope || (succ.get_schedule() == orig.get_schedule()) || (succ.get_domain() == orig.get_domain())) begin found = succ.m_find_successor(phase,stay_in_scope,orig); if (found != null) begin return found; end end end return null; endfunction function uvm_phase uvm_phase::m_find_successor_by_name(string name, bit stay_in_scope=1, uvm_phase orig_phase=null); uvm_phase found; if (get_name() == name) return this; foreach (m_successors[succ]) begin uvm_phase orig; orig = (orig_phase==null) ? this : orig_phase; if (!stay_in_scope || (succ.get_schedule() == orig.get_schedule()) || (succ.get_domain() == orig.get_domain())) begin found = succ.m_find_successor_by_name(name,stay_in_scope,orig); if (found != null) return found; end end return null; endfunction function uvm_phase uvm_phase::find(uvm_phase phase, bit stay_in_scope=1); if (phase == m_imp || phase == this) return phase; find = m_find_predecessor(phase,stay_in_scope,this); if (find == null) find = m_find_successor(phase,stay_in_scope,this); endfunction function uvm_phase uvm_phase::find_by_name(string name, bit stay_in_scope=1); if (get_name() == name) return this; find_by_name = m_find_predecessor_by_name(name,stay_in_scope,this); if (find_by_name == null) find_by_name = m_find_successor_by_name(name,stay_in_scope,this); endfunction function bit uvm_phase::is(uvm_phase phase); return (m_imp == phase || this == phase); endfunction function bit uvm_phase::is_before(uvm_phase phase); return (!is(phase) && m_find_successor(phase,0,this) != null); endfunction function bit uvm_phase::is_after(uvm_phase phase); return (!is(phase) && m_find_predecessor(phase,0,this) != null); endfunction task uvm_phase::execute_phase(); uvm_task_phase task_phase; uvm_root top; uvm_phase_state_change state_chg; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); foreach (m_predecessors[pred]) wait (pred.m_state == UVM_PHASE_DONE); if (m_state == UVM_PHASE_DONE) return; state_chg = uvm_phase_state_change::type_id::create(get_name()); state_chg.m_phase = this; state_chg.m_jump_to = null; state_chg.m_prev_state = m_state; m_state = UVM_PHASE_SYNCING; begin uvm_callback_iter#(uvm_phase,uvm_phase_cb) iter = new(this); uvm_phase_cb cb = iter.first(); while(cb != null) begin cb.phase_state_change(this, state_chg); cb = iter.next(); end end #0; if (m_sync.size()) begin foreach (m_sync[i]) begin wait (m_sync[i].m_state >= UVM_PHASE_SYNCING); end end m_run_count++; if (m_phase_trace) begin begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,"PH/TRC/STRT")) uvm_report_info ("PH/TRC/STRT", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),"Starting phase"}, UVM_LOW, "t/uvm/src/base/uvm_phase.svh", 1366, "", 1); end end if (m_phase_type != UVM_PHASE_NODE) begin state_chg.m_prev_state = m_state; m_state = UVM_PHASE_STARTED; begin uvm_callback_iter#(uvm_phase,uvm_phase_cb) iter = new(this); uvm_phase_cb cb = iter.first(); while(cb != null) begin cb.phase_state_change(this, state_chg); cb = iter.next(); end end #0; state_chg.m_prev_state = m_state; m_state = UVM_PHASE_EXECUTING; begin uvm_callback_iter#(uvm_phase,uvm_phase_cb) iter = new(this); uvm_phase_cb cb = iter.first(); while(cb != null) begin cb.phase_state_change(this, state_chg); cb = iter.next(); end end #0; end else begin state_chg.m_prev_state = m_state; m_state = UVM_PHASE_STARTED; begin uvm_callback_iter#(uvm_phase,uvm_phase_cb) iter = new(this); uvm_phase_cb cb = iter.first(); while(cb != null) begin cb.phase_state_change(this, state_chg); cb = iter.next(); end end m_imp.traverse(top,this,UVM_PHASE_STARTED); m_ready_to_end_count = 0 ; #0; if (!$cast(task_phase,m_imp)) begin state_chg.m_prev_state = m_state; m_state = UVM_PHASE_EXECUTING; begin uvm_callback_iter#(uvm_phase,uvm_phase_cb) iter = new(this); uvm_phase_cb cb = iter.first(); while(cb != null) begin cb.phase_state_change(this, state_chg); cb = iter.next(); end end #0; m_imp.traverse(top,this,UVM_PHASE_EXECUTING); end else begin m_executing_phases[this] = 1; state_chg.m_prev_state = m_state; m_state = UVM_PHASE_EXECUTING; begin uvm_callback_iter#(uvm_phase,uvm_phase_cb) iter = new(this); uvm_phase_cb cb = iter.first(); while(cb != null) begin cb.phase_state_change(this, state_chg); cb = iter.next(); end end fork : master_phase_process begin m_phase_proc = process::self(); task_phase.traverse(top,this,UVM_PHASE_EXECUTING); wait(0); end join_none uvm_wait_for_nba_region(); fork begin fork begin wait (m_premature_end); begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"PH/TRC/EXE/JUMP")) uvm_report_info ("PH/TRC/EXE/JUMP", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),"PHASE EXIT ON JUMP REQUEST"}, UVM_DEBUG, "t/uvm/src/base/uvm_phase.svh", 1446, "", 1); end end begin bit do_ready_to_end ; uvm_objection phase_done; phase_done = get_objection(); if (phase_done.get_objection_total(top) || m_use_ovm_run_semantic && m_imp.get_name() == "run") begin if (!phase_done.m_top_all_dropped) phase_done.wait_for(UVM_ALL_DROPPED, top); begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"PH/TRC/EXE/ALLDROP")) uvm_report_info ("PH/TRC/EXE/ALLDROP", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),"PHASE EXIT ALL_DROPPED"}, UVM_DEBUG, "t/uvm/src/base/uvm_phase.svh", 1459, "", 1); end end else begin if (m_phase_trace) begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,"PH/TRC/SKIP")) uvm_report_info ("PH/TRC/SKIP", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),"No objections raised, skipping phase"}, UVM_LOW, "t/uvm/src/base/uvm_phase.svh", 1462, "", 1); end end wait_for_self_and_siblings_to_drop() ; do_ready_to_end = 1; while (do_ready_to_end) begin uvm_wait_for_nba_region(); begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"PH_READY_TO_END")) uvm_report_info ("PH_READY_TO_END", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),"PHASE READY TO END"}, UVM_DEBUG, "t/uvm/src/base/uvm_phase.svh", 1474, "", 1); end m_ready_to_end_count++; if (m_phase_trace) begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"PH_READY_TO_END_CB")) uvm_report_info ("PH_READY_TO_END_CB", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),"CALLING READY_TO_END CB"}, UVM_HIGH, "t/uvm/src/base/uvm_phase.svh", 1477, "", 1); end state_chg.m_prev_state = m_state; m_state = UVM_PHASE_READY_TO_END; begin uvm_callback_iter#(uvm_phase,uvm_phase_cb) iter = new(this); uvm_phase_cb cb = iter.first(); while(cb != null) begin cb.phase_state_change(this, state_chg); cb = iter.next(); end end if (m_imp != null) m_imp.traverse(top,this,UVM_PHASE_READY_TO_END); uvm_wait_for_nba_region(); wait_for_self_and_siblings_to_drop(); do_ready_to_end = (m_state == UVM_PHASE_EXECUTING) && (m_ready_to_end_count < get_max_ready_to_end_iterations()) ; end end begin if (this.get_name() == "run") begin if (top.phase_timeout == 0) wait(top.phase_timeout != 0); if (m_phase_trace) begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"PH/TRC/TO_WAIT")) uvm_report_info ("PH/TRC/TO_WAIT", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),$sformatf("STARTING PHASE TIMEOUT WATCHDOG (timeout == %t)", top.phase_timeout)}, UVM_HIGH, "t/uvm/src/base/uvm_phase.svh", 1497, "", 1); end #(top.phase_timeout); if ($time == 9200s) begin if (m_phase_trace) begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,"PH/TRC/TIMEOUT")) uvm_report_info ("PH/TRC/TIMEOUT", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),"PHASE TIMEOUT WATCHDOG EXPIRED"}, UVM_LOW, "t/uvm/src/base/uvm_phase.svh", 1501, "", 1); end foreach (m_executing_phases[p]) begin uvm_objection p_phase_done; p_phase_done = p.get_objection(); if ((p_phase_done != null) && (p_phase_done.get_objection_total() > 0)) begin if (m_phase_trace) begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,"PH/TRC/TIMEOUT/OBJCTN")) uvm_report_info ("PH/TRC/TIMEOUT/OBJCTN", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),$sformatf("Phase '%s' has outstanding objections:\n%s", p.get_full_name(), p_phase_done.convert2string())}, UVM_LOW, "t/uvm/src/base/uvm_phase.svh", 1510, "", 1); end end end begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_TIMEOUT")) uvm_report_fatal ("PH_TIMEOUT", $sformatf("Default timeout of %0t hit, indicating a probable testbench issue", 9200s), UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1516, "", 1); end end else begin if (m_phase_trace) begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,"PH/TRC/TIMEOUT")) uvm_report_info ("PH/TRC/TIMEOUT", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),"PHASE TIMEOUT WATCHDOG EXPIRED"}, UVM_LOW, "t/uvm/src/base/uvm_phase.svh", 1520, "", 1); end foreach (m_executing_phases[p]) begin uvm_objection p_phase_done; p_phase_done = p.get_objection(); if ((p_phase_done != null) && (p_phase_done.get_objection_total() > 0)) begin if (m_phase_trace) begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,"PH/TRC/TIMEOUT/OBJCTN")) uvm_report_info ("PH/TRC/TIMEOUT/OBJCTN", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),$sformatf("Phase '%s' has outstanding objections:\n%s", p.get_full_name(), p_phase_done.convert2string())}, UVM_LOW, "t/uvm/src/base/uvm_phase.svh", 1529, "", 1); end end end begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_TIMEOUT")) uvm_report_fatal ("PH_TIMEOUT", $sformatf("Explicit timeout of %0t hit, indicating a probable testbench issue", top.phase_timeout), UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1535, "", 1); end end if (m_phase_trace) begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"PH/TRC/EXE/3")) uvm_report_info ("PH/TRC/EXE/3", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),"PHASE EXIT TIMEOUT"}, UVM_DEBUG, "t/uvm/src/base/uvm_phase.svh", 1538, "", 1); end end else begin wait (0); end end join_any disable fork; end join end end m_executing_phases.delete(this); if (m_phase_type == UVM_PHASE_NODE) begin if(m_premature_end) begin if(m_jump_phase != null) begin state_chg.m_jump_to = m_jump_phase; begin if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"PH_JUMP")) uvm_report_info ("PH_JUMP", $sformatf("phase %s (schedule %s, domain %s) is jumping to phase %s", get_name(), get_schedule_name(), get_domain_name(), m_jump_phase.get_name()), UVM_MEDIUM, "t/uvm/src/base/uvm_phase.svh", 1582, "", 1); end end else begin begin if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"PH_JUMP")) uvm_report_info ("PH_JUMP", $sformatf("phase %s (schedule %s, domain %s) is ending prematurely", get_name(), get_schedule_name(), get_domain_name()), UVM_MEDIUM, "t/uvm/src/base/uvm_phase.svh", 1588, "", 1); end end #0; if (m_phase_trace) begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"PH_END")) uvm_report_info ("PH_END", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),"ENDING PHASE PREMATURELY"}, UVM_HIGH, "t/uvm/src/base/uvm_phase.svh", 1594, "", 1); end end else begin if (task_phase == null) m_wait_for_pred(); end if (m_phase_trace) begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"PH_END")) uvm_report_info ("PH_END", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),"ENDING PHASE"}, UVM_HIGH, "t/uvm/src/base/uvm_phase.svh", 1608, "", 1); end state_chg.m_prev_state = m_state; m_state = UVM_PHASE_ENDED; begin uvm_callback_iter#(uvm_phase,uvm_phase_cb) iter = new(this); uvm_phase_cb cb = iter.first(); while(cb != null) begin cb.phase_state_change(this, state_chg); cb = iter.next(); end end if (m_imp != null) m_imp.traverse(top,this,UVM_PHASE_ENDED); #0; state_chg.m_prev_state = m_state; if(m_premature_end) m_state = UVM_PHASE_JUMPING; else m_state = UVM_PHASE_CLEANUP ; begin uvm_callback_iter#(uvm_phase,uvm_phase_cb) iter = new(this); uvm_phase_cb cb = iter.first(); while(cb != null) begin cb.phase_state_change(this, state_chg); cb = iter.next(); end end if (m_phase_proc != null) begin m_phase_proc.kill(); m_phase_proc = null; end #0; begin uvm_objection objection = get_objection(); if (objection != null) objection.clear(); end end m_premature_end = 0 ; if(m_jump_fwd || m_jump_bkwd) begin if(m_jump_fwd) begin clear_successors(UVM_PHASE_DONE,m_jump_phase); end m_jump_phase.clear_successors(); end else begin if (m_phase_trace) begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,"PH/TRC/DONE")) uvm_report_info ("PH/TRC/DONE", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),"Completed phase"}, UVM_LOW, "t/uvm/src/base/uvm_phase.svh", 1650, "", 1); end state_chg.m_prev_state = m_state; m_state = UVM_PHASE_DONE; begin uvm_callback_iter#(uvm_phase,uvm_phase_cb) iter = new(this); uvm_phase_cb cb = iter.first(); while(cb != null) begin cb.phase_state_change(this, state_chg); cb = iter.next(); end end m_phase_proc = null; #0; end #0; begin uvm_objection objection; objection = get_objection(); if (objection != null) objection.clear(); end if(m_jump_fwd || m_jump_bkwd) begin void'(m_phase_hopper.try_put(m_jump_phase)); m_jump_phase = null; m_jump_fwd = 0; m_jump_bkwd = 0; end else if (m_successors.size() == 0) begin top.m_phase_all_done=1; end else begin foreach (m_successors[succ]) begin if(succ.m_state < UVM_PHASE_SCHEDULED) begin state_chg.m_prev_state = succ.m_state; state_chg.m_phase = succ; succ.m_state = UVM_PHASE_SCHEDULED; begin uvm_callback_iter#(uvm_phase,uvm_phase_cb) iter = new(this); uvm_phase_cb cb = iter.first(); while(cb != null) begin cb.phase_state_change(succ, state_chg); cb = iter.next(); end end #0; void'(m_phase_hopper.try_put(succ)); if (m_phase_trace) begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,"PH/TRC/SCHEDULED")) uvm_report_info ("PH/TRC/SCHEDULED", {$sformatf("Phase '%0s' (id=%0d) ", succ.get_full_name(), succ.get_inst_id()),{"Scheduled from phase ",get_full_name()}}, UVM_LOW, "t/uvm/src/base/uvm_phase.svh", 1689, "", 1); end end end end endtask function void uvm_phase::get_adjacent_predecessor_nodes(ref uvm_phase pred[]); bit done; bit predecessors[uvm_phase]; int idx; foreach (m_predecessors[p]) predecessors[p] = 1; do begin done = 1; foreach (predecessors[p]) begin if (p.get_phase_type() != UVM_PHASE_NODE) begin predecessors.delete(p); foreach (p.m_predecessors[next_p]) predecessors[next_p] = 1; done = 0; end end end while (!done); pred = new [predecessors.size()]; foreach (predecessors[p]) begin pred[idx++] = p; end endfunction : get_adjacent_predecessor_nodes function void uvm_phase::get_adjacent_successor_nodes(ref uvm_phase succ[]); bit done; bit successors[uvm_phase]; int idx; foreach (m_successors[s]) successors[s] = 1; do begin done = 1; foreach (successors[s]) begin if (s.get_phase_type() != UVM_PHASE_NODE) begin successors.delete(s); foreach (s.m_successors[next_s]) successors[next_s] = 1; done = 0; end end end while (!done); succ = new [successors.size()]; foreach (successors[s]) begin succ[idx++] = s; end endfunction : get_adjacent_successor_nodes function void uvm_phase::get_predecessors_for_successors(output bit pred_of_succ[uvm_phase]); bit done; uvm_phase successors[]; get_adjacent_successor_nodes(successors); foreach (successors[s]) foreach (successors[s].m_predecessors[pred]) pred_of_succ[pred] = 1; do begin done=1; foreach (pred_of_succ[pred]) begin if (pred.get_phase_type() != UVM_PHASE_NODE) begin pred_of_succ.delete(pred); foreach (pred.m_predecessors[next_pred]) pred_of_succ[next_pred] = 1; done =0; end end end while (!done); pred_of_succ.delete(this); endfunction task uvm_phase::m_wait_for_pred(); bit pred_of_succ[uvm_phase]; get_predecessors_for_successors(pred_of_succ); foreach (pred_of_succ[sibling]) begin if (m_phase_trace) begin string s; s = $sformatf("Waiting for phase '%s' (%0d) to be READY_TO_END. Current state is %s", sibling.get_name(),sibling.get_inst_id(),sibling.m_state.name()); begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"PH/TRC/WAIT_PRED_OF_SUCC")) uvm_report_info ("PH/TRC/WAIT_PRED_OF_SUCC", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),s}, UVM_HIGH, "t/uvm/src/base/uvm_phase.svh", 1803, "", 1); end end sibling.wait_for_state(UVM_PHASE_READY_TO_END, UVM_GTE); if (m_phase_trace) begin string s; s = $sformatf("Phase '%s' (%0d) is now READY_TO_END. Releasing phase", sibling.get_name(),sibling.get_inst_id()); begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"PH/TRC/WAIT_PRED_OF_SUCC")) uvm_report_info ("PH/TRC/WAIT_PRED_OF_SUCC", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),s}, UVM_HIGH, "t/uvm/src/base/uvm_phase.svh", 1812, "", 1); end end end if (m_phase_trace) begin if (pred_of_succ.num()) begin string s = "( "; foreach (pred_of_succ[pred]) s = {s, pred.get_full_name()," "}; s = {s, ")"}; begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"PH/TRC/WAIT_PRED_OF_SUCC")) uvm_report_info ("PH/TRC/WAIT_PRED_OF_SUCC", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),{"*** All pred to succ ",s," in READY_TO_END state, so ending phase ***"}}, UVM_HIGH, "t/uvm/src/base/uvm_phase.svh", 1824, "", 1); end end else begin begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"PH/TRC/WAIT_PRED_OF_SUCC")) uvm_report_info ("PH/TRC/WAIT_PRED_OF_SUCC", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),"*** No pred to succ other than myself, so ending phase ***"}, UVM_HIGH, "t/uvm/src/base/uvm_phase.svh", 1828, "", 1); end end end #0; endtask function void uvm_phase::m_report_null_objection(uvm_object obj, string description, int count, string action); string m_action; string m_addon; string m_obj_name = (obj == null) ? "uvm_top" : obj.get_full_name(); if ((action == "raise") || (action == "drop")) begin if (count != 1) m_action = $sformatf("%s %0d objections", action, count); else m_action = $sformatf("%s an objection", action); end else if (action == "get_objection_count") begin m_action = "call get_objection_count"; end if (this.get_phase_type() == UVM_PHASE_IMP) begin m_addon = " (This is a UVM_PHASE_IMP, you have to query the schedule to find the UVM_PHASE_NODE)"; end begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/PH/NULL_OBJECTION")) uvm_report_error ("UVM/PH/NULL_OBJECTION", $sformatf("'%s' attempted to %s on '%s', however '%s' is not a task-based phase node! %s", m_obj_name, m_action, get_name(), get_name(), m_addon), UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1869, "", 1); end endfunction : m_report_null_objection function void uvm_phase::raise_objection (uvm_object obj, string description="", int count=1); uvm_objection phase_done; phase_done = get_objection(); if (phase_done != null) phase_done.raise_objection(obj,description,count); else m_report_null_objection(obj, description, count, "raise"); endfunction function void uvm_phase::drop_objection (uvm_object obj, string description="", int count=1); uvm_objection phase_done; phase_done = get_objection(); if (phase_done != null) phase_done.drop_objection(obj,description,count); else m_report_null_objection(obj, description, count, "drop"); endfunction function int uvm_phase::get_objection_count (uvm_object obj=null); uvm_objection phase_done; phase_done = get_objection(); if (phase_done != null) return phase_done.get_objection_count(obj); else begin m_report_null_objection(obj, "" , 0, "get_objection_count"); return 0; end endfunction : get_objection_count function void uvm_phase::sync(uvm_domain target, uvm_phase phase=null, uvm_phase with_phase=null); if (!this.is_domain()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BADSYNC")) uvm_report_fatal ("PH_BADSYNC", "sync() called from a non-domain phase schedule node", UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1923, "", 1); end end else if (target == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BADSYNC")) uvm_report_fatal ("PH_BADSYNC", "sync() called with a null target domain", UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1926, "", 1); end end else if (!target.is_domain()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BADSYNC")) uvm_report_fatal ("PH_BADSYNC", "sync() called with a non-domain phase schedule node as target", UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1929, "", 1); end end else if (phase == null && with_phase != null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BADSYNC")) uvm_report_fatal ("PH_BADSYNC", "sync() called with null phase and non-null with phase", UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1932, "", 1); end end else if (phase == null) begin int visited[uvm_phase]; uvm_phase queue[$]; queue.push_back(this); visited[this] = 1; while (queue.size()) begin uvm_phase node; node = queue.pop_front(); if (node.m_imp != null) begin sync(target, node.m_imp); end foreach (node.m_successors[succ]) begin if (!visited.exists(succ)) begin queue.push_back(succ); visited[succ] = 1; end end end end else begin uvm_phase from_node, to_node; int found_to[$], found_from[$]; if(with_phase == null) with_phase = phase; from_node = find(phase); to_node = target.find(with_phase); if(from_node == null || to_node == null) return; found_to = from_node.m_sync.find_index(node) with (node == to_node); found_from = to_node.m_sync.find_index(node) with (node == from_node); if (found_to.size() == 0) from_node.m_sync.push_back(to_node); if (found_from.size() == 0) to_node.m_sync.push_back(from_node); end endfunction function void uvm_phase::unsync(uvm_domain target, uvm_phase phase=null, uvm_phase with_phase=null); if (!this.is_domain()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BADSYNC")) uvm_report_fatal ("PH_BADSYNC", "unsync() called from a non-domain phase schedule node", UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1977, "", 1); end end else if (target == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BADSYNC")) uvm_report_fatal ("PH_BADSYNC", "unsync() called with a null target domain", UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1979, "", 1); end end else if (!target.is_domain()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BADSYNC")) uvm_report_fatal ("PH_BADSYNC", "unsync() called with a non-domain phase schedule node as target", UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1981, "", 1); end end else if (phase == null && with_phase != null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BADSYNC")) uvm_report_fatal ("PH_BADSYNC", "unsync() called with null phase and non-null with phase", UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1983, "", 1); end end else if (phase == null) begin int visited[uvm_phase]; uvm_phase queue[$]; queue.push_back(this); visited[this] = 1; while (queue.size()) begin uvm_phase node; node = queue.pop_front(); if (node.m_imp != null) unsync(target,node.m_imp); foreach (node.m_successors[succ]) begin if (!visited.exists(succ)) begin queue.push_back(succ); visited[succ] = 1; end end end end else begin uvm_phase from_node, to_node; int found_to[$], found_from[$]; if(with_phase == null) with_phase = phase; from_node = find(phase); to_node = target.find(with_phase); if(from_node == null || to_node == null) return; found_to = from_node.m_sync.find_index(node) with (node == to_node); found_from = to_node.m_sync.find_index(node) with (node == from_node); if (found_to.size()) from_node.m_sync.delete(found_to[0]); if (found_from.size()) to_node.m_sync.delete(found_from[0]); end endfunction task uvm_phase::wait_for_state(uvm_phase_state state, uvm_wait_op op=UVM_EQ); case (op) UVM_EQ: wait((state&m_state) != 0); UVM_NE: wait((state&m_state) == 0); UVM_LT: wait(m_state < state); UVM_LTE: wait(m_state <= state); UVM_GT: wait(m_state > state); UVM_GTE: wait(m_state >= state); endcase endtask function void uvm_phase::set_jump_phase(uvm_phase phase) ; uvm_phase d; if ((m_state < UVM_PHASE_STARTED) || (m_state > UVM_PHASE_ENDED) ) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"JMPPHIDL")) uvm_report_error ("JMPPHIDL", { "Attempting to jump from phase \"", get_name(), "\" which is not currently active (current state is ", m_state.name(), "). The jump will not happen until the phase becomes ", "active."}, UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 2051, "", 1); end end d = m_find_predecessor(phase,0); if (d == null) begin d = m_find_successor(phase,0); if (d == null) begin string msg; $sformat(msg,{"phase %s is neither a predecessor or successor of ", "phase %s or is non-existant, so we cannot jump to it. ", "Phase control flow is now undefined so the simulation ", "must terminate"}, phase.get_name(), get_name()); begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BADJUMP")) uvm_report_fatal ("PH_BADJUMP", msg, UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 2077, "", 1); end end else begin m_jump_fwd = 1; begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"PH_JUMPF")) uvm_report_info ("PH_JUMPF", $sformatf("jumping forward to phase %s", phase.get_name()), UVM_DEBUG, "t/uvm/src/base/uvm_phase.svh", 2082, "", 1); end end end else begin m_jump_bkwd = 1; begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"PH_JUMPB")) uvm_report_info ("PH_JUMPB", $sformatf("jumping backward to phase %s", phase.get_name()), UVM_DEBUG, "t/uvm/src/base/uvm_phase.svh", 2088, "", 1); end end m_jump_phase = d; endfunction function void uvm_phase::end_prematurely() ; m_premature_end = 1 ; endfunction function void uvm_phase::jump(uvm_phase phase); set_jump_phase(phase) ; end_prematurely() ; endfunction function void uvm_phase::jump_all(uvm_phase phase); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"NOTIMPL")) uvm_report_warning ("NOTIMPL", "uvm_phase::jump_all is not implemented and has been replaced by uvm_domain::jump_all", UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 2120, "", 1); end endfunction function uvm_phase uvm_phase::get_jump_target(); return m_jump_phase; endfunction function void uvm_phase::clear(uvm_phase_state state = UVM_PHASE_DORMANT); uvm_objection phase_done; phase_done = get_objection(); m_state = state; m_phase_proc = null; if (phase_done != null) phase_done.clear(this); endfunction function void uvm_phase::clear_successors(uvm_phase_state state = UVM_PHASE_DORMANT, uvm_phase end_state=null); if(this == end_state) return; clear(state); foreach(m_successors[succ]) begin succ.clear_successors(state, end_state); end endfunction task uvm_phase::wait_for_self_and_siblings_to_drop() ; bit need_to_check_all = 1 ; uvm_root top; uvm_coreservice_t cs; bit siblings[uvm_phase]; cs = uvm_coreservice_t::get(); top = cs.get_root(); get_predecessors_for_successors(siblings); foreach (m_sync[i]) begin siblings[m_sync[i]] = 1; end while (need_to_check_all) begin uvm_objection phase_done; phase_done = get_objection(); need_to_check_all = 0 ; if ((phase_done != null) && (phase_done.get_objection_total(top) != 0)) begin m_state = UVM_PHASE_EXECUTING ; phase_done.wait_for(UVM_ALL_DROPPED, top); need_to_check_all = 1 ; end foreach(siblings[sib]) begin uvm_objection sib_phase_done; sib_phase_done = sib.get_objection(); sib.wait_for_state(UVM_PHASE_EXECUTING, UVM_GTE); if ((sib_phase_done != null) && (sib_phase_done.get_objection_total(top) != 0)) begin m_state = UVM_PHASE_EXECUTING ; sib_phase_done.wait_for(UVM_ALL_DROPPED, top); need_to_check_all = 1 ; end end end endtask function void uvm_phase::kill(); begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"PH_KILL")) uvm_report_info ("PH_KILL", {"killing phase '", get_name(),"'"}, UVM_DEBUG, "t/uvm/src/base/uvm_phase.svh", 2214, "", 1); end if (m_phase_proc != null) begin m_phase_proc.kill(); m_phase_proc = null; end endfunction function void uvm_phase::kill_successors(); foreach (m_successors[succ]) succ.kill_successors(); kill(); endfunction task uvm_phase::m_run_phases(); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); begin uvm_phase ph = uvm_domain::get_common_domain(); void'(m_phase_hopper.try_put(ph)); end m_uvm_core_state=UVM_CORE_RUNNING; forever begin uvm_phase phase; m_phase_hopper.get(phase); fork begin phase.execute_phase(); end join_none #0; end endtask function void uvm_phase::m_terminate_phase(); uvm_objection phase_done; phase_done = get_objection(); if (phase_done != null) phase_done.clear(this); endfunction function void uvm_phase::m_print_termination_state(); uvm_root top; uvm_coreservice_t cs; uvm_objection phase_done; phase_done = get_objection(); cs = uvm_coreservice_t::get(); top = cs.get_root(); if (phase_done != null) begin begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"PH_TERMSTATE")) uvm_report_info ("PH_TERMSTATE", $sformatf("phase %s outstanding objections = %0d", get_name(), phase_done.get_objection_total(top)), UVM_DEBUG, "t/uvm/src/base/uvm_phase.svh", 2293, "", 1); end end else begin begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"PH_TERMSTATE")) uvm_report_info ("PH_TERMSTATE", $sformatf("phase %s has no outstanding objections", get_name()), UVM_DEBUG, "t/uvm/src/base/uvm_phase.svh", 2299, "", 1); end end endfunction typedef class uvm_build_phase; typedef class uvm_connect_phase; typedef class uvm_end_of_elaboration_phase; typedef class uvm_start_of_simulation_phase; typedef class uvm_run_phase; typedef class uvm_extract_phase; typedef class uvm_check_phase; typedef class uvm_report_phase; typedef class uvm_final_phase; typedef class uvm_pre_reset_phase; typedef class uvm_reset_phase; typedef class uvm_post_reset_phase; typedef class uvm_pre_configure_phase; typedef class uvm_configure_phase; typedef class uvm_post_configure_phase; typedef class uvm_pre_main_phase; typedef class uvm_main_phase; typedef class uvm_post_main_phase; typedef class uvm_pre_shutdown_phase; typedef class uvm_shutdown_phase; typedef class uvm_post_shutdown_phase; uvm_phase build_ph; uvm_phase connect_ph; uvm_phase end_of_elaboration_ph; uvm_phase start_of_simulation_ph; uvm_phase run_ph; uvm_phase extract_ph; uvm_phase check_ph; uvm_phase report_ph; class uvm_domain extends uvm_phase; static local uvm_domain m_uvm_domain; static local uvm_domain m_domains[string]; static local uvm_phase m_uvm_schedule; static function void get_domains(output uvm_domain domains[string]); domains = m_domains; endfunction static function uvm_phase get_uvm_schedule(); void'(get_uvm_domain()); return m_uvm_schedule; endfunction static function uvm_domain get_common_domain(); uvm_domain domain; if(m_domains.exists("common")) domain = m_domains["common"]; if (domain != null) return domain; domain = new("common"); domain.add(uvm_build_phase::get()); domain.add(uvm_connect_phase::get()); domain.add(uvm_end_of_elaboration_phase::get()); domain.add(uvm_start_of_simulation_phase::get()); domain.add(uvm_run_phase::get()); domain.add(uvm_extract_phase::get()); domain.add(uvm_check_phase::get()); domain.add(uvm_report_phase::get()); domain.add(uvm_final_phase::get()); build_ph = domain.find(uvm_build_phase::get()); connect_ph = domain.find(uvm_connect_phase::get()); end_of_elaboration_ph = domain.find(uvm_end_of_elaboration_phase::get()); start_of_simulation_ph = domain.find(uvm_start_of_simulation_phase::get()); run_ph = domain.find(uvm_run_phase::get()); extract_ph = domain.find(uvm_extract_phase::get()); check_ph = domain.find(uvm_check_phase::get()); report_ph = domain.find(uvm_report_phase::get()); domain = get_uvm_domain(); m_domains["common"].add(domain, .with_phase(m_domains["common"].find(uvm_run_phase::get()))); return m_domains["common"]; endfunction static function void add_uvm_phases(uvm_phase schedule); schedule.add(uvm_pre_reset_phase::get()); schedule.add(uvm_reset_phase::get()); schedule.add(uvm_post_reset_phase::get()); schedule.add(uvm_pre_configure_phase::get()); schedule.add(uvm_configure_phase::get()); schedule.add(uvm_post_configure_phase::get()); schedule.add(uvm_pre_main_phase::get()); schedule.add(uvm_main_phase::get()); schedule.add(uvm_post_main_phase::get()); schedule.add(uvm_pre_shutdown_phase::get()); schedule.add(uvm_shutdown_phase::get()); schedule.add(uvm_post_shutdown_phase::get()); endfunction static function uvm_domain get_uvm_domain(); if (m_uvm_domain == null) begin m_uvm_domain = new("uvm"); m_uvm_schedule = new("uvm_sched", UVM_PHASE_SCHEDULE); add_uvm_phases(m_uvm_schedule); m_uvm_domain.add(m_uvm_schedule); end return m_uvm_domain; endfunction function new(string name); super.new(name,UVM_PHASE_DOMAIN); if (m_domains.exists(name)) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UNIQDOMNAM")) uvm_report_error ("UNIQDOMNAM", $sformatf("Domain created with non-unique name '%s'", name), UVM_NONE, "t/uvm/src/base/uvm_domain.svh", 183, "", 1); end m_domains[name] = this; endfunction function void jump(uvm_phase phase); uvm_phase phases[$]; m_get_transitive_children(phases); phases = phases.find(item) with (item.get_state() inside {[UVM_PHASE_STARTED:UVM_PHASE_CLEANUP]}); foreach(phases[idx]) if(phases[idx].is_before(phase) || phases[idx].is_after(phase)) phases[idx].jump(phase); endfunction static function void jump_all(uvm_phase phase); uvm_domain domains[string]; uvm_domain::get_domains(domains); foreach(domains[idx]) domains[idx].jump(phase); endfunction endclass virtual class uvm_bottomup_phase extends uvm_phase; function new(string name); super.new(name,UVM_PHASE_IMP); endfunction virtual function void traverse(uvm_component comp, uvm_phase phase, uvm_phase_state state); string name; uvm_domain phase_domain =phase.get_domain(); uvm_domain comp_domain = comp.get_domain(); if (comp.get_first_child(name)) do traverse(comp.get_child(name), phase, state); while(comp.get_next_child(name)); if (m_phase_trace) begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"PH_TRACE")) uvm_report_info ("PH_TRACE", $sformatf("bottomup-phase phase=%s state=%s comp=%s comp.domain=%s phase.domain=%s", phase.get_name(), state.name(), comp.get_full_name(),comp_domain.get_name(),phase_domain.get_name()), UVM_DEBUG, "t/uvm/src/base/uvm_bottomup_phase.svh", 64, "", 1); end if (phase_domain == uvm_domain::get_common_domain() || phase_domain == comp_domain) begin case (state) UVM_PHASE_STARTED: begin comp.m_current_phase = phase; comp.m_apply_verbosity_settings(phase); comp.phase_started(phase); end UVM_PHASE_EXECUTING: begin uvm_phase ph = this; if (comp.m_phase_imps.exists(this)) ph = comp.m_phase_imps[this]; ph.execute(comp, phase); end UVM_PHASE_READY_TO_END: begin comp.phase_ready_to_end(phase); end UVM_PHASE_ENDED: begin comp.phase_ended(phase); comp.m_current_phase = null; end default: begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BADEXEC")) uvm_report_fatal ("PH_BADEXEC", "bottomup phase traverse internal error", UVM_NONE, "t/uvm/src/base/uvm_bottomup_phase.svh", 88, "", 1); end endcase end endfunction virtual function void execute(uvm_component comp, uvm_phase phase); process proc = process::self(); proc.srandom(uvm_create_random_seed(phase.get_type_name(), comp.get_full_name())); comp.m_current_phase = phase; exec_func(comp,phase); endfunction endclass virtual class uvm_topdown_phase extends uvm_phase; function new(string name); super.new(name,UVM_PHASE_IMP); endfunction virtual function void traverse(uvm_component comp, uvm_phase phase, uvm_phase_state state); string name; uvm_domain phase_domain = phase.get_domain(); uvm_domain comp_domain = comp.get_domain(); if (m_phase_trace) begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"PH_TRACE")) uvm_report_info ("PH_TRACE", $sformatf("topdown-phase phase=%s state=%s comp=%s comp.domain=%s phase.domain=%s", phase.get_name(), state.name(), comp.get_full_name(),comp_domain.get_name(),phase_domain.get_name()), UVM_DEBUG, "t/uvm/src/base/uvm_topdown_phase.svh", 59, "", 1); end if (phase_domain == uvm_domain::get_common_domain() || phase_domain == comp_domain) begin case (state) UVM_PHASE_STARTED: begin comp.m_current_phase = phase; comp.m_apply_verbosity_settings(phase); comp.phase_started(phase); end UVM_PHASE_EXECUTING: begin if (!(phase.get_name() == "build" && comp.m_build_done)) begin uvm_phase ph = this; comp.m_phasing_active++; if (comp.m_phase_imps.exists(this)) ph = comp.m_phase_imps[this]; ph.execute(comp, phase); comp.m_phasing_active--; end end UVM_PHASE_READY_TO_END: begin comp.phase_ready_to_end(phase); end UVM_PHASE_ENDED: begin comp.phase_ended(phase); comp.m_current_phase = null; end default: begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BADEXEC")) uvm_report_fatal ("PH_BADEXEC", "topdown phase traverse internal error", UVM_NONE, "t/uvm/src/base/uvm_topdown_phase.svh", 87, "", 1); end endcase end if(comp.get_first_child(name)) do traverse(comp.get_child(name), phase, state); while(comp.get_next_child(name)); endfunction virtual function void execute(uvm_component comp, uvm_phase phase); process proc = process::self(); proc.srandom(uvm_create_random_seed(phase.get_type_name(), comp.get_full_name())); comp.m_current_phase = phase; exec_func(comp,phase); endfunction endclass virtual class uvm_task_phase extends uvm_phase; function new(string name); super.new(name,UVM_PHASE_IMP); endfunction virtual function void traverse(uvm_component comp, uvm_phase phase, uvm_phase_state state); phase.m_num_procs_not_yet_returned = 0; m_traverse(comp, phase, state); endfunction function void m_traverse(uvm_component comp, uvm_phase phase, uvm_phase_state state); string name; uvm_domain phase_domain =phase.get_domain(); uvm_domain comp_domain = comp.get_domain(); uvm_sequencer_base seqr; if (comp.get_first_child(name)) do m_traverse(comp.get_child(name), phase, state); while(comp.get_next_child(name)); if (m_phase_trace) begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"PH_TRACE")) uvm_report_info ("PH_TRACE", $sformatf("topdown-phase phase=%s state=%s comp=%s comp.domain=%s phase.domain=%s", phase.get_name(), state.name(), comp.get_full_name(),comp_domain.get_name(),phase_domain.get_name()), UVM_DEBUG, "t/uvm/src/base/uvm_task_phase.svh", 94, "", 1); end if (phase_domain == uvm_domain::get_common_domain() || phase_domain == comp_domain) begin case (state) UVM_PHASE_STARTED: begin comp.m_current_phase = phase; comp.m_apply_verbosity_settings(phase); comp.phase_started(phase); if ($cast(seqr, comp)) seqr.start_phase_sequence(phase); end UVM_PHASE_EXECUTING: begin uvm_phase ph = this; if (comp.m_phase_imps.exists(this)) ph = comp.m_phase_imps[this]; ph.execute(comp, phase); end UVM_PHASE_READY_TO_END: begin comp.phase_ready_to_end(phase); end UVM_PHASE_ENDED: begin if ($cast(seqr, comp)) seqr.stop_phase_sequence(phase); comp.phase_ended(phase); comp.m_current_phase = null; end default: begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BADEXEC")) uvm_report_fatal ("PH_BADEXEC", "task phase traverse internal error", UVM_NONE, "t/uvm/src/base/uvm_task_phase.svh", 122, "", 1); end endcase end endfunction virtual function void execute(uvm_component comp, uvm_phase phase); fork begin process proc; proc = process::self(); proc.srandom(uvm_create_random_seed(phase.get_type_name(), comp.get_full_name())); phase.m_num_procs_not_yet_returned++; exec_task(comp,phase); phase.m_num_procs_not_yet_returned--; end join_none endfunction endclass class uvm_build_phase extends uvm_topdown_phase; virtual function void exec_func(uvm_component comp, uvm_phase phase); comp.build_phase(phase); endfunction local static uvm_build_phase m_inst; static function string type_name(); return "uvm_build_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_build_phase"; endfunction : get_type_name static function uvm_build_phase get(); if(m_inst == null) m_inst = new(); return m_inst; endfunction protected function new(string name="build"); super.new(name); endfunction endclass class uvm_connect_phase extends uvm_bottomup_phase; virtual function void exec_func(uvm_component comp, uvm_phase phase); comp.connect_phase(phase); endfunction local static uvm_connect_phase m_inst; static function string type_name(); return "uvm_connect_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_connect_phase"; endfunction : get_type_name static function uvm_connect_phase get(); if(m_inst == null) m_inst = new(); return m_inst; endfunction protected function new(string name="connect"); super.new(name); endfunction endclass class uvm_end_of_elaboration_phase extends uvm_bottomup_phase; virtual function void exec_func(uvm_component comp, uvm_phase phase); comp.end_of_elaboration_phase(phase); endfunction local static uvm_end_of_elaboration_phase m_inst; static function string type_name(); return "uvm_end_of_elaboration_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_end_of_elaboration_phase"; endfunction : get_type_name static function uvm_end_of_elaboration_phase get(); if(m_inst == null) begin m_inst = new(); end return m_inst; endfunction protected function new(string name="end_of_elaboration"); super.new(name); endfunction endclass class uvm_start_of_simulation_phase extends uvm_bottomup_phase; virtual function void exec_func(uvm_component comp, uvm_phase phase); comp.start_of_simulation_phase(phase); endfunction local static uvm_start_of_simulation_phase m_inst; static function string type_name(); return "uvm_start_of_simulation_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_start_of_simulation_phase"; endfunction : get_type_name static function uvm_start_of_simulation_phase get(); if(m_inst == null) m_inst = new(); return m_inst; endfunction protected function new(string name="start_of_simulation"); super.new(name); endfunction endclass class uvm_run_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.run_phase(phase); endtask local static uvm_run_phase m_inst; static function string type_name(); return "uvm_run_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_run_phase"; endfunction : get_type_name static function uvm_run_phase get(); if(m_inst == null) m_inst = new; return m_inst; endfunction protected function new(string name="run"); super.new(name); endfunction endclass class uvm_extract_phase extends uvm_bottomup_phase; virtual function void exec_func(uvm_component comp, uvm_phase phase); comp.extract_phase(phase); endfunction local static uvm_extract_phase m_inst; static function string type_name(); return "uvm_extract_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_extract_phase"; endfunction : get_type_name static function uvm_extract_phase get(); if(m_inst == null) m_inst = new(); return m_inst; endfunction protected function new(string name="extract"); super.new(name); endfunction endclass class uvm_check_phase extends uvm_bottomup_phase; virtual function void exec_func(uvm_component comp, uvm_phase phase); comp.check_phase(phase); endfunction local static uvm_check_phase m_inst; static function string type_name(); return "uvm_check_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_check_phase"; endfunction : get_type_name static function uvm_check_phase get(); if(m_inst == null) m_inst = new(); return m_inst; endfunction protected function new(string name="check"); super.new(name); endfunction endclass class uvm_report_phase extends uvm_bottomup_phase; virtual function void exec_func(uvm_component comp, uvm_phase phase); comp.report_phase(phase); endfunction local static uvm_report_phase m_inst; static function string type_name(); return "uvm_report_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_report_phase"; endfunction : get_type_name static function uvm_report_phase get(); if(m_inst == null) m_inst = new(); return m_inst; endfunction protected function new(string name="report"); super.new(name); endfunction endclass class uvm_final_phase extends uvm_topdown_phase; virtual function void exec_func(uvm_component comp, uvm_phase phase); comp.final_phase(phase); endfunction local static uvm_final_phase m_inst; static function string type_name(); return "uvm_final_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_final_phase"; endfunction : get_type_name static function uvm_final_phase get(); if(m_inst == null) m_inst = new(); return m_inst; endfunction protected function new(string name="final"); super.new(name); endfunction endclass class uvm_pre_reset_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.pre_reset_phase(phase); endtask local static uvm_pre_reset_phase m_inst; static function string type_name(); return "uvm_pre_reset_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_pre_reset_phase"; endfunction : get_type_name static function uvm_pre_reset_phase get(); if(m_inst == null) m_inst = new; return m_inst; endfunction protected function new(string name="pre_reset"); super.new(name); endfunction endclass class uvm_reset_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.reset_phase(phase); endtask local static uvm_reset_phase m_inst; static function string type_name(); return "uvm_reset_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_reset_phase"; endfunction : get_type_name static function uvm_reset_phase get(); if(m_inst == null) m_inst = new; return m_inst; endfunction protected function new(string name="reset"); super.new(name); endfunction endclass class uvm_post_reset_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.post_reset_phase(phase); endtask local static uvm_post_reset_phase m_inst; static function string type_name(); return "uvm_post_reset_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_post_reset_phase"; endfunction : get_type_name static function uvm_post_reset_phase get(); if(m_inst == null) m_inst = new; return m_inst; endfunction protected function new(string name="post_reset"); super.new(name); endfunction endclass class uvm_pre_configure_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.pre_configure_phase(phase); endtask local static uvm_pre_configure_phase m_inst; static function string type_name(); return "uvm_pre_configure_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_pre_configure_phase"; endfunction : get_type_name static function uvm_pre_configure_phase get(); if(m_inst == null) m_inst = new; return m_inst; endfunction protected function new(string name="pre_configure"); super.new(name); endfunction endclass class uvm_configure_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.configure_phase(phase); endtask local static uvm_configure_phase m_inst; static function string type_name(); return "uvm_configure_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_configure_phase"; endfunction : get_type_name static function uvm_configure_phase get(); if(m_inst == null) m_inst = new; return m_inst; endfunction protected function new(string name="configure"); super.new(name); endfunction endclass class uvm_post_configure_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.post_configure_phase(phase); endtask local static uvm_post_configure_phase m_inst; static function string type_name(); return "uvm_post_configure_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_post_configure_phase"; endfunction : get_type_name static function uvm_post_configure_phase get(); if(m_inst == null) m_inst = new; return m_inst; endfunction protected function new(string name="post_configure"); super.new(name); endfunction endclass class uvm_pre_main_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.pre_main_phase(phase); endtask local static uvm_pre_main_phase m_inst; static function string type_name(); return "uvm_pre_main_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_pre_main_phase"; endfunction : get_type_name static function uvm_pre_main_phase get(); if(m_inst == null) m_inst = new; return m_inst; endfunction protected function new(string name="pre_main"); super.new(name); endfunction endclass class uvm_main_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.main_phase(phase); endtask local static uvm_main_phase m_inst; static function string type_name(); return "uvm_main_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_main_phase"; endfunction : get_type_name static function uvm_main_phase get(); if(m_inst == null) m_inst = new; return m_inst; endfunction protected function new(string name="main"); super.new(name); endfunction endclass class uvm_post_main_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.post_main_phase(phase); endtask local static uvm_post_main_phase m_inst; static function string type_name(); return "uvm_post_main_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_post_main_phase"; endfunction : get_type_name static function uvm_post_main_phase get(); if(m_inst == null) m_inst = new; return m_inst; endfunction protected function new(string name="post_main"); super.new(name); endfunction endclass class uvm_pre_shutdown_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.pre_shutdown_phase(phase); endtask local static uvm_pre_shutdown_phase m_inst; static function string type_name(); return "uvm_pre_shutdown_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_pre_shutdown_phase"; endfunction : get_type_name static function uvm_pre_shutdown_phase get(); if(m_inst == null) m_inst = new; return m_inst; endfunction protected function new(string name="pre_shutdown"); super.new(name); endfunction endclass class uvm_shutdown_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.shutdown_phase(phase); endtask local static uvm_shutdown_phase m_inst; static function string type_name(); return "uvm_shutdown_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_shutdown_phase"; endfunction : get_type_name static function uvm_shutdown_phase get(); if(m_inst == null) m_inst = new; return m_inst; endfunction protected function new(string name="shutdown"); super.new(name); endfunction endclass class uvm_post_shutdown_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.post_shutdown_phase(phase); endtask local static uvm_post_shutdown_phase m_inst; static function string type_name(); return "uvm_post_shutdown_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_post_shutdown_phase"; endfunction : get_type_name static function uvm_post_shutdown_phase get(); if(m_inst == null) m_inst = new; return m_inst; endfunction protected function new(string name="post_shutdown"); super.new(name); endfunction endclass virtual class uvm_run_test_callback extends uvm_callback; extern function new( string name="uvm_run_test_callback"); virtual function void pre_run_test(); endfunction virtual function void post_run_test(); endfunction virtual function void pre_abort(); endfunction extern static function bit add( uvm_run_test_callback cb ); extern static function bit delete( uvm_run_test_callback cb ); extern static function void m_do_pre_run_test(); extern static function void m_do_post_run_test(); extern static function void m_do_pre_abort(); local static uvm_run_test_callback m_registered_cbs[$]; endclass : uvm_run_test_callback function uvm_run_test_callback::new( string name="uvm_run_test_callback"); super.new( name ); endfunction function bit uvm_run_test_callback::add( uvm_run_test_callback cb ); bit found; int unsigned i; if ( cb == null ) begin return 0; end found = 0; i = 0; while ( ! found && ( i < m_registered_cbs.size() ) ) begin if ( m_registered_cbs[ i ] == cb ) begin found = 1; end ++i; end if ( ! found ) begin m_registered_cbs.push_back( cb ); end return ! found; endfunction function bit uvm_run_test_callback::delete( uvm_run_test_callback cb ); int cb_idxs[$]; if ( cb == null ) begin return 0; end cb_idxs = m_registered_cbs.find_index( item ) with ( item == cb ); foreach ( cb_idxs[ i ] ) begin m_registered_cbs.delete( i ); end return ( cb_idxs.size() > 0 ); endfunction function void uvm_run_test_callback::m_do_pre_run_test(); foreach ( m_registered_cbs[ i ] ) begin m_registered_cbs[ i ].pre_run_test(); end endfunction function void uvm_run_test_callback::m_do_post_run_test(); foreach ( m_registered_cbs[ i ] ) begin m_registered_cbs[ i ].post_run_test(); end endfunction function void uvm_run_test_callback::m_do_pre_abort(); foreach ( m_registered_cbs[ i ] ) begin m_registered_cbs[ i ].pre_abort(); end endfunction typedef class uvm_objection; typedef class uvm_sequence_base; typedef class uvm_sequence_item; virtual class uvm_component extends uvm_report_object; extern function new (string name, uvm_component parent); extern virtual function uvm_component get_parent (); extern virtual function string get_full_name (); extern function void get_children(ref uvm_component children[$]); extern function uvm_component get_child (string name); extern function int get_next_child (ref string name); extern function int get_first_child (ref string name); extern function int get_num_children (); extern function int has_child (string name); extern virtual function void set_name (string name); extern function uvm_component lookup (string name); extern function int unsigned get_depth(); extern virtual function void build_phase(uvm_phase phase); extern virtual function void connect_phase(uvm_phase phase); extern virtual function void end_of_elaboration_phase(uvm_phase phase); extern virtual function void start_of_simulation_phase(uvm_phase phase); extern virtual task run_phase(uvm_phase phase); extern virtual task pre_reset_phase(uvm_phase phase); extern virtual task reset_phase(uvm_phase phase); extern virtual task post_reset_phase(uvm_phase phase); extern virtual task pre_configure_phase(uvm_phase phase); extern virtual task configure_phase(uvm_phase phase); extern virtual task post_configure_phase(uvm_phase phase); extern virtual task pre_main_phase(uvm_phase phase); extern virtual task main_phase(uvm_phase phase); extern virtual task post_main_phase(uvm_phase phase); extern virtual task pre_shutdown_phase(uvm_phase phase); extern virtual task shutdown_phase(uvm_phase phase); extern virtual task post_shutdown_phase(uvm_phase phase); extern virtual function void extract_phase(uvm_phase phase); extern virtual function void check_phase(uvm_phase phase); extern virtual function void report_phase(uvm_phase phase); extern virtual function void final_phase(uvm_phase phase); extern virtual function void phase_started (uvm_phase phase); extern virtual function void phase_ready_to_end (uvm_phase phase); extern virtual function void phase_ended (uvm_phase phase); extern function void set_domain(uvm_domain domain, int hier=1); extern function uvm_domain get_domain(); extern virtual protected function void define_domain(uvm_domain domain); extern virtual task suspend (); extern virtual task resume (); extern virtual function void resolve_bindings (); extern function string massage_scope(string scope); extern virtual function void apply_config_settings (bit verbose = 0); extern virtual function bit use_automatic_config(); extern function void print_config(bit recurse = 0, bit audit = 0); extern function void print_config_with_audit(bit recurse = 0); static bit print_config_matches; virtual function void raised (uvm_objection objection, uvm_object source_obj, string description, int count); endfunction virtual function void dropped (uvm_objection objection, uvm_object source_obj, string description, int count); endfunction virtual task all_dropped (uvm_objection objection, uvm_object source_obj, string description, int count); endtask extern function uvm_component create_component (string requested_type_name, string name); extern function uvm_object create_object (string requested_type_name, string name=""); extern static function void set_type_override_by_type (uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace=1); extern function void set_inst_override_by_type(string relative_inst_path, uvm_object_wrapper original_type, uvm_object_wrapper override_type); extern static function void set_type_override(string original_type_name, string override_type_name, bit replace=1); extern function void set_inst_override(string relative_inst_path, string original_type_name, string override_type_name); extern function void print_override_info(string requested_type_name, string name=""); extern function void set_report_id_verbosity_hier (string id, int verbosity); extern function void set_report_severity_id_verbosity_hier(uvm_severity severity, string id, int verbosity); extern function void set_report_severity_action_hier (uvm_severity severity, uvm_action action); extern function void set_report_id_action_hier (string id, uvm_action action); extern function void set_report_severity_id_action_hier(uvm_severity severity, string id, uvm_action action); extern function void set_report_default_file_hier (UVM_FILE file); extern function void set_report_severity_file_hier (uvm_severity severity, UVM_FILE file); extern function void set_report_id_file_hier (string id, UVM_FILE file); extern function void set_report_severity_id_file_hier(uvm_severity severity, string id, UVM_FILE file); extern function void set_report_verbosity_level_hier (int verbosity); virtual function void pre_abort; endfunction extern function void accept_tr (uvm_transaction tr, time accept_time = 0); extern virtual protected function void do_accept_tr (uvm_transaction tr); extern function int begin_tr (uvm_transaction tr, string stream_name="main", string label="", string desc="", time begin_time=0, int parent_handle=0); extern virtual protected function void do_begin_tr (uvm_transaction tr, string stream_name, int tr_handle); extern function void end_tr (uvm_transaction tr, time end_time=0, bit free_handle=1); extern virtual protected function void do_end_tr (uvm_transaction tr, int tr_handle); extern function int record_error_tr (string stream_name="main", uvm_object info=null, string label="error_tr", string desc="", time error_time=0, bit keep_active=0); extern function int record_event_tr (string stream_name="main", uvm_object info=null, string label="event_tr", string desc="", time event_time=0, bit keep_active=0); extern virtual function uvm_tr_stream get_tr_stream(string name, string stream_type_name=""); extern virtual function void free_tr_stream(uvm_tr_stream stream); bit print_enabled = 1; uvm_tr_database tr_database; extern virtual function uvm_tr_database get_tr_database(); extern virtual function void set_tr_database(uvm_tr_database db); protected uvm_domain m_domain; uvm_phase m_phase_imps[uvm_phase]; uvm_phase m_current_phase; protected process m_phase_process; bit m_build_done; int m_phasing_active; extern function void set_local(uvm_resource_base rsrc) ; uvm_component m_parent; protected uvm_component m_children[string]; protected uvm_component m_children_by_handle[uvm_component]; extern protected virtual function bit m_add_child(uvm_component child); extern local virtual function void m_set_full_name(); extern function void do_resolve_bindings(); extern function void do_flush(); extern virtual function void flush (); extern local function void m_extract_name(string name , output string leaf , output string remainder ); extern virtual function uvm_object create (string name=""); extern virtual function uvm_object clone (); local uvm_tr_stream m_streams[string][string]; local uvm_recorder m_tr_h[uvm_transaction]; extern protected function int m_begin_tr (uvm_transaction tr, int parent_handle=0, string stream_name="main", string label="", string desc="", time begin_time=0); string m_name; typedef uvm_abstract_component_registry#(uvm_component, "uvm_component") type_id; static function string type_name(); return "uvm_component"; endfunction : type_name virtual function string get_type_name(); return "uvm_component"; endfunction : get_type_name protected uvm_event_pool event_pool; int unsigned recording_detail = UVM_NONE; extern function void do_print(uvm_printer printer); extern function void m_set_cl_msg_args; extern function void m_set_cl_verb; extern function void m_set_cl_action; extern function void m_set_cl_sev; extern function void m_apply_verbosity_settings(uvm_phase phase); typedef struct { string comp; string phase; time offset; uvm_verbosity verbosity; string id; } m_verbosity_setting; m_verbosity_setting m_verbosity_settings[$]; static m_verbosity_setting m_time_settings[$]; extern function void m_do_pre_abort; uvm_resource_base m_unsupported_resource_base = null; extern function void m_unsupported_set_local(uvm_resource_base rsrc); typedef struct { string arg; string args[$]; int unsigned used; } uvm_cmdline_parsed_arg_t; static uvm_cmdline_parsed_arg_t m_uvm_applied_cl_action[$]; static uvm_cmdline_parsed_arg_t m_uvm_applied_cl_sev[$]; endclass : uvm_component typedef class uvm_cmdline_processor; typedef class uvm_component_proxy; typedef class uvm_top_down_visitor_adapter; typedef class uvm_report_message; typedef class uvm_report_object; typedef class uvm_report_handler; typedef class uvm_default_report_server; class uvm_root extends uvm_component; extern static function uvm_root get(); uvm_cmdline_processor clp; virtual function string get_type_name(); return "uvm_root"; endfunction extern virtual task run_test (string test_name=""); virtual function void die(); uvm_report_server l_rs = uvm_report_server::get_server(); m_uvm_core_state=UVM_CORE_PRE_ABORT; m_do_pre_abort(); uvm_run_test_callback::m_do_pre_abort(); l_rs.report_summarize(); m_uvm_core_state=UVM_CORE_ABORTED; $finish; endfunction extern function void set_timeout(time timeout, bit overridable=1); local bit finish_on_completion = 1; virtual function bit get_finish_on_completion(); return finish_on_completion; endfunction : get_finish_on_completion virtual function void set_finish_on_completion(bit f); finish_on_completion = f; endfunction : set_finish_on_completion extern function uvm_component find (string comp_match); extern function void find_all (string comp_match, ref uvm_component comps[$], input uvm_component comp=null); extern function void print_topology (uvm_printer printer=null); bit enable_print_topology = 0; extern function void set_enable_print_topology (bit enable); extern function bit get_enable_print_topology (); time phase_timeout = 9200s; extern function void m_find_all_recurse(string comp_match, ref uvm_component comps[$], input uvm_component comp=null); extern protected function new (); extern protected virtual function bit m_add_child (uvm_component child); extern function void build_phase(uvm_phase phase); extern local function void m_do_verbosity_settings(); extern local function void m_do_timeout_settings(); extern local function void m_do_factory_settings(); extern local function void m_process_inst_override(string ovr); extern local function void m_process_type_override(string ovr); extern local function void m_do_config_settings(); extern local function void m_do_max_quit_settings(); extern local function void m_do_dump_args(); extern local function void m_process_config(string cfg, bit is_int); extern local function void m_process_default_sequence(string cfg); extern function void m_check_verbosity(); extern function void m_check_uvm_field_flag_size(); extern virtual function void report_header(UVM_FILE file = 0); static local uvm_root m_inst; extern virtual task run_phase (uvm_phase phase); function void phase_started(uvm_phase phase); if (phase == end_of_elaboration_ph) begin do_resolve_bindings(); if (enable_print_topology) print_topology(); begin uvm_report_server srvr; srvr = uvm_report_server::get_server(); if(srvr.get_severity_count(UVM_ERROR) > 0) begin uvm_report_fatal("BUILDERR", "stopping due to build errors", UVM_NONE); end end end endfunction bit m_phase_all_done; extern static function uvm_root m_uvm_get_root(); static local bit m_relnotes_done=0; function void end_of_elaboration_phase(uvm_phase phase); uvm_component_proxy p = new("proxy"); uvm_top_down_visitor_adapter#(uvm_component) adapter = new("adapter"); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_visitor#(uvm_component) v = cs.get_component_visitor(); adapter.accept(this, v, p); endfunction endclass function uvm_root uvm_root::get(); uvm_coreservice_t cs = uvm_coreservice_t::get(); return cs.get_root(); endfunction function uvm_root::new(); uvm_report_handler rh; super.new("__top__", null); rh = new("reporter"); set_report_handler(rh); if (m_inst != null) begin begin if (m_inst.uvm_report_enabled(UVM_NONE,UVM_FATAL,"UVM/ROOT/MULTI")) m_inst.uvm_report_fatal ("UVM/ROOT/MULTI", "Attempting to construct multiple roots", UVM_NONE, "t/uvm/src/base/uvm_root.svh", 378, "", 1); end return; end m_inst = this; clp = uvm_cmdline_processor::get_inst(); endfunction function uvm_root uvm_root::m_uvm_get_root(); if (m_inst == null) begin uvm_root top; top = new(); if (top != m_inst) return null; top.m_domain = uvm_domain::get_uvm_domain(); end return m_inst; endfunction function void uvm_root::report_header(UVM_FILE file = 0); string q[$]; uvm_report_server srvr; uvm_cmdline_processor clp; string args[$]; srvr = uvm_report_server::get_server(); clp = uvm_cmdline_processor::get_inst(); if (clp.get_arg_matches("+UVM_NO_RELNOTES", args)) return; if (!m_relnotes_done) begin q.push_back("\n *********** IMPORTANT RELEASE NOTES ************\n"); m_relnotes_done = 1; q.push_back("\n This implementation of the UVM Library deviates from the 1800.2-2017\n"); q.push_back(" standard. See the DEVIATIONS.md file contained in the release\n"); q.push_back(" for more details.\n"); end q.push_back("\n----------------------------------------------------------------\n"); q.push_back({uvm_revision_string(),"\n"}); q.push_back("\n"); q.push_back("All copyright owners for this kit are listed in NOTICE.txt\n"); q.push_back("All Rights Reserved Worldwide\n"); q.push_back("----------------------------------------------------------------\n"); if(m_relnotes_done) q.push_back("\n (Specify +UVM_NO_RELNOTES to turn off this notice)\n"); begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,"UVM/RELNOTES")) uvm_report_info ("UVM/RELNOTES", uvm_pkg::m_uvm_string_queue_join(q), UVM_LOW, "t/uvm/src/base/uvm_root.svh", 449, "", 1); end endfunction task uvm_root::run_test(string test_name=""); uvm_report_server l_rs; uvm_factory factory; bit testname_plusarg; int test_name_count; string test_names[$]; string msg; uvm_component uvm_test_top; process phase_runner_proc; uvm_run_test_callback::m_do_pre_run_test(); factory=uvm_factory::get(); m_uvm_core_state=UVM_CORE_PRE_RUN; testname_plusarg = 0; uvm_objection::m_init_objections(); m_do_dump_args(); if ($value$plusargs("UVM_TESTNAME=%s", test_name)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"NO_DPI_TSTNAME")) uvm_report_info ("NO_DPI_TSTNAME", "UVM_NO_DPI defined--getting UVM_TESTNAME directly, without DPI", UVM_NONE, "t/uvm/src/base/uvm_root.svh", 517, "", 1); end testname_plusarg = 1; end if (test_name != "") begin if(m_children.exists("uvm_test_top")) begin uvm_report_fatal("TTINST", "An uvm_test_top already exists via a previous call to run_test", UVM_NONE); #0; end $cast(uvm_test_top, factory.create_component_by_name(test_name, "", "uvm_test_top", null)); if (uvm_test_top == null) begin msg = testname_plusarg ? {"command line +UVM_TESTNAME=",test_name} : {"call to run_test(",test_name,")"}; uvm_report_fatal("INVTST", {"Requested test from ",msg, " not found." }, UVM_NONE); end end if (m_children.num() == 0) begin uvm_report_fatal("NOCOMP", {"No components instantiated. You must either instantiate", " at least one component before calling run_test or use", " run_test to do so. To run a test using run_test,", " use +UVM_TESTNAME or supply the test name in", " the argument to run_test(). Exiting simulation."}, UVM_NONE); return; end begin if(test_name=="") uvm_report_info("RNTST", "Running test ...", UVM_LOW); else if (test_name == uvm_test_top.get_type_name()) uvm_report_info("RNTST", {"Running test ",test_name,"..."}, UVM_LOW); else uvm_report_info("RNTST", {"Running test ",uvm_test_top.get_type_name()," (via factory override for test \"",test_name,"\")..."}, UVM_LOW); end fork begin phase_runner_proc = process::self(); uvm_phase::m_run_phases(); end join_none #0; wait (m_phase_all_done == 1); m_uvm_core_state=UVM_CORE_POST_RUN; phase_runner_proc.kill(); l_rs = uvm_report_server::get_server(); uvm_run_test_callback::m_do_post_run_test(); l_rs.report_summarize(); m_uvm_core_state=UVM_CORE_FINISHED; if (get_finish_on_completion()) $finish; endtask function void uvm_root::find_all(string comp_match, ref uvm_component comps[$], input uvm_component comp=null); if (comp==null) comp = this; m_find_all_recurse(comp_match, comps, comp); endfunction function uvm_component uvm_root::find (string comp_match); uvm_component comp_list[$]; find_all(comp_match,comp_list); if (comp_list.size() > 1) uvm_report_warning("MMATCH", $sformatf("Found %0d components matching '%s'. Returning first match, %0s.", comp_list.size(),comp_match,comp_list[0].get_full_name()), UVM_NONE); if (comp_list.size() == 0) begin uvm_report_warning("CMPNFD", {"Component matching '",comp_match, "' was not found in the list of uvm_components"}, UVM_NONE); return null; end return comp_list[0]; endfunction function void uvm_root::print_topology(uvm_printer printer=null); if (m_children.num()==0) begin uvm_report_warning("EMTCOMP", "print_topology - No UVM components to print.", UVM_NONE); return; end if (printer==null) printer = uvm_printer::get_default(); begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"UVMTOP")) uvm_report_info ("UVMTOP", "UVM testbench topology:", UVM_NONE, "t/uvm/src/base/uvm_root.svh", 640, "", 1); end print(printer) ; endfunction function void uvm_root::set_timeout(time timeout, bit overridable=1); static bit m_uvm_timeout_overridable = 1; if (m_uvm_timeout_overridable == 0) begin uvm_report_info("NOTIMOUTOVR", $sformatf("The global timeout setting of %0d is not overridable to %0d due to a previous setting.", phase_timeout, timeout), UVM_NONE); return; end m_uvm_timeout_overridable = overridable; phase_timeout = timeout; endfunction function void uvm_root::m_find_all_recurse(string comp_match, ref uvm_component comps[$], input uvm_component comp=null); string name; if (comp.get_first_child(name)) do begin this.m_find_all_recurse(comp_match, comps, comp.get_child(name)); end while (comp.get_next_child(name)); if (uvm_is_match(comp_match, comp.get_full_name()) && comp.get_name() != "") comps.push_back(comp); endfunction function bit uvm_root::m_add_child (uvm_component child); if(super.m_add_child(child)) begin return 1; end else return 0; endfunction function void uvm_root::build_phase(uvm_phase phase); super.build_phase(phase); m_set_cl_msg_args(); m_do_verbosity_settings(); m_do_timeout_settings(); m_do_factory_settings(); m_do_config_settings(); m_do_max_quit_settings(); endfunction function void uvm_root::m_do_verbosity_settings(); string set_verbosity_settings[$]; string split_vals[$]; uvm_verbosity tmp_verb; void'(clp.get_arg_values("+uvm_set_verbosity=", set_verbosity_settings)); for(int i = 0; i < set_verbosity_settings.size(); i++) begin uvm_split_string(set_verbosity_settings[i], ",", split_vals); if(split_vals.size() < 4 || split_vals.size() > 5) begin uvm_report_warning("INVLCMDARGS", $sformatf("Invalid number of arguments found on the command line for setting '+uvm_set_verbosity=%s'. Setting ignored.", set_verbosity_settings[i]), UVM_NONE, "", ""); end if(!clp.m_convert_verb(split_vals[2], tmp_verb)) begin uvm_report_warning("INVLCMDVERB", $sformatf("Invalid verbosity found on the command line for setting '%s'.", set_verbosity_settings[i]), UVM_NONE, "", ""); end end endfunction function void uvm_root::m_do_timeout_settings(); string timeout_settings[$]; string timeout; string split_timeout[$]; int timeout_count; time timeout_int; string override_spec; timeout_count = clp.get_arg_values("+UVM_TIMEOUT=", timeout_settings); if (timeout_count == 0) return; else begin timeout = timeout_settings[0]; if (timeout_count > 1) begin string timeout_list; string sep; for (int i = 0; i < timeout_settings.size(); i++) begin if (i != 0) sep = "; "; timeout_list = {timeout_list, sep, timeout_settings[i]}; end uvm_report_warning("MULTTIMOUT", $sformatf("Multiple (%0d) +UVM_TIMEOUT arguments provided on the command line. '%s' will be used. Provided list: %s.", timeout_count, timeout, timeout_list), UVM_NONE); end uvm_report_info("TIMOUTSET", $sformatf("'+UVM_TIMEOUT=%s' provided on the command line is being applied.", timeout), UVM_NONE); void'($sscanf(timeout,"%d,%s",timeout_int,override_spec)); case(override_spec) "YES" : set_timeout(timeout_int, 1); "NO" : set_timeout(timeout_int, 0); default : set_timeout(timeout_int, 1); endcase end endfunction function void uvm_root::m_do_factory_settings(); string args[$]; void'(clp.get_arg_matches("/^\\+(UVM_SET_INST_OVERRIDE|uvm_set_inst_override)=/",args)); foreach(args[i]) begin m_process_inst_override(args[i].substr(23, args[i].len()-1)); end void'(clp.get_arg_matches("/^\\+(UVM_SET_TYPE_OVERRIDE|uvm_set_type_override)=/",args)); foreach(args[i]) begin m_process_type_override(args[i].substr(23, args[i].len()-1)); end endfunction function void uvm_root::m_process_inst_override(string ovr); string split_val[$]; uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); uvm_split_string(ovr, ",", split_val); if(split_val.size() != 3 ) begin uvm_report_error("UVM_CMDLINE_PROC", {"Invalid setting for +uvm_set_inst_override=", ovr, ", setting must specify ,,"}, UVM_NONE); return; end uvm_report_info("INSTOVR", {"Applying instance override from the command line: +uvm_set_inst_override=", ovr}, UVM_NONE); factory.set_inst_override_by_name(split_val[0], split_val[1], split_val[2]); endfunction function void uvm_root::m_process_type_override(string ovr); string split_val[$]; int replace=1; uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); uvm_split_string(ovr, ",", split_val); if(split_val.size() > 3 || split_val.size() < 2) begin uvm_report_error("UVM_CMDLINE_PROC", {"Invalid setting for +uvm_set_type_override=", ovr, ", setting must specify ,[,]"}, UVM_NONE); return; end if(split_val.size() == 3) begin if(split_val[2]=="0") replace = 0; else if (split_val[2] == "1") replace = 1; else begin uvm_report_error("UVM_CMDLINE_PROC", {"Invalid replace arg for +uvm_set_type_override=", ovr ," value must be 0 or 1"}, UVM_NONE); return; end end uvm_report_info("UVM_CMDLINE_PROC", {"Applying type override from the command line: +uvm_set_type_override=", ovr}, UVM_NONE); factory.set_type_override_by_name(split_val[0], split_val[1], replace); endfunction function void uvm_root::m_process_config(string cfg, bit is_int); uvm_bitstream_t v; string split_val[$]; uvm_root m_uvm_top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); m_uvm_top = cs.get_root(); uvm_split_string(cfg, ",", split_val); if(split_val.size() == 1) begin uvm_report_error("UVM_CMDLINE_PROC", {"Invalid +uvm_set_config command\"", cfg, "\" missing field and value: component is \"", split_val[0], "\""}, UVM_NONE); return; end if(split_val.size() == 2) begin uvm_report_error("UVM_CMDLINE_PROC", {"Invalid +uvm_set_config command\"", cfg, "\" missing value: component is \"", split_val[0], "\" field is \"", split_val[1], "\""}, UVM_NONE); return; end if(split_val.size() > 3) begin uvm_report_error("UVM_CMDLINE_PROC", $sformatf("Invalid +uvm_set_config command\"%s\" : expected only 3 fields (component, field and value).", cfg), UVM_NONE); return; end if(is_int) begin if(split_val[2].len() > 2) begin string base, extval; base = split_val[2].substr(0,1); extval = split_val[2].substr(2,split_val[2].len()-1); case(base) "'b" : v = extval.atobin(); "0b" : v = extval.atobin(); "'o" : v = extval.atooct(); "'d" : v = extval.atoi(); "'h" : v = extval.atohex(); "'x" : v = extval.atohex(); "0x" : v = extval.atohex(); default : v = split_val[2].atoi(); endcase end else begin v = split_val[2].atoi(); end uvm_report_info("UVM_CMDLINE_PROC", {"Applying config setting from the command line: +uvm_set_config_int=", cfg}, UVM_NONE); uvm_config_int::set(m_uvm_top, split_val[0], split_val[1], v); end else begin uvm_report_info("UVM_CMDLINE_PROC", {"Applying config setting from the command line: +uvm_set_config_string=", cfg}, UVM_NONE); uvm_config_string::set(m_uvm_top, split_val[0], split_val[1], split_val[2]); end endfunction function void uvm_root::m_process_default_sequence(string cfg); string split_val[$]; uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_root m_uvm_top = cs.get_root(); uvm_factory f = cs.get_factory(); uvm_object_wrapper w; uvm_split_string(cfg, ",", split_val); if(split_val.size() == 1) begin uvm_report_error("UVM_CMDLINE_PROC", {"Invalid +uvm_set_default_sequence command\"", cfg, "\" missing phase and type: sequencer is \"", split_val[0], "\""}, UVM_NONE); return; end if(split_val.size() == 2) begin uvm_report_error("UVM_CMDLINE_PROC", {"Invalid +uvm_set_default_sequence command\"", cfg, "\" missing type: sequencer is \"", split_val[0], "\" phase is \"", split_val[1], "\""}, UVM_NONE); return; end if(split_val.size() > 3) begin uvm_report_error("UVM_CMDLINE_PROC", $sformatf("Invalid +uvm_set_default_sequence command\"%s\" : expected only 3 fields (sequencer, phase and type).", cfg), UVM_NONE); return; end w = f.find_wrapper_by_name(split_val[2]); if (w == null) begin uvm_report_error("UVM_CMDLINE_PROC", $sformatf("Invalid type '%s' provided to +uvm_set_default_sequence", split_val[2]), UVM_NONE); return; end else begin uvm_report_info("UVM_CMDLINE_PROC", {"Setting default sequence from the command line: +uvm_set_default_sequence=", cfg}, UVM_NONE); uvm_config_db#(uvm_object_wrapper)::set(this, {split_val[0], ".", split_val[1]}, "default_sequence", w); end endfunction : m_process_default_sequence function void uvm_root::m_do_config_settings(); string args[$]; void'(clp.get_arg_matches("/^\\+(UVM_SET_CONFIG_INT|uvm_set_config_int)=/",args)); foreach(args[i]) begin m_process_config(args[i].substr(20, args[i].len()-1), 1); end void'(clp.get_arg_matches("/^\\+(UVM_SET_CONFIG_STRING|uvm_set_config_string)=/",args)); foreach(args[i]) begin m_process_config(args[i].substr(23, args[i].len()-1), 0); end void'(clp.get_arg_matches("/^\\+(UVM_SET_DEFAULT_SEQUENCE|uvm_set_default_sequence)=/", args)); foreach(args[i]) begin m_process_default_sequence(args[i].substr(26, args[i].len()-1)); end endfunction function void uvm_root::m_do_max_quit_settings(); uvm_report_server srvr; string max_quit_settings[$]; int max_quit_count; string max_quit; string split_max_quit[$]; int max_quit_int; srvr = uvm_report_server::get_server(); max_quit_count = clp.get_arg_values("+UVM_MAX_QUIT_COUNT=", max_quit_settings); if (max_quit_count == 0) return; else begin max_quit = max_quit_settings[0]; if (max_quit_count > 1) begin string max_quit_list; string sep; for (int i = 0; i < max_quit_settings.size(); i++) begin if (i != 0) sep = "; "; max_quit_list = {max_quit_list, sep, max_quit_settings[i]}; end uvm_report_warning("MULTMAXQUIT", $sformatf("Multiple (%0d) +UVM_MAX_QUIT_COUNT arguments provided on the command line. '%s' will be used. Provided list: %s.", max_quit_count, max_quit, max_quit_list), UVM_NONE); end uvm_report_info("MAXQUITSET", $sformatf("'+UVM_MAX_QUIT_COUNT=%s' provided on the command line is being applied.", max_quit), UVM_NONE); uvm_split_string(max_quit, ",", split_max_quit); max_quit_int = split_max_quit[0].atoi(); case(split_max_quit[1]) "YES" : srvr.set_max_quit_count(max_quit_int, 1); "NO" : srvr.set_max_quit_count(max_quit_int, 0); default : srvr.set_max_quit_count(max_quit_int, 1); endcase end endfunction function void uvm_root::m_do_dump_args(); string dump_args[$]; string all_args[$]; string out_string; if(clp.get_arg_matches("+UVM_DUMP_CMDLINE_ARGS", dump_args)) begin clp.get_args(all_args); foreach (all_args[idx]) begin uvm_report_info("DUMPARGS", $sformatf("idx=%0d arg=[%s]",idx,all_args[idx]), UVM_NONE); end end endfunction function void uvm_root::m_check_verbosity(); string verb_string; string verb_settings[$]; int verb_count; int plusarg; int verbosity = UVM_MEDIUM; verb_count = $value$plusargs("UVM_VERBOSITY=%s",verb_string); if (verb_count) verb_settings.push_back(verb_string); if (verb_count > 0) begin verb_string = verb_settings[0]; plusarg = 1; end if (verb_count > 1) begin string verb_list; string sep; for (int i = 0; i < verb_settings.size(); i++) begin if (i != 0) sep = ", "; verb_list = {verb_list, sep, verb_settings[i]}; end uvm_report_warning("MULTVERB", $sformatf("Multiple (%0d) +UVM_VERBOSITY arguments provided on the command line. '%s' will be used. Provided list: %s.", verb_count, verb_string, verb_list), UVM_NONE); end if(plusarg == 1) begin case(verb_string) "UVM_NONE" : verbosity = UVM_NONE; "NONE" : verbosity = UVM_NONE; "UVM_LOW" : verbosity = UVM_LOW; "LOW" : verbosity = UVM_LOW; "UVM_MEDIUM" : verbosity = UVM_MEDIUM; "MEDIUM" : verbosity = UVM_MEDIUM; "UVM_HIGH" : verbosity = UVM_HIGH; "HIGH" : verbosity = UVM_HIGH; "UVM_FULL" : verbosity = UVM_FULL; "FULL" : verbosity = UVM_FULL; "UVM_DEBUG" : verbosity = UVM_DEBUG; "DEBUG" : verbosity = UVM_DEBUG; default : begin verbosity = verb_string.atoi(); if(verbosity > 0) uvm_report_info("NSTVERB", $sformatf("Non-standard verbosity value, using provided '%0d'.", verbosity), UVM_NONE); if(verbosity == 0) begin verbosity = UVM_MEDIUM; uvm_report_warning("ILLVERB", "Illegal verbosity value, using default of UVM_MEDIUM.", UVM_NONE); end end endcase end set_report_verbosity_level_hier(verbosity); endfunction function void uvm_root::m_check_uvm_field_flag_size(); if ( (UVM_FIELD_FLAG_RESERVED_BITS) < UVM_FIELD_FLAG_RESERVED_BITS ) begin uvm_report_fatal( "BAD_FIELD_FLAG_SZ", $sformatf( "Macro UVM_FIELD_FLAG_SIZE is set to %0d which is less than the required minimum of UVM_FIELD_FLAG_RESERVED_BITS (%0d).", UVM_FIELD_FLAG_RESERVED_BITS, UVM_FIELD_FLAG_RESERVED_BITS ) ); end endfunction task uvm_root::run_phase (uvm_phase phase); foreach(m_uvm_applied_cl_action[idx]) if(m_uvm_applied_cl_action[idx].used==0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"INVLCMDARGS")) uvm_report_warning ("INVLCMDARGS", $sformatf("\"+uvm_set_action=%s\" never took effect due to a mismatching component pattern",m_uvm_applied_cl_action[idx].arg), UVM_NONE, "t/uvm/src/base/uvm_root.svh", 1130, "", 1); end end foreach(m_uvm_applied_cl_sev[idx]) if(m_uvm_applied_cl_sev[idx].used==0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"INVLCMDARGS")) uvm_report_warning ("INVLCMDARGS", $sformatf("\"+uvm_set_severity=%s\" never took effect due to a mismatching component pattern",m_uvm_applied_cl_sev[idx].arg), UVM_NONE, "t/uvm/src/base/uvm_root.svh", 1134, "", 1); end end if($time > 0) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"RUNPHSTIME")) uvm_report_fatal ("RUNPHSTIME", {"The run phase must start at time 0, current time is ", $sformatf("%0t", $realtime), ". No non-zero delays are allowed before ", "run_test(), and pre-run user defined phases may not consume ", "simulation time before the start of the run phase."}, UVM_NONE, "t/uvm/src/base/uvm_root.svh", 1141, "", 1); end endtask function void uvm_root::set_enable_print_topology (bit enable); enable_print_topology = enable; endfunction function bit uvm_root::get_enable_print_topology(); return enable_print_topology; endfunction function uvm_component::new (string name, uvm_component parent); string error_str; uvm_root top; uvm_coreservice_t cs; super.new(name); if (parent==null && name == "__top__") begin set_name(""); return; end cs = uvm_coreservice_t::get(); top = cs.get_root(); begin uvm_phase bld; uvm_domain common; common = uvm_domain::get_common_domain(); bld = common.find(uvm_build_phase::get()); if (bld == null) uvm_report_fatal("COMP/INTERNAL", "attempt to find build phase object failed",UVM_NONE); if (bld.get_state() == UVM_PHASE_DONE) begin uvm_report_fatal("ILLCRT", {"It is illegal to create a component ('", name,"' under '", (parent == null ? top.get_full_name() : parent.get_full_name()), "') after the build phase has ended."}, UVM_NONE); end end if (name == "") begin name.itoa(m_inst_count); name = {"COMP_", name}; end if(parent == this) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"THISPARENT")) uvm_report_fatal ("THISPARENT", "cannot set the parent of a component to itself", UVM_NONE, "t/uvm/src/base/uvm_component.svh", 1635, "", 1); end end if (parent == null) parent = top; if(uvm_report_enabled(UVM_MEDIUM+1, UVM_INFO, "NEWCOMP")) begin if (uvm_report_enabled(UVM_MEDIUM+1,UVM_INFO,"NEWCOMP")) uvm_report_info ("NEWCOMP", {"Creating ", (parent==top?"uvm_top":parent.get_full_name()),".",name}, UVM_MEDIUM+1, "t/uvm/src/base/uvm_component.svh", 1643, "", 1); end if (parent.has_child(name) && this != parent.get_child(name)) begin if (parent == top) begin error_str = {"Name '",name,"' is not unique to other top-level ", "instances. If parent is a module, build a unique name by combining the ", "the module name and component name: $sformatf(\"\%m.\%s\",\"",name,"\")."}; begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"CLDEXT")) uvm_report_fatal ("CLDEXT", error_str, UVM_NONE, "t/uvm/src/base/uvm_component.svh", 1650, "", 1); end end else begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"CLDEXT")) uvm_report_fatal ("CLDEXT", $sformatf("Cannot set '%s' as a child of '%s', %s", name, parent.get_full_name(), "which already has a child by that name."), UVM_NONE, "t/uvm/src/base/uvm_component.svh", 1656, "", 1); end return; end m_parent = parent; set_name(name); if (!m_parent.m_add_child(this)) m_parent = null; event_pool = new("event_pool"); m_domain = parent.m_domain; reseed(); if (!uvm_config_db #(uvm_bitstream_t)::get(this, "", "recording_detail", recording_detail)) void'(uvm_config_db #(int)::get(this, "", "recording_detail", recording_detail)); m_rh.set_name(get_full_name()); set_report_verbosity_level(parent.get_report_verbosity_level()); m_set_cl_msg_args(); endfunction function bit uvm_component::m_add_child(uvm_component child); if (m_children.exists(child.get_name()) && m_children[child.get_name()] != child) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"BDCLD")) uvm_report_warning ("BDCLD", $sformatf("A child with the name '%0s' (type=%0s) already exists.", child.get_name(), m_children[child.get_name()].get_type_name()), UVM_NONE, "t/uvm/src/base/uvm_component.svh", 1695, "", 1); end return 0; end if (m_children_by_handle.exists(child)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"BDCHLD")) uvm_report_warning ("BDCHLD", $sformatf("A child with the name '%0s' %0s %0s'", child.get_name(), "already exists in parent under name '", m_children_by_handle[child].get_name()), UVM_NONE, "t/uvm/src/base/uvm_component.svh", 1704, "", 1); end return 0; end m_children[child.get_name()] = child; m_children_by_handle[child] = child; return 1; endfunction function void uvm_component::get_children(ref uvm_component children[$]); foreach(m_children[i]) children.push_back(m_children[i]); endfunction function int uvm_component::get_first_child(ref string name); return m_children.first(name); endfunction function int uvm_component::get_next_child(ref string name); return m_children.next(name); endfunction function uvm_component uvm_component::get_child(string name); if (m_children.exists(name)) return m_children[name]; begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"NOCHILD")) uvm_report_warning ("NOCHILD", {"Component with name '",name, "' is not a child of component '",get_full_name(),"'"}, UVM_NONE, "t/uvm/src/base/uvm_component.svh", 1754, "", 1); end return null; endfunction function int uvm_component::has_child(string name); return m_children.exists(name); endfunction function int uvm_component::get_num_children(); return m_children.num(); endfunction function string uvm_component::get_full_name (); if(m_name == "") return get_name(); else return m_name; endfunction function uvm_component uvm_component::get_parent (); return m_parent; endfunction function void uvm_component::set_name (string name); if(m_name != "") begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"INVSTNM")) uvm_report_error ("INVSTNM", $sformatf("It is illegal to change the name of a component. The component name will not be changed to \"%s\"", name), UVM_NONE, "t/uvm/src/base/uvm_component.svh", 1801, "", 1); end return; end super.set_name(name); m_set_full_name(); endfunction function void uvm_component::m_set_full_name(); uvm_root top; if ($cast(top, m_parent) || m_parent==null) m_name = get_name(); else m_name = {m_parent.get_full_name(), ".", get_name()}; foreach (m_children[c]) begin uvm_component tmp; tmp = m_children[c]; tmp.m_set_full_name(); end endfunction function uvm_component uvm_component::lookup( string name ); string leaf , remainder; uvm_component comp; uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); comp = this; m_extract_name(name, leaf, remainder); if (leaf == "") begin comp = top; m_extract_name(remainder, leaf, remainder); end if (!comp.has_child(leaf)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"Lookup Error")) uvm_report_warning ("Lookup Error", $sformatf("Cannot find child %0s",leaf), UVM_NONE, "t/uvm/src/base/uvm_component.svh", 1852, "", 1); end return null; end if( remainder != "" ) return comp.m_children[leaf].lookup(remainder); return comp.m_children[leaf]; endfunction function int unsigned uvm_component::get_depth(); if(m_name == "") return 0; get_depth = 1; foreach(m_name[i]) if(m_name[i] == ".") ++get_depth; endfunction function void uvm_component::m_extract_name(input string name , output string leaf , output string remainder ); int i , len; len = name.len(); for( i = 0; i < name.len(); i++ ) begin if( name[i] == "." ) begin break; end end if( i == len ) begin leaf = name; remainder = ""; return; end leaf = name.substr( 0 , i - 1 ); remainder = name.substr( i + 1 , len - 1 ); return; endfunction function void uvm_component::flush(); return; endfunction function void uvm_component::do_flush(); foreach( m_children[s] ) m_children[s].do_flush(); flush(); endfunction function uvm_object uvm_component::create (string name =""); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"ILLCRT")) uvm_report_error ("ILLCRT", "create cannot be called on a uvm_component. Use create_component instead.", UVM_NONE, "t/uvm/src/base/uvm_component.svh", 1934, "", 1); end return null; endfunction function uvm_object uvm_component::clone (); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"ILLCLN")) uvm_report_error ("ILLCLN", $sformatf("Attempting to clone '%s'. Clone cannot be called on a uvm_component. The clone target variable will be set to null.", get_full_name()), UVM_NONE, "t/uvm/src/base/uvm_component.svh", 1943, "", 1); end return null; endfunction function void uvm_component::print_override_info (string requested_type_name, string name=""); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); factory.debug_create_by_name(requested_type_name, get_full_name(), name); endfunction function uvm_component uvm_component::create_component (string requested_type_name, string name); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); return factory.create_component_by_name(requested_type_name, get_full_name(), name, this); endfunction function uvm_object uvm_component::create_object (string requested_type_name, string name=""); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); return factory.create_object_by_name(requested_type_name, get_full_name(), name); endfunction function void uvm_component::set_type_override (string original_type_name, string override_type_name, bit replace=1); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); factory.set_type_override_by_name(original_type_name,override_type_name, replace); endfunction function void uvm_component::set_type_override_by_type (uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace=1); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); factory.set_type_override_by_type(original_type, override_type, replace); endfunction function void uvm_component::set_inst_override (string relative_inst_path, string original_type_name, string override_type_name); string full_inst_path; uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); if (relative_inst_path == "") full_inst_path = get_full_name(); else full_inst_path = {get_full_name(), ".", relative_inst_path}; factory.set_inst_override_by_name( original_type_name, override_type_name, full_inst_path); endfunction function void uvm_component::set_inst_override_by_type (string relative_inst_path, uvm_object_wrapper original_type, uvm_object_wrapper override_type); string full_inst_path; uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); if (relative_inst_path == "") full_inst_path = get_full_name(); else full_inst_path = {get_full_name(), ".", relative_inst_path}; factory.set_inst_override_by_type(original_type, override_type, full_inst_path); endfunction function void uvm_component::set_report_id_verbosity_hier( string id, int verbosity); set_report_id_verbosity(id, verbosity); foreach( m_children[c] ) m_children[c].set_report_id_verbosity_hier(id, verbosity); endfunction function void uvm_component::set_report_severity_id_verbosity_hier( uvm_severity severity, string id, int verbosity); set_report_severity_id_verbosity(severity, id, verbosity); foreach( m_children[c] ) m_children[c].set_report_severity_id_verbosity_hier(severity, id, verbosity); endfunction function void uvm_component::set_report_severity_action_hier( uvm_severity severity, uvm_action action); set_report_severity_action(severity, action); foreach( m_children[c] ) m_children[c].set_report_severity_action_hier(severity, action); endfunction function void uvm_component::set_report_id_action_hier( string id, uvm_action action); set_report_id_action(id, action); foreach( m_children[c] ) m_children[c].set_report_id_action_hier(id, action); endfunction function void uvm_component::set_report_severity_id_action_hier( uvm_severity severity, string id, uvm_action action); set_report_severity_id_action(severity, id, action); foreach( m_children[c] ) m_children[c].set_report_severity_id_action_hier(severity, id, action); endfunction function void uvm_component::set_report_severity_file_hier( uvm_severity severity, UVM_FILE file); set_report_severity_file(severity, file); foreach( m_children[c] ) m_children[c].set_report_severity_file_hier(severity, file); endfunction function void uvm_component::set_report_default_file_hier( UVM_FILE file); set_report_default_file(file); foreach( m_children[c] ) m_children[c].set_report_default_file_hier(file); endfunction function void uvm_component::set_report_id_file_hier( string id, UVM_FILE file); set_report_id_file(id, file); foreach( m_children[c] ) m_children[c].set_report_id_file_hier(id, file); endfunction function void uvm_component::set_report_severity_id_file_hier ( uvm_severity severity, string id, UVM_FILE file); set_report_severity_id_file(severity, id, file); foreach( m_children[c] ) m_children[c].set_report_severity_id_file_hier(severity, id, file); endfunction function void uvm_component::set_report_verbosity_level_hier(int verbosity); set_report_verbosity_level(verbosity); foreach( m_children[c] ) m_children[c].set_report_verbosity_level_hier(verbosity); endfunction function void uvm_component::build_phase(uvm_phase phase); m_build_done = 1; if (use_automatic_config()) apply_config_settings(print_config_matches); endfunction function void uvm_component::connect_phase(uvm_phase phase); return; endfunction function void uvm_component::start_of_simulation_phase(uvm_phase phase); return; endfunction function void uvm_component::end_of_elaboration_phase(uvm_phase phase); return; endfunction task uvm_component::run_phase(uvm_phase phase); return; endtask function void uvm_component::extract_phase(uvm_phase phase); return; endfunction function void uvm_component::check_phase(uvm_phase phase); return; endfunction function void uvm_component::report_phase(uvm_phase phase); return; endfunction function void uvm_component::final_phase(uvm_phase phase); return; endfunction task uvm_component::pre_reset_phase(uvm_phase phase); return; endtask task uvm_component::reset_phase(uvm_phase phase); return; endtask task uvm_component::post_reset_phase(uvm_phase phase); return; endtask task uvm_component::pre_configure_phase(uvm_phase phase); return; endtask task uvm_component::configure_phase(uvm_phase phase); return; endtask task uvm_component::post_configure_phase(uvm_phase phase); return; endtask task uvm_component::pre_main_phase(uvm_phase phase); return; endtask task uvm_component::main_phase(uvm_phase phase); return; endtask task uvm_component::post_main_phase(uvm_phase phase); return; endtask task uvm_component::pre_shutdown_phase(uvm_phase phase); return; endtask task uvm_component::shutdown_phase(uvm_phase phase); return; endtask task uvm_component::post_shutdown_phase(uvm_phase phase); return; endtask function void uvm_component::phase_started(uvm_phase phase); endfunction function void uvm_component::phase_ended(uvm_phase phase); endfunction function void uvm_component::phase_ready_to_end (uvm_phase phase); endfunction function void uvm_component::define_domain(uvm_domain domain); uvm_phase schedule; schedule = domain.find_by_name("uvm_sched"); if (schedule == null) begin uvm_domain common; schedule = new("uvm_sched", UVM_PHASE_SCHEDULE); uvm_domain::add_uvm_phases(schedule); domain.add(schedule); common = uvm_domain::get_common_domain(); if (common.find(domain,0) == null) common.add(domain,.with_phase(uvm_run_phase::get())); end endfunction function void uvm_component::set_domain(uvm_domain domain, int hier=1); m_domain = domain; define_domain(domain); if (hier) foreach (m_children[c]) m_children[c].set_domain(domain); endfunction function uvm_domain uvm_component::get_domain(); return m_domain; endfunction task uvm_component::suspend(); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"COMP/SPND/UNIMP")) uvm_report_warning ("COMP/SPND/UNIMP", "suspend() not implemented", UVM_NONE, "t/uvm/src/base/uvm_component.svh", 2395, "", 1); end endtask task uvm_component::resume(); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"COMP/RSUM/UNIMP")) uvm_report_warning ("COMP/RSUM/UNIMP", "resume() not implemented", UVM_NONE, "t/uvm/src/base/uvm_component.svh", 2403, "", 1); end endtask function void uvm_component::resolve_bindings(); return; endfunction function void uvm_component::do_resolve_bindings(); foreach( m_children[s] ) m_children[s].do_resolve_bindings(); resolve_bindings(); endfunction function void uvm_component::accept_tr (uvm_transaction tr, time accept_time=0); uvm_event#(uvm_object) e; if(tr == null) return; tr.accept_tr(accept_time); do_accept_tr(tr); e = event_pool.get("accept_tr"); if(e!=null) e.trigger(); endfunction function int uvm_component::begin_tr (uvm_transaction tr, string stream_name="main", string label="", string desc="", time begin_time=0, int parent_handle=0); return m_begin_tr(tr, parent_handle, stream_name, label, desc, begin_time); endfunction function uvm_tr_database uvm_component::get_tr_database(); if (tr_database == null) begin uvm_coreservice_t cs = uvm_coreservice_t::get(); tr_database = cs.get_default_tr_database(); end return tr_database; endfunction : get_tr_database function void uvm_component::set_tr_database(uvm_tr_database db); tr_database = db; endfunction : set_tr_database function uvm_tr_stream uvm_component::get_tr_stream( string name, string stream_type_name="" ); uvm_tr_database db = get_tr_database(); if (!m_streams.exists(name) || !m_streams[name].exists(stream_type_name)) m_streams[name][stream_type_name] = db.open_stream(name, this.get_full_name(), stream_type_name); return m_streams[name][stream_type_name]; endfunction : get_tr_stream function void uvm_component::free_tr_stream(uvm_tr_stream stream); if (stream == null) return; if (!m_streams.exists(stream.get_name()) || !m_streams[stream.get_name()].exists(stream.get_stream_type_name())) return; if (m_streams[stream.get_name()][stream.get_stream_type_name()] != stream) return; m_streams[stream.get_name()].delete(stream.get_type_name()); if (m_streams[stream.get_name()].size() == 0) m_streams.delete(stream.get_name()); if (stream.is_open() || stream.is_closed()) begin stream.free(); end endfunction : free_tr_stream function int uvm_component::m_begin_tr (uvm_transaction tr, int parent_handle=0, string stream_name="main", string label="", string desc="", time begin_time=0); uvm_event#(uvm_object) e; string name; string kind; uvm_tr_database db; int handle, link_handle; uvm_tr_stream stream; uvm_recorder recorder, parent_recorder, link_recorder; if (tr == null) return 0; db = get_tr_database(); if (parent_handle != 0) parent_recorder = uvm_recorder::get_recorder_from_handle(parent_handle); if (parent_recorder == null) begin uvm_sequence_item seq; if ($cast(seq,tr)) begin uvm_sequence_base parent_seq = seq.get_parent_sequence(); if (parent_seq != null) begin parent_recorder = parent_seq.m_tr_recorder; end end end if(parent_recorder != null) begin link_handle = tr.begin_child_tr(begin_time, parent_recorder.get_handle()); end else begin link_handle = tr.begin_tr(begin_time); end if (link_handle != 0) link_recorder = uvm_recorder::get_recorder_from_handle(link_handle); if (tr.get_name() != "") name = tr.get_name(); else name = tr.get_type_name(); if (uvm_verbosity'(recording_detail) != UVM_NONE) begin if (stream_name == "") stream_name = "main"; stream = get_tr_stream(stream_name, "TVM"); if (stream != null ) begin kind = (parent_recorder == null) ? "Begin_No_Parent, Link" : "Begin_End, Link"; recorder = stream.open_recorder(name, begin_time, kind); if (recorder != null) begin if (label != "") recorder.record_string("label", label); if (desc != "") recorder.record_string("desc", desc); if (parent_recorder != null) begin tr_database.establish_link(uvm_parent_child_link::get_link(parent_recorder, recorder)); end if (link_recorder != null) begin tr_database.establish_link(uvm_related_link::get_link(recorder, link_recorder)); end m_tr_h[tr] = recorder; end end handle = (recorder == null) ? 0 : recorder.get_handle(); do_begin_tr(tr, stream_name, handle); end e = event_pool.get("begin_tr"); if (e!=null) e.trigger(tr); return handle; endfunction function void uvm_component::end_tr (uvm_transaction tr, time end_time=0, bit free_handle=1); uvm_event#(uvm_object) e; uvm_recorder recorder; if (tr == null) return; tr.end_tr(end_time,free_handle); if (uvm_verbosity'(recording_detail) != UVM_NONE) begin if (m_tr_h.exists(tr)) begin recorder = m_tr_h[tr]; do_end_tr(tr, recorder.get_handle()); m_tr_h.delete(tr); tr.record(recorder); recorder.close(end_time); if (free_handle) recorder.free(); end else begin do_end_tr(tr, 0); end end e = event_pool.get("end_tr"); if(e!=null) e.trigger(); endfunction function int uvm_component::record_error_tr (string stream_name="main", uvm_object info=null, string label="error_tr", string desc="", time error_time=0, bit keep_active=0); uvm_recorder recorder; string etype; uvm_tr_stream stream; int handle; if(keep_active) etype = "Error, Link"; else etype = "Error"; if(error_time == 0) error_time = $realtime; if (stream_name == "") stream_name = "main"; stream = get_tr_stream(stream_name, "TVM"); handle = 0; if (stream != null) begin recorder = stream.open_recorder(label, error_time, etype); if (recorder != null) begin if (label != "") recorder.record_string("label", label); if (desc != "") recorder.record_string("desc", desc); if (info!=null) info.record(recorder); recorder.close(error_time); if (keep_active == 0) begin recorder.free(); end else begin handle = recorder.get_handle(); end end end return handle; endfunction function int uvm_component::record_event_tr (string stream_name="main", uvm_object info=null, string label="event_tr", string desc="", time event_time=0, bit keep_active=0); uvm_recorder recorder; string etype; int handle; uvm_tr_stream stream; if(keep_active) etype = "Event, Link"; else etype = "Event"; if(event_time == 0) event_time = $realtime; if (stream_name == "") stream_name = "main"; stream = get_tr_stream(stream_name, "TVM"); handle = 0; if (stream != null) begin recorder = stream.open_recorder(label, event_time, etype); if (recorder != null) begin if (label != "") recorder.record_string("label", label); if (desc != "") recorder.record_string("desc", desc); if (info!=null) info.record(recorder); recorder.close(event_time); if (keep_active == 0) begin recorder.free(); end else begin handle = recorder.get_handle(); end end end return handle; endfunction function void uvm_component::do_accept_tr (uvm_transaction tr); return; endfunction function void uvm_component::do_begin_tr (uvm_transaction tr, string stream_name, int tr_handle); return; endfunction function void uvm_component::do_end_tr (uvm_transaction tr, int tr_handle); return; endfunction function string uvm_component::massage_scope(string scope); if(scope == "") return "^$"; if(scope == "*") return {get_full_name(), ".*"}; if(scope == "uvm_test_top") return "uvm_test_top"; if(scope[0] == ".") return {get_full_name(), scope}; return {get_full_name(), ".", scope}; endfunction function bit uvm_component::use_automatic_config(); return 1; endfunction function void uvm_component::apply_config_settings (bit verbose=0); uvm_resource_pool rp = uvm_resource_pool::get(); uvm_queue#(uvm_resource_base) rq; uvm_resource_base r; rq = rp.lookup_scope(get_full_name()); rp.sort_by_precedence(rq); for(int i=rq.size()-1; i>=0; --i) begin r = rq.get(i); if(verbose) uvm_report_info("CFGAPL",$sformatf("applying configuration to field %s", r.get_name()),UVM_NONE); set_local(r); end endfunction function void uvm_component::print_config(bit recurse = 0, audit = 0); uvm_resource_pool rp = uvm_resource_pool::get(); uvm_report_info("CFGPRT","visible resources:",UVM_INFO); rp.print_resources(rp.lookup_scope(get_full_name()), audit); if(recurse) begin uvm_component c; foreach(m_children[name]) begin c = m_children[name]; c.print_config(recurse, audit); end end endfunction function void uvm_component::print_config_with_audit(bit recurse = 0); print_config(recurse, 1); endfunction function void uvm_component::do_print(uvm_printer printer); super.do_print(printer); if(uvm_verbosity'(recording_detail) != UVM_NONE) case (recording_detail) UVM_LOW : printer.print_generic("recording_detail", "uvm_verbosity", $bits(recording_detail), "UVM_LOW"); UVM_MEDIUM : printer.print_generic("recording_detail", "uvm_verbosity", $bits(recording_detail), "UVM_MEDIUM"); UVM_HIGH : printer.print_generic("recording_detail", "uvm_verbosity", $bits(recording_detail), "UVM_HIGH"); UVM_FULL : printer.print_generic("recording_detail", "uvm_verbosity", $bits(recording_detail), "UVM_FULL"); default : printer.print_field_int("recording_detail", recording_detail, $bits(recording_detail), UVM_DEC, , "integral"); endcase endfunction function void uvm_component::set_local(uvm_resource_base rsrc) ; bit success; if((rsrc != null) && (rsrc.get_name() == "recording_detail")) begin begin begin uvm_resource#(uvm_integral_t) __tmp_rsrc__; success = $cast(__tmp_rsrc__, rsrc); if (success) begin recording_detail = __tmp_rsrc__.read(this); end end if (!success) begin uvm_resource#(uvm_bitstream_t) __tmp_rsrc__; success = $cast(__tmp_rsrc__, rsrc); if (success) begin recording_detail = __tmp_rsrc__.read(this); end end if (!success) begin uvm_resource#(int) __tmp_rsrc__; success = $cast(__tmp_rsrc__, rsrc); if (success) begin recording_detail = __tmp_rsrc__.read(this); end end if (!success) begin uvm_resource#(int unsigned) __tmp_rsrc__; success = $cast(__tmp_rsrc__, rsrc); if (success) begin recording_detail = __tmp_rsrc__.read(this); end end end end if (!success) super.set_local(rsrc); endfunction function void uvm_component::m_unsupported_set_local(uvm_resource_base rsrc); m_unsupported_resource_base = rsrc; endfunction typedef class uvm_cmdline_processor; function void uvm_component::m_set_cl_msg_args; string s_; process p_; p_=process::self(); if(p_!=null) s_=p_.get_randstate(); else begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM")) uvm_report_warning ("UVM", "run_test() invoked from a non process context", UVM_NONE, "t/uvm/src/base/uvm_component.svh", 3043, "", 1); end m_set_cl_verb(); m_set_cl_action(); m_set_cl_sev(); if(p_!=null) p_.set_randstate(s_); endfunction function void uvm_component::m_set_cl_verb; static string values[$]; static bit first = 1; string args[$]; uvm_cmdline_processor clp = uvm_cmdline_processor::get_inst(); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); if(first) begin string t[$]; m_verbosity_setting setting; void'(clp.get_arg_values("+uvm_set_verbosity=",values)); foreach(values[i]) begin args.delete(); uvm_split_string(values[i], ",", args); if(((args.size() == 4) || (args.size() == 5)) && (clp.m_convert_verb(args[2], setting.verbosity) == 1) ) t.push_back(values[i]); else uvm_report_warning("UVM/CMDLINE",$sformatf("argument %s not recognized and therefore dropped",values[i])); end values=t; first=0; end foreach(values[i]) begin m_verbosity_setting setting; args.delete(); uvm_split_string(values[i], ",", args); begin setting.comp = args[0]; setting.id = args[1]; void'(clp.m_convert_verb(args[2],setting.verbosity)); setting.phase = args[3]; setting.offset = 0; if(args.size() == 5) setting.offset = args[4].atoi(); if((setting.phase == "time") && (this == top)) begin m_time_settings.push_back(setting); end if (uvm_is_match(setting.comp, get_full_name()) ) begin if((setting.phase == "" || setting.phase == "build" || setting.phase == "time") && (setting.offset == 0) ) begin if(setting.id == "_ALL_") set_report_verbosity_level(setting.verbosity); else set_report_id_verbosity(setting.id, setting.verbosity); end else begin if(setting.phase != "time") begin m_verbosity_settings.push_back(setting); end end end end end if(this == top) begin fork begin time last_time = 0; if (m_time_settings.size() > 0) m_time_settings.sort() with ( item.offset ); foreach(m_time_settings[i]) begin uvm_component comps[$]; top.find_all(m_time_settings[i].comp,comps); #(m_time_settings[i].offset - last_time); last_time = m_time_settings[i].offset; if(m_time_settings[i].id == "_ALL_") begin foreach(comps[j]) begin comps[j].set_report_verbosity_level(m_time_settings[i].verbosity); end end else begin foreach(comps[j]) begin comps[j].set_report_id_verbosity(m_time_settings[i].id, m_time_settings[i].verbosity); end end end end join_none end endfunction function void uvm_component::m_set_cl_action; static bit initialized = 0; uvm_severity sev; uvm_action action; uvm_cmdline_processor uvm_cmdline_proc = uvm_cmdline_processor::get_inst(); if(!initialized) begin string values[$]; void'(uvm_cmdline_proc.get_arg_values("+uvm_set_action=",values)); foreach(values[idx]) begin uvm_cmdline_parsed_arg_t t; string args[$]; uvm_split_string(values[idx], ",", args); if(args.size() != 4) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"INVLCMDARGS")) uvm_report_warning ("INVLCMDARGS", $sformatf("+uvm_set_action requires 4 arguments, but %0d given for command +uvm_set_action=%s, Usage: +uvm_set_action=,,,", args.size(), values[idx]), UVM_NONE, "t/uvm/src/base/uvm_component.svh", 3169, "", 1); end continue; end if((args[2] != "_ALL_") && !uvm_string_to_severity(args[2], sev)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"INVLCMDARGS")) uvm_report_warning ("INVLCMDARGS", $sformatf("Bad severity argument \"%s\" given to command +uvm_set_action=%s, Usage: +uvm_set_action=,,,", args[2], values[idx]), UVM_NONE, "t/uvm/src/base/uvm_component.svh", 3173, "", 1); end continue; end if(!uvm_string_to_action(args[3], action)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"INVLCMDARGS")) uvm_report_warning ("INVLCMDARGS", $sformatf("Bad action argument \"%s\" given to command +uvm_set_action=%s, Usage: +uvm_set_action=,,,", args[3], values[idx]), UVM_NONE, "t/uvm/src/base/uvm_component.svh", 3177, "", 1); end continue; end t.args=args; t.arg=values[idx]; m_uvm_applied_cl_action.push_back(t); end initialized=1; end foreach(m_uvm_applied_cl_action[i]) begin string args[$] = m_uvm_applied_cl_action[i].args; if (!uvm_is_match(args[0], get_full_name()) ) continue; void'(uvm_string_to_severity(args[2], sev)); void'(uvm_string_to_action(args[3], action)); m_uvm_applied_cl_action[i].used++; if(args[1] == "_ALL_") begin if(args[2] == "_ALL_") begin set_report_severity_action(UVM_INFO, action); set_report_severity_action(UVM_WARNING, action); set_report_severity_action(UVM_ERROR, action); set_report_severity_action(UVM_FATAL, action); end else begin set_report_severity_action(sev, action); end end else begin if(args[2] == "_ALL_") begin set_report_id_action(args[1], action); end else begin set_report_severity_id_action(sev, args[1], action); end end end endfunction function void uvm_component::m_set_cl_sev; static bit initialized; uvm_severity orig_sev, sev; uvm_cmdline_processor uvm_cmdline_proc = uvm_cmdline_processor::get_inst(); if(!initialized) begin string values[$]; void'(uvm_cmdline_proc.get_arg_values("+uvm_set_severity=",values)); foreach(values[idx]) begin uvm_cmdline_parsed_arg_t t; string args[$]; uvm_split_string(values[idx], ",", args); if(args.size() != 4) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"INVLCMDARGS")) uvm_report_warning ("INVLCMDARGS", $sformatf("+uvm_set_severity requires 4 arguments, but %0d given for command +uvm_set_severity=%s, Usage: +uvm_set_severity=,,,", args.size(), values[idx]), UVM_NONE, "t/uvm/src/base/uvm_component.svh", 3240, "", 1); end continue; end if(args[2] != "_ALL_" && !uvm_string_to_severity(args[2], orig_sev)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"INVLCMDARGS")) uvm_report_warning ("INVLCMDARGS", $sformatf("Bad severity argument \"%s\" given to command +uvm_set_severity=%s, Usage: +uvm_set_severity=,,,", args[2], values[idx]), UVM_NONE, "t/uvm/src/base/uvm_component.svh", 3244, "", 1); end continue; end if(!uvm_string_to_severity(args[3], sev)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"INVLCMDARGS")) uvm_report_warning ("INVLCMDARGS", $sformatf("Bad severity argument \"%s\" given to command +uvm_set_severity=%s, Usage: +uvm_set_severity=,,,", args[3], values[idx]), UVM_NONE, "t/uvm/src/base/uvm_component.svh", 3248, "", 1); end continue; end t.args=args; t.arg=values[idx]; m_uvm_applied_cl_sev.push_back(t); end initialized=1; end foreach(m_uvm_applied_cl_sev[i]) begin string args[$]=m_uvm_applied_cl_sev[i].args; if (!uvm_is_match(args[0], get_full_name()) ) continue; void'(uvm_string_to_severity(args[2], orig_sev)); void'(uvm_string_to_severity(args[3], sev)); m_uvm_applied_cl_sev[i].used++; if(args[1] == "_ALL_" && args[2] == "_ALL_") begin set_report_severity_override(UVM_INFO,sev); set_report_severity_override(UVM_WARNING,sev); set_report_severity_override(UVM_ERROR,sev); set_report_severity_override(UVM_FATAL,sev); end else if(args[1] == "_ALL_") begin set_report_severity_override(orig_sev,sev); end else if(args[2] == "_ALL_") begin set_report_severity_id_override(UVM_INFO,args[1],sev); set_report_severity_id_override(UVM_WARNING,args[1],sev); set_report_severity_id_override(UVM_ERROR,args[1],sev); set_report_severity_id_override(UVM_FATAL,args[1],sev); end else begin set_report_severity_id_override(orig_sev,args[1],sev); end end endfunction function void uvm_component::m_apply_verbosity_settings(uvm_phase phase); int i; while (i < m_verbosity_settings.size()) begin if(phase.get_name() == m_verbosity_settings[i].phase) begin if( m_verbosity_settings[i].offset == 0 ) begin if(m_verbosity_settings[i].id == "_ALL_") set_report_verbosity_level(m_verbosity_settings[i].verbosity); else set_report_id_verbosity(m_verbosity_settings[i].id, m_verbosity_settings[i].verbosity); end else begin process p = process::self(); string p_rand = p.get_randstate(); fork begin m_verbosity_setting setting = m_verbosity_settings[i]; #setting.offset; if(setting.id == "_ALL_") set_report_verbosity_level(setting.verbosity); else set_report_id_verbosity(setting.id, setting.verbosity); end join_none p.set_randstate(p_rand); end m_verbosity_settings.delete(i); continue; end i++; end endfunction function void uvm_component::m_do_pre_abort; foreach(m_children[i]) m_children[i].m_do_pre_abort(); pre_abort(); endfunction `define UVM_OBJECTION_SVH typedef class uvm_objection_context_object; typedef class uvm_objection; typedef class uvm_sequence_base; typedef class uvm_objection_callback; typedef uvm_callbacks #(uvm_objection,uvm_objection_callback) uvm_objection_cbs_t; typedef class uvm_cmdline_processor; class uvm_objection_events; int waiters; event raised; event dropped; event all_dropped; endclass class uvm_objection extends uvm_report_object; static local bit m_register_cb_uvm_objection_callback = uvm_callbacks#(uvm_objection,uvm_objection_callback)::m_register_pair("uvm_objection","uvm_objection_callback"); protected bit m_trace_mode; protected int m_source_count[uvm_object]; protected int m_total_count [uvm_object]; protected time m_drain_time [uvm_object]; protected uvm_objection_events m_events [uvm_object]; bit m_top_all_dropped; protected uvm_root m_top; static uvm_objection m_objections[$]; local static uvm_objection_context_object m_context_pool[$]; local process m_drain_proc[uvm_object]; local static uvm_objection_context_object m_scheduled_list[$]; local uvm_objection_context_object m_scheduled_contexts[uvm_object]; local uvm_objection_context_object m_forked_list[$]; local uvm_objection_context_object m_forked_contexts[uvm_object]; protected bit m_prop_mode = 1; protected bit m_cleared; function new(string name=""); uvm_cmdline_processor clp; uvm_coreservice_t cs_ ; string trace_args[$]; super.new(name); cs_ = uvm_coreservice_t::get(); m_top = cs_.get_root(); set_report_verbosity_level(m_top.get_report_verbosity_level()); clp = uvm_cmdline_processor::get_inst(); if(clp.get_arg_matches("+UVM_OBJECTION_TRACE", trace_args)) begin m_trace_mode=1; end m_objections.push_back(this); endfunction function bit trace_mode (int mode=-1); trace_mode = m_trace_mode; if(mode == 0) m_trace_mode = 0; else if(mode == 1) m_trace_mode = 1; endfunction function void m_report(uvm_object obj, uvm_object source_obj, string description, int count, string action); int _count = m_source_count.exists(obj) ? m_source_count[obj] : 0; int _total = m_total_count.exists(obj) ? m_total_count[obj] : 0; if (!uvm_report_enabled(UVM_NONE,UVM_INFO,"OBJTN_TRC") || !m_trace_mode) return; if (source_obj == obj) uvm_report_info("OBJTN_TRC", $sformatf("Object %0s %0s %0d objection(s)%s: count=%0d total=%0d", obj.get_full_name()==""?"uvm_top":obj.get_full_name(), action, count, description != ""? {" (",description,")"}:"", _count, _total), UVM_NONE); else begin int cpath = 0, last_dot=0; string sname = source_obj.get_full_name(), nm = obj.get_full_name(); int max = sname.len() > nm.len() ? nm.len() : sname.len(); while((sname[cpath] == nm[cpath]) && (cpath < max)) begin if(sname[cpath] == ".") last_dot = cpath; cpath++; end if(last_dot) sname = sname.substr(last_dot+1, sname.len()); uvm_report_info("OBJTN_TRC", $sformatf("Object %0s %0s %0d objection(s) %0s its total (%s from source object %s%s): count=%0d total=%0d", obj.get_full_name()==""?"uvm_top":obj.get_full_name(), action=="raised"?"added":"subtracted", count, action=="raised"?"to":"from", action, sname, description != ""?{", ",description}:"", _count, _total), UVM_NONE); end endfunction function uvm_object m_get_parent(uvm_object obj); uvm_component comp; uvm_sequence_base seq; if ($cast(comp, obj)) begin obj = comp.get_parent(); end else if ($cast(seq, obj)) begin obj = seq.get_sequencer(); end else obj = m_top; if (obj == null) obj = m_top; return obj; endfunction function void m_propagate (uvm_object obj, uvm_object source_obj, string description, int count, bit raise, int in_top_thread); if (obj != null && obj != m_top) begin obj = m_get_parent(obj); if(raise) m_raise(obj, source_obj, description, count); else m_drop(obj, source_obj, description, count, in_top_thread); end endfunction function void set_propagate_mode (bit prop_mode); if (!m_top_all_dropped && (get_objection_total() != 0)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/BASE/OBJTN/PROP_MODE")) uvm_report_error ("UVM/BASE/OBJTN/PROP_MODE", {"The propagation mode of '", this.get_full_name(), "' cannot be changed while the objection is raised ", "or draining!"}, UVM_NONE, "t/uvm/src/base/uvm_objection.svh", 265, "", 1); end return; end m_prop_mode = prop_mode; endfunction : set_propagate_mode function bit get_propagate_mode(); return m_prop_mode; endfunction : get_propagate_mode virtual function void raise_objection (uvm_object obj=null, string description="", int count=1); if(obj == null) obj = m_top; m_cleared = 0; m_top_all_dropped = 0; m_raise (obj, obj, description, count); endfunction function void m_raise (uvm_object obj, uvm_object source_obj, string description="", int count=1); int idx; uvm_objection_context_object ctxt; if (count == 0) return; if (m_total_count.exists(obj)) m_total_count[obj] += count; else m_total_count[obj] = count; if (source_obj==obj) begin if (m_source_count.exists(obj)) m_source_count[obj] += count; else m_source_count[obj] = count; end if (m_trace_mode) m_report(obj,source_obj,description,count,"raised"); raised(obj, source_obj, description, count); idx = 0; while (idx < m_scheduled_list.size()) begin if ((m_scheduled_list[idx].obj == obj) && (m_scheduled_list[idx].objection == this)) begin ctxt = m_scheduled_list[idx]; m_scheduled_list.delete(idx); break; end idx++; end if (ctxt == null) begin idx = 0; while (idx < m_forked_list.size()) begin if (m_forked_list[idx].obj == obj) begin ctxt = m_forked_list[idx]; m_forked_list.delete(idx); m_scheduled_contexts.delete(ctxt.obj); break; end idx++; end end if (ctxt == null) begin if (m_forked_contexts.exists(obj)) begin ctxt = m_forked_contexts[obj]; m_forked_contexts.delete(obj); m_drain_proc[obj].kill(); m_drain_proc.delete(obj); end end if (ctxt == null) begin if (!m_prop_mode && obj != m_top) m_raise(m_top,source_obj,description,count); else if (obj != m_top) m_propagate(obj, source_obj, description, count, 1, 0); end else begin int diff_count; diff_count = count - ctxt.count; if (diff_count != 0) begin if (diff_count > 0) begin if (!m_prop_mode && obj != m_top) m_raise(m_top, source_obj, description, diff_count); else if (obj != m_top) m_propagate(obj, source_obj, description, diff_count, 1, 0); end else begin diff_count = -diff_count; if (!m_prop_mode && obj != m_top) m_drop(m_top, source_obj, description, diff_count); else if (obj != m_top) m_propagate(obj, source_obj, description, diff_count, 0, 0); end end ctxt.clear(); m_context_pool.push_back(ctxt); end endfunction virtual function void drop_objection (uvm_object obj=null, string description="", int count=1); if(obj == null) obj = m_top; m_drop (obj, obj, description, count, 0); endfunction function void m_drop (uvm_object obj, uvm_object source_obj, string description="", int count=1, int in_top_thread=0); if (count == 0) return; if (!m_total_count.exists(obj) || (count > m_total_count[obj])) begin if(m_cleared) return; uvm_report_fatal("OBJTN_ZERO", {"Object \"", obj.get_full_name(), "\" attempted to drop objection '",this.get_name(),"' count below zero"}); return; end if (obj == source_obj) begin if (!m_source_count.exists(obj) || (count > m_source_count[obj])) begin if(m_cleared) return; uvm_report_fatal("OBJTN_ZERO", {"Object \"", obj.get_full_name(), "\" attempted to drop objection '",this.get_name(),"' count below zero"}); return; end m_source_count[obj] -= count; end m_total_count[obj] -= count; if (m_trace_mode) m_report(obj,source_obj,description,count,"dropped"); dropped(obj, source_obj, description, count); if (m_total_count[obj] != 0) begin if (!m_prop_mode && obj != m_top) m_drop(m_top,source_obj,description, count, in_top_thread); else if (obj != m_top) begin this.m_propagate(obj, source_obj, description, count, 0, in_top_thread); end end else begin uvm_objection_context_object ctxt; if (m_context_pool.size()) ctxt = m_context_pool.pop_front(); else ctxt = new; ctxt.obj = obj; ctxt.source_obj = source_obj; ctxt.description = description; ctxt.count = count; ctxt.objection = this; m_scheduled_list.push_back(ctxt); end endfunction virtual function void clear(uvm_object obj=null); string name; int idx; if (obj==null) obj=m_top; name = obj.get_full_name(); if (name == "") name = "uvm_top"; else name = obj.get_full_name(); if (!m_top_all_dropped && get_objection_total(m_top)) uvm_report_warning("OBJTN_CLEAR",{"Object '",name, "' cleared objection counts for ",get_name()}); m_source_count.delete(); m_total_count.delete(); idx = 0; while (idx < m_scheduled_list.size()) begin if (m_scheduled_list[idx].objection == this) begin m_scheduled_list[idx].clear(); m_context_pool.push_back(m_scheduled_list[idx]); m_scheduled_list.delete(idx); end else begin idx++; end end m_scheduled_contexts.delete(); while (m_forked_list.size()) begin m_forked_list[0].clear(); m_context_pool.push_back(m_forked_list[0]); void'(m_forked_list.pop_front()); end foreach (m_forked_contexts[o]) begin m_drain_proc[o].kill(); m_drain_proc.delete(o); m_forked_contexts[o].clear(); m_context_pool.push_back(m_forked_contexts[o]); m_forked_contexts.delete(o); end m_top_all_dropped = 0; m_cleared = 1; if (m_events.exists(m_top)) ->m_events[m_top].all_dropped; endfunction static task m_execute_scheduled_forks(); while(1) begin wait(m_scheduled_list.size() != 0); if(m_scheduled_list.size() != 0) begin uvm_objection_context_object c; c = m_scheduled_list.pop_front(); c.objection.m_scheduled_contexts[c.obj] = c; c.objection.m_forked_list.push_back(c); fork : guard automatic uvm_objection objection = c.objection; begin if (objection.m_forked_list.size() > 0) begin uvm_objection_context_object ctxt; ctxt = objection.m_forked_list.pop_front(); objection.m_scheduled_contexts.delete(ctxt.obj); objection.m_forked_contexts[ctxt.obj] = ctxt; objection.m_drain_proc[ctxt.obj] = process::self(); objection.m_forked_drain(ctxt.obj, ctxt.source_obj, ctxt.description, ctxt.count, 1); objection.m_drain_proc.delete(ctxt.obj); objection.m_forked_contexts.delete(ctxt.obj); ctxt.clear(); m_context_pool.push_back(ctxt); end end join_none : guard end end endtask task m_forked_drain (uvm_object obj, uvm_object source_obj, string description="", int count=1, int in_top_thread=0); if (m_drain_time.exists(obj)) #(m_drain_time[obj]); if (m_trace_mode) m_report(obj,source_obj,description,count,"all_dropped"); all_dropped(obj,source_obj,description, count); wait fork; if (m_source_count.exists(obj) && m_source_count[obj] == 0) m_source_count.delete(obj); if (m_total_count.exists(obj) && m_total_count[obj] == 0) m_total_count.delete(obj); if (!m_prop_mode && obj != m_top) m_drop(m_top,source_obj,description, count, 1); else if (obj != m_top) m_propagate(obj, source_obj, description, count, 0, 1); endtask static function void m_init_objections(); fork uvm_objection::m_execute_scheduled_forks(); join_none endfunction function void set_drain_time (uvm_object obj=null, time drain); if (obj==null) obj = m_top; m_drain_time[obj] = drain; endfunction virtual function void raised (uvm_object obj, uvm_object source_obj, string description, int count); uvm_component comp; if ($cast(comp,obj)) comp.raised(this, source_obj, description, count); begin uvm_callback_iter#(uvm_objection,uvm_objection_callback) iter = new(this); uvm_objection_callback cb = iter.first(); while(cb != null) begin cb.raised(this,obj,source_obj,description,count); cb = iter.next(); end end if (m_events.exists(obj)) ->m_events[obj].raised; endfunction virtual function void dropped (uvm_object obj, uvm_object source_obj, string description, int count); uvm_component comp; if($cast(comp,obj)) comp.dropped(this, source_obj, description, count); begin uvm_callback_iter#(uvm_objection,uvm_objection_callback) iter = new(this); uvm_objection_callback cb = iter.first(); while(cb != null) begin cb.dropped(this,obj,source_obj,description,count); cb = iter.next(); end end if (m_events.exists(obj)) ->m_events[obj].dropped; endfunction virtual task all_dropped (uvm_object obj, uvm_object source_obj, string description, int count); uvm_component comp; if($cast(comp,obj)) comp.all_dropped(this, source_obj, description, count); begin uvm_callback_iter#(uvm_objection,uvm_objection_callback) iter = new(this); uvm_objection_callback cb = iter.first(); while(cb != null) begin cb.all_dropped(this,obj,source_obj,description,count); cb = iter.next(); end end if (m_events.exists(obj)) ->m_events[obj].all_dropped; if (obj == m_top) m_top_all_dropped = 1; endtask function void get_objectors(ref uvm_object list[$]); list.delete(); foreach (m_source_count[obj]) list.push_back(obj); endfunction task wait_for(uvm_objection_event objt_event, uvm_object obj=null); if (obj==null) obj = m_top; if (!m_events.exists(obj)) begin m_events[obj] = new; end m_events[obj].waiters++; case (objt_event) UVM_RAISED: @(m_events[obj].raised); UVM_DROPPED: @(m_events[obj].dropped); UVM_ALL_DROPPED: @(m_events[obj].all_dropped); endcase m_events[obj].waiters--; if (m_events[obj].waiters == 0) m_events.delete(obj); endtask task wait_for_total_count(uvm_object obj=null, int count=0); if (obj==null) obj = m_top; if(!m_total_count.exists(obj) && count == 0) return; if (count == 0) wait (!m_total_count.exists(obj) && count == 0); else wait (m_total_count.exists(obj) && m_total_count[obj] == count); endtask function int get_objection_count (uvm_object obj=null); if (obj==null) obj = m_top; if (!m_source_count.exists(obj)) return 0; return m_source_count[obj]; endfunction function int get_objection_total (uvm_object obj=null); if (obj==null) obj = m_top; if (!m_total_count.exists(obj)) return 0; else return m_total_count[obj]; endfunction function time get_drain_time (uvm_object obj=null); if (obj==null) obj = m_top; if (!m_drain_time.exists(obj)) return 0; return m_drain_time[obj]; endfunction protected function string m_display_objections(uvm_object obj=null, bit show_header=1); static string blank=" "; string s; int total; uvm_object list[string]; uvm_object curr_obj; int depth; string name; string this_obj_name; string curr_obj_name; foreach (m_total_count[o]) begin uvm_object theobj = o; if ( m_total_count[o] > 0) list[theobj.get_full_name()] = theobj; end if (obj==null) obj = m_top; total = get_objection_total(obj); s = $sformatf("The total objection count is %0d\n",total); if (total == 0) return s; s = {s,"---------------------------------------------------------\n"}; s = {s,"Source Total \n"}; s = {s,"Count Count Object\n"}; s = {s,"---------------------------------------------------------\n"}; this_obj_name = obj.get_full_name(); curr_obj_name = this_obj_name; do begin curr_obj = list[curr_obj_name]; depth=0; foreach (curr_obj_name[i]) if (curr_obj_name[i] == ".") depth++; name = curr_obj_name; for (int i=curr_obj_name.len()-1;i >= 0; i--) if (curr_obj_name[i] == ".") begin name = curr_obj_name.substr(i+1,curr_obj_name.len()-1); break; end if (curr_obj_name == "") name = "uvm_top"; else depth++; s = {s, $sformatf("%-6d %-6d %s%s\n", m_source_count.exists(curr_obj) ? m_source_count[curr_obj] : 0, m_total_count.exists(curr_obj) ? m_total_count[curr_obj] : 0, blank.substr(0,2*depth), name)}; end while (list.next(curr_obj_name) && curr_obj_name.substr(0,this_obj_name.len()-1) == this_obj_name); s = {s,"---------------------------------------------------------\n"}; return s; endfunction function string convert2string(); return m_display_objections(m_top,1); endfunction function void display_objections(uvm_object obj=null, bit show_header=1); string m = m_display_objections(obj,show_header); begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"UVM/OBJ/DISPLAY")) uvm_report_info ("UVM/OBJ/DISPLAY", m, UVM_NONE, "t/uvm/src/base/uvm_objection.svh", 1033, "", 1); end endfunction typedef uvm_object_registry#(uvm_objection,"uvm_objection") type_id; static function type_id get_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_objection tmp = new(name); return tmp; endfunction virtual function string get_type_name (); return "uvm_objection"; endfunction function void do_copy (uvm_object rhs); uvm_objection _rhs; $cast(_rhs, rhs); m_source_count = _rhs.m_source_count; m_total_count = _rhs.m_total_count; m_drain_time = _rhs.m_drain_time; m_prop_mode = _rhs.m_prop_mode; endfunction endclass typedef class uvm_cmdline_processor; class uvm_objection_context_object; uvm_object obj; uvm_object source_obj; string description; int count; uvm_objection objection; function void clear(); obj = null; source_obj = null; description = ""; count = 0; objection = null; endfunction : clear endclass typedef uvm_objection uvm_callbacks_objection; class uvm_objection_callback extends uvm_callback; function new(string name); super.new(name); endfunction virtual function void raised (uvm_objection objection, uvm_object obj, uvm_object source_obj, string description, int count); endfunction virtual function void dropped (uvm_objection objection, uvm_object obj, uvm_object source_obj, string description, int count); endfunction virtual task all_dropped (uvm_objection objection, uvm_object obj, uvm_object source_obj, string description, int count); endtask endclass `define UVM_HEARTBEAT_SVH typedef enum { UVM_ALL_ACTIVE, UVM_ONE_ACTIVE, UVM_ANY_ACTIVE, UVM_NO_HB_MODE } uvm_heartbeat_modes; typedef class uvm_heartbeat_callback; typedef uvm_callbacks #(uvm_objection,uvm_heartbeat_callback) uvm_heartbeat_cbs_t ; typedef class uvm_objection_callback; class uvm_heartbeat extends uvm_object; protected uvm_objection m_objection; protected uvm_heartbeat_callback m_cb; protected uvm_component m_cntxt; protected uvm_heartbeat_modes m_mode; protected uvm_component m_hblist[$]; protected uvm_event#(uvm_object) m_event; protected bit m_started; protected event m_stop_event; function new(string name, uvm_component cntxt, uvm_objection objection=null); uvm_coreservice_t cs; super.new(name); m_objection = objection; cs = uvm_coreservice_t::get(); if(cntxt != null) m_cntxt = cntxt; else m_cntxt = cs.get_root(); m_cb = new({name,"_cb"},m_cntxt); endfunction function uvm_heartbeat_modes set_mode (uvm_heartbeat_modes mode = UVM_NO_HB_MODE); set_mode = m_mode; if(mode == UVM_ANY_ACTIVE || mode == UVM_ONE_ACTIVE || mode == UVM_ALL_ACTIVE) m_mode = mode; endfunction function void set_heartbeat (uvm_event#(uvm_object) e, ref uvm_component comps[$]); uvm_object c; foreach(comps[i]) begin c = comps[i]; if(!m_cb.cnt.exists(c)) m_cb.cnt[c]=0; if(!m_cb.last_trigger.exists(c)) m_cb.last_trigger[c]=0; end if(e==null && m_event==null) return; start(e); endfunction function void add (uvm_component comp); uvm_object c = comp; if(m_cb.cnt.exists(c)) return; m_cb.cnt[c]=0; m_cb.last_trigger[c]=0; endfunction function void remove (uvm_component comp); uvm_object c = comp; if(m_cb.cnt.exists(c)) m_cb.cnt.delete(c); if(m_cb.last_trigger.exists(c)) m_cb.last_trigger.delete(c); endfunction function void start (uvm_event#(uvm_object) e=null); if(m_event == null && e == null) begin m_cntxt.uvm_report_warning("NOEVNT", { "start() was called for: ", get_name(), " with a null trigger and no currently set trigger" }, UVM_NONE); return; end if((m_event != null) && (e != m_event) && m_started) begin m_cntxt.uvm_report_error("ILHBVNT", { "start() was called for: ", get_name(), " with trigger ", e.get_name(), " which is different ", "from the original trigger ", m_event.get_name() }, UVM_NONE); return; end if(e != null) m_event = e; m_enable_cb(); m_start_hb_process(); endfunction function void stop (); m_started = 0; ->m_stop_event; m_disable_cb(); endfunction function void m_start_hb_process(); if(m_started) return; m_started = 1; fork m_hb_process; join_none endfunction protected bit m_added; function void m_enable_cb; void'(m_cb.callback_mode(1)); if(m_objection == null) return; if(!m_added) uvm_heartbeat_cbs_t::add(m_objection, m_cb); m_added = 1; endfunction function void m_disable_cb; void'(m_cb.callback_mode(0)); endfunction task m_hb_process; uvm_object obj; bit triggered; time last_trigger=0; fork begin while(1) begin m_event.wait_trigger(); if(triggered) begin case (m_mode) UVM_ALL_ACTIVE: begin foreach(m_cb.cnt[idx]) begin obj = idx; if(!m_cb.cnt[obj]) begin m_cntxt.uvm_report_fatal("HBFAIL", $sformatf("Did not recieve an update of %s for component %s since last event trigger at time %0t : last update time was %0t", m_objection.get_name(), obj.get_full_name(), last_trigger, m_cb.last_trigger[obj]), UVM_NONE); end end end UVM_ANY_ACTIVE: begin if(m_cb.cnt.num() && !m_cb.objects_triggered()) begin string s; foreach(m_cb.cnt[idx]) begin obj = idx; s={s,"\n ",obj.get_full_name()}; end m_cntxt.uvm_report_fatal("HBFAIL", $sformatf("Did not recieve an update of %s on any component since last event trigger at time %0t. The list of registered components is:%s", m_objection.get_name(), last_trigger, s), UVM_NONE); end end UVM_ONE_ACTIVE: begin if(m_cb.objects_triggered() > 1) begin string s; foreach(m_cb.cnt[idx]) begin obj = idx; if(m_cb.cnt[obj]) $swrite(s,"%s\n %s (updated: %0t)", s, obj.get_full_name(), m_cb.last_trigger[obj]); end m_cntxt.uvm_report_fatal("HBFAIL", $sformatf("Recieved update of %s from more than one component since last event trigger at time %0t. The list of triggered components is:%s", m_objection.get_name(), last_trigger, s), UVM_NONE); end if(m_cb.cnt.num() && !m_cb.objects_triggered()) begin string s; foreach(m_cb.cnt[idx]) begin obj = idx; s={s,"\n ",obj.get_full_name()}; end m_cntxt.uvm_report_fatal("HBFAIL", $sformatf("Did not recieve an update of %s on any component since last event trigger at time %0t. The list of registered components is:%s", m_objection.get_name(), last_trigger, s), UVM_NONE); end end endcase end m_cb.reset_counts(); last_trigger = $realtime; triggered = 1; end end @(m_stop_event); join_any disable fork; endtask endclass class uvm_heartbeat_callback extends uvm_objection_callback; int cnt [uvm_object]; time last_trigger [uvm_object]; uvm_object target; uvm_coreservice_t cs = uvm_coreservice_t::get(); function new(string name, uvm_object target); super.new(name); if (target != null) this.target = target; else this.target = cs.get_root(); endfunction virtual function void raised (uvm_objection objection, uvm_object obj, uvm_object source_obj, string description, int count); if(obj == target) begin if(!cnt.exists(source_obj)) cnt[source_obj] = 0; cnt[source_obj] = cnt[source_obj]+1; last_trigger[source_obj] = $realtime; end endfunction virtual function void dropped (uvm_objection objection, uvm_object obj, uvm_object source_obj, string description, int count); raised(objection,obj,source_obj,description,count); endfunction function void reset_counts; foreach(cnt[i]) cnt[i] = 0; endfunction function int objects_triggered; objects_triggered = 0; foreach(cnt[i]) if (cnt[i] != 0) objects_triggered++; endfunction endclass class uvm_cmd_line_verb; string comp_path; string id; uvm_verbosity verb; int exec_time; endclass typedef class uvm_cmdline_processor; uvm_cmdline_processor uvm_cmdline_proc; class uvm_cmdline_processor extends uvm_report_object; static local uvm_cmdline_processor m_inst; static function uvm_cmdline_processor get_inst(); if(m_inst == null) m_inst = new("uvm_cmdline_proc"); uvm_cmdline_proc = m_inst; return m_inst; endfunction protected string m_argv[$]; protected string m_plus_argv[$]; protected string m_uvm_argv[$]; function void get_args (output string args[$]); args = m_argv; endfunction function void get_plusargs (output string args[$]); args = m_plus_argv; endfunction function void get_uvm_args (output string args[$]); args = m_uvm_argv; endfunction function int get_arg_matches (string match, ref string args[$]); bit match_is_regex = (match.len() > 2) && (match[0] == "/") && (match[match.len()-1] == "/"); int len = match.len(); args.delete(); foreach (m_argv[i]) begin if ( match_is_regex && uvm_is_match( match, m_argv[i] ) ) begin args.push_back( m_argv[i] ); end else if((m_argv[i].len() >= len) && (m_argv[i].substr(0,len - 1) == match)) begin args.push_back(m_argv[i]); end end return args.size(); endfunction function int get_arg_value (string match, ref string value); int chars = match.len(); get_arg_value = 0; foreach (m_argv[i]) begin if(m_argv[i].len() >= chars) begin if(m_argv[i].substr(0,chars-1) == match) begin get_arg_value++; if(get_arg_value == 1) value = m_argv[i].substr(chars,m_argv[i].len()-1); end end end endfunction function int get_arg_values (string match, ref string values[$]); int chars = match.len(); values.delete(); foreach (m_argv[i]) begin if(m_argv[i].len() >= chars) begin if(m_argv[i].substr(0,chars-1) == match) values.push_back(m_argv[i].substr(chars,m_argv[i].len()-1)); end end return values.size(); endfunction function string get_tool_name (); return uvm_dpi_get_tool_name(); endfunction function string get_tool_version (); return uvm_dpi_get_tool_version(); endfunction function new(string name = ""); string s; string sub; int doInit=1; super.new(name); do begin s = uvm_dpi_get_next_arg(doInit); doInit=0; if(s!="") begin m_argv.push_back(s); if(s[0] == "+") begin m_plus_argv.push_back(s); end if(s.len() >= 4 && (s[0]=="-" || s[0]=="+")) begin sub = s.substr(1,3); sub = sub.toupper(); if(sub == "UVM") m_uvm_argv.push_back(s); end end end while(s!=""); endfunction function bit m_convert_verb(string verb_str, output uvm_verbosity verb_enum); case (verb_str) "NONE" : begin verb_enum = UVM_NONE; return 1; end "UVM_NONE" : begin verb_enum = UVM_NONE; return 1; end "LOW" : begin verb_enum = UVM_LOW; return 1; end "UVM_LOW" : begin verb_enum = UVM_LOW; return 1; end "MEDIUM" : begin verb_enum = UVM_MEDIUM; return 1; end "UVM_MEDIUM" : begin verb_enum = UVM_MEDIUM; return 1; end "HIGH" : begin verb_enum = UVM_HIGH; return 1; end "UVM_HIGH" : begin verb_enum = UVM_HIGH; return 1; end "FULL" : begin verb_enum = UVM_FULL; return 1; end "UVM_FULL" : begin verb_enum = UVM_FULL; return 1; end "DEBUG" : begin verb_enum = UVM_DEBUG; return 1; end "UVM_DEBUG" : begin verb_enum = UVM_DEBUG; return 1; end default : begin return 0; end endcase endfunction endclass virtual class uvm_visitor#(type NODE=uvm_component) extends uvm_object; function new (string name = ""); super.new(name); endfunction virtual function void begin_v(); endfunction virtual function void end_v(); endfunction pure virtual function void visit(NODE node); endclass virtual class uvm_structure_proxy#(type STRUCTURE=uvm_component) extends uvm_object; function new (string name = ""); super.new(name); endfunction pure virtual function void get_immediate_children(STRUCTURE s, ref STRUCTURE children[$]); endclass virtual class uvm_visitor_adapter#(type STRUCTURE=uvm_component,VISITOR=uvm_visitor#(STRUCTURE)) extends uvm_object; pure virtual function void accept(STRUCTURE s, VISITOR v,uvm_structure_proxy#(STRUCTURE) p, bit invoke_begin_end=1); function new (string name = ""); super.new(name); endfunction endclass class uvm_top_down_visitor_adapter#(type STRUCTURE=uvm_component,VISITOR=uvm_visitor#(STRUCTURE)) extends uvm_visitor_adapter#(STRUCTURE,VISITOR); function new (string name = ""); super.new(name); endfunction virtual function void accept(STRUCTURE s, VISITOR v,uvm_structure_proxy#(STRUCTURE) p, bit invoke_begin_end=1); STRUCTURE c[$]; if(invoke_begin_end) v.begin_v(); v.visit(s); p.get_immediate_children(s, c); foreach(c[idx]) accept(c[idx],v,p,0); if(invoke_begin_end) v.end_v(); endfunction endclass class uvm_bottom_up_visitor_adapter#(type STRUCTURE=uvm_component,VISITOR=uvm_visitor#(STRUCTURE)) extends uvm_visitor_adapter#(STRUCTURE,VISITOR); function new (string name = ""); super.new(name); endfunction virtual function void accept(STRUCTURE s, VISITOR v,uvm_structure_proxy#(STRUCTURE) p, bit invoke_begin_end=1); STRUCTURE c[$]; if(invoke_begin_end) v.begin_v(); p.get_immediate_children(s, c); foreach(c[idx]) accept(c[idx],v,p,0); v.visit(s); if(invoke_begin_end) v.end_v(); endfunction endclass class uvm_by_level_visitor_adapter#(type STRUCTURE=uvm_component,VISITOR=uvm_visitor#(STRUCTURE)) extends uvm_visitor_adapter#(STRUCTURE,VISITOR); function new (string name = ""); super.new(name); endfunction virtual function void accept(STRUCTURE s, VISITOR v,uvm_structure_proxy#(STRUCTURE) p, bit invoke_begin_end=1); STRUCTURE c[$]; c.push_back(s); if(invoke_begin_end) v.begin_v(); while(c.size() > 0) begin STRUCTURE q[$]; foreach(c[idx]) begin STRUCTURE t[$]; v.visit(c[idx]); p.get_immediate_children(c[idx], t); q = {q,t}; end c=q; end if(invoke_begin_end) v.end_v(); endfunction endclass class uvm_component_proxy extends uvm_structure_proxy#(uvm_component); virtual function void get_immediate_children(STRUCTURE s, ref STRUCTURE children[$]); s.get_children(children); endfunction function new (string name = ""); super.new(name); endfunction endclass class uvm_component_name_check_visitor extends uvm_visitor#(uvm_component); local uvm_root _root; virtual function string get_name_constraint(); return "/^[][[:alnum:](){}_:-]([][[:alnum:](){} _:-]*[][[:alnum:](){}_:-])?$/"; endfunction virtual function void visit(NODE node); if(_root != node) begin if ( ! uvm_is_match( get_name_constraint(), node.get_name() ) ) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/COMP/NAME")) uvm_report_warning ("UVM/COMP/NAME", $sformatf("the name \"%s\" of the component \"%s\" violates the uvm component name constraints",node.get_name(),node.get_full_name()), UVM_NONE, "t/uvm/src/base/uvm_traversal.svh", 274, "", 1); end end end endfunction function new (string name = ""); super.new(name); endfunction virtual function void begin_v(); uvm_coreservice_t cs = uvm_coreservice_t::get(); _root = cs.get_root(); begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"UVM/COMP/NAMECHECK")) uvm_report_info ("UVM/COMP/NAMECHECK", "This implementation of the component name checks requires DPI to be enabled", UVM_NONE, "t/uvm/src/base/uvm_traversal.svh", 289, "", 1); end endfunction endclass `define UVM_DAP_SVH virtual class uvm_set_get_dap_base#(type T=int) extends uvm_object; typedef uvm_set_get_dap_base#(T) this_type; function new(string name="unnamed-uvm_set_get_dap_base#(T)"); super.new(name); endfunction : new pure virtual function void set(T value); pure virtual function bit try_set(T value); pure virtual function T get(); pure virtual function bit try_get(output T value); endclass : uvm_set_get_dap_base class uvm_simple_lock_dap#(type T=int) extends uvm_set_get_dap_base#(T); typedef uvm_simple_lock_dap#(T) this_type; typedef uvm_object_registry #(uvm_simple_lock_dap#(T)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_simple_lock_dap#(T) tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction local T m_value; local bit m_locked; function new(string name="unnamed-uvm_simple_lock_dap#(T)"); super.new(name); m_locked = 0; endfunction : new virtual function void set(T value); if (m_locked) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/SIMPLE_LOCK_DAP/SAG")) uvm_report_error ("UVM/SIMPLE_LOCK_DAP/SAG", $sformatf("Attempt to set new value on '%s', but the data access policy forbids setting while locked!", get_full_name()), UVM_NONE, "t/uvm/src/dap/uvm_simple_lock_dap.svh", 68, "", 1); end else begin m_value = value; end endfunction : set virtual function bit try_set(T value); if (m_locked) return 0; else begin m_value = value; return 1; end endfunction : try_set virtual function T get(); return m_value; endfunction : get virtual function bit try_get(output T value); value = get(); return 1; endfunction : try_get function void lock(); m_locked = 1; endfunction : lock function void unlock(); m_locked = 0; endfunction : unlock function bit is_locked(); return m_locked; endfunction : is_locked virtual function void do_copy(uvm_object rhs); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/SIMPLE_LOCK_DAP/CPY")) uvm_report_error ("UVM/SIMPLE_LOCK_DAP/CPY", "'copy()' is not supported for 'uvm_simple_lock_dap#(T)'", UVM_NONE, "t/uvm/src/dap/uvm_simple_lock_dap.svh", 144, "", 1); end endfunction : do_copy virtual function void do_pack(uvm_packer packer); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/SIMPLE_LOCK_DAP/PCK")) uvm_report_error ("UVM/SIMPLE_LOCK_DAP/PCK", "'pack()' is not supported for 'uvm_simple_lock_dap#(T)'", UVM_NONE, "t/uvm/src/dap/uvm_simple_lock_dap.svh", 149, "", 1); end endfunction : do_pack virtual function void do_unpack(uvm_packer packer); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/SIMPLE_LOCK_DAP/UPK")) uvm_report_error ("UVM/SIMPLE_LOCK_DAP/UPK", "'unpack()' is not supported for 'uvm_simple_lock_dap#(T)'", UVM_NONE, "t/uvm/src/dap/uvm_simple_lock_dap.svh", 154, "", 1); end endfunction : do_unpack virtual function string convert2string(); if (m_locked) return $sformatf("(%s) %0p [LOCKED]", $typename(m_value), m_value); else return $sformatf("(%s) %0p [UNLOCKED]", $typename(m_value), m_value); endfunction : convert2string virtual function void do_print(uvm_printer printer); super.do_print(printer); printer.print_field("lock_state", m_locked, $bits(m_locked)); printer.print_generic("value", $typename(m_value), 0, $sformatf("%0p", m_value)); endfunction : do_print endclass class uvm_get_to_lock_dap#(type T=int) extends uvm_set_get_dap_base#(T); typedef uvm_get_to_lock_dap#(T) this_type; typedef uvm_object_registry #(uvm_get_to_lock_dap#(T)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_get_to_lock_dap#(T) tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction local T m_value; local bit m_locked; function new(string name="unnamed-uvm_get_to_lock_dap#(T)"); super.new(name); m_locked = 0; endfunction : new virtual function void set(T value); if (m_locked) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/GET_TO_LOCK_DAP/SAG")) uvm_report_error ("UVM/GET_TO_LOCK_DAP/SAG", $sformatf("Attempt to set new value on '%s', but the data access policy forbids setting after a get!", get_full_name()), UVM_NONE, "t/uvm/src/dap/uvm_get_to_lock_dap.svh", 67, "", 1); end else begin m_value = value; end endfunction : set virtual function bit try_set(T value); if (m_locked) return 0; else begin m_value = value; return 1; end endfunction : try_set virtual function T get(); m_locked = 1; return m_value; endfunction : get virtual function bit try_get(output T value); value = get(); return 1; endfunction : try_get virtual function void do_copy(uvm_object rhs); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/GET_TO_LOCK_DAP/CPY")) uvm_report_error ("UVM/GET_TO_LOCK_DAP/CPY", "'copy()' is not supported for 'uvm_get_to_lock_dap#(T)'", UVM_NONE, "t/uvm/src/dap/uvm_get_to_lock_dap.svh", 119, "", 1); end endfunction : do_copy virtual function void do_pack(uvm_packer packer); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/GET_TO_LOCK_DAP/PCK")) uvm_report_error ("UVM/GET_TO_LOCK_DAP/PCK", "'pack()' is not supported for 'uvm_get_to_lock_dap#(T)'", UVM_NONE, "t/uvm/src/dap/uvm_get_to_lock_dap.svh", 124, "", 1); end endfunction : do_pack virtual function void do_unpack(uvm_packer packer); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/GET_TO_LOCK_DAP/UPK")) uvm_report_error ("UVM/GET_TO_LOCK_DAP/UPK", "'unpack()' is not supported for 'uvm_get_to_lock_dap#(T)'", UVM_NONE, "t/uvm/src/dap/uvm_get_to_lock_dap.svh", 129, "", 1); end endfunction : do_unpack virtual function string convert2string(); if (m_locked) return $sformatf("(%s) %0p [LOCKED]", $typename(m_value), m_value); else return $sformatf("(%s) %0p [UNLOCKED]", $typename(m_value), m_value); endfunction : convert2string virtual function void do_print(uvm_printer printer); super.do_print(printer); printer.print_field_int("lock_state", m_locked, $bits(m_locked)); printer.print_generic("value", $typename(m_value), 0, $sformatf("%0p", m_value)); endfunction : do_print endclass class uvm_set_before_get_dap#(type T=int) extends uvm_set_get_dap_base#(T); typedef uvm_set_before_get_dap#(T) this_type; typedef uvm_object_registry #(uvm_set_before_get_dap#(T)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_set_before_get_dap#(T) tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction local T m_value; local bit m_set; function new(string name="unnamed-uvm_set_before_get_dap#(T)"); super.new(name); m_set = 0; endfunction : new virtual function void set(T value); m_set = 1; m_value = value; endfunction : set virtual function bit try_set(T value); set(value); return 1; endfunction : try_set virtual function T get(); if (!m_set) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/SET_BEFORE_GET_DAP/NO_SET")) uvm_report_error ("UVM/SET_BEFORE_GET_DAP/NO_SET", $sformatf("Attempt to get value on '%s', but the data access policy forbits calling 'get' prior to calling 'set' or 'try_set'!", get_full_name()), UVM_NONE, "t/uvm/src/dap/uvm_set_before_get_dap.svh", 117, "", 1); end end return m_value; endfunction : get virtual function bit try_get(output T value); if (!m_set) begin return 0; end else begin value = m_value; return 1; end endfunction : try_get virtual function void do_copy(uvm_object rhs); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/SET_BEFORE_GET_DAP/CPY")) uvm_report_error ("UVM/SET_BEFORE_GET_DAP/CPY", "'copy()' is not supported for 'uvm_set_before_get_dap#(T)'", UVM_NONE, "t/uvm/src/dap/uvm_set_before_get_dap.svh", 149, "", 1); end endfunction : do_copy virtual function void do_pack(uvm_packer packer); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/SET_BEFORE_GET_DAP/PCK")) uvm_report_error ("UVM/SET_BEFORE_GET_DAP/PCK", "'pack()' is not supported for 'uvm_set_before_get_dap#(T)'", UVM_NONE, "t/uvm/src/dap/uvm_set_before_get_dap.svh", 154, "", 1); end endfunction : do_pack virtual function void do_unpack(uvm_packer packer); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/SET_BEFORE_GET_DAP/UPK")) uvm_report_error ("UVM/SET_BEFORE_GET_DAP/UPK", "'unpack()' is not supported for 'uvm_set_before_get_dap#(T)'", UVM_NONE, "t/uvm/src/dap/uvm_set_before_get_dap.svh", 159, "", 1); end endfunction : do_unpack virtual function string convert2string(); if (m_set) return $sformatf("(%s) %0p [SET]", $typename(m_value), m_value); else return $sformatf("(%s) %0p [UNSET]", $typename(m_value), m_value); endfunction : convert2string virtual function void do_print(uvm_printer printer); super.do_print(printer); printer.print_field_int("set_state", m_set, $bits(m_set)); printer.print_generic("value", $typename(m_value), 0, $sformatf("%0p", m_value)); endfunction : do_print endclass `define UVM_TASK_ERROR "UVM TLM interface task not implemented" `define UVM_FUNCTION_ERROR "UVM TLM interface function not implemented" virtual class uvm_tlm_if_base #(type T1=int, type T2=int); virtual task put( input T1 t ); uvm_report_error("put", "UVM TLM interface task not implemented", UVM_NONE); endtask virtual task get( output T2 t ); uvm_report_error("get", "UVM TLM interface task not implemented", UVM_NONE); endtask virtual task peek( output T2 t ); uvm_report_error("peek", "UVM TLM interface task not implemented", UVM_NONE); endtask virtual function bit try_put( input T1 t ); uvm_report_error("try_put", "UVM TLM interface function not implemented", UVM_NONE); return 0; endfunction virtual function bit can_put(); uvm_report_error("can_put", "UVM TLM interface function not implemented", UVM_NONE); return 0; endfunction virtual function bit try_get( output T2 t ); uvm_report_error("try_get", "UVM TLM interface function not implemented", UVM_NONE); return 0; endfunction virtual function bit can_get(); uvm_report_error("can_get", "UVM TLM interface function not implemented", UVM_NONE); return 0; endfunction virtual function bit try_peek( output T2 t ); uvm_report_error("try_peek", "UVM TLM interface function not implemented", UVM_NONE); return 0; endfunction virtual function bit can_peek(); uvm_report_error("can_ppeek", "UVM TLM interface function not implemented", UVM_NONE); return 0; endfunction virtual task transport( input T1 req , output T2 rsp ); uvm_report_error("transport", "UVM TLM interface task not implemented", UVM_NONE); endtask virtual function bit nb_transport(input T1 req, output T2 rsp); uvm_report_error("nb_transport", "UVM TLM interface function not implemented", UVM_NONE); return 0; endfunction virtual function void write( input T1 t ); uvm_report_error("write", "UVM TLM interface function not implemented", UVM_NONE); endfunction endclass `define UVM_SEQ_ITEM_TASK_ERROR "Sequencer interface task not implemented" `define UVM_SEQ_ITEM_FUNCTION_ERROR "Sequencer interface function not implemented" virtual class uvm_sqr_if_base #(type T1=uvm_object, T2=T1); virtual task get_next_item(output T1 t); uvm_report_error("get_next_item", "Sequencer interface task not implemented", UVM_NONE); endtask virtual task try_next_item(output T1 t); uvm_report_error("try_next_item", "Sequencer interface task not implemented", UVM_NONE); endtask virtual function void item_done(input T2 t = null); uvm_report_error("item_done", "Sequencer interface function not implemented", UVM_NONE); endfunction virtual task wait_for_sequences(); uvm_report_error("wait_for_sequences", "Sequencer interface task not implemented", UVM_NONE); endtask virtual function bit has_do_available(); uvm_report_error("has_do_available", "Sequencer interface function not implemented", UVM_NONE); return 0; endfunction virtual task get(output T1 t); uvm_report_error("get", "Sequencer interface task not implemented", UVM_NONE); endtask virtual task peek(output T1 t); uvm_report_error("peek", "Sequencer interface task not implemented", UVM_NONE); endtask virtual task put(input T2 t); uvm_report_error("put", "Sequencer interface task not implemented", UVM_NONE); endtask virtual function void put_response(input T2 t); uvm_report_error("put_response", "Sequencer interface function not implemented", UVM_NONE); endfunction virtual function void disable_auto_item_recording(); uvm_report_error("disable_auto_item_recording", "Sequencer interface function not implemented", UVM_NONE); endfunction virtual function bit is_auto_item_recording_enabled(); uvm_report_error("is_auto_item_recording_enabled", "Sequencer interface function not implemented", UVM_NONE); return 0; endfunction endclass const int UVM_UNBOUNDED_CONNECTIONS = -1; const string s_connection_error_id = "Connection Error"; const string s_connection_warning_id = "Connection Warning"; const string s_spaces = " "; typedef class uvm_port_component_base; typedef uvm_port_component_base uvm_port_list[string]; virtual class uvm_port_component_base extends uvm_component; function new (string name, uvm_component parent); super.new(name,parent); endfunction pure virtual function void get_connected_to(ref uvm_port_list list); pure virtual function bit is_port(); pure virtual function bit is_export(); pure virtual function bit is_imp(); virtual function bit use_automatic_config(); return 0; endfunction : use_automatic_config virtual task do_task_phase (uvm_phase phase); endtask endclass class uvm_port_component #(type PORT=uvm_object) extends uvm_port_component_base; PORT m_port; function new (string name, uvm_component parent, PORT port); super.new(name,parent); if (port == null) uvm_report_fatal("Bad usage", "Null handle to port", UVM_NONE); m_port = port; endfunction virtual function string get_type_name(); if(m_port == null) return "uvm_port_component"; return m_port.get_type_name(); endfunction virtual function void resolve_bindings(); m_port.resolve_bindings(); endfunction function PORT get_port(); return m_port; endfunction virtual function void get_connected_to(ref uvm_port_list list); PORT list1[string]; m_port.get_connected_to(list1); list.delete(); foreach(list1[name]) begin list[name] = list1[name].get_comp(); end endfunction function bit is_port (); return m_port.is_port(); endfunction function bit is_export (); return m_port.is_export(); endfunction function bit is_imp (); return m_port.is_imp(); endfunction endclass virtual class uvm_port_base #(type IF=uvm_void) extends IF; typedef uvm_port_base #(IF) this_type; protected int unsigned m_if_mask; protected this_type m_if; protected int unsigned m_def_index; uvm_port_component #(this_type) m_comp; local this_type m_provided_by[string]; local this_type m_provided_to[string]; local uvm_port_type_e m_port_type; local int m_min_size; local int m_max_size; local bit m_resolved; local this_type m_imp_list[string]; function new (string name, uvm_component parent, uvm_port_type_e port_type, int min_size=0, int max_size=1); uvm_component comp; int tmp; m_port_type = port_type; m_min_size = min_size; m_max_size = max_size; m_comp = new(name, parent, this); if (!uvm_config_int::get(m_comp, "", "check_connection_relationships",tmp)) m_comp.set_report_id_action(s_connection_warning_id, UVM_NO_ACTION); endfunction function string get_name(); return m_comp.get_name(); endfunction virtual function string get_full_name(); return m_comp.get_full_name(); endfunction virtual function uvm_component get_parent(); return m_comp.get_parent(); endfunction virtual function uvm_port_component_base get_comp(); return m_comp; endfunction virtual function string get_type_name(); case( m_port_type ) UVM_PORT : return "port"; UVM_EXPORT : return "export"; UVM_IMPLEMENTATION : return "implementation"; endcase endfunction function int max_size (); return m_max_size; endfunction function int min_size (); return m_min_size; endfunction function bit is_unbounded (); return (m_max_size == UVM_UNBOUNDED_CONNECTIONS); endfunction function bit is_port (); return m_port_type == UVM_PORT; endfunction function bit is_export (); return m_port_type == UVM_EXPORT; endfunction function bit is_imp (); return m_port_type == UVM_IMPLEMENTATION; endfunction function int size (); return m_imp_list.num(); endfunction function void set_if (int index=0); m_if = get_if(index); if (m_if != null) m_def_index = index; endfunction function int m_get_if_mask(); return m_if_mask; endfunction function void set_default_index (int index); m_def_index = index; endfunction virtual function void connect (this_type provider); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); if (end_of_elaboration_ph.get_state() == UVM_PHASE_EXECUTING || end_of_elaboration_ph.get_state() == UVM_PHASE_DONE ) begin m_comp.uvm_report_warning("Late Connection", {"Attempt to connect ",this.get_full_name()," (of type ",this.get_type_name(), ") at or after end_of_elaboration phase. Ignoring."}); return; end if (provider == null) begin m_comp.uvm_report_error(s_connection_error_id, "Cannot connect to null port handle", UVM_NONE); return; end if (provider == this) begin m_comp.uvm_report_error(s_connection_error_id, "Cannot connect a port instance to itself", UVM_NONE); return; end if ((provider.m_if_mask & m_if_mask) != m_if_mask) begin m_comp.uvm_report_error(s_connection_error_id, {provider.get_full_name(), " (of type ",provider.get_type_name(), ") does not provide the complete interface required of this port (type ", get_type_name(),")"}, UVM_NONE); return; end if (is_imp()) begin m_comp.uvm_report_error(s_connection_error_id, $sformatf( "Cannot call an imp port's connect method. An imp is connected only to the component passed in its constructor. (You attempted to bind this imp to %s)", provider.get_full_name()), UVM_NONE); return; end if (is_export() && provider.is_port()) begin m_comp.uvm_report_error(s_connection_error_id, $sformatf( "Cannot connect exports to ports Try calling port.connect(export) instead. (You attempted to bind this export to %s).", provider.get_full_name()), UVM_NONE); return; end void'(m_check_relationship(provider)); m_provided_by[provider.get_full_name()] = provider; provider.m_provided_to[get_full_name()] = this; endfunction function void debug_connected_to (int level=0, int max_level=-1); int sz, num, curr_num; string s_sz; static string indent, save; this_type port; if (level < 0) level = 0; if (level == 0) begin save = ""; indent=" "; end if (max_level != -1 && level >= max_level) return; num = m_provided_by.num(); if (m_provided_by.num() != 0) begin foreach (m_provided_by[nm]) begin curr_num++; port = m_provided_by[nm]; save = {save, indent, " | \n"}; save = {save, indent, " |_",nm," (",port.get_type_name(),")\n"}; indent = (num > 1 && curr_num != num) ? {indent," | "}:{indent, " "}; port.debug_connected_to(level+1, max_level); indent = indent.substr(0,indent.len()-4-1); end end if (level == 0) begin if (save != "") save = {"This port's fanout network:\n\n ", get_full_name()," (",get_type_name(),")\n",save,"\n"}; if (m_imp_list.num() == 0) begin uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); if (end_of_elaboration_ph.get_state() == UVM_PHASE_EXECUTING || end_of_elaboration_ph.get_state() == UVM_PHASE_DONE ) save = {save," Connected implementations: none\n"}; else save = {save, " Connected implementations: not resolved until end-of-elab\n"}; end else begin save = {save," Resolved implementation list:\n"}; foreach (m_imp_list[nm]) begin port = m_imp_list[nm]; s_sz.itoa(sz); save = {save, indent, s_sz, ": ",nm," (",port.get_type_name(),")\n"}; sz++; end end m_comp.uvm_report_info("debug_connected_to", save); end endfunction function void debug_provided_to (int level=0, int max_level=-1); string nm; int num,curr_num; this_type port; static string indent, save; if (level < 0) level = 0; if (level == 0) begin save = ""; indent = " "; end if (max_level != -1 && level > max_level) return; num = m_provided_to.num(); if (num != 0) begin foreach (m_provided_to[nm]) begin curr_num++; port = m_provided_to[nm]; save = {save, indent, " | \n"}; save = {save, indent, " |_",nm," (",port.get_type_name(),")\n"}; indent = (num > 1 && curr_num != num) ? {indent," | "}:{indent, " "}; port.debug_provided_to(level+1, max_level); indent = indent.substr(0,indent.len()-4-1); end end if (level == 0) begin if (save != "") save = {"This port's fanin network:\n\n ", get_full_name()," (",get_type_name(),")\n",save,"\n"}; if (m_provided_to.num() == 0) save = {save,indent,"This port has not been bound\n"}; m_comp.uvm_report_info("debug_provided_to", save); end endfunction function void get_connected_to (ref uvm_port_base #(IF) list[string]); this_type port; list.delete(); foreach (m_provided_by[name]) begin port = m_provided_by[name]; list[name] = port; end endfunction function void get_provided_to (ref uvm_port_base #(IF) list[string]); this_type port; list.delete(); foreach (m_provided_to[name]) begin port = m_provided_to[name]; list[name] = port; end endfunction local function bit m_check_relationship (this_type provider); string s; this_type from; uvm_component from_parent; uvm_component to_parent; uvm_component from_gparent; uvm_component to_gparent; if (get_type_name() == "uvm_analysis_port") return 1; from = this; from_parent = get_parent(); to_parent = provider.get_parent(); if (from_parent == null || to_parent == null) return 1; from_gparent = from_parent.get_parent(); to_gparent = to_parent.get_parent(); if (from.is_port() && provider.is_port() && from_gparent != to_parent) begin s = {provider.get_full_name(), " (of type ",provider.get_type_name(), ") is not up one level of hierarchy from this port. ", "A port-to-port connection takes the form ", "child_component.child_port.connect(parent_port)"}; m_comp.uvm_report_warning(s_connection_warning_id, s, UVM_NONE); return 0; end else if (from.is_port() && (provider.is_export() || provider.is_imp()) && from_gparent != to_gparent) begin s = {provider.get_full_name(), " (of type ",provider.get_type_name(), ") is not at the same level of hierarchy as this port. ", "A port-to-export connection takes the form ", "component1.port.connect(component2.export)"}; m_comp.uvm_report_warning(s_connection_warning_id, s, UVM_NONE); return 0; end else if (from.is_export() && (provider.is_export() || provider.is_imp()) && from_parent != to_gparent) begin s = {provider.get_full_name(), " (of type ",provider.get_type_name(), ") is not down one level of hierarchy from this export. ", "An export-to-export or export-to-imp connection takes the form ", "parent_export.connect(child_component.child_export)"}; m_comp.uvm_report_warning(s_connection_warning_id, s, UVM_NONE); return 0; end return 1; endfunction local function void m_add_list (this_type provider); string sz; this_type imp; for (int i = 0; i < provider.size(); i++) begin imp = provider.get_if(i); if (!m_imp_list.exists(imp.get_full_name())) m_imp_list[imp.get_full_name()] = imp; end endfunction virtual function void resolve_bindings(); if (m_resolved) return; if (is_imp()) begin m_imp_list[get_full_name()] = this; end else begin foreach (m_provided_by[nm]) begin this_type port; port = m_provided_by[nm]; port.resolve_bindings(); m_add_list(port); end end m_resolved = 1; if (size() < min_size() ) begin m_comp.uvm_report_error(s_connection_error_id, $sformatf("connection count of %0d does not meet required minimum of %0d", size(), min_size()), UVM_NONE); end if (max_size() != UVM_UNBOUNDED_CONNECTIONS && size() > max_size() ) begin m_comp.uvm_report_error(s_connection_error_id, $sformatf("connection count of %0d exceeds maximum of %0d", size(), max_size()), UVM_NONE); end if (size()) set_if(0); endfunction function uvm_port_base #(IF) get_if(int index=0); string s; if (size()==0) begin m_comp.uvm_report_warning("get_if", "Port size is zero; cannot get interface at any index", UVM_NONE); return null; end if (index < 0 || index >= size()) begin $sformat(s, "Index %0d out of range [0,%0d]", index, size()-1); m_comp.uvm_report_warning(s_connection_error_id, s, UVM_NONE); return null; end foreach (m_imp_list[nm]) begin if (index == 0) return m_imp_list[nm]; index--; end endfunction endclass class uvm_blocking_put_imp #(type T=int, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = (1<<0); endfunction virtual function string get_type_name(); return "uvm_blocking_put_imp"; endfunction task put (T t); m_imp.put(t); endtask endclass class uvm_nonblocking_put_imp #(type T=int, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = (1<<4); endfunction virtual function string get_type_name(); return "uvm_nonblocking_put_imp"; endfunction function bit try_put (T t); return m_imp.try_put(t); endfunction function bit can_put(); return m_imp.can_put(); endfunction endclass class uvm_put_imp #(type T=int, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = ((1<<0) | (1<<4)); endfunction virtual function string get_type_name(); return "uvm_put_imp"; endfunction task put (T t); m_imp.put(t); endtask function bit try_put (T t); return m_imp.try_put(t); endfunction function bit can_put(); return m_imp.can_put(); endfunction endclass class uvm_blocking_get_imp #(type T=int, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = (1<<1); endfunction virtual function string get_type_name(); return "uvm_blocking_get_imp"; endfunction task get (output T t); m_imp.get(t); endtask endclass class uvm_nonblocking_get_imp #(type T=int, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = (1<<5); endfunction virtual function string get_type_name(); return "uvm_nonblocking_get_imp"; endfunction function bit try_get (output T t); return m_imp.try_get(t); endfunction function bit can_get(); return m_imp.can_get(); endfunction endclass class uvm_get_imp #(type T=int, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = ((1<<1) | (1<<5)); endfunction virtual function string get_type_name(); return "uvm_get_imp"; endfunction task get (output T t); m_imp.get(t); endtask function bit try_get (output T t); return m_imp.try_get(t); endfunction function bit can_get(); return m_imp.can_get(); endfunction endclass class uvm_blocking_peek_imp #(type T=int, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = (1<<2); endfunction virtual function string get_type_name(); return "uvm_blocking_peek_imp"; endfunction task peek (output T t); m_imp.peek(t); endtask endclass class uvm_nonblocking_peek_imp #(type T=int, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = (1<<6); endfunction virtual function string get_type_name(); return "uvm_nonblocking_peek_imp"; endfunction function bit try_peek (output T t); return m_imp.try_peek(t); endfunction function bit can_peek(); return m_imp.can_peek(); endfunction endclass class uvm_peek_imp #(type T=int, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = ((1<<2) | (1<<6)); endfunction virtual function string get_type_name(); return "uvm_peek_imp"; endfunction task peek (output T t); m_imp.peek(t); endtask function bit try_peek (output T t); return m_imp.try_peek(t); endfunction function bit can_peek(); return m_imp.can_peek(); endfunction endclass class uvm_blocking_get_peek_imp #(type T=int, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = ((1<<1) | (1<<2)); endfunction virtual function string get_type_name(); return "uvm_blocking_get_peek_imp"; endfunction task get (output T t); m_imp.get(t); endtask task peek (output T t); m_imp.peek(t); endtask endclass class uvm_nonblocking_get_peek_imp #(type T=int, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = ((1<<5) | (1<<6)); endfunction virtual function string get_type_name(); return "uvm_nonblocking_get_peek_imp"; endfunction function bit try_get (output T t); return m_imp.try_get(t); endfunction function bit can_get(); return m_imp.can_get(); endfunction function bit try_peek (output T t); return m_imp.try_peek(t); endfunction function bit can_peek(); return m_imp.can_peek(); endfunction endclass class uvm_get_peek_imp #(type T=int, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = (((1<<1) | (1<<5)) | ((1<<2) | (1<<6))); endfunction virtual function string get_type_name(); return "uvm_get_peek_imp"; endfunction task get (output T t); m_imp.get(t); endtask task peek (output T t); m_imp.peek(t); endtask function bit try_get (output T t); return m_imp.try_get(t); endfunction function bit can_get(); return m_imp.can_get(); endfunction function bit try_peek (output T t); return m_imp.try_peek(t); endfunction function bit can_peek(); return m_imp.can_peek(); endfunction endclass class uvm_blocking_master_imp #(type REQ=int, type RSP=REQ, type IMP=int, type REQ_IMP=IMP, type RSP_IMP=IMP) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); typedef IMP this_imp_type; typedef REQ_IMP this_req_type; typedef RSP_IMP this_rsp_type; local this_req_type m_req_imp; local this_rsp_type m_rsp_imp; function new (string name, this_imp_type imp, this_req_type req_imp = null, this_rsp_type rsp_imp = null); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); if(req_imp==null) $cast(req_imp, imp); if(rsp_imp==null) $cast(rsp_imp, imp); m_req_imp = req_imp; m_rsp_imp = rsp_imp; m_if_mask = ((1<<0) | (1<<1) | (1<<2) | (1<<9)); endfunction virtual function string get_type_name(); return "uvm_blocking_master_imp"; endfunction task put (REQ t); m_req_imp.put(t); endtask task get (output RSP t); m_rsp_imp.get(t); endtask task peek (output RSP t); m_rsp_imp.peek(t); endtask endclass class uvm_nonblocking_master_imp #(type REQ=int, type RSP=REQ, type IMP=int, type REQ_IMP=IMP, type RSP_IMP=IMP) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); typedef IMP this_imp_type; typedef REQ_IMP this_req_type; typedef RSP_IMP this_rsp_type; local this_req_type m_req_imp; local this_rsp_type m_rsp_imp; function new (string name, this_imp_type imp, this_req_type req_imp = null, this_rsp_type rsp_imp = null); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); if(req_imp==null) $cast(req_imp, imp); if(rsp_imp==null) $cast(rsp_imp, imp); m_req_imp = req_imp; m_rsp_imp = rsp_imp; m_if_mask = ((1<<4) | (1<<5) | (1<<6) | (1<<9)); endfunction virtual function string get_type_name(); return "uvm_nonblocking_master_imp"; endfunction function bit try_put (REQ t); return m_req_imp.try_put(t); endfunction function bit can_put(); return m_req_imp.can_put(); endfunction function bit try_get (output RSP t); return m_rsp_imp.try_get(t); endfunction function bit can_get(); return m_rsp_imp.can_get(); endfunction function bit try_peek (output RSP t); return m_rsp_imp.try_peek(t); endfunction function bit can_peek(); return m_rsp_imp.can_peek(); endfunction endclass class uvm_master_imp #(type REQ=int, type RSP=REQ, type IMP=int, type REQ_IMP=IMP, type RSP_IMP=IMP) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); typedef IMP this_imp_type; typedef REQ_IMP this_req_type; typedef RSP_IMP this_rsp_type; local this_req_type m_req_imp; local this_rsp_type m_rsp_imp; function new (string name, this_imp_type imp, this_req_type req_imp = null, this_rsp_type rsp_imp = null); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); if(req_imp==null) $cast(req_imp, imp); if(rsp_imp==null) $cast(rsp_imp, imp); m_req_imp = req_imp; m_rsp_imp = rsp_imp; m_if_mask = (((1<<0) | (1<<1) | (1<<2) | (1<<9)) | ((1<<4) | (1<<5) | (1<<6) | (1<<9))); endfunction virtual function string get_type_name(); return "uvm_master_imp"; endfunction task put (REQ t); m_req_imp.put(t); endtask function bit try_put (REQ t); return m_req_imp.try_put(t); endfunction function bit can_put(); return m_req_imp.can_put(); endfunction task get (output RSP t); m_rsp_imp.get(t); endtask task peek (output RSP t); m_rsp_imp.peek(t); endtask function bit try_get (output RSP t); return m_rsp_imp.try_get(t); endfunction function bit can_get(); return m_rsp_imp.can_get(); endfunction function bit try_peek (output RSP t); return m_rsp_imp.try_peek(t); endfunction function bit can_peek(); return m_rsp_imp.can_peek(); endfunction endclass class uvm_blocking_slave_imp #(type REQ=int, type RSP=REQ, type IMP=int, type REQ_IMP=IMP, type RSP_IMP=IMP) extends uvm_port_base #(uvm_tlm_if_base #(RSP, REQ)); typedef IMP this_imp_type; typedef REQ_IMP this_req_type; typedef RSP_IMP this_rsp_type; local this_req_type m_req_imp; local this_rsp_type m_rsp_imp; function new (string name, this_imp_type imp, this_req_type req_imp = null, this_rsp_type rsp_imp = null); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); if(req_imp==null) $cast(req_imp, imp); if(rsp_imp==null) $cast(rsp_imp, imp); m_req_imp = req_imp; m_rsp_imp = rsp_imp; m_if_mask = ((1<<0) | (1<<1) | (1<<2) | (1<<10)); endfunction virtual function string get_type_name(); return "uvm_blocking_slave_imp"; endfunction task put (RSP t); m_rsp_imp.put(t); endtask task get (output REQ t); m_req_imp.get(t); endtask task peek (output REQ t); m_req_imp.peek(t); endtask endclass class uvm_nonblocking_slave_imp #(type REQ=int, type RSP=REQ, type IMP=int, type REQ_IMP=IMP, type RSP_IMP=IMP) extends uvm_port_base #(uvm_tlm_if_base #(RSP, REQ)); typedef IMP this_imp_type; typedef REQ_IMP this_req_type; typedef RSP_IMP this_rsp_type; local this_req_type m_req_imp; local this_rsp_type m_rsp_imp; function new (string name, this_imp_type imp, this_req_type req_imp = null, this_rsp_type rsp_imp = null); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); if(req_imp==null) $cast(req_imp, imp); if(rsp_imp==null) $cast(rsp_imp, imp); m_req_imp = req_imp; m_rsp_imp = rsp_imp; m_if_mask = ((1<<4) | (1<<5) | (1<<6) | (1<<10)); endfunction virtual function string get_type_name(); return "uvm_nonblocking_slave_imp"; endfunction function bit try_put (RSP t); return m_rsp_imp.try_put(t); endfunction function bit can_put(); return m_rsp_imp.can_put(); endfunction function bit try_get (output REQ t); return m_req_imp.try_get(t); endfunction function bit can_get(); return m_req_imp.can_get(); endfunction function bit try_peek (output REQ t); return m_req_imp.try_peek(t); endfunction function bit can_peek(); return m_req_imp.can_peek(); endfunction endclass class uvm_slave_imp #(type REQ=int, type RSP=REQ, type IMP=int, type REQ_IMP=IMP, type RSP_IMP=IMP) extends uvm_port_base #(uvm_tlm_if_base #(RSP, REQ)); typedef IMP this_imp_type; typedef REQ_IMP this_req_type; typedef RSP_IMP this_rsp_type; local this_req_type m_req_imp; local this_rsp_type m_rsp_imp; function new (string name, this_imp_type imp, this_req_type req_imp = null, this_rsp_type rsp_imp = null); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); if(req_imp==null) $cast(req_imp, imp); if(rsp_imp==null) $cast(rsp_imp, imp); m_req_imp = req_imp; m_rsp_imp = rsp_imp; m_if_mask = (((1<<0) | (1<<1) | (1<<2) | (1<<10)) | ((1<<4) | (1<<5) | (1<<6) | (1<<10))); endfunction virtual function string get_type_name(); return "uvm_slave_imp"; endfunction task put (RSP t); m_rsp_imp.put(t); endtask function bit try_put (RSP t); return m_rsp_imp.try_put(t); endfunction function bit can_put(); return m_rsp_imp.can_put(); endfunction task get (output REQ t); m_req_imp.get(t); endtask task peek (output REQ t); m_req_imp.peek(t); endtask function bit try_get (output REQ t); return m_req_imp.try_get(t); endfunction function bit can_get(); return m_req_imp.can_get(); endfunction function bit try_peek (output REQ t); return m_req_imp.try_peek(t); endfunction function bit can_peek(); return m_req_imp.can_peek(); endfunction endclass class uvm_blocking_transport_imp #(type REQ=int, type RSP=REQ, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = (1<<3); endfunction virtual function string get_type_name(); return "uvm_blocking_transport_imp"; endfunction task transport (REQ req, output RSP rsp); m_imp.transport(req, rsp); endtask endclass class uvm_nonblocking_transport_imp #(type REQ=int, type RSP=REQ, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = (1<<7); endfunction virtual function string get_type_name(); return "uvm_nonblocking_transport_imp"; endfunction function bit nb_transport (REQ req, output RSP rsp); return m_imp.nb_transport(req, rsp); endfunction endclass class uvm_transport_imp #(type REQ=int, type RSP=REQ, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = ((1<<3) | (1<<7)); endfunction virtual function string get_type_name(); return "uvm_transport_imp"; endfunction task transport (REQ req, output RSP rsp); m_imp.transport(req, rsp); endtask function bit nb_transport (REQ req, output RSP rsp); return m_imp.nb_transport(req, rsp); endfunction endclass class uvm_blocking_put_port #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (1<<0); endfunction virtual function string get_type_name(); return "uvm_blocking_put_port"; endfunction task put (T t); this.m_if.put(t); endtask endclass class uvm_nonblocking_put_port #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (1<<4); endfunction virtual function string get_type_name(); return "uvm_nonblocking_put_port"; endfunction function bit try_put (T t); return this.m_if.try_put(t); endfunction function bit can_put(); return this.m_if.can_put(); endfunction endclass class uvm_put_port #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = ((1<<0) | (1<<4)); endfunction virtual function string get_type_name(); return "uvm_put_port"; endfunction task put (T t); this.m_if.put(t); endtask function bit try_put (T t); return this.m_if.try_put(t); endfunction function bit can_put(); return this.m_if.can_put(); endfunction endclass class uvm_blocking_get_port #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (1<<1); endfunction virtual function string get_type_name(); return "uvm_blocking_get_port"; endfunction task get (output T t); this.m_if.get(t); endtask endclass class uvm_nonblocking_get_port #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (1<<5); endfunction virtual function string get_type_name(); return "uvm_nonblocking_get_port"; endfunction function bit try_get (output T t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction endclass class uvm_get_port #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = ((1<<1) | (1<<5)); endfunction virtual function string get_type_name(); return "uvm_get_port"; endfunction task get (output T t); this.m_if.get(t); endtask function bit try_get (output T t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction endclass class uvm_blocking_peek_port #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (1<<2); endfunction virtual function string get_type_name(); return "uvm_blocking_peek_port"; endfunction task peek (output T t); this.m_if.peek(t); endtask endclass class uvm_nonblocking_peek_port #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (1<<6); endfunction virtual function string get_type_name(); return "uvm_nonblocking_peek_port"; endfunction function bit try_peek (output T t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_peek_port #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = ((1<<2) | (1<<6)); endfunction virtual function string get_type_name(); return "uvm_peek_port"; endfunction task peek (output T t); this.m_if.peek(t); endtask function bit try_peek (output T t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_blocking_get_peek_port #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = ((1<<1) | (1<<2)); endfunction virtual function string get_type_name(); return "uvm_blocking_get_peek_port"; endfunction task get (output T t); this.m_if.get(t); endtask task peek (output T t); this.m_if.peek(t); endtask endclass class uvm_nonblocking_get_peek_port #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = ((1<<5) | (1<<6)); endfunction virtual function string get_type_name(); return "uvm_nonblocking_get_peek_port"; endfunction function bit try_get (output T t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction function bit try_peek (output T t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_get_peek_port #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (((1<<1) | (1<<5)) | ((1<<2) | (1<<6))); endfunction virtual function string get_type_name(); return "uvm_get_peek_port"; endfunction task get (output T t); this.m_if.get(t); endtask task peek (output T t); this.m_if.peek(t); endtask function bit try_get (output T t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction function bit try_peek (output T t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_blocking_master_port #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = ((1<<0) | (1<<1) | (1<<2) | (1<<9)); endfunction virtual function string get_type_name(); return "uvm_blocking_master_port"; endfunction task put (REQ t); this.m_if.put(t); endtask task get (output RSP t); this.m_if.get(t); endtask task peek (output RSP t); this.m_if.peek(t); endtask endclass class uvm_nonblocking_master_port #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = ((1<<4) | (1<<5) | (1<<6) | (1<<9)); endfunction virtual function string get_type_name(); return "uvm_nonblocking_master_port"; endfunction function bit try_put (REQ t); return this.m_if.try_put(t); endfunction function bit can_put(); return this.m_if.can_put(); endfunction function bit try_get (output RSP t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction function bit try_peek (output RSP t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_master_port #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (((1<<0) | (1<<1) | (1<<2) | (1<<9)) | ((1<<4) | (1<<5) | (1<<6) | (1<<9))); endfunction virtual function string get_type_name(); return "uvm_master_port"; endfunction task put (REQ t); this.m_if.put(t); endtask function bit try_put (REQ t); return this.m_if.try_put(t); endfunction function bit can_put(); return this.m_if.can_put(); endfunction task get (output RSP t); this.m_if.get(t); endtask task peek (output RSP t); this.m_if.peek(t); endtask function bit try_get (output RSP t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction function bit try_peek (output RSP t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_blocking_slave_port #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(RSP, REQ)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = ((1<<0) | (1<<1) | (1<<2) | (1<<10)); endfunction virtual function string get_type_name(); return "uvm_blocking_slave_port"; endfunction task put (RSP t); this.m_if.put(t); endtask task get (output REQ t); this.m_if.get(t); endtask task peek (output REQ t); this.m_if.peek(t); endtask endclass class uvm_nonblocking_slave_port #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(RSP, REQ)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = ((1<<4) | (1<<5) | (1<<6) | (1<<10)); endfunction virtual function string get_type_name(); return "uvm_nonblocking_slave_port"; endfunction function bit try_put (RSP t); return this.m_if.try_put(t); endfunction function bit can_put(); return this.m_if.can_put(); endfunction function bit try_get (output REQ t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction function bit try_peek (output REQ t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_slave_port #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(RSP, REQ)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (((1<<0) | (1<<1) | (1<<2) | (1<<10)) | ((1<<4) | (1<<5) | (1<<6) | (1<<10))); endfunction virtual function string get_type_name(); return "uvm_slave_port"; endfunction task put (RSP t); this.m_if.put(t); endtask function bit try_put (RSP t); return this.m_if.try_put(t); endfunction function bit can_put(); return this.m_if.can_put(); endfunction task get (output REQ t); this.m_if.get(t); endtask task peek (output REQ t); this.m_if.peek(t); endtask function bit try_get (output REQ t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction function bit try_peek (output REQ t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_blocking_transport_port #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (1<<3); endfunction virtual function string get_type_name(); return "uvm_blocking_transport_port"; endfunction task transport (REQ req, output RSP rsp); this.m_if.transport(req, rsp); endtask endclass class uvm_nonblocking_transport_port #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (1<<7); endfunction virtual function string get_type_name(); return "uvm_nonblocking_transport_port"; endfunction function bit nb_transport (REQ req, output RSP rsp); return this.m_if.nb_transport(req, rsp); endfunction endclass class uvm_transport_port #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = ((1<<3) | (1<<7)); endfunction virtual function string get_type_name(); return "uvm_transport_port"; endfunction task transport (REQ req, output RSP rsp); this.m_if.transport(req, rsp); endtask function bit nb_transport (REQ req, output RSP rsp); return this.m_if.nb_transport(req, rsp); endfunction endclass class uvm_blocking_put_export #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (1<<0); endfunction virtual function string get_type_name(); return "uvm_blocking_put_export"; endfunction task put (T t); this.m_if.put(t); endtask endclass class uvm_nonblocking_put_export #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (1<<4); endfunction virtual function string get_type_name(); return "uvm_nonblocking_put_export"; endfunction function bit try_put (T t); return this.m_if.try_put(t); endfunction function bit can_put(); return this.m_if.can_put(); endfunction endclass class uvm_put_export #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = ((1<<0) | (1<<4)); endfunction virtual function string get_type_name(); return "uvm_put_export"; endfunction task put (T t); this.m_if.put(t); endtask function bit try_put (T t); return this.m_if.try_put(t); endfunction function bit can_put(); return this.m_if.can_put(); endfunction endclass class uvm_blocking_get_export #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (1<<1); endfunction virtual function string get_type_name(); return "uvm_blocking_get_export"; endfunction task get (output T t); this.m_if.get(t); endtask endclass class uvm_nonblocking_get_export #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (1<<5); endfunction virtual function string get_type_name(); return "uvm_nonblocking_get_export"; endfunction function bit try_get (output T t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction endclass class uvm_get_export #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = ((1<<1) | (1<<5)); endfunction virtual function string get_type_name(); return "uvm_get_export"; endfunction task get (output T t); this.m_if.get(t); endtask function bit try_get (output T t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction endclass class uvm_blocking_peek_export #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (1<<2); endfunction virtual function string get_type_name(); return "uvm_blocking_peek_export"; endfunction task peek (output T t); this.m_if.peek(t); endtask endclass class uvm_nonblocking_peek_export #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (1<<6); endfunction virtual function string get_type_name(); return "uvm_nonblocking_peek_export"; endfunction function bit try_peek (output T t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_peek_export #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = ((1<<2) | (1<<6)); endfunction virtual function string get_type_name(); return "uvm_peek_export"; endfunction task peek (output T t); this.m_if.peek(t); endtask function bit try_peek (output T t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_blocking_get_peek_export #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = ((1<<1) | (1<<2)); endfunction virtual function string get_type_name(); return "uvm_blocking_get_peek_export"; endfunction task get (output T t); this.m_if.get(t); endtask task peek (output T t); this.m_if.peek(t); endtask endclass class uvm_nonblocking_get_peek_export #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = ((1<<5) | (1<<6)); endfunction virtual function string get_type_name(); return "uvm_nonblocking_get_peek_export"; endfunction function bit try_get (output T t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction function bit try_peek (output T t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_get_peek_export #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (((1<<1) | (1<<5)) | ((1<<2) | (1<<6))); endfunction virtual function string get_type_name(); return "uvm_get_peek_export"; endfunction task get (output T t); this.m_if.get(t); endtask task peek (output T t); this.m_if.peek(t); endtask function bit try_get (output T t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction function bit try_peek (output T t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_blocking_master_export #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = ((1<<0) | (1<<1) | (1<<2) | (1<<9)); endfunction virtual function string get_type_name(); return "uvm_blocking_master_export"; endfunction task put (REQ t); this.m_if.put(t); endtask task get (output RSP t); this.m_if.get(t); endtask task peek (output RSP t); this.m_if.peek(t); endtask endclass class uvm_nonblocking_master_export #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = ((1<<4) | (1<<5) | (1<<6) | (1<<9)); endfunction virtual function string get_type_name(); return "uvm_nonblocking_master_export"; endfunction function bit try_put (REQ t); return this.m_if.try_put(t); endfunction function bit can_put(); return this.m_if.can_put(); endfunction function bit try_get (output RSP t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction function bit try_peek (output RSP t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_master_export #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (((1<<0) | (1<<1) | (1<<2) | (1<<9)) | ((1<<4) | (1<<5) | (1<<6) | (1<<9))); endfunction virtual function string get_type_name(); return "uvm_master_export"; endfunction task put (REQ t); this.m_if.put(t); endtask function bit try_put (REQ t); return this.m_if.try_put(t); endfunction function bit can_put(); return this.m_if.can_put(); endfunction task get (output RSP t); this.m_if.get(t); endtask task peek (output RSP t); this.m_if.peek(t); endtask function bit try_get (output RSP t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction function bit try_peek (output RSP t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_blocking_slave_export #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(RSP, REQ)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = ((1<<0) | (1<<1) | (1<<2) | (1<<10)); endfunction virtual function string get_type_name(); return "uvm_blocking_slave_export"; endfunction task put (RSP t); this.m_if.put(t); endtask task get (output REQ t); this.m_if.get(t); endtask task peek (output REQ t); this.m_if.peek(t); endtask endclass class uvm_nonblocking_slave_export #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(RSP, REQ)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = ((1<<4) | (1<<5) | (1<<6) | (1<<10)); endfunction virtual function string get_type_name(); return "uvm_nonblocking_slave_export"; endfunction function bit try_put (RSP t); return this.m_if.try_put(t); endfunction function bit can_put(); return this.m_if.can_put(); endfunction function bit try_get (output REQ t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction function bit try_peek (output REQ t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_slave_export #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(RSP, REQ)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (((1<<0) | (1<<1) | (1<<2) | (1<<10)) | ((1<<4) | (1<<5) | (1<<6) | (1<<10))); endfunction virtual function string get_type_name(); return "uvm_slave_export"; endfunction task put (RSP t); this.m_if.put(t); endtask function bit try_put (RSP t); return this.m_if.try_put(t); endfunction function bit can_put(); return this.m_if.can_put(); endfunction task get (output REQ t); this.m_if.get(t); endtask task peek (output REQ t); this.m_if.peek(t); endtask function bit try_get (output REQ t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction function bit try_peek (output REQ t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_blocking_transport_export #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (1<<3); endfunction virtual function string get_type_name(); return "uvm_blocking_transport_export"; endfunction task transport (REQ req, output RSP rsp); this.m_if.transport(req, rsp); endtask endclass class uvm_nonblocking_transport_export #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (1<<7); endfunction virtual function string get_type_name(); return "uvm_nonblocking_transport_export"; endfunction function bit nb_transport (REQ req, output RSP rsp); return this.m_if.nb_transport(req, rsp); endfunction endclass class uvm_transport_export #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = ((1<<3) | (1<<7)); endfunction virtual function string get_type_name(); return "uvm_transport_export"; endfunction task transport (REQ req, output RSP rsp); this.m_if.transport(req, rsp); endtask function bit nb_transport (REQ req, output RSP rsp); return this.m_if.nb_transport(req, rsp); endfunction endclass class uvm_analysis_port # (type T = int) extends uvm_port_base # (uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent); super.new (name, parent, UVM_PORT, 0, UVM_UNBOUNDED_CONNECTIONS); m_if_mask = (1<<8); endfunction virtual function string get_type_name(); return "uvm_analysis_port"; endfunction function void write (input T t); uvm_tlm_if_base # (T, T) tif; for (int i = 0; i < this.size(); i++) begin tif = this.get_if (i); if ( tif == null ) uvm_report_fatal ("NTCONN", {"No uvm_tlm interface is connected to ", get_full_name(), " for executing write()"}, UVM_NONE); tif.write (t); end endfunction endclass class uvm_analysis_imp #(type T=int, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = (1<<8); endfunction virtual function string get_type_name(); return "uvm_analysis_imp"; endfunction function void write (input T t); m_imp.write (t); endfunction endclass class uvm_analysis_export #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent = null); super.new (name, parent, UVM_EXPORT, 1, UVM_UNBOUNDED_CONNECTIONS); m_if_mask = (1<<8); endfunction virtual function string get_type_name(); return "uvm_analysis_export"; endfunction function void write (input T t); uvm_tlm_if_base #(T, T) tif; for (int i = 0; i < this.size(); i++) begin tif = this.get_if (i); if (tif == null) uvm_report_fatal ("NTCONN", {"No uvm_tlm interface is connected to ", get_full_name(), " for executing write()"}, UVM_NONE); tif.write (t); end endfunction endclass `define UVM_TLM_FIFO_TASK_ERROR "fifo channel task not implemented" `define UVM_TLM_FIFO_FUNCTION_ERROR "fifo channel function not implemented" class uvm_tlm_event; event trigger; endclass virtual class uvm_tlm_fifo_base #(type T=int) extends uvm_component; typedef uvm_abstract_component_registry #(uvm_tlm_fifo_base #(T)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction typedef uvm_tlm_fifo_base #(T) this_type; uvm_put_imp #(T, this_type) put_export; uvm_get_peek_imp #(T, this_type) get_peek_export; uvm_analysis_port #(T) put_ap; uvm_analysis_port #(T) get_ap; uvm_put_imp #(T, this_type) blocking_put_export; uvm_put_imp #(T, this_type) nonblocking_put_export; uvm_get_peek_imp #(T, this_type) blocking_get_export; uvm_get_peek_imp #(T, this_type) nonblocking_get_export; uvm_get_peek_imp #(T, this_type) get_export; uvm_get_peek_imp #(T, this_type) blocking_peek_export; uvm_get_peek_imp #(T, this_type) nonblocking_peek_export; uvm_get_peek_imp #(T, this_type) peek_export; uvm_get_peek_imp #(T, this_type) blocking_get_peek_export; uvm_get_peek_imp #(T, this_type) nonblocking_get_peek_export; function new(string name, uvm_component parent = null); super.new(name, parent); put_export = new("put_export", this); blocking_put_export = put_export; nonblocking_put_export = put_export; get_peek_export = new("get_peek_export", this); blocking_get_peek_export = get_peek_export; nonblocking_get_peek_export = get_peek_export; blocking_get_export = get_peek_export; nonblocking_get_export = get_peek_export; get_export = get_peek_export; blocking_peek_export = get_peek_export; nonblocking_peek_export = get_peek_export; peek_export = get_peek_export; put_ap = new("put_ap", this); get_ap = new("get_ap", this); endfunction virtual function bit use_automatic_config(); return 0; endfunction : use_automatic_config virtual function void flush(); uvm_report_error("flush", "fifo channel function not implemented", UVM_NONE); endfunction virtual function int size(); uvm_report_error("size", "fifo channel function not implemented", UVM_NONE); return 0; endfunction virtual task put(T t); uvm_report_error("put", "fifo channel task not implemented", UVM_NONE); endtask virtual task get(output T t); uvm_report_error("get", "fifo channel task not implemented", UVM_NONE); endtask virtual task peek(output T t); uvm_report_error("peek", "fifo channel task not implemented", UVM_NONE); endtask virtual function bit try_put(T t); uvm_report_error("try_put", "fifo channel function not implemented", UVM_NONE); return 0; endfunction virtual function bit try_get(output T t); uvm_report_error("try_get", "fifo channel function not implemented", UVM_NONE); return 0; endfunction virtual function bit try_peek(output T t); uvm_report_error("try_peek", "fifo channel function not implemented", UVM_NONE); return 0; endfunction virtual function bit can_put(); uvm_report_error("can_put", "fifo channel function not implemented", UVM_NONE); return 0; endfunction virtual function bit can_get(); uvm_report_error("can_get", "fifo channel function not implemented", UVM_NONE); return 0; endfunction virtual function bit can_peek(); uvm_report_error("can_peek", "fifo channel function not implemented", UVM_NONE); return 0; endfunction virtual function uvm_tlm_event ok_to_put(); uvm_report_error("ok_to_put", "fifo channel function not implemented", UVM_NONE); return null; endfunction virtual function uvm_tlm_event ok_to_get(); uvm_report_error("ok_to_get", "fifo channel function not implemented", UVM_NONE); return null; endfunction virtual function uvm_tlm_event ok_to_peek(); uvm_report_error("ok_to_peek", "fifo channel function not implemented", UVM_NONE); return null; endfunction virtual function bit is_empty(); uvm_report_error("is_empty", "fifo channel function not implemented", UVM_NONE); return 0; endfunction virtual function bit is_full(); uvm_report_error("is_full", "fifo channel function not implemented"); return 0; endfunction virtual function int used(); uvm_report_error("used", "fifo channel function not implemented", UVM_NONE); return 0; endfunction endclass typedef class uvm_tlm_event; class uvm_tlm_fifo #(type T=int) extends uvm_tlm_fifo_base #(T); typedef uvm_component_registry #(uvm_tlm_fifo#(T)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_tlm_fifo #(T)"; endfunction : type_name virtual function string get_type_name(); return "uvm_tlm_fifo #(T)"; endfunction : get_type_name local mailbox #( T ) m; local int m_size; protected int m_pending_blocked_gets; function new(string name, uvm_component parent = null, int size = 1); super.new(name, parent); m = new( size ); m_size = size; endfunction virtual function int size(); return m_size; endfunction virtual function int used(); return m.num(); endfunction virtual function bit is_empty(); return (m.num() == 0); endfunction virtual function bit is_full(); return (m_size != 0) && (m.num() == m_size); endfunction virtual task put( input T t ); m.put( t ); put_ap.write( t ); endtask virtual task get( output T t ); m_pending_blocked_gets++; m.get( t ); m_pending_blocked_gets--; get_ap.write( t ); endtask virtual task peek( output T t ); m.peek( t ); endtask virtual function bit try_get( output T t ); if( !m.try_get( t ) ) begin return 0; end get_ap.write( t ); return 1; endfunction virtual function bit try_peek( output T t ); if( !m.try_peek( t ) ) begin return 0; end return 1; endfunction virtual function bit try_put( input T t ); if( !m.try_put( t ) ) begin return 0; end put_ap.write( t ); return 1; endfunction virtual function bit can_put(); return m_size == 0 || m.num() < m_size; endfunction virtual function bit can_get(); return m.num() > 0 && m_pending_blocked_gets == 0; endfunction virtual function bit can_peek(); return m.num() > 0; endfunction virtual function void flush(); T t; bit r; r = 1; while( r ) r = try_get( t ) ; if( m.num() > 0 && m_pending_blocked_gets != 0 ) begin uvm_report_error("flush failed" , "there are blocked gets preventing the flush", UVM_NONE); end endfunction endclass class uvm_tlm_analysis_fifo #(type T = int) extends uvm_tlm_fifo #(T); typedef uvm_component_registry #(uvm_tlm_analysis_fifo#(T)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_tlm_analysis_fifo #(T)"; endfunction : type_name virtual function string get_type_name(); return "uvm_tlm_analysis_fifo #(T)"; endfunction : get_type_name uvm_analysis_imp #(T, uvm_tlm_analysis_fifo #(T)) analysis_export; function new(string name , uvm_component parent = null); super.new(name, parent, 0); analysis_export = new("analysis_export", this); endfunction function void write(input T t); void'(this.try_put(t)); endfunction endclass class uvm_tlm_req_rsp_channel #(type REQ=int, type RSP=REQ) extends uvm_component; typedef uvm_tlm_req_rsp_channel #(REQ, RSP) this_type; typedef uvm_component_registry #(uvm_tlm_req_rsp_channel#(REQ,RSP)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_tlm_req_rsp_channel #(REQ,RSP)"; endfunction : type_name virtual function string get_type_name(); return "uvm_tlm_req_rsp_channel #(REQ,RSP)"; endfunction : get_type_name uvm_put_export #(REQ) put_request_export; uvm_get_peek_export #(RSP) get_peek_response_export; uvm_get_peek_export #(REQ) get_peek_request_export; uvm_put_export #(RSP) put_response_export; uvm_analysis_port #(REQ) request_ap; uvm_analysis_port #(RSP) response_ap; uvm_master_imp #(REQ, RSP, this_type, uvm_tlm_fifo #(REQ), uvm_tlm_fifo #(RSP)) master_export; uvm_slave_imp #(REQ, RSP, this_type, uvm_tlm_fifo #(REQ), uvm_tlm_fifo #(RSP)) slave_export; uvm_put_export #(REQ) blocking_put_request_export, nonblocking_put_request_export; uvm_get_peek_export #(REQ) get_request_export, blocking_get_request_export, nonblocking_get_request_export, peek_request_export, blocking_peek_request_export, nonblocking_peek_request_export, blocking_get_peek_request_export, nonblocking_get_peek_request_export; uvm_put_export #(RSP) blocking_put_response_export, nonblocking_put_response_export; uvm_get_peek_export #(RSP) get_response_export, blocking_get_response_export, nonblocking_get_response_export, peek_response_export, blocking_peek_response_export, nonblocking_peek_response_export, blocking_get_peek_response_export, nonblocking_get_peek_response_export; uvm_master_imp #(REQ, RSP, this_type, uvm_tlm_fifo #(REQ), uvm_tlm_fifo #(RSP)) blocking_master_export, nonblocking_master_export; uvm_slave_imp #(REQ, RSP, this_type, uvm_tlm_fifo #(REQ), uvm_tlm_fifo #(RSP)) blocking_slave_export, nonblocking_slave_export; protected uvm_tlm_fifo #(REQ) m_request_fifo; protected uvm_tlm_fifo #(RSP) m_response_fifo; function new (string name, uvm_component parent=null, int request_fifo_size=1, int response_fifo_size=1); super.new (name, parent); m_request_fifo = new ("request_fifo", this, request_fifo_size); m_response_fifo = new ("response_fifo", this, response_fifo_size); request_ap = new ("request_ap", this); response_ap = new ("response_ap", this); put_request_export = new ("put_request_export", this); get_peek_request_export = new ("get_peek_request_export", this); put_response_export = new ("put_response_export", this); get_peek_response_export = new ("get_peek_response_export", this); master_export = new ("master_export", this, m_request_fifo, m_response_fifo); slave_export = new ("slave_export", this, m_request_fifo, m_response_fifo); create_aliased_exports(); set_report_id_action_hier(s_connection_error_id, UVM_NO_ACTION); endfunction virtual function void connect_phase(uvm_phase phase); put_request_export.connect (m_request_fifo.put_export); get_peek_request_export.connect (m_request_fifo.get_peek_export); m_request_fifo.put_ap.connect (request_ap); put_response_export.connect (m_response_fifo.put_export); get_peek_response_export.connect (m_response_fifo.get_peek_export); m_response_fifo.put_ap.connect (response_ap); endfunction function void create_aliased_exports(); blocking_put_request_export = put_request_export; nonblocking_put_request_export = put_request_export; get_request_export = get_peek_request_export; blocking_get_request_export = get_peek_request_export; nonblocking_get_request_export = get_peek_request_export; peek_request_export = get_peek_request_export; blocking_peek_request_export = get_peek_request_export; nonblocking_peek_request_export = get_peek_request_export; blocking_get_peek_request_export = get_peek_request_export; nonblocking_get_peek_request_export = get_peek_request_export; blocking_put_response_export = put_response_export; nonblocking_put_response_export = put_response_export; get_response_export = get_peek_response_export; blocking_get_response_export = get_peek_response_export; nonblocking_get_response_export = get_peek_response_export; peek_response_export = get_peek_response_export; blocking_peek_response_export = get_peek_response_export; nonblocking_peek_response_export = get_peek_response_export; blocking_get_peek_response_export = get_peek_response_export; nonblocking_get_peek_response_export = get_peek_response_export; blocking_master_export = master_export; nonblocking_master_export = master_export; blocking_slave_export = slave_export; nonblocking_slave_export = slave_export; endfunction endclass class uvm_tlm_transport_channel #(type REQ=int, type RSP=REQ) extends uvm_tlm_req_rsp_channel #(REQ, RSP); typedef uvm_component_registry #(uvm_tlm_transport_channel#(REQ,RSP)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_tlm_transport_channel #(REQ,RSP)"; endfunction : type_name virtual function string get_type_name(); return "uvm_tlm_transport_channel #(REQ,RSP)"; endfunction : get_type_name typedef uvm_tlm_transport_channel #(REQ, RSP) this_type; uvm_transport_imp #(REQ, RSP, this_type) transport_export; function new (string name, uvm_component parent=null); super.new(name, parent, 1, 1); transport_export = new("transport_export", this); endfunction task transport (REQ request, output RSP response ); this.m_request_fifo.put( request ); this.m_response_fifo.get( response ); endtask function bit nb_transport (REQ req, output RSP rsp ); if(this.m_request_fifo.try_put(req)) return this.m_response_fifo.try_get(rsp); else return 0; endfunction endclass class uvm_seq_item_pull_port #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_sqr_if_base #(REQ, RSP)); function new (string name, uvm_component parent, int min_size=0, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = ((1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) | (1<<8)); endfunction virtual function string get_type_name(); return "uvm_seq_item_pull_port"; endfunction function void disable_auto_item_recording(); this.m_if.disable_auto_item_recording(); endfunction function bit is_auto_item_recording_enabled(); return this.m_if.is_auto_item_recording_enabled(); endfunction task get_next_item(output REQ t); this.m_if.get_next_item(t); endtask task try_next_item(output REQ t); this.m_if.try_next_item(t); endtask function void item_done(input RSP t = null); this.m_if.item_done(t); endfunction task wait_for_sequences(); this.m_if.wait_for_sequences(); endtask function bit has_do_available(); return this.m_if.has_do_available(); endfunction function void put_response(input RSP t); this.m_if.put_response(t); endfunction task get(output REQ t); this.m_if.get(t); endtask task peek(output REQ t); this.m_if.peek(t); endtask task put(input RSP t); this.m_if.put(t); endtask bit print_enabled; endclass class uvm_seq_item_pull_export #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_sqr_if_base #(REQ, RSP)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = ((1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) | (1<<8)); endfunction virtual function string get_type_name(); return "uvm_seq_item_pull_export"; endfunction function void disable_auto_item_recording(); this.m_if.disable_auto_item_recording(); endfunction function bit is_auto_item_recording_enabled(); return this.m_if.is_auto_item_recording_enabled(); endfunction task get_next_item(output REQ t); this.m_if.get_next_item(t); endtask task try_next_item(output REQ t); this.m_if.try_next_item(t); endtask function void item_done(input RSP t = null); this.m_if.item_done(t); endfunction task wait_for_sequences(); this.m_if.wait_for_sequences(); endtask function bit has_do_available(); return this.m_if.has_do_available(); endfunction function void put_response(input RSP t); this.m_if.put_response(t); endfunction task get(output REQ t); this.m_if.get(t); endtask task peek(output REQ t); this.m_if.peek(t); endtask task put(input RSP t); this.m_if.put(t); endtask endclass class uvm_seq_item_pull_imp #(type REQ=int, type RSP=REQ, type IMP=int) extends uvm_port_base #(uvm_sqr_if_base #(REQ, RSP)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = ((1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) | (1<<8)); endfunction virtual function string get_type_name(); return "uvm_seq_item_pull_imp"; endfunction function void disable_auto_item_recording(); m_imp.disable_auto_item_recording(); endfunction function bit is_auto_item_recording_enabled(); return m_imp.is_auto_item_recording_enabled(); endfunction task get_next_item(output REQ t); m_imp.get_next_item(t); endtask task try_next_item(output REQ t); m_imp.try_next_item(t); endtask function void item_done(input RSP t = null); m_imp.item_done(t); endfunction task wait_for_sequences(); m_imp.wait_for_sequences(); endtask function bit has_do_available(); return m_imp.has_do_available(); endfunction function void put_response(input RSP t); m_imp.put_response(t); endfunction task get(output REQ t); m_imp.get(t); endtask task peek(output REQ t); m_imp.peek(t); endtask task put(input RSP t); m_imp.put(t); endtask endclass class uvm_class_pair #(type T1=int, T2=T1) extends uvm_object; typedef uvm_class_pair #(T1, T2 ) this_type; typedef uvm_object_registry #(this_type) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); this_type tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_class_pair #(T1,T2)"; endfunction : type_name virtual function string get_type_name(); return "uvm_class_pair #(T1,T2)"; endfunction : get_type_name T1 first; T2 second; function new (string name="", T1 f=null, T2 s=null); super.new(name); if (f == null) first = new; else first = f; if (s == null) second = new; else second = s; endfunction virtual function string convert2string; string s; $sformat(s, "pair : %s, %s", first.convert2string(), second.convert2string()); return s; endfunction virtual function bit do_compare(uvm_object rhs, uvm_comparer comparer); this_type rhs_; if(!$cast(rhs_,rhs)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"WRONG_TYPE")) uvm_report_error ("WRONG_TYPE", {"do_compare: rhs argument is not of type '",get_type_name(),"'"}, UVM_NONE, "t/uvm/src/comps/uvm_pair.svh", 88, "", 1); end return 0; end return first.compare(rhs_.first) && second.compare(rhs_.second); endfunction virtual function void do_copy (uvm_object rhs); this_type rhs_; if(!$cast(rhs_,rhs)) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"WRONG_TYPE")) uvm_report_fatal ("WRONG_TYPE", {"do_copy: rhs argument is not of type '",get_type_name(),"'"}, UVM_NONE, "t/uvm/src/comps/uvm_pair.svh", 97, "", 1); end first.copy(rhs_.first); second.copy(rhs_.second); endfunction endclass class uvm_built_in_pair #(type T1=int, T2=T1) extends uvm_object; typedef uvm_built_in_pair #(T1,T2) this_type; typedef uvm_object_registry #(this_type) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); this_type tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_built_in_pair #(T1,T2)"; endfunction : type_name virtual function string get_type_name(); return "uvm_built_in_pair #(T1,T2)"; endfunction : get_type_name T1 first; T2 second; function new (string name=""); super.new(name); endfunction virtual function string convert2string; return $sformatf("built-in pair : %p, %p", first, second); endfunction virtual function bit do_compare(uvm_object rhs, uvm_comparer comparer); this_type rhs_; if(!$cast(rhs_,rhs)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"WRONG_TYPE")) uvm_report_error ("WRONG_TYPE", {"do_compare: rhs argument is not of type '",get_type_name(),"'"}, UVM_NONE, "t/uvm/src/comps/uvm_pair.svh", 146, "", 1); end return 0; end return first == rhs_.first && second == rhs_.second; endfunction function void do_copy (uvm_object rhs); this_type rhs_; if(!$cast(rhs_,rhs)) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"WRONG_TYPE")) uvm_report_fatal ("WRONG_TYPE", {"do_copy: rhs argument is not of type '",get_type_name(),"'"}, UVM_NONE, "t/uvm/src/comps/uvm_pair.svh", 155, "", 1); end first = rhs_.first; second = rhs_.second; endfunction endclass class uvm_built_in_comp #(type T=int); static function bit comp(T a, T b); return a == b; endfunction endclass class uvm_built_in_converter #(type T=int); static function string convert2string(input T t); return $sformatf("%p" , t ); endfunction endclass class uvm_built_in_clone #(type T=int); static function T clone(input T from); return from; endfunction endclass class uvm_class_comp #(type T=int); static function bit comp(input T a, input T b); return a.compare(b); endfunction endclass class uvm_class_converter #(type T=int); static function string convert2string(input T t); return t.convert2string(); endfunction endclass class uvm_class_clone #(type T=int); static function uvm_object clone(input T from); return from.clone(); endfunction endclass class uvm_in_order_comparator #( type T = int , type comp_type = uvm_built_in_comp #( T ) , type convert = uvm_built_in_converter #( T ) , type pair_type = uvm_built_in_pair #( T ) ) extends uvm_component; typedef uvm_in_order_comparator #(T,comp_type,convert,pair_type) this_type; typedef uvm_component_registry #(this_type) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_in_order_comparator #(T,comp_type,convert,pair_type)"; endfunction : type_name virtual function string get_type_name(); return "uvm_in_order_comparator #(T,comp_type,convert,pair_type)"; endfunction : get_type_name uvm_analysis_export #(T) before_export; uvm_analysis_export #(T) after_export; uvm_analysis_port #(pair_type) pair_ap; local uvm_tlm_analysis_fifo #(T) m_before_fifo; local uvm_tlm_analysis_fifo #(T) m_after_fifo; int m_matches, m_mismatches; function new(string name, uvm_component parent); super.new(name, parent); before_export = new("before_export", this); after_export = new("after_export", this); pair_ap = new("pair_ap", this); m_before_fifo = new("before", this); m_after_fifo = new("after", this); m_matches = 0; m_mismatches = 0; endfunction virtual function void connect_phase(uvm_phase phase); before_export.connect(m_before_fifo.analysis_export); after_export.connect(m_after_fifo.analysis_export); endfunction virtual task run_phase(uvm_phase phase); pair_type pair; T b; T a; string s; super.run_phase(phase); forever begin m_before_fifo.get(b); m_after_fifo.get(a); if(!comp_type::comp(b, a)) begin $sformat(s, "%s differs from %s", convert::convert2string(a), convert::convert2string(b)); uvm_report_warning("Comparator Mismatch", s); m_mismatches++; end else begin s = convert::convert2string(b); uvm_report_info("Comparator Match", s); m_matches++; end pair = new("after/before"); pair.first = a; pair.second = b; pair_ap.write(pair); end endtask virtual function void flush(); m_matches = 0; m_mismatches = 0; endfunction endclass class uvm_in_order_built_in_comparator #(type T=int) extends uvm_in_order_comparator #(T); typedef uvm_in_order_built_in_comparator #(T) this_type; typedef uvm_component_registry #(this_type) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_in_order_built_in_comparator #(T)"; endfunction : type_name virtual function string get_type_name(); return "uvm_in_order_built_in_comparator #(T)"; endfunction : get_type_name function new(string name, uvm_component parent); super.new(name, parent); endfunction endclass class uvm_in_order_class_comparator #( type T = int ) extends uvm_in_order_comparator #( T , uvm_class_comp #( T ) , uvm_class_converter #( T ) , uvm_class_pair #( T, T ) ); typedef uvm_in_order_class_comparator #(T) this_type; typedef uvm_component_registry #(this_type) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_in_order_class_comparator #(T)"; endfunction : type_name virtual function string get_type_name(); return "uvm_in_order_class_comparator #(T)"; endfunction : get_type_name function new( string name , uvm_component parent); super.new( name, parent ); endfunction endclass class uvm_algorithmic_comparator #( type BEFORE=int, type AFTER=int, type TRANSFORMER=int) extends uvm_component; typedef uvm_algorithmic_comparator #( BEFORE , AFTER , TRANSFORMER ) this_type; typedef uvm_component_registry #(this_type) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_algorithmic_comparator #(BEFORE,AFTER,TRANSFORMER)"; endfunction : type_name virtual function string get_type_name(); return "uvm_algorithmic_comparator #(BEFORE,AFTER,TRANSFORMER)"; endfunction : get_type_name uvm_analysis_imp #(BEFORE, this_type) before_export; uvm_analysis_export #(AFTER) after_export; local uvm_in_order_class_comparator #(AFTER) comp; local TRANSFORMER m_transformer; function new(string name, uvm_component parent=null, TRANSFORMER transformer=null); super.new( name , parent ); m_transformer = transformer; comp = new("comp", this ); before_export = new("before_analysis_export" , this ); after_export = new("after_analysis_export" , this ); endfunction virtual function void connect_phase(uvm_phase phase); after_export.connect( comp.after_export ); endfunction function void write( input BEFORE b ); comp.before_export.write( m_transformer.transform( b ) ); endfunction endclass virtual class uvm_subscriber #(type T=int) extends uvm_component; typedef uvm_subscriber #(T) this_type; uvm_analysis_imp #(T, this_type) analysis_export; function new (string name, uvm_component parent); super.new(name, parent); analysis_export = new("analysis_imp", this); endfunction pure virtual function void write(T t); endclass virtual class uvm_monitor extends uvm_component; typedef uvm_abstract_component_registry #(uvm_monitor,"uvm_monitor") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_monitor"; endfunction : type_name virtual function string get_type_name(); return "uvm_monitor"; endfunction : get_type_name function new (string name, uvm_component parent); super.new(name, parent); endfunction endclass typedef class uvm_sequence_item; class uvm_driver #(type REQ=uvm_sequence_item, type RSP=REQ) extends uvm_component; typedef uvm_component_registry #(uvm_driver#(REQ,RSP)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_driver #(REQ,RSP)"; endfunction : type_name virtual function string get_type_name(); return "uvm_driver #(REQ,RSP)"; endfunction : get_type_name uvm_seq_item_pull_port #(REQ, RSP) seq_item_port; uvm_seq_item_pull_port #(REQ, RSP) seq_item_prod_if; uvm_analysis_port #(RSP) rsp_port; REQ req; RSP rsp; function new (string name, uvm_component parent); super.new(name, parent); seq_item_port = new("seq_item_port", this); rsp_port = new("rsp_port", this); seq_item_prod_if = seq_item_port; endfunction virtual function void end_of_elaboration_phase(uvm_phase phase); if(seq_item_port.size<1) begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"DRVCONNECT")) uvm_report_warning ("DRVCONNECT", "the driver is not connected to a sequencer via the standard mechanisms enabled by connect()", UVM_NONE, "t/uvm/src/comps/uvm_driver.svh", 90, "", 1); end endfunction endclass class uvm_push_driver #(type REQ=uvm_sequence_item, type RSP=REQ) extends uvm_component; typedef uvm_component_registry #(uvm_push_driver#(REQ,RSP)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_push_driver #(REQ,RSP)"; endfunction : type_name virtual function string get_type_name(); return "uvm_push_driver #(REQ,RSP)"; endfunction : get_type_name uvm_blocking_put_imp #(REQ, uvm_push_driver #(REQ,RSP)) req_export; uvm_analysis_port #(RSP) rsp_port; REQ req; RSP rsp; function new (string name, uvm_component parent); super.new(name, parent); req_export = new("req_export", this); rsp_port = new("rsp_port", this); endfunction function void check_port_connections(); if (req_export.size() != 1) uvm_report_fatal("Connection Error", $sformatf("Must connect to seq_item_port(%0d)", req_export.size()), UVM_NONE); endfunction virtual function void end_of_elaboration_phase(uvm_phase phase); super.end_of_elaboration_phase(phase); check_port_connections(); endfunction virtual task put(REQ item); uvm_report_fatal("UVM_PUSH_DRIVER", "Put task for push driver is not implemented", UVM_NONE); endtask endclass virtual class uvm_scoreboard extends uvm_component; typedef uvm_abstract_component_registry #(uvm_scoreboard,"uvm_scoreboard") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_scoreboard"; endfunction : type_name virtual function string get_type_name(); return "uvm_scoreboard"; endfunction : get_type_name function new (string name, uvm_component parent); super.new(name, parent); endfunction endclass virtual class uvm_agent extends uvm_component; uvm_active_passive_enum is_active = UVM_ACTIVE; typedef uvm_abstract_component_registry #(uvm_agent,"uvm_agent") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_agent"; endfunction : type_name virtual function string get_type_name(); return "uvm_agent"; endfunction : get_type_name function new (string name, uvm_component parent); super.new(name, parent); endfunction function void build_phase(uvm_phase phase); int active; uvm_resource_pool rp; uvm_resource_types::rsrc_q_t rq; bit found; super.build_phase(phase); rp = uvm_resource_pool::get(); rq = rp.lookup_name(get_full_name(), "is_active", null, 0); uvm_resource_pool::sort_by_precedence(rq); for (int i = 0; i < rq.size() && !found; i++) begin uvm_resource_base rsrc = rq.get(i); begin begin uvm_resource#(uvm_active_passive_enum) __tmp_rsrc__; found = $cast(__tmp_rsrc__, rsrc); if (found) begin is_active = __tmp_rsrc__.read(this); end end if (!found) begin uvm_active_passive_enum __tmp_val__; string __tmp_string_val__; bit __tmp_success_val__; begin uvm_resource#(string) __tmp_rsrc__; __tmp_success_val__ = $cast(__tmp_rsrc__, rsrc); if (__tmp_success_val__) begin __tmp_string_val__ = __tmp_rsrc__.read(this); end end if (__tmp_success_val__ && uvm_enum_wrapper#(uvm_active_passive_enum)::from_name(__tmp_string_val__, __tmp_val__)) begin is_active = __tmp_val__; found = __tmp_success_val__; end end if (!found) begin typedef bit [$bits(uvm_active_passive_enum)-1:0] __tmp_int_t__; __tmp_int_t__ __tmp_int_val__; bit __tmp_success_val__; begin begin uvm_resource#(__tmp_int_t__) __tmp_rsrc__; __tmp_success_val__ = $cast(__tmp_rsrc__, rsrc); if (__tmp_success_val__) begin __tmp_int_val__ = __tmp_rsrc__.read(this); end end if (!__tmp_success_val__) begin begin uvm_resource#(uvm_integral_t) __tmp_rsrc__; __tmp_success_val__ = $cast(__tmp_rsrc__, rsrc); if (__tmp_success_val__) begin __tmp_int_val__ = __tmp_rsrc__.read(this); end end if (!__tmp_success_val__) begin uvm_resource#(uvm_bitstream_t) __tmp_rsrc__; __tmp_success_val__ = $cast(__tmp_rsrc__, rsrc); if (__tmp_success_val__) begin __tmp_int_val__ = __tmp_rsrc__.read(this); end end if (!__tmp_success_val__) begin uvm_resource#(int) __tmp_rsrc__; __tmp_success_val__ = $cast(__tmp_rsrc__, rsrc); if (__tmp_success_val__) begin __tmp_int_val__ = __tmp_rsrc__.read(this); end end if (!__tmp_success_val__) begin uvm_resource#(int unsigned) __tmp_rsrc__; __tmp_success_val__ = $cast(__tmp_rsrc__, rsrc); if (__tmp_success_val__) begin __tmp_int_val__ = __tmp_rsrc__.read(this); end end end end if (__tmp_success_val__) begin is_active = uvm_active_passive_enum'(__tmp_int_val__); found = __tmp_success_val__; end end end end endfunction virtual function uvm_active_passive_enum get_is_active(); return is_active; endfunction endclass virtual class uvm_env extends uvm_component; typedef uvm_abstract_component_registry #(uvm_env,"uvm_env") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_env"; endfunction : type_name virtual function string get_type_name(); return "uvm_env"; endfunction : get_type_name function new (string name="env", uvm_component parent=null); super.new(name,parent); endfunction endclass virtual class uvm_test extends uvm_component; typedef uvm_abstract_component_registry #(uvm_test,"uvm_test") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_test"; endfunction : type_name virtual function string get_type_name(); return "uvm_test"; endfunction : get_type_name function new (string name, uvm_component parent); super.new(name,parent); endfunction endclass typedef class uvm_sequence_base; typedef class uvm_sequencer_base; class uvm_sequence_item extends uvm_transaction; local int m_sequence_id = -1; protected bit m_use_sequence_info; protected int m_depth = -1; protected uvm_sequencer_base m_sequencer; protected uvm_sequence_base m_parent_sequence; static bit issued1,issued2; bit print_sequence_info; function new (string name = "uvm_sequence_item"); super.new(name); endfunction function string get_type_name(); return "uvm_sequence_item"; endfunction typedef uvm_object_registry#(uvm_sequence_item,"uvm_sequence_item") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function void set_sequence_id(int id); m_sequence_id = id; endfunction function int get_sequence_id(); return (m_sequence_id); endfunction function void set_item_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer = null); set_use_sequence_info(1); if (parent_seq != null) set_parent_sequence(parent_seq); if (sequencer == null && m_parent_sequence != null) sequencer = m_parent_sequence.get_sequencer(); set_sequencer(sequencer); if (m_parent_sequence != null) set_depth(m_parent_sequence.get_depth() + 1); reseed(); endfunction function void set_use_sequence_info(bit value); m_use_sequence_info = value; endfunction function bit get_use_sequence_info(); return (m_use_sequence_info); endfunction function void set_id_info(uvm_sequence_item item); if (item == null) begin uvm_report_fatal(get_full_name(), "set_id_info called with null parameter", UVM_NONE); end this.set_transaction_id(item.get_transaction_id()); this.set_sequence_id(item.get_sequence_id()); endfunction virtual function void set_sequencer(uvm_sequencer_base sequencer); m_sequencer = sequencer; m_set_p_sequencer(); endfunction function uvm_sequencer_base get_sequencer(); return m_sequencer; endfunction function void set_parent_sequence(uvm_sequence_base parent); m_parent_sequence = parent; endfunction function uvm_sequence_base get_parent_sequence(); return (m_parent_sequence); endfunction function void set_depth(int value); m_depth = value; endfunction function int get_depth(); if (m_depth != -1) begin return (m_depth); end if (m_parent_sequence == null) begin m_depth = 1; end else begin m_depth = m_parent_sequence.get_depth() + 1; end return (m_depth); endfunction virtual function bit is_item(); return(1); endfunction function string get_full_name(); if(m_parent_sequence != null) get_full_name = {m_parent_sequence.get_full_name(), "."}; else if(m_sequencer!=null) get_full_name = {m_sequencer.get_full_name(), "."}; if(get_name() != "") get_full_name = {get_full_name, get_name()}; else begin get_full_name = {get_full_name, "_item"}; end endfunction function string get_root_sequence_name(); uvm_sequence_base root_seq; root_seq = get_root_sequence(); if (root_seq == null) return ""; else return root_seq.get_name(); endfunction virtual function void m_set_p_sequencer(); return; endfunction function uvm_sequence_base get_root_sequence(); uvm_sequence_item root_seq_base; uvm_sequence_base root_seq; root_seq_base = this; while(1) begin if(root_seq_base.get_parent_sequence()!=null) begin root_seq_base = root_seq_base.get_parent_sequence(); $cast(root_seq, root_seq_base); end else return root_seq; end endfunction function string get_sequence_path(); uvm_sequence_item this_item; string seq_path; this_item = this; seq_path = this.get_name(); while(1) begin if(this_item.get_parent_sequence()!=null) begin this_item = this_item.get_parent_sequence(); seq_path = {this_item.get_name(), ".", seq_path}; end else return seq_path; end endfunction virtual function uvm_report_object uvm_get_report_object(); if(m_sequencer == null) begin uvm_coreservice_t cs = uvm_coreservice_t::get(); return cs.get_root(); end else return m_sequencer; endfunction function int uvm_report_enabled(int verbosity, uvm_severity severity=UVM_INFO, string id=""); uvm_report_object l_report_object = uvm_get_report_object(); if (l_report_object.get_report_verbosity_level(severity, id) < verbosity) return 0; return 1; endfunction virtual function void uvm_report( uvm_severity severity, string id, string message, int verbosity = (severity == uvm_severity'(UVM_ERROR)) ? UVM_LOW : (severity == uvm_severity'(UVM_FATAL)) ? UVM_NONE : UVM_MEDIUM, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_report_message l_report_message; if (report_enabled_checked == 0) begin if (!uvm_report_enabled(verbosity, severity, id)) return; end l_report_message = uvm_report_message::new_report_message(); l_report_message.set_report_message(severity, id, message, verbosity, filename, line, context_name); uvm_process_report_message(l_report_message); endfunction virtual function void uvm_report_info( string id, string message, int verbosity = UVM_MEDIUM, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); this.uvm_report(UVM_INFO, id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction virtual function void uvm_report_warning( string id, string message, int verbosity = UVM_MEDIUM, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); this.uvm_report(UVM_WARNING, id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction virtual function void uvm_report_error( string id, string message, int verbosity = UVM_NONE, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); this.uvm_report(UVM_ERROR, id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction virtual function void uvm_report_fatal( string id, string message, int verbosity = UVM_NONE, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); this.uvm_report(UVM_FATAL, id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction virtual function void uvm_process_report_message (uvm_report_message report_message); uvm_report_object l_report_object = uvm_get_report_object(); report_message.set_report_object(l_report_object); if (report_message.get_context() == "") report_message.set_context(get_sequence_path()); l_report_object.m_rh.process_report_message(report_message); endfunction function void do_print (uvm_printer printer); string temp_str0, temp_str1; int depth = get_depth(); super.do_print(printer); if(print_sequence_info || m_use_sequence_info) begin printer.print_field_int("depth", depth, $bits(depth), UVM_DEC, ".", "int"); if(m_parent_sequence != null) begin temp_str0 = m_parent_sequence.get_name(); temp_str1 = m_parent_sequence.get_full_name(); end printer.print_string("parent sequence (name)", temp_str0); printer.print_string("parent sequence (full name)", temp_str1); temp_str1 = ""; if(m_sequencer != null) begin temp_str1 = m_sequencer.get_full_name(); end printer.print_string("sequencer", temp_str1); end endfunction endclass typedef uvm_config_db#(uvm_sequence_base) uvm_config_seq; typedef class uvm_sequence_request; class uvm_sequence_process_wrapper; process pid; uvm_sequence_base seq; endclass : uvm_sequence_process_wrapper virtual class uvm_sequencer_base extends uvm_component; typedef enum {SEQ_TYPE_REQ, SEQ_TYPE_LOCK} seq_req_t; protected uvm_sequence_request arb_sequence_q[$]; protected bit arb_completed[int]; protected uvm_sequence_base lock_list[$]; protected uvm_sequence_base reg_sequences[int]; protected int m_sequencer_id; protected int m_lock_arb_size; protected int m_arb_size; protected int m_wait_for_item_sequence_id, m_wait_for_item_transaction_id; protected int m_wait_relevant_count = 0 ; protected int m_max_zero_time_wait_relevant_count = 10; protected time m_last_wait_relevant_time = 0 ; local uvm_sequencer_arb_mode m_arbitration = UVM_SEQ_ARB_FIFO; local static int g_request_id; local static int g_sequence_id = 1; local static int g_sequencer_id = 1; extern function new (string name, uvm_component parent); extern function bit is_child (uvm_sequence_base parent, uvm_sequence_base child); extern virtual function int user_priority_arbitration(int avail_sequences[$]); extern virtual task execute_item(uvm_sequence_item item); protected uvm_sequence_process_wrapper m_default_sequences[uvm_phase]; extern virtual function void start_phase_sequence(uvm_phase phase); extern virtual function void stop_phase_sequence(uvm_phase phase); extern virtual task wait_for_grant(uvm_sequence_base sequence_ptr, int item_priority = -1, bit lock_request = 0); extern virtual task wait_for_item_done(uvm_sequence_base sequence_ptr, int transaction_id); extern function bit is_blocked(uvm_sequence_base sequence_ptr); extern function bit has_lock(uvm_sequence_base sequence_ptr); extern virtual task lock(uvm_sequence_base sequence_ptr); extern virtual task grab(uvm_sequence_base sequence_ptr); extern virtual function void unlock(uvm_sequence_base sequence_ptr); extern virtual function void ungrab(uvm_sequence_base sequence_ptr); extern virtual function void stop_sequences(); extern virtual function bit is_grabbed(); extern virtual function uvm_sequence_base current_grabber(); extern virtual function bit has_do_available(); extern function void set_arbitration(UVM_SEQ_ARB_TYPE val); extern function UVM_SEQ_ARB_TYPE get_arbitration(); extern virtual task wait_for_sequences(); extern virtual function void send_request(uvm_sequence_base sequence_ptr, uvm_sequence_item t, bit rerandomize = 0); extern virtual function void set_max_zero_time_wait_relevant_count(int new_val) ; extern virtual function uvm_sequence_base get_arbitration_sequence( int index ); extern protected function void grant_queued_locks(); extern protected task m_select_sequence(); extern protected function int m_choose_next_request(); extern task m_wait_for_arbitration_completed(int request_id); extern function void m_set_arbitration_completed(int request_id); extern local task m_lock_req(uvm_sequence_base sequence_ptr, bit lock); extern function void m_unlock_req(uvm_sequence_base sequence_ptr); extern local function void remove_sequence_from_queues(uvm_sequence_base sequence_ptr); extern function void m_sequence_exiting(uvm_sequence_base sequence_ptr); extern function void kill_sequence(uvm_sequence_base sequence_ptr); extern virtual function void analysis_write(uvm_sequence_item t); extern function void do_print (uvm_printer printer); extern virtual function int m_register_sequence(uvm_sequence_base sequence_ptr); extern protected virtual function void m_unregister_sequence(int sequence_id); extern protected function uvm_sequence_base m_find_sequence(int sequence_id); extern protected function void m_update_lists(); extern function string convert2string(); extern protected virtual function int m_find_number_driver_connections(); extern protected task m_wait_arb_not_equal(); extern protected task m_wait_for_available_sequence(); extern protected function int m_get_seq_item_priority(uvm_sequence_request seq_q_entry); int m_is_relevant_completed; local bit m_auto_item_recording = 1; virtual function void disable_auto_item_recording(); m_auto_item_recording = 0; endfunction virtual function bit is_auto_item_recording_enabled(); return m_auto_item_recording; endfunction static uvm_sequencer_base all_sequencer_insts[int unsigned]; endclass function uvm_sequencer_base::new (string name, uvm_component parent); super.new(name, parent); m_sequencer_id = g_sequencer_id++; m_lock_arb_size = -1; all_sequencer_insts[m_sequencer_id]=this; endfunction function void uvm_sequencer_base::do_print (uvm_printer printer); super.do_print(printer); printer.print_array_header("arbitration_queue", arb_sequence_q.size()); foreach (arb_sequence_q[i]) printer.print_string($sformatf("[%0d]", i), $sformatf("%s@seqid%0d",arb_sequence_q[i].request.name(),arb_sequence_q[i].sequence_id), "["); printer.print_array_footer(arb_sequence_q.size()); printer.print_array_header("lock_queue", lock_list.size()); foreach(lock_list[i]) printer.print_string($sformatf("[%0d]", i), $sformatf("%s@seqid%0d",lock_list[i].get_full_name(),lock_list[i].get_sequence_id()), "["); printer.print_array_footer(lock_list.size()); endfunction function void uvm_sequencer_base::m_update_lists(); m_lock_arb_size++; endfunction function string uvm_sequencer_base::convert2string(); string s; $sformat(s, " -- arb i/id/type: "); foreach (arb_sequence_q[i]) begin $sformat(s, "%s %0d/%0d/%s ", s, i, arb_sequence_q[i].sequence_id, arb_sequence_q[i].request.name()); end $sformat(s, "%s\n -- lock_list i/id: ", s); foreach (lock_list[i]) begin $sformat(s, "%s %0d/%0d",s, i, lock_list[i].get_sequence_id()); end return(s); endfunction function int uvm_sequencer_base::m_find_number_driver_connections(); return 0; endfunction function int uvm_sequencer_base::m_register_sequence(uvm_sequence_base sequence_ptr); if (sequence_ptr.m_get_sqr_sequence_id(m_sequencer_id, 1) > 0) return sequence_ptr.get_sequence_id(); sequence_ptr.m_set_sqr_sequence_id(m_sequencer_id, g_sequence_id++); reg_sequences[sequence_ptr.get_sequence_id()] = sequence_ptr; return sequence_ptr.get_sequence_id(); endfunction function uvm_sequence_base uvm_sequencer_base::m_find_sequence(int sequence_id); uvm_sequence_base seq_ptr; int i; if (sequence_id == -1) begin if (reg_sequences.first(i)) begin return(reg_sequences[i]); end return(null); end if (!reg_sequences.exists(sequence_id)) return null; return reg_sequences[sequence_id]; endfunction function void uvm_sequencer_base::m_unregister_sequence(int sequence_id); if (!reg_sequences.exists(sequence_id)) return; reg_sequences.delete(sequence_id); endfunction function int uvm_sequencer_base::user_priority_arbitration(int avail_sequences[$]); return avail_sequences[0]; endfunction function void uvm_sequencer_base::grant_queued_locks(); begin uvm_sequence_request zombies[$]; zombies = arb_sequence_q.find(item) with (item.request==SEQ_TYPE_LOCK && item.process_id.status inside {process::KILLED,process::FINISHED}); foreach(zombies[idx]) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"SEQLCKZMB")) uvm_report_error ("SEQLCKZMB", $sformatf("The task responsible for requesting a lock on sequencer '%s' for sequence '%s' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues", this.get_full_name(), zombies[idx].sequence_ptr.get_full_name()), UVM_NONE, "t/uvm/src/seq/uvm_sequencer_base.svh", 557, "", 1); end remove_sequence_from_queues(zombies[idx].sequence_ptr); end end begin int lock_req_indices[$]; lock_req_indices = arb_sequence_q.find_first_index(item) with (item.request==SEQ_TYPE_LOCK && is_blocked(item.sequence_ptr) == 0); if(lock_req_indices.size()) begin uvm_sequence_request lock_req = arb_sequence_q[lock_req_indices[0]]; lock_list.push_back(lock_req.sequence_ptr); m_set_arbitration_completed(lock_req.request_id); arb_sequence_q.delete(lock_req_indices[0]); m_update_lists(); end end endfunction task uvm_sequencer_base::m_select_sequence(); int selected_sequence; do begin wait_for_sequences(); selected_sequence = m_choose_next_request(); if (selected_sequence == -1) begin m_wait_for_available_sequence(); end end while (selected_sequence == -1); if (selected_sequence >= 0) begin m_set_arbitration_completed(arb_sequence_q[selected_sequence].request_id); arb_sequence_q.delete(selected_sequence); m_update_lists(); end endtask function int uvm_sequencer_base::m_choose_next_request(); int i, temp; int avail_sequence_count; int sum_priority_val; int avail_sequences[$]; int highest_sequences[$]; int highest_pri; string s; avail_sequence_count = 0; grant_queued_locks(); i = 0; while (i < arb_sequence_q.size()) begin if ((arb_sequence_q[i].process_id.status == process::KILLED) || (arb_sequence_q[i].process_id.status == process::FINISHED)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"SEQREQZMB")) uvm_report_error ("SEQREQZMB", $sformatf("The task responsible for requesting a wait_for_grant on sequencer '%s' for sequence '%s' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues", this.get_full_name(), arb_sequence_q[i].sequence_ptr.get_full_name()), UVM_NONE, "t/uvm/src/seq/uvm_sequencer_base.svh", 625, "", 1); end remove_sequence_from_queues(arb_sequence_q[i].sequence_ptr); continue; end if (i < arb_sequence_q.size()) if (arb_sequence_q[i].request == SEQ_TYPE_REQ) if (is_blocked(arb_sequence_q[i].sequence_ptr) == 0) if (arb_sequence_q[i].sequence_ptr.is_relevant() == 1) begin if (m_arbitration == UVM_SEQ_ARB_FIFO) begin return i; end else avail_sequences.push_back(i); end i++; end if (m_arbitration == UVM_SEQ_ARB_FIFO) begin return -1; end if (avail_sequences.size() < 1) begin return -1; end if (avail_sequences.size() == 1) begin return avail_sequences[0]; end if (lock_list.size() > 0) begin for (i = 0; i < avail_sequences.size(); i++) begin if (is_blocked(arb_sequence_q[avail_sequences[i]].sequence_ptr) != 0) begin avail_sequences.delete(i); i--; end end if (avail_sequences.size() < 1) return -1; if (avail_sequences.size() == 1) return avail_sequences[0]; end if (m_arbitration == UVM_SEQ_ARB_WEIGHTED) begin sum_priority_val = 0; for (i = 0; i < avail_sequences.size(); i++) begin sum_priority_val += m_get_seq_item_priority(arb_sequence_q[avail_sequences[i]]); end temp = $urandom_range(sum_priority_val-1, 0); sum_priority_val = 0; for (i = 0; i < avail_sequences.size(); i++) begin if ((m_get_seq_item_priority(arb_sequence_q[avail_sequences[i]]) + sum_priority_val) > temp) begin return avail_sequences[i]; end sum_priority_val += m_get_seq_item_priority(arb_sequence_q[avail_sequences[i]]); end uvm_report_fatal("Sequencer", "UVM Internal error in weighted arbitration code", UVM_NONE); end if (m_arbitration == UVM_SEQ_ARB_RANDOM) begin i = $urandom_range(avail_sequences.size()-1, 0); return avail_sequences[i]; end if ((m_arbitration == UVM_SEQ_ARB_STRICT_FIFO) || m_arbitration == UVM_SEQ_ARB_STRICT_RANDOM) begin highest_pri = 0; for (i = 0; i < avail_sequences.size(); i++) begin if (m_get_seq_item_priority(arb_sequence_q[avail_sequences[i]]) > highest_pri) begin highest_sequences.delete(); highest_sequences.push_back(avail_sequences[i]); highest_pri = m_get_seq_item_priority(arb_sequence_q[avail_sequences[i]]); end else if (m_get_seq_item_priority(arb_sequence_q[avail_sequences[i]]) == highest_pri) begin highest_sequences.push_back(avail_sequences[i]); end end if (m_arbitration == UVM_SEQ_ARB_STRICT_FIFO) begin return(highest_sequences[0]); end i = $urandom_range(highest_sequences.size()-1, 0); return highest_sequences[i]; end if (m_arbitration == UVM_SEQ_ARB_USER) begin i = user_priority_arbitration( avail_sequences); highest_sequences = avail_sequences.find with (item == i); if (highest_sequences.size() == 0) begin uvm_report_fatal("Sequencer", $sformatf("Error in User arbitration, sequence %0d not available\n%s", i, convert2string()), UVM_NONE); end return(i); end uvm_report_fatal("Sequencer", "Internal error: Failed to choose sequence", UVM_NONE); endfunction task uvm_sequencer_base::m_wait_arb_not_equal(); wait (m_arb_size != m_lock_arb_size); endtask task uvm_sequencer_base::m_wait_for_available_sequence(); int i; int is_relevant_entries[$]; m_arb_size = m_lock_arb_size; for (i = 0; i < arb_sequence_q.size(); i++) begin if (arb_sequence_q[i].request == SEQ_TYPE_REQ) begin if (is_blocked(arb_sequence_q[i].sequence_ptr) == 0) begin if (arb_sequence_q[i].sequence_ptr.is_relevant() == 0) begin is_relevant_entries.push_back(i); end end end end if (is_relevant_entries.size() == 0) begin m_wait_arb_not_equal(); return; end fork begin fork begin fork begin m_is_relevant_completed = 0; for(i = 0; i < is_relevant_entries.size(); i++) begin fork automatic int k = i; begin arb_sequence_q[is_relevant_entries[k]].sequence_ptr.wait_for_relevant(); if ($realtime != m_last_wait_relevant_time) begin m_last_wait_relevant_time = $realtime ; m_wait_relevant_count = 0 ; end else begin m_wait_relevant_count++ ; if (m_wait_relevant_count > m_max_zero_time_wait_relevant_count) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"SEQRELEVANTLOOP")) uvm_report_fatal ("SEQRELEVANTLOOP", $sformatf("Zero time loop detected, passed wait_for_relevant %0d times without time advancing",m_wait_relevant_count), UVM_NONE, "t/uvm/src/seq/uvm_sequencer_base.svh", 798, "", 1); end end end m_is_relevant_completed = 1; end join_none end wait (m_is_relevant_completed > 0); end begin m_wait_arb_not_equal(); end join_any end join_any disable fork; end join endtask function int uvm_sequencer_base::m_get_seq_item_priority(uvm_sequence_request seq_q_entry); if (seq_q_entry.item_priority != -1) begin if (seq_q_entry.item_priority <= 0) begin uvm_report_fatal("SEQITEMPRI", $sformatf("Sequence item from %s has illegal priority: %0d", seq_q_entry.sequence_ptr.get_full_name(), seq_q_entry.item_priority), UVM_NONE); end return seq_q_entry.item_priority; end if (seq_q_entry.sequence_ptr.get_priority() < 0) begin uvm_report_fatal("SEQDEFPRI", $sformatf("Sequence %s has illegal priority: %0d", seq_q_entry.sequence_ptr.get_full_name(), seq_q_entry.sequence_ptr.get_priority()), UVM_NONE); end return seq_q_entry.sequence_ptr.get_priority(); endfunction task uvm_sequencer_base::m_wait_for_arbitration_completed(int request_id); int lock_arb_size; forever begin lock_arb_size = m_lock_arb_size; if (arb_completed.exists(request_id)) begin arb_completed.delete(request_id); return; end wait (lock_arb_size != m_lock_arb_size); end endtask function void uvm_sequencer_base::m_set_arbitration_completed(int request_id); arb_completed[request_id] = 1; endfunction function bit uvm_sequencer_base::is_child (uvm_sequence_base parent, uvm_sequence_base child); uvm_sequence_base child_parent; if (child == null) begin uvm_report_fatal("uvm_sequencer", "is_child passed null child", UVM_NONE); end if (parent == null) begin uvm_report_fatal("uvm_sequencer", "is_child passed null parent", UVM_NONE); end child_parent = child.get_parent_sequence(); while (child_parent != null) begin if (child_parent.get_inst_id() == parent.get_inst_id()) begin return 1; end child_parent = child_parent.get_parent_sequence(); end return 0; endfunction class m_uvm_sqr_seq_base extends uvm_sequence_base; function new(string name="unnamed-m_uvm_sqr_seq_base"); super.new(name); endfunction : new endclass : m_uvm_sqr_seq_base task uvm_sequencer_base::execute_item(uvm_sequence_item item); m_uvm_sqr_seq_base seq; seq = new("execute_item_seq"); item.set_sequencer(this); item.set_parent_sequence(seq); seq.set_sequencer(this); seq.start_item(item); seq.finish_item(item); endtask task uvm_sequencer_base::wait_for_grant(uvm_sequence_base sequence_ptr, int item_priority = -1, bit lock_request = 0); uvm_sequence_request req_s; int my_seq_id; if (sequence_ptr == null) uvm_report_fatal("uvm_sequencer", "wait_for_grant passed null sequence_ptr", UVM_NONE); my_seq_id = m_register_sequence(sequence_ptr); if (lock_request == 1) begin req_s = new(); req_s.grant = 0; req_s.sequence_id = my_seq_id; req_s.request = SEQ_TYPE_LOCK; req_s.sequence_ptr = sequence_ptr; req_s.request_id = g_request_id++; req_s.process_id = process::self(); arb_sequence_q.push_back(req_s); end req_s = new(); req_s.grant = 0; req_s.request = SEQ_TYPE_REQ; req_s.sequence_id = my_seq_id; req_s.item_priority = item_priority; req_s.sequence_ptr = sequence_ptr; req_s.request_id = g_request_id++; req_s.process_id = process::self(); arb_sequence_q.push_back(req_s); m_update_lists(); m_wait_for_arbitration_completed(req_s.request_id); req_s.sequence_ptr.m_wait_for_grant_semaphore++; endtask task uvm_sequencer_base::wait_for_item_done(uvm_sequence_base sequence_ptr, int transaction_id); int sequence_id; sequence_id = sequence_ptr.m_get_sqr_sequence_id(m_sequencer_id, 1); m_wait_for_item_sequence_id = -1; m_wait_for_item_transaction_id = -1; if (transaction_id == -1) wait (m_wait_for_item_sequence_id == sequence_id); else wait ((m_wait_for_item_sequence_id == sequence_id && m_wait_for_item_transaction_id == transaction_id)); endtask function bit uvm_sequencer_base::is_blocked(uvm_sequence_base sequence_ptr); if (sequence_ptr == null) uvm_report_fatal("uvm_sequence_controller", "is_blocked passed null sequence_ptr", UVM_NONE); foreach (lock_list[i]) begin if ((lock_list[i].get_inst_id() != sequence_ptr.get_inst_id()) && (is_child(lock_list[i], sequence_ptr) == 0)) begin return 1; end end return 0; endfunction function bit uvm_sequencer_base::has_lock(uvm_sequence_base sequence_ptr); int my_seq_id; if (sequence_ptr == null) uvm_report_fatal("uvm_sequence_controller", "has_lock passed null sequence_ptr", UVM_NONE); my_seq_id = m_register_sequence(sequence_ptr); foreach (lock_list[i]) begin if (lock_list[i].get_inst_id() == sequence_ptr.get_inst_id()) begin return 1; end end return 0; endfunction task uvm_sequencer_base::m_lock_req(uvm_sequence_base sequence_ptr, bit lock); int my_seq_id; uvm_sequence_request new_req; if (sequence_ptr == null) uvm_report_fatal("uvm_sequence_controller", "lock_req passed null sequence_ptr", UVM_NONE); my_seq_id = m_register_sequence(sequence_ptr); new_req = new(); new_req.grant = 0; new_req.sequence_id = sequence_ptr.get_sequence_id(); new_req.request = SEQ_TYPE_LOCK; new_req.sequence_ptr = sequence_ptr; new_req.request_id = g_request_id++; new_req.process_id = process::self(); if (lock == 1) begin arb_sequence_q.push_back(new_req); end else begin arb_sequence_q.push_front(new_req); m_update_lists(); end grant_queued_locks(); m_wait_for_arbitration_completed(new_req.request_id); endtask function void uvm_sequencer_base::m_unlock_req(uvm_sequence_base sequence_ptr); if (sequence_ptr == null) begin uvm_report_fatal("uvm_sequencer", "m_unlock_req passed null sequence_ptr", UVM_NONE); end begin int q[$]; int seqid=sequence_ptr.get_inst_id(); q=lock_list.find_first_index(item) with (item.get_inst_id() == seqid); if(q.size()==1) begin lock_list.delete(q[0]); grant_queued_locks(); m_update_lists(); end else uvm_report_warning("SQRUNL", {"Sequence '", sequence_ptr.get_full_name(), "' called ungrab / unlock, but didn't have lock"}, UVM_NONE); end endfunction task uvm_sequencer_base::lock(uvm_sequence_base sequence_ptr); m_lock_req(sequence_ptr, 1); endtask task uvm_sequencer_base::grab(uvm_sequence_base sequence_ptr); m_lock_req(sequence_ptr, 0); endtask function void uvm_sequencer_base::unlock(uvm_sequence_base sequence_ptr); m_unlock_req(sequence_ptr); endfunction function void uvm_sequencer_base::ungrab(uvm_sequence_base sequence_ptr); m_unlock_req(sequence_ptr); endfunction function void uvm_sequencer_base::remove_sequence_from_queues( uvm_sequence_base sequence_ptr); int i; int seq_id; seq_id = sequence_ptr.m_get_sqr_sequence_id(m_sequencer_id, 0); i = 0; do begin if (arb_sequence_q.size() > i) begin if ((arb_sequence_q[i].sequence_id == seq_id) || (is_child(sequence_ptr, arb_sequence_q[i].sequence_ptr))) begin if (sequence_ptr.get_sequence_state() == UVM_FINISHED) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"SEQFINERR")) uvm_report_error ("SEQFINERR", $sformatf("Parent sequence '%s' should not finish before all items from itself and items from descendent sequences are processed. The item request from the sequence '%s' is being removed.", sequence_ptr.get_full_name(), arb_sequence_q[i].sequence_ptr.get_full_name()), UVM_NONE, "t/uvm/src/seq/uvm_sequencer_base.svh", 1153, "", 1); end arb_sequence_q.delete(i); m_update_lists(); end else begin i++; end end end while (i < arb_sequence_q.size()); i = 0; do begin if (lock_list.size() > i) begin if ((lock_list[i].get_inst_id() == sequence_ptr.get_inst_id()) || (is_child(sequence_ptr, lock_list[i]))) begin if (sequence_ptr.get_sequence_state() == UVM_FINISHED) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"SEQFINERR")) uvm_report_error ("SEQFINERR", $sformatf("Parent sequence '%s' should not finish before locks from itself and descedent sequences are removed. The lock held by the child sequence '%s' is being removed.",sequence_ptr.get_full_name(), lock_list[i].get_full_name()), UVM_NONE, "t/uvm/src/seq/uvm_sequencer_base.svh", 1172, "", 1); end lock_list.delete(i); m_update_lists(); end else begin i++; end end end while (i < lock_list.size()); m_unregister_sequence(sequence_ptr.m_get_sqr_sequence_id(m_sequencer_id, 1)); endfunction function void uvm_sequencer_base::stop_sequences(); uvm_sequence_base seq_ptr; seq_ptr = m_find_sequence(-1); while (seq_ptr != null) begin kill_sequence(seq_ptr); seq_ptr = m_find_sequence(-1); end endfunction function void uvm_sequencer_base::m_sequence_exiting(uvm_sequence_base sequence_ptr); remove_sequence_from_queues(sequence_ptr); endfunction function void uvm_sequencer_base::kill_sequence(uvm_sequence_base sequence_ptr); remove_sequence_from_queues(sequence_ptr); sequence_ptr.m_kill(); endfunction function bit uvm_sequencer_base::is_grabbed(); return (lock_list.size() != 0); endfunction function uvm_sequence_base uvm_sequencer_base::current_grabber(); if (lock_list.size() == 0) begin return null; end return lock_list[lock_list.size()-1]; endfunction function bit uvm_sequencer_base::has_do_available(); foreach (arb_sequence_q[i]) begin if ((arb_sequence_q[i].sequence_ptr.is_relevant() == 1) && (is_blocked(arb_sequence_q[i].sequence_ptr) == 0)) begin return 1; end end return 0; endfunction function void uvm_sequencer_base::set_arbitration(UVM_SEQ_ARB_TYPE val); m_arbitration = val; endfunction function UVM_SEQ_ARB_TYPE uvm_sequencer_base::get_arbitration(); return m_arbitration; endfunction function uvm_sequence_base uvm_sequencer_base::get_arbitration_sequence( int index); return arb_sequence_q[index].sequence_ptr; endfunction function void uvm_sequencer_base::analysis_write(uvm_sequence_item t); return; endfunction task uvm_sequencer_base::wait_for_sequences(); uvm_wait_for_nba_region(); endtask function void uvm_sequencer_base::send_request(uvm_sequence_base sequence_ptr, uvm_sequence_item t, bit rerandomize = 0); return; endfunction function void uvm_sequencer_base::set_max_zero_time_wait_relevant_count(int new_val) ; m_max_zero_time_wait_relevant_count = new_val ; endfunction function void uvm_sequencer_base::start_phase_sequence(uvm_phase phase); uvm_resource_pool rp = uvm_resource_pool::get(); uvm_resource_types::rsrc_q_t rq; uvm_sequence_base seq; uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory f = cs.get_factory(); rq = rp.lookup_name({get_full_name(), ".", phase.get_name(), "_phase"}, "default_sequence", null, 0); uvm_resource_pool::sort_by_precedence(rq); for (int i = 0; seq == null && i < rq.size(); i++) begin uvm_resource_base rsrc = rq.get(i); uvm_resource#(uvm_sequence_base) sbr; uvm_resource#(uvm_object_wrapper) owr; if ($cast(sbr, rsrc) && sbr != null) begin seq = sbr.read(this); if (seq == null) begin begin if (uvm_report_enabled(UVM_FULL,UVM_INFO,"UVM/SQR/PH/DEF/SB/NULL")) uvm_report_info ("UVM/SQR/PH/DEF/SB/NULL", {"Default phase sequence for phase '", phase.get_name(),"' explicitly disabled"}, UVM_FULL, "t/uvm/src/seq/uvm_sequencer_base.svh", 1341, "", 1); end return; end end else if ($cast(owr, rsrc) && owr != null) begin uvm_object_wrapper wrapper; wrapper = owr.read(this); if (wrapper == null) begin begin if (uvm_report_enabled(UVM_FULL,UVM_INFO,"UVM/SQR/PH/DEF/OW/NULL")) uvm_report_info ("UVM/SQR/PH/DEF/OW/NULL", {"Default phase sequence for phase '", phase.get_name(),"' explicitly disabled"}, UVM_FULL, "t/uvm/src/seq/uvm_sequencer_base.svh", 1353, "", 1); end return; end if (!$cast(seq, f.create_object_by_type(wrapper, get_full_name(), wrapper.get_type_name())) || seq == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"PHASESEQ")) uvm_report_warning ("PHASESEQ", {"Default sequence for phase '", phase.get_name(),"' %s is not a sequence type"}, UVM_NONE, "t/uvm/src/seq/uvm_sequencer_base.svh", 1361, "", 1); end return; end end end if (seq == null) begin begin if (uvm_report_enabled(UVM_FULL,UVM_INFO,"PHASESEQ")) uvm_report_info ("PHASESEQ", {"No default phase sequence for phase '", phase.get_name(),"'"}, UVM_FULL, "t/uvm/src/seq/uvm_sequencer_base.svh", 1369, "", 1); end return; end begin if (uvm_report_enabled(UVM_FULL,UVM_INFO,"PHASESEQ")) uvm_report_info ("PHASESEQ", {"Starting default sequence '", seq.get_type_name(),"' for phase '", phase.get_name(),"'"}, UVM_FULL, "t/uvm/src/seq/uvm_sequencer_base.svh", 1374, "", 1); end seq.print_sequence_info = 1; seq.set_sequencer(this); seq.reseed(); seq.set_starting_phase(phase); if (seq.get_randomize_enabled() && !seq.randomize()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"STRDEFSEQ")) uvm_report_warning ("STRDEFSEQ", {"Randomization failed for default sequence '", seq.get_type_name(),"' for phase '", phase.get_name(),"'"}, UVM_NONE, "t/uvm/src/seq/uvm_sequencer_base.svh", 1383, "", 1); end return; end fork begin uvm_sequence_process_wrapper w = new(); w.pid = process::self(); w.seq = seq; w.pid.srandom(uvm_create_random_seed(seq.get_type_name(), this.get_full_name())); m_default_sequences[phase] = w; seq.start(this); m_default_sequences.delete(phase); end join_none endfunction function void uvm_sequencer_base::stop_phase_sequence(uvm_phase phase); if (m_default_sequences.exists(phase)) begin begin if (uvm_report_enabled(UVM_FULL,UVM_INFO,"PHASESEQ")) uvm_report_info ("PHASESEQ", {"Killing default sequence '", m_default_sequences[phase].seq.get_type_name(), "' for phase '", phase.get_name(), "'"}, UVM_FULL, "t/uvm/src/seq/uvm_sequencer_base.svh", 1409, "", 1); end m_default_sequences[phase].seq.kill(); end else begin begin if (uvm_report_enabled(UVM_FULL,UVM_INFO,"PHASESEQ")) uvm_report_info ("PHASESEQ", {"No default sequence to kill for phase '", phase.get_name(), "'"}, UVM_FULL, "t/uvm/src/seq/uvm_sequencer_base.svh", 1415, "", 1); end end endfunction : stop_phase_sequence class uvm_sequence_request; bit grant; int sequence_id; int request_id; int item_priority; process process_id; uvm_sequencer_base::seq_req_t request; uvm_sequence_base sequence_ptr; endclass class uvm_sequencer_analysis_fifo #(type RSP = uvm_sequence_item) extends uvm_tlm_fifo #(RSP); uvm_analysis_imp #(RSP, uvm_sequencer_analysis_fifo #(RSP)) analysis_export; uvm_sequencer_base sequencer_ptr; function new (string name, uvm_component parent = null); super.new(name, parent, 0); analysis_export = new ("analysis_export", this); endfunction function void write(input RSP t); if (sequencer_ptr == null) uvm_report_fatal ("SEQRNULL", "The sequencer pointer is null when attempting a write", UVM_NONE); sequencer_ptr.analysis_write(t); endfunction endclass virtual class uvm_sequencer_param_base #(type REQ = uvm_sequence_item, type RSP = REQ) extends uvm_sequencer_base; typedef uvm_sequencer_param_base #( REQ , RSP) this_type; typedef REQ req_type; typedef RSP rsp_type; REQ m_last_req_buffer[$]; RSP m_last_rsp_buffer[$]; protected int m_num_last_reqs = 1; protected int num_last_items = m_num_last_reqs; protected int m_num_last_rsps = 1; protected int m_num_reqs_sent; protected int m_num_rsps_received; uvm_sequencer_analysis_fifo #(RSP) sqr_rsp_analysis_fifo; extern function new (string name, uvm_component parent); extern virtual function void send_request(uvm_sequence_base sequence_ptr, uvm_sequence_item t, bit rerandomize = 0); function REQ get_current_item(); REQ t; if (m_req_fifo.try_peek(t) == 0) return null; return t; endfunction extern function int get_num_reqs_sent(); extern function void set_num_last_reqs(int unsigned max); extern function int unsigned get_num_last_reqs(); function REQ last_req(int unsigned n = 0); if(n > m_num_last_reqs) begin uvm_report_warning("HSTOB", $sformatf("Invalid last access (%0d), the max history is %0d", n, m_num_last_reqs)); return null; end if(n == m_last_req_buffer.size()) return null; return m_last_req_buffer[n]; endfunction uvm_analysis_export #(RSP) rsp_export; extern function int get_num_rsps_received(); extern function void set_num_last_rsps(int unsigned max); extern function int unsigned get_num_last_rsps(); function RSP last_rsp(int unsigned n = 0); if(n > m_num_last_rsps) begin uvm_report_warning("HSTOB", $sformatf("Invalid last access (%0d), the max history is %0d", n, m_num_last_rsps)); return null; end if(n == m_last_rsp_buffer.size()) return null; return m_last_rsp_buffer[n]; endfunction extern function void m_last_rsp_push_front(RSP item); extern function void put_response (RSP t); extern virtual function void build_phase(uvm_phase phase); extern virtual function void connect_phase(uvm_phase phase); extern virtual function void do_print (uvm_printer printer); extern virtual function void analysis_write(uvm_sequence_item t); extern function void m_last_req_push_front(REQ item); uvm_tlm_fifo #(REQ) m_req_fifo; endclass function uvm_sequencer_param_base::new (string name, uvm_component parent); super.new(name, parent); rsp_export = new("rsp_export", this); sqr_rsp_analysis_fifo = new("sqr_rsp_analysis_fifo", this); sqr_rsp_analysis_fifo.print_enabled = 0; m_req_fifo = new("req_fifo", this); m_req_fifo.print_enabled = 0; endfunction function void uvm_sequencer_param_base::do_print (uvm_printer printer); super.do_print(printer); printer.print_field_int("num_last_reqs", m_num_last_reqs, $bits(m_num_last_reqs), UVM_DEC); printer.print_field_int("num_last_rsps", m_num_last_rsps, $bits(m_num_last_rsps), UVM_DEC); endfunction function void uvm_sequencer_param_base::connect_phase(uvm_phase phase); super.connect_phase(phase); rsp_export.connect(sqr_rsp_analysis_fifo.analysis_export); endfunction function void uvm_sequencer_param_base::build_phase(uvm_phase phase); super.build_phase(phase); sqr_rsp_analysis_fifo.sequencer_ptr = this; endfunction function void uvm_sequencer_param_base::send_request(uvm_sequence_base sequence_ptr, uvm_sequence_item t, bit rerandomize = 0); REQ param_t; if (sequence_ptr == null) begin uvm_report_fatal("SNDREQ", "Send request sequence_ptr is null", UVM_NONE); end if (sequence_ptr.m_wait_for_grant_semaphore < 1) begin uvm_report_fatal("SNDREQ", "Send request called without wait_for_grant", UVM_NONE); end sequence_ptr.m_wait_for_grant_semaphore--; if ($cast(param_t, t)) begin if (rerandomize == 1) begin if (!param_t.randomize()) begin uvm_report_warning("SQRSNDREQ", "Failed to rerandomize sequence item in send_request"); end end if (param_t.get_transaction_id() == -1) begin param_t.set_transaction_id(sequence_ptr.m_next_transaction_id++); end m_last_req_push_front(param_t); end else begin uvm_report_fatal("SQRSNDREQCAST",$sformatf("send_request failed to cast sequence item"), UVM_NONE); end param_t.set_sequence_id(sequence_ptr.m_get_sqr_sequence_id(m_sequencer_id, 1)); t.set_sequencer(this); if (m_req_fifo.try_put(param_t) != 1) begin uvm_report_fatal("SQRSNDREQGNI", "Concurrent calls to get_next_item() not supported. Consider using a semaphore to ensure that concurrent processes take turns in the driver", UVM_NONE); end m_num_reqs_sent++; grant_queued_locks(); endfunction function void uvm_sequencer_param_base::put_response (RSP t); uvm_sequence_base sequence_ptr; if (t == null) begin uvm_report_fatal("SQRPUT", "Driver put a null response", UVM_NONE); end m_last_rsp_push_front(t); m_num_rsps_received++; if (t.get_sequence_id() == -1) begin uvm_report_fatal("SQRPUT", "Driver put a response with null sequence_id", UVM_NONE); return; end sequence_ptr = m_find_sequence(t.get_sequence_id()); if (sequence_ptr != null) begin if (sequence_ptr.get_use_response_handler() == 1) begin sequence_ptr.response_handler(t); return; end sequence_ptr.put_response(t); end else begin uvm_report_warning("Sequencer", $sformatf("Dropping response for sequence %0d, sequence not found. Probable cause: sequence exited or has been killed", t.get_sequence_id())); end endfunction function void uvm_sequencer_param_base::analysis_write(uvm_sequence_item t); RSP response; if (!$cast(response, t)) begin uvm_report_fatal("ANALWRT", "Failure to cast analysis port write item", UVM_NONE); end put_response(response); endfunction function int uvm_sequencer_param_base::get_num_reqs_sent(); return m_num_reqs_sent; endfunction function int uvm_sequencer_param_base::get_num_rsps_received(); return m_num_rsps_received; endfunction function void uvm_sequencer_param_base::set_num_last_reqs(int unsigned max); if(max > 1024) begin uvm_report_warning("HSTOB", $sformatf("Invalid last size; 1024 is the maximum and will be used")); max = 1024; end while((m_last_req_buffer.size() != 0) && (m_last_req_buffer.size() > max)) void'(m_last_req_buffer.pop_back()); m_num_last_reqs = max; num_last_items = max; endfunction function int unsigned uvm_sequencer_param_base::get_num_last_reqs(); return m_num_last_reqs; endfunction function void uvm_sequencer_param_base::m_last_req_push_front(REQ item); if(!m_num_last_reqs) return; if(m_last_req_buffer.size() == m_num_last_reqs) void'(m_last_req_buffer.pop_back()); this.m_last_req_buffer.push_front(item); endfunction function void uvm_sequencer_param_base::set_num_last_rsps(int unsigned max); if(max > 1024) begin uvm_report_warning("HSTOB", $sformatf("Invalid last size; 1024 is the maximum and will be used")); max = 1024; end while((m_last_rsp_buffer.size() != 0) && (m_last_rsp_buffer.size() > max)) begin void'(m_last_rsp_buffer.pop_back()); end m_num_last_rsps = max; endfunction function int unsigned uvm_sequencer_param_base::get_num_last_rsps(); return m_num_last_rsps; endfunction function void uvm_sequencer_param_base::m_last_rsp_push_front(RSP item); if(!m_num_last_rsps) return; if(m_last_rsp_buffer.size() == m_num_last_rsps) void'(m_last_rsp_buffer.pop_back()); this.m_last_rsp_buffer.push_front(item); endfunction class uvm_sequencer #(type REQ=uvm_sequence_item, RSP=REQ) extends uvm_sequencer_param_base #(REQ, RSP); typedef uvm_sequencer #( REQ , RSP) this_type; bit sequence_item_requested; bit get_next_item_called; typedef uvm_component_registry #(this_type) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction extern function new (string name, uvm_component parent=null); extern virtual function void stop_sequences(); extern virtual function string get_type_name(); uvm_seq_item_pull_imp #(REQ, RSP, this_type) seq_item_export; extern virtual task get_next_item (output REQ t); extern virtual task try_next_item (output REQ t); extern virtual function void item_done (RSP item = null); extern virtual task put (RSP t); extern task get (output REQ t); extern task peek (output REQ t); extern function void item_done_trigger(RSP item = null); function RSP item_done_get_trigger_data(); return last_rsp(0); endfunction extern protected virtual function int m_find_number_driver_connections(); endclass typedef uvm_sequencer #(uvm_sequence_item) uvm_virtual_sequencer; function uvm_sequencer::new (string name, uvm_component parent=null); super.new(name, parent); seq_item_export = new ("seq_item_export", this); endfunction function void uvm_sequencer::stop_sequences(); REQ t; super.stop_sequences(); sequence_item_requested = 0; get_next_item_called = 0; if (m_req_fifo.used()) begin uvm_report_info(get_full_name(), "Sequences stopped. Removing request from sequencer fifo"); m_req_fifo.flush(); end endfunction function string uvm_sequencer::get_type_name(); return "uvm_sequencer"; endfunction function int uvm_sequencer::m_find_number_driver_connections(); uvm_port_base #(uvm_sqr_if_base #(REQ, RSP)) provided_to_port_list[string]; seq_item_export.get_provided_to(provided_to_port_list); return provided_to_port_list.num(); endfunction task uvm_sequencer::get_next_item(output REQ t); REQ req_item; if (get_next_item_called == 1) uvm_report_error(get_full_name(), "Get_next_item called twice without item_done or get in between", UVM_NONE); if (!sequence_item_requested) m_select_sequence(); sequence_item_requested = 1; get_next_item_called = 1; m_req_fifo.peek(t); endtask task uvm_sequencer::try_next_item(output REQ t); int selected_sequence; time arb_time; uvm_sequence_base seq; if (get_next_item_called == 1) begin uvm_report_error(get_full_name(), "get_next_item/try_next_item called twice without item_done or get in between", UVM_NONE); return; end wait_for_sequences(); selected_sequence = m_choose_next_request(); if (selected_sequence == -1) begin t = null; return; end m_set_arbitration_completed(arb_sequence_q[selected_sequence].request_id); seq = arb_sequence_q[selected_sequence].sequence_ptr; arb_sequence_q.delete(selected_sequence); m_update_lists(); sequence_item_requested = 1; get_next_item_called = 1; wait_for_sequences(); if (!m_req_fifo.try_peek(t)) uvm_report_error("TRY_NEXT_BLOCKED", {"try_next_item: the selected sequence '", seq.get_full_name(), "' did not produce an item within an NBA delay. ", "Sequences should not consume time between calls to start_item and finish_item. ", "Returning null item."}, UVM_NONE); endtask function void uvm_sequencer::item_done(RSP item = null); REQ t; sequence_item_requested = 0; get_next_item_called = 0; if (m_req_fifo.try_get(t) == 0) begin uvm_report_fatal("SQRBADITMDN", {"Item_done() called with no outstanding requests.", " Each call to item_done() must be paired with a previous call to get_next_item()."}); end else begin m_wait_for_item_sequence_id = t.get_sequence_id(); m_wait_for_item_transaction_id = t.get_transaction_id(); end if (item != null) begin seq_item_export.put_response(item); end grant_queued_locks(); endfunction task uvm_sequencer::put (RSP t); put_response(t); endtask task uvm_sequencer::get(output REQ t); if (sequence_item_requested == 0) begin m_select_sequence(); end sequence_item_requested = 1; m_req_fifo.peek(t); item_done(); endtask task uvm_sequencer::peek(output REQ t); if (sequence_item_requested == 0) begin m_select_sequence(); end sequence_item_requested = 1; m_req_fifo.peek(t); endtask function void uvm_sequencer::item_done_trigger(RSP item = null); item_done(item); endfunction class uvm_push_sequencer #(type REQ=uvm_sequence_item, RSP=REQ) extends uvm_sequencer_param_base #(REQ, RSP); typedef uvm_push_sequencer #( REQ , RSP) this_type; uvm_blocking_put_port #(REQ) req_port; function new (string name, uvm_component parent=null); super.new(name, parent); req_port = new ("req_port", this); endfunction task run_phase(uvm_phase phase); REQ t; int selected_sequence; fork super.run_phase(phase); forever begin m_select_sequence(); m_req_fifo.get(t); req_port.put(t); m_wait_for_item_sequence_id = t.get_sequence_id(); m_wait_for_item_transaction_id = t.get_transaction_id(); end join endtask protected virtual function int m_find_number_driver_connections(); return req_port.size(); endfunction endclass virtual class uvm_sequence_base extends uvm_sequence_item; typedef uvm_abstract_object_registry#(uvm_sequence_base,"uvm_sequence_base") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_sequence_base"; endfunction : type_name virtual function string get_type_name(); return "uvm_sequence_base"; endfunction : get_type_name protected uvm_sequence_state m_sequence_state; int m_next_transaction_id = 1; local int m_priority = -1; uvm_recorder m_tr_recorder; int m_wait_for_grant_semaphore; protected int m_sqr_seq_ids[int]; protected bit children_array[uvm_sequence_base]; protected uvm_sequence_item response_queue[$]; protected int response_queue_depth = 8; protected bit response_queue_error_report_enabled; local bit do_not_randomize; protected process m_sequence_process; local bit m_use_response_handler; local bit is_rel_default; local bit wait_rel_default; function new (string name = "uvm_sequence"); super.new(name); m_sequence_state = UVM_CREATED; m_wait_for_grant_semaphore = 0; m_init_phase_daps(1); endfunction virtual function bit get_randomize_enabled(); return (do_not_randomize == 0); endfunction : get_randomize_enabled virtual function void set_randomize_enabled(bit enable); do_not_randomize = !enable; endfunction : set_randomize_enabled virtual function bit is_item(); return 0; endfunction function uvm_sequence_state_enum get_sequence_state(); return m_sequence_state; endfunction task wait_for_sequence_state(int unsigned state_mask); wait (m_sequence_state & state_mask); endtask function int get_tr_handle(); if (m_tr_recorder != null) return m_tr_recorder.get_handle(); else return 0; endfunction virtual task start (uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence = null, int this_priority = -1, bit call_pre_post = 1); bit old_automatic_phase_objection; set_item_context(parent_sequence, sequencer); if (!(m_sequence_state inside {UVM_CREATED,UVM_STOPPED,UVM_FINISHED})) begin uvm_report_fatal("SEQ_NOT_DONE", {"Sequence ", get_full_name(), " already started"},UVM_NONE); end if (m_parent_sequence != null) begin m_parent_sequence.children_array[this] = 1; end if (this_priority < -1) begin uvm_report_fatal("SEQPRI", $sformatf("Sequence %s start has illegal priority: %0d", get_full_name(), this_priority), UVM_NONE); end if (this_priority < 0) begin if (parent_sequence == null) this_priority = 100; else this_priority = parent_sequence.get_priority(); end clear_response_queue(); m_priority = this_priority; if (m_sequencer != null) begin int handle; if (m_parent_sequence == null) begin handle = m_sequencer.begin_tr(this, get_name()); m_tr_recorder = uvm_recorder::get_recorder_from_handle(handle); end else begin handle = m_sequencer.begin_tr(.tr(this), .stream_name(get_root_sequence_name()), .parent_handle((m_parent_sequence.m_tr_recorder == null) ? 0 : m_parent_sequence.m_tr_recorder.get_handle())); m_tr_recorder = uvm_recorder::get_recorder_from_handle(handle); end end set_sequence_id(-1); if (m_sequencer != null) begin void'(m_sequencer.m_register_sequence(this)); end m_sequence_state = UVM_PRE_START; fork begin m_sequence_process = process::self(); #0; if (get_automatic_phase_objection()) begin m_safe_raise_starting_phase("automatic phase objection"); end pre_start(); if (call_pre_post == 1) begin m_sequence_state = UVM_PRE_BODY; #0; pre_body(); end if (parent_sequence != null) begin parent_sequence.pre_do(0); parent_sequence.mid_do(this); end m_sequence_state = UVM_BODY; #0; body(); m_sequence_state = UVM_ENDED; #0; if (parent_sequence != null) begin parent_sequence.post_do(this); end if (call_pre_post == 1) begin m_sequence_state = UVM_POST_BODY; #0; post_body(); end m_sequence_state = UVM_POST_START; #0; post_start(); if (get_automatic_phase_objection()) begin m_safe_drop_starting_phase("automatic phase objection"); end m_sequence_state = UVM_FINISHED; #0; end join if (m_sequencer != null) begin m_sequencer.end_tr(this); end if (m_sequence_state != UVM_STOPPED) begin clean_exit_sequence(); end #0; if ((m_parent_sequence != null) && (m_parent_sequence.children_array.exists(this))) begin m_parent_sequence.children_array.delete(this); end old_automatic_phase_objection = get_automatic_phase_objection(); m_init_phase_daps(1); set_automatic_phase_objection(old_automatic_phase_objection); endtask function void clean_exit_sequence(); if (m_sequencer != null) m_sequencer.m_sequence_exiting(this); else foreach(m_sqr_seq_ids[seqrID]) begin uvm_sequencer_base s = uvm_sequencer_base::all_sequencer_insts[seqrID]; s.m_sequence_exiting(this); end m_sqr_seq_ids.delete(); endfunction virtual task pre_start(); return; endtask virtual task pre_body(); return; endtask virtual task pre_do(bit is_item); return; endtask virtual function void mid_do(uvm_sequence_item this_item); return; endfunction virtual task body(); uvm_report_warning("uvm_sequence_base", "Body definition undefined"); return; endtask virtual function void post_do(uvm_sequence_item this_item); return; endfunction virtual task post_body(); return; endtask virtual task post_start(); return; endtask local uvm_get_to_lock_dap#(bit) m_automatic_phase_objection_dap; local uvm_get_to_lock_dap#(uvm_phase) m_starting_phase_dap; function void m_init_phase_daps(bit create); string apo_name = $sformatf("%s.automatic_phase_objection", get_full_name()); string sp_name = $sformatf("%s.starting_phase", get_full_name()); if (create) begin m_automatic_phase_objection_dap = uvm_get_to_lock_dap#(bit)::type_id::create(apo_name, get_sequencer()); m_starting_phase_dap = uvm_get_to_lock_dap#(uvm_phase)::type_id::create(sp_name, get_sequencer()); end else begin m_automatic_phase_objection_dap.set_name(apo_name); m_starting_phase_dap.set_name(sp_name); end endfunction : m_init_phase_daps function uvm_phase get_starting_phase(); return m_starting_phase_dap.get(); endfunction : get_starting_phase function void set_starting_phase(uvm_phase phase); m_starting_phase_dap.set(phase); endfunction : set_starting_phase function void set_automatic_phase_objection(bit value); m_automatic_phase_objection_dap.set(value); endfunction : set_automatic_phase_objection function bit get_automatic_phase_objection(); return m_automatic_phase_objection_dap.get(); endfunction : get_automatic_phase_objection function void m_safe_raise_starting_phase(string description = "", int count = 1); uvm_phase starting_phase = get_starting_phase(); if (starting_phase != null) starting_phase.raise_objection(this, description, count); endfunction : m_safe_raise_starting_phase function void m_safe_drop_starting_phase(string description = "", int count = 1); uvm_phase starting_phase = get_starting_phase(); if (starting_phase != null) starting_phase.drop_objection(this, description, count); endfunction : m_safe_drop_starting_phase function void set_priority (int value); m_priority = value; endfunction function int get_priority(); return m_priority; endfunction virtual function bit is_relevant(); is_rel_default = 1; return 1; endfunction virtual task wait_for_relevant(); event e; wait_rel_default = 1; if (is_rel_default != wait_rel_default) uvm_report_fatal("RELMSM", "is_relevant() was implemented without defining wait_for_relevant()", UVM_NONE); @e; endtask task lock(uvm_sequencer_base sequencer = null); if (sequencer == null) sequencer = m_sequencer; if (sequencer == null) uvm_report_fatal("LOCKSEQR", "Null m_sequencer reference", UVM_NONE); sequencer.lock(this); endtask task grab(uvm_sequencer_base sequencer = null); if (sequencer == null) begin if (m_sequencer == null) begin uvm_report_fatal("GRAB", "Null m_sequencer reference", UVM_NONE); end m_sequencer.grab(this); end else begin sequencer.grab(this); end endtask function void unlock(uvm_sequencer_base sequencer = null); if (sequencer == null) begin if (m_sequencer == null) begin uvm_report_fatal("UNLOCK", "Null m_sequencer reference", UVM_NONE); end m_sequencer.unlock(this); end else begin sequencer.unlock(this); end endfunction function void ungrab(uvm_sequencer_base sequencer = null); unlock(sequencer); endfunction function bit is_blocked(); return m_sequencer.is_blocked(this); endfunction function bit has_lock(); return m_sequencer.has_lock(this); endfunction function void kill(); if (m_sequence_process != null) begin if (m_sequencer == null) begin m_kill(); if (get_automatic_phase_objection()) begin m_safe_drop_starting_phase("automatic phase objection"); end return; end m_sequencer.kill_sequence(this); if (get_automatic_phase_objection()) begin m_safe_drop_starting_phase("automatic phase objection"); end return; end endfunction virtual function void do_kill(); return; endfunction function void m_kill(); do_kill(); foreach(children_array[i]) begin i.kill(); end if (m_sequence_process != null) begin m_sequence_process.kill; m_sequence_process = null; end m_sequence_state = UVM_STOPPED; if ((m_parent_sequence != null) && (m_parent_sequence.children_array.exists(this))) m_parent_sequence.children_array.delete(this); clean_exit_sequence(); endfunction protected function uvm_sequence_item create_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); $cast(create_item, factory.create_object_by_type( type_var, this.get_full_name(), name )); create_item.set_item_context(this, l_sequencer); endfunction virtual task start_item (uvm_sequence_item item, int set_priority = -1, uvm_sequencer_base sequencer=null); if(item == null) begin uvm_report_fatal("NULLITM", {"attempting to start a null item from sequence '", get_full_name(), "'"}, UVM_NONE); return; end if ( ! item.is_item() ) begin uvm_report_fatal("SEQNOTITM", {"attempting to start a sequence using start_item() from sequence '", get_full_name(), "'. Use seq.start() instead."}, UVM_NONE); return; end if (sequencer == null) sequencer = item.get_sequencer(); if(sequencer == null) sequencer = get_sequencer(); if(sequencer == null) begin uvm_report_fatal("SEQ",{"neither the item's sequencer nor dedicated sequencer has been supplied to start item in ",get_full_name()},UVM_NONE); return; end item.set_item_context(this, sequencer); if (set_priority < 0) set_priority = get_priority(); sequencer.wait_for_grant(this, set_priority); if (sequencer.is_auto_item_recording_enabled()) begin void'(sequencer.begin_tr(.tr(item), .stream_name(item.get_root_sequence_name()), .label("Transactions"), .parent_handle((m_tr_recorder == null) ? 0 : m_tr_recorder.get_handle()))); end pre_do(1); endtask virtual task finish_item (uvm_sequence_item item, int set_priority = -1); uvm_sequencer_base sequencer; sequencer = item.get_sequencer(); if (sequencer == null) begin uvm_report_fatal("STRITM", "sequence_item has null sequencer", UVM_NONE); end mid_do(item); sequencer.send_request(this, item); sequencer.wait_for_item_done(this, -1); if (sequencer.is_auto_item_recording_enabled()) begin sequencer.end_tr(item); end post_do(item); endtask virtual task wait_for_grant(int item_priority = -1, bit lock_request = 0); if (m_sequencer == null) begin uvm_report_fatal("WAITGRANT", "Null m_sequencer reference", UVM_NONE); end m_sequencer.wait_for_grant(this, item_priority, lock_request); endtask virtual function void send_request(uvm_sequence_item request, bit rerandomize = 0); if (m_sequencer == null) begin uvm_report_fatal("SENDREQ", "Null m_sequencer reference", UVM_NONE); end m_sequencer.send_request(this, request, rerandomize); endfunction virtual task wait_for_item_done(int transaction_id = -1); if (m_sequencer == null) begin uvm_report_fatal("WAITITEMDONE", "Null m_sequencer reference", UVM_NONE); end m_sequencer.wait_for_item_done(this, transaction_id); endtask function void use_response_handler(bit enable); m_use_response_handler = enable; endfunction function bit get_use_response_handler(); return m_use_response_handler; endfunction virtual function void response_handler(uvm_sequence_item response); return; endfunction function void set_response_queue_error_report_enabled(bit value); response_queue_error_report_enabled = value; endfunction : set_response_queue_error_report_enabled function bit get_response_queue_error_report_enabled(); return response_queue_error_report_enabled; endfunction : get_response_queue_error_report_enabled function void set_response_queue_depth(int value); response_queue_depth = value; endfunction function int get_response_queue_depth(); return response_queue_depth; endfunction virtual function void clear_response_queue(); response_queue.delete(); endfunction virtual function void put_base_response(input uvm_sequence_item response); if ((response_queue_depth == -1) || (response_queue.size() < response_queue_depth)) begin response_queue.push_back(response); return; end if (response_queue_error_report_enabled) begin uvm_report_error(get_full_name(), "Response queue overflow, response was dropped", UVM_NONE); end endfunction virtual function void put_response (uvm_sequence_item response_item); put_base_response(response_item); endfunction virtual task get_base_response(output uvm_sequence_item response, input int transaction_id = -1); int queue_size, i; if (response_queue.size() == 0) wait (response_queue.size() != 0); if (transaction_id == -1) begin response = response_queue.pop_front(); return; end forever begin queue_size = response_queue.size(); for (i = 0; i < queue_size; i++) begin if (response_queue[i].get_transaction_id() == transaction_id) begin $cast(response,response_queue[i]); response_queue.delete(i); return; end end wait (response_queue.size() != queue_size); end endtask function int m_get_sqr_sequence_id(int sequencer_id, bit update_sequence_id); if (m_sqr_seq_ids.exists(sequencer_id)) begin if (update_sequence_id == 1) begin set_sequence_id(m_sqr_seq_ids[sequencer_id]); end return m_sqr_seq_ids[sequencer_id]; end if (update_sequence_id == 1) set_sequence_id(-1); return -1; endfunction function void m_set_sqr_sequence_id(int sequencer_id, int sequence_id); m_sqr_seq_ids[sequencer_id] = sequence_id; set_sequence_id(sequence_id); endfunction endclass virtual class uvm_sequence #(type REQ = uvm_sequence_item, type RSP = REQ) extends uvm_sequence_base; typedef uvm_sequencer_param_base #(REQ, RSP) sequencer_t; sequencer_t param_sequencer; REQ req; RSP rsp; function new (string name = "uvm_sequence"); super.new(name); endfunction function void send_request(uvm_sequence_item request, bit rerandomize = 0); REQ m_request; if (m_sequencer == null) begin uvm_report_fatal("SSENDREQ", "Null m_sequencer reference", UVM_NONE); end if (!$cast(m_request, request)) begin uvm_report_fatal("SSENDREQ", "Failure to cast uvm_sequence_item to request", UVM_NONE); end m_sequencer.send_request(this, m_request, rerandomize); endfunction function REQ get_current_item(); if (!$cast(param_sequencer, m_sequencer)) uvm_report_fatal("SGTCURR", "Failure to cast m_sequencer to the parameterized sequencer", UVM_NONE); return (param_sequencer.get_current_item()); endfunction virtual task get_response(output RSP response, input int transaction_id = -1); uvm_sequence_item rsp; get_base_response( rsp, transaction_id); $cast(response,rsp); endtask virtual function void put_response(uvm_sequence_item response_item); RSP response; if (!$cast(response, response_item)) begin uvm_report_fatal("PUTRSP", "Failure to cast response in put_response", UVM_NONE); end put_base_response(response_item); endfunction function void do_print (uvm_printer printer); super.do_print(printer); printer.print_object("req", req); printer.print_object("rsp", rsp); endfunction endclass typedef class uvm_sequence_library_cfg; class uvm_sequence_library #(type REQ=uvm_sequence_item,RSP=REQ) extends uvm_sequence #(REQ,RSP); typedef uvm_object_registry #(uvm_sequence_library#(REQ,RSP)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_sequence_library#(REQ,RSP) tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_sequence_library #(REQ,RSP)"; endfunction : type_name virtual function string get_type_name(); return "uvm_sequence_library #(REQ,RSP)"; endfunction : get_type_name extern function new(string name=""); uvm_sequence_lib_mode selection_mode; int unsigned min_random_count=10; int unsigned max_random_count=10; protected int unsigned sequences_executed; rand int unsigned sequence_count = 10; rand int unsigned select_rand; randc bit [15:0] select_randc; protected int seqs_distrib[string] = '{default:0}; protected uvm_object_wrapper sequences[$]; constraint valid_rand_selection { select_rand inside {[0:sequences.size()-1]}; } constraint valid_randc_selection { select_randc inside {[0:sequences.size()-1]}; } constraint valid_sequence_count { sequence_count inside {[min_random_count:max_random_count]}; } extern virtual function int unsigned select_sequence(int unsigned max); extern static function void add_typewide_sequence(uvm_object_wrapper seq_type); extern static function void add_typewide_sequences(uvm_object_wrapper seq_types[$]); extern function void add_sequence(uvm_object_wrapper seq_type); extern virtual function void add_sequences(uvm_object_wrapper seq_types[$]); extern virtual function void remove_sequence(uvm_object_wrapper seq_type); extern virtual function void get_sequences(ref uvm_object_wrapper seq_types[$]); extern virtual function uvm_object_wrapper get_sequence(int unsigned idx); extern function void init_sequence_library(); typedef uvm_sequence_library #(REQ,RSP) this_type; static protected uvm_object_wrapper m_typewide_sequences[$]; bit m_abort; extern static function bit m_static_check(uvm_object_wrapper seq_type); extern static function bit m_check(uvm_object_wrapper seq_type, this_type lib); extern function bit m_dyn_check(uvm_object_wrapper seq_type); extern function void m_get_config(); extern static function bit m_add_typewide_sequence(uvm_object_wrapper seq_type); extern virtual task execute(uvm_object_wrapper wrap); extern virtual task body(); extern virtual function void do_print(uvm_printer printer); extern function void pre_randomize(); endclass class uvm_sequence_library_cfg extends uvm_object; typedef uvm_object_registry#(uvm_sequence_library_cfg,"uvm_sequence_library_cfg") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_sequence_library_cfg tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_sequence_library_cfg"; endfunction : type_name virtual function string get_type_name(); return "uvm_sequence_library_cfg"; endfunction : get_type_name uvm_sequence_lib_mode selection_mode; int unsigned min_random_count; int unsigned max_random_count; function new(string name="", uvm_sequence_lib_mode mode=UVM_SEQ_LIB_RAND, int unsigned min=1, int unsigned max=10); super.new(name); selection_mode = mode; min_random_count = min; max_random_count = max; endfunction endclass function uvm_sequence_library::new(string name=""); super.new(name); init_sequence_library(); valid_rand_selection.constraint_mode(0); valid_randc_selection.constraint_mode(0); endfunction function bit uvm_sequence_library::m_add_typewide_sequence(uvm_object_wrapper seq_type); this_type::add_typewide_sequence(seq_type); return 1; endfunction function void uvm_sequence_library::add_typewide_sequence(uvm_object_wrapper seq_type); if (m_static_check(seq_type)) m_typewide_sequences.push_back(seq_type); endfunction function void uvm_sequence_library::add_typewide_sequences(uvm_object_wrapper seq_types[$]); foreach (seq_types[i]) add_typewide_sequence(seq_types[i]); endfunction function void uvm_sequence_library::add_sequence(uvm_object_wrapper seq_type); if (m_dyn_check(seq_type)) sequences.push_back(seq_type); endfunction function void uvm_sequence_library::add_sequences(uvm_object_wrapper seq_types[$]); foreach (seq_types[i]) add_sequence(seq_types[i]); endfunction function void uvm_sequence_library::remove_sequence(uvm_object_wrapper seq_type); foreach (sequences[i]) if (sequences[i] == seq_type) begin sequences.delete(i); return; end endfunction function void uvm_sequence_library::get_sequences(ref uvm_object_wrapper seq_types[$]); foreach (sequences[i]) seq_types.push_back(sequences[i]); endfunction function uvm_object_wrapper uvm_sequence_library::get_sequence(int unsigned idx); if(idx < sequences.size()) return sequences[idx]; else begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"SEQ_LIB/GET_SEQ")) uvm_report_error ("SEQ_LIB/GET_SEQ", $sformatf("idx %0d > number of sequences in library", idx), UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 453, "", 1); end return null; end endfunction function int unsigned uvm_sequence_library::select_sequence(int unsigned max); static int unsigned counter; select_sequence = counter; counter++; if (counter >= max) counter = 0; endfunction function void uvm_sequence_library::init_sequence_library(); foreach (this_type::m_typewide_sequences[i]) sequences.push_back(this_type::m_typewide_sequences[i]); endfunction function bit uvm_sequence_library::m_static_check(uvm_object_wrapper seq_type); if (!m_check(seq_type,null)) return 0; foreach (m_typewide_sequences[i]) if (m_typewide_sequences[i] == seq_type) return 0; return 1; endfunction function bit uvm_sequence_library::m_dyn_check(uvm_object_wrapper seq_type); if (!m_check(seq_type,this)) return 0; foreach (sequences[i]) if (sequences[i] == seq_type) return 0; return 1; endfunction function bit uvm_sequence_library::m_check(uvm_object_wrapper seq_type, this_type lib); uvm_object obj; uvm_sequence_base seq; uvm_root top; uvm_coreservice_t cs; string name; string typ; obj = seq_type.create_object(); name = (lib == null) ? type_name() : lib.get_full_name(); typ = (lib == null) ? type_name() : lib.get_type_name(); cs = uvm_coreservice_t::get(); top = cs.get_root(); if (!$cast(seq, obj)) begin begin if (top.uvm_report_enabled(UVM_NONE,UVM_ERROR,"SEQLIB/BAD_SEQ_TYPE")) top.uvm_report_error ("SEQLIB/BAD_SEQ_TYPE", {"Object '",obj.get_type_name(), "' is not a sequence. Cannot add to sequence library '",name, "'"}, UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 538, "", 1); end return 0; end return 1; endfunction function void uvm_sequence_library::pre_randomize(); m_get_config(); endfunction function void uvm_sequence_library::m_get_config(); uvm_sequence_library_cfg cfg; string phase_name; uvm_phase starting_phase = get_starting_phase(); if (starting_phase != null) begin phase_name = {starting_phase.get_name(),"_phase"}; end if (uvm_config_db #(uvm_sequence_library_cfg)::get(m_sequencer, phase_name, "default_sequence.config", cfg) ) begin selection_mode = cfg.selection_mode; min_random_count = cfg.min_random_count; max_random_count = cfg.max_random_count; end else begin void'(uvm_config_db #(int unsigned)::get(m_sequencer, phase_name, "default_sequence.min_random_count", min_random_count) ); void'(uvm_config_db #(int unsigned)::get(m_sequencer, phase_name, "default_sequence.max_random_count", max_random_count) ); void'(uvm_config_db #(uvm_sequence_lib_mode)::get(m_sequencer, phase_name, "default_sequence.selection_mode", selection_mode) ); end if (max_random_count == 0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"SEQLIB/MAX_ZERO")) uvm_report_warning ("SEQLIB/MAX_ZERO", $sformatf("max_random_count (%0d) zero. Nothing will be done.", max_random_count), UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 593, "", 1); end if (min_random_count > max_random_count) min_random_count = max_random_count; end else if (min_random_count > max_random_count) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"SEQLIB/MIN_GT_MAX")) uvm_report_error ("SEQLIB/MIN_GT_MAX", $sformatf("min_random_count (%0d) greater than max_random_count (%0d). Setting min to max.", min_random_count,max_random_count), UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 600, "", 1); end min_random_count = max_random_count; end else begin if (selection_mode == UVM_SEQ_LIB_ITEM) begin uvm_sequencer #(REQ,RSP) seqr; uvm_object_wrapper lhs = REQ::get_type(); uvm_object_wrapper rhs = uvm_sequence_item::get_type(); if (lhs == rhs) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"SEQLIB/BASE_ITEM")) uvm_report_error ("SEQLIB/BASE_ITEM", {"selection_mode cannot be UVM_SEQ_LIB_ITEM when ", "the REQ type is the base uvm_sequence_item. Using UVM_SEQ_LIB_RAND mode"}, UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 610, "", 1); end selection_mode = UVM_SEQ_LIB_RAND; end if (m_sequencer == null || !$cast(seqr,m_sequencer)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"SEQLIB/VIRT_SEQ")) uvm_report_error ("SEQLIB/VIRT_SEQ", {"selection_mode cannot be UVM_SEQ_LIB_ITEM when ", "running as a virtual sequence. Using UVM_SEQ_LIB_RAND mode"}, UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 615, "", 1); end selection_mode = UVM_SEQ_LIB_RAND; end end end endfunction task uvm_sequence_library::body(); uvm_object_wrapper wrap; uvm_phase starting_phase = get_starting_phase(); if (m_sequencer == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"SEQLIB/VIRT_SEQ")) uvm_report_fatal ("SEQLIB/VIRT_SEQ", {"Sequence library 'm_sequencer' handle is null ", " no current support for running as a virtual sequence."}, UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 634, "", 1); end return; end if (sequences.size() == 0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"SEQLIB/NOSEQS")) uvm_report_error ("SEQLIB/NOSEQS", "Sequence library does not contain any sequences. Did you forget to call init_sequence_library() in the constructor?", UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 639, "", 1); end return; end if (!get_randomize_enabled()) m_get_config(); m_safe_raise_starting_phase({"starting sequence library ",get_full_name()," (", get_type_name(),")"}); begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,"SEQLIB/START")) uvm_report_info ("SEQLIB/START", $sformatf("Starting sequence library %s in %s phase: %0d iterations in mode %s", get_type_name(), (starting_phase != null ? starting_phase.get_name() : "unknown"), sequence_count, selection_mode.name()), UVM_LOW, "t/uvm/src/seq/uvm_sequence_library.svh", 652, "", 1); end begin if (uvm_report_enabled(UVM_FULL,UVM_INFO,"SEQLIB/SPRINT")) uvm_report_info ("SEQLIB/SPRINT", {"\n",sprint(uvm_table_printer::get_default())}, UVM_FULL, "t/uvm/src/seq/uvm_sequence_library.svh", 654, "", 1); end case (selection_mode) UVM_SEQ_LIB_RAND: begin valid_rand_selection.constraint_mode(1); valid_sequence_count.constraint_mode(0); for (int i=1; i<=sequence_count; i++) begin if (!randomize(select_rand)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"SEQLIB/RAND_FAIL")) uvm_report_error ("SEQLIB/RAND_FAIL", "Random sequence selection failed", UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 663, "", 1); end break; end else begin wrap = sequences[select_rand]; end execute(wrap); end valid_rand_selection.constraint_mode(0); valid_sequence_count.constraint_mode(1); end UVM_SEQ_LIB_RANDC: begin uvm_object_wrapper q[$]; valid_randc_selection.constraint_mode(1); valid_sequence_count.constraint_mode(0); for (int i=1; i<=sequence_count; i++) begin if (!randomize(select_randc)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"SEQLIB/RANDC_FAIL")) uvm_report_error ("SEQLIB/RANDC_FAIL", "Random sequence selection failed", UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 681, "", 1); end break; end else begin wrap = sequences[select_randc]; end q.push_back(wrap); end valid_randc_selection.constraint_mode(0); valid_sequence_count.constraint_mode(1); foreach(q[i]) execute(q[i]); valid_randc_selection.constraint_mode(0); valid_sequence_count.constraint_mode(1); end UVM_SEQ_LIB_ITEM: begin for (int i=1; i<=sequence_count; i++) begin wrap = REQ::get_type(); execute(wrap); end end UVM_SEQ_LIB_USER: begin for (int i=1; i<=sequence_count; i++) begin int user_selection; user_selection = select_sequence(sequences.size()-1); if (user_selection >= sequences.size()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"SEQLIB/USER_FAIL")) uvm_report_error ("SEQLIB/USER_FAIL", "User sequence selection out of range", UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 709, "", 1); end wrap = REQ::get_type(); end else begin wrap = sequences[user_selection]; end execute(wrap); end end default: begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"SEQLIB/RAND_MODE")) uvm_report_fatal ("SEQLIB/RAND_MODE", $sformatf("Unknown random sequence selection mode: %0d",selection_mode), UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 721, "", 1); end end endcase begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,"SEQLIB/END")) uvm_report_info ("SEQLIB/END", {"Ending sequence library in phase ", (starting_phase != null ? starting_phase.get_name() : "unknown")}, UVM_LOW, "t/uvm/src/seq/uvm_sequence_library.svh", 726, "", 1); end begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"SEQLIB/DSTRB")) uvm_report_info ("SEQLIB/DSTRB", $sformatf("%p",seqs_distrib), UVM_HIGH, "t/uvm/src/seq/uvm_sequence_library.svh", 728, "", 1); end m_safe_drop_starting_phase({"starting sequence library ",get_full_name()," (", get_type_name(),")"}); endtask task uvm_sequence_library::execute(uvm_object_wrapper wrap); uvm_object obj; uvm_sequence_item seq_or_item; uvm_sequence_base seq_base; REQ req_item; uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); obj = factory.create_object_by_type(wrap,get_full_name(), $sformatf("%s:%0d",wrap.get_type_name(),sequences_executed+1)); if (!$cast(seq_base, obj)) begin if (!$cast(req_item, obj)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"SEQLIB/WRONG_ITEM_TYPE")) uvm_report_error ("SEQLIB/WRONG_ITEM_TYPE", {"The item created by '", get_full_name(), "' when in 'UVM_SEQ_LIB_ITEM' mode doesn't match the REQ type which was passed in to the uvm_sequence_library#(REQ[,RSP]), this can happen if the REQ type which was passed in was a pure-virtual type. Either configure the factory overrides to properly generate items for this sequence library, or do not execute this sequence library in UVM_SEQ_LIB_ITEM mode."}, UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 756, "", 1); end return; end end void'($cast(seq_or_item,obj)); begin if (uvm_report_enabled(UVM_FULL,UVM_INFO,"SEQLIB/EXEC")) uvm_report_info ("SEQLIB/EXEC", {"Executing ",(seq_or_item.is_item() ? "item " : "sequence "),seq_or_item.get_name(), " (",seq_or_item.get_type_name(),")"}, UVM_FULL, "t/uvm/src/seq/uvm_sequence_library.svh", 764, "", 1); end seq_or_item.print_sequence_info = 1; begin uvm_sequence_base __seq; if ( seq_or_item.is_item() ) begin start_item(seq_or_item, -1); if ( ! seq_or_item.randomize() with {} ) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RNDFLD")) uvm_report_warning ("RNDFLD", "Randomization failed in uvm_rand_send action", UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 766, "", 1); end end finish_item(seq_or_item, -1); end else if ( $cast( __seq, seq_or_item ) ) begin __seq.set_item_context(this,seq_or_item.get_sequencer()); if ( __seq.get_randomize_enabled() ) begin if ( ! seq_or_item.randomize() with {} ) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RNDFLD")) uvm_report_warning ("RNDFLD", "Randomization failed in uvm_rand_send action", UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 766, "", 1); end end end __seq.start(__seq.get_sequencer(), this, -1, 0); end else begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"NOT_SEQ_OR_ITEM")) uvm_report_warning ("NOT_SEQ_OR_ITEM", "Object passed uvm_rand_send appears to be neither a sequence or item.", UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 766, "", 1); end end end seqs_distrib[seq_or_item.get_type_name()] = seqs_distrib[seq_or_item.get_type_name()]+1; sequences_executed++; endtask function void uvm_sequence_library::do_print(uvm_printer printer); printer.print_field_int("min_random_count",min_random_count,32,UVM_DEC,,"int unsigned"); printer.print_field_int("max_random_count",max_random_count,32,UVM_DEC,,"int unsigned"); printer.print_generic("selection_mode","uvm_sequence_lib_mode",32,selection_mode.name()); printer.print_field_int("sequence_count",sequence_count,32,UVM_DEC,,"int unsigned"); printer.print_array_header("typewide_sequences",m_typewide_sequences.size(),"queue_object_types"); foreach (m_typewide_sequences[i]) printer.print_generic($sformatf("[%0d]",i),"uvm_object_wrapper","-",m_typewide_sequences[i].get_type_name()); printer.print_array_footer(); printer.print_array_header("sequences",sequences.size(),"queue_object_types"); foreach (sequences[i]) printer.print_generic($sformatf("[%0d]",i),"uvm_object_wrapper","-",sequences[i].get_type_name()); printer.print_array_footer(); printer.print_array_header("seqs_distrib",seqs_distrib.num(),"as_int_string"); foreach (seqs_distrib[typ]) begin printer.print_field_int({"[",typ,"]"},seqs_distrib[typ],32,,UVM_DEC,"int unsigned"); end printer.print_array_footer(); endfunction typedef uvm_sequence #(uvm_sequence_item, uvm_sequence_item) uvm_default_sequence_type; typedef uvm_sequencer #(uvm_sequence_item, uvm_sequence_item) uvm_default_sequencer_type; typedef uvm_driver #(uvm_sequence_item, uvm_sequence_item) uvm_default_driver_type; typedef uvm_sequencer_param_base #(uvm_sequence_item, uvm_sequence_item) uvm_default_sequencer_param_type; `define UVM_TLM_NB_FW_MASK (1<<0) `define UVM_TLM_NB_BW_MASK (1<<1) `define UVM_TLM_B_MASK (1<<2) class uvm_time; static local real m_resolution = 1.0e-12; local real m_res; local time m_time; local string m_name; static function void set_time_resolution(real res); m_resolution = res; endfunction function new(string name = "uvm_tlm_time", real res = 0); m_name = name; m_res = (res == 0) ? m_resolution : res; reset(); endfunction function string get_name(); return m_name; endfunction function void reset(); m_time = 0; endfunction local function real to_m_res(real t, time scaled, real secs); return t/real'(scaled) * (secs/m_res); endfunction function real get_realtime(time scaled, real secs = 1.0e-9); return m_time*real'(scaled) * m_res/secs; endfunction function void incr(real t, time scaled, real secs = 1.0e-9); if (t < 0.0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/TIMENEG")) uvm_report_error ("UVM/TLM/TIMENEG", {"Cannot increment uvm_tlm_time variable ", m_name, " by a negative value"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm_time.svh", 134, "", 1); end return; end if (scaled == 0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"UVM/TLM/BADSCALE")) uvm_report_fatal ("UVM/TLM/BADSCALE", "uvm_tlm_time::incr() called with a scaled time literal that is smaller than the current timescale", UVM_NONE, "t/uvm/src/tlm2/uvm_tlm_time.svh", 139, "", 1); end end m_time += to_m_res(t, scaled, secs); endfunction function void decr(real t, time scaled, real secs); if (t < 0.0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/TIMENEG")) uvm_report_error ("UVM/TLM/TIMENEG", {"Cannot decrement uvm_tlm_time variable ", m_name, " by a negative value"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm_time.svh", 161, "", 1); end return; end if (scaled == 0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"UVM/TLM/BADSCALE")) uvm_report_fatal ("UVM/TLM/BADSCALE", "uvm_tlm_time::decr() called with a scaled time literal that is smaller than the current timescale", UVM_NONE, "t/uvm/src/tlm2/uvm_tlm_time.svh", 166, "", 1); end end m_time -= to_m_res(t, scaled, secs); if (m_time < 0.0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/TOODECR")) uvm_report_error ("UVM/TLM/TOODECR", {"Cannot decrement uvm_tlm_time variable ", m_name, " to a negative value"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm_time.svh", 172, "", 1); end reset(); end endfunction function real get_abstime(real secs); return m_time*m_res/secs; endfunction function void set_abstime(real t, real secs); m_time = t*secs/m_res; endfunction endclass typedef uvm_time uvm_tlm_time; typedef enum { UVM_TLM_READ_COMMAND, UVM_TLM_WRITE_COMMAND, UVM_TLM_IGNORE_COMMAND } uvm_tlm_command_e; typedef enum { UVM_TLM_OK_RESPONSE = 1, UVM_TLM_INCOMPLETE_RESPONSE = 0, UVM_TLM_GENERIC_ERROR_RESPONSE = -1, UVM_TLM_ADDRESS_ERROR_RESPONSE = -2, UVM_TLM_COMMAND_ERROR_RESPONSE = -3, UVM_TLM_BURST_ERROR_RESPONSE = -4, UVM_TLM_BYTE_ENABLE_ERROR_RESPONSE = -5 } uvm_tlm_response_status_e; typedef class uvm_tlm_extension_base; class uvm_tlm_generic_payload extends uvm_sequence_item; rand bit [63:0] m_address; rand uvm_tlm_command_e m_command; rand byte unsigned m_data[]; rand int unsigned m_length; rand uvm_tlm_response_status_e m_response_status; bit m_dmi; rand byte unsigned m_byte_enable[]; rand int unsigned m_byte_enable_length; rand int unsigned m_streaming_width; protected uvm_tlm_extension_base m_extensions [uvm_tlm_extension_base]; local rand uvm_tlm_extension_base m_rand_exts[]; typedef uvm_object_registry#(uvm_tlm_generic_payload,"uvm_tlm_generic_payload") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_tlm_generic_payload tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_tlm_generic_payload"; endfunction : type_name virtual function string get_type_name(); return "uvm_tlm_generic_payload"; endfunction : get_type_name function new(string name=""); super.new(name); m_address = 0; m_command = UVM_TLM_IGNORE_COMMAND; m_length = 0; m_response_status = UVM_TLM_INCOMPLETE_RESPONSE; m_dmi = 0; m_byte_enable_length = 0; m_streaming_width = 0; endfunction function void do_print(uvm_printer printer); byte unsigned be; super.do_print(printer); printer.print_field_int ("address", m_address, 64, UVM_HEX); printer.print_generic ("command", "uvm_tlm_command_e", 32, m_command.name()); printer.print_generic ("response_status", "uvm_tlm_response_status_e", 32, m_response_status.name()); printer.print_field_int ("streaming_width", m_streaming_width, 32, UVM_HEX); printer.print_array_header("data", m_length, "darray(byte)"); for (int i=0; i < m_length && i < m_data.size(); i++) begin if (m_byte_enable_length) begin be = m_byte_enable[i % m_byte_enable_length]; printer.print_generic ($sformatf("[%0d]",i), "byte", 8, $sformatf("'h%h%s",m_data[i],((be=='hFF) ? "" : " x"))); end else printer.print_generic ($sformatf("[%0d]",i), "byte", 8, $sformatf("'h%h",m_data[i])); end printer.print_array_footer(); begin string name; printer.print_array_header("extensions", m_extensions.num(), "aa(obj,obj)"); foreach (m_extensions[ext_]) begin uvm_tlm_extension_base ext = m_extensions[ext_]; name = {"[",ext.get_name(),"]"}; printer.print_object(name, ext, "["); end printer.print_array_footer(); end endfunction function void do_copy(uvm_object rhs); uvm_tlm_generic_payload gp; super.do_copy(rhs); $cast(gp, rhs); m_address = gp.m_address; m_command = gp.m_command; m_data = gp.m_data; m_dmi = gp.m_dmi; m_length = gp.m_length; m_response_status = gp.m_response_status; m_byte_enable = gp.m_byte_enable; m_streaming_width = gp.m_streaming_width; m_byte_enable_length = gp.m_byte_enable_length; m_extensions.delete(); foreach (gp.m_extensions[ext]) $cast(m_extensions[ext], gp.m_extensions[ext].clone()); endfunction `define m_uvm_tlm_fast_compare_int(VALUE,RADIX,NAME="") \ if ( (!comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold())) && \ ((VALUE) != (gp.VALUE)) ) begin \ string name = (NAME == "") ? `"VALUE`" : NAME; \ void'(comparer.compare_field_int(name , VALUE, gp.VALUE, $bits(VALUE), RADIX)); \ end `define m_uvm_tlm_fast_compare_enum(VALUE,TYPE,NAME="") \ if ( (!comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold())) && \ ((VALUE) != (gp.VALUE)) ) begin \ string name = (NAME == "") ? `"VALUE`" : NAME; \ void'( comparer.compare_string(name, \ $sformatf("%s'(%s)", `"TYPE`", VALUE.name()), \ $sformatf("%s'(%s)", `"TYPE`", gp.VALUE.name())) ); \ end function bit do_compare(uvm_object rhs, uvm_comparer comparer); uvm_tlm_generic_payload gp; do_compare = super.do_compare(rhs, comparer); $cast(gp, rhs); if ( (!comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold())) && ((m_address) != (gp.m_address)) ) begin string name = ("" == "") ? "m_address" : ""; void'(comparer.compare_field_int(name , m_address, gp.m_address, $bits(m_address), UVM_HEX)); end if ( (!comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold())) && ((m_command) != (gp.m_command)) ) begin string name = ("" == "") ? "m_command" : ""; void'( comparer.compare_string(name, $sformatf("%s'(%s)", "uvm_tlm_command_e", m_command.name()), $sformatf("%s'(%s)", "uvm_tlm_command_e", gp.m_command.name())) ); end if ( (!comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold())) && ((m_length) != (gp.m_length)) ) begin string name = ("" == "") ? "m_length" : ""; void'(comparer.compare_field_int(name , m_length, gp.m_length, $bits(m_length), UVM_UNSIGNED)); end if ( (!comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold())) && ((m_dmi) != (gp.m_dmi)) ) begin string name = ("" == "") ? "m_dmi" : ""; void'(comparer.compare_field_int(name , m_dmi, gp.m_dmi, $bits(m_dmi), UVM_BIN)); end if ( (!comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold())) && ((m_byte_enable_length) != (gp.m_byte_enable_length)) ) begin string name = ("" == "") ? "m_byte_enable_length" : ""; void'(comparer.compare_field_int(name , m_byte_enable_length, gp.m_byte_enable_length, $bits(m_byte_enable_length), UVM_UNSIGNED)); end if ( (!comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold())) && ((m_response_status) != (gp.m_response_status)) ) begin string name = ("" == "") ? "m_response_status" : ""; void'( comparer.compare_string(name, $sformatf("%s'(%s)", "uvm_tlm_response_status_e", m_response_status.name()), $sformatf("%s'(%s)", "uvm_tlm_response_status_e", gp.m_response_status.name())) ); end if ( (!comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold())) && ((m_streaming_width) != (gp.m_streaming_width)) ) begin string name = ("" == "") ? "m_streaming_width" : ""; void'(comparer.compare_field_int(name , m_streaming_width, gp.m_streaming_width, $bits(m_streaming_width), UVM_UNSIGNED)); end if ( (!comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold())) && m_byte_enable_length == gp.m_byte_enable_length ) begin for (int i=0; i < m_byte_enable_length && i < m_byte_enable.size(); i++) begin if ( (!comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold())) && ((m_byte_enable[i]) != (gp.m_byte_enable[i])) ) begin string name = ($sformatf("m_byte_enable[%0d]", i) == "") ? "m_byte_enable[i]" : $sformatf("m_byte_enable[%0d]", i); void'(comparer.compare_field_int(name , m_byte_enable[i], gp.m_byte_enable[i], $bits(m_byte_enable[i]), UVM_HEX)); end end end if ( (!comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold())) && m_length == gp.m_length ) begin byte unsigned be; for (int i=0; i < m_length && i < m_data.size(); i++) begin if (m_byte_enable_length) begin be = m_byte_enable[i % m_byte_enable_length]; end else begin be = 8'hFF; end if ( (!comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold())) && ((m_data[i] & be) != (gp.m_data[i] & be)) ) begin string name = ($sformatf("m_data[%0d] & %0x", i, be) == "") ? "m_data[i] & be" : $sformatf("m_data[%0d] & %0x", i, be); void'(comparer.compare_field_int(name , m_data[i] & be, gp.m_data[i] & be, $bits(m_data[i] & be), UVM_HEX)); end end end if ( !comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold()) ) foreach (m_extensions[ext_]) begin uvm_tlm_extension_base ext = ext_; uvm_tlm_extension_base rhs_ext = gp.m_extensions.exists(ext) ? gp.m_extensions[ext] : null; void'(comparer.compare_object(ext.get_name(), m_extensions[ext], rhs_ext)); if ( !comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold()) ) break; end if (comparer.get_result()) begin string msg = $sformatf("GP miscompare between '%s' and '%s':\nlhs = %s\nrhs = %s", get_full_name(), gp.get_full_name(), this.convert2string(), gp.convert2string()); comparer.print_msg(msg); end return (comparer.get_result() == 0); endfunction `undef m_uvm_tlm_fast_compare_int `undef m_uvm_tlm_fast_compare_enum function void do_pack(uvm_packer packer); super.do_pack(packer); if (m_length > m_data.size()) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PACK_DATA_ARR")) uvm_report_fatal ("PACK_DATA_ARR", $sformatf("Data array m_length property (%0d) greater than m_data.size (%0d)", m_length,m_data.size()), UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_generic_payload.svh", 562, "", 1); end if (m_byte_enable_length > m_byte_enable.size()) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PACK_DATA_ARR")) uvm_report_fatal ("PACK_DATA_ARR", $sformatf("Data array m_byte_enable_length property (%0d) greater than m_byte_enable.size (%0d)", m_byte_enable_length,m_byte_enable.size()), UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_generic_payload.svh", 566, "", 1); end begin bit __array[]; { << bit { __array}} = m_address; __array = new [64] (__array); packer.pack_bits(__array, 64); end begin bit __array[]; { << bit { __array}} = m_command; __array = new [32] (__array); packer.pack_bits(__array, 32); end begin bit __array[]; { << bit { __array}} = m_length; __array = new [32] (__array); packer.pack_bits(__array, 32); end begin bit __array[]; { << bit { __array}} = m_dmi; __array = new [1] (__array); packer.pack_bits(__array, 1); end for (int i=0; i 64) recorder.record_field("address", m_address, $bits(m_address), UVM_NORADIX); else recorder.record_field_int("address", m_address, $bits(m_address), UVM_NORADIX); end if (recorder != null && recorder.is_open()) begin if (recorder.use_record_attribute()) recorder.record_generic("command", $sformatf("%p", m_command.name())); else recorder.record_string("command",m_command.name()); end if (recorder != null && recorder.is_open()) begin if (recorder.use_record_attribute()) recorder.record_generic("data_length", $sformatf("%p", m_length)); else if ($bits(m_length) > 64) recorder.record_field("data_length", m_length, $bits(m_length), UVM_NORADIX); else recorder.record_field_int("data_length", m_length, $bits(m_length), UVM_NORADIX); end if (recorder != null && recorder.is_open()) begin if (recorder.use_record_attribute()) recorder.record_generic("byte_enable_length", $sformatf("%p", m_byte_enable_length)); else if ($bits(m_byte_enable_length) > 64) recorder.record_field("byte_enable_length", m_byte_enable_length, $bits(m_byte_enable_length), UVM_NORADIX); else recorder.record_field_int("byte_enable_length", m_byte_enable_length, $bits(m_byte_enable_length), UVM_NORADIX); end if (recorder != null && recorder.is_open()) begin if (recorder.use_record_attribute()) recorder.record_generic("response_status", $sformatf("%p", m_response_status.name())); else recorder.record_string("response_status",m_response_status.name()); end if (recorder != null && recorder.is_open()) begin if (recorder.use_record_attribute()) recorder.record_generic("streaming_width", $sformatf("%p", m_streaming_width)); else if ($bits(m_streaming_width) > 64) recorder.record_field("streaming_width", m_streaming_width, $bits(m_streaming_width), UVM_NORADIX); else recorder.record_field_int("streaming_width", m_streaming_width, $bits(m_streaming_width), UVM_NORADIX); end for (int i=0; i < m_length; i++) if (recorder != null && recorder.is_open()) begin if (recorder.use_record_attribute()) recorder.record_generic($sformatf("\\data[%0d] ", i), $sformatf("%p", m_data[i])); else if ($bits(m_data[i]) > 64) recorder.record_field($sformatf("\\data[%0d] ", i), m_data[i], $bits(m_data[i]), UVM_NORADIX); else recorder.record_field_int($sformatf("\\data[%0d] ", i), m_data[i], $bits(m_data[i]), UVM_NORADIX); end for (int i=0; i < m_byte_enable_length; i++) if (recorder != null && recorder.is_open()) begin if (recorder.use_record_attribute()) recorder.record_generic($sformatf("\\byte_en[%0d] ", i), $sformatf("%p", m_byte_enable[i])); else if ($bits(m_byte_enable[i]) > 64) recorder.record_field($sformatf("\\byte_en[%0d] ", i), m_byte_enable[i], $bits(m_byte_enable[i]), UVM_NORADIX); else recorder.record_field_int($sformatf("\\byte_en[%0d] ", i), m_byte_enable[i], $bits(m_byte_enable[i]), UVM_NORADIX); end foreach (m_extensions[ext]) recorder.record_object(ext.get_name(),m_extensions[ext]); endfunction function string convert2string(); string msg; string s; $sformat(msg, "%s %s [0x%16x] =", super.convert2string(), m_command.name(), m_address); for(int unsigned i = 0; i < m_length; i++) begin if (!m_byte_enable_length || (m_byte_enable[i % m_byte_enable_length] == 'hFF)) $sformat(s, " %02x", m_data[i]); else $sformat(s, " --"); msg = { msg , s }; end msg = { msg, " (status=", get_response_string(), ")" }; return msg; endfunction virtual function uvm_tlm_command_e get_command(); return m_command; endfunction virtual function void set_command(uvm_tlm_command_e command); m_command = command; endfunction virtual function bit is_read(); return (m_command == UVM_TLM_READ_COMMAND); endfunction virtual function void set_read(); set_command(UVM_TLM_READ_COMMAND); endfunction virtual function bit is_write(); return (m_command == UVM_TLM_WRITE_COMMAND); endfunction virtual function void set_write(); set_command(UVM_TLM_WRITE_COMMAND); endfunction virtual function void set_address(bit [63:0] addr); m_address = addr; endfunction virtual function bit [63:0] get_address(); return m_address; endfunction virtual function void get_data (output byte unsigned p []); p = m_data; endfunction virtual function void set_data(ref byte unsigned p []); m_data = p; endfunction virtual function int unsigned get_data_length(); return m_length; endfunction virtual function void set_data_length(int unsigned length); m_length = length; endfunction virtual function int unsigned get_streaming_width(); return m_streaming_width; endfunction virtual function void set_streaming_width(int unsigned width); m_streaming_width = width; endfunction virtual function void get_byte_enable(output byte unsigned p[]); p = m_byte_enable; endfunction virtual function void set_byte_enable(ref byte unsigned p[]); m_byte_enable = p; endfunction virtual function int unsigned get_byte_enable_length(); return m_byte_enable_length; endfunction virtual function void set_byte_enable_length(int unsigned length); m_byte_enable_length = length; endfunction virtual function void set_dmi_allowed(bit dmi); m_dmi = dmi; endfunction virtual function bit is_dmi_allowed(); return m_dmi; endfunction virtual function uvm_tlm_response_status_e get_response_status(); return m_response_status; endfunction virtual function void set_response_status(uvm_tlm_response_status_e status); m_response_status = status; endfunction virtual function bit is_response_ok(); return (int'(m_response_status) > 0); endfunction virtual function bit is_response_error(); return !is_response_ok(); endfunction virtual function string get_response_string(); case(m_response_status) UVM_TLM_OK_RESPONSE : return "OK"; UVM_TLM_INCOMPLETE_RESPONSE : return "INCOMPLETE"; UVM_TLM_GENERIC_ERROR_RESPONSE : return "GENERIC_ERROR"; UVM_TLM_ADDRESS_ERROR_RESPONSE : return "ADDRESS_ERROR"; UVM_TLM_COMMAND_ERROR_RESPONSE : return "COMMAND_ERROR"; UVM_TLM_BURST_ERROR_RESPONSE : return "BURST_ERROR"; UVM_TLM_BYTE_ENABLE_ERROR_RESPONSE : return "BYTE_ENABLE_ERROR"; endcase return "UNKNOWN_RESPONSE"; endfunction function uvm_tlm_extension_base set_extension(uvm_tlm_extension_base ext); uvm_tlm_extension_base ext_handle = ext.get_type_handle(); if(!m_extensions.exists(ext_handle)) set_extension = null; else set_extension = m_extensions[ext_handle]; m_extensions[ext_handle] = ext; endfunction function int get_num_extensions(); return m_extensions.num(); endfunction: get_num_extensions function uvm_tlm_extension_base get_extension(uvm_tlm_extension_base ext_handle); if(!m_extensions.exists(ext_handle)) return null; return m_extensions[ext_handle]; endfunction function void clear_extension(uvm_tlm_extension_base ext_handle); if(m_extensions.exists(ext_handle)) m_extensions.delete(ext_handle); else begin if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"GP_EXT")) uvm_report_info ("GP_EXT", $sformatf("Unable to find extension to clear"), UVM_MEDIUM, "t/uvm/src/tlm2/uvm_tlm2_generic_payload.svh", 965, "", 1); end endfunction function void clear_extensions(); m_extensions.delete(); endfunction function void pre_randomize(); int i; m_rand_exts = new [m_extensions.num()]; foreach (m_extensions[ext_]) begin uvm_tlm_extension_base ext = ext_; m_rand_exts[i++] = m_extensions[ext]; end endfunction function void post_randomize(); m_rand_exts.delete(); endfunction endclass typedef uvm_tlm_generic_payload uvm_tlm_gp; virtual class uvm_tlm_extension_base extends uvm_object; function new(string name = ""); super.new(name); endfunction pure virtual function uvm_tlm_extension_base get_type_handle(); pure virtual function string get_type_handle_name(); virtual function void do_copy(uvm_object rhs); super.do_copy(rhs); endfunction virtual function uvm_object create (string name=""); return null; endfunction endclass class uvm_tlm_extension #(type T=int) extends uvm_tlm_extension_base; typedef uvm_tlm_extension#(T) this_type; local static this_type m_my_tlm_ext_type = ID(); function new(string name=""); super.new(name); endfunction static function this_type ID(); if (m_my_tlm_ext_type == null) m_my_tlm_ext_type = new(); return m_my_tlm_ext_type; endfunction virtual function uvm_tlm_extension_base get_type_handle(); return ID(); endfunction virtual function string get_type_handle_name(); return $typename(T); endfunction virtual function uvm_object create (string name=""); return null; endfunction endclass typedef class uvm_time; typedef enum { UNINITIALIZED_PHASE, BEGIN_REQ, END_REQ, BEGIN_RESP, END_RESP } uvm_tlm_phase_e; typedef enum { UVM_TLM_ACCEPTED, UVM_TLM_UPDATED, UVM_TLM_COMPLETED } uvm_tlm_sync_e; `define UVM_TLM_TASK_ERROR "TLM-2 interface task not implemented" `define UVM_TLM_FUNCTION_ERROR "UVM TLM 2 interface function not implemented" class uvm_tlm_if #(type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e); virtual function uvm_tlm_sync_e nb_transport_fw(T t, ref P p, input uvm_tlm_time delay); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"nb_transport_fw")) uvm_report_error ("nb_transport_fw", "UVM TLM 2 interface function not implemented", UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_ifs.svh", 115, "", 1); end return UVM_TLM_ACCEPTED; endfunction virtual function uvm_tlm_sync_e nb_transport_bw(T t, ref P p, input uvm_tlm_time delay); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"nb_transport_bw")) uvm_report_error ("nb_transport_bw", "UVM TLM 2 interface function not implemented", UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_ifs.svh", 158, "", 1); end return UVM_TLM_ACCEPTED; endfunction virtual task b_transport(T t, uvm_tlm_time delay); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"b_transport")) uvm_report_error ("b_transport", "TLM-2 interface task not implemented", UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_ifs.svh", 182, "", 1); end endtask endclass `define UVM_TLM_NB_TRANSPORT_FW_IMP(imp, T, P, t, p, delay) \ function uvm_tlm_sync_e nb_transport_fw(T t, ref P p, input uvm_tlm_time delay); \ if (delay == null) begin \ `uvm_error("UVM/TLM/NULLDELAY", \ {get_full_name(), \ ".nb_transport_fw() called with 'null' delay"}) \ return UVM_TLM_COMPLETED; \ end \ return imp.nb_transport_fw(t, p, delay); \ endfunction `define UVM_TLM_NB_TRANSPORT_BW_IMP(imp, T, P, t, p, delay) \ function uvm_tlm_sync_e nb_transport_bw(T t, ref P p, input uvm_tlm_time delay); \ if (delay == null) begin \ `uvm_error("UVM/TLM/NULLDELAY", \ {get_full_name(), \ ".nb_transport_bw() called with 'null' delay"}) \ return UVM_TLM_COMPLETED; \ end \ return imp.nb_transport_bw(t, p, delay); \ endfunction `define UVM_TLM_B_TRANSPORT_IMP(imp, T, t, delay) \ task b_transport(T t, uvm_tlm_time delay); \ if (delay == null) begin \ `uvm_error("UVM/TLM/NULLDELAY", \ {get_full_name(), \ ".b_transport() called with 'null' delay"}) \ return; \ end \ imp.b_transport(t, delay); \ endtask class uvm_tlm_b_transport_imp #(type T=uvm_tlm_generic_payload, type IMP=int) extends uvm_port_base #(uvm_tlm_if #(T)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = (1<<2); endfunction virtual function string get_type_name(); return "uvm_tlm_b_transport_imp"; endfunction task b_transport(T t, uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".b_transport() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_imps.svh", 173, "", 1); end return; end m_imp.b_transport(t, delay); endtask endclass class uvm_tlm_nb_transport_fw_imp #(type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e, type IMP=int) extends uvm_port_base #(uvm_tlm_if #(T,P)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = (1<<0); endfunction virtual function string get_type_name(); return "uvm_tlm_nb_transport_fw_imp"; endfunction function uvm_tlm_sync_e nb_transport_fw(T t, ref P p, input uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".nb_transport_fw() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_imps.svh", 190, "", 1); end return UVM_TLM_COMPLETED; end return m_imp.nb_transport_fw(t, p, delay); endfunction endclass class uvm_tlm_nb_transport_bw_imp #(type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e, type IMP=int) extends uvm_port_base #(uvm_tlm_if #(T,P)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = (1<<1); endfunction virtual function string get_type_name(); return "uvm_tlm_nb_transport_bw_imp"; endfunction function uvm_tlm_sync_e nb_transport_bw(T t, ref P p, input uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".nb_transport_bw() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_imps.svh", 207, "", 1); end return UVM_TLM_COMPLETED; end return m_imp.nb_transport_bw(t, p, delay); endfunction endclass class uvm_tlm_b_transport_port #(type T=uvm_tlm_generic_payload) extends uvm_port_base #(uvm_tlm_if #(T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (1<<2); endfunction virtual function string get_type_name(); return "uvm_tlm_b_transport_port"; endfunction task b_transport(T t, uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".b_transport() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_ports.svh", 41, "", 1); end return; end this.m_if.b_transport(t, delay); endtask endclass class uvm_tlm_nb_transport_fw_port #(type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e) extends uvm_port_base #(uvm_tlm_if #(T,P)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (1<<0); endfunction virtual function string get_type_name(); return "uvm_tlm_nb_transport_fw_port"; endfunction function uvm_tlm_sync_e nb_transport_fw(T t, ref P p, input uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".nb_transport_fw() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_ports.svh", 59, "", 1); end return UVM_TLM_COMPLETED; end return this.m_if.nb_transport_fw(t, p, delay); endfunction endclass class uvm_tlm_nb_transport_bw_port #(type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e) extends uvm_port_base #(uvm_tlm_if #(T,P)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (1<<1); endfunction virtual function string get_type_name(); return "uvm_tlm_nb_transport_bw_port"; endfunction function uvm_tlm_sync_e nb_transport_bw(T t, ref P p, input uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".nb_transport_bw() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_ports.svh", 78, "", 1); end return UVM_TLM_COMPLETED; end return this.m_if.nb_transport_bw(t, p, delay); endfunction endclass class uvm_tlm_b_transport_export #(type T=uvm_tlm_generic_payload) extends uvm_port_base #(uvm_tlm_if #(T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (1<<2); endfunction virtual function string get_type_name(); return "uvm_tlm_b_transport_export"; endfunction task b_transport(T t, uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".b_transport() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_exports.svh", 39, "", 1); end return; end this.m_if.b_transport(t, delay); endtask endclass class uvm_tlm_nb_transport_fw_export #(type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e) extends uvm_port_base #(uvm_tlm_if #(T,P)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (1<<0); endfunction virtual function string get_type_name(); return "uvm_tlm_nb_transport_fw_export"; endfunction function uvm_tlm_sync_e nb_transport_fw(T t, ref P p, input uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".nb_transport_fw() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_exports.svh", 53, "", 1); end return UVM_TLM_COMPLETED; end return this.m_if.nb_transport_fw(t, p, delay); endfunction endclass class uvm_tlm_nb_transport_bw_export #(type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e) extends uvm_port_base #(uvm_tlm_if #(T,P)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (1<<1); endfunction virtual function string get_type_name(); return "uvm_tlm_nb_transport_bw_export"; endfunction function uvm_tlm_sync_e nb_transport_bw(T t, ref P p, input uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".nb_transport_bw() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_exports.svh", 68, "", 1); end return UVM_TLM_COMPLETED; end return this.m_if.nb_transport_bw(t, p, delay); endfunction endclass virtual class uvm_tlm_b_target_socket_base #(type T=uvm_tlm_generic_payload) extends uvm_port_base #(uvm_tlm_if #(T)); function new (string name, uvm_component parent); super.new (name, parent, UVM_IMPLEMENTATION, 1, 1); m_if_mask = (1<<2); endfunction virtual function string get_type_name(); return "uvm_tlm_b_target_socket"; endfunction endclass virtual class uvm_tlm_b_initiator_socket_base #(type T=uvm_tlm_generic_payload) extends uvm_port_base #(uvm_tlm_if #(T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (1<<2); endfunction virtual function string get_type_name(); return "uvm_tlm_b_initiator_socket"; endfunction task b_transport(T t, uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".b_transport() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets_base.svh", 77, "", 1); end return; end this.m_if.b_transport(t, delay); endtask endclass virtual class uvm_tlm_nb_target_socket_base #(type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e) extends uvm_port_base #(uvm_tlm_if #(T,P)); uvm_tlm_nb_transport_bw_port #(T,P) bw_port; function new (string name, uvm_component parent); super.new (name, parent, UVM_IMPLEMENTATION, 1, 1); m_if_mask = (1<<0); endfunction virtual function string get_type_name(); return "uvm_tlm_nb_target_socket"; endfunction function uvm_tlm_sync_e nb_transport_bw(T t, ref P p, input uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".nb_transport_bw() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets_base.svh", 102, "", 1); end return UVM_TLM_COMPLETED; end return bw_port.nb_transport_bw(t, p, delay); endfunction endclass virtual class uvm_tlm_nb_initiator_socket_base #(type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e) extends uvm_port_base #(uvm_tlm_if #(T,P)); function new (string name, uvm_component parent); super.new (name, parent, UVM_PORT, 1, 1); m_if_mask = (1<<0); endfunction virtual function string get_type_name(); return "uvm_tlm_nb_initiator_socket"; endfunction function uvm_tlm_sync_e nb_transport_fw(T t, ref P p, input uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".nb_transport_fw() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets_base.svh", 125, "", 1); end return UVM_TLM_COMPLETED; end return this.m_if.nb_transport_fw(t, p, delay); endfunction endclass virtual class uvm_tlm_nb_passthrough_initiator_socket_base #(type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e) extends uvm_port_base #(uvm_tlm_if #(T,P)); uvm_tlm_nb_transport_bw_export #(T,P) bw_export; function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (1<<0); bw_export = new("bw_export", get_comp()); endfunction virtual function string get_type_name(); return "uvm_tlm_nb_passthrough_initiator_socket"; endfunction function uvm_tlm_sync_e nb_transport_fw(T t, ref P p, input uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".nb_transport_fw() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets_base.svh", 155, "", 1); end return UVM_TLM_COMPLETED; end return this.m_if.nb_transport_fw(t, p, delay); endfunction function uvm_tlm_sync_e nb_transport_bw(T t, ref P p, input uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".nb_transport_bw() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets_base.svh", 156, "", 1); end return UVM_TLM_COMPLETED; end return bw_export.nb_transport_bw(t, p, delay); endfunction endclass virtual class uvm_tlm_nb_passthrough_target_socket_base #(type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e) extends uvm_port_base #(uvm_tlm_if #(T,P)); uvm_tlm_nb_transport_bw_port #(T,P) bw_port; function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (1<<0); bw_port = new("bw_port", get_comp()); endfunction virtual function string get_type_name(); return "uvm_tlm_nb_passthrough_target_socket"; endfunction function uvm_tlm_sync_e nb_transport_fw(T t, ref P p, input uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".nb_transport_fw() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets_base.svh", 183, "", 1); end return UVM_TLM_COMPLETED; end return this.m_if.nb_transport_fw(t, p, delay); endfunction function uvm_tlm_sync_e nb_transport_bw(T t, ref P p, input uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".nb_transport_bw() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets_base.svh", 184, "", 1); end return UVM_TLM_COMPLETED; end return bw_port.nb_transport_bw(t, p, delay); endfunction endclass virtual class uvm_tlm_b_passthrough_initiator_socket_base #(type T=uvm_tlm_generic_payload) extends uvm_port_base #(uvm_tlm_if #(T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (1<<2); endfunction virtual function string get_type_name(); return "uvm_tlm_b_passthrough_initiator_socket"; endfunction task b_transport(T t, uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".b_transport() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets_base.svh", 200, "", 1); end return; end this.m_if.b_transport(t, delay); endtask endclass virtual class uvm_tlm_b_passthrough_target_socket_base #(type T=uvm_tlm_generic_payload) extends uvm_port_base #(uvm_tlm_if #(T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (1<<2); endfunction virtual function string get_type_name(); return "uvm_tlm_b_passthrough_target_socket"; endfunction task b_transport(T t, uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".b_transport() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets_base.svh", 217, "", 1); end return; end this.m_if.b_transport(t, delay); endtask endclass class uvm_tlm_b_initiator_socket #(type T=uvm_tlm_generic_payload) extends uvm_tlm_b_initiator_socket_base #(T); function new(string name, uvm_component parent); super.new(name, parent); endfunction function void connect(this_type provider); uvm_tlm_b_passthrough_initiator_socket_base #(T) initiator_pt_socket; uvm_tlm_b_passthrough_target_socket_base #(T) target_pt_socket; uvm_tlm_b_target_socket_base #(T) target_socket; uvm_component c; super.connect(provider); if($cast(initiator_pt_socket, provider) || $cast(target_pt_socket, provider) || $cast(target_socket, provider)) return; c = get_comp(); begin if (c.uvm_report_enabled(UVM_NONE,UVM_ERROR,get_type_name())) c.uvm_report_error (get_type_name(), "type mismatch in connect -- connection cannot be completed", UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets.svh", 87, "", 1); end endfunction endclass class uvm_tlm_b_target_socket #(type IMP=int, type T=uvm_tlm_generic_payload) extends uvm_tlm_b_target_socket_base #(T); local IMP m_imp; function new (string name, uvm_component parent, IMP imp = null); super.new (name, parent); if (imp == null) $cast(m_imp, parent); else m_imp = imp; if (m_imp == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM2/NOIMP")) uvm_report_error ("UVM/TLM2/NOIMP", {"b_target socket ", name, " has no implementation"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets.svh", 121, "", 1); end endfunction function void connect(this_type provider); uvm_component c; super.connect(provider); c = get_comp(); begin if (c.uvm_report_enabled(UVM_NONE,UVM_ERROR,get_type_name())) c.uvm_report_error (get_type_name(), "You cannot call connect() on a target termination socket", UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets.svh", 134, "", 1); end endfunction task b_transport(T t, uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".b_transport() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets.svh", 137, "", 1); end return; end m_imp.b_transport(t, delay); endtask endclass class uvm_tlm_nb_initiator_socket #(type IMP=int, type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e) extends uvm_tlm_nb_initiator_socket_base #(T,P); uvm_tlm_nb_transport_bw_imp #(T,P,IMP) bw_imp; function new(string name, uvm_component parent, IMP imp = null); super.new (name, parent); if (imp == null) $cast(imp, parent); if (imp == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM2/NOIMP")) uvm_report_error ("UVM/TLM2/NOIMP", {"nb_initiator socket ", name, " has no implementation"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets.svh", 168, "", 1); end bw_imp = new("bw_imp", imp); endfunction function void connect(this_type provider); uvm_tlm_nb_passthrough_initiator_socket_base #(T,P) initiator_pt_socket; uvm_tlm_nb_passthrough_target_socket_base #(T,P) target_pt_socket; uvm_tlm_nb_target_socket_base #(T,P) target_socket; uvm_component c; super.connect(provider); if($cast(initiator_pt_socket, provider)) begin initiator_pt_socket.bw_export.connect(bw_imp); return; end if($cast(target_pt_socket, provider)) begin target_pt_socket.bw_port.connect(bw_imp); return; end if($cast(target_socket, provider)) begin target_socket.bw_port.connect(bw_imp); return; end c = get_comp(); begin if (c.uvm_report_enabled(UVM_NONE,UVM_ERROR,get_type_name())) c.uvm_report_error (get_type_name(), "type mismatch in connect -- connection cannot be completed", UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets.svh", 200, "", 1); end endfunction endclass class uvm_tlm_nb_target_socket #(type IMP=int, type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e) extends uvm_tlm_nb_target_socket_base #(T,P); local IMP m_imp; function new (string name, uvm_component parent, IMP imp = null); super.new (name, parent); if (imp == null) $cast(m_imp, parent); else m_imp = imp; bw_port = new("bw_port", get_comp()); if (m_imp == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM2/NOIMP")) uvm_report_error ("UVM/TLM2/NOIMP", {"nb_target socket ", name, " has no implementation"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets.svh", 236, "", 1); end endfunction function void connect(this_type provider); uvm_component c; super.connect(provider); c = get_comp(); begin if (c.uvm_report_enabled(UVM_NONE,UVM_ERROR,get_type_name())) c.uvm_report_error (get_type_name(), "You cannot call connect() on a target termination socket", UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets.svh", 249, "", 1); end endfunction function uvm_tlm_sync_e nb_transport_fw(T t, ref P p, input uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".nb_transport_fw() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets.svh", 252, "", 1); end return UVM_TLM_COMPLETED; end return m_imp.nb_transport_fw(t, p, delay); endfunction endclass class uvm_tlm_b_passthrough_initiator_socket #(type T=uvm_tlm_generic_payload) extends uvm_tlm_b_passthrough_initiator_socket_base #(T); function new(string name, uvm_component parent); super.new(name, parent); endfunction function void connect(this_type provider); uvm_tlm_b_passthrough_initiator_socket_base #(T) initiator_pt_socket; uvm_tlm_b_passthrough_target_socket_base #(T) target_pt_socket; uvm_tlm_b_target_socket_base #(T) target_socket; uvm_component c; super.connect(provider); if($cast(initiator_pt_socket, provider) || $cast(target_pt_socket, provider) || $cast(target_socket, provider)) return; c = get_comp(); begin if (c.uvm_report_enabled(UVM_NONE,UVM_ERROR,get_type_name())) c.uvm_report_error (get_type_name(), "type mismatch in connect -- connection cannot be completed", UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets.svh", 290, "", 1); end endfunction endclass class uvm_tlm_b_passthrough_target_socket #(type T=uvm_tlm_generic_payload) extends uvm_tlm_b_passthrough_target_socket_base #(T); function new(string name, uvm_component parent); super.new(name, parent); endfunction function void connect(this_type provider); uvm_tlm_b_passthrough_target_socket_base #(T) target_pt_socket; uvm_tlm_b_target_socket_base #(T) target_socket; uvm_component c; super.connect(provider); if($cast(target_pt_socket, provider) || $cast(target_socket, provider)) return; c = get_comp(); begin if (c.uvm_report_enabled(UVM_NONE,UVM_ERROR,get_type_name())) c.uvm_report_error (get_type_name(), "type mismatch in connect -- connection cannot be completed", UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets.svh", 323, "", 1); end endfunction endclass class uvm_tlm_nb_passthrough_initiator_socket #(type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e) extends uvm_tlm_nb_passthrough_initiator_socket_base #(T,P); function new(string name, uvm_component parent); super.new(name, parent); endfunction function void connect(this_type provider); uvm_tlm_nb_passthrough_initiator_socket_base #(T,P) initiator_pt_socket; uvm_tlm_nb_passthrough_target_socket_base #(T,P) target_pt_socket; uvm_tlm_nb_target_socket_base #(T,P) target_socket; uvm_component c; super.connect(provider); if($cast(initiator_pt_socket, provider)) begin bw_export.connect(initiator_pt_socket.bw_export); return; end if($cast(target_pt_socket, provider)) begin target_pt_socket.bw_port.connect(bw_export); return; end if($cast(target_socket, provider)) begin target_socket.bw_port.connect(bw_export); return; end c = get_comp(); begin if (c.uvm_report_enabled(UVM_NONE,UVM_ERROR,get_type_name())) c.uvm_report_error (get_type_name(), "type mismatch in connect -- connection cannot be completed", UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets.svh", 375, "", 1); end endfunction endclass class uvm_tlm_nb_passthrough_target_socket #(type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e) extends uvm_tlm_nb_passthrough_target_socket_base #(T,P); function new(string name, uvm_component parent); super.new(name, parent); endfunction function void connect(this_type provider); uvm_tlm_nb_passthrough_target_socket_base #(T,P) target_pt_socket; uvm_tlm_nb_target_socket_base #(T,P) target_socket; uvm_component c; super.connect(provider); if($cast(target_pt_socket, provider)) begin target_pt_socket.bw_port.connect(bw_port); return; end if($cast(target_socket, provider)) begin target_socket.bw_port.connect(bw_port); return; end c = get_comp(); begin if (c.uvm_report_enabled(UVM_NONE,UVM_ERROR,get_type_name())) c.uvm_report_error (get_type_name(), "type mismatch in connect -- connection cannot be completed", UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets.svh", 419, "", 1); end endfunction endclass `define UVM_REG_MODEL__SV typedef class uvm_reg_field; typedef class uvm_vreg_field; typedef class uvm_reg; typedef class uvm_reg_file; typedef class uvm_vreg; typedef class uvm_reg_block; typedef class uvm_mem; typedef class uvm_reg_item; typedef class uvm_reg_map; typedef class uvm_reg_map_info; typedef class uvm_reg_sequence; typedef class uvm_reg_adapter; typedef class uvm_reg_indirect_data; typedef bit unsigned [64-1:0] uvm_reg_data_t ; typedef logic unsigned [64-1:0] uvm_reg_data_logic_t ; typedef bit unsigned [64-1:0] uvm_reg_addr_t ; typedef logic unsigned [64-1:0] uvm_reg_addr_logic_t ; typedef bit unsigned [((64-1)/8+1)-1:0] uvm_reg_byte_en_t ; typedef bit [32-1:0] uvm_reg_cvr_t ; typedef struct { string path; int offset; int size; } uvm_hdl_path_slice; typedef uvm_resource_db#(uvm_reg_cvr_t) uvm_reg_cvr_rsrc_db; typedef enum { UVM_IS_OK, UVM_NOT_OK, UVM_HAS_X } uvm_status_e; typedef enum { UVM_FRONTDOOR, UVM_BACKDOOR, UVM_PREDICT, UVM_DEFAULT_DOOR } uvm_door_e; typedef enum { UVM_NO_CHECK, UVM_CHECK } uvm_check_e; typedef enum { UVM_NO_ENDIAN, UVM_LITTLE_ENDIAN, UVM_BIG_ENDIAN, UVM_LITTLE_FIFO, UVM_BIG_FIFO } uvm_endianness_e; typedef enum { UVM_REG, UVM_FIELD, UVM_MEM } uvm_elem_kind_e; typedef enum { UVM_READ, UVM_WRITE, UVM_BURST_READ, UVM_BURST_WRITE } uvm_access_e; typedef enum { UVM_NO_HIER, UVM_HIER } uvm_hier_e; typedef enum { UVM_PREDICT_DIRECT, UVM_PREDICT_READ, UVM_PREDICT_WRITE } uvm_predict_e; typedef enum uvm_reg_cvr_t { UVM_NO_COVERAGE = 'h0000, UVM_CVR_REG_BITS = 'h0001, UVM_CVR_ADDR_MAP = 'h0002, UVM_CVR_FIELD_VALS = 'h0004, UVM_CVR_ALL = -1 } uvm_coverage_model_e; typedef enum bit [63:0] { UVM_DO_REG_HW_RESET = 64'h0000_0000_0000_0001, UVM_DO_REG_BIT_BASH = 64'h0000_0000_0000_0002, UVM_DO_REG_ACCESS = 64'h0000_0000_0000_0004, UVM_DO_MEM_ACCESS = 64'h0000_0000_0000_0008, UVM_DO_SHARED_ACCESS = 64'h0000_0000_0000_0010, UVM_DO_MEM_WALK = 64'h0000_0000_0000_0020, UVM_DO_ALL_REG_MEM_TESTS = 64'hffff_ffff_ffff_ffff } uvm_reg_mem_tests_e; class uvm_hdl_path_concat; uvm_hdl_path_slice slices[]; function void set(uvm_hdl_path_slice t[]); slices = t; endfunction function void add_slice(uvm_hdl_path_slice slice); slices = new [slices.size()+1] (slices); slices[slices.size()-1] = slice; endfunction function void add_path(string path, int unsigned offset = -1, int unsigned size = -1); uvm_hdl_path_slice t; t.offset = offset; t.path = path; t.size = size; add_slice(t); endfunction endclass function automatic string uvm_hdl_concat2string(uvm_hdl_path_concat concat); string image = "{"; if (concat.slices.size() == 1 && concat.slices[0].offset == -1 && concat.slices[0].size == -1) return concat.slices[0].path; foreach (concat.slices[i]) begin uvm_hdl_path_slice slice=concat.slices[i]; image = { image, (i == 0) ? "" : ", ", slice.path }; if (slice.offset >= 0) image = { image, "@", $sformatf("[%0d +: %0d]", slice.offset, slice.size) }; end image = { image, "}" }; return image; endfunction typedef struct packed { uvm_reg_addr_t min; uvm_reg_addr_t max; int unsigned stride; } uvm_reg_map_addr_range; class uvm_reg_item extends uvm_sequence_item; typedef uvm_object_registry#(uvm_reg_item,"uvm_reg_item") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_reg_item tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_reg_item"; endfunction : type_name virtual function string get_type_name(); return "uvm_reg_item"; endfunction : get_type_name uvm_elem_kind_e element_kind; uvm_object element; rand uvm_access_e kind; rand uvm_reg_data_t value[]; constraint max_values { value.size() > 0 && value.size() < 1000; } rand uvm_reg_addr_t offset; uvm_status_e status; uvm_reg_map local_map; uvm_reg_map map; uvm_door_e path; rand uvm_sequence_base parent; int prior = -1; rand uvm_object extension; string bd_kind; string fname; int lineno; function new(string name=""); super.new(name); value = new[1]; endfunction virtual function string convert2string(); string s,value_s; s = {"kind=",kind.name(), " ele_kind=",element_kind.name(), " ele_name=",element==null?"null":element.get_full_name() }; if (value.size() > 1 && uvm_report_enabled(UVM_HIGH, UVM_INFO, "RegModel")) begin value_s = "'{"; foreach (value[i]) value_s = {value_s,$sformatf("%0h,",value[i])}; value_s[value_s.len()-1]="}"; end else value_s = $sformatf("%0h",value[0]); s = {s, " value=",value_s}; if (element_kind == UVM_MEM) s = {s, $sformatf(" offset=%0h",offset)}; s = {s," map=",(map==null?"null":map.get_full_name())," path=",path.name()}; s = {s," status=",status.name()}; return s; endfunction virtual function void do_copy(uvm_object rhs); uvm_reg_item rhs_; if (rhs == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"REG/NULL")) uvm_report_fatal ("REG/NULL", "do_copy: rhs argument is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_item.svh", 215, "", 1); end if (!$cast(rhs_,rhs)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"WRONG_TYPE")) uvm_report_error ("WRONG_TYPE", "Provided rhs is not of type uvm_reg_item", UVM_NONE, "t/uvm/src/reg/uvm_reg_item.svh", 218, "", 1); end return; end super.do_copy(rhs); element_kind = rhs_.element_kind; element = rhs_.element; kind = rhs_.kind; value = rhs_.value; offset = rhs_.offset; status = rhs_.status; local_map = rhs_.local_map; map = rhs_.map; path = rhs_.path; extension = rhs_.extension; bd_kind = rhs_.bd_kind; parent = rhs_.parent; prior = rhs_.prior; fname = rhs_.fname; lineno = rhs_.lineno; endfunction endclass typedef struct { uvm_access_e kind; uvm_reg_addr_t addr; uvm_reg_data_t data; int n_bits; uvm_reg_byte_en_t byte_en; uvm_status_e status; } uvm_reg_bus_op; virtual class uvm_reg_adapter extends uvm_object; typedef uvm_abstract_object_registry#(uvm_reg_adapter,"uvm_reg_adapter") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_reg_adapter"; endfunction : type_name virtual function string get_type_name(); return "uvm_reg_adapter"; endfunction : get_type_name function new(string name=""); super.new(name); endfunction bit supports_byte_enable; bit provides_responses; uvm_sequence_base parent_sequence; pure virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); pure virtual function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw); local uvm_reg_item m_item; virtual function uvm_reg_item get_item(); return m_item; endfunction virtual function void m_set_item(uvm_reg_item item); m_item = item; endfunction endclass class uvm_reg_tlm_adapter extends uvm_reg_adapter; typedef uvm_object_registry#(uvm_reg_tlm_adapter,"uvm_reg_tlm_adapter") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_reg_tlm_adapter tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_reg_tlm_adapter"; endfunction : type_name virtual function string get_type_name(); return "uvm_reg_tlm_adapter"; endfunction : get_type_name function new(string name = "uvm_reg_tlm_adapter"); super.new(name); endfunction virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); uvm_tlm_gp gp = uvm_tlm_gp::type_id::create("tlm_gp",, this.get_full_name()); int nbytes = (rw.n_bits-1)/8+1; uvm_reg_addr_t addr=rw.addr; if (rw.kind == UVM_WRITE) gp.set_command(UVM_TLM_WRITE_COMMAND); else gp.set_command(UVM_TLM_READ_COMMAND); gp.set_address(addr); gp.m_byte_enable = new [nbytes]; gp.m_byte_enable_length = nbytes; gp.set_streaming_width (nbytes); gp.m_data = new [gp.get_streaming_width()]; gp.m_length = nbytes; for (int i = 0; i < nbytes; i++) begin gp.m_data[i] = rw.data[i*8+:8]; gp.m_byte_enable[i] = (i > nbytes) ? 8'h00 : (rw.byte_en[i] ? 8'hFF : 8'h00); end return gp; endfunction virtual function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw); uvm_tlm_gp gp; int nbytes; if (bus_item == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"REG/NULL_ITEM")) uvm_report_fatal ("REG/NULL_ITEM", "bus2reg: bus_item argument is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_adapter.svh", 228, "", 1); end if (!$cast(gp,bus_item)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"WRONG_TYPE")) uvm_report_error ("WRONG_TYPE", "Provided bus_item is not of type uvm_tlm_gp", UVM_NONE, "t/uvm/src/reg/uvm_reg_adapter.svh", 231, "", 1); end return; end if (gp.get_command() == UVM_TLM_WRITE_COMMAND) rw.kind = UVM_WRITE; else rw.kind = UVM_READ; rw.addr = gp.get_address(); rw.byte_en = 0; foreach (gp.m_byte_enable[i]) rw.byte_en[i] = gp.m_byte_enable[i]; rw.data = 0; foreach (gp.m_data[i]) rw.data[i*8+:8] = gp.m_data[i]; rw.status = (gp.is_response_ok()) ? UVM_IS_OK : UVM_NOT_OK; endfunction endclass class uvm_predict_s; bit addr[uvm_reg_addr_t]; uvm_reg_item reg_item; endclass class uvm_reg_predictor #(type BUSTYPE=int) extends uvm_component; typedef uvm_component_registry #(uvm_reg_predictor#(BUSTYPE)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction uvm_analysis_imp #(BUSTYPE, uvm_reg_predictor #(BUSTYPE)) bus_in; uvm_analysis_port #(uvm_reg_item) reg_ap; uvm_reg_map map; uvm_reg_adapter adapter; function new (string name, uvm_component parent); super.new(name, parent); bus_in = new("bus_in", this); reg_ap = new("reg_ap", this); endfunction static function string type_name(); static string m_type_name; if (m_type_name == "") begin BUSTYPE t; t = BUSTYPE::type_id::create("t"); m_type_name = {"uvm_reg_predictor #(", t.get_type_name(), ")"}; end return m_type_name; endfunction virtual function string get_type_name(); return type_name(); endfunction : get_type_name virtual function void pre_predict(uvm_reg_item rw); endfunction local uvm_predict_s m_pending[uvm_reg]; virtual function void write(BUSTYPE tr); uvm_reg rg; uvm_reg_bus_op rw; if (adapter == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"REG/WRITE/NULL")) uvm_report_fatal ("REG/WRITE/NULL", "write: adapter handle is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_predictor.svh", 160, "", 1); end rw.byte_en = -1; adapter.bus2reg(tr,rw); rg = map.get_reg_by_offset(rw.addr, (rw.kind == UVM_READ)); if (rg != null) begin bit found; uvm_reg_item reg_item; uvm_reg_map local_map; uvm_reg_map_info map_info; uvm_predict_s predict_info; uvm_reg_indirect_data ireg; uvm_reg ir; if (!m_pending.exists(rg)) begin uvm_reg_item item = new; predict_info =new; item.element_kind = UVM_REG; item.element = rg; item.path = UVM_PREDICT; item.map = map; item.kind = rw.kind; predict_info.reg_item = item; m_pending[rg] = predict_info; end predict_info = m_pending[rg]; reg_item = predict_info.reg_item; if (predict_info.addr.exists(rw.addr)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"REG_PREDICT_COLLISION")) uvm_report_error ("REG_PREDICT_COLLISION", {"Collision detected for register '", rg.get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_predictor.svh", 194, "", 1); end m_pending.delete(rg); end local_map = rg.get_local_map(map); map_info = local_map.get_reg_map_info(rg); ir=($cast(ireg, rg))?ireg.get_indirect_reg():rg; foreach (map_info.addr[i]) begin if (rw.addr == map_info.addr[i]) begin found = 1; reg_item.value[0] |= rw.data << (i * map.get_n_bytes()*8); predict_info.addr[rw.addr] = 1; if (predict_info.addr.num() == map_info.addr.size()) begin uvm_predict_e predict_kind = (reg_item.kind == UVM_WRITE) ? UVM_PREDICT_WRITE : UVM_PREDICT_READ; if (reg_item.kind == UVM_READ && local_map.get_check_on_read() && reg_item.status != UVM_NOT_OK) begin void'(rg.do_check(ir.get_mirrored_value(), reg_item.value[0], local_map)); end pre_predict(reg_item); ir.XsampleX(reg_item.value[0], rw.byte_en, reg_item.kind == UVM_READ, local_map); begin uvm_reg_block blk = rg.get_parent(); blk.XsampleX(map_info.offset, reg_item.kind == UVM_READ, local_map); end rg.do_predict(reg_item, predict_kind, rw.byte_en); if(reg_item.kind == UVM_WRITE) begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"REG_PREDICT")) uvm_report_info ("REG_PREDICT", {"Observed WRITE transaction to register ", ir.get_full_name(), ": value='h", $sformatf("%0h",reg_item.value[0]), " : updated value = 'h", $sformatf("%0h",ir.get())}, UVM_HIGH, "t/uvm/src/reg/uvm_reg_predictor.svh", 235, "", 1); end else begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"REG_PREDICT")) uvm_report_info ("REG_PREDICT", {"Observed READ transaction to register ", ir.get_full_name(), ": value='h", $sformatf("%0h",reg_item.value[0])}, UVM_HIGH, "t/uvm/src/reg/uvm_reg_predictor.svh", 239, "", 1); end reg_ap.write(reg_item); m_pending.delete(rg); end break; end end if (!found) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"REG_PREDICT_INTERNAL")) uvm_report_error ("REG_PREDICT_INTERNAL", {"Unexpected failed address lookup for register '", rg.get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_predictor.svh", 248, "", 1); end end else begin begin if (uvm_report_enabled(UVM_FULL,UVM_INFO,"REG_PREDICT_NOT_FOR_ME")) uvm_report_info ("REG_PREDICT_NOT_FOR_ME", {"Observed transaction does not target a register: ", $sformatf("%p",tr)}, UVM_FULL, "t/uvm/src/reg/uvm_reg_predictor.svh", 253, "", 1); end end endfunction virtual function void check_phase(uvm_phase phase); string q[$]; super.check_phase(phase); foreach (m_pending[l]) begin uvm_reg rg=l; q.push_back($sformatf("\n%s",rg.get_full_name())); end if (m_pending.num() > 0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"PENDING REG ITEMS")) uvm_report_error ("PENDING REG ITEMS", $sformatf("There are %0d incomplete register transactions still pending completion:%s",m_pending.num(),uvm_pkg::m_uvm_string_queue_join(q)), UVM_NONE, "t/uvm/src/reg/uvm_reg_predictor.svh", 274, "", 1); end end endfunction endclass class uvm_reg_sequence #(type BASE=uvm_sequence #(uvm_reg_item)) extends BASE; typedef uvm_object_registry #(uvm_reg_sequence #(BASE)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_reg_sequence #(BASE) tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction uvm_reg_block model; uvm_reg_adapter adapter; uvm_sequencer #(uvm_reg_item) reg_seqr; function new (string name="uvm_reg_sequence_inst"); super.new(name); endfunction virtual task body(); if (m_sequencer == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"NO_SEQR")) uvm_report_fatal ("NO_SEQR", {"Sequence executing as translation sequence, ", "but is not associated with a sequencer (m_sequencer == null)"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_sequence.svh", 127, "", 1); end end if (reg_seqr == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"REG_XLATE_NO_SEQR")) uvm_report_warning ("REG_XLATE_NO_SEQR", {"Executing RegModel translation sequence on sequencer ", m_sequencer.get_full_name(),"' does not have an upstream sequencer defined. ", "Execution of register items available only via direct calls to 'do_reg_item'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_sequence.svh", 133, "", 1); end wait(0); end begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,"REG_XLATE_SEQ_START")) uvm_report_info ("REG_XLATE_SEQ_START", {"Starting RegModel translation sequence on sequencer ", m_sequencer.get_full_name(),"'"}, UVM_LOW, "t/uvm/src/reg/uvm_reg_sequence.svh", 138, "", 1); end forever begin uvm_reg_item reg_item; reg_seqr.peek(reg_item); do_reg_item(reg_item); reg_seqr.get(reg_item); #0; end endtask typedef enum { LOCAL, UPSTREAM } seq_parent_e; seq_parent_e parent_select = LOCAL; uvm_sequence_base upstream_parent; virtual task do_reg_item(uvm_reg_item rw); string rws=rw.convert2string(); if (m_sequencer == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"REG/DO_ITEM/NULL")) uvm_report_fatal ("REG/DO_ITEM/NULL", "do_reg_item: m_sequencer is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_sequence.svh", 161, "", 1); end if (adapter == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"REG/DO_ITEM/NULL")) uvm_report_fatal ("REG/DO_ITEM/NULL", "do_reg_item: adapter handle is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_sequence.svh", 163, "", 1); end begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"DO_RW_ACCESS")) uvm_report_info ("DO_RW_ACCESS", {"Doing transaction: ",rws}, UVM_HIGH, "t/uvm/src/reg/uvm_reg_sequence.svh", 165, "", 1); end if (parent_select == LOCAL) begin upstream_parent = rw.parent; rw.parent = this; end if (rw.kind == UVM_WRITE) rw.local_map.do_bus_write(rw, m_sequencer, adapter); else rw.local_map.do_bus_read(rw, m_sequencer, adapter); if (parent_select == LOCAL) rw.parent = upstream_parent; endtask virtual task write_reg(input uvm_reg rg, output uvm_status_e status, input uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); if (rg == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"NO_REG")) uvm_report_error ("NO_REG", "Register argument is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_sequence.svh", 211, "", 1); end else rg.write(status,value,path,map,this,prior,extension,fname,lineno); endtask virtual task read_reg(input uvm_reg rg, output uvm_status_e status, output uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); if (rg == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"NO_REG")) uvm_report_error ("NO_REG", "Register argument is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_sequence.svh", 229, "", 1); end else rg.read(status,value,path,map,this,prior,extension,fname,lineno); endtask virtual task poke_reg(input uvm_reg rg, output uvm_status_e status, input uvm_reg_data_t value, input string kind = "", input uvm_object extension = null, input string fname = "", input int lineno = 0); if (rg == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"NO_REG")) uvm_report_error ("NO_REG", "Register argument is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_sequence.svh", 246, "", 1); end else rg.poke(status,value,kind,this,extension,fname,lineno); endtask virtual task peek_reg(input uvm_reg rg, output uvm_status_e status, output uvm_reg_data_t value, input string kind = "", input uvm_object extension = null, input string fname = "", input int lineno = 0); if (rg == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"NO_REG")) uvm_report_error ("NO_REG", "Register argument is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_sequence.svh", 263, "", 1); end else rg.peek(status,value,kind,this,extension,fname,lineno); endtask virtual task update_reg(input uvm_reg rg, output uvm_status_e status, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); if (rg == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"NO_REG")) uvm_report_error ("NO_REG", "Register argument is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_sequence.svh", 281, "", 1); end else rg.update(status,path,map,this,prior,extension,fname,lineno); endtask virtual task mirror_reg(input uvm_reg rg, output uvm_status_e status, input uvm_check_e check = UVM_NO_CHECK, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); if (rg == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"NO_REG")) uvm_report_error ("NO_REG", "Register argument is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_sequence.svh", 300, "", 1); end else rg.mirror(status,check,path,map,this,prior,extension,fname,lineno); endtask virtual task write_mem(input uvm_mem mem, output uvm_status_e status, input uvm_reg_addr_t offset, input uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); if (mem == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"NO_MEM")) uvm_report_error ("NO_MEM", "Memory argument is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_sequence.svh", 320, "", 1); end else mem.write(status,offset,value,path,map,this,prior,extension,fname,lineno); endtask virtual task read_mem(input uvm_mem mem, output uvm_status_e status, input uvm_reg_addr_t offset, output uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); if (mem == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"NO_MEM")) uvm_report_error ("NO_MEM", "Memory argument is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_sequence.svh", 339, "", 1); end else mem.read(status,offset,value,path,map,this,prior,extension,fname,lineno); endtask virtual task poke_mem(input uvm_mem mem, output uvm_status_e status, input uvm_reg_addr_t offset, input uvm_reg_data_t value, input string kind = "", input uvm_object extension = null, input string fname = "", input int lineno = 0); if (mem == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"NO_MEM")) uvm_report_error ("NO_MEM", "Memory argument is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_sequence.svh", 357, "", 1); end else mem.poke(status,offset,value,kind,this,extension,fname,lineno); endtask virtual task peek_mem(input uvm_mem mem, output uvm_status_e status, input uvm_reg_addr_t offset, output uvm_reg_data_t value, input string kind = "", input uvm_object extension = null, input string fname = "", input int lineno = 0); if (mem == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"NO_MEM")) uvm_report_error ("NO_MEM", "Memory argument is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_sequence.svh", 375, "", 1); end else mem.peek(status,offset,value,kind,this,extension,fname,lineno); endtask virtual function void put_response(uvm_sequence_item response_item); put_base_response(response_item); endfunction endclass virtual class uvm_reg_frontdoor extends uvm_reg_sequence #(uvm_sequence #(uvm_sequence_item)); typedef uvm_abstract_object_registry#(uvm_reg_frontdoor,"uvm_reg_frontdoor") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_reg_frontdoor"; endfunction : type_name virtual function string get_type_name(); return "uvm_reg_frontdoor"; endfunction : get_type_name uvm_reg_item rw_info; uvm_sequencer_base sequencer; function new(string name=""); super.new(name); endfunction string fname; int lineno; endclass: uvm_reg_frontdoor typedef class uvm_reg; typedef class uvm_mem; typedef class uvm_reg_backdoor; class uvm_reg_cbs extends uvm_callback; typedef uvm_object_registry#(uvm_reg_cbs,"uvm_reg_cbs") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_reg_cbs tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_reg_cbs"; endfunction : type_name virtual function string get_type_name(); return "uvm_reg_cbs"; endfunction : get_type_name function new(string name = "uvm_reg_cbs"); super.new(name); endfunction virtual task pre_write(uvm_reg_item rw); endtask virtual task post_write(uvm_reg_item rw); endtask virtual task pre_read(uvm_reg_item rw); endtask virtual task post_read(uvm_reg_item rw); endtask virtual function void post_predict(input uvm_reg_field fld, input uvm_reg_data_t previous, inout uvm_reg_data_t value, input uvm_predict_e kind, input uvm_door_e path, input uvm_reg_map map); endfunction virtual function void encode(ref uvm_reg_data_t data[]); endfunction virtual function void decode(ref uvm_reg_data_t data[]); endfunction endclass typedef uvm_callbacks#(uvm_reg, uvm_reg_cbs) uvm_reg_cb ; typedef uvm_callback_iter#(uvm_reg, uvm_reg_cbs) uvm_reg_cb_iter ; typedef uvm_callbacks#(uvm_reg_backdoor, uvm_reg_cbs) uvm_reg_bd_cb ; typedef uvm_callback_iter#(uvm_reg_backdoor, uvm_reg_cbs) uvm_reg_bd_cb_iter ; typedef uvm_callbacks#(uvm_mem, uvm_reg_cbs) uvm_mem_cb ; typedef uvm_callback_iter#(uvm_mem, uvm_reg_cbs) uvm_mem_cb_iter ; typedef uvm_callbacks#(uvm_reg_field, uvm_reg_cbs) uvm_reg_field_cb ; typedef uvm_callback_iter#(uvm_reg_field, uvm_reg_cbs) uvm_reg_field_cb_iter ; class uvm_reg_read_only_cbs extends uvm_reg_cbs; function new(string name = "uvm_reg_read_only_cbs"); super.new(name); endfunction typedef uvm_object_registry#(uvm_reg_read_only_cbs,"uvm_reg_read_only_cbs") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_reg_read_only_cbs tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_reg_read_only_cbs"; endfunction : type_name virtual function string get_type_name(); return "uvm_reg_read_only_cbs"; endfunction : get_type_name virtual task pre_write(uvm_reg_item rw); string name = rw.element.get_full_name(); if (rw.status != UVM_IS_OK) return; if (rw.element_kind == UVM_FIELD) begin uvm_reg_field fld; uvm_reg rg; $cast(fld, rw.element); rg = fld.get_parent(); name = rg.get_full_name(); end begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/REG/READONLY")) uvm_report_error ("UVM/REG/READONLY", {name, " is read-only. Cannot call write() method."}, UVM_NONE, "t/uvm/src/reg/uvm_reg_cbs.svh", 232, "", 1); end rw.status = UVM_NOT_OK; endtask local static uvm_reg_read_only_cbs m_me; local static function uvm_reg_read_only_cbs get(); if (m_me == null) m_me = new; return m_me; endfunction static function void add(uvm_reg rg); uvm_reg_field flds[$]; uvm_reg_cb::add(rg, get()); rg.get_fields(flds); foreach (flds[i]) begin uvm_reg_field_cb::add(flds[i], get()); end endfunction static function void remove(uvm_reg rg); uvm_reg_cb_iter cbs = new(rg); uvm_reg_field flds[$]; void'(cbs.first()); while (cbs.get_cb() != get()) begin if (cbs.get_cb() == null) return; void'(cbs.next()); end uvm_reg_cb::delete(rg, get()); rg.get_fields(flds); foreach (flds[i]) begin uvm_reg_field_cb::delete(flds[i], get()); end endfunction endclass class uvm_reg_write_only_cbs extends uvm_reg_cbs; function new(string name = "uvm_reg_write_only_cbs"); super.new(name); endfunction typedef uvm_object_registry#(uvm_reg_write_only_cbs,"uvm_reg_write_only_cbs") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_reg_write_only_cbs tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_reg_write_only_cbs"; endfunction : type_name virtual function string get_type_name(); return "uvm_reg_write_only_cbs"; endfunction : get_type_name virtual task pre_read(uvm_reg_item rw); string name = rw.element.get_full_name(); if (rw.status != UVM_IS_OK) return; if (rw.element_kind == UVM_FIELD) begin uvm_reg_field fld; uvm_reg rg; $cast(fld, rw.element); rg = fld.get_parent(); name = rg.get_full_name(); end begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/REG/WRTEONLY")) uvm_report_error ("UVM/REG/WRTEONLY", {name, " is write-only. Cannot call read() method."}, UVM_NONE, "t/uvm/src/reg/uvm_reg_cbs.svh", 316, "", 1); end rw.status = UVM_NOT_OK; endtask local static uvm_reg_write_only_cbs m_me; local static function uvm_reg_write_only_cbs get(); if (m_me == null) m_me = new; return m_me; endfunction static function void add(uvm_reg rg); uvm_reg_field flds[$]; uvm_reg_cb::add(rg, get()); rg.get_fields(flds); foreach (flds[i]) begin uvm_reg_field_cb::add(flds[i], get()); end endfunction static function void remove(uvm_reg rg); uvm_reg_cb_iter cbs = new(rg); uvm_reg_field flds[$]; void'(cbs.first()); while (cbs.get_cb() != get()) begin if (cbs.get_cb() == null) return; void'(cbs.next()); end uvm_reg_cb::delete(rg, get()); rg.get_fields(flds); foreach (flds[i]) begin uvm_reg_field_cb::delete(flds[i], get()); end endfunction endclass typedef class uvm_reg_cbs; virtual class uvm_reg_backdoor extends uvm_object; typedef uvm_abstract_object_registry#(uvm_reg_backdoor,"uvm_reg_backdoor") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_reg_backdoor"; endfunction : type_name virtual function string get_type_name(); return "uvm_reg_backdoor"; endfunction : get_type_name function new(string name = ""); super.new(name); endfunction: new protected task do_pre_read(uvm_reg_item rw); pre_read(rw); begin uvm_callback_iter#(uvm_reg_backdoor,uvm_reg_cbs) iter = new(this); uvm_reg_cbs cb = iter.first(); while(cb != null) begin cb.pre_read(rw); cb = iter.next(); end end endtask protected task do_post_read(uvm_reg_item rw); uvm_callback_iter#(uvm_reg_backdoor, uvm_reg_cbs) iter = new(this); for(uvm_reg_cbs cb = iter.last(); cb != null; cb=iter.prev()) cb.decode(rw.value); begin uvm_callback_iter#(uvm_reg_backdoor,uvm_reg_cbs) iter = new(this); uvm_reg_cbs cb = iter.first(); while(cb != null) begin cb.post_read(rw); cb = iter.next(); end end post_read(rw); endtask protected task do_pre_write(uvm_reg_item rw); uvm_callback_iter#(uvm_reg_backdoor, uvm_reg_cbs) iter = new(this); pre_write(rw); begin uvm_callback_iter#(uvm_reg_backdoor,uvm_reg_cbs) iter = new(this); uvm_reg_cbs cb = iter.first(); while(cb != null) begin cb.pre_write(rw); cb = iter.next(); end end for(uvm_reg_cbs cb = iter.first(); cb != null; cb = iter.next()) cb.encode(rw.value); endtask protected task do_post_write(uvm_reg_item rw); begin uvm_callback_iter#(uvm_reg_backdoor,uvm_reg_cbs) iter = new(this); uvm_reg_cbs cb = iter.first(); while(cb != null) begin cb.post_write(rw); cb = iter.next(); end end post_write(rw); endtask extern virtual task write(uvm_reg_item rw); extern virtual task read(uvm_reg_item rw); extern virtual function void read_func(uvm_reg_item rw); extern virtual function bit is_auto_updated(uvm_reg_field field); extern virtual local task wait_for_change(uvm_object element); extern function void start_update_thread(uvm_object element); extern function void kill_update_thread(uvm_object element); extern function bit has_update_threads(); virtual task pre_read(uvm_reg_item rw); endtask virtual task post_read(uvm_reg_item rw); endtask virtual task pre_write(uvm_reg_item rw); endtask virtual task post_write(uvm_reg_item rw); endtask string fname; int lineno; local process m_update_thread[uvm_object]; static local bit m_register_cb_uvm_reg_cbs = uvm_callbacks#(uvm_reg_backdoor,uvm_reg_cbs)::m_register_pair("uvm_reg_backdoor","uvm_reg_cbs"); endclass: uvm_reg_backdoor function bit uvm_reg_backdoor::is_auto_updated(uvm_reg_field field); return 0; endfunction task uvm_reg_backdoor::wait_for_change(uvm_object element); begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"RegModel")) uvm_report_fatal ("RegModel", "uvm_reg_backdoor::wait_for_change() method has not been overloaded", UVM_NONE, "t/uvm/src/reg/uvm_reg_backdoor.svh", 171, "", 1); end endtask function void uvm_reg_backdoor::start_update_thread(uvm_object element); uvm_reg rg; if (this.m_update_thread.exists(element)) begin this.kill_update_thread(element); end if (!$cast(rg,element)) return; fork begin uvm_reg_field fields[$]; this.m_update_thread[element] = process::self(); rg.get_fields(fields); forever begin uvm_status_e status; uvm_reg_data_t val; uvm_reg_item r_item = new("bd_r_item"); r_item.element = rg; r_item.element_kind = UVM_REG; this.read(r_item); val = r_item.value[0]; if (r_item.status != UVM_IS_OK) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Backdoor read of register '%s' failed.", rg.get_name()), UVM_NONE, "t/uvm/src/reg/uvm_reg_backdoor.svh", 206, "", 1); end end foreach (fields[i]) begin if (this.is_auto_updated(fields[i])) begin r_item.value[0] = (val >> fields[i].get_lsb_pos()) & ((1 << fields[i].get_n_bits())-1); fields[i].do_predict(r_item); end end this.wait_for_change(element); end end join_none endfunction function void uvm_reg_backdoor::kill_update_thread(uvm_object element); if (this.m_update_thread.exists(element)) begin this.m_update_thread[element].kill(); this.m_update_thread.delete(element); end endfunction function bit uvm_reg_backdoor::has_update_threads(); return this.m_update_thread.num() > 0; endfunction task uvm_reg_backdoor::write(uvm_reg_item rw); begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"RegModel")) uvm_report_fatal ("RegModel", "uvm_reg_backdoor::write() method has not been overloaded", UVM_NONE, "t/uvm/src/reg/uvm_reg_backdoor.svh", 248, "", 1); end endtask task uvm_reg_backdoor::read(uvm_reg_item rw); do_pre_read(rw); read_func(rw); do_post_read(rw); endtask function void uvm_reg_backdoor::read_func(uvm_reg_item rw); begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"RegModel")) uvm_report_fatal ("RegModel", "uvm_reg_backdoor::read_func() method has not been overloaded", UVM_NONE, "t/uvm/src/reg/uvm_reg_backdoor.svh", 264, "", 1); end rw.status = UVM_NOT_OK; endfunction typedef class uvm_reg_cbs; class uvm_reg_field extends uvm_object; rand uvm_reg_data_t value; local uvm_reg_data_t m_mirrored; local uvm_reg_data_t m_desired; local string m_access; local uvm_reg m_parent; local int unsigned m_lsb; local int unsigned m_size; local bit m_volatile; local uvm_reg_data_t m_reset[string]; local bit m_written; local bit m_read_in_progress; local bit m_write_in_progress; local string m_fname; local int m_lineno; local int m_cover_on; local bit m_individually_accessible; local uvm_check_e m_check; local static int m_max_size; local static bit m_policy_names[string]; constraint uvm_reg_field_valid { if (64 > m_size) { value < (64'h1 << m_size); } } typedef uvm_object_registry#(uvm_reg_field,"uvm_reg_field") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_reg_field tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_reg_field"; endfunction : type_name virtual function string get_type_name(); return "uvm_reg_field"; endfunction : get_type_name extern function new(string name = "uvm_reg_field"); extern function void configure(uvm_reg parent, int unsigned size, int unsigned lsb_pos, string access, bit volatile, uvm_reg_data_t reset, bit has_reset, bit is_rand, bit individually_accessible); extern virtual function string get_full_name(); extern virtual function uvm_reg get_parent(); extern virtual function uvm_reg get_register(); extern virtual function int unsigned get_lsb_pos(); extern virtual function int unsigned get_n_bits(); extern static function int unsigned get_max_size(); extern virtual function string set_access(string mode); extern static function bit define_access(string name); local static bit m_predefined = m_predefine_policies(); extern local static function bit m_predefine_policies(); extern virtual function string get_access(uvm_reg_map map = null); extern virtual function bit is_known_access(uvm_reg_map map = null); extern virtual function void set_volatility(bit volatile); extern virtual function bit is_volatile(); extern virtual function void set(uvm_reg_data_t value, string fname = "", int lineno = 0); extern virtual function uvm_reg_data_t get(string fname = "", int lineno = 0); extern virtual function uvm_reg_data_t get_mirrored_value(string fname = "", int lineno = 0); extern virtual function void reset(string kind = "HARD"); extern virtual function uvm_reg_data_t get_reset(string kind = "HARD"); extern virtual function bit has_reset(string kind = "HARD", bit delete = 0); extern virtual function void set_reset(uvm_reg_data_t value, string kind = "HARD"); extern virtual function bit needs_update(); extern virtual task write (output uvm_status_e status, input uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern virtual task read (output uvm_status_e status, output uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern virtual task poke (output uvm_status_e status, input uvm_reg_data_t value, input string kind = "", input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern virtual task peek (output uvm_status_e status, output uvm_reg_data_t value, input string kind = "", input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern virtual task mirror(output uvm_status_e status, input uvm_check_e check = UVM_NO_CHECK, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern function void set_compare(uvm_check_e check=UVM_CHECK); extern function uvm_check_e get_compare(); extern function bit is_indv_accessible (uvm_door_e path, uvm_reg_map local_map); extern function bit predict (uvm_reg_data_t value, uvm_reg_byte_en_t be = -1, uvm_predict_e kind = UVM_PREDICT_DIRECT, uvm_door_e path = UVM_FRONTDOOR, uvm_reg_map map = null, string fname = "", int lineno = 0); extern virtual function uvm_reg_data_t XpredictX (uvm_reg_data_t cur_val, uvm_reg_data_t wr_val, uvm_reg_map map); extern virtual function uvm_reg_data_t XupdateX(); extern function bit Xcheck_accessX (input uvm_reg_item rw, output uvm_reg_map_info map_info); extern virtual task do_write(uvm_reg_item rw); extern virtual task do_read(uvm_reg_item rw); extern virtual function void do_predict (uvm_reg_item rw, uvm_predict_e kind=UVM_PREDICT_DIRECT, uvm_reg_byte_en_t be = -1); extern function void pre_randomize(); extern function void post_randomize(); static local bit m_register_cb_uvm_reg_cbs = uvm_callbacks#(uvm_reg_field,uvm_reg_cbs)::m_register_pair("uvm_reg_field","uvm_reg_cbs"); virtual task pre_write (uvm_reg_item rw); endtask virtual task post_write (uvm_reg_item rw); endtask virtual task pre_read (uvm_reg_item rw); endtask virtual task post_read (uvm_reg_item rw); endtask extern virtual function void do_print (uvm_printer printer); extern virtual function string convert2string; extern virtual function uvm_object clone(); extern virtual function void do_copy (uvm_object rhs); extern virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); extern virtual function void do_pack (uvm_packer packer); extern virtual function void do_unpack (uvm_packer packer); endclass: uvm_reg_field function uvm_reg_field::new(string name = "uvm_reg_field"); super.new(name); endfunction: new function void uvm_reg_field::configure(uvm_reg parent, int unsigned size, int unsigned lsb_pos, string access, bit volatile, uvm_reg_data_t reset, bit has_reset, bit is_rand, bit individually_accessible); m_parent = parent; if (size == 0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Field \"%s\" cannot have 0 bits", get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_reg_field.svh", 416, "", 1); end size = 1; end m_size = size; m_volatile = volatile; m_access = access.toupper(); m_lsb = lsb_pos; m_cover_on = UVM_NO_COVERAGE; m_written = 0; m_check = volatile ? UVM_NO_CHECK : UVM_CHECK; m_individually_accessible = individually_accessible; if (has_reset) set_reset(reset); m_parent.add_field(this); if (!m_policy_names.exists(m_access)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Access policy '",access, "' for field '",get_full_name(),"' is not defined. Setting to RW"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_field.svh", 436, "", 1); end m_access = "RW"; end if (size > m_max_size) m_max_size = size; case (access) "RO", "RC", "RS", "WC", "WS", "W1C", "W1S", "W1T", "W0C", "W0S", "W0T", "W1SRC", "W1CRS", "W0SRC", "W0CRS", "WSRC", "WCRS", "WOC", "WOS": is_rand = 0; endcase if (!is_rand) value.rand_mode(0); endfunction: configure function uvm_reg uvm_reg_field::get_parent(); return m_parent; endfunction: get_parent function string uvm_reg_field::get_full_name(); return {m_parent.get_full_name(), ".", get_name()}; endfunction: get_full_name function uvm_reg uvm_reg_field::get_register(); return m_parent; endfunction: get_register function int unsigned uvm_reg_field::get_lsb_pos(); return m_lsb; endfunction: get_lsb_pos function int unsigned uvm_reg_field::get_n_bits(); return m_size; endfunction: get_n_bits function int unsigned uvm_reg_field::get_max_size(); return m_max_size; endfunction: get_max_size function bit uvm_reg_field::is_known_access(uvm_reg_map map = null); string acc = get_access(map); case (acc) "RO", "RW", "RC", "RS", "WC", "WS", "W1C", "W1S", "W1T", "W0C", "W0S", "W0T", "WRC", "WRS", "W1SRC", "W1CRS", "W0SRC", "W0CRS", "WSRC", "WCRS", "WO", "WOC", "WOS", "W1", "WO1" : return 1; endcase return 0; endfunction function string uvm_reg_field::get_access(uvm_reg_map map = null); string field_access = m_access; if (map == uvm_reg_map::backdoor()) return field_access; case (m_parent.get_rights(map)) "RW": return field_access; "RO": case (field_access) "RW", "RO", "WC", "WS", "W1C", "W1S", "W1T", "W0C", "W0S", "W0T", "W1" : field_access = "RO"; "RC", "WRC", "W1SRC", "W0SRC", "WSRC" : field_access = "RC"; "RS", "WRS", "W1CRS", "W0CRS", "WCRS" : field_access = "RS"; "WO", "WOC", "WOS", "WO1": begin field_access = "NOACCESS"; end endcase "WO": case (field_access) "RW","WRC","WRS" : field_access = "WO"; "W1SRC" : field_access = "W1S"; "W0SRC": field_access = "W0S"; "W1CRS": field_access = "W1C"; "W0CRS": field_access = "W0C"; "WCRS": field_access = "WC"; "W1" : field_access = "W1"; "WO1" : field_access = "WO1"; "WSRC" : field_access = "WS"; "RO","RC","RS": field_access = "NOACCESS"; endcase default: begin field_access = "NOACCESS"; begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Register '",m_parent.get_full_name(), "' containing field '",get_name(),"' is mapped in map '", map.get_full_name(),"' with unknown access right '", m_parent.get_rights(map), "'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_field.svh", 570, "", 1); end end endcase return field_access; endfunction: get_access function string uvm_reg_field::set_access(string mode); set_access = m_access; m_access = mode.toupper(); if (!m_policy_names.exists(m_access)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Access policy '",m_access, "' is not a defined field access policy"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_field.svh", 584, "", 1); end m_access = set_access; end endfunction: set_access function bit uvm_reg_field::define_access(string name); if (!m_predefined) m_predefined = m_predefine_policies(); name = name.toupper(); if (m_policy_names.exists(name)) return 0; m_policy_names[name] = 1; return 1; endfunction function bit uvm_reg_field::m_predefine_policies(); if (m_predefined) return 1; m_predefined = 1; void'(define_access("RO")); void'(define_access("RW")); void'(define_access("RC")); void'(define_access("RS")); void'(define_access("WRC")); void'(define_access("WRS")); void'(define_access("WC")); void'(define_access("WS")); void'(define_access("WSRC")); void'(define_access("WCRS")); void'(define_access("W1C")); void'(define_access("W1S")); void'(define_access("W1T")); void'(define_access("W0C")); void'(define_access("W0S")); void'(define_access("W0T")); void'(define_access("W1SRC")); void'(define_access("W1CRS")); void'(define_access("W0SRC")); void'(define_access("W0CRS")); void'(define_access("WO")); void'(define_access("WOC")); void'(define_access("WOS")); void'(define_access("W1")); void'(define_access("WO1")); return 1; endfunction function void uvm_reg_field::set_volatility(bit volatile); m_volatile = volatile; endfunction function bit uvm_reg_field::is_volatile(); return m_volatile; endfunction function uvm_reg_data_t uvm_reg_field::XpredictX (uvm_reg_data_t cur_val, uvm_reg_data_t wr_val, uvm_reg_map map); uvm_reg_data_t mask = ('b1 << m_size)-1; case (get_access(map)) "RO": return cur_val; "RW": return wr_val; "RC": return cur_val; "RS": return cur_val; "WC": return '0; "WS": return mask; "WRC": return wr_val; "WRS": return wr_val; "WSRC": return mask; "WCRS": return '0; "W1C": return cur_val & (~wr_val); "W1S": return cur_val | wr_val; "W1T": return cur_val ^ wr_val; "W0C": return cur_val & wr_val; "W0S": return cur_val | (~wr_val & mask); "W0T": return cur_val ^ (~wr_val & mask); "W1SRC": return cur_val | wr_val; "W1CRS": return cur_val & (~wr_val); "W0SRC": return cur_val | (~wr_val & mask); "W0CRS": return cur_val & wr_val; "WO": return wr_val; "WOC": return '0; "WOS": return mask; "W1": return (m_written) ? cur_val : wr_val; "WO1": return (m_written) ? cur_val : wr_val; "NOACCESS": return cur_val; default: return wr_val; endcase begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"RegModel")) uvm_report_fatal ("RegModel", "uvm_reg_field::XpredictX(): Internal error", UVM_NONE, "t/uvm/src/reg/uvm_reg_field.svh", 691, "", 1); end return 0; endfunction: XpredictX function bit uvm_reg_field::predict (uvm_reg_data_t value, uvm_reg_byte_en_t be = -1, uvm_predict_e kind = UVM_PREDICT_DIRECT, uvm_door_e path = UVM_FRONTDOOR, uvm_reg_map map = null, string fname = "", int lineno = 0); uvm_reg_item rw = new; rw.value[0] = value; rw.path = path; rw.map = map; rw.fname = fname; rw.lineno = lineno; do_predict(rw, kind, be); predict = (rw.status == UVM_NOT_OK) ? 0 : 1; endfunction: predict function void uvm_reg_field::do_predict(uvm_reg_item rw, uvm_predict_e kind = UVM_PREDICT_DIRECT, uvm_reg_byte_en_t be = -1); uvm_reg_data_t field_val = rw.value[0] & ((1 << m_size)-1); if (rw.status != UVM_NOT_OK) rw.status = UVM_IS_OK; if (!be[0]) return; m_fname = rw.fname; m_lineno = rw.lineno; case (kind) UVM_PREDICT_WRITE: begin uvm_reg_field_cb_iter cbs = new(this); if (rw.path == UVM_FRONTDOOR || rw.path == UVM_PREDICT) field_val = XpredictX(m_mirrored, field_val, rw.map); m_written = 1; for (uvm_reg_cbs cb = cbs.first(); cb != null; cb = cbs.next()) cb.post_predict(this, m_mirrored, field_val, UVM_PREDICT_WRITE, rw.path, rw.map); field_val &= ('b1 << m_size)-1; end UVM_PREDICT_READ: begin uvm_reg_field_cb_iter cbs = new(this); if (rw.path == UVM_FRONTDOOR || rw.path == UVM_PREDICT) begin string acc = get_access(rw.map); if (acc == "RC" || acc == "WRC" || acc == "WSRC" || acc == "W1SRC" || acc == "W0SRC") field_val = 0; else if (acc == "RS" || acc == "WRS" || acc == "WCRS" || acc == "W1CRS" || acc == "W0CRS") field_val = ('b1 << m_size)-1; else if (acc == "WO" || acc == "WOC" || acc == "WOS" || acc == "WO1" || acc == "NOACCESS") return; end for (uvm_reg_cbs cb = cbs.first(); cb != null; cb = cbs.next()) cb.post_predict(this, m_mirrored, field_val, UVM_PREDICT_READ, rw.path, rw.map); field_val &= ('b1 << m_size)-1; end UVM_PREDICT_DIRECT: begin if (m_parent.is_busy()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Trying to predict value of field '", get_name(),"' while register '",m_parent.get_full_name(), "' is being accessed"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_field.svh", 797, "", 1); end rw.status = UVM_NOT_OK; end end endcase m_mirrored = field_val; m_desired = field_val; this.value = field_val; endfunction: do_predict function uvm_reg_data_t uvm_reg_field::XupdateX(); XupdateX = 0; case (m_access) "RO": XupdateX = m_desired; "RW": XupdateX = m_desired; "RC": XupdateX = m_desired; "RS": XupdateX = m_desired; "WRC": XupdateX = m_desired; "WRS": XupdateX = m_desired; "WC": XupdateX = m_desired; "WS": XupdateX = m_desired; "WSRC": XupdateX = m_desired; "WCRS": XupdateX = m_desired; "W1C": XupdateX = ~m_desired; "W1S": XupdateX = m_desired; "W1T": XupdateX = m_desired ^ m_mirrored; "W0C": XupdateX = m_desired; "W0S": XupdateX = ~m_desired; "W0T": XupdateX = ~(m_desired ^ m_mirrored); "W1SRC": XupdateX = m_desired; "W1CRS": XupdateX = ~m_desired; "W0SRC": XupdateX = ~m_desired; "W0CRS": XupdateX = m_desired; "WO": XupdateX = m_desired; "WOC": XupdateX = m_desired; "WOS": XupdateX = m_desired; "W1": XupdateX = m_desired; "WO1": XupdateX = m_desired; default: XupdateX = m_desired; endcase XupdateX &= (1 << m_size) - 1; endfunction: XupdateX function void uvm_reg_field::set(uvm_reg_data_t value, string fname = "", int lineno = 0); uvm_reg_data_t mask = ('b1 << m_size)-1; m_fname = fname; m_lineno = lineno; if (value >> m_size) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", $sformatf("Specified value (0x%h) greater than field \"%s\" size (%0d bits)", value, get_name(), m_size), UVM_NONE, "t/uvm/src/reg/uvm_reg_field.svh", 863, "", 1); end value &= mask; end if (m_parent.is_busy()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/FLD/SET/BSY")) uvm_report_warning ("UVM/FLD/SET/BSY", $sformatf("Setting the value of field \"%s\" while containing register \"%s\" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.", get_name(), m_parent.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_reg_field.svh", 870, "", 1); end end case (m_access) "RO": m_desired = m_desired; "RW": m_desired = value; "RC": m_desired = m_desired; "RS": m_desired = m_desired; "WC": m_desired = '0; "WS": m_desired = mask; "WRC": m_desired = value; "WRS": m_desired = value; "WSRC": m_desired = mask; "WCRS": m_desired = '0; "W1C": m_desired = m_desired & (~value); "W1S": m_desired = m_desired | value; "W1T": m_desired = m_desired ^ value; "W0C": m_desired = m_desired & value; "W0S": m_desired = m_desired | (~value & mask); "W0T": m_desired = m_desired ^ (~value & mask); "W1SRC": m_desired = m_desired | value; "W1CRS": m_desired = m_desired & (~value); "W0SRC": m_desired = m_desired | (~value & mask); "W0CRS": m_desired = m_desired & value; "WO": m_desired = value; "WOC": m_desired = '0; "WOS": m_desired = mask; "W1": m_desired = (m_written) ? m_desired : value; "WO1": m_desired = (m_written) ? m_desired : value; default: m_desired = value; endcase this.value = m_desired; endfunction: set function uvm_reg_data_t uvm_reg_field::get(string fname = "", int lineno = 0); m_fname = fname; m_lineno = lineno; get = m_desired; endfunction: get function uvm_reg_data_t uvm_reg_field::get_mirrored_value(string fname = "", int lineno = 0); m_fname = fname; m_lineno = lineno; get_mirrored_value = m_mirrored; endfunction: get_mirrored_value function void uvm_reg_field::reset(string kind = "HARD"); if (!m_reset.exists(kind)) return; m_mirrored = m_reset[kind]; m_desired = m_mirrored; value = m_mirrored; if (kind == "HARD") m_written = 0; endfunction: reset function bit uvm_reg_field::has_reset(string kind = "HARD", bit delete = 0); if (!m_reset.exists(kind)) return 0; if (delete) m_reset.delete(kind); return 1; endfunction: has_reset function uvm_reg_data_t uvm_reg_field::get_reset(string kind = "HARD"); if (!m_reset.exists(kind)) return m_desired; return m_reset[kind]; endfunction: get_reset function void uvm_reg_field::set_reset(uvm_reg_data_t value, string kind = "HARD"); m_reset[kind] = value & ((1<> m_size) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"uvm_reg_field::write(): Value greater than field '", get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_field.svh", 1092, "", 1); end rw.value[0] &= ((1<> m_lsb) & ((1<0) begin prev_lsb = fields[fld_idx-1].get_lsb_pos(); prev_sz = fields[fld_idx-1].get_n_bits(); end if (fld_idx < fields.size()-1) begin next_lsb = fields[fld_idx+1].get_lsb_pos(); next_sz = fields[fld_idx+1].get_n_bits(); end if (fld_idx == 0 && ((next_lsb % bus_sz) == 0 || (next_lsb - this_sz) > (next_lsb % bus_sz))) return 1; else if (fld_idx == (fields.size()-1) && ((this_lsb % bus_sz) == 0 || (this_lsb - (prev_lsb + prev_sz)) >= (this_lsb % bus_sz))) return 1; else begin if ((this_lsb % bus_sz) == 0) begin if ((next_lsb % bus_sz) == 0 || (next_lsb - (this_lsb + this_sz)) >= (next_lsb % bus_sz)) return 1; end else begin if ( (next_lsb - (this_lsb + this_sz)) >= (next_lsb % bus_sz) && ((this_lsb - (prev_lsb + prev_sz)) >= (this_lsb % bus_sz)) ) return 1; end end end end begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Target bus does not support byte enabling, and the field '", get_full_name(),"' is not the only field within the entire bus width. ", "Individual field access will not be available. ", "Accessing complete register instead."}, UVM_NONE, "t/uvm/src/reg/uvm_reg_field.svh", 1422, "", 1); end return 0; endfunction task uvm_reg_field::poke(output uvm_status_e status, input uvm_reg_data_t value, input string kind = "", input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_data_t tmp; m_fname = fname; m_lineno = lineno; if (value >> m_size) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"uvm_reg_field::poke(): Value exceeds size of field '", get_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_field.svh", 1446, "", 1); end value &= value & ((1<> m_lsb) & ((1< 64) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Virtual field \"%s\" cannot have more than %0d bits", this.get_full_name(), 64), UVM_NONE, "t/uvm/src/reg/uvm_vreg_field.svh", 327, "", 1); end size = 64; end this.size = size; this.lsb = lsb_pos; this.parent.add_field(this); endfunction: configure function string uvm_vreg_field::get_full_name(); get_full_name = {this.parent.get_full_name(), ".", this.get_name()}; endfunction: get_full_name function uvm_vreg uvm_vreg_field::get_register(); get_register = this.parent; endfunction: get_register function uvm_vreg uvm_vreg_field::get_parent(); get_parent = this.parent; endfunction: get_parent function int unsigned uvm_vreg_field::get_lsb_pos_in_register(); get_lsb_pos_in_register = this.lsb; endfunction: get_lsb_pos_in_register function int unsigned uvm_vreg_field::get_n_bits(); get_n_bits = this.size; endfunction: get_n_bits function string uvm_vreg_field::get_access(uvm_reg_map map = null); if (this.parent.get_memory() == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot call uvm_vreg_field::get_rights() on unimplemented virtual field \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg_field.svh", 368, "", 1); end return "RW"; end return this.parent.get_access(map); endfunction: get_access task uvm_vreg_field::write(input longint unsigned idx, output uvm_status_e status, input uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_data_t tmp; uvm_reg_data_t segval; uvm_reg_addr_t segoff; uvm_status_e st; int flsb, fmsb, rmwbits; int segsiz, segn; uvm_mem mem; uvm_door_e rm_path; uvm_vreg_field_cb_iter cbs = new(this); this.fname = fname; this.lineno = lineno; write_in_progress = 1'b1; mem = this.parent.get_memory(); if (mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot call uvm_vreg_field::write() on unimplemented virtual register \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg_field.svh", 404, "", 1); end status = UVM_NOT_OK; return; end if (path == UVM_DEFAULT_DOOR) begin uvm_reg_block blk = this.parent.get_block(); path = blk.get_default_door(); end status = UVM_IS_OK; this.parent.XatomicX(1); if (value >> this.size) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", $sformatf("Writing value 'h%h that is greater than field \"%s\" size (%0d bits)", value, this.get_full_name(), this.get_n_bits()), UVM_NONE, "t/uvm/src/reg/uvm_vreg_field.svh", 419, "", 1); end value &= value & ((1< 0) begin uvm_reg_addr_t segn; mem.read(st, segoff, tmp, rm_path, map, parent, , extension, fname, lineno); if (st != UVM_IS_OK && st != UVM_HAS_X) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Unable to read LSB bits in %s[%0d] to for RMW cycle on virtual field %s.", mem.get_full_name(), segoff, this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg_field.svh", 453, "", 1); end status = UVM_NOT_OK; this.parent.XatomicX(0); return; end value = (value << rmwbits) | (tmp & ((1< 0) begin if (segn > 0) begin mem.read(st, segoff + segn - 1, tmp, rm_path, map, parent,, extension, fname, lineno); if (st != UVM_IS_OK && st != UVM_HAS_X) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Unable to read MSB bits in %s[%0d] to for RMW cycle on virtual field %s.", mem.get_full_name(), segoff+segn-1, this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg_field.svh", 472, "", 1); end status = UVM_NOT_OK; this.parent.XatomicX(0); return; end end value |= (tmp & ~((1<> segsiz; end this.post_write(idx, value, path, map, status); for (uvm_vreg_field_cbs cb = cbs.first(); cb != null; cb = cbs.next()) begin cb.fname = this.fname; cb.lineno = this.lineno; cb.post_write(this, idx, value, path, map, status); end this.parent.XatomicX(0); begin if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("Wrote virtual field \"%s\"[%0d] via %s with: 'h%h", this.get_full_name(), idx, (path == UVM_FRONTDOOR) ? "frontdoor" : "backdoor", value), UVM_MEDIUM, "t/uvm/src/reg/uvm_vreg_field.svh", 505, "", 1); end write_in_progress = 1'b0; this.fname = ""; this.lineno = 0; endtask: write task uvm_vreg_field::read(input longint unsigned idx, output uvm_status_e status, output uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_data_t tmp; uvm_reg_data_t segval; uvm_reg_addr_t segoff; uvm_status_e st; int flsb, lsb; int segsiz, segn; uvm_mem mem; uvm_vreg_field_cb_iter cbs = new(this); this.fname = fname; this.lineno = lineno; read_in_progress = 1'b1; mem = this.parent.get_memory(); if (mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot call uvm_vreg_field::read() on unimplemented virtual register \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg_field.svh", 540, "", 1); end status = UVM_NOT_OK; return; end if (path == UVM_DEFAULT_DOOR) begin uvm_reg_block blk = this.parent.get_block(); path = blk.get_default_door(); end status = UVM_IS_OK; this.parent.XatomicX(1); value = 0; this.pre_read(idx, path, map); for (uvm_vreg_field_cbs cb = cbs.first(); cb != null; cb = cbs.next()) begin cb.fname = this.fname; cb.lineno = this.lineno; cb.pre_read(this, idx, path, map); end segsiz = mem.get_n_bytes() * 8; flsb = this.get_lsb_pos_in_register(); segoff = this.parent.get_offset_in_memory(idx) + (flsb / segsiz); lsb = flsb % segsiz; segn = (lsb + this.get_n_bits() - 1) / segsiz + 1; segoff += segn - 1; repeat (segn) begin value = value << segsiz; mem.read(st, segoff, tmp, path, map, parent, , extension, fname, lineno); if (st != UVM_IS_OK && st != UVM_HAS_X) status = UVM_NOT_OK; segoff--; value |= tmp; end value = value >> lsb; value &= (1<> this.size) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", $sformatf("Writing value 'h%h that is greater than field \"%s\" size (%0d bits)", value, this.get_full_name(), this.get_n_bits()), UVM_NONE, "t/uvm/src/reg/uvm_vreg_field.svh", 644, "", 1); end value &= value & ((1< 0) begin uvm_reg_addr_t segn; mem.peek(st, segoff, tmp, "", parent, extension, fname, lineno); if (st != UVM_IS_OK && st != UVM_HAS_X) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Unable to read LSB bits in %s[%0d] to for RMW cycle on virtual field %s.", mem.get_full_name(), segoff, this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg_field.svh", 666, "", 1); end status = UVM_NOT_OK; this.parent.XatomicX(0); return; end value = (value << rmwbits) | (tmp & ((1< 0) begin if (segn > 0) begin mem.peek(st, segoff + segn - 1, tmp, "", parent, extension, fname, lineno); if (st != UVM_IS_OK && st != UVM_HAS_X) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Unable to read MSB bits in %s[%0d] to for RMW cycle on virtual field %s.", mem.get_full_name(), segoff+segn-1, this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg_field.svh", 685, "", 1); end status = UVM_NOT_OK; this.parent.XatomicX(0); return; end end value |= (tmp & ~((1<> segsiz; end this.parent.XatomicX(0); begin if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("Wrote virtual field \"%s\"[%0d] with: 'h%h", this.get_full_name(), idx, value), UVM_MEDIUM, "t/uvm/src/reg/uvm_vreg_field.svh", 707, "", 1); end this.fname = ""; this.lineno = 0; endtask: poke task uvm_vreg_field::peek(input longint unsigned idx, output uvm_status_e status, output uvm_reg_data_t value, input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_data_t tmp; uvm_reg_data_t segval; uvm_reg_addr_t segoff; uvm_status_e st; int flsb, lsb; int segsiz, segn; uvm_mem mem; this.fname = fname; this.lineno = lineno; mem = this.parent.get_memory(); if (mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot call uvm_vreg_field::peek() on unimplemented virtual register \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg_field.svh", 735, "", 1); end status = UVM_NOT_OK; return; end status = UVM_IS_OK; this.parent.XatomicX(1); value = 0; segsiz = mem.get_n_bytes() * 8; flsb = this.get_lsb_pos_in_register(); segoff = this.parent.get_offset_in_memory(idx) + (flsb / segsiz); lsb = flsb % segsiz; segn = (lsb + this.get_n_bits() - 1) / segsiz + 1; segoff += segn - 1; repeat (segn) begin value = value << segsiz; mem.peek(st, segoff, tmp, "", parent, extension, fname, lineno); if (st != UVM_IS_OK && st != UVM_HAS_X) status = UVM_NOT_OK; segoff--; value |= tmp; end value = value >> lsb; value &= (1< m_max_size) m_max_size = n_bits; endfunction: new function void uvm_reg::configure (uvm_reg_block blk_parent, uvm_reg_file regfile_parent=null, string hdl_path = ""); if (blk_parent == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/REG/CFG/NOBLK")) uvm_report_error ("UVM/REG/CFG/NOBLK", {"uvm_reg::configure() called without a parent block for instance \"", get_name(), "\" of register type \"", get_type_name(), "\"."}, UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 623, "", 1); end return; end m_parent = blk_parent; m_parent.add_reg(this); m_regfile_parent = regfile_parent; if (hdl_path != "") add_hdl_path_slice(hdl_path, -1, -1); endfunction: configure function void uvm_reg::add_field(uvm_reg_field field); int offset; int idx; if (m_locked) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", "Cannot add field to locked register model", UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 642, "", 1); end return; end if (field == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"RegModel")) uvm_report_fatal ("RegModel", "Attempting to register NULL field", UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 646, "", 1); end offset = field.get_lsb_pos(); idx = -1; foreach (m_fields[i]) begin if (offset < m_fields[i].get_lsb_pos()) begin int j = i; m_fields.insert(j, field); idx = i; break; end end if (idx < 0) begin m_fields.push_back(field); idx = m_fields.size()-1; end m_n_used_bits += field.get_n_bits(); if (m_n_used_bits > m_n_bits) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Fields use more bits (%0d) than available in register \"%s\" (%0d)", m_n_used_bits, get_name(), m_n_bits), UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 671, "", 1); end end if (idx > 0) begin if (m_fields[idx-1].get_lsb_pos() + m_fields[idx-1].get_n_bits() > offset) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Field %s overlaps field %s in register \"%s\"", m_fields[idx-1].get_name(), field.get_name(), get_name()), UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 680, "", 1); end end end if (idx < m_fields.size()-1) begin if (offset + field.get_n_bits() > m_fields[idx+1].get_lsb_pos()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Field %s overlaps field %s in register \"%s\"", field.get_name(), m_fields[idx+1].get_name(), get_name()), UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 689, "", 1); end end end endfunction: add_field function void uvm_reg::Xlock_modelX(); if (m_locked) return; m_locked = 1; endfunction function void uvm_reg::set_frontdoor(uvm_reg_frontdoor ftdr, uvm_reg_map map = null, string fname = "", int lineno = 0); uvm_reg_map_info map_info; ftdr.fname = m_fname; ftdr.lineno = m_lineno; map = get_local_map(map); if (map == null) return; map_info = map.get_reg_map_info(this); if (map_info == null) map.add_reg(this, -1, "RW", 1, ftdr); else begin map_info.frontdoor = ftdr; end endfunction: set_frontdoor function uvm_reg_frontdoor uvm_reg::get_frontdoor(uvm_reg_map map = null); uvm_reg_map_info map_info; map = get_local_map(map); if (map == null) return null; map_info = map.get_reg_map_info(this); return map_info.frontdoor; endfunction: get_frontdoor function void uvm_reg::set_backdoor(uvm_reg_backdoor bkdr, string fname = "", int lineno = 0); bkdr.fname = fname; bkdr.lineno = lineno; if (m_backdoor != null && m_backdoor.has_update_threads()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", "Previous register backdoor still has update threads running. Backdoors with active mirroring should only be set before simulation starts.", UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 750, "", 1); end end m_backdoor = bkdr; endfunction: set_backdoor function uvm_reg_backdoor uvm_reg::get_backdoor(bit inherited = 1); if (m_backdoor == null && inherited) begin uvm_reg_block blk = get_parent(); uvm_reg_backdoor bkdr; while (blk != null) begin bkdr = blk.get_backdoor(); if (bkdr != null) begin m_backdoor = bkdr; break; end blk = blk.get_parent(); end end return m_backdoor; endfunction: get_backdoor function void uvm_reg::clear_hdl_path(string kind = "RTL"); if (kind == "ALL") begin m_hdl_paths_pool = new("hdl_paths"); return; end if (kind == "") begin if (m_regfile_parent != null) kind = m_regfile_parent.get_default_hdl_path(); else kind = m_parent.get_default_hdl_path(); end if (!m_hdl_paths_pool.exists(kind)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Unknown HDL Abstraction '",kind,"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 793, "", 1); end return; end m_hdl_paths_pool.delete(kind); endfunction function void uvm_reg::add_hdl_path(uvm_hdl_path_slice slices[], string kind = "RTL"); uvm_queue #(uvm_hdl_path_concat) paths = m_hdl_paths_pool.get(kind); uvm_hdl_path_concat concat = new(); concat.set(slices); paths.push_back(concat); endfunction function void uvm_reg::add_hdl_path_slice(string name, int offset, int size, bit first = 0, string kind = "RTL"); uvm_queue #(uvm_hdl_path_concat) paths = m_hdl_paths_pool.get(kind); uvm_hdl_path_concat concat; if (first || paths.size() == 0) begin concat = new(); paths.push_back(concat); end else concat = paths.get(paths.size()-1); concat.add_path(name, offset, size); endfunction function bit uvm_reg::has_hdl_path(string kind = ""); if (kind == "") begin if (m_regfile_parent != null) kind = m_regfile_parent.get_default_hdl_path(); else kind = m_parent.get_default_hdl_path(); end return m_hdl_paths_pool.exists(kind); endfunction function void uvm_reg::get_hdl_path_kinds (ref string kinds[$]); string kind; kinds.delete(); if (!m_hdl_paths_pool.first(kind)) return; do kinds.push_back(kind); while (m_hdl_paths_pool.next(kind)); endfunction function void uvm_reg::get_hdl_path(ref uvm_hdl_path_concat paths[$], input string kind = ""); uvm_queue #(uvm_hdl_path_concat) hdl_paths; if (kind == "") begin if (m_regfile_parent != null) kind = m_regfile_parent.get_default_hdl_path(); else kind = m_parent.get_default_hdl_path(); end if (!has_hdl_path(kind)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Register does not have hdl path defined for abstraction '",kind,"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 877, "", 1); end return; end hdl_paths = m_hdl_paths_pool.get(kind); for (int i=0; i 1 && map == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"set_offset requires a non-null map when register '", get_full_name(),"' belongs to more than one map."}, UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 949, "", 1); end return; end map = get_local_map(map); if (map == null) return; map.m_set_reg_offset(this, offset, unmapped); endfunction function void uvm_reg::set_parent(uvm_reg_block blk_parent, uvm_reg_file regfile_parent); if (m_parent != null) begin end m_parent = blk_parent; m_regfile_parent = regfile_parent; endfunction function uvm_reg_block uvm_reg::get_parent(); return get_block(); endfunction function uvm_reg_file uvm_reg::get_regfile(); return m_regfile_parent; endfunction function string uvm_reg::get_full_name(); if (m_regfile_parent != null) return {m_regfile_parent.get_full_name(), ".", get_name()}; if (m_parent != null) return {m_parent.get_full_name(), ".", get_name()}; return get_name(); endfunction: get_full_name function void uvm_reg::add_map(uvm_reg_map map); m_maps[map] = 1; endfunction function void uvm_reg::get_maps(ref uvm_reg_map maps[$]); foreach (m_maps[map]) maps.push_back(map); endfunction function int uvm_reg::get_n_maps(); return m_maps.num(); endfunction function bit uvm_reg::is_in_map(uvm_reg_map map); if (m_maps.exists(map)) return 1; foreach (m_maps[l]) begin uvm_reg_map local_map = l; uvm_reg_map parent_map = local_map.get_parent_map(); while (parent_map != null) begin if (parent_map == map) return 1; parent_map = parent_map.get_parent_map(); end end return 0; endfunction function uvm_reg_map uvm_reg::get_local_map(uvm_reg_map map); if (map == null) return get_default_map(); if (m_maps.exists(map)) return map; foreach (m_maps[l]) begin uvm_reg_map local_map=l; uvm_reg_map parent_map = local_map.get_parent_map(); while (parent_map != null) begin if (parent_map == map) return local_map; parent_map = parent_map.get_parent_map(); end end begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Register '",get_full_name(),"' is not contained within map '",map.get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 1062, "", 1); end return null; endfunction function uvm_reg_map uvm_reg::get_default_map(); if (m_maps.num() == 0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Register '",get_full_name(),"' is not registered with any map"}, UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 1075, "", 1); end return null; end if (m_maps.num() == 1) begin uvm_reg_map map; void'(m_maps.first(map)); return map; end foreach (m_maps[l]) begin uvm_reg_map map = l; uvm_reg_block blk = map.get_parent(); uvm_reg_map default_map = blk.get_default_map(); if (default_map != null) begin uvm_reg_map local_map = get_local_map(default_map); if (local_map != null) return local_map; end end begin uvm_reg_map map; void'(m_maps.first(map)); return map; end endfunction function string uvm_reg::get_rights(uvm_reg_map map = null); uvm_reg_map_info info; map = get_local_map(map); if (map == null) return "RW"; info = map.get_reg_map_info(this); return info.rights; endfunction function uvm_reg_block uvm_reg::get_block(); get_block = m_parent; endfunction function uvm_reg_addr_t uvm_reg::get_offset(uvm_reg_map map = null); uvm_reg_map_info map_info; uvm_reg_map orig_map = map; map = get_local_map(map); if (map == null) return -1; map_info = map.get_reg_map_info(this); if (map_info.unmapped) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Register '",get_name(), "' is unmapped in map '", ((orig_map == null) ? map.get_full_name() : orig_map.get_full_name()),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 1151, "", 1); end return -1; end return map_info.offset; endfunction function int uvm_reg::get_addresses(uvm_reg_map map=null, ref uvm_reg_addr_t addr[]); uvm_reg_map_info map_info; uvm_reg_map orig_map = map; map = get_local_map(map); if (map == null) return -1; map_info = map.get_reg_map_info(this); if (map_info.unmapped) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Register '",get_name(), "' is unmapped in map '", ((orig_map == null) ? map.get_full_name() : orig_map.get_full_name()),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 1177, "", 1); end return -1; end addr = map_info.addr; return map.get_n_bytes(); endfunction function uvm_reg_addr_t uvm_reg::get_address(uvm_reg_map map = null); uvm_reg_addr_t addr[]; void'(get_addresses(map,addr)); return addr[0]; endfunction function int unsigned uvm_reg::get_n_bits(); return m_n_bits; endfunction function int unsigned uvm_reg::get_n_bytes(); return ((m_n_bits-1) / 8) + 1; endfunction function int unsigned uvm_reg::get_max_size(); return m_max_size; endfunction: get_max_size function void uvm_reg::get_fields(ref uvm_reg_field fields[$]); foreach(m_fields[i]) fields.push_back(m_fields[i]); endfunction function uvm_reg_field uvm_reg::get_field_by_name(string name); foreach (m_fields[i]) if (m_fields[i].get_name() == name) return m_fields[i]; begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Unable to locate field '",name, "' in register '",get_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 1232, "", 1); end return null; endfunction function string uvm_reg::Xget_fields_accessX(uvm_reg_map map); bit is_R; bit is_W; foreach(m_fields[i]) begin case (m_fields[i].get_access(map)) "RO", "RC", "RS": is_R = 1; "WO", "WOC", "WOS", "WO1": is_W = 1; default: return "RW"; endcase if (is_R && is_W) return "RW"; end case ({is_R, is_W}) 2'b01: return "WO"; 2'b10: return "RO"; endcase return "RW"; endfunction function void uvm_reg::include_coverage(string scope, uvm_reg_cvr_t models, uvm_object accessor = null); uvm_reg_cvr_rsrc_db::set({"uvm_reg::", scope}, "include_coverage", models, accessor); endfunction function uvm_reg_cvr_t uvm_reg::build_coverage(uvm_reg_cvr_t models); build_coverage = UVM_NO_COVERAGE; void'(uvm_reg_cvr_rsrc_db::read_by_name({"uvm_reg::", get_full_name()}, "include_coverage", build_coverage, this)); return build_coverage & models; endfunction: build_coverage function void uvm_reg::add_coverage(uvm_reg_cvr_t models); m_has_cover |= models; endfunction: add_coverage function bit uvm_reg::has_coverage(uvm_reg_cvr_t models); return ((m_has_cover & models) == models); endfunction: has_coverage function uvm_reg_cvr_t uvm_reg::set_coverage(uvm_reg_cvr_t is_on); if (is_on == uvm_reg_cvr_t'(UVM_NO_COVERAGE)) begin m_cover_on = is_on; return m_cover_on; end m_cover_on = m_has_cover & is_on; return m_cover_on; endfunction: set_coverage function bit uvm_reg::get_coverage(uvm_reg_cvr_t is_on); if (has_coverage(is_on) == 0) return 0; return ((m_cover_on & is_on) == is_on); endfunction: get_coverage function void uvm_reg::set(uvm_reg_data_t value, string fname = "", int lineno = 0); m_fname = fname; m_lineno = lineno; foreach (m_fields[i]) m_fields[i].set((value >> m_fields[i].get_lsb_pos()) & ((1 << m_fields[i].get_n_bits()) - 1)); endfunction: set function bit uvm_reg::predict (uvm_reg_data_t value, uvm_reg_byte_en_t be = -1, uvm_predict_e kind = UVM_PREDICT_DIRECT, uvm_door_e path = UVM_FRONTDOOR, uvm_reg_map map = null, string fname = "", int lineno = 0); uvm_reg_item rw = new; rw.value[0] = value; rw.path = path; rw.map = map; rw.fname = fname; rw.lineno = lineno; do_predict(rw, kind, be); predict = (rw.status == UVM_NOT_OK) ? 0 : 1; endfunction: predict function void uvm_reg::do_predict(uvm_reg_item rw, uvm_predict_e kind = UVM_PREDICT_DIRECT, uvm_reg_byte_en_t be = -1); uvm_reg_data_t reg_value = rw.value[0]; m_fname = rw.fname; m_lineno = rw.lineno; if (rw.status ==UVM_IS_OK ) rw.status = UVM_IS_OK; if (m_is_busy && kind == UVM_PREDICT_DIRECT) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Trying to predict value of register '", get_full_name(),"' while it is being accessed"}, UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 1395, "", 1); end rw.status = UVM_NOT_OK; return; end foreach (m_fields[i]) begin rw.value[0] = (reg_value >> m_fields[i].get_lsb_pos()) & ((1 << m_fields[i].get_n_bits())-1); m_fields[i].do_predict(rw, kind, be>>(m_fields[i].get_lsb_pos()/8)); end rw.value[0] = reg_value; endfunction: do_predict function uvm_reg_data_t uvm_reg::get(string fname = "", int lineno = 0); m_fname = fname; m_lineno = lineno; get = 0; foreach (m_fields[i]) get |= m_fields[i].get() << m_fields[i].get_lsb_pos(); endfunction: get function uvm_reg_data_t uvm_reg::get_mirrored_value(string fname = "", int lineno = 0); m_fname = fname; m_lineno = lineno; get_mirrored_value = 0; foreach (m_fields[i]) get_mirrored_value |= m_fields[i].get_mirrored_value() << m_fields[i].get_lsb_pos(); endfunction: get_mirrored_value function void uvm_reg::reset(string kind = "HARD"); foreach (m_fields[i]) m_fields[i].reset(kind); void'(m_atomic.try_get(1)); m_atomic.put(1); m_process = null; Xset_busyX(0); endfunction: reset function uvm_reg_data_t uvm_reg::get_reset(string kind = "HARD"); get_reset = 0; foreach (m_fields[i]) get_reset |= m_fields[i].get_reset(kind) << m_fields[i].get_lsb_pos(); endfunction: get_reset function bit uvm_reg::has_reset(string kind = "HARD", bit delete = 0); has_reset = 0; foreach (m_fields[i]) begin has_reset |= m_fields[i].has_reset(kind, delete); if (!delete && has_reset) return 1; end endfunction: has_reset function void uvm_reg::set_reset(uvm_reg_data_t value, string kind = "HARD"); foreach (m_fields[i]) begin m_fields[i].set_reset(value >> m_fields[i].get_lsb_pos(), kind); end endfunction: set_reset function bit uvm_reg::needs_update(); needs_update = 0; foreach (m_fields[i]) begin if (m_fields[i].needs_update()) begin return 1; end end endfunction: needs_update task uvm_reg::update(output uvm_status_e status, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_data_t upd; status = UVM_IS_OK; if (!needs_update()) return; upd = 0; foreach (m_fields[i]) upd |= m_fields[i].XupdateX() << m_fields[i].get_lsb_pos(); write(status, upd, path, map, parent, prior, extension, fname, lineno); endtask: update task uvm_reg::write(output uvm_status_e status, input uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_item rw; XatomicX(1); set(value); rw = uvm_reg_item::type_id::create("write_item",,get_full_name()); rw.element = this; rw.element_kind = UVM_REG; rw.kind = UVM_WRITE; rw.value[0] = value; rw.path = path; rw.map = map; rw.parent = parent; rw.prior = prior; rw.extension = extension; rw.fname = fname; rw.lineno = lineno; do_write(rw); status = rw.status; XatomicX(0); endtask task uvm_reg::do_write (uvm_reg_item rw); uvm_reg_cb_iter cbs = new(this); uvm_reg_map_info map_info; uvm_reg_data_t value; m_fname = rw.fname; m_lineno = rw.lineno; if (!Xcheck_accessX(rw,map_info)) return; XatomicX(1); m_write_in_progress = 1'b1; rw.value[0] &= ((1 << m_n_bits)-1); value = rw.value[0]; rw.status = UVM_IS_OK; begin : pre_write_callbacks uvm_reg_data_t msk; int lsb; foreach (m_fields[i]) begin uvm_reg_field_cb_iter cbs = new(m_fields[i]); uvm_reg_field f = m_fields[i]; lsb = f.get_lsb_pos(); msk = ((1<> lsb; f.pre_write(rw); for (uvm_reg_cbs cb=cbs.first(); cb!=null; cb=cbs.next()) begin rw.element = f; rw.element_kind = UVM_FIELD; cb.pre_write(rw); end value = (value & ~msk) | (rw.value[0] << lsb); end end rw.element = this; rw.element_kind = UVM_REG; rw.value[0] = value; pre_write(rw); for (uvm_reg_cbs cb=cbs.first(); cb!=null; cb=cbs.next()) cb.pre_write(rw); if (rw.status != UVM_IS_OK) begin m_write_in_progress = 1'b0; XatomicX(0); return; end case (rw.path) UVM_BACKDOOR: begin uvm_reg_data_t final_val; uvm_reg_backdoor bkdr = get_backdoor(); if (rw.map != null) rw.local_map = rw.map; else rw.local_map = get_default_map(); value = rw.value[0]; rw.kind = UVM_READ; if (bkdr != null) bkdr.read(rw); else backdoor_read(rw); if (rw.status == UVM_NOT_OK) begin m_write_in_progress = 1'b0; return; end begin foreach (m_fields[i]) begin uvm_reg_data_t field_val; int lsb = m_fields[i].get_lsb_pos(); int sz = m_fields[i].get_n_bits(); field_val = m_fields[i].XpredictX((rw.value[0] >> lsb) & ((1<> lsb) & ((1<> f.get_lsb_pos()) & ((1<> f.get_lsb_pos()) & ((1<> hdl_concat.slices[j].offset; slice &= (1 << hdl_concat.slices[j].size)-1; ok &= uvm_hdl_deposit(hdl_concat.slices[j].path, slice); end end end rw.status = (ok ? UVM_IS_OK : UVM_NOT_OK); endtask task uvm_reg::backdoor_read (uvm_reg_item rw); rw.status = backdoor_read_func(rw); endtask function uvm_status_e uvm_reg::backdoor_read_func(uvm_reg_item rw); uvm_hdl_path_concat paths[$]; uvm_reg_data_t val; bit ok=1; get_full_hdl_path(paths,rw.bd_kind); foreach (paths[i]) begin uvm_hdl_path_concat hdl_concat = paths[i]; val = 0; foreach (hdl_concat.slices[j]) begin begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"RegMem")) uvm_report_info ("RegMem", $sformatf("backdoor_read from %s ", hdl_concat.slices[j].path), UVM_DEBUG, "t/uvm/src/reg/uvm_reg.svh", 2184, "", 1); end if (hdl_concat.slices[j].offset < 0) begin ok &= uvm_hdl_read(hdl_concat.slices[j].path,val); continue; end begin uvm_reg_data_t slice; int k = hdl_concat.slices[j].offset; ok &= uvm_hdl_read(hdl_concat.slices[j].path, slice); repeat (hdl_concat.slices[j].size) begin val[k++] = slice[0]; slice >>= 1; end end end val &= (1 << m_n_bits)-1; if (i == 0) rw.value[0] = val; if (val != rw.value[0]) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Backdoor read of register %s with multiple HDL copies: values are not the same: %0h at path '%s', and %0h at path '%s'. Returning first value.", get_full_name(), rw.value[0], uvm_hdl_concat2string(paths[0]), val, uvm_hdl_concat2string(paths[i])), UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 2212, "", 1); end return UVM_NOT_OK; end begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"RegMem")) uvm_report_info ("RegMem", $sformatf("returned backdoor value 0x%0x",rw.value[0]), UVM_DEBUG, "t/uvm/src/reg/uvm_reg.svh", 2216, "", 1); end end rw.status = (ok) ? UVM_IS_OK : UVM_NOT_OK; return rw.status; endfunction task uvm_reg::poke(output uvm_status_e status, input uvm_reg_data_t value, input string kind = "", input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_backdoor bkdr = get_backdoor(); uvm_reg_item rw; m_fname = fname; m_lineno = lineno; if (bkdr == null && !has_hdl_path(kind)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"No backdoor access available to poke register '",get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 2244, "", 1); end status = UVM_NOT_OK; return; end if (!m_is_locked_by_field) XatomicX(1); rw = uvm_reg_item::type_id::create("reg_poke_item",,get_full_name()); rw.element = this; rw.path = UVM_BACKDOOR; rw.element_kind = UVM_REG; rw.kind = UVM_WRITE; rw.bd_kind = kind; rw.value[0] = value & ((1 << m_n_bits)-1); rw.parent = parent; rw.extension = extension; rw.fname = fname; rw.lineno = lineno; if (bkdr != null) bkdr.write(rw); else backdoor_write(rw); status = rw.status; begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("Poked register \"%s\": 'h%h", get_full_name(), value), UVM_HIGH, "t/uvm/src/reg/uvm_reg.svh", 2273, "", 1); end do_predict(rw, UVM_PREDICT_WRITE); if (!m_is_locked_by_field) XatomicX(0); endtask: poke task uvm_reg::peek(output uvm_status_e status, output uvm_reg_data_t value, input string kind = "", input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_backdoor bkdr = get_backdoor(); uvm_reg_item rw; m_fname = fname; m_lineno = lineno; if (bkdr == null && !has_hdl_path(kind)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("No backdoor access available to peek register \"%s\"", get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 2301, "", 1); end status = UVM_NOT_OK; return; end if(!m_is_locked_by_field) XatomicX(1); rw = uvm_reg_item::type_id::create("mem_peek_item",,get_full_name()); rw.element = this; rw.path = UVM_BACKDOOR; rw.element_kind = UVM_REG; rw.kind = UVM_READ; rw.bd_kind = kind; rw.parent = parent; rw.extension = extension; rw.fname = fname; rw.lineno = lineno; if (bkdr != null) bkdr.read(rw); else backdoor_read(rw); status = rw.status; value = rw.value[0]; begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("Peeked register \"%s\": 'h%h", get_full_name(), value), UVM_HIGH, "t/uvm/src/reg/uvm_reg.svh", 2330, "", 1); end do_predict(rw, UVM_PREDICT_READ); if (!m_is_locked_by_field) XatomicX(0); endtask: peek function bit uvm_reg::do_check(input uvm_reg_data_t expected, input uvm_reg_data_t actual, uvm_reg_map map); uvm_reg_data_t valid_bits_mask = 0; foreach(m_fields[i]) begin string acc = m_fields[i].get_access(map); acc = acc.substr(0, 1); if (!(m_fields[i].get_compare() == UVM_NO_CHECK ||acc == "WO")) begin valid_bits_mask |= ((1 << m_fields[i].get_n_bits())-1)<< m_fields[i].get_lsb_pos(); end end if ((actual&valid_bits_mask) === (expected&valid_bits_mask)) return 1; begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Register \"%s\" value read from DUT (0x%h) does not match mirrored value (0x%h) (valid bit mask = 0x%h)", get_full_name(), actual, expected,valid_bits_mask), UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 2357, "", 1); end foreach(m_fields[i]) begin string acc = m_fields[i].get_access(map); acc = acc.substr(0, 1); if (!(m_fields[i].get_compare() == UVM_NO_CHECK || acc == "WO")) begin uvm_reg_data_t mask = ((1 << m_fields[i].get_n_bits())-1); uvm_reg_data_t val = actual >> m_fields[i].get_lsb_pos() & mask; uvm_reg_data_t exp = expected >> m_fields[i].get_lsb_pos() & mask; if (val !== exp) begin begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("Field %s (%s[%0d:%0d]) mismatch read=%0d'h%0h mirrored=%0d'h%0h ", m_fields[i].get_name(), get_full_name(), m_fields[i].get_lsb_pos() + m_fields[i].get_n_bits() - 1, m_fields[i].get_lsb_pos(), m_fields[i].get_n_bits(), val, m_fields[i].get_n_bits(), exp), UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 2376, "", 1); end end end end return 0; endfunction task uvm_reg::mirror(output uvm_status_e status, input uvm_check_e check = UVM_NO_CHECK, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_data_t v; uvm_reg_data_t exp; uvm_reg_backdoor bkdr = get_backdoor(); XatomicX(1); m_fname = fname; m_lineno = lineno; if (path == UVM_DEFAULT_DOOR) path = m_parent.get_default_door(); if (path == UVM_BACKDOOR && (bkdr != null || has_hdl_path())) map = uvm_reg_map::backdoor(); else map = get_local_map(map); if (map == null) return; if (check == UVM_CHECK) exp = get_mirrored_value(); XreadX(status, v, path, map, parent, prior, extension, fname, lineno); if (status == UVM_NOT_OK) begin XatomicX(0); return; end if (check == UVM_CHECK) void'(do_check(exp, v, map)); XatomicX(0); endtask: mirror task uvm_reg::XatomicX(bit on); process m_reg_process; m_reg_process=process::self(); if (on) begin if (m_reg_process == m_process) return; m_atomic.get(1); m_process = m_reg_process; end else begin void'(m_atomic.try_get(1)); m_atomic.put(1); m_process = null; end endtask: XatomicX function string uvm_reg::convert2string(); string res_str; string t_str; bit with_debug_info; string prefix; $sformat(convert2string, "Register %s -- %0d bytes, mirror value:'h%h", get_full_name(), get_n_bytes(),get()); if (m_maps.num()==0) convert2string = {convert2string, " (unmapped)\n"}; else convert2string = {convert2string, "\n"}; foreach (m_maps[map]) begin uvm_reg_map parent_map = map; int unsigned offset; while (parent_map != null) begin uvm_reg_map this_map = parent_map; parent_map = this_map.get_parent_map(); offset = parent_map == null ? this_map.get_base_addr(UVM_NO_HIER) : parent_map.get_submap_offset(this_map); prefix = {prefix, " "}; begin uvm_endianness_e e = this_map.get_endian(); $sformat(convert2string, "%sMapped in '%s' -- %d bytes, %s, offset 'h%0h\n", prefix, this_map.get_full_name(), this_map.get_n_bytes(), e.name(), offset); end end end prefix = " "; foreach(m_fields[i]) begin $sformat(convert2string, "%s\n%s", convert2string, m_fields[i].convert2string()); end if (m_read_in_progress == 1'b1) begin if (m_fname != "" && m_lineno != 0) $sformat(res_str, "%s:%0d ",m_fname, m_lineno); convert2string = {convert2string, "\n", res_str, "currently executing read method"}; end if ( m_write_in_progress == 1'b1) begin if (m_fname != "" && m_lineno != 0) $sformat(res_str, "%s:%0d ",m_fname, m_lineno); convert2string = {convert2string, "\n", res_str, "currently executing write method"}; end endfunction: convert2string function void uvm_reg::do_print (uvm_printer printer); uvm_reg_field f[$]; super.do_print(printer); get_fields(f); foreach(f[i]) printer.print_generic(f[i].get_name(),f[i].get_type_name(),-2,f[i].convert2string()); endfunction function uvm_object uvm_reg::clone(); begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"RegModel")) uvm_report_fatal ("RegModel", "RegModel registers cannot be cloned", UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 2528, "", 1); end return null; endfunction function void uvm_reg::do_copy(uvm_object rhs); begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"RegModel")) uvm_report_fatal ("RegModel", "RegModel registers cannot be copied", UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 2535, "", 1); end endfunction function bit uvm_reg::do_compare (uvm_object rhs, uvm_comparer comparer); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", "RegModel registers cannot be compared", UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 2543, "", 1); end return 0; endfunction function void uvm_reg::do_pack (uvm_packer packer); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", "RegModel registers cannot be packed", UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 2551, "", 1); end endfunction function void uvm_reg::do_unpack (uvm_packer packer); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", "RegModel registers cannot be unpacked", UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 2558, "", 1); end endfunction typedef class uvm_reg_indirect_ftdr_seq; class uvm_reg_indirect_data extends uvm_reg; protected uvm_reg m_idx; protected uvm_reg m_tbl[]; function new(string name = "uvm_reg_indirect", int unsigned n_bits, int has_cover); super.new(name,n_bits,has_cover); endfunction: new virtual function void build(); endfunction: build function void configure (uvm_reg idx, uvm_reg reg_a[], uvm_reg_block blk_parent, uvm_reg_file regfile_parent = null); super.configure(blk_parent, regfile_parent, ""); m_idx = idx; m_tbl = reg_a; uvm_resource_db#(bit)::set({"REG::", get_full_name()}, "NO_REG_TESTS", 1); foreach (m_maps[map]) begin add_frontdoors(map); end endfunction virtual function void add_map(uvm_reg_map map); super.add_map(map); add_frontdoors(map); endfunction local function void add_frontdoors(uvm_reg_map map); foreach (m_tbl[i]) begin uvm_reg_indirect_ftdr_seq fd; if (m_tbl[i] == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,get_full_name())) uvm_report_error (get_full_name(), $sformatf("Indirect register #%0d is NULL", i), UVM_NONE, "t/uvm/src/reg/uvm_reg_indirect.svh", 90, "", 1); end continue; end fd = new(m_idx, i, this); if (m_tbl[i].is_in_map(map)) m_tbl[i].set_frontdoor(fd, map); else map.add_reg(m_tbl[i], -1, "RW", 1, fd); end endfunction virtual function void do_predict (uvm_reg_item rw, uvm_predict_e kind = UVM_PREDICT_DIRECT, uvm_reg_byte_en_t be = -1); if (m_idx.get() >= m_tbl.size()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,get_full_name())) uvm_report_error (get_full_name(), $sformatf("Address register %s has a value (%0d) greater than the maximum indirect register array size (%0d)", m_idx.get_full_name(), m_idx.get(), m_tbl.size()), UVM_NONE, "t/uvm/src/reg/uvm_reg_indirect.svh", 105, "", 1); end rw.status = UVM_NOT_OK; return; end begin int unsigned idx = m_idx.get(); m_tbl[idx].do_predict(rw, kind, be); end endfunction virtual function uvm_reg_map get_local_map(uvm_reg_map map); return m_idx.get_local_map(map); endfunction virtual function void add_field (uvm_reg_field field); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,get_full_name())) uvm_report_error (get_full_name(), "Cannot add field to an indirect data access register", UVM_NONE, "t/uvm/src/reg/uvm_reg_indirect.svh", 126, "", 1); end endfunction virtual function void set (uvm_reg_data_t value, string fname = "", int lineno = 0); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,get_full_name())) uvm_report_error (get_full_name(), "Cannot set() an indirect data access register", UVM_NONE, "t/uvm/src/reg/uvm_reg_indirect.svh", 132, "", 1); end endfunction virtual function uvm_reg_data_t get(string fname = "", int lineno = 0); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,get_full_name())) uvm_report_error (get_full_name(), "Cannot get() an indirect data access register", UVM_NONE, "t/uvm/src/reg/uvm_reg_indirect.svh", 137, "", 1); end return 0; endfunction virtual function uvm_reg get_indirect_reg(string fname = "", int lineno = 0); int unsigned idx = m_idx.get_mirrored_value(); return(m_tbl[idx]); endfunction virtual function bit needs_update(); return 0; endfunction virtual task write(output uvm_status_e status, input uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); if (path == UVM_DEFAULT_DOOR) begin uvm_reg_block blk = get_parent(); path = blk.get_default_door(); end if (path == UVM_BACKDOOR) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,get_full_name())) uvm_report_warning (get_full_name(), "Cannot backdoor-write an indirect data access register. Switching to frontdoor.", UVM_NONE, "t/uvm/src/reg/uvm_reg_indirect.svh", 167, "", 1); end path = UVM_FRONTDOOR; end begin uvm_reg_item rw; XatomicX(1); rw = uvm_reg_item::type_id::create("write_item",,get_full_name()); rw.element = this; rw.element_kind = UVM_REG; rw.kind = UVM_WRITE; rw.value[0] = value; rw.path = path; rw.map = map; rw.parent = parent; rw.prior = prior; rw.extension = extension; rw.fname = fname; rw.lineno = lineno; do_write(rw); status = rw.status; XatomicX(0); end endtask virtual task read(output uvm_status_e status, output uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); if (path == UVM_DEFAULT_DOOR) begin uvm_reg_block blk = get_parent(); path = blk.get_default_door(); end if (path == UVM_BACKDOOR) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,get_full_name())) uvm_report_warning (get_full_name(), "Cannot backdoor-read an indirect data access register. Switching to frontdoor.", UVM_NONE, "t/uvm/src/reg/uvm_reg_indirect.svh", 214, "", 1); end path = UVM_FRONTDOOR; end super.read(status, value, path, map, parent, prior, extension, fname, lineno); endtask virtual task poke(output uvm_status_e status, input uvm_reg_data_t value, input string kind = "", input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,get_full_name())) uvm_report_error (get_full_name(), "Cannot poke() an indirect data access register", UVM_NONE, "t/uvm/src/reg/uvm_reg_indirect.svh", 228, "", 1); end status = UVM_NOT_OK; endtask virtual task peek(output uvm_status_e status, output uvm_reg_data_t value, input string kind = "", input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,get_full_name())) uvm_report_error (get_full_name(), "Cannot peek() an indirect data access register", UVM_NONE, "t/uvm/src/reg/uvm_reg_indirect.svh", 239, "", 1); end status = UVM_NOT_OK; endtask virtual task update(output uvm_status_e status, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); status = UVM_IS_OK; endtask virtual task mirror(output uvm_status_e status, input uvm_check_e check = UVM_NO_CHECK, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); status = UVM_IS_OK; endtask endclass : uvm_reg_indirect_data class uvm_reg_indirect_ftdr_seq extends uvm_reg_frontdoor; local uvm_reg m_addr_reg; local uvm_reg m_data_reg; local int m_idx; function new(uvm_reg addr_reg, int idx, uvm_reg data_reg); super.new("uvm_reg_indirect_ftdr_seq"); m_addr_reg = addr_reg; m_idx = idx; m_data_reg = data_reg; endfunction: new virtual task body(); uvm_reg_item rw; $cast(rw,rw_info.clone()); rw.element = m_addr_reg; rw.kind = UVM_WRITE; rw.value[0]= m_idx; m_addr_reg.XatomicX(1); m_data_reg.XatomicX(1); m_addr_reg.do_write(rw); if (rw.status == UVM_NOT_OK) return; $cast(rw,rw_info.clone()); rw.element = m_data_reg; if (rw_info.kind == UVM_WRITE) m_data_reg.do_write(rw); else begin m_data_reg.do_read(rw); rw_info.value[0] = rw.value[0]; end m_addr_reg.XatomicX(0); m_data_reg.XatomicX(0); rw_info.status = rw.status; endtask endclass class uvm_reg_fifo extends uvm_reg; local uvm_reg_field value; local int m_set_cnt; local int unsigned m_size; rand uvm_reg_data_t fifo[$]; constraint valid_fifo_size { fifo.size() <= m_size; } function new(string name = "reg_fifo", int unsigned size, int unsigned n_bits, int has_cover); super.new(name,n_bits,has_cover); m_size = size; endfunction virtual function void build(); value = uvm_reg_field::type_id::create("value"); value.configure(this, get_n_bits(), 0, "RW", 0, 32'h0, 1, 0, 1); endfunction function void set_compare(uvm_check_e check=UVM_CHECK); value.set_compare(check); endfunction function int unsigned size(); return fifo.size(); endfunction function int unsigned capacity(); return m_size; endfunction virtual function void set(uvm_reg_data_t value, string fname = "", int lineno = 0); value &= ((1 << get_n_bits())-1); if (fifo.size() == m_size) begin return; end super.set(value,fname,lineno); m_set_cnt++; fifo.push_back(this.value.value); endfunction virtual task update(output uvm_status_e status, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_data_t upd; if (!m_set_cnt || fifo.size() == 0) return; m_update_in_progress = 1; for (int i=fifo.size()-m_set_cnt; m_set_cnt > 0; i++, m_set_cnt--) begin if (i >= 0) begin write(status,fifo[i],path,map,parent,prior,extension,fname,lineno); end end m_update_in_progress = 0; endtask virtual function uvm_reg_data_t get(string fname="", int lineno=0); return fifo[0]; endfunction virtual function void do_predict(uvm_reg_item rw, uvm_predict_e kind = UVM_PREDICT_DIRECT, uvm_reg_byte_en_t be = -1); super.do_predict(rw,kind,be); if (rw.status == UVM_NOT_OK) return; case (kind) UVM_PREDICT_WRITE, UVM_PREDICT_DIRECT: begin if (fifo.size() != m_size && !m_update_in_progress) fifo.push_back(this.value.value); end UVM_PREDICT_READ: begin uvm_reg_data_t value = rw.value[0] & ((1 << get_n_bits())-1); uvm_reg_data_t mirror_val; if (fifo.size() == 0) begin return; end mirror_val = fifo.pop_front(); if (this.value.get_compare() == UVM_CHECK && mirror_val != value) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"MIRROR_MISMATCH")) uvm_report_warning ("MIRROR_MISMATCH", $sformatf("Observed DUT read value 'h%0h != mirror value 'h%0h",value,mirror_val), UVM_NONE, "t/uvm/src/reg/uvm_reg_fifo.svh", 237, "", 1); end end end endcase endfunction virtual task pre_write(uvm_reg_item rw); if (m_set_cnt && !m_update_in_progress) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"Needs Update")) uvm_report_error ("Needs Update", "Must call update() after set() and before write()", UVM_NONE, "t/uvm/src/reg/uvm_reg_fifo.svh", 259, "", 1); end rw.status = UVM_NOT_OK; return; end if (fifo.size() >= m_size && !m_update_in_progress) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"FIFO Full")) uvm_report_error ("FIFO Full", "Write to full FIFO ignored", UVM_NONE, "t/uvm/src/reg/uvm_reg_fifo.svh", 264, "", 1); end rw.status = UVM_NOT_OK; return; end endtask virtual task pre_read(uvm_reg_item rw); if (fifo.size() == 0) begin rw.status = UVM_NOT_OK; return; end endtask function void post_randomize(); m_set_cnt = 0; endfunction endclass class uvm_reg_file extends uvm_object; local uvm_reg_block parent; local uvm_reg_file m_rf; local string default_hdl_path = "RTL"; local uvm_object_string_pool #(uvm_queue #(string)) hdl_paths_pool; typedef uvm_object_registry#(uvm_reg_file,"uvm_reg_file") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_reg_file tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_reg_file"; endfunction : type_name virtual function string get_type_name(); return "uvm_reg_file"; endfunction : get_type_name extern function new (string name=""); extern function void configure (uvm_reg_block blk_parent, uvm_reg_file regfile_parent, string hdl_path = ""); extern virtual function string get_full_name(); extern virtual function uvm_reg_block get_parent (); extern virtual function uvm_reg_block get_block (); extern virtual function uvm_reg_file get_regfile (); extern function void clear_hdl_path (string kind = "RTL"); extern function void add_hdl_path (string path, string kind = "RTL"); extern function bit has_hdl_path (string kind = ""); extern function void get_hdl_path (ref string paths[$], input string kind = ""); extern function void get_full_hdl_path (ref string paths[$], input string kind = "", input string separator = "."); extern function void set_default_hdl_path (string kind); extern function string get_default_hdl_path (); extern virtual function void do_print (uvm_printer printer); extern virtual function string convert2string(); extern virtual function uvm_object clone (); extern virtual function void do_copy (uvm_object rhs); extern virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); extern virtual function void do_pack (uvm_packer packer); extern virtual function void do_unpack (uvm_packer packer); endclass: uvm_reg_file function uvm_reg_file::new(string name=""); super.new(name); hdl_paths_pool = new("hdl_paths"); endfunction: new function void uvm_reg_file::configure(uvm_reg_block blk_parent, uvm_reg_file regfile_parent, string hdl_path = ""); if (blk_parent == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/RFILE/CFG/NOBLK")) uvm_report_error ("UVM/RFILE/CFG/NOBLK", {"uvm_reg_file::configure() called without a parent block for instance \"", get_name(), "\" of register file type \"", get_type_name(), "\"."}, UVM_NONE, "t/uvm/src/reg/uvm_reg_file.svh", 148, "", 1); end return; end this.parent = blk_parent; this.m_rf = regfile_parent; this.add_hdl_path(hdl_path); endfunction: configure function uvm_reg_block uvm_reg_file::get_block(); get_block = this.parent; endfunction: get_block function uvm_reg_file uvm_reg_file::get_regfile(); return m_rf; endfunction function void uvm_reg_file::clear_hdl_path(string kind = "RTL"); if (kind == "ALL") begin hdl_paths_pool = new("hdl_paths"); return; end if (kind == "") begin if (m_rf != null) kind = m_rf.get_default_hdl_path(); else kind = parent.get_default_hdl_path(); end if (!hdl_paths_pool.exists(kind)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Unknown HDL Abstraction '",kind,"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_file.svh", 188, "", 1); end return; end hdl_paths_pool.delete(kind); endfunction function void uvm_reg_file::add_hdl_path(string path, string kind = "RTL"); uvm_queue #(string) paths; paths = hdl_paths_pool.get(kind); paths.push_back(path); endfunction function bit uvm_reg_file::has_hdl_path(string kind = ""); if (kind == "") begin if (m_rf != null) kind = m_rf.get_default_hdl_path(); else kind = parent.get_default_hdl_path(); end return hdl_paths_pool.exists(kind); endfunction function void uvm_reg_file::get_hdl_path(ref string paths[$], input string kind = ""); uvm_queue #(string) hdl_paths; if (kind == "") begin if (m_rf != null) kind = m_rf.get_default_hdl_path(); else kind = parent.get_default_hdl_path(); end if (!has_hdl_path(kind)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Register does not have hdl path defined for abstraction '",kind,"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_file.svh", 237, "", 1); end return; end hdl_paths = hdl_paths_pool.get(kind); for (int i=0; i= min_offset; start_offset <= max_offset - len + 1; } constraint uvm_mem_mam_policy_no_overlap { foreach (in_use[i]) { !(start_offset <= in_use[i].Xend_offsetX && start_offset + len - 1 >= in_use[i].Xstart_offsetX); } } endclass class uvm_mem_mam_cfg; rand int unsigned n_bytes; rand bit [63:0] start_offset; rand bit [63:0] end_offset; rand uvm_mem_mam::alloc_mode_e mode; rand uvm_mem_mam::locality_e locality; constraint uvm_mem_mam_cfg_valid { end_offset > start_offset; n_bytes < 64; } endclass function uvm_mem_region::new(bit [63:0] start_offset, bit [63:0] end_offset, int unsigned len, int unsigned n_bytes, uvm_mem_mam parent); this.Xstart_offsetX = start_offset; this.Xend_offsetX = end_offset; this.len = len; this.n_bytes = n_bytes; this.parent = parent; this.XvregX = null; endfunction: new function bit [63:0] uvm_mem_region::get_start_offset(); return this.Xstart_offsetX; endfunction: get_start_offset function bit [63:0] uvm_mem_region::get_end_offset(); return this.Xend_offsetX; endfunction: get_end_offset function int unsigned uvm_mem_region::get_len(); return this.len; endfunction: get_len function int unsigned uvm_mem_region::get_n_bytes(); return this.n_bytes; endfunction: get_n_bytes function string uvm_mem_region::convert2string(); $sformat(convert2string, "['h%h:'h%h]", this.Xstart_offsetX, this.Xend_offsetX); endfunction: convert2string function void uvm_mem_region::release_region(); this.parent.release_region(this); endfunction function uvm_mem uvm_mem_region::get_memory(); return this.parent.get_memory(); endfunction: get_memory function uvm_vreg uvm_mem_region::get_virtual_registers(); return this.XvregX; endfunction: get_virtual_registers function uvm_mem_mam::new(string name, uvm_mem_mam_cfg cfg, uvm_mem mem = null); this.cfg = cfg; this.memory = mem; this.default_alloc = new; endfunction: new function uvm_mem_mam_cfg uvm_mem_mam::reconfigure(uvm_mem_mam_cfg cfg = null); uvm_root top; uvm_coreservice_t cs; if (cfg == null) return this.cfg; cs = uvm_coreservice_t::get(); top = cs.get_root(); if (cfg.n_bytes !== this.cfg.n_bytes) begin top.uvm_report_error("uvm_mem_mam", $sformatf("Cannot reconfigure Memory Allocation Manager with a different number of bytes (%0d !== %0d)", cfg.n_bytes, this.cfg.n_bytes), UVM_LOW); return this.cfg; end foreach (this.in_use[i]) begin if (this.in_use[i].get_start_offset() < cfg.start_offset || this.in_use[i].get_end_offset() > cfg.end_offset) begin top.uvm_report_error("uvm_mem_mam", $sformatf("Cannot reconfigure Memory Allocation Manager with a currently allocated region outside of the managed address range ([%0d:%0d] outside of [%0d:%0d])", this.in_use[i].get_start_offset(), this.in_use[i].get_end_offset(), cfg.start_offset, cfg.end_offset), UVM_LOW); return this.cfg; end end reconfigure = this.cfg; this.cfg = cfg; endfunction: reconfigure function uvm_mem_region uvm_mem_mam::reserve_region(bit [63:0] start_offset, int unsigned n_bytes, string fname = "", int lineno = 0); bit [63:0] end_offset; this.fname = fname; this.lineno = lineno; if (n_bytes == 0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", "Cannot reserve 0 bytes", UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 638, "", 1); end return null; end if (start_offset < this.cfg.start_offset) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot reserve before start of memory space: 'h%h < 'h%h", start_offset, this.cfg.start_offset), UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 644, "", 1); end return null; end end_offset = start_offset + ((n_bytes-1) / this.cfg.n_bytes); n_bytes = (end_offset - start_offset + 1) * this.cfg.n_bytes; if (end_offset > this.cfg.end_offset) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot reserve past end of memory space: 'h%h > 'h%h", end_offset, this.cfg.end_offset), UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 653, "", 1); end return null; end begin if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("Attempting to reserve ['h%h:'h%h]...", start_offset, end_offset), UVM_MEDIUM, "t/uvm/src/reg/uvm_mem_mam.svh", 658, "", 1); end foreach (this.in_use[i]) begin if (start_offset <= this.in_use[i].get_end_offset() && end_offset >= this.in_use[i].get_start_offset()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot reserve ['h%h:'h%h] because it overlaps with %s", start_offset, end_offset, this.in_use[i].convert2string()), UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 669, "", 1); end return null; end if (start_offset > this.in_use[i].get_start_offset()) begin reserve_region = new(start_offset, end_offset, end_offset - start_offset + 1, n_bytes, this); this.in_use.insert(i, reserve_region); return reserve_region; end end reserve_region = new(start_offset, end_offset, end_offset - start_offset + 1, n_bytes, this); this.in_use.push_back(reserve_region); endfunction: reserve_region function uvm_mem_region uvm_mem_mam::request_region(int unsigned n_bytes, uvm_mem_mam_policy alloc = null, string fname = "", int lineno = 0); this.fname = fname; this.lineno = lineno; if (alloc == null) alloc = this.default_alloc; alloc.len = (n_bytes-1) / this.cfg.n_bytes + 1; alloc.min_offset = this.cfg.start_offset; alloc.max_offset = this.cfg.end_offset; alloc.in_use = this.in_use; if (!alloc.randomize()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", "Unable to randomize policy", UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 702, "", 1); end return null; end return reserve_region(alloc.start_offset, n_bytes); endfunction: request_region function void uvm_mem_mam::release_region(uvm_mem_region region); if (region == null) return; foreach (this.in_use[i]) begin if (this.in_use[i] == region) begin this.in_use.delete(i); return; end end begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Attempting to release unallocated region\n", region.convert2string()}, UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 721, "", 1); end endfunction: release_region function void uvm_mem_mam::release_all_regions(); in_use.delete(); endfunction: release_all_regions function string uvm_mem_mam::convert2string(); convert2string = "Allocated memory regions:\n"; foreach (this.in_use[i]) begin $sformat(convert2string, "%s %s\n", convert2string, this.in_use[i].convert2string()); end endfunction: convert2string function uvm_mem_region uvm_mem_mam::for_each(bit reset = 0); if (reset) this.for_each_idx = -1; this.for_each_idx++; if (this.for_each_idx >= this.in_use.size()) begin return null; end return this.in_use[this.for_each_idx]; endfunction: for_each function uvm_mem uvm_mem_mam::get_memory(); return this.memory; endfunction: get_memory task uvm_mem_region::write(output uvm_status_e status, input uvm_reg_addr_t offset, input uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_mem mem = this.parent.get_memory(); this.fname = fname; this.lineno = lineno; if (mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", "Cannot use uvm_mem_region::write() on a region that was allocated by a Memory Allocation Manager that was not associated with a uvm_mem instance", UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 773, "", 1); end status = UVM_NOT_OK; return; end if (offset > this.len) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Attempting to write to an offset outside of the allocated region (%0d > %0d)", offset, this.len), UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 781, "", 1); end status = UVM_NOT_OK; return; end mem.write(status, offset + this.get_start_offset(), value, path, map, parent, prior, extension); endtask: write task uvm_mem_region::read(output uvm_status_e status, input uvm_reg_addr_t offset, output uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_mem mem = this.parent.get_memory(); this.fname = fname; this.lineno = lineno; if (mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", "Cannot use uvm_mem_region::read() on a region that was allocated by a Memory Allocation Manager that was not associated with a uvm_mem instance", UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 806, "", 1); end status = UVM_NOT_OK; return; end if (offset > this.len) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Attempting to read from an offset outside of the allocated region (%0d > %0d)", offset, this.len), UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 814, "", 1); end status = UVM_NOT_OK; return; end mem.read(status, offset + this.get_start_offset(), value, path, map, parent, prior, extension); endtask: read task uvm_mem_region::burst_write(output uvm_status_e status, input uvm_reg_addr_t offset, input uvm_reg_data_t value[], input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_mem mem = this.parent.get_memory(); this.fname = fname; this.lineno = lineno; if (mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", "Cannot use uvm_mem_region::burst_write() on a region that was allocated by a Memory Allocation Manager that was not associated with a uvm_mem instance", UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 839, "", 1); end status = UVM_NOT_OK; return; end if (offset + value.size() > this.len) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Attempting to burst-write to an offset outside of the allocated region (burst to [%0d:%0d] > mem_size %0d)", offset,offset+value.size(),this.len), UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 847, "", 1); end status = UVM_NOT_OK; return; end mem.burst_write(status, offset + get_start_offset(), value, path, map, parent, prior, extension); endtask: burst_write task uvm_mem_region::burst_read(output uvm_status_e status, input uvm_reg_addr_t offset, output uvm_reg_data_t value[], input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_mem mem = this.parent.get_memory(); this.fname = fname; this.lineno = lineno; if (mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", "Cannot use uvm_mem_region::burst_read() on a region that was allocated by a Memory Allocation Manager that was not associated with a uvm_mem instance", UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 873, "", 1); end status = UVM_NOT_OK; return; end if (offset + value.size() > this.len) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Attempting to burst-read to an offset outside of the allocated region (burst to [%0d:%0d] > mem_size %0d)", offset,offset+value.size(),this.len), UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 881, "", 1); end status = UVM_NOT_OK; return; end mem.burst_read(status, offset + get_start_offset(), value, path, map, parent, prior, extension); endtask: burst_read task uvm_mem_region::poke(output uvm_status_e status, input uvm_reg_addr_t offset, input uvm_reg_data_t value, input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_mem mem = this.parent.get_memory(); this.fname = fname; this.lineno = lineno; if (mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", "Cannot use uvm_mem_region::poke() on a region that was allocated by a Memory Allocation Manager that was not associated with a uvm_mem instance", UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 904, "", 1); end status = UVM_NOT_OK; return; end if (offset > this.len) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Attempting to poke to an offset outside of the allocated region (%0d > %0d)", offset, this.len), UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 912, "", 1); end status = UVM_NOT_OK; return; end mem.poke(status, offset + this.get_start_offset(), value, "", parent, extension); endtask: poke task uvm_mem_region::peek(output uvm_status_e status, input uvm_reg_addr_t offset, output uvm_reg_data_t value, input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_mem mem = this.parent.get_memory(); this.fname = fname; this.lineno = lineno; if (mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", "Cannot use uvm_mem_region::peek() on a region that was allocated by a Memory Allocation Manager that was not associated with a uvm_mem instance", UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 933, "", 1); end status = UVM_NOT_OK; return; end if (offset > this.len) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Attempting to peek from an offset outside of the allocated region (%0d > %0d)", offset, this.len), UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 941, "", 1); end status = UVM_NOT_OK; return; end mem.peek(status, offset + this.get_start_offset(), value, "", parent, extension); endtask: peek typedef class uvm_mem_region; typedef class uvm_mem_mam; typedef class uvm_vreg_cbs; class uvm_vreg extends uvm_object; static local bit m_register_cb_uvm_vreg_cbs = uvm_callbacks#(uvm_vreg,uvm_vreg_cbs)::m_register_pair("uvm_vreg","uvm_vreg_cbs"); local bit locked; local uvm_reg_block parent; local int unsigned n_bits; local int unsigned n_used_bits; local uvm_vreg_field fields[$]; local uvm_mem mem; local uvm_reg_addr_t offset; local int unsigned incr; local longint unsigned size; local bit is_static; local uvm_mem_region region; local semaphore atomic; local string fname; local int lineno; local bit read_in_progress; local bit write_in_progress; extern function new(string name, int unsigned n_bits); extern function void configure(uvm_reg_block parent, uvm_mem mem = null, longint unsigned size = 0, uvm_reg_addr_t offset = 0, int unsigned incr = 0); extern virtual function bit implement(longint unsigned n, uvm_mem mem = null, uvm_reg_addr_t offset = 0, int unsigned incr = 0); extern virtual function uvm_mem_region allocate(longint unsigned n, uvm_mem_mam mam, uvm_mem_mam_policy alloc = null); extern virtual function uvm_mem_region get_region(); extern virtual function void release_region(); extern virtual function void set_parent(uvm_reg_block parent); extern function void Xlock_modelX(); extern function void add_field(uvm_vreg_field field); extern task XatomicX(bit on); extern virtual function string get_full_name(); extern virtual function uvm_reg_block get_parent(); extern virtual function uvm_reg_block get_block(); extern virtual function uvm_mem get_memory(); extern virtual function int get_n_maps (); extern function bit is_in_map (uvm_reg_map map); extern virtual function void get_maps (ref uvm_reg_map maps[$]); extern virtual function string get_rights(uvm_reg_map map = null); extern virtual function string get_access(uvm_reg_map map = null); extern virtual function int unsigned get_size(); extern virtual function int unsigned get_n_bytes(); extern virtual function int unsigned get_n_memlocs(); extern virtual function int unsigned get_incr(); extern virtual function void get_fields(ref uvm_vreg_field fields[$]); extern virtual function uvm_vreg_field get_field_by_name(string name); extern virtual function uvm_reg_addr_t get_offset_in_memory(longint unsigned idx); extern virtual function uvm_reg_addr_t get_address(longint unsigned idx, uvm_reg_map map = null); extern virtual task write(input longint unsigned idx, output uvm_status_e status, input uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern virtual task read(input longint unsigned idx, output uvm_status_e status, output uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern virtual task poke(input longint unsigned idx, output uvm_status_e status, input uvm_reg_data_t value, input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern virtual task peek(input longint unsigned idx, output uvm_status_e status, output uvm_reg_data_t value, input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern function void reset(string kind = "HARD"); virtual task pre_write(longint unsigned idx, ref uvm_reg_data_t wdat, ref uvm_door_e path, ref uvm_reg_map map); endtask: pre_write virtual task post_write(longint unsigned idx, uvm_reg_data_t wdat, uvm_door_e path, uvm_reg_map map, ref uvm_status_e status); endtask: post_write virtual task pre_read(longint unsigned idx, ref uvm_door_e path, ref uvm_reg_map map); endtask: pre_read virtual task post_read(longint unsigned idx, ref uvm_reg_data_t rdat, input uvm_door_e path, input uvm_reg_map map, ref uvm_status_e status); endtask: post_read extern virtual function void do_print (uvm_printer printer); extern virtual function string convert2string; extern virtual function uvm_object clone(); extern virtual function void do_copy (uvm_object rhs); extern virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); extern virtual function void do_pack (uvm_packer packer); extern virtual function void do_unpack (uvm_packer packer); endclass: uvm_vreg virtual class uvm_vreg_cbs extends uvm_callback; typedef uvm_abstract_object_registry#(uvm_vreg_cbs,"uvm_vreg_cbs") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_vreg_cbs"; endfunction : type_name virtual function string get_type_name(); return "uvm_vreg_cbs"; endfunction : get_type_name string fname; int lineno; function new(string name = "uvm_reg_cbs"); super.new(name); endfunction virtual task pre_write(uvm_vreg rg, longint unsigned idx, ref uvm_reg_data_t wdat, ref uvm_door_e path, ref uvm_reg_map map); endtask: pre_write virtual task post_write(uvm_vreg rg, longint unsigned idx, uvm_reg_data_t wdat, uvm_door_e path, uvm_reg_map map, ref uvm_status_e status); endtask: post_write virtual task pre_read(uvm_vreg rg, longint unsigned idx, ref uvm_door_e path, ref uvm_reg_map map); endtask: pre_read virtual task post_read(uvm_vreg rg, longint unsigned idx, ref uvm_reg_data_t rdat, input uvm_door_e path, input uvm_reg_map map, ref uvm_status_e status); endtask: post_read endclass: uvm_vreg_cbs typedef uvm_callbacks#(uvm_vreg, uvm_vreg_cbs) uvm_vreg_cb ; typedef uvm_callback_iter#(uvm_vreg, uvm_vreg_cbs) uvm_vreg_cb_iter ; function uvm_vreg::new(string name, int unsigned n_bits); super.new(name); if (n_bits == 0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Virtual register \"%s\" cannot have 0 bits", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 425, "", 1); end n_bits = 1; end if (n_bits > 64) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Virtual register \"%s\" cannot have more than %0d bits (%0d)", this.get_full_name(), 64, n_bits), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 429, "", 1); end n_bits = 64; end this.n_bits = n_bits; this.locked = 0; endfunction: new function void uvm_vreg::configure(uvm_reg_block parent, uvm_mem mem = null, longint unsigned size = 0, uvm_reg_addr_t offset = 0, int unsigned incr = 0); this.parent = parent; this.n_used_bits = 0; if (mem != null) begin void'(this.implement(size, mem, offset, incr)); this.is_static = 1; end else begin this.mem = null; this.is_static = 0; end this.parent.add_vreg(this); this.atomic = new(1); endfunction: configure function void uvm_vreg::Xlock_modelX(); if (this.locked) return; this.locked = 1; endfunction: Xlock_modelX function void uvm_vreg::add_field(uvm_vreg_field field); int offset; int idx; if (this.locked) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", "Cannot add virtual field to locked virtual register model", UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 473, "", 1); end return; end if (field == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"RegModel")) uvm_report_fatal ("RegModel", "Attempting to register NULL virtual field", UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 477, "", 1); end offset = field.get_lsb_pos_in_register(); idx = -1; foreach (this.fields[i]) begin if (offset < this.fields[i].get_lsb_pos_in_register()) begin int j = i; this.fields.insert(j, field); idx = i; break; end end if (idx < 0) begin this.fields.push_back(field); idx = this.fields.size()-1; end this.n_used_bits += field.get_n_bits(); if (this.n_used_bits > this.n_bits) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Virtual fields use more bits (%0d) than available in virtual register \"%s\" (%0d)", this.n_used_bits, this.get_full_name(), this.n_bits), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 501, "", 1); end end if (idx > 0) begin if (this.fields[idx-1].get_lsb_pos_in_register() + this.fields[idx-1].get_n_bits() > offset) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Field %s overlaps field %s in virtual register \"%s\"", this.fields[idx-1].get_name(), field.get_name(), this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 511, "", 1); end end end if (idx < this.fields.size()-1) begin if (offset + field.get_n_bits() > this.fields[idx+1].get_lsb_pos_in_register()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Field %s overlaps field %s in virtual register \"%s\"", field.get_name(), this.fields[idx+1].get_name(), this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 520, "", 1); end end end endfunction: add_field task uvm_vreg::XatomicX(bit on); if (on) this.atomic.get(1); else begin void'(this.atomic.try_get(1)); this.atomic.put(1); end endtask: XatomicX function void uvm_vreg::reset(string kind = "HARD"); void'(this.atomic.try_get(1)); this.atomic.put(1); endfunction: reset function string uvm_vreg::get_full_name(); uvm_reg_block blk; get_full_name = this.get_name(); blk = this.get_block(); if (blk == null) return get_full_name; if (blk.get_parent() == null) return get_full_name; get_full_name = {this.parent.get_full_name(), ".", get_full_name}; endfunction: get_full_name function void uvm_vreg::set_parent(uvm_reg_block parent); this.parent = parent; endfunction: set_parent function uvm_reg_block uvm_vreg::get_parent(); get_parent = this.parent; endfunction: get_parent function uvm_reg_block uvm_vreg::get_block(); get_block = this.parent; endfunction: get_block function bit uvm_vreg::implement(longint unsigned n, uvm_mem mem = null, uvm_reg_addr_t offset = 0, int unsigned incr = 0); uvm_mem_region region; if(n < 1) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Attempting to implement virtual register \"%s\" with a subscript less than one doesn't make sense",this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 579, "", 1); end return 0; end if (mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Attempting to implement virtual register \"%s\" using a NULL uvm_mem reference", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 584, "", 1); end return 0; end if (this.is_static) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Virtual register \"%s\" is static and cannot be dynamically implemented", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 589, "", 1); end return 0; end if (mem.get_block() != this.parent) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Attempting to implement virtual register \"%s\" on memory \"%s\" in a different block", this.get_full_name(), mem.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 596, "", 1); end return 0; end begin int min_incr = (this.get_n_bytes()-1) / mem.get_n_bytes() + 1; if (incr == 0) incr = min_incr; if (min_incr > incr) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Virtual register \"%s\" increment is too small (%0d): Each virtual register requires at least %0d locations in memory \"%s\".", this.get_full_name(), incr, min_incr, mem.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 606, "", 1); end return 0; end end if (offset + (n * incr) > mem.get_size()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Given Offset for Virtual register \"%s[%0d]\" is too big for memory %s@'h%0h", this.get_full_name(), n, mem.get_full_name(), offset), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 613, "", 1); end return 0; end region = mem.mam.reserve_region(offset,n*incr*mem.get_n_bytes()); if (region == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Could not allocate a memory region for virtual register \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 620, "", 1); end return 0; end if (this.mem != null) begin begin if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("Virtual register \"%s\" is being moved re-implemented from %s@'h%0h to %s@'h%0h", this.get_full_name(), this.mem.get_full_name(), this.offset, mem.get_full_name(), offset), UVM_MEDIUM, "t/uvm/src/reg/uvm_vreg.svh", 629, "", 1); end this.release_region(); end this.region = region; this.mem = mem; this.size = n; this.offset = offset; this.incr = incr; this.mem.Xadd_vregX(this); return 1; endfunction: implement function uvm_mem_region uvm_vreg::allocate(longint unsigned n, uvm_mem_mam mam, uvm_mem_mam_policy alloc=null); uvm_mem mem; if(n < 1) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Attempting to implement virtual register \"%s\" with a subscript less than one doesn't make sense",this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 652, "", 1); end return null; end if (mam == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Attempting to implement virtual register \"%s\" using a NULL uvm_mem_mam reference", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 657, "", 1); end return null; end if (this.is_static) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Virtual register \"%s\" is static and cannot be dynamically allocated", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 662, "", 1); end return null; end mem = mam.get_memory(); if (mem.get_block() != this.parent) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Attempting to allocate virtual register \"%s\" on memory \"%s\" in a different block", this.get_full_name(), mem.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 670, "", 1); end return null; end begin int min_incr = (this.get_n_bytes()-1) / mem.get_n_bytes() + 1; if (incr == 0) incr = min_incr; if (min_incr < incr) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Virtual register \"%s\" increment is too small (%0d): Each virtual register requires at least %0d locations in memory \"%s\".", this.get_full_name(), incr, min_incr, mem.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 680, "", 1); end return null; end end allocate = mam.request_region(n*incr*mem.get_n_bytes(), alloc); if (allocate == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Could not allocate a memory region for virtual register \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 688, "", 1); end return null; end if (this.mem != null) begin begin if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("Virtual register \"%s\" is being moved from %s@'h%0h to %s@'h%0h", this.get_full_name(), this.mem.get_full_name(), this.offset, mem.get_full_name(), allocate.get_start_offset()), UVM_MEDIUM, "t/uvm/src/reg/uvm_vreg.svh", 698, "", 1); end this.release_region(); end this.region = allocate; this.mem = mam.get_memory(); this.offset = allocate.get_start_offset(); this.size = n; this.incr = incr; this.mem.Xadd_vregX(this); endfunction: allocate function uvm_mem_region uvm_vreg::get_region(); return this.region; endfunction: get_region function void uvm_vreg::release_region(); if (this.is_static) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Virtual register \"%s\" is static and cannot be dynamically released", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 721, "", 1); end return; end if (this.mem != null) this.mem.Xdelete_vregX(this); if (this.region != null) begin this.region.release_region(); end this.region = null; this.mem = null; this.size = 0; this.offset = 0; this.reset(); endfunction: release_region function uvm_mem uvm_vreg::get_memory(); return this.mem; endfunction: get_memory function uvm_reg_addr_t uvm_vreg::get_offset_in_memory(longint unsigned idx); if (this.mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot call uvm_vreg::get_offset_in_memory() on unimplemented virtual register \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 749, "", 1); end return 0; end return this.offset + idx * this.incr; endfunction function uvm_reg_addr_t uvm_vreg::get_address(longint unsigned idx, uvm_reg_map map = null); if (this.mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot get address of of unimplemented virtual register \"%s\".", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 760, "", 1); end return 0; end return this.mem.get_address(this.get_offset_in_memory(idx), map); endfunction: get_address function int unsigned uvm_vreg::get_size(); if (this.size == 0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot call uvm_vreg::get_size() on unimplemented virtual register \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 771, "", 1); end return 0; end return this.size; endfunction: get_size function int unsigned uvm_vreg::get_n_bytes(); return ((this.n_bits-1) / 8) + 1; endfunction: get_n_bytes function int unsigned uvm_vreg::get_n_memlocs(); if (this.mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot call uvm_vreg::get_n_memlocs() on unimplemented virtual register \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 787, "", 1); end return 0; end return (this.get_n_bytes()-1) / this.mem.get_n_bytes() + 1; endfunction: get_n_memlocs function int unsigned uvm_vreg::get_incr(); if (this.incr == 0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot call uvm_vreg::get_incr() on unimplemented virtual register \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 798, "", 1); end return 0; end return this.incr; endfunction: get_incr function int uvm_vreg::get_n_maps(); if (this.mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot call uvm_vreg::get_n_maps() on unimplemented virtual register \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 809, "", 1); end return 0; end return this.mem.get_n_maps(); endfunction: get_n_maps function void uvm_vreg::get_maps(ref uvm_reg_map maps[$]); if (this.mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot call uvm_vreg::get_maps() on unimplemented virtual register \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 820, "", 1); end return; end this.mem.get_maps(maps); endfunction: get_maps function bit uvm_vreg::is_in_map(uvm_reg_map map); if (this.mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot call uvm_vreg::is_in_map() on unimplemented virtual register \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 831, "", 1); end return 0; end return this.mem.is_in_map(map); endfunction function string uvm_vreg::get_access(uvm_reg_map map = null); if (this.mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot call uvm_vreg::get_rights() on unimplemented virtual register \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 842, "", 1); end return "RW"; end return this.mem.get_access(map); endfunction: get_access function string uvm_vreg::get_rights(uvm_reg_map map = null); if (this.mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot call uvm_vreg::get_rights() on unimplemented virtual register \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 853, "", 1); end return "RW"; end return this.mem.get_rights(map); endfunction: get_rights function void uvm_vreg::get_fields(ref uvm_vreg_field fields[$]); foreach(this.fields[i]) fields.push_back(this.fields[i]); endfunction: get_fields function uvm_vreg_field uvm_vreg::get_field_by_name(string name); foreach (this.fields[i]) begin if (this.fields[i].get_name() == name) begin return this.fields[i]; end end begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", $sformatf("Unable to locate field \"%s\" in virtual register \"%s\".", name, this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 874, "", 1); end get_field_by_name = null; endfunction: get_field_by_name task uvm_vreg::write(input longint unsigned idx, output uvm_status_e status, input uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_vreg_cb_iter cbs = new(this); uvm_reg_addr_t addr; uvm_reg_data_t tmp; uvm_reg_data_t msk; int lsb; this.write_in_progress = 1'b1; this.fname = fname; this.lineno = lineno; if (this.mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot write to unimplemented virtual register \"%s\".", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 899, "", 1); end status = UVM_NOT_OK; return; end if (path == UVM_DEFAULT_DOOR) path = this.parent.get_default_door(); foreach (fields[i]) begin uvm_vreg_field_cb_iter cbs = new(fields[i]); uvm_vreg_field f = fields[i]; lsb = f.get_lsb_pos_in_register(); msk = ((1<> lsb; f.pre_write(idx, tmp, path, map); for (uvm_vreg_field_cbs cb = cbs.first(); cb != null; cb = cbs.next()) begin cb.fname = this.fname; cb.lineno = this.lineno; cb.pre_write(f, idx, tmp, path, map); end value = (value & ~msk) | (tmp << lsb); end this.pre_write(idx, value, path, map); for (uvm_vreg_cbs cb = cbs.first(); cb != null; cb = cbs.next()) begin cb.fname = this.fname; cb.lineno = this.lineno; cb.pre_write(this, idx, value, path, map); end addr = this.offset + (idx * this.incr); lsb = 0; status = UVM_IS_OK; for (int i = 0; i < this.get_n_memlocs(); i++) begin uvm_status_e s; msk = ((1<<(this.mem.get_n_bytes()*8))-1) << lsb; tmp = (value & msk) >> lsb; this.mem.write(s, addr + i, tmp, path, map , parent, , extension, fname, lineno); if (s != UVM_IS_OK && s != UVM_HAS_X) status = s; lsb += this.mem.get_n_bytes() * 8; end for (uvm_vreg_cbs cb = cbs.first(); cb != null; cb = cbs.next()) begin cb.fname = this.fname; cb.lineno = this.lineno; cb.post_write(this, idx, value, path, map, status); end this.post_write(idx, value, path, map, status); foreach (fields[i]) begin uvm_vreg_field_cb_iter cbs = new(fields[i]); uvm_vreg_field f = fields[i]; lsb = f.get_lsb_pos_in_register(); msk = ((1<> lsb; for (uvm_vreg_field_cbs cb = cbs.first(); cb != null; cb = cbs.next()) begin cb.fname = this.fname; cb.lineno = this.lineno; cb.post_write(f, idx, tmp, path, map, status); end f.post_write(idx, tmp, path, map, status); value = (value & ~msk) | (tmp << lsb); end begin if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("Wrote virtual register \"%s\"[%0d] via %s with: 'h%h", this.get_full_name(), idx, (path == UVM_FRONTDOOR) ? "frontdoor" : "backdoor", value), UVM_MEDIUM, "t/uvm/src/reg/uvm_vreg.svh", 976, "", 1); end this.write_in_progress = 1'b0; this.fname = ""; this.lineno = 0; endtask: write task uvm_vreg::read(input longint unsigned idx, output uvm_status_e status, output uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_vreg_cb_iter cbs = new(this); uvm_reg_addr_t addr; uvm_reg_data_t tmp; uvm_reg_data_t msk; int lsb; this.read_in_progress = 1'b1; this.fname = fname; this.lineno = lineno; if (this.mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot read from unimplemented virtual register \"%s\".", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 1005, "", 1); end status = UVM_NOT_OK; return; end if (path == UVM_DEFAULT_DOOR) path = this.parent.get_default_door(); foreach (fields[i]) begin uvm_vreg_field_cb_iter cbs = new(fields[i]); uvm_vreg_field f = fields[i]; f.pre_read(idx, path, map); for (uvm_vreg_field_cbs cb = cbs.first(); cb != null; cb = cbs.next()) begin cb.fname = this.fname; cb.lineno = this.lineno; cb.pre_read(f, idx, path, map); end end this.pre_read(idx, path, map); for (uvm_vreg_cbs cb = cbs.first(); cb != null; cb = cbs.next()) begin cb.fname = this.fname; cb.lineno = this.lineno; cb.pre_read(this, idx, path, map); end addr = this.offset + (idx * this.incr); lsb = 0; value = 0; status = UVM_IS_OK; for (int i = 0; i < this.get_n_memlocs(); i++) begin uvm_status_e s; this.mem.read(s, addr + i, tmp, path, map, parent, , extension, fname, lineno); if (s != UVM_IS_OK && s != UVM_HAS_X) status = s; value |= tmp << lsb; lsb += this.mem.get_n_bytes() * 8; end for (uvm_vreg_cbs cb = cbs.first(); cb != null; cb = cbs.next()) begin cb.fname = this.fname; cb.lineno = this.lineno; cb.post_read(this, idx, value, path, map, status); end this.post_read(idx, value, path, map, status); foreach (fields[i]) begin uvm_vreg_field_cb_iter cbs = new(fields[i]); uvm_vreg_field f = fields[i]; lsb = f.get_lsb_pos_in_register(); msk = ((1<> lsb; for (uvm_vreg_field_cbs cb = cbs.first(); cb != null; cb = cbs.next()) begin cb.fname = this.fname; cb.lineno = this.lineno; cb.post_read(f, idx, tmp, path, map, status); end f.post_read(idx, tmp, path, map, status); value = (value & ~msk) | (tmp << lsb); end begin if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("Read virtual register \"%s\"[%0d] via %s: 'h%h", this.get_full_name(), idx, (path == UVM_FRONTDOOR) ? "frontdoor" : "backdoor", value), UVM_MEDIUM, "t/uvm/src/reg/uvm_vreg.svh", 1078, "", 1); end this.read_in_progress = 1'b0; this.fname = ""; this.lineno = 0; endtask: read task uvm_vreg::poke(input longint unsigned idx, output uvm_status_e status, input uvm_reg_data_t value, input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_addr_t addr; uvm_reg_data_t tmp; uvm_reg_data_t msk; int lsb; this.fname = fname; this.lineno = lineno; if (this.mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot poke in unimplemented virtual register \"%s\".", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 1101, "", 1); end status = UVM_NOT_OK; return; end addr = this.offset + (idx * this.incr); lsb = 0; status = UVM_IS_OK; for (int i = 0; i < this.get_n_memlocs(); i++) begin uvm_status_e s; msk = ((1<<(this.mem.get_n_bytes() * 8))-1) << lsb; tmp = (value & msk) >> lsb; this.mem.poke(status, addr + i, tmp, "", parent, extension, fname, lineno); if (s != UVM_IS_OK && s != UVM_HAS_X) status = s; lsb += this.mem.get_n_bytes() * 8; end begin if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("Poked virtual register \"%s\"[%0d] with: 'h%h", this.get_full_name(), idx, value), UVM_MEDIUM, "t/uvm/src/reg/uvm_vreg.svh", 1123, "", 1); end this.fname = ""; this.lineno = 0; endtask: poke task uvm_vreg::peek(input longint unsigned idx, output uvm_status_e status, output uvm_reg_data_t value, input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_addr_t addr; uvm_reg_data_t tmp; uvm_reg_data_t msk; int lsb; this.fname = fname; this.lineno = lineno; if (this.mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot peek in from unimplemented virtual register \"%s\".", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 1145, "", 1); end status = UVM_NOT_OK; return; end addr = this.offset + (idx * this.incr); lsb = 0; value = 0; status = UVM_IS_OK; for (int i = 0; i < this.get_n_memlocs(); i++) begin uvm_status_e s; this.mem.peek(status, addr + i, tmp, "", parent, extension, fname, lineno); if (s != UVM_IS_OK && s != UVM_HAS_X) status = s; value |= tmp << lsb; lsb += this.mem.get_n_bytes() * 8; end begin if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("Peeked virtual register \"%s\"[%0d]: 'h%h", this.get_full_name(), idx, value), UVM_MEDIUM, "t/uvm/src/reg/uvm_vreg.svh", 1166, "", 1); end this.fname = ""; this.lineno = 0; endtask: peek function void uvm_vreg::do_print (uvm_printer printer); super.do_print(printer); printer.print_generic("initiator", parent.get_type_name(), -1, convert2string()); endfunction function string uvm_vreg::convert2string(); string res_str; string t_str; bit with_debug_info; $sformat(convert2string, "Virtual register %s -- ", this.get_full_name()); if (this.size == 0) $sformat(convert2string, "%sunimplemented", convert2string); else begin uvm_reg_map maps[$]; mem.get_maps(maps); $sformat(convert2string, "%s[%0d] in %0s['h%0h+'h%0h]\n", convert2string, this.size, this.mem.get_full_name(), this.offset, this.incr); foreach (maps[i]) begin uvm_reg_addr_t addr0 = this.get_address(0, maps[i]); $sformat(convert2string, " Address in map '%s' -- @'h%0h+%0h", maps[i].get_full_name(), addr0, this.get_address(1, maps[i]) - addr0); end end foreach(this.fields[i]) begin $sformat(convert2string, "%s\n%s", convert2string, this.fields[i].convert2string()); end endfunction: convert2string function uvm_object uvm_vreg::clone(); return null; endfunction function void uvm_vreg::do_copy (uvm_object rhs); endfunction function bit uvm_vreg::do_compare (uvm_object rhs, uvm_comparer comparer); return 0; endfunction function void uvm_vreg::do_pack (uvm_packer packer); endfunction function void uvm_vreg::do_unpack (uvm_packer packer); endfunction class uvm_mem extends uvm_object; typedef enum {UNKNOWNS, ZEROES, ONES, ADDRESS, VALUE, INCR, DECR} init_e; local bit m_locked; local bit m_read_in_progress; local bit m_write_in_progress; local string m_access; local longint unsigned m_size; local uvm_reg_block m_parent; local bit m_maps[uvm_reg_map]; local int unsigned m_n_bits; local uvm_reg_backdoor m_backdoor; local bit m_is_powered_down; local int m_has_cover; local int m_cover_on; local string m_fname; local int m_lineno; local bit m_vregs[uvm_vreg]; local uvm_object_string_pool #(uvm_queue #(uvm_hdl_path_concat)) m_hdl_paths_pool; local static int unsigned m_max_size; extern function new (string name, longint unsigned size, int unsigned n_bits, string access = "RW", int has_coverage = UVM_NO_COVERAGE); extern function void configure (uvm_reg_block parent, string hdl_path = ""); extern virtual function void set_offset (uvm_reg_map map, uvm_reg_addr_t offset, bit unmapped = 0); extern virtual function void set_parent(uvm_reg_block parent); extern function void add_map(uvm_reg_map map); extern function void Xlock_modelX(); extern function void Xadd_vregX(uvm_vreg vreg); extern function void Xdelete_vregX(uvm_vreg vreg); uvm_mem_mam mam; extern virtual function string get_full_name(); extern virtual function uvm_reg_block get_parent (); extern virtual function uvm_reg_block get_block (); extern virtual function int get_n_maps (); extern function bit is_in_map (uvm_reg_map map); extern virtual function void get_maps (ref uvm_reg_map maps[$]); extern function uvm_reg_map get_local_map (uvm_reg_map map); extern function uvm_reg_map get_default_map (); extern virtual function string get_rights (uvm_reg_map map = null); extern virtual function string get_access(uvm_reg_map map = null); extern function longint unsigned get_size(); extern function int unsigned get_n_bytes(); extern function int unsigned get_n_bits(); extern static function int unsigned get_max_size(); extern virtual function void get_virtual_registers(ref uvm_vreg regs[$]); extern virtual function void get_virtual_fields(ref uvm_vreg_field fields[$]); extern virtual function uvm_vreg get_vreg_by_name(string name); extern virtual function uvm_vreg_field get_vfield_by_name(string name); extern virtual function uvm_vreg get_vreg_by_offset(uvm_reg_addr_t offset, uvm_reg_map map = null); extern virtual function uvm_reg_addr_t get_offset (uvm_reg_addr_t offset = 0, uvm_reg_map map = null); extern virtual function uvm_reg_addr_t get_address(uvm_reg_addr_t offset = 0, uvm_reg_map map = null); extern virtual function int get_addresses(uvm_reg_addr_t offset = 0, uvm_reg_map map=null, ref uvm_reg_addr_t addr[]); extern virtual task write(output uvm_status_e status, input uvm_reg_addr_t offset, input uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern virtual task read(output uvm_status_e status, input uvm_reg_addr_t offset, output uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern virtual task burst_write(output uvm_status_e status, input uvm_reg_addr_t offset, input uvm_reg_data_t value[], input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern virtual task burst_read(output uvm_status_e status, input uvm_reg_addr_t offset, ref uvm_reg_data_t value[], input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern virtual task poke(output uvm_status_e status, input uvm_reg_addr_t offset, input uvm_reg_data_t value, input string kind = "", input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern virtual task peek(output uvm_status_e status, input uvm_reg_addr_t offset, output uvm_reg_data_t value, input string kind = "", input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern protected function bit Xcheck_accessX (input uvm_reg_item rw, output uvm_reg_map_info map_info); extern virtual task do_write (uvm_reg_item rw); extern virtual task do_read (uvm_reg_item rw); extern function void set_frontdoor(uvm_reg_frontdoor ftdr, uvm_reg_map map = null, string fname = "", int lineno = 0); extern function uvm_reg_frontdoor get_frontdoor(uvm_reg_map map = null); extern function void set_backdoor (uvm_reg_backdoor bkdr, string fname = "", int lineno = 0); extern function uvm_reg_backdoor get_backdoor(bit inherited = 1); extern function void clear_hdl_path (string kind = "RTL"); extern function void add_hdl_path (uvm_hdl_path_slice slices[], string kind = "RTL"); extern function void add_hdl_path_slice(string name, int offset, int size, bit first = 0, string kind = "RTL"); extern function bit has_hdl_path (string kind = ""); extern function void get_hdl_path (ref uvm_hdl_path_concat paths[$], input string kind = ""); extern function void get_full_hdl_path (ref uvm_hdl_path_concat paths[$], input string kind = "", input string separator = "."); extern function void get_hdl_path_kinds (ref string kinds[$]); extern virtual protected task backdoor_read(uvm_reg_item rw); extern virtual task backdoor_write(uvm_reg_item rw); extern virtual function uvm_status_e backdoor_read_func(uvm_reg_item rw); static local bit m_register_cb_uvm_reg_cbs = uvm_callbacks#(uvm_mem,uvm_reg_cbs)::m_register_pair("uvm_mem","uvm_reg_cbs"); virtual task pre_write(uvm_reg_item rw); endtask virtual task post_write(uvm_reg_item rw); endtask virtual task pre_read(uvm_reg_item rw); endtask virtual task post_read(uvm_reg_item rw); endtask extern protected function uvm_reg_cvr_t build_coverage(uvm_reg_cvr_t models); extern virtual protected function void add_coverage(uvm_reg_cvr_t models); extern virtual function bit has_coverage(uvm_reg_cvr_t models); extern virtual function uvm_reg_cvr_t set_coverage(uvm_reg_cvr_t is_on); extern virtual function bit get_coverage(uvm_reg_cvr_t is_on); protected virtual function void sample(uvm_reg_addr_t offset, bit is_read, uvm_reg_map map); endfunction function void XsampleX(uvm_reg_addr_t addr, bit is_read, uvm_reg_map map); sample(addr, is_read, map); endfunction extern virtual function void do_print (uvm_printer printer); extern virtual function string convert2string(); extern virtual function uvm_object clone(); extern virtual function void do_copy (uvm_object rhs); extern virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); extern virtual function void do_pack (uvm_packer packer); extern virtual function void do_unpack (uvm_packer packer); endclass: uvm_mem function uvm_mem::new (string name, longint unsigned size, int unsigned n_bits, string access = "RW", int has_coverage = UVM_NO_COVERAGE); super.new(name); m_locked = 0; if (n_bits == 0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Memory '",get_full_name(),"' cannot have 0 bits"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 537, "", 1); end n_bits = 1; end m_size = size; m_n_bits = n_bits; m_backdoor = null; m_access = access.toupper(); m_has_cover = has_coverage; m_hdl_paths_pool = new("hdl_paths"); if (n_bits > m_max_size) m_max_size = n_bits; endfunction: new function void uvm_mem::configure(uvm_reg_block parent, string hdl_path=""); if (parent == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"REG/NULL_PARENT")) uvm_report_fatal ("REG/NULL_PARENT", "configure: parent argument is null", UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 559, "", 1); end m_parent = parent; if (m_access != "RW" && m_access != "RO") begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Memory '",get_full_name(),"' can only be RW or RO"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 564, "", 1); end m_access = "RW"; end begin uvm_mem_mam_cfg cfg = new; cfg.n_bytes = ((m_n_bits-1) / 8) + 1; cfg.start_offset = 0; cfg.end_offset = m_size-1; cfg.mode = uvm_mem_mam::GREEDY; cfg.locality = uvm_mem_mam::BROAD; mam = new(get_full_name(), cfg, this); end m_parent.add_mem(this); if (hdl_path != "") add_hdl_path_slice(hdl_path, -1, -1); endfunction: configure function void uvm_mem::set_offset (uvm_reg_map map, uvm_reg_addr_t offset, bit unmapped = 0); uvm_reg_map orig_map = map; if (m_maps.num() > 1 && map == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"set_offset requires a non-null map when memory '", get_full_name(),"' belongs to more than one map."}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 597, "", 1); end return; end map = get_local_map(map); if (map == null) return; map.m_set_mem_offset(this, offset, unmapped); endfunction function void uvm_mem::add_map(uvm_reg_map map); m_maps[map] = 1; endfunction function void uvm_mem::Xlock_modelX(); m_locked = 1; endfunction: Xlock_modelX function string uvm_mem::get_full_name(); if (m_parent == null) return get_name(); return {m_parent.get_full_name(), ".", get_name()}; endfunction: get_full_name function uvm_reg_block uvm_mem::get_block(); return m_parent; endfunction: get_block function int uvm_mem::get_n_maps(); return m_maps.num(); endfunction: get_n_maps function void uvm_mem::get_maps(ref uvm_reg_map maps[$]); foreach (m_maps[map]) maps.push_back(map); endfunction function bit uvm_mem::is_in_map(uvm_reg_map map); if (m_maps.exists(map)) return 1; foreach (m_maps[l]) begin uvm_reg_map local_map=l; uvm_reg_map parent_map = local_map.get_parent_map(); while (parent_map != null) begin if (parent_map == map) return 1; parent_map = parent_map.get_parent_map(); end end return 0; endfunction function uvm_reg_map uvm_mem::get_local_map(uvm_reg_map map); if (map == null) return get_default_map(); if (m_maps.exists(map)) return map; foreach (m_maps[l]) begin uvm_reg_map local_map = l; uvm_reg_map parent_map = local_map.get_parent_map(); while (parent_map != null) begin if (parent_map == map) return local_map; parent_map = parent_map.get_parent_map(); end end begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Memory '",get_full_name(),"' is not contained within map '",map.get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 694, "", 1); end return null; endfunction function uvm_reg_map uvm_mem::get_default_map(); if (m_maps.num() == 0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Memory '",get_full_name(),"' is not registered with any map"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 706, "", 1); end return null; end if (m_maps.num() == 1) begin void'(m_maps.first(get_default_map)); end foreach (m_maps[l]) begin uvm_reg_map map = l; uvm_reg_block blk = map.get_parent(); uvm_reg_map default_map = blk.get_default_map(); if (default_map != null) begin uvm_reg_map local_map = get_local_map(default_map); if (local_map != null) return local_map; end end void'(m_maps.first(get_default_map)); endfunction function string uvm_mem::get_access(uvm_reg_map map = null); get_access = m_access; if (get_n_maps() == 1) return get_access; map = get_local_map(map); if (map == null) return get_access; case (get_rights(map)) "RW": return get_access; "RO": case (get_access) "RW", "RO": get_access = "RO"; "WO": begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"WO memory '",get_full_name(), "' restricted to RO in map '",map.get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 754, "", 1); end default: begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Memory '",get_full_name(), "' has invalid access mode, '",get_access,"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 757, "", 1); end endcase "WO": case (get_access) "RW", "WO": get_access = "WO"; "RO": begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"RO memory '",get_full_name(), "' restricted to WO in map '",map.get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 765, "", 1); end default: begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Memory '",get_full_name(), "' has invalid access mode, '",get_access,"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 768, "", 1); end endcase default: begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Shared memory '",get_full_name(), "' is not shared in map '",map.get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 772, "", 1); end endcase endfunction: get_access function string uvm_mem::get_rights(uvm_reg_map map = null); uvm_reg_map_info info; if (m_maps.num() <= 1) begin return "RW"; end map = get_local_map(map); if (map == null) return "RW"; info = map.get_mem_map_info(this); return info.rights; endfunction: get_rights function uvm_reg_addr_t uvm_mem::get_offset(uvm_reg_addr_t offset = 0, uvm_reg_map map = null); uvm_reg_map_info map_info; uvm_reg_map orig_map = map; map = get_local_map(map); if (map == null) return -1; map_info = map.get_mem_map_info(this); if (map_info.unmapped) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Memory '",get_name(), "' is unmapped in map '", ((orig_map == null) ? map.get_full_name() : orig_map.get_full_name()),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 817, "", 1); end return -1; end return map_info.offset; endfunction: get_offset function void uvm_mem::get_virtual_registers(ref uvm_vreg regs[$]); foreach (m_vregs[vreg]) regs.push_back(vreg); endfunction function void uvm_mem::get_virtual_fields(ref uvm_vreg_field fields[$]); foreach (m_vregs[l]) begin uvm_vreg vreg = l; vreg.get_fields(fields); end endfunction: get_virtual_fields function uvm_vreg_field uvm_mem::get_vfield_by_name(string name); uvm_vreg_field vfields[$]; get_virtual_fields(vfields); foreach (vfields[i]) if (vfields[i].get_name() == name) return vfields[i]; begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Unable to find virtual field '",name, "' in memory '",get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 860, "", 1); end return null; endfunction: get_vfield_by_name function uvm_vreg uvm_mem::get_vreg_by_name(string name); foreach (m_vregs[l]) begin uvm_vreg vreg = l; if (vreg.get_name() == name) return vreg; end begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Unable to find virtual register '",name, "' in memory '",get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 877, "", 1); end return null; endfunction: get_vreg_by_name function uvm_vreg uvm_mem::get_vreg_by_offset(uvm_reg_addr_t offset, uvm_reg_map map = null); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", "uvm_mem::get_vreg_by_offset() not yet implemented", UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 887, "", 1); end return null; endfunction: get_vreg_by_offset function int uvm_mem::get_addresses(uvm_reg_addr_t offset = 0, uvm_reg_map map=null, ref uvm_reg_addr_t addr[]); uvm_reg_map_info map_info; uvm_reg_map system_map; uvm_reg_map orig_map = map; map = get_local_map(map); if (map == null) return 0; map_info = map.get_mem_map_info(this); if (map_info.unmapped) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Memory '",get_name(), "' is unmapped in map '", ((orig_map == null) ? map.get_full_name() : orig_map.get_full_name()),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 913, "", 1); end return 0; end addr = map_info.addr; foreach (addr[i]) addr[i] = addr[i] + map_info.mem_range.stride * offset; return map.get_n_bytes(); endfunction function uvm_reg_addr_t uvm_mem::get_address(uvm_reg_addr_t offset = 0, uvm_reg_map map = null); uvm_reg_addr_t addr[]; void'(get_addresses(offset, map, addr)); return addr[0]; endfunction function longint unsigned uvm_mem::get_size(); return m_size; endfunction: get_size function int unsigned uvm_mem::get_n_bits(); return m_n_bits; endfunction: get_n_bits function int unsigned uvm_mem::get_max_size(); return m_max_size; endfunction: get_max_size function int unsigned uvm_mem::get_n_bytes(); return (m_n_bits - 1) / 8 + 1; endfunction: get_n_bytes function uvm_reg_cvr_t uvm_mem::build_coverage(uvm_reg_cvr_t models); build_coverage = UVM_NO_COVERAGE; void'(uvm_reg_cvr_rsrc_db::read_by_name({"uvm_reg::", get_full_name()}, "include_coverage", build_coverage, this)); return build_coverage & models; endfunction: build_coverage function void uvm_mem::add_coverage(uvm_reg_cvr_t models); m_has_cover |= models; endfunction: add_coverage function bit uvm_mem::has_coverage(uvm_reg_cvr_t models); return ((m_has_cover & models) == models); endfunction: has_coverage function uvm_reg_cvr_t uvm_mem::set_coverage(uvm_reg_cvr_t is_on); if (is_on == uvm_reg_cvr_t'(UVM_NO_COVERAGE)) begin m_cover_on = is_on; return m_cover_on; end m_cover_on = m_has_cover & is_on; return m_cover_on; endfunction: set_coverage function bit uvm_mem::get_coverage(uvm_reg_cvr_t is_on); if (has_coverage(is_on) == 0) return 0; return ((m_cover_on & is_on) == is_on); endfunction: get_coverage task uvm_mem::write(output uvm_status_e status, input uvm_reg_addr_t offset, input uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_item rw = uvm_reg_item::type_id::create("mem_write",,get_full_name()); rw.element = this; rw.element_kind = UVM_MEM; rw.kind = UVM_WRITE; rw.offset = offset; rw.value[0] = value; rw.path = path; rw.map = map; rw.parent = parent; rw.prior = prior; rw.extension = extension; rw.fname = fname; rw.lineno = lineno; do_write(rw); status = rw.status; endtask: write task uvm_mem::read(output uvm_status_e status, input uvm_reg_addr_t offset, output uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_item rw; rw = uvm_reg_item::type_id::create("mem_read",,get_full_name()); rw.element = this; rw.element_kind = UVM_MEM; rw.kind = UVM_READ; rw.value[0] = 0; rw.offset = offset; rw.path = path; rw.map = map; rw.parent = parent; rw.prior = prior; rw.extension = extension; rw.fname = fname; rw.lineno = lineno; do_read(rw); status = rw.status; value = rw.value[0]; endtask: read task uvm_mem::burst_write(output uvm_status_e status, input uvm_reg_addr_t offset, input uvm_reg_data_t value[], input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_item rw; rw = uvm_reg_item::type_id::create("mem_burst_write",,get_full_name()); rw.element = this; rw.element_kind = UVM_MEM; rw.kind = UVM_BURST_WRITE; rw.offset = offset; rw.value = value; rw.path = path; rw.map = map; rw.parent = parent; rw.prior = prior; rw.extension = extension; rw.fname = fname; rw.lineno = lineno; do_write(rw); status = rw.status; endtask: burst_write task uvm_mem::burst_read(output uvm_status_e status, input uvm_reg_addr_t offset, ref uvm_reg_data_t value[], input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_item rw; rw = uvm_reg_item::type_id::create("mem_burst_read",,get_full_name()); rw.element = this; rw.element_kind = UVM_MEM; rw.kind = UVM_BURST_READ; rw.offset = offset; rw.value = value; rw.path = path; rw.map = map; rw.parent = parent; rw.prior = prior; rw.extension = extension; rw.fname = fname; rw.lineno = lineno; do_read(rw); status = rw.status; value = rw.value; endtask: burst_read task uvm_mem::do_write(uvm_reg_item rw); uvm_mem_cb_iter cbs = new(this); uvm_reg_map_info map_info; m_fname = rw.fname; m_lineno = rw.lineno; if (!Xcheck_accessX(rw, map_info)) return; m_write_in_progress = 1'b1; rw.status = UVM_IS_OK; pre_write(rw); for (uvm_reg_cbs cb=cbs.first(); cb!=null; cb=cbs.next()) cb.pre_write(rw); if (rw.status != UVM_IS_OK) begin m_write_in_progress = 1'b0; return; end rw.status = UVM_NOT_OK; if (rw.path == UVM_FRONTDOOR) begin uvm_reg_map system_map = rw.local_map.get_root_map(); if (map_info.frontdoor != null) begin uvm_reg_frontdoor fd = map_info.frontdoor; fd.rw_info = rw; if (fd.sequencer == null) fd.sequencer = system_map.get_sequencer(); fd.start(fd.sequencer, rw.parent); end else begin rw.local_map.do_write(rw); end if (rw.status != UVM_NOT_OK) for (uvm_reg_addr_t idx = rw.offset; idx <= rw.offset + rw.value.size(); idx++) begin XsampleX(map_info.mem_range.stride * idx, 0, rw.map); m_parent.XsampleX(map_info.offset + (map_info.mem_range.stride * idx), 0, rw.map); end end else begin if (get_access(rw.map) inside {"RW", "WO"}) begin uvm_reg_backdoor bkdr = get_backdoor(); if (bkdr != null) bkdr.write(rw); else backdoor_write(rw); end else rw.status = UVM_NOT_OK; end post_write(rw); for (uvm_reg_cbs cb=cbs.first(); cb!=null; cb=cbs.next()) cb.post_write(rw); if (uvm_report_enabled(UVM_HIGH, UVM_INFO, "RegModel")) begin string path_s,value_s,pre_s,range_s; if (rw.path == UVM_FRONTDOOR) path_s = (map_info.frontdoor != null) ? "user frontdoor" : {"map ",rw.map.get_full_name()}; else path_s = (get_backdoor() != null) ? "user backdoor" : "DPI backdoor"; if (rw.value.size() > 1) begin value_s = "='{"; pre_s = "Burst "; foreach (rw.value[i]) value_s = {value_s,$sformatf("%0h,",rw.value[i])}; value_s[value_s.len()-1]="}"; range_s = $sformatf("[%0d:%0d]",rw.offset,rw.offset+rw.value.size()); end else begin value_s = $sformatf("=%0h",rw.value[0]); range_s = $sformatf("[%0d]",rw.offset); end begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", {pre_s,"Wrote memory via ",path_s,": ", get_full_name(),range_s,value_s}, UVM_HIGH, "t/uvm/src/reg/uvm_mem.svh", 1265, "", 1); end end m_write_in_progress = 1'b0; endtask: do_write task uvm_mem::do_read(uvm_reg_item rw); uvm_mem_cb_iter cbs = new(this); uvm_reg_map_info map_info; m_fname = rw.fname; m_lineno = rw.lineno; if (!Xcheck_accessX(rw, map_info)) return; m_read_in_progress = 1'b1; rw.status = UVM_IS_OK; pre_read(rw); for (uvm_reg_cbs cb=cbs.first(); cb!=null; cb=cbs.next()) cb.pre_read(rw); if (rw.status != UVM_IS_OK) begin m_read_in_progress = 1'b0; return; end rw.status = UVM_NOT_OK; if (rw.path == UVM_FRONTDOOR) begin uvm_reg_map system_map = rw.local_map.get_root_map(); if (map_info.frontdoor != null) begin uvm_reg_frontdoor fd = map_info.frontdoor; fd.rw_info = rw; if (fd.sequencer == null) fd.sequencer = system_map.get_sequencer(); fd.start(fd.sequencer, rw.parent); end else begin rw.local_map.do_read(rw); end if (rw.status != UVM_NOT_OK) for (uvm_reg_addr_t idx = rw.offset; idx <= rw.offset + rw.value.size(); idx++) begin XsampleX(map_info.mem_range.stride * idx, 1, rw.map); m_parent.XsampleX(map_info.offset + (map_info.mem_range.stride * idx), 1, rw.map); end end else begin if (get_access(rw.map) inside {"RW", "RO"}) begin uvm_reg_backdoor bkdr = get_backdoor(); if (bkdr != null) bkdr.read(rw); else backdoor_read(rw); end else rw.status = UVM_NOT_OK; end post_read(rw); for (uvm_reg_cbs cb=cbs.first(); cb!=null; cb=cbs.next()) cb.post_read(rw); if (uvm_report_enabled(UVM_HIGH, UVM_INFO, "RegModel")) begin string path_s,value_s,pre_s,range_s; if (rw.path == UVM_FRONTDOOR) path_s = (map_info.frontdoor != null) ? "user frontdoor" : {"map ",rw.map.get_full_name()}; else path_s = (get_backdoor() != null) ? "user backdoor" : "DPI backdoor"; if (rw.value.size() > 1) begin value_s = "='{"; pre_s = "Burst "; foreach (rw.value[i]) value_s = {value_s,$sformatf("%0h,",rw.value[i])}; value_s[value_s.len()-1]="}"; range_s = $sformatf("[%0d:%0d]",rw.offset,(rw.offset+rw.value.size())); end else begin value_s = $sformatf("=%0h",rw.value[0]); range_s = $sformatf("[%0d]",rw.offset); end begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", {pre_s,"Read memory via ",path_s,": ", get_full_name(),range_s,value_s}, UVM_HIGH, "t/uvm/src/reg/uvm_mem.svh", 1373, "", 1); end end m_read_in_progress = 1'b0; endtask: do_read function bit uvm_mem::Xcheck_accessX(input uvm_reg_item rw, output uvm_reg_map_info map_info); if (rw.offset >= m_size) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,get_type_name())) uvm_report_error (get_type_name(), $sformatf("Offset 'h%0h exceeds size of memory, 'h%0h", rw.offset, m_size), UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 1389, "", 1); end rw.status = UVM_NOT_OK; return 0; end if (rw.path == UVM_DEFAULT_DOOR) rw.path = m_parent.get_default_door(); if (rw.path == UVM_BACKDOOR) begin if (get_backdoor() == null && !has_hdl_path()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"No backdoor access available for memory '",get_full_name(), "' . Using frontdoor instead."}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 1401, "", 1); end rw.path = UVM_FRONTDOOR; end else if (rw.map == null) begin if (get_default_map() != null) rw.map = get_default_map(); else rw.map = uvm_reg_map::backdoor(); end end if (rw.path != UVM_BACKDOOR) begin rw.local_map = get_local_map(rw.map); if (rw.local_map == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,get_type_name())) uvm_report_error (get_type_name(), {"No transactor available to physically access memory from map '", rw.map.get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 1420, "", 1); end rw.status = UVM_NOT_OK; return 0; end map_info = rw.local_map.get_mem_map_info(this); if (map_info.frontdoor == null) begin if (map_info.unmapped) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Memory '",get_full_name(), "' unmapped in map '", rw.map.get_full_name(), "' and does not have a user-defined frontdoor"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 1432, "", 1); end rw.status = UVM_NOT_OK; return 0; end if ((rw.value.size() > 1)) begin if (get_n_bits() > rw.local_map.get_n_bytes()*8) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot burst a %0d-bit memory through a narrower data path (%0d bytes)", get_n_bits(), rw.local_map.get_n_bytes()*8), UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 1441, "", 1); end rw.status = UVM_NOT_OK; return 0; end if (rw.offset + rw.value.size() > m_size) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Burst of size 'd%0d starting at offset 'd%0d exceeds size of memory, 'd%0d", rw.value.size(), rw.offset, m_size), UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 1448, "", 1); end return 0; end end end if (rw.map == null) rw.map = rw.local_map; end return 1; endfunction task uvm_mem::poke(output uvm_status_e status, input uvm_reg_addr_t offset, input uvm_reg_data_t value, input string kind = "", input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_item rw; uvm_reg_backdoor bkdr = get_backdoor(); m_fname = fname; m_lineno = lineno; if (bkdr == null && !has_hdl_path(kind)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"No backdoor access available in memory '", get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 1484, "", 1); end status = UVM_NOT_OK; return; end rw = uvm_reg_item::type_id::create("mem_poke_item",,get_full_name()); rw.element = this; rw.path = UVM_BACKDOOR; rw.element_kind = UVM_MEM; rw.kind = UVM_WRITE; rw.offset = offset; rw.value[0] = value & ((1 << m_n_bits)-1); rw.bd_kind = kind; rw.parent = parent; rw.extension = extension; rw.fname = fname; rw.lineno = lineno; if (bkdr != null) bkdr.write(rw); else backdoor_write(rw); status = rw.status; begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("Poked memory '%s[%0d]' with value 'h%h", get_full_name(), offset, value), UVM_HIGH, "t/uvm/src/reg/uvm_mem.svh", 1511, "", 1); end endtask: poke task uvm_mem::peek(output uvm_status_e status, input uvm_reg_addr_t offset, output uvm_reg_data_t value, input string kind = "", input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_backdoor bkdr = get_backdoor(); uvm_reg_item rw; m_fname = fname; m_lineno = lineno; if (bkdr == null && !has_hdl_path(kind)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"No backdoor access available in memory '", get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 1534, "", 1); end status = UVM_NOT_OK; return; end rw = uvm_reg_item::type_id::create("mem_peek_item",,get_full_name()); rw.element = this; rw.path = UVM_BACKDOOR; rw.element_kind = UVM_MEM; rw.kind = UVM_READ; rw.offset = offset; rw.bd_kind = kind; rw.parent = parent; rw.extension = extension; rw.fname = fname; rw.lineno = lineno; if (bkdr != null) bkdr.read(rw); else backdoor_read(rw); status = rw.status; value = rw.value[0]; begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("Peeked memory '%s[%0d]' has value 'h%h", get_full_name(), offset, value), UVM_HIGH, "t/uvm/src/reg/uvm_mem.svh", 1561, "", 1); end endtask: peek function void uvm_mem::set_frontdoor(uvm_reg_frontdoor ftdr, uvm_reg_map map = null, string fname = "", int lineno = 0); uvm_reg_map_info map_info; m_fname = fname; m_lineno = lineno; map = get_local_map(map); if (map == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Memory '",get_full_name(), "' not found in map '", map.get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 1583, "", 1); end return; end map_info = map.get_mem_map_info(this); map_info.frontdoor = ftdr; endfunction: set_frontdoor function uvm_reg_frontdoor uvm_mem::get_frontdoor(uvm_reg_map map = null); uvm_reg_map_info map_info; map = get_local_map(map); if (map == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Memory '",get_full_name(), "' not found in map '", map.get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 1602, "", 1); end return null; end map_info = map.get_mem_map_info(this); return map_info.frontdoor; endfunction: get_frontdoor function void uvm_mem::set_backdoor(uvm_reg_backdoor bkdr, string fname = "", int lineno = 0); m_fname = fname; m_lineno = lineno; m_backdoor = bkdr; endfunction: set_backdoor function uvm_reg_backdoor uvm_mem::get_backdoor(bit inherited = 1); if (m_backdoor == null && inherited) begin uvm_reg_block blk = get_parent(); uvm_reg_backdoor bkdr; while (blk != null) begin bkdr = blk.get_backdoor(); if (bkdr != null) begin m_backdoor = bkdr; break; end blk = blk.get_parent(); end end return m_backdoor; endfunction: get_backdoor function uvm_status_e uvm_mem::backdoor_read_func(uvm_reg_item rw); uvm_hdl_path_concat paths[$]; uvm_hdl_data_t val; bit ok=1; get_full_hdl_path(paths,rw.bd_kind); foreach (rw.value[mem_idx]) begin string idx; idx.itoa(rw.offset + mem_idx); foreach (paths[i]) begin uvm_hdl_path_concat hdl_concat = paths[i]; val = 0; foreach (hdl_concat.slices[j]) begin string hdl_path = {hdl_concat.slices[j].path, "[", idx, "]"}; begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", {"backdoor_read from ",hdl_path}, UVM_DEBUG, "t/uvm/src/reg/uvm_mem.svh", 1667, "", 1); end if (hdl_concat.slices[j].offset < 0) begin ok &= uvm_hdl_read(hdl_path, val); continue; end begin uvm_reg_data_t slice; int k = hdl_concat.slices[j].offset; ok &= uvm_hdl_read(hdl_path, slice); repeat (hdl_concat.slices[j].size) begin val[k++] = slice[0]; slice >>= 1; end end end val &= (1 << m_n_bits)-1; if (i == 0) rw.value[mem_idx] = val; if (val != rw.value[mem_idx]) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Backdoor read of register %s with multiple HDL copies: values are not the same: %0h at path '%s', and %0h at path '%s'. Returning first value.", get_full_name(), rw.value[mem_idx], uvm_hdl_concat2string(paths[0]), val, uvm_hdl_concat2string(paths[i])), UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 1692, "", 1); end return UVM_NOT_OK; end end end rw.status = (ok) ? UVM_IS_OK : UVM_NOT_OK; return rw.status; endfunction task uvm_mem::backdoor_read(uvm_reg_item rw); rw.status = backdoor_read_func(rw); endtask task uvm_mem::backdoor_write(uvm_reg_item rw); uvm_hdl_path_concat paths[$]; bit ok=1; get_full_hdl_path(paths,rw.bd_kind); foreach (rw.value[mem_idx]) begin string idx; idx.itoa(rw.offset + mem_idx); foreach (paths[i]) begin uvm_hdl_path_concat hdl_concat = paths[i]; foreach (hdl_concat.slices[j]) begin begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("backdoor_write to %s ",hdl_concat.slices[j].path), UVM_DEBUG, "t/uvm/src/reg/uvm_mem.svh", 1727, "", 1); end if (hdl_concat.slices[j].offset < 0) begin ok &= uvm_hdl_deposit({hdl_concat.slices[j].path,"[", idx, "]"},rw.value[mem_idx]); continue; end begin uvm_reg_data_t slice; slice = rw.value[mem_idx] >> hdl_concat.slices[j].offset; slice &= (1 << hdl_concat.slices[j].size)-1; ok &= uvm_hdl_deposit({hdl_concat.slices[j].path, "[", idx, "]"}, slice); end end end end rw.status = (ok ? UVM_IS_OK : UVM_NOT_OK); endtask function void uvm_mem::clear_hdl_path(string kind = "RTL"); if (kind == "ALL") begin m_hdl_paths_pool = new("hdl_paths"); return; end if (kind == "") kind = m_parent.get_default_hdl_path(); if (!m_hdl_paths_pool.exists(kind)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Unknown HDL Abstraction '",kind,"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 1760, "", 1); end return; end m_hdl_paths_pool.delete(kind); endfunction function void uvm_mem::add_hdl_path(uvm_hdl_path_slice slices[], string kind = "RTL"); uvm_queue #(uvm_hdl_path_concat) paths = m_hdl_paths_pool.get(kind); uvm_hdl_path_concat concat = new(); concat.set(slices); paths.push_back(concat); endfunction function void uvm_mem::add_hdl_path_slice(string name, int offset, int size, bit first = 0, string kind = "RTL"); uvm_queue #(uvm_hdl_path_concat) paths=m_hdl_paths_pool.get(kind); uvm_hdl_path_concat concat; if (first || paths.size() == 0) begin concat = new(); paths.push_back(concat); end else concat = paths.get(paths.size()-1); concat.add_path(name, offset, size); endfunction function bit uvm_mem::has_hdl_path(string kind = ""); if (kind == "") kind = m_parent.get_default_hdl_path(); return m_hdl_paths_pool.exists(kind); endfunction function void uvm_mem::get_hdl_path(ref uvm_hdl_path_concat paths[$], input string kind = ""); uvm_queue #(uvm_hdl_path_concat) hdl_paths; if (kind == "") kind = m_parent.get_default_hdl_path(); if (!has_hdl_path(kind)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Memory does not have hdl path defined for abstraction '",kind,"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 1822, "", 1); end return; end hdl_paths = m_hdl_paths_pool.get(kind); for (int i=0; i= range.min && addrs[i] <= range.max) begin string a; a = $sformatf("%0h",addrs[i]); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"In map '",get_full_name(),"' register '", rg.get_full_name(), "' overlaps with address range of memory '", top_map.m_mems_by_offset[range].get_full_name(),"': 'h",a}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 716, "", 1); end end end end info.addr = addrs; end end if (unmapped) begin info.offset = -1; info.unmapped = 1; end else begin info.offset = offset; info.unmapped = 0; end end endfunction function void uvm_reg_map::add_mem(uvm_mem mem, uvm_reg_addr_t offset, string rights = "RW", bit unmapped=0, uvm_reg_frontdoor frontdoor=null); if (m_mems_info.exists(mem)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Memory '",mem.get_name(), "' has already been added to map '",get_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 746, "", 1); end return; end if (mem.get_parent() != get_parent()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Memory '",mem.get_full_name(),"' may not be added to address map '", get_full_name(),"' : they are not in the same block"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 753, "", 1); end return; end mem.add_map(this); begin uvm_reg_map_info info = new; info.offset = offset; info.rights = rights; info.unmapped = unmapped; info.frontdoor = frontdoor; m_mems_info[mem] = info; end endfunction: add_mem function void uvm_reg_map::m_set_mem_offset(uvm_mem mem, uvm_reg_addr_t offset, bit unmapped); if (!m_mems_info.exists(mem)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Cannot modify offset of memory '",mem.get_full_name(), "' in address map '",get_full_name(), "' : memory not mapped in that address map"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 781, "", 1); end return; end begin uvm_reg_map_info info = m_mems_info[mem]; uvm_reg_block blk = get_parent(); uvm_reg_map top_map = get_root_map(); uvm_reg_addr_t addrs[]; if (blk.is_locked()) begin if (!info.unmapped) begin foreach (top_map.m_mems_by_offset[range]) begin if (top_map.m_mems_by_offset[range] == mem) top_map.m_mems_by_offset.delete(range); end end if (!unmapped) begin uvm_reg_addr_t addrs[],addrs_max[]; uvm_reg_addr_t min, max, min2, max2; int unsigned stride; void'(get_physical_addresses(offset,0,mem.get_n_bytes(),addrs)); min = (addrs[0] < addrs[addrs.size()-1]) ? addrs[0] : addrs[addrs.size()-1]; min2 = addrs[0]; void'(get_physical_addresses(offset,(mem.get_size()-1), mem.get_n_bytes(),addrs_max)); max = (addrs_max[0] > addrs_max[addrs_max.size()-1]) ? addrs_max[0] : addrs_max[addrs_max.size()-1]; max2 = addrs_max[0]; stride = mem.get_n_bytes()/get_addr_unit_bytes(); foreach (top_map.m_regs_by_offset[reg_addr]) begin if (reg_addr >= min && reg_addr <= max) begin string a,b; a = $sformatf("[%0h:%0h]",min,max); b = $sformatf("%0h",reg_addr); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"In map '",get_full_name(),"' memory '", mem.get_full_name(), "' with range ",a, " overlaps with address of existing register '", top_map.m_regs_by_offset[reg_addr].get_full_name(),"': 'h",b}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 829, "", 1); end end end foreach (top_map.m_mems_by_offset[range]) begin if (min <= range.max && max >= range.max || min <= range.min && max >= range.min || min >= range.min && max <= range.max) begin string a,b; a = $sformatf("[%0h:%0h]",min,max); b = $sformatf("[%0h:%0h]",range.min,range.max); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"In map '",get_full_name(),"' memory '", mem.get_full_name(), "' with range ",a, " overlaps existing memory with range '", top_map.m_mems_by_offset[range].get_full_name(),"': ",b}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 843, "", 1); end end end begin uvm_reg_map_addr_range range = '{ min, max, stride}; top_map.m_mems_by_offset[range] = mem; info.addr = addrs; info.mem_range = range; end end end if (unmapped) begin info.offset = -1; info.unmapped = 1; end else begin info.offset = offset; info.unmapped = 0; end end endfunction function void uvm_reg_map::add_submap (uvm_reg_map child_map, uvm_reg_addr_t offset); uvm_reg_map parent_map; if (child_map == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Attempting to add NULL map to map '",get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 877, "", 1); end return; end parent_map = child_map.get_parent_map(); if (parent_map != null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Map '", child_map.get_full_name(), "' is already a child of map '", parent_map.get_full_name(), "'. Cannot also be a child of map '", get_full_name(), "'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 890, "", 1); end return; end begin : n_bytes_match_check if (m_n_bytes > child_map.get_n_bytes(UVM_NO_HIER)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", $sformatf("Adding %0d-byte submap '%s' to %0d-byte parent map '%s'", child_map.get_n_bytes(UVM_NO_HIER), child_map.get_full_name(), m_n_bytes, get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 900, "", 1); end end end child_map.add_parent_map(this,offset); set_submap_offset(child_map, offset); endfunction: add_submap function void uvm_reg_map::reset(string kind = "SOFT"); uvm_reg regs[$]; get_registers(regs); foreach (regs[i]) begin regs[i].reset(kind); end endfunction function void uvm_reg_map::add_parent_map(uvm_reg_map parent_map, uvm_reg_addr_t offset); if (parent_map == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Attempting to add NULL parent map to map '",get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 930, "", 1); end return; end if (m_parent_map != null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Map \"%s\" already a submap of map \"%s\" at offset 'h%h", get_full_name(), m_parent_map.get_full_name(), m_parent_map.get_submap_offset(this)), UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 938, "", 1); end return; end m_parent_map = parent_map; parent_map.m_submaps[this] = offset; endfunction: add_parent_map function void uvm_reg_map::set_sequencer(uvm_sequencer_base sequencer, uvm_reg_adapter adapter=null); if (sequencer == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"REG_NULL_SQR")) uvm_report_error ("REG_NULL_SQR", "Null reference specified for bus sequencer", UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 954, "", 1); end return; end if (adapter == null) begin begin if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"REG_NO_ADAPT")) uvm_report_info ("REG_NO_ADAPT", {"Adapter not specified for map '",get_full_name(), "'. Accesses via this map will send abstract 'uvm_reg_item' items to sequencer '", sequencer.get_full_name(),"'"}, UVM_MEDIUM, "t/uvm/src/reg/uvm_reg_map.svh", 961, "", 1); end end m_sequencer = sequencer; m_adapter = adapter; endfunction function uvm_reg_block uvm_reg_map::get_parent(); return m_parent; endfunction function uvm_reg_map uvm_reg_map::get_parent_map(); return m_parent_map; endfunction function uvm_reg_map uvm_reg_map::get_root_map(); return (m_parent_map == null) ? this : m_parent_map.get_root_map(); endfunction: get_root_map function uvm_reg_addr_t uvm_reg_map::get_base_addr(uvm_hier_e hier=UVM_HIER); uvm_reg_map child = this; if (hier == UVM_NO_HIER || m_parent_map == null) return m_base_addr; get_base_addr = m_parent_map.get_submap_offset(this); get_base_addr += m_parent_map.get_base_addr(UVM_HIER); endfunction function int unsigned uvm_reg_map::get_n_bytes(uvm_hier_e hier=UVM_HIER); if (hier == UVM_NO_HIER) return m_n_bytes; return m_system_n_bytes; endfunction function int unsigned uvm_reg_map::get_addr_unit_bytes(); return (m_byte_addressing) ? 1 : m_n_bytes; endfunction function uvm_endianness_e uvm_reg_map::get_endian(uvm_hier_e hier=UVM_HIER); if (hier == UVM_NO_HIER || m_parent_map == null) return m_endian; return m_parent_map.get_endian(hier); endfunction function uvm_sequencer_base uvm_reg_map::get_sequencer(uvm_hier_e hier=UVM_HIER); if (hier == UVM_NO_HIER || m_parent_map == null) return m_sequencer; return m_parent_map.get_sequencer(hier); endfunction function uvm_reg_adapter uvm_reg_map::get_adapter(uvm_hier_e hier=UVM_HIER); if (hier == UVM_NO_HIER || m_parent_map == null) return m_adapter; return m_parent_map.get_adapter(hier); endfunction function void uvm_reg_map::get_submaps(ref uvm_reg_map maps[$], input uvm_hier_e hier=UVM_HIER); foreach (m_submaps[submap]) maps.push_back(submap); if (hier == UVM_HIER) foreach (m_submaps[submap_]) begin uvm_reg_map submap=submap_; submap.get_submaps(maps); end endfunction function void uvm_reg_map::get_registers(ref uvm_reg regs[$], input uvm_hier_e hier=UVM_HIER); foreach (m_regs_info[rg]) regs.push_back(rg); if (hier == UVM_HIER) foreach (m_submaps[submap_]) begin uvm_reg_map submap=submap_; submap.get_registers(regs); end endfunction function void uvm_reg_map::get_fields(ref uvm_reg_field fields[$], input uvm_hier_e hier=UVM_HIER); foreach (m_regs_info[rg_]) begin uvm_reg rg = rg_; rg.get_fields(fields); end if (hier == UVM_HIER) foreach (this.m_submaps[submap_]) begin uvm_reg_map submap=submap_; submap.get_fields(fields); end endfunction function void uvm_reg_map::get_memories(ref uvm_mem mems[$], input uvm_hier_e hier=UVM_HIER); foreach (m_mems_info[mem]) mems.push_back(mem); if (hier == UVM_HIER) foreach (m_submaps[submap_]) begin uvm_reg_map submap=submap_; submap.get_memories(mems); end endfunction function void uvm_reg_map::get_virtual_registers(ref uvm_vreg regs[$], input uvm_hier_e hier=UVM_HIER); uvm_mem mems[$]; get_memories(mems,hier); foreach (mems[i]) mems[i].get_virtual_registers(regs); endfunction function void uvm_reg_map::get_virtual_fields(ref uvm_vreg_field fields[$], input uvm_hier_e hier=UVM_HIER); uvm_vreg regs[$]; get_virtual_registers(regs,hier); foreach (regs[i]) regs[i].get_fields(fields); endfunction function string uvm_reg_map::get_full_name(); if (m_parent == null) return get_name(); else return {m_parent.get_full_name(), ".", get_name()}; endfunction function uvm_reg_map_info uvm_reg_map::get_mem_map_info(uvm_mem mem, bit error=1); if (!m_mems_info.exists(mem)) begin if (error) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"REG_NO_MAP")) uvm_report_error ("REG_NO_MAP", {"Memory '",mem.get_name(),"' not in map '",get_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1157, "", 1); end return null; end return m_mems_info[mem]; endfunction function uvm_reg_map_info uvm_reg_map::get_reg_map_info(uvm_reg rg, bit error=1); uvm_reg_map_info result; if (!m_regs_info.exists(rg)) begin if (error) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"REG_NO_MAP")) uvm_report_error ("REG_NO_MAP", {"Register '",rg.get_name(),"' not in map '",get_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1170, "", 1); end return null; end result = m_regs_info[rg]; if(!result.is_initialized) begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"map '",get_name(),"' does not seem to be initialized correctly, check that the top register model is locked()"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1175, "", 1); end return result; endfunction function void uvm_reg_map::set_base_addr(uvm_reg_addr_t offset); if (m_parent_map != null) begin m_parent_map.set_submap_offset(this, offset); end else begin m_base_addr = offset; if (m_parent.is_locked()) begin uvm_reg_map top_map = get_root_map(); top_map.Xinit_address_mapX(); end end endfunction function int unsigned uvm_reg_map::get_size(); int unsigned max_addr; int unsigned addr; foreach (m_regs_info[rg_]) begin uvm_reg rg = rg_; addr = m_regs_info[rg].offset + ((rg.get_n_bytes()-1)/m_n_bytes); if (addr > max_addr) max_addr = addr; end foreach (m_mems_info[mem_]) begin uvm_mem mem = mem_; addr = m_mems_info[mem].offset + (mem.get_size() * (((mem.get_n_bytes()-1)/m_n_bytes)+1)) -1; if (addr > max_addr) max_addr = addr; end foreach (m_submaps[submap_]) begin uvm_reg_map submap=submap_; addr = m_submaps[submap] + submap.get_size(); if (addr > max_addr) max_addr = addr; end return max_addr + 1; endfunction function void uvm_reg_map::Xverify_map_configX(); bit error; uvm_reg_map root_map = get_root_map(); if (root_map.get_adapter() == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Map '",root_map.get_full_name(), "' does not have an adapter registered"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1243, "", 1); end error++; end if (root_map.get_sequencer() == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Map '",root_map.get_full_name(), "' does not have a sequencer registered"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1248, "", 1); end error++; end if (error) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"RegModel")) uvm_report_fatal ("RegModel", {"Must register an adapter and sequencer ", "for each top-level map in RegModel model"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1253, "", 1); end return; end endfunction function int uvm_reg_map::get_physical_addresses_to_map( uvm_reg_addr_t base_addr, uvm_reg_addr_t mem_offset, int unsigned n_bytes, ref uvm_reg_addr_t addr[], input uvm_reg_map parent_map, ref int unsigned byte_offset, input uvm_mem mem=null ); int bus_width = get_n_bytes(UVM_NO_HIER); uvm_reg_map up_map; uvm_reg_addr_t local_addr[]; uvm_reg_addr_t lbase_addr; up_map = get_parent_map(); lbase_addr = up_map==null ? get_base_addr(UVM_NO_HIER): up_map.get_submap_offset(this); if(up_map!=parent_map) begin uvm_reg_addr_t lb; uvm_reg_addr_t laddr; begin if(mem_offset) begin base_addr+=mem_offset*mem.get_n_bytes()/get_addr_unit_bytes(); end laddr=lbase_addr + base_addr*get_addr_unit_bytes()/up_map.get_addr_unit_bytes(); lb = (base_addr*get_addr_unit_bytes()) % up_map.get_addr_unit_bytes(); byte_offset += lb; end return up_map.get_physical_addresses_to_map(laddr, 0, n_bytes+lb, addr,parent_map,byte_offset); end else begin uvm_reg_addr_t lbase_addr2; local_addr= new[ceil(n_bytes,bus_width)]; lbase_addr2 = base_addr; if(mem_offset) if(mem!=null && (mem.get_n_bytes() >= get_addr_unit_bytes())) begin lbase_addr2 = base_addr + mem_offset*mem.get_n_bytes()/get_addr_unit_bytes(); byte_offset += (mem_offset*mem.get_n_bytes() % get_addr_unit_bytes()); end else begin lbase_addr2 = base_addr + mem_offset; end case (get_endian(UVM_NO_HIER)) UVM_LITTLE_ENDIAN: begin foreach (local_addr[i]) begin local_addr[i] = lbase_addr2 + i*bus_width/get_addr_unit_bytes(); end end UVM_BIG_ENDIAN: begin foreach (local_addr[i]) begin local_addr[i] = lbase_addr2 + (local_addr.size()-1-i)*bus_width/get_addr_unit_bytes() ; end end UVM_LITTLE_FIFO: begin foreach (local_addr[i]) begin local_addr[i] = lbase_addr2; end end UVM_BIG_FIFO: begin foreach (local_addr[i]) begin local_addr[i] = lbase_addr2; end end default: begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/REG/MAPNOENDIANESS")) uvm_report_error ("UVM/REG/MAPNOENDIANESS", {"Map has no specified endianness. ", $sformatf("Cannot access %0d bytes register via its %0d byte \"%s\" interface", n_bytes, bus_width, get_full_name())}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1347, "", 1); end end endcase addr = new [local_addr.size()] (local_addr); foreach(addr[idx]) addr[idx] += lbase_addr; end endfunction function int uvm_reg_map::get_physical_addresses(uvm_reg_addr_t base_addr, uvm_reg_addr_t mem_offset, int unsigned n_bytes, ref uvm_reg_addr_t addr[]); int unsigned skip; return get_physical_addresses_to_map(base_addr, mem_offset, n_bytes, addr,null,skip); endfunction function void uvm_reg_map::set_submap_offset(uvm_reg_map submap, uvm_reg_addr_t offset); if (submap == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"REG/NULL")) uvm_report_error ("REG/NULL", "set_submap_offset: submap handle is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1385, "", 1); end return; end m_submaps[submap] = offset; if (m_parent.is_locked()) begin uvm_reg_map root_map = get_root_map(); root_map.Xinit_address_mapX(); end endfunction function uvm_reg_addr_t uvm_reg_map::get_submap_offset(uvm_reg_map submap); if (submap == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"REG/NULL")) uvm_report_error ("REG/NULL", "set_submap_offset: submap handle is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1400, "", 1); end return -1; end if (!m_submaps.exists(submap)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Map '",submap.get_full_name(), "' is not a submap of '",get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1405, "", 1); end return -1; end return m_submaps[submap]; endfunction function uvm_reg uvm_reg_map::get_reg_by_offset(uvm_reg_addr_t offset, bit read = 1); if (!m_parent.is_locked()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot get register by offset: Block %s is not locked.", m_parent.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1417, "", 1); end return null; end if (!read && m_regs_by_offset_wo.exists(offset)) return m_regs_by_offset_wo[offset]; if (m_regs_by_offset.exists(offset)) return m_regs_by_offset[offset]; return null; endfunction function uvm_mem uvm_reg_map::get_mem_by_offset(uvm_reg_addr_t offset); if (!m_parent.is_locked()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot memory register by offset: Block %s is not locked.", m_parent.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1435, "", 1); end return null; end foreach (m_mems_by_offset[range]) begin if (range.min <= offset && offset <= range.max) begin return m_mems_by_offset[range]; end end return null; endfunction function void uvm_reg_map::Xinit_address_mapX(); int unsigned bus_width; uvm_reg_map top_map = get_root_map(); if (this == top_map) begin top_map.m_regs_by_offset.delete(); top_map.m_regs_by_offset_wo.delete(); top_map.m_mems_by_offset.delete(); end foreach (m_submaps[l]) begin uvm_reg_map map=l; map.Xinit_address_mapX(); end foreach (m_regs_info[rg_]) begin uvm_reg rg = rg_; m_regs_info[rg].is_initialized=1; if (!m_regs_info[rg].unmapped) begin string rg_acc = rg.Xget_fields_accessX(this); uvm_reg_addr_t addrs[]; bus_width = get_physical_addresses(m_regs_info[rg].offset,0,rg.get_n_bytes(),addrs); foreach (addrs[i]) begin uvm_reg_addr_t addr = addrs[i]; if (top_map.m_regs_by_offset.exists(addr) && (top_map.m_regs_by_offset[addr] != rg)) begin uvm_reg rg2 = top_map.m_regs_by_offset[addr]; string rg2_acc = rg2.Xget_fields_accessX(this); if (rg_acc == "RO" && rg2_acc == "WO") begin top_map.m_regs_by_offset[addr] = rg; uvm_reg_read_only_cbs::add(rg); top_map.m_regs_by_offset_wo[addr] = rg2; uvm_reg_write_only_cbs::add(rg2); end else if (rg_acc == "WO" && rg2_acc == "RO") begin top_map.m_regs_by_offset_wo[addr] = rg; uvm_reg_write_only_cbs::add(rg); uvm_reg_read_only_cbs::add(rg2); end else begin string a; a = $sformatf("%0h",addr); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"In map '",get_full_name(),"' register '", rg.get_full_name(), "' maps to same address as register '", top_map.m_regs_by_offset[addr].get_full_name(),"': 'h",a}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1503, "", 1); end end end else top_map.m_regs_by_offset[addr] = rg; foreach (top_map.m_mems_by_offset[range]) begin if (addr >= range.min && addr <= range.max) begin string a,b; a = $sformatf("%0h",addr); b = $sformatf("[%0h:%0h]",range.min,range.max); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"In map '",get_full_name(),"' register '", rg.get_full_name(), "' with address ",a, "maps to same address as memory '", top_map.m_mems_by_offset[range].get_full_name(),"': ",b}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1517, "", 1); end end end end m_regs_info[rg].addr = addrs; end end foreach (m_mems_info[mem_]) begin uvm_mem mem = mem_; if (!m_mems_info[mem].unmapped) begin uvm_reg_addr_t addrs[],addrs_max[]; uvm_reg_addr_t min, max, min2, max2; int unsigned stride; int unsigned bo; bus_width = get_physical_addresses_to_map(m_mems_info[mem].offset,0,mem.get_n_bytes(),addrs,null,bo,mem); min = (addrs[0] < addrs[addrs.size()-1]) ? addrs[0] : addrs[addrs.size()-1]; void'(get_physical_addresses_to_map(m_mems_info[mem].offset,(mem.get_size()-1),mem.get_n_bytes(),addrs_max,null,bo,mem)); max = (addrs_max[0] > addrs_max[addrs_max.size()-1]) ? addrs_max[0] : addrs_max[addrs_max.size()-1]; stride = mem.get_n_bytes()/get_addr_unit_bytes(); if(mem.get_n_bytes() get_addr_unit_bytes()) if(mem.get_n_bytes() % get_addr_unit_bytes()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/REG/ADDR")) uvm_report_warning ("UVM/REG/ADDR", $sformatf("memory %s is not matching the word width of the enclosing map %s \ (one memory word not fitting into k map addresses)", mem.get_full_name(),get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1571, "", 1); end end if(mem.get_n_bytes() < get_addr_unit_bytes()) if(get_addr_unit_bytes() % mem.get_n_bytes()) begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/REG/ADDR")) uvm_report_warning ("UVM/REG/ADDR", $sformatf("the memory %s is not matching the word width of the enclosing map %s \ (one map address doesnt cover k memory words)", mem.get_full_name(),get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1578, "", 1); end if(mem.get_n_bits() % 8) begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/REG/ADDR")) uvm_report_warning ("UVM/REG/ADDR", $sformatf("this implementation of UVM requires memory words to be k*8 bits (mem %s \ has %0d bit words)",mem.get_full_name(),mem.get_n_bits()), UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1582, "", 1); end foreach (top_map.m_regs_by_offset[reg_addr]) begin if (reg_addr >= min && reg_addr <= max) begin string a; a = $sformatf("%0h",reg_addr); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"In map '",get_full_name(),"' memory '", mem.get_full_name(), "' maps to same address as register '", top_map.m_regs_by_offset[reg_addr].get_full_name(),"': 'h",a}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1590, "", 1); end end end foreach (top_map.m_mems_by_offset[range]) begin if (min <= range.max && max >= range.max || min <= range.min && max >= range.min || min >= range.min && max <= range.max) if(top_map.m_mems_by_offset[range]!=mem) begin string a; a = $sformatf("[%0h:%0h]",min,max); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"In map '",get_full_name(),"' memory '", mem.get_full_name(), "' overlaps with address range of memory '", top_map.m_mems_by_offset[range].get_full_name(),"': 'h",a}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1604, "", 1); end end end begin uvm_reg_map_addr_range range = '{ min, max, stride}; top_map.m_mems_by_offset[ range ] = mem; m_mems_info[mem].addr = addrs; m_mems_info[mem].mem_range = range; end end end if (bus_width == 0) bus_width = m_n_bytes; m_system_n_bytes = bus_width; endfunction function void uvm_reg_map::Xget_bus_infoX(uvm_reg_item rw, output uvm_reg_map_info map_info, output int size, output int lsb, output int addr_skip); if (rw.element_kind == UVM_MEM) begin uvm_mem mem; if(rw.element == null || !$cast(mem,rw.element)) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"REG/CAST")) uvm_report_fatal ("REG/CAST", {"uvm_reg_item 'element_kind' is UVM_MEM, ", "but 'element' does not point to a memory: ",rw.get_name()}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1639, "", 1); end map_info = get_mem_map_info(mem); size = mem.get_n_bits(); end else if (rw.element_kind == UVM_REG) begin uvm_reg rg; if(rw.element == null || !$cast(rg,rw.element)) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"REG/CAST")) uvm_report_fatal ("REG/CAST", {"uvm_reg_item 'element_kind' is UVM_REG, ", "but 'element' does not point to a register: ",rw.get_name()}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1647, "", 1); end map_info = get_reg_map_info(rg); size = rg.get_n_bits(); end else if (rw.element_kind == UVM_FIELD) begin uvm_reg_field field; if(rw.element == null || !$cast(field,rw.element)) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"REG/CAST")) uvm_report_fatal ("REG/CAST", {"uvm_reg_item 'element_kind' is UVM_FIELD, ", "but 'element' does not point to a field: ",rw.get_name()}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1655, "", 1); end map_info = get_reg_map_info(field.get_parent()); size = field.get_n_bits(); lsb = field.get_lsb_pos(); addr_skip = lsb/(get_n_bytes()*8); end endfunction task uvm_reg_map::do_write(uvm_reg_item rw); uvm_sequence_base tmp_parent_seq; uvm_reg_map system_map = get_root_map(); uvm_reg_adapter adapter = system_map.get_adapter(); uvm_sequencer_base sequencer = system_map.get_sequencer(); uvm_reg_seq_base parent_proxy; if (adapter != null && adapter.parent_sequence != null) begin uvm_object o; uvm_sequence_base seq; o = adapter.parent_sequence.clone(); if (o == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"REG/CLONE")) uvm_report_fatal ("REG/CLONE", {"failed to clone adapter's parent sequence: '", adapter.parent_sequence.get_full_name(), "' (of type '", adapter.parent_sequence.get_type_name(), "')"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1686, "", 1); end if (!$cast(seq, o)) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"REG/CAST")) uvm_report_fatal ("REG/CAST", {"failed to cast: '", o.get_full_name(), "' (of type '", o.get_type_name(), "') to uvm_sequence_base!"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1693, "", 1); end seq.set_parent_sequence(rw.parent); rw.parent = seq; tmp_parent_seq = seq; end if (rw.parent == null) begin parent_proxy = new("default_parent_seq"); rw.parent = parent_proxy; tmp_parent_seq = rw.parent; end if (adapter == null) begin uvm_event#(uvm_object) end_event ; uvm_event_pool ep; ep = rw.get_event_pool(); end_event = ep.get("end") ; rw.set_sequencer(sequencer); rw.parent.start_item(rw,rw.prior); rw.parent.finish_item(rw); end_event.wait_on(); end else begin do_bus_write(rw, sequencer, adapter); end if (tmp_parent_seq != null) sequencer.m_sequence_exiting(tmp_parent_seq); endtask task uvm_reg_map::do_read(uvm_reg_item rw); uvm_sequence_base tmp_parent_seq; uvm_reg_map system_map = get_root_map(); uvm_reg_adapter adapter = system_map.get_adapter(); uvm_sequencer_base sequencer = system_map.get_sequencer(); uvm_reg_seq_base parent_proxy; if (adapter != null && adapter.parent_sequence != null) begin uvm_object o; uvm_sequence_base seq; o = adapter.parent_sequence.clone(); if (o == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"REG/CLONE")) uvm_report_fatal ("REG/CLONE", {"failed to clone adapter's parent sequence: '", adapter.parent_sequence.get_full_name(), "' (of type '", adapter.parent_sequence.get_type_name(), "')"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1745, "", 1); end if (!$cast(seq, o)) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"REG/CAST")) uvm_report_fatal ("REG/CAST", {"failed to cast: '", o.get_full_name(), "' (of type '", o.get_type_name(), "') to uvm_sequence_base!"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1752, "", 1); end seq.set_parent_sequence(rw.parent); rw.parent = seq; tmp_parent_seq = seq; end if (rw.parent == null) begin parent_proxy = new("default_parent_seq"); rw.parent = parent_proxy; tmp_parent_seq = rw.parent; end if (adapter == null) begin uvm_event#(uvm_object) end_event ; uvm_event_pool ep; ep = rw.get_event_pool(); end_event = ep.get("end") ; rw.set_sequencer(sequencer); rw.parent.start_item(rw,rw.prior); rw.parent.finish_item(rw); end_event.wait_on(); end else begin do_bus_read(rw, sequencer, adapter); end if (tmp_parent_seq != null) sequencer.m_sequence_exiting(tmp_parent_seq); endtask task uvm_reg_map::do_bus_write (uvm_reg_item rw, uvm_sequencer_base sequencer, uvm_reg_adapter adapter); do_bus_access(rw, sequencer, adapter); endtask task uvm_reg_map::perform_accesses(ref uvm_reg_bus_op accesses[$], input uvm_reg_item rw, input uvm_reg_adapter adapter, input uvm_sequencer_base sequencer); string op; uvm_reg_data_logic_t data; uvm_endianness_e endian; op=(rw.kind inside {UVM_READ,UVM_BURST_READ}) ? "Read" : "Wrote"; endian=get_endian(UVM_NO_HIER); if(policy!=null) policy.order(accesses); foreach(accesses[i]) begin uvm_reg_bus_op rw_access=accesses[i]; uvm_sequence_item bus_req; if ((rw_access.kind == UVM_WRITE) && (endian == UVM_BIG_ENDIAN)) begin { >> { rw_access.data }} = { << byte { rw_access.data}}; end adapter.m_set_item(rw); bus_req = adapter.reg2bus(rw_access); adapter.m_set_item(null); if (bus_req == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"RegMem")) uvm_report_fatal ("RegMem", {"adapter [",adapter.get_name(),"] didnt return a bus transaction"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1823, "", 1); end bus_req.set_sequencer(sequencer); rw.parent.start_item(bus_req,rw.prior); if (rw.parent != null && i == 0) rw.parent.mid_do(rw); rw.parent.finish_item(bus_req); begin uvm_event#(uvm_object) end_event ; uvm_event_pool ep; ep = bus_req.get_event_pool(); end_event = ep.get("end") ; end_event.wait_on(); end if (adapter.provides_responses) begin uvm_sequence_item bus_rsp; uvm_access_e op; rw.parent.get_base_response(bus_rsp,bus_req.get_transaction_id()); adapter.bus2reg(bus_rsp,rw_access); end else begin adapter.bus2reg(bus_req,rw_access); end if ((rw_access.kind == UVM_READ) && (endian == UVM_BIG_ENDIAN)) begin { >> { rw_access.data }} = { << byte { rw_access.data}}; end rw.status = rw_access.status; begin data = rw_access.data & ((1<>bit_shift) & 'hff; p[idx]=n; end if(extra_byte) p.push_back(ac); end accesses.delete(); foreach(adr[i]) begin uvm_reg_bus_op rw_access; uvm_reg_data_t data; for(int i0=0;i0=0;i--) begin if(rw_access.byte_en[i]==0) rw_access.n_bits-=8; else break; end accesses.push_back(rw_access); end perform_accesses(accesses, rw, adapter, sequencer); if(rw.kind inside {UVM_READ,UVM_BURST_READ}) begin p.delete(); foreach(accesses[i0]) for(int i1=0;i1 max_size) max_size = uvm_reg_field::get_max_size(); if (uvm_mem::get_max_size() > max_size) max_size = uvm_mem::get_max_size(); if (max_size > 64) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"RegModel")) uvm_report_fatal ("RegModel", $sformatf("Register model requires that UVM_REG_DATA_WIDTH be defined as %0d or greater. Currently defined as %0d", max_size, 64), UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 1153, "", 1); end end Xinit_address_mapsX(); if(m_root_names[get_name()]>1) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/REG/DUPLROOT")) uvm_report_error ("UVM/REG/DUPLROOT", $sformatf("There are %0d root register models named \"%s\". The names of the root register models have to be unique", m_root_names[get_name()], get_name()), UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 1162, "", 1); end -> m_uvm_lock_model_complete; end endfunction function string uvm_reg_block::get_full_name(); if (parent == null) return get_name(); return {parent.get_full_name(), ".", get_name()}; endfunction: get_full_name function void uvm_reg_block::get_fields(ref uvm_reg_field fields[$], input uvm_hier_e hier=UVM_HIER); foreach (regs[rg_]) begin uvm_reg rg = rg_; rg.get_fields(fields); end if (hier == UVM_HIER) foreach (blks[blk_]) begin uvm_reg_block blk = blk_; blk.get_fields(fields); end endfunction: get_fields function void uvm_reg_block::get_virtual_fields(ref uvm_vreg_field fields[$], input uvm_hier_e hier=UVM_HIER); foreach (vregs[vreg_]) begin uvm_vreg vreg = vreg_; vreg.get_fields(fields); end if (hier == UVM_HIER) foreach (blks[blk_]) begin uvm_reg_block blk = blk_; blk.get_virtual_fields(fields); end endfunction: get_virtual_fields function void uvm_reg_block::get_registers(ref uvm_reg regs[$], input uvm_hier_e hier=UVM_HIER); foreach (this.regs[rg]) regs.push_back(rg); if (hier == UVM_HIER) foreach (blks[blk_]) begin uvm_reg_block blk = blk_; blk.get_registers(regs); end endfunction: get_registers function void uvm_reg_block::get_virtual_registers(ref uvm_vreg regs[$], input uvm_hier_e hier=UVM_HIER); foreach (vregs[rg]) regs.push_back(rg); if (hier == UVM_HIER) foreach (blks[blk_]) begin uvm_reg_block blk = blk_; blk.get_virtual_registers(regs); end endfunction: get_virtual_registers function void uvm_reg_block::get_memories(ref uvm_mem mems[$], input uvm_hier_e hier=UVM_HIER); foreach (this.mems[mem_]) begin uvm_mem mem = mem_; mems.push_back(mem); end if (hier == UVM_HIER) foreach (blks[blk_]) begin uvm_reg_block blk = blk_; blk.get_memories(mems); end endfunction: get_memories function void uvm_reg_block::get_blocks(ref uvm_reg_block blks[$], input uvm_hier_e hier=UVM_HIER); foreach (this.blks[blk_]) begin uvm_reg_block blk = blk_; blks.push_back(blk); if (hier == UVM_HIER) blk.get_blocks(blks); end endfunction: get_blocks function void uvm_reg_block::get_root_blocks(ref uvm_reg_block blks[$]); foreach (m_roots[blk]) begin blks.push_back(blk); end endfunction function int uvm_reg_block::find_blocks(input string name, ref uvm_reg_block blks[$], input uvm_reg_block root = null, input uvm_object accessor = null); uvm_reg_block r[$]; uvm_reg_block b[$]; if (root != null) begin name = {root.get_full_name(), ".", name}; b='{root}; end else begin get_root_blocks(b); end foreach(b[idx]) begin r.push_back(b[idx]); b[idx].get_blocks(r); end blks.delete(); foreach(r[idx]) begin if ( uvm_is_match( name, r[idx].get_full_name() ) ) blks.push_back(r[idx]); end return blks.size(); endfunction function uvm_reg_block uvm_reg_block::find_block(input string name, input uvm_reg_block root = null, input uvm_object accessor = null); uvm_reg_block blks[$]; if (!find_blocks(name, blks, root, accessor)) return null; if (blks.size() > 1) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"MRTH1BLK")) uvm_report_warning ("MRTH1BLK", {"More than one block matched the name \"", name, "\"."}, UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 1341, "", 1); end end return blks[0]; endfunction function void uvm_reg_block::get_maps(ref uvm_reg_map maps[$]); foreach (this.maps[map]) maps.push_back(map); endfunction function uvm_reg_block uvm_reg_block::get_parent(); get_parent = this.parent; endfunction: get_parent function uvm_reg_block uvm_reg_block::get_block_by_name(string name); if (get_name() == name) return this; foreach (blks[blk_]) begin uvm_reg_block blk = blk_; if (blk.get_name() == name) return blk; end foreach (blks[blk_]) begin uvm_reg_block blk = blk_; uvm_reg_block subblks[$]; blk_.get_blocks(subblks, UVM_HIER); foreach (subblks[j]) if (subblks[j].get_name() == name) return subblks[j]; end begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Unable to locate block '",name, "' in block '",get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 1395, "", 1); end return null; endfunction: get_block_by_name function uvm_reg uvm_reg_block::get_reg_by_name(string name); foreach (regs[rg_]) begin uvm_reg rg = rg_; if (rg.get_name() == name) return rg; end foreach (blks[blk_]) begin uvm_reg_block blk = blk_; uvm_reg subregs[$]; blk_.get_registers(subregs, UVM_HIER); foreach (subregs[j]) if (subregs[j].get_name() == name) return subregs[j]; end begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Unable to locate register '",name, "' in block '",get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 1422, "", 1); end return null; endfunction: get_reg_by_name function uvm_vreg uvm_reg_block::get_vreg_by_name(string name); foreach (vregs[rg_]) begin uvm_vreg rg = rg_; if (rg.get_name() == name) return rg; end foreach (blks[blk_]) begin uvm_reg_block blk = blk_; uvm_vreg subvregs[$]; blk_.get_virtual_registers(subvregs, UVM_HIER); foreach (subvregs[j]) if (subvregs[j].get_name() == name) return subvregs[j]; end begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Unable to locate virtual register '",name, "' in block '",get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 1449, "", 1); end return null; endfunction: get_vreg_by_name function uvm_mem uvm_reg_block::get_mem_by_name(string name); foreach (mems[mem_]) begin uvm_mem mem = mem_; if (mem.get_name() == name) return mem; end foreach (blks[blk_]) begin uvm_reg_block blk = blk_; uvm_mem submems[$]; blk_.get_memories(submems, UVM_HIER); foreach (submems[j]) if (submems[j].get_name() == name) return submems[j]; end begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Unable to locate memory '",name, "' in block '",get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 1476, "", 1); end return null; endfunction: get_mem_by_name function uvm_reg_field uvm_reg_block::get_field_by_name(string name); foreach (regs[rg_]) begin uvm_reg rg = rg_; uvm_reg_field fields[$]; rg.get_fields(fields); foreach (fields[i]) if (fields[i].get_name() == name) return fields[i]; end foreach (blks[blk_]) begin uvm_reg_block blk = blk_; uvm_reg subregs[$]; blk_.get_registers(subregs, UVM_HIER); foreach (subregs[j]) begin uvm_reg_field fields[$]; subregs[j].get_fields(fields); foreach (fields[i]) if (fields[i].get_name() == name) return fields[i]; end end begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Unable to locate field '",name, "' in block '",get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 1511, "", 1); end return null; endfunction: get_field_by_name function uvm_vreg_field uvm_reg_block::get_vfield_by_name(string name); foreach (vregs[rg_]) begin uvm_vreg rg =rg_; uvm_vreg_field fields[$]; rg.get_fields(fields); foreach (fields[i]) if (fields[i].get_name() == name) return fields[i]; end foreach (blks[blk_]) begin uvm_reg_block blk = blk_; uvm_vreg subvregs[$]; blk_.get_virtual_registers(subvregs, UVM_HIER); foreach (subvregs[j]) begin uvm_vreg_field fields[$]; subvregs[j].get_fields(fields); foreach (fields[i]) if (fields[i].get_name() == name) return fields[i]; end end begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Unable to locate virtual field '",name, "' in block '",get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 1547, "", 1); end return null; endfunction: get_vfield_by_name function uvm_reg_cvr_t uvm_reg_block::set_coverage(uvm_reg_cvr_t is_on); this.cover_on = this.has_cover & is_on; foreach (regs[rg_]) begin uvm_reg rg = rg_; void'(rg.set_coverage(is_on)); end foreach (mems[mem_]) begin uvm_mem mem = mem_; void'(mem.set_coverage(is_on)); end foreach (blks[blk_]) begin uvm_reg_block blk = blk_; void'(blk.set_coverage(is_on)); end return this.cover_on; endfunction: set_coverage function void uvm_reg_block::sample_values(); foreach (regs[rg_]) begin uvm_reg rg = rg_; rg.sample_values(); end foreach (blks[blk_]) begin uvm_reg_block blk = blk_; blk.sample_values(); end endfunction function void uvm_reg_block::XsampleX(uvm_reg_addr_t addr, bit is_read, uvm_reg_map map); sample(addr, is_read, map); if (parent != null) begin end endfunction function uvm_reg_cvr_t uvm_reg_block::build_coverage(uvm_reg_cvr_t models); build_coverage = UVM_NO_COVERAGE; void'(uvm_reg_cvr_rsrc_db::read_by_name({"uvm_reg::", get_full_name()}, "include_coverage", build_coverage, this)); return build_coverage & models; endfunction: build_coverage function void uvm_reg_block::add_coverage(uvm_reg_cvr_t models); this.has_cover |= models; endfunction: add_coverage function bit uvm_reg_block::has_coverage(uvm_reg_cvr_t models); return ((this.has_cover & models) == models); endfunction: has_coverage function bit uvm_reg_block::get_coverage(uvm_reg_cvr_t is_on = UVM_CVR_ALL); if (this.has_coverage(is_on) == 0) return 0; return ((this.cover_on & is_on) == is_on); endfunction: get_coverage function void uvm_reg_block::reset(string kind = "HARD"); foreach (regs[rg_]) begin uvm_reg rg = rg_; rg.reset(kind); end foreach (blks[blk_]) begin uvm_reg_block blk = blk_; blk.reset(kind); end endfunction function bit uvm_reg_block::needs_update(); needs_update = 0; foreach (regs[rg_]) begin uvm_reg rg = rg_; if (rg.needs_update()) return 1; end foreach (blks[blk_]) begin uvm_reg_block blk =blk_; if (blk.needs_update()) return 1; end endfunction: needs_update task uvm_reg_block::update(output uvm_status_e status, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); status = UVM_IS_OK; if (!needs_update()) begin begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("%s:%0d - RegModel block %s does not need updating", fname, lineno, this.get_name()), UVM_HIGH, "t/uvm/src/reg/uvm_reg_block.svh", 1694, "", 1); end return; end begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("%s:%0d - Updating model block %s with %s path", fname, lineno, this.get_name(), path.name ), UVM_HIGH, "t/uvm/src/reg/uvm_reg_block.svh", 1699, "", 1); end foreach (regs[rg_]) begin uvm_reg rg = rg_; if (rg.needs_update()) begin rg.update(status, path, null, parent, prior, extension); if (status != UVM_IS_OK && status != UVM_HAS_X) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Register \"%s\" could not be updated", rg.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 1707, "", 1); end return; end end end foreach (blks[blk_]) begin uvm_reg_block blk = blk_; blk.update(status,path,parent,prior,extension,fname,lineno); end endtask: update task uvm_reg_block::mirror(output uvm_status_e status, input uvm_check_e check = UVM_NO_CHECK, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_status_e final_status = UVM_IS_OK; foreach (regs[rg_]) begin uvm_reg rg = rg_; rg.mirror(status, check, path, null, parent, prior, extension, fname, lineno); if (status != UVM_IS_OK && status != UVM_HAS_X) begin final_status = status; end end foreach (blks[blk_]) begin uvm_reg_block blk = blk_; blk.mirror(status, check, path, parent, prior, extension, fname, lineno); if (status != UVM_IS_OK && status != UVM_HAS_X) begin final_status = status; end end endtask: mirror task uvm_reg_block::write_reg_by_name(output uvm_status_e status, input string name, input uvm_reg_data_t data, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg rg; this.fname = fname; this.lineno = lineno; status = UVM_NOT_OK; rg = this.get_reg_by_name(name); if (rg != null) rg.write(status, data, path, map, parent, prior, extension); endtask: write_reg_by_name task uvm_reg_block::read_reg_by_name(output uvm_status_e status, input string name, output uvm_reg_data_t data, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg rg; this.fname = fname; this.lineno = lineno; status = UVM_NOT_OK; rg = this.get_reg_by_name(name); if (rg != null) rg.read(status, data, path, map, parent, prior, extension); endtask: read_reg_by_name task uvm_reg_block::write_mem_by_name(output uvm_status_e status, input string name, input uvm_reg_addr_t offset, input uvm_reg_data_t data, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_mem mem; this.fname = fname; this.lineno = lineno; status = UVM_NOT_OK; mem = get_mem_by_name(name); if (mem != null) mem.write(status, offset, data, path, map, parent, prior, extension); endtask: write_mem_by_name task uvm_reg_block::read_mem_by_name(output uvm_status_e status, input string name, input uvm_reg_addr_t offset, output uvm_reg_data_t data, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_mem mem; this.fname = fname; this.lineno = lineno; status = UVM_NOT_OK; mem = get_mem_by_name(name); if (mem != null) mem.read(status, offset, data, path, map, parent, prior, extension); endtask: read_mem_by_name task uvm_reg_block::readmemh(string filename); endtask: readmemh task uvm_reg_block::writememh(string filename); endtask: writememh function uvm_reg_map uvm_reg_block::create_map(string name, uvm_reg_addr_t base_addr, int unsigned n_bytes, uvm_endianness_e endian, bit byte_addressing=1); uvm_reg_map map; map = uvm_reg_map::type_id::create(name,,this.get_full_name()); map.configure(this,base_addr,n_bytes,endian,byte_addressing); add_map(map); return map; endfunction function void uvm_reg_block::add_map(uvm_reg_map map); if (this.locked) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", "Cannot add map to locked model", UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 1890, "", 1); end return; end if (this.maps.exists(map)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Map '",map.get_name(), "' already exists in '",get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 1896, "", 1); end return; end this.maps[map] = 1; if (maps.num() == 1) default_map = map; endfunction: add_map function uvm_reg_map uvm_reg_block::get_map_by_name(string name); uvm_reg_map maps[$]; this.get_maps(maps); foreach (maps[i]) if (maps[i].get_name() == name) return maps[i]; foreach (maps[i]) begin uvm_reg_map submaps[$]; maps[i].get_submaps(submaps, UVM_HIER); foreach (submaps[j]) if (submaps[j].get_name() == name) return submaps[j]; end begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Map with name '",name,"' does not exist in block"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 1928, "", 1); end return null; endfunction function void uvm_reg_block::set_default_map(uvm_reg_map map); if (!maps.exists(map)) begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Map '",map.get_full_name(),"' does not exist in block"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 1937, "", 1); end default_map = map; endfunction function uvm_reg_map uvm_reg_block::get_default_map(); return default_map; endfunction function uvm_door_e uvm_reg_block::get_default_door(); if (this.default_path != UVM_DEFAULT_DOOR) return this.default_path; if (this.parent != null) return this.parent.get_default_door(); return UVM_FRONTDOOR; endfunction function void uvm_reg_block::set_default_door(uvm_door_e door); this.default_path = door; endfunction function void uvm_reg_block::Xinit_address_mapsX(); foreach (maps[map_]) begin uvm_reg_map map = map_; map.Xinit_address_mapX(); end endfunction function void uvm_reg_block::set_backdoor(uvm_reg_backdoor bkdr, string fname = "", int lineno = 0); bkdr.fname = fname; bkdr.lineno = lineno; if (this.backdoor != null && this.backdoor.has_update_threads()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", "Previous register backdoor still has update threads running. Backdoors with active mirroring should only be set before simulation starts.", UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 2000, "", 1); end end this.backdoor = bkdr; endfunction: set_backdoor function uvm_reg_backdoor uvm_reg_block::get_backdoor(bit inherited = 1); if (backdoor == null && inherited) begin uvm_reg_block blk = get_parent(); while (blk != null) begin uvm_reg_backdoor bkdr = blk.get_backdoor(); if (bkdr != null) return bkdr; blk = blk.get_parent(); end end return this.backdoor; endfunction: get_backdoor function void uvm_reg_block::clear_hdl_path(string kind = "RTL"); if (kind == "ALL") begin hdl_paths_pool = new("hdl_paths"); return; end if (kind == "") kind = get_default_hdl_path(); if (!hdl_paths_pool.exists(kind)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Unknown HDL Abstraction '",kind,"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 2036, "", 1); end return; end hdl_paths_pool.delete(kind); endfunction function void uvm_reg_block::add_hdl_path(string path, string kind = "RTL"); uvm_queue #(string) paths; paths = hdl_paths_pool.get(kind); paths.push_back(path); endfunction function bit uvm_reg_block::has_hdl_path(string kind = ""); if (kind == "") begin kind = get_default_hdl_path(); end return hdl_paths_pool.exists(kind); endfunction function void uvm_reg_block::get_hdl_path(ref string paths[$], input string kind = ""); uvm_queue #(string) hdl_paths; if (kind == "") kind = get_default_hdl_path(); if (!has_hdl_path(kind)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Block does not have hdl path defined for abstraction '",kind,"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 2077, "", 1); end return; end hdl_paths = hdl_paths_pool.get(kind); for (int i=0; i 0) begin mem.read(status, k-1, val, UVM_FRONTDOOR, maps[j], this); if (status != UVM_IS_OK) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"uvm_mem_walk_seq")) uvm_report_error ("uvm_mem_walk_seq", $sformatf("Status was %s when reading \"%s[%0d]\" through map \"%s\".", status.name(), mem.get_full_name(), k, maps[j].get_full_name()), UVM_NONE, "t/uvm/src/reg/sequences/uvm_mem_walk_seq.svh", 143, "", 1); end end else begin exp = ~(k-1) & ((1'b1< 32) val = uvm_reg_data_t'(val << 32) | $random; if (mode == "RO") begin mem.peek(status, k, exp); if (status != UVM_IS_OK) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"uvm_mem_access_seq")) uvm_report_error ("uvm_mem_access_seq", $sformatf("Status was %s when reading \"%s[%0d]\" through backdoor.", status.name(), mem.get_full_name(), k), UVM_NONE, "t/uvm/src/reg/sequences/uvm_mem_access_seq.svh", 124, "", 1); end end end else exp = val; mem.write(status, k, val, UVM_FRONTDOOR, maps[j], this); if (status != UVM_IS_OK) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"uvm_mem_access_seq")) uvm_report_error ("uvm_mem_access_seq", $sformatf("Status was %s when writing \"%s[%0d]\" through map \"%s\".", status.name(), mem.get_full_name(), k, maps[j].get_full_name()), UVM_NONE, "t/uvm/src/reg/sequences/uvm_mem_access_seq.svh", 132, "", 1); end end #1; val = 'x; mem.peek(status, k, val); if (status != UVM_IS_OK) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"uvm_mem_access_seq")) uvm_report_error ("uvm_mem_access_seq", $sformatf("Status was %s when reading \"%s[%0d]\" through backdoor.", status.name(), mem.get_full_name(), k), UVM_NONE, "t/uvm/src/reg/sequences/uvm_mem_access_seq.svh", 140, "", 1); end end else begin if (val !== exp) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"uvm_mem_access_seq")) uvm_report_error ("uvm_mem_access_seq", $sformatf("Backdoor \"%s[%0d]\" read back as 'h%h instead of 'h%h.", mem.get_full_name(), k, val, exp), UVM_NONE, "t/uvm/src/reg/sequences/uvm_mem_access_seq.svh", 145, "", 1); end end end exp = ~exp & ((1'b1< local_size__) abstractions = abstractions[0:local_size__-1]; else while (abstractions.size() < local_size__) abstractions.push_back(abstractions[local_size__]); foreach (abstractions[i]) abstractions[i] = __local_packer__.unpack_string(); end UVM_RECORD: if (!((UVM_DEFAULT)&UVM_NORECORD)) begin begin int sz__; foreach (abstractions[i]) sz__ = i; if(sz__ == 0) begin if (__local_recorder__ != null && __local_recorder__.is_open()) begin if (__local_recorder__.use_record_attribute()) __local_recorder__.record_generic("abstractions", $sformatf("%p", 0)); else if (32 > 64) __local_recorder__.record_field("abstractions", 0, 32, UVM_DEC); else __local_recorder__.record_field_int("abstractions", 0, 32, UVM_DEC); end end else if(sz__ < 10) begin foreach(abstractions[i]) begin string nm__ = $sformatf("%s[%0d]", "abstractions", i); if (__local_recorder__ != null && __local_recorder__.is_open()) begin if (__local_recorder__.use_record_attribute()) __local_recorder__.record_generic(nm__, $sformatf("%p", abstractions[i])); else __local_recorder__.record_string(nm__,abstractions[i]); end end end else begin for(int i=0; i<5; ++i) begin string nm__ = $sformatf("%s[%0d]", "abstractions", i); if (__local_recorder__ != null && __local_recorder__.is_open()) begin if (__local_recorder__.use_record_attribute()) __local_recorder__.record_generic(nm__, $sformatf("%p", abstractions[i])); else __local_recorder__.record_string(nm__,abstractions[i]); end end for(int i=sz__-5; i __tmp_curr) __tmp_curr = __tmp_max - __tmp_end_elements; if (__tmp_curr < __tmp_begin_elements) __tmp_curr = __tmp_begin_elements; else __local_printer__.print_array_range(__tmp_begin_elements, __tmp_curr-1); while (__tmp_curr < __tmp_max) begin __local_printer__.print_string($sformatf("[%0d]", __tmp_curr), abstractions[__tmp_curr]); __tmp_curr++; end end end end __local_printer__.print_array_footer(__tmp_max); end end UVM_SET: if (!((UVM_DEFAULT)&UVM_NOSET)) begin if(local_rsrc_name__ == "abstractions") begin begin begin uvm_resource#(uvm_integral_t) __tmp_rsrc__; local_success__ = $cast(__tmp_rsrc__, local_rsrc__); if (local_success__) begin local_size__ = __tmp_rsrc__.read(this); end end if (!local_success__) begin uvm_resource#(uvm_bitstream_t) __tmp_rsrc__; local_success__ = $cast(__tmp_rsrc__, local_rsrc__); if (local_success__) begin local_size__ = __tmp_rsrc__.read(this); end end if (!local_success__) begin uvm_resource#(int) __tmp_rsrc__; local_success__ = $cast(__tmp_rsrc__, local_rsrc__); if (local_success__) begin local_size__ = __tmp_rsrc__.read(this); end end if (!local_success__) begin uvm_resource#(int unsigned) __tmp_rsrc__; local_success__ = $cast(__tmp_rsrc__, local_rsrc__); if (local_success__) begin local_size__ = __tmp_rsrc__.read(this); end end end if (local_success__) if (abstractions.size() > local_size__) abstractions = abstractions[0:local_size__-1]; else while (abstractions.size() < local_size__) abstractions.push_back(abstractions[local_size__]); end else begin string local_name__ = {"abstractions", "["}; if (local_rsrc_name__.len() && local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), local_rsrc_name__.len()-2); int local_index__; int local_code__ = $sscanf(local_index_str__, "%d", local_index__); if (local_code__ > 0) begin if (local_index__ < 0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/FIELDS/QDA_IDX")) uvm_report_warning ("UVM/FIELDS/QDA_IDX", $sformatf("Index '%0d' is not valid for field '%s.%s' of size '%0d'", local_index__, get_full_name(), "abstractions", abstractions.size() ), UVM_NONE, "t/uvm/src/reg/sequences/uvm_reg_mem_hdl_paths_seq.svh", 59, "", 1); end end else begin string tmp_string__; begin uvm_resource#(string) __tmp_rsrc__; local_success__ = $cast(__tmp_rsrc__, local_rsrc__); if (local_success__) begin tmp_string__ = __tmp_rsrc__.read(this); end end if (local_success__) begin if (local_index__ >= abstractions.size()) if (abstractions.size() > local_index__ + 1) abstractions = abstractions[0:local_index__ + 1-1]; else while (abstractions.size() < local_index__ + 1) abstractions.push_back(abstractions[local_index__ + 1]); abstractions[local_index__] = tmp_string__; end end end end end end endcase end endfunction : __m_uvm_execute_field_op function new(string name="uvm_reg_mem_hdl_paths_seq"); super.new(name); endfunction virtual task body(); if (model == null) begin uvm_report_error("uvm_reg_mem_hdl_paths_seq", "Register model handle is null"); return; end begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,"uvm_reg_mem_hdl_paths_seq")) uvm_report_info ("uvm_reg_mem_hdl_paths_seq", {"checking HDL paths for all registers/memories in ", model.get_full_name()}, UVM_LOW, "t/uvm/src/reg/sequences/uvm_reg_mem_hdl_paths_seq.svh", 76, "", 1); end if (abstractions.size() == 0) do_block(model, ""); else begin foreach (abstractions[i]) do_block(model, abstractions[i]); end begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,"uvm_reg_mem_hdl_paths_seq")) uvm_report_info ("uvm_reg_mem_hdl_paths_seq", "HDL path validation completed ", UVM_LOW, "t/uvm/src/reg/sequences/uvm_reg_mem_hdl_paths_seq.svh", 85, "", 1); end endtask: body virtual task reset_blk(uvm_reg_block blk); endtask protected virtual function void do_block(uvm_reg_block blk, string kind); uvm_reg regs[$]; uvm_mem mems[$]; begin if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"uvm_reg_mem_hdl_paths_seq")) uvm_report_info ("uvm_reg_mem_hdl_paths_seq", {"Validating HDL paths in ", blk.get_full_name(), " for ", (kind == "") ? "default" : kind, " design abstraction"}, UVM_MEDIUM, "t/uvm/src/reg/sequences/uvm_reg_mem_hdl_paths_seq.svh", 104, "", 1); end blk.get_registers(regs, UVM_NO_HIER); foreach (regs[i]) check_reg(regs[i], kind); blk.get_memories(mems, UVM_NO_HIER); foreach (mems[i]) check_mem(mems[i], kind); begin uvm_reg_block blks[$]; blk.get_blocks(blks); foreach (blks[i]) begin do_block(blks[i], kind); end end endfunction: do_block protected virtual function void check_reg(uvm_reg r, string kind); uvm_hdl_path_concat paths[$]; if(!r.has_hdl_path(kind)) return; r.get_full_hdl_path(paths, kind); if (paths.size() == 0) return; foreach(paths[p]) begin uvm_hdl_path_concat path=paths[p]; foreach (path.slices[j]) begin string p_ = path.slices[j].path; uvm_reg_data_t d; if (!uvm_hdl_read(p_,d)) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"uvm_reg_mem_hdl_paths_seq")) uvm_report_error ("uvm_reg_mem_hdl_paths_seq", $sformatf("HDL path \"%s\" for register \"%s\" is not readable", p_, r.get_full_name()), UVM_NONE, "t/uvm/src/reg/sequences/uvm_reg_mem_hdl_paths_seq.svh", 145, "", 1); end if (!uvm_hdl_check_path(p_)) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"uvm_reg_mem_hdl_paths_seq")) uvm_report_error ("uvm_reg_mem_hdl_paths_seq", $sformatf("HDL path \"%s\" for register \"%s\" is not accessible", p_, r.get_full_name()), UVM_NONE, "t/uvm/src/reg/sequences/uvm_reg_mem_hdl_paths_seq.svh", 149, "", 1); end end end endfunction protected virtual function void check_mem(uvm_mem m, string kind); uvm_hdl_path_concat paths[$]; if(!m.has_hdl_path(kind)) return; m.get_full_hdl_path(paths, kind); if (paths.size() == 0) return; foreach(paths[p]) begin uvm_hdl_path_concat path=paths[p]; foreach (path.slices[j]) begin string p_ = path.slices[j].path; if(!uvm_hdl_check_path(p_)) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"uvm_reg_mem_hdl_paths_seq")) uvm_report_error ("uvm_reg_mem_hdl_paths_seq", $sformatf("HDL path \"%s\" for memory \"%s\" is not accessible", p_, m.get_full_name()), UVM_NONE, "t/uvm/src/reg/sequences/uvm_reg_mem_hdl_paths_seq.svh", 174, "", 1); end end end endfunction endclass: uvm_reg_mem_hdl_paths_seq endpackage verilator-5.044/test_regress/t/uvm/uvm_pkg_all_v2020_3_1_nodpi.svh0000644000542200017500000721770615125463617025442 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Concatenated UVM header for internal testing // SPDX-License-Identifier: Apache-2.0 //---------------------------------------------------------------------- // To recreate: // Using verilator_ext_tests: // t_uvm_hello_v2020_3_1_nodpi --gold // //---------------------------------------------------------------------- // Copyright 2007-2022 Cadence Design Systems, Inc. // Copyright 2023 Intel Corporation // Copyright 2007-2011 Mentor Graphics Corporation // Copyright 2013-2024 NVIDIA Corporation // Copyright 2011-2022 Synopsys, Inc. // All Rights Reserved Worldwide // // Licensed under the Apache License, Version 2.0 (the // "License"); you may not use this file except in // compliance with the License. You may obtain a copy of // the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in // writing, software distributed under the License is // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See // the License for the specific language governing // permissions and limitations under the License. //---------------------------------------------------------------------- `define UVM_NO_DPI `define UVM_PKG_SV `define UVM_MACROS_SVH `define UVM_STRING_QUEUE_STREAMING_PACK(q) uvm_pkg::m_uvm_string_queue_join(q) `define uvm_typename(X) $typename(X) `define uvm_delay(TIME) #(TIME); `define UVM_VERSION_DEFINES_SVH `define UVM_VERSION 2020 `define UVM_VERSION_POST_2017 `define UVM_VERSION_POST_2017_1_0 `define UVM_VERSION_POST_2017_1_1 `define UVM_VERSION_POST_2020_1_0 `define UVM_VERSION_POST_2020_1_1 `define UVM_VERSION_POST_2020_2_0 `define UVM_NAME UVM `define UVM_MAJOR_REV 2020 `define UVM_MINOR_REV 3.0 `define UVM_VERSION_STRING uvm_pkg::UVM_VERSION_STRING `define UVM_POST_VERSION_1_1 `define UVM_POST_VERSION_1_2 `define UVM_GLOBAL_DEFINES_SVH `define UVM_COMPONENT_CONFIG_MODE_DEFAULT CONFIG_CHECK_NAMES `define UVM_MAX_STREAMBITS 4096 `define UVM_PACKER_MAX_BYTES `UVM_MAX_STREAMBITS `define UVM_DEFAULT_TIMEOUT 9200s `define UVM_MESSAGE_DEFINES_SVH `define UVM_LINE_WIDTH 120 `define UVM_NUM_LINES 120 `define uvm_file `__FILE__ `define uvm_line `__LINE__ `define uvm_report_begin(SEVERITY, ID, VERBOSITY, RO=uvm_get_report_object()) \ begin \ uvm_pkg::uvm_report_object _local_report_object_;\ _local_report_object_ = RO.uvm_get_report_object() ; \ if ((_local_report_object_.get_report_verbosity_level(SEVERITY, ID) >= VERBOSITY) && \ (_local_report_object_.get_report_action(SEVERITY, ID) != uvm_pkg::UVM_NO_ACTION)) begin `define uvm_report_end \ end \ end `define uvm_info(ID, MSG, VERBOSITY) \ `uvm_report_begin(uvm_pkg::UVM_INFO, ID, VERBOSITY) \ uvm_report_info(ID, MSG, VERBOSITY, `uvm_file, `uvm_line, "", 1); \ `uvm_report_end `define uvm_warning(ID, MSG) \ `uvm_report_begin(uvm_pkg::UVM_WARNING, ID, uvm_pkg::UVM_NONE) \ uvm_report_warning(ID, MSG, uvm_pkg::UVM_NONE, `uvm_file, `uvm_line, "", 1); \ `uvm_report_end `define uvm_error(ID, MSG) \ `uvm_report_begin(uvm_pkg::UVM_ERROR, ID, uvm_pkg::UVM_NONE) \ uvm_report_error(ID, MSG, uvm_pkg::UVM_NONE, `uvm_file, `uvm_line, "", 1); \ `uvm_report_end `define uvm_fatal(ID, MSG) \ `uvm_report_begin(uvm_pkg::UVM_FATAL, ID, uvm_pkg::UVM_NONE) \ uvm_report_fatal(ID, MSG, uvm_pkg::UVM_NONE, `uvm_file, `uvm_line, "", 1); \ `uvm_report_end `define uvm_info_context(ID, MSG, VERBOSITY, RO) \ `uvm_report_begin(uvm_pkg::UVM_INFO, ID, VERBOSITY, RO) \ _local_report_object_.uvm_report_info(ID, MSG, VERBOSITY, `uvm_file, `uvm_line, "", 1); \ `uvm_report_end `define uvm_warning_context(ID, MSG, RO) \ `uvm_report_begin(uvm_pkg::UVM_WARNING, ID, uvm_pkg::UVM_NONE, RO) \ _local_report_object_.uvm_report_warning(ID, MSG, uvm_pkg::UVM_NONE, `uvm_file, `uvm_line, "", 1); \ `uvm_report_end `define uvm_error_context(ID, MSG, RO) \ `uvm_report_begin(uvm_pkg::UVM_ERROR, ID, uvm_pkg::UVM_NONE, RO) \ _local_report_object_.uvm_report_error(ID, MSG, uvm_pkg::UVM_NONE, `uvm_file, `uvm_line, "", 1); \ `uvm_report_end `define uvm_fatal_context(ID, MSG, RO) \ `uvm_report_begin(uvm_pkg::UVM_FATAL, ID, uvm_pkg::UVM_NONE, RO) \ _local_report_object_.uvm_report_fatal(ID, MSG, uvm_pkg::UVM_NONE, `uvm_file, `uvm_line, "", 1); \ `uvm_report_end `define uvm_message_begin(SEVERITY, ID, MSG, VERBOSITY, FILE, LINE, RM) \ `uvm_report_begin(SEVERITY, ID, VERBOSITY) \ uvm_pkg::uvm_report_message __uvm_msg; \ if (RM == null) RM = uvm_pkg::uvm_report_message::new_report_message(); \ __uvm_msg = RM; \ __uvm_msg.set_report_message(SEVERITY, ID, MSG, VERBOSITY, FILE, LINE, ""); `define uvm_message_end \ uvm_process_report_message(__uvm_msg); \ `uvm_report_end `define uvm_message_context_begin(SEVERITY, ID, MSG, VERBOSITY, FILE, LINE, RO, RM) \ `uvm_report_begin(SEVERITY, ID, VERBOSITY, RO) \ uvm_pkg::uvm_report_object __report_object; \ uvm_pkg::uvm_report_message __uvm_msg; \ __report_object = RO; \ if (RM == null) RM = uvm_pkg::uvm_report_message::new_report_message(); \ __uvm_msg = RM; \ __uvm_msg.set_report_message(SEVERITY, ID, MSG, VERBOSITY, FILE, LINE, ""); `define uvm_message_context_end \ __report_object.uvm_process_report_message(__uvm_msg); \ `uvm_report_end `define uvm_info_begin(ID, MSG, VERBOSITY, RM = __uvm_msg) \ `uvm_message_begin(uvm_pkg::UVM_INFO, ID, MSG, VERBOSITY, `uvm_file, `uvm_line, RM) `define uvm_info_end \ `uvm_message_end `define uvm_warning_begin(ID, MSG, RM = __uvm_msg) \ `uvm_message_begin(uvm_pkg::UVM_WARNING, ID, MSG, uvm_pkg::UVM_NONE, `uvm_file, `uvm_line, RM) `define uvm_warning_end \ `uvm_message_end `define uvm_error_begin(ID, MSG, RM = __uvm_msg) \ `uvm_message_begin(uvm_pkg::UVM_ERROR, ID, MSG, uvm_pkg::UVM_NONE, `uvm_file, `uvm_line, RM) `define uvm_error_end \ `uvm_message_end `define uvm_fatal_begin(ID, MSG, RM = __uvm_msg) \ `uvm_message_begin(uvm_pkg::UVM_FATAL, ID, MSG, uvm_pkg::UVM_NONE, `uvm_file, `uvm_line, RM) `define uvm_fatal_end \ `uvm_message_end `define uvm_info_context_begin(ID, MSG, VERBOSITY, RO, RM = __uvm_msg) \ `uvm_message_context_begin(uvm_pkg::UVM_INFO, ID, MSG, VERBOSITY, `uvm_file, `uvm_line, RO, RM) `define uvm_info_context_end \ `uvm_message_context_end `define uvm_warning_context_begin(ID, MSG, RO, RM = __uvm_msg) \ `uvm_message_context_begin(uvm_pkg::UVM_WARNING, ID, MSG, uvm_pkg::UVM_NONE, `uvm_file, `uvm_line, RO, RM) `define uvm_warning_context_end \ `uvm_message_context_end `define uvm_error_context_begin(ID, MSG, RO, RM = __uvm_msg) \ `uvm_message_context_begin(uvm_pkg::UVM_ERROR, ID, MSG, uvm_pkg::UVM_NONE, `uvm_file, `uvm_line, RO, RM) `define uvm_error_context_end \ `uvm_message_context_end `define uvm_fatal_context_begin(ID, MSG, RO, RM = __uvm_msg) \ `uvm_message_context_begin(uvm_pkg::UVM_FATAL, ID, MSG, uvm_pkg::UVM_NONE, `uvm_file, `uvm_line, RO, RM) `define uvm_fatal_context_end \ `uvm_message_context_end `define uvm_message_add_tag(NAME, VALUE, ACTION=(uvm_pkg::UVM_LOG|uvm_pkg::UVM_RM_RECORD)) \ __uvm_msg.add_string(NAME, VALUE, ACTION); `define uvm_message_add_int(VAR, RADIX, LABEL="", ACTION=(uvm_pkg::UVM_LOG|uvm_pkg::UVM_RM_RECORD)) \ if (LABEL == "") \ __uvm_msg.add_int(`"VAR`", VAR, $bits(VAR), RADIX, ACTION); \ else \ __uvm_msg.add_int(LABEL, VAR, $bits(VAR), RADIX, ACTION); `define uvm_message_add_string(VAR, LABEL="", ACTION=(uvm_pkg::UVM_LOG|uvm_pkg::UVM_RM_RECORD)) \ if (LABEL == "") \ __uvm_msg.add_string(`"VAR`", VAR, ACTION); \ else \ __uvm_msg.add_string(LABEL, VAR, ACTION); `define uvm_message_add_object(VAR, LABEL="", ACTION=(uvm_pkg::UVM_LOG|uvm_pkg::UVM_RM_RECORD)) \ if (LABEL == "") \ __uvm_msg.add_object(`"VAR`", VAR, ACTION); \ else \ __uvm_msg.add_object(LABEL, VAR, ACTION); `define UVM_PHASE_DEFINES_SVH `define m_uvm_task_phase(PHASE,COMP,PREFIX) \ class PREFIX``PHASE``_phase extends uvm_task_phase; \ virtual task exec_task(uvm_component comp, uvm_phase phase); \ COMP comp_; \ if ($cast(comp_,comp)) \ comp_.``PHASE``_phase(phase); \ endtask \ local static PREFIX``PHASE``_phase m_inst; \ `uvm_type_name_decl(`"PREFIX``PHASE``_phase`") \ static function PREFIX``PHASE``_phase get(); \ if(m_inst == null) begin \ m_inst = new; \ end \ return m_inst; \ endfunction \ protected function new(string name=`"PHASE`"); \ super.new(name); \ endfunction \ endclass \ `define m_uvm_topdown_phase(PHASE,COMP,PREFIX) \ class PREFIX``PHASE``_phase extends uvm_topdown_phase; \ virtual function void exec_func(uvm_component comp, uvm_phase phase); \ COMP comp_; \ if ($cast(comp_,comp)) \ comp_.``PHASE``_phase(phase); \ endfunction \ local static PREFIX``PHASE``_phase m_inst; \ `uvm_type_name_decl(`"PREFIX``PHASE``_phase`") \ static function PREFIX``PHASE``_phase get(); \ if(m_inst == null) begin \ m_inst = new(); \ end \ return m_inst; \ endfunction \ protected function new(string name=`"PHASE`"); \ super.new(name); \ endfunction \ endclass \ `define m_uvm_bottomup_phase(PHASE,COMP,PREFIX) \ class PREFIX``PHASE``_phase extends uvm_bottomup_phase; \ virtual function void exec_func(uvm_component comp, uvm_phase phase); \ COMP comp_; \ if ($cast(comp_,comp)) \ comp_.``PHASE``_phase(phase); \ endfunction \ static PREFIX``PHASE``_phase m_inst; \ `uvm_type_name_decl(`"PREFIX``PHASE``_phase`") \ static function PREFIX``PHASE``_phase get(); \ if(m_inst == null) begin \ m_inst = new(); \ end \ return m_inst; \ endfunction \ protected function new(string name=`"PHASE`"); \ super.new(name); \ endfunction \ endclass \ `define uvm_builtin_task_phase(PHASE) \ `m_uvm_task_phase(PHASE,uvm_component,uvm_) `define uvm_builtin_topdown_phase(PHASE) \ `m_uvm_topdown_phase(PHASE,uvm_component,uvm_) `define uvm_builtin_bottomup_phase(PHASE) \ `m_uvm_bottomup_phase(PHASE,uvm_component,uvm_) `define uvm_user_task_phase(PHASE,COMP,PREFIX) \ `m_uvm_task_phase(PHASE,COMP,PREFIX) `define uvm_user_topdown_phase(PHASE,COMP,PREFIX) \ `m_uvm_topdown_phase(PHASE,COMP,PREFIX) `define uvm_user_bottomup_phase(PHASE,COMP,PREFIX) \ `m_uvm_bottomup_phase(PHASE,COMP,PREFIX) `define UVM_PRINTER_DEFINES_SVH `define uvm_print_int(VALUE, SIZE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ `uvm_print_named_int(`"VALUE`", VALUE, SIZE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_named_int(NAME, VALUE, SIZE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ if (SIZE > 64) \ PRINTER.print_field(NAME, VALUE, SIZE, RADIX, ".", `"VALUE_TYPE`"); \ else \ PRINTER.print_field_int(NAME, VALUE, SIZE, RADIX, ".", `"VALUE_TYPE`"); `define uvm_print_real(VALUE, PRINTER=printer) \ `uvm_print_named_real(`"VALUE`", VALUE, PRINTER) `define uvm_print_named_real(NAME, VALUE, PRINTER=printer) \ PRINTER.print_real(NAME, VALUE); `define uvm_print_enum(TYPE, VALUE, PRINTER=printer) \ `uvm_print_named_enum(TYPE, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_enum(TYPE, NAME, VALUE, PRINTER=printer) \ if (VALUE.name() == "") \ `uvm_print_named_int(NAME, VALUE, $bits(VALUE), UVM_NORADIX, TYPE, PRINTER) \ else \ PRINTER.print_generic(NAME, `"TYPE`", $bits(VALUE), VALUE.name()); `define uvm_print_object(VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ `uvm_print_named_object(`"VALUE`", VALUE, RECURSION_POLICY, PRINTER) `define uvm_print_named_object(NAME, VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ if ((RECURSION_POLICY != UVM_DEFAULT_POLICY) && \ (RECURSION_POLICY != PRINTER.get_recursion_policy())) begin \ uvm_recursion_policy_enum __saved_recursion_policy = PRINTER.get_recursion_policy(); \ PRINTER.set_recursion_policy(RECURSION_POLICY); \ `m_uvm_print_named_object(NAME, VALUE, PRINTER) \ PRINTER.set_recursion_policy(__saved_recursion_policy); \ end \ else begin \ `m_uvm_print_named_object(NAME, VALUE, PRINTER) \ end `define m_uvm_print_named_object(NAME, VALUE, PRINTER) \ if (PRINTER.object_printed(VALUE, PRINTER.get_recursion_policy()) != uvm_policy::NEVER) begin \ uvm_recursion_policy_enum __saved_recursion_policy = PRINTER.get_recursion_policy(); \ PRINTER.set_recursion_policy(UVM_REFERENCE); \ PRINTER.print_object(NAME, VALUE); \ PRINTER.set_recursion_policy(__saved_recursion_policy); \ end \ else begin \ PRINTER.print_object(NAME, VALUE); \ end `define uvm_print_string(VALUE, PRINTER=printer) \ `uvm_print_named_string(`"VALUE`", VALUE, PRINTER) `define uvm_print_named_string(NAME, VALUE, PRINTER=printer) \ PRINTER.print_string(NAME, VALUE); `define uvm_print_qda_int(ARRAY_TYPE, VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ `uvm_print_named_qda_int(ARRAY_TYPE, `"VALUE`", VALUE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_named_qda_int(ARRAY_TYPE, NAME, VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ begin \ int __tmp_max = $right(VALUE) + 1; \ PRINTER.print_array_header(NAME, \ __tmp_max, \ `"ARRAY_TYPE``(``VALUE_TYPE``)`"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ int __tmp_begin_elements, __tmp_end_elements; \ __tmp_begin_elements = PRINTER.get_begin_elements(); \ __tmp_end_elements = PRINTER.get_end_elements(); \ /* Fast Bypass */ \ if (__tmp_begin_elements == -1 || __tmp_end_elements == -1) begin \ foreach (VALUE[__tmp_index]) begin \ `uvm_print_named_int($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ $bits(VALUE[__tmp_index]), \ RADIX, \ VALUE_TYPE, \ PRINTER) \ end \ end \ else begin \ int __tmp_curr; \ foreach(VALUE[__tmp_index]) begin \ if (__tmp_curr < __tmp_begin_elements) begin \ `uvm_print_named_int($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ $bits(VALUE[__tmp_index]), \ RADIX, \ VALUE_TYPE, \ PRINTER) \ end \ else \ break; \ __tmp_curr++; \ end \ if (__tmp_curr < __tmp_max ) begin \ if ((__tmp_max - __tmp_end_elements) > __tmp_curr) \ __tmp_curr = __tmp_max - __tmp_end_elements; \ if (__tmp_curr < __tmp_begin_elements) \ __tmp_curr = __tmp_begin_elements; \ else \ PRINTER.print_array_range(__tmp_begin_elements, __tmp_curr-1); \ while (__tmp_curr < __tmp_max) begin \ `uvm_print_named_int($sformatf("[%0d]", __tmp_curr), \ VALUE[__tmp_curr], \ $bits(VALUE[__tmp_curr]), \ RADIX, \ VALUE_TYPE, \ PRINTER) \ __tmp_curr++; \ end \ end \ end \ end \ PRINTER.print_array_footer(__tmp_max); \ end `define uvm_print_array_int(VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ `uvm_print_named_qda_int(da, `"VALUE`", VALUE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_named_array_int(NAME, VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ `uvm_print_named_qda_int(da, NAME, VALUE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_sarray_int(VALUE, RADIX=UVM_RADIX, VALUE_TYPE=integral, PRINTER=printer) \ `uvm_print_named_qda_int(sa, `"VALUE`", VALUE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_named_sarray_int(NAME, VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ `uvm_print_named_qda_int(sa, NAME, VALUE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_queue_int(VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ `uvm_print_named_qda_int(queue, `"VALUE`", VALUE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_named_queue_int(NAME, VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ `uvm_print_named_qda_int(queue, NAME, VALUE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_qda_real(ARRAY_TYPE, VALUE, PRINTER=printer) \ `uvm_print_named_qda_real(ARRAY_TYPE, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_qda_real(ARRAY_TYPE, NAME, VALUE, PRINTER=printer) \ begin \ int __tmp_max = $right(VALUE) + 1; \ PRINTER.print_array_header(NAME, \ __tmp_max, \ `"ARRAY_TYPE``(real)`"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ int __tmp_begin_elements, __tmp_end_elements; \ __tmp_begin_elements = PRINTER.get_begin_elements(); \ __tmp_end_elements = PRINTER.get_end_elements(); \ /* Fast Bypass */ \ if (__tmp_begin_elements == -1 || __tmp_end_elements == -1) begin \ foreach (VALUE[__tmp_index]) begin \ `uvm_print_named_real($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER) \ end \ end \ else begin \ int __tmp_curr; \ foreach(VALUE[__tmp_index]) begin \ if (__tmp_curr < __tmp_begin_elements) begin \ `uvm_print_named_real($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER) \ end \ else \ break; \ __tmp_curr++; \ end \ if (__tmp_curr < __tmp_max ) begin \ if ((__tmp_max - __tmp_end_elements) > __tmp_curr) \ __tmp_curr = __tmp_max - __tmp_end_elements; \ if (__tmp_curr < __tmp_begin_elements) \ __tmp_curr = __tmp_begin_elements; \ else \ PRINTER.print_array_range(__tmp_begin_elements, __tmp_curr-1); \ while (__tmp_curr < __tmp_max) begin \ `uvm_print_named_real($sformatf("[%0d]", __tmp_curr), \ VALUE[__tmp_curr], \ PRINTER) \ __tmp_curr++; \ end \ end \ end \ end \ PRINTER.print_array_footer(__tmp_max); \ end `define uvm_print_array_real(VALUE, PRINTER=printer) \ `uvm_print_named_qda_real(da, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_array_real(NAME, VALUE, PRINTER=printer) \ `uvm_print_named_qda_real(da, NAME, VALUE, PRINTER) `define uvm_print_sarray_real(VALUE, PRINTER=printer) \ `uvm_print_named_qda_real(sa, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_sarray_real(NAME, VALUE, PRINTER=printer) \ `uvm_print_named_qda_real(sa, NAME, VALUE, PRINTER) `define uvm_print_queue_real(VALUE,PRINTER=printer) \ `uvm_print_named_qda_real(queue, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_queue_real(NAME, VALUE, PRINTER=printer) \ `uvm_print_named_qda_real(queue, NAME, VALUE, PRINTER) `define uvm_print_qda_enum(ARRAY_TYPE, TYPE, VALUE, PRINTER=printer) \ `uvm_print_named_qda_enum(ARRAY_TYPE, TYPE, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_qda_enum(ARRAY_TYPE, TYPE, NAME, VALUE, PRINTER=printer) \ begin \ int __tmp_max = $right(VALUE) + 1; \ PRINTER.print_array_header(NAME, \ __tmp_max, \ {`"ARRAY_TYPE``(`", `"TYPE`", ")"}); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ int __tmp_begin_elements, __tmp_end_elements; \ __tmp_begin_elements = PRINTER.get_begin_elements(); \ __tmp_end_elements = PRINTER.get_end_elements(); \ /* Fast Bypass */ \ if (__tmp_begin_elements == -1 || __tmp_end_elements == -1) begin \ foreach (VALUE[__tmp_index]) begin \ `uvm_print_named_enum(TYPE, \ $sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER) \ end \ end \ else begin \ int __tmp_curr; \ foreach(VALUE[__tmp_index]) begin \ if (__tmp_curr < __tmp_begin_elements) begin \ `uvm_print_named_enum(TYPE, \ $sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER) \ end \ else \ break; \ __tmp_curr++; \ end \ if (__tmp_curr < __tmp_max ) begin \ if ((__tmp_max - __tmp_end_elements) > __tmp_curr) \ __tmp_curr = __tmp_max - __tmp_end_elements; \ if (__tmp_curr < __tmp_begin_elements) \ __tmp_curr = __tmp_begin_elements; \ else \ PRINTER.print_array_range(__tmp_begin_elements, __tmp_curr-1); \ while (__tmp_curr < __tmp_max) begin \ `uvm_print_named_enum(TYPE, \ $sformatf("[%0d]", __tmp_curr), \ VALUE[__tmp_curr], \ PRINTER) \ __tmp_curr++; \ end \ end \ end \ end \ PRINTER.print_array_footer(__tmp_max); \ end `define uvm_print_array_enum(TYPE, VALUE, PRINTER=printer) \ `uvm_print_named_qda_enum(da, `"VALUE`", TYPE, VALUE, PRINTER) `define uvm_print_named_array_enum(TYPE, NAME, VALUE, PRINTER=printer) \ `uvm_print_named_qda_enum(da, TYPE, NAME, VALUE, PRINTER) `define uvm_print_sarray_enum(TYPE, VALUE, PRINTER=printer) \ `uvm_print_named_qda_enum(sa, TYPE, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_sarray_enum(TYPE, NAME, VALUE, PRINTER=printer) \ `uvm_print_named_qda_enum(sa, TYPE, NAME, VALUE, PRINTER) `define uvm_print_queue_enum(TYPE, VALUE, PRINTER=printer) \ `uvm_print_named_qda_enum(queue, TYPE, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_queue_enum(TYPE, NAME, VALUE, PRINTER=printer) \ `uvm_print_named_qda_enum(queue, TYPE, NAME, VALUE, PRINTER) `define uvm_print_qda_object(ARRAY_TYPE, VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ `uvm_print_named_qda_object(ARRAY_TYPE, `"VALUE`", VALUE, RECURSION_POLICY, PRINTER) `define uvm_print_named_qda_object(ARRAY_TYPE, NAME, VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ begin \ int __tmp_max = $right(VALUE) + 1; \ PRINTER.print_array_header(NAME, \ __tmp_max, \ `"ARRAY_TYPE``(object)`"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ uvm_recursion_policy_enum __tmp_recursion_policy; \ int __tmp_begin_elements, __tmp_end_elements; \ __tmp_begin_elements = PRINTER.get_begin_elements(); \ __tmp_end_elements = PRINTER.get_end_elements(); \ __tmp_recursion_policy = PRINTER.get_recursion_policy(); \ if ((RECURSION_POLICY != UVM_DEFAULT_POLICY) && \ (__tmp_recursion_policy != RECURSION_POLICY)) \ PRINTER.set_recursion_policy(RECURSION_POLICY); \ /* Fast Bypass */ \ if (__tmp_begin_elements == -1 || __tmp_end_elements == -1) begin \ foreach (VALUE[__tmp_index]) begin \ `m_uvm_print_named_object($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER) \ end \ end \ else begin \ int __tmp_curr; \ foreach(VALUE[__tmp_index]) begin \ if (__tmp_curr < __tmp_begin_elements) begin \ `m_uvm_print_named_object($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER) \ end \ else \ break; \ __tmp_curr++; \ end \ if (__tmp_curr < __tmp_max ) begin \ if ((__tmp_max - __tmp_end_elements) > __tmp_curr) \ __tmp_curr = __tmp_max - __tmp_end_elements; \ if (__tmp_curr < __tmp_begin_elements) \ __tmp_curr = __tmp_begin_elements; \ else \ PRINTER.print_array_range(__tmp_begin_elements, __tmp_curr-1); \ while (__tmp_curr < __tmp_max) begin \ `m_uvm_print_named_object($sformatf("[%0d]", __tmp_curr), \ VALUE[__tmp_curr], \ PRINTER) \ __tmp_curr++; \ end \ end \ end \ if ((RECURSION_POLICY != UVM_DEFAULT_POLICY) && \ (__tmp_recursion_policy != RECURSION_POLICY)) \ PRINTER.set_recursion_policy(__tmp_recursion_policy); \ end \ PRINTER.print_array_footer(__tmp_max); \ end `define uvm_print_array_object(VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ `uvm_print_named_qda_object(da, `"VALUE`", VALUE, RECURSION_POLICY, PRINTER) `define uvm_print_named_array_object(NAME, VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ `uvm_print_named_qda_object(da, NAME, VALUE, RECURSION_POLICY, PRINTER) `define uvm_print_sarray_object(VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ `uvm_print_named_qda_object(sa, `"VALUE`", VALUE, RECURSION_POLICY, PRINTER) `define uvm_print_named_sarray_object(NAME, VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ `uvm_print_named_qda_object(sa, NAME, VALUE, RECURSION_POLICY, PRINTER) `define uvm_print_queue_object(VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ `uvm_print_named_qda_object(queue, `"VALUE`", VALUE, RECURSION_POLICY, PRINTER) `define uvm_print_named_queue_object(NAME, VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ `uvm_print_named_qda_object(queue, NAME, VALUE, RECURSION_POLICY, PRINTER) `define uvm_print_qda_string(ARRAY_TYPE, VALUE, PRINTER=printer) \ `uvm_print_named_qda_string(ARRAY_TYPE, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_qda_string(ARRAY_TYPE, NAME, VALUE, PRINTER=printer) \ begin \ int __tmp_max = $right(VALUE) + 1; \ PRINTER.print_array_header(NAME, \ __tmp_max, \ `"ARRAY_TYPE``(string)`"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ int __tmp_begin_elements, __tmp_end_elements; \ __tmp_begin_elements = PRINTER.get_begin_elements(); \ __tmp_end_elements = PRINTER.get_end_elements(); \ /* Fast Bypass */ \ if (__tmp_begin_elements == -1 || __tmp_end_elements == -1) begin \ foreach (VALUE[__tmp_index]) begin \ `uvm_print_named_string($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER) \ end \ end \ else begin \ int __tmp_curr; \ foreach(VALUE[__tmp_index]) begin \ if (__tmp_curr < __tmp_begin_elements) begin \ `uvm_print_named_string($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER) \ end \ else \ break; \ __tmp_curr++; \ end \ if (__tmp_curr < __tmp_max ) begin \ if ((__tmp_max - __tmp_end_elements) > __tmp_curr) \ __tmp_curr = __tmp_max - __tmp_end_elements; \ if (__tmp_curr < __tmp_begin_elements) \ __tmp_curr = __tmp_begin_elements; \ else \ PRINTER.print_array_range(__tmp_begin_elements, __tmp_curr-1); \ while (__tmp_curr < __tmp_max) begin \ `uvm_print_named_string($sformatf("[%0d]", __tmp_curr), \ VALUE[__tmp_curr], \ PRINTER) \ __tmp_curr++; \ end \ end \ end \ end \ PRINTER.print_array_footer(__tmp_max); \ end `define uvm_print_array_string(VALUE, PRINTER=printer) \ `uvm_print_named_qda_string(da, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_array_string(NAME, VALUE, PRINTER=printer) \ `uvm_print_named_qda_string(da, NAME, VALUE, PRINTER) `define uvm_print_sarray_string(VALUE, PRINTER=printer) \ `uvm_print_named_qda_string(sa, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_sarray_string(NAME, VALUE, PRINTER=printer) \ `uvm_print_named_qda_string(sa, NAME, VALUE, PRINTER) `define uvm_print_queue_string(VALUE, PRINTER=printer) \ `uvm_print_named_qda_string(queue, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_queue_string(NAME, VALUE, PRINTER=printer) \ `uvm_print_named_qda_string(queue, NAME, VALUE, PRINTER) `define uvm_print_aa_int_string(VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ `uvm_print_named_aa_int_string(`"VALUE`", VALUE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_named_aa_int_string(NAME, VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ begin \ PRINTER.print_array_header(NAME, \ VALUE.num(), \ `"aa(``VALUE_TYPE``,string)`"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ foreach(VALUE[__tmp_index]) \ `uvm_print_named_int($sformatf("[%s]", __tmp_index), \ VALUE[__tmp_index], \ $bits(VALUE[__tmp_index]), \ RADIX, \ VALUE_TYPE, \ PRINTER ) \ end \ PRINTER.print_array_footer(VALUE.num()); \ end `define uvm_print_aa_object_string(VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ `uvm_print_named_aa_object_string(`"VALUE`", VALUE, RECURSION_POLICY, PRINTER) `define uvm_print_named_aa_object_string(NAME, VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ begin \ PRINTER.print_array_header(NAME, \ VALUE.num(), \ "aa(object,string)"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ uvm_recursion_policy_enum __tmp_recursion_policy; \ __tmp_recursion_policy = PRINTER.get_recursion_policy(); \ if ((RECURSION_POLICY != UVM_DEFAULT_POLICY) && \ (__tmp_recursion_policy != RECURSION_POLICY)) \ PRINTER.set_recursion_policy(RECURSION_POLICY); \ foreach(VALUE[__tmp_index]) \ `m_uvm_print_named_object($sformatf("[%s]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER ) \ if ((RECURSION_POLICY != UVM_DEFAULT_POLICY) && \ (__tmp_recursion_policy != RECURSION_POLICY)) \ PRINTER.set_recursion_policy(__tmp_recursion_policy); \ end \ PRINTER.print_array_footer(VALUE.num()); \ end `define uvm_print_aa_string_string(VALUE, PRINTER=printer) \ `uvm_print_named_aa_string_string(`"VALUE`", VALUE, PRINTER) `define uvm_print_named_aa_string_string(NAME, VALUE, PRINTER=printer) \ begin \ PRINTER.print_array_header(NAME, \ VALUE.num(), \ "aa(string,string)"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ foreach(VALUE[__tmp_index]) \ `uvm_print_named_string($sformatf("[%s]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER ) \ end \ PRINTER.print_array_footer(VALUE.num()); \ end `define uvm_print_aa_int_int(VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=int, INDEX_TYPE=int, PRINTER=printer) \ `uvm_print_named_aa_int_int(`"VALUE`", VALUE, RADIX, VALUE_TYPE, INDEX_TYPE, PRINTER) `define uvm_print_named_aa_int_int(NAME, VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=int, INDEX_TYPE=int, PRINTER=printer) \ begin \ PRINTER.print_array_header(NAME, \ VALUE.num(), \ `"aa(``VALUE_TYPE``,``INDEX_TYPE``)`"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ foreach(VALUE[__tmp_index]) \ `uvm_print_named_int($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ $bits(VALUE[__tmp_index]), \ RADIX, \ VALUE_TYPE, \ PRINTER ) \ end \ PRINTER.print_array_footer(VALUE.num()); \ end `define uvm_print_aa_object_int(VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, INDEX_TYPE=int, PRINTER=printer) \ `uvm_print_named_aa_object_int(`"VALUE`", VALUE, RECURSION_POLICY, INDEX_TYPE, PRINTER) `define uvm_print_named_aa_object_int(NAME, VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, INDEX_TYPE=int, PRINTER=printer) \ begin \ PRINTER.print_array_header(NAME, \ VALUE.num(), \ `"aa(object,``INDEX_TYPE``)`"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ uvm_recursion_policy_enum __tmp_recursion_policy; \ __tmp_recursion_policy = PRINTER.get_recursion_policy(); \ if ((RECURSION_POLICY != UVM_DEFAULT_POLICY) && \ (__tmp_recursion_policy != RECURSION_POLICY)) \ PRINTER.set_recursion_policy(RECURSION_POLICY); \ foreach(VALUE[__tmp_index]) \ `m_uvm_print_named_object($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER ) \ if ((RECURSION_POLICY != UVM_DEFAULT_POLICY) && \ (__tmp_recursion_policy != RECURSION_POLICY)) \ PRINTER.set_recursion_policy(__tmp_recursion_policy); \ end \ PRINTER.print_array_footer(VALUE.num()); \ end `define uvm_print_aa_string_int(VALUE, INDEX_TYPE=int, PRINTER=printer) \ `uvm_print_named_aa_string_int(`"VALUE`", VALUE, INDEX_TYPE, PRINTER) `define uvm_print_named_aa_string_int(NAME, VALUE, INDEX_TYPE=int, PRINTER=printer) \ begin \ PRINTER.print_array_header(NAME, \ VALUE.num(), \ `"aa(string,``INDEX_TYPE``)`"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ foreach(VALUE[__tmp_index]) \ `uvm_print_named_string($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER ) \ end \ PRINTER.print_array_footer(VALUE.num()); \ end `define uvm_print_aa_int_enum(ENUM_TYPE, VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=int, PRINTER=printer) \ `uvm_print_named_aa_int_enum(`"VALUE`", ENUM_TYPE, VALUE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_named_aa_int_enum(NAME, ENUM_TYPE, VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=int, PRINTER=printer) \ begin \ PRINTER.print_array_header(NAME, \ VALUE.num(), \ `"aa(``VALUE_TYPE``,``ENUM_TYPE``)`"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ foreach(VALUE[__tmp_index]) \ `uvm_print_named_int((__tmp_index.name() == "") ? $sformatf("[%s'(%0d)]", `"ENUM_TYPE`",__tmp_index) \ : $sformatf("[%s]", __tmp_index.name()), \ VALUE[__tmp_index], \ $bits(VALUE[__tmp_index]), \ RADIX, \ VALUE_TYPE, \ PRINTER ) \ end \ PRINTER.print_array_footer(VALUE.num()); \ end `define uvm_print_int3(F, R, P) \ `uvm_print_int(F, $bits(F), R, , P) `define uvm_print_int4(F, R, NM, P) \ `uvm_print_named_int(NM, F, $bits(F), R, , P) `define uvm_print_object2(F, P) \ `uvm_print_object(F, ,P) `define uvm_print_string2(F, P) \ `uvm_print_string(F, P) `define uvm_print_array_int3(F, R, P) \ `uvm_print_named_qda_int(da, `"F`", F, R, ,P) `define uvm_print_sarray_int3(F, R, P) \ `uvm_print_named_qda_int(sa, `"F`", F, R, ,P) `define uvm_print_qda_int4(F, R, P, T) \ `uvm_print_named_qda_int(T, `"F`", F, R, ,P) `define uvm_print_queue_int3(F, R, P) \ `uvm_print_named_qda_int(queue, `"F`", F, R, ,P) `define uvm_print_array_object3(F, P, FLAG) \ `uvm_print_array_object(F, ,P) `define uvm_print_sarray_object3(F, P,FLAG) \ `uvm_print_sarray_object(F, ,P) `define uvm_print_object_qda4(F, P, T, FLAG) \ `uvm_print_named_qda_object(T, `"F`", F, ,P) `define uvm_print_object_queue3(F, P, FLAG) \ `uvm_print_queue_object(F, ,P) `define uvm_print_array_string2(F, P) \ `uvm_print_array_string(F, P) `define uvm_print_sarray_string2(F, P) \ `uvm_print_sarray_string(F, P) `define uvm_print_string_qda3(F, P, T) \ `uvm_print_named_qda_string(T, `"F`", F, P) `define uvm_print_string_queue2(F, P) \ `uvm_print_queue_string(F, P) `define uvm_print_aa_string_int3(F, R, P) \ `uvm_print_aa_int_string(F, R, ,P) `define uvm_print_aa_string_object3(F, P, FLAG) \ `uvm_print_aa_object_string(F, ,P) `define uvm_print_aa_string_string2(F, P) \ `uvm_print_aa_string_string(F, P) `define uvm_print_aa_int_object3(F, P, FLAG) \ `uvm_print_aa_object_int(F, ,P) `define uvm_print_aa_int_key4(KEY, F, R, P) \ `uvm_print_aa_int_int(F, R, ,KEY, P) `define UVM_COMPARER_DEFINES_SVH `define m_uvm_compare_threshold_begin(COMPARER) \ if ((!COMPARER.get_threshold() || \ (COMPARER.get_result() < COMPARER.get_threshold()))) begin \ `define m_uvm_compare_threshold_end \ end `define m_uvm_compare_begin(LVALUE, RVALUE, COMPARER=comparer) \ `m_uvm_compare_threshold_begin(COMPARER) \ if ((LVALUE) !== (RVALUE)) begin \ `define m_uvm_compare_end \ end \ `m_uvm_compare_threshold_end `define uvm_compare_int(LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `uvm_compare_named_int(`"LVALUE`", LVALUE, RVALUE, RADIX, COMPARER) `define uvm_compare_named_int(NAME, LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ if ($bits(LVALUE) <= 64) \ void'(COMPARER.compare_field_int(NAME , LVALUE, RVALUE, $bits(LVALUE), RADIX)); \ else \ void'(COMPARER.compare_field(NAME , LVALUE, RVALUE, $bits(LVALUE), RADIX)); \ `m_uvm_compare_end `define uvm_compare_enum(LVALUE, RVALUE, TYPE, COMPARER=comparer) \ `uvm_compare_named_enum(`"LVALUE`", LVALUE, RVALUE, TYPE, COMPARER) `define uvm_compare_named_enum(NAME, LVALUE, RVALUE, TYPE, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ void'(COMPARER.compare_string(NAME , \ $sformatf("%s'(%s)", `"TYPE`", LVALUE.name()), \ $sformatf("%s'(%s)", `"TYPE`", RVALUE.name())) ); \ `m_uvm_compare_end `define uvm_compare_real(LVALUE, RVALUE, COMPARER=comparer) \ `uvm_compare_named_real(`"LVALUE`", LVALUE, RVALUE, COMPARER) `define uvm_compare_named_real(NAME, LVALUE, RVALUE, COMPARER=comparer) \ `m_uvm_compare_threshold_begin(COMPARER) \ if ((LVALUE) != (RVALUE)) begin \ void'(COMPARER.compare_field_real(NAME , LVALUE, RVALUE)); \ end \ `m_uvm_compare_threshold_end `define uvm_compare_object(LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `uvm_compare_named_object(`"LVALUE`", LVALUE, RVALUE, POLICY, COMPARER) `define uvm_compare_named_object(NAME, LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ uvm_recursion_policy_enum prev_rec__; \ prev_rec__ = COMPARER.get_recursion_policy(); \ if (POLICY != UVM_DEFAULT_POLICY) \ COMPARER.set_recursion_policy(POLICY); \ `m_uvm_compare_named_object(NAME, LVALUE, RVALUE, COMPARER) \ if (POLICY != UVM_DEFAULT_POLICY) \ COMPARER.set_recursion_policy(prev_rec__); \ `m_uvm_compare_end `define m_uvm_compare_named_object(NAME, LVALUE, RVALUE, COMPARER) \ if (COMPARER.get_recursion_policy() != UVM_REFERENCE) begin \ bit local_rv__; \ uvm_policy::recursion_state_e local_state__; \ local_state__ = COMPARER.object_compared(LVALUE, RVALUE, COMPARER.get_recursion_policy(), local_rv__); \ if ((local_state__ == uvm_policy::FINISHED) && \ !local_rv__) \ COMPARER.print_msg($sformatf("'%s' miscompared using saved return value", NAME)); \ else if (local_state__ == uvm_policy::NEVER) \ void'(COMPARER.compare_object(NAME, LVALUE, RVALUE)); \ /* else skip to avoid infinite loop */ \ end \ else begin \ void'(COMPARER.compare_object(NAME, LVALUE, RVALUE)); \ end `define uvm_compare_string(LVALUE, RVALUE, COMPARER=comparer) \ `uvm_compare_named_string(`"LVALUE`", LVALUE, RVALUE, COMPARER) `define uvm_compare_named_string(NAME, LVALUE, RVALUE, COMPARER=comparer) \ `m_uvm_compare_threshold_begin(COMPARER) \ if ((LVALUE) != (RVALUE)) begin \ void'(COMPARER.compare_string(NAME , LVALUE, RVALUE)); \ end \ `m_uvm_compare_threshold_end `define uvm_compare_sarray_int(LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `uvm_compare_named_sarray_int(`"LVALUE`", LVALUE, RVALUE, RADIX, COMPARER) `define uvm_compare_named_sarray_int(NAME, LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ foreach (LVALUE[i]) begin \ `uvm_compare_named_int($sformatf("%s[%0d]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ RADIX, \ COMPARER) \ end \ `m_uvm_compare_end `define uvm_compare_qda_int(LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `uvm_compare_named_qda_int(`"LVALUE`", LVALUE, RVALUE, RADIX, COMPARER) `define uvm_compare_named_qda_int(NAME, LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ `uvm_compare_named_int($sformatf("%s.size()", NAME), \ LVALUE.size(), \ RVALUE.size(), \ UVM_DEC, \ COMPARER) \ `uvm_compare_named_sarray_int(NAME, LVALUE, RVALUE, RADIX, COMPARER) \ `m_uvm_compare_end `define uvm_compare_sarray_real(LVALUE, RVALUE, COMPARER=comparer) \ `uvm_compare_named_sarray_real(`"LVALUE`", LVALUE, RVALUE,COMPARER) `define uvm_compare_named_sarray_real(NAME, LVALUE, RVALUE, COMPARER=comparer) \ `m_uvm_compare_threshold_begin(COMPARER) \ if ((LVALUE) != (RVALUE)) begin \ foreach (LVALUE[i]) begin \ `uvm_compare_named_real($sformatf("%s[%0d]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ COMPARER) \ end \ end \ `m_uvm_compare_threshold_end `define uvm_compare_qda_real(LVALUE, RVALUE, COMPARER=comparer) \ `uvm_compare_named_qda_real(`"LVALUE`", LVALUE, RVALUE, COMPARER) `define uvm_compare_named_qda_real(NAME, LVALUE, RVALUE, COMPARER=comparer) \ `m_uvm_compare_threshold_begin(COMPARER) \ `uvm_compare_named_real($sformatf("%s.size()", NAME), \ LVALUE.size(), \ RVALUE.size(), \ COMPARER) \ `uvm_compare_named_sarray_real(NAME, LVALUE, RVALUE, COMPARER) \ `m_uvm_compare_threshold_end `define uvm_compare_sarray_enum(LVALUE, RVALUE, TYPE, COMPARER=comparer) \ `uvm_compare_named_sarray_enum(`"LVALUE`", LVALUE, RVALUE, TYPE, COMPARER) `define uvm_compare_named_sarray_enum(NAME, LVALUE, RVALUE, TYPE, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ foreach (LVALUE[i]) begin \ `uvm_compare_named_enum($sformatf("%s[%0d]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ TYPE, \ COMPARER) \ end \ `m_uvm_compare_end `define uvm_compare_qda_enum(LVALUE, RVALUE, TYPE, COMPARER=comparer) \ `uvm_compare_named_qda_enum(`"LVALUE`", LVALUE, RVALUE, TYPE, COMPARER) `define uvm_compare_named_qda_enum(NAME, LVALUE, RVALUE, TYPE, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ `uvm_compare_named_int($sformatf("%s.size()", NAME), \ LVALUE.size(), \ RVALUE.size(), \ UVM_DEC, \ COMPARER) \ `uvm_compare_named_sarray_enum(NAME, LVALUE, RVALUE, TYPE, COMPARER) \ `m_uvm_compare_end `define uvm_compare_sarray_object(LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `uvm_compare_named_sarray_object(`"LVALUE`", LVALUE, RVALUE, POLICY, COMPARER) `define uvm_compare_named_sarray_object(NAME, LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ uvm_recursion_policy_enum prev_rec__; \ prev_rec__ = COMPARER.get_recursion_policy(); \ if (POLICY != UVM_DEFAULT_POLICY) \ COMPARER.set_recursion_policy(POLICY); \ foreach (LVALUE[i]) begin \ `m_uvm_compare_named_object($sformatf("%s[%0d]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ COMPARER) \ end \ if (POLICY != UVM_DEFAULT_POLICY) \ COMPARER.set_recursion_policy(prev_rec__); \ `m_uvm_compare_end `define uvm_compare_qda_object(LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `uvm_compare_named_qda_object(`"LVALUE`", LVALUE, RVALUE, POLICY, COMPARER) `define uvm_compare_named_qda_object(NAME, LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ `uvm_compare_named_int($sformatf("%s.size()", NAME), \ LVALUE.size(), \ RVALUE.size(), \ UVM_DEC, \ COMPARER) \ `uvm_compare_named_sarray_object(NAME, LVALUE, RVALUE, POLICY, COMPARER) \ `m_uvm_compare_end `define uvm_compare_sarray_string(LVALUE, RVALUE, COMPARER=comparer) \ `uvm_compare_named_sarray_string(`"LVALUE`", LVALUE, RVALUE, COMPARER) `define uvm_compare_named_sarray_string(NAME, LVALUE, RVALUE, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ foreach (LVALUE[i]) begin \ `uvm_compare_named_string($sformatf("%s[%0d]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ COMPARER) \ end \ `m_uvm_compare_end `define uvm_compare_qda_string(LVALUE, RVALUE, COMPARER=comparer) \ `uvm_compare_named_qda_string(`"LVALUE`", LVALUE, RVALUE, COMPARER) `define uvm_compare_named_qda_string(NAME, LVALUE, RVALUE, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ `uvm_compare_named_int($sformatf("%s.size()", NAME), \ LVALUE.size(), \ RVALUE.size(), \ UVM_DEC, \ COMPARER) \ `uvm_compare_named_sarray_string(NAME, LVALUE, RVALUE, COMPARER) \ `m_uvm_compare_end `define uvm_compare_aa_int_string(LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `uvm_compare_named_aa_int_string(`"LVALUE`", LVALUE, RVALUE, RADIX, COMPARER) `define uvm_compare_named_aa_int_string(NAME, LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ foreach(LVALUE[i]) begin \ if (!RVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%s' not in RHS", NAME, i)); \ end \ else begin \ `uvm_compare_named_int($sformatf("%s[%s]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ RADIX, \ COMPARER) \ end \ end \ foreach(RVALUE[i]) begin \ if(!LVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%s' not in LHS", NAME, i)); \ end \ end \ `m_uvm_compare_end `define uvm_compare_aa_object_string(LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `uvm_compare_named_aa_object_string(`"LVALUE`", LVALUE, RVALUE, POLICY, COMPARER) `define uvm_compare_named_aa_object_string(NAME, LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ uvm_recursion_policy_enum prev_rec__; \ prev_rec__ = COMPARER.get_recursion_policy(); \ if (POLICY != UVM_DEFAULT_POLICY) \ COMPARER.set_recursion_policy(POLICY); \ foreach(LVALUE[i]) begin \ if (!RVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%s' not in RHS", NAME, i)); \ end \ else begin \ `m_uvm_compare_named_object($sformatf("%s[%s]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ COMPARER) \ end \ end \ foreach(RVALUE[i]) begin \ if(!LVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%s' not in LHS", NAME, i)); \ end \ end \ if (POLICY != UVM_DEFAULT_POLICY) \ COMPARER.set_recursion_policy(prev_rec__); \ `m_uvm_compare_end `define uvm_compare_aa_string_string(LVALUE, RVALUE, COMPARER=comparer) \ `uvm_compare_named_aa_string_string(`"LVALUE`", LVALUE, RVALUE, COMPARER) `define uvm_compare_named_aa_string_string(NAME, LVALUE, RVALUE, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ foreach(LVALUE[i]) begin \ if (!RVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%s' not in RHS", NAME, i)); \ end \ else begin \ `uvm_compare_named_string($sformatf("%s[%s]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ COMPARER) \ end \ end \ foreach(RVALUE[i]) begin \ if(!LVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%s' not in LHS", NAME, i)); \ end \ end \ `m_uvm_compare_end `define uvm_compare_aa_int_int(LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `uvm_compare_named_aa_int_int(`"LVALUE`", LVALUE, RVALUE, RADIX, COMPARER) `define uvm_compare_named_aa_int_int(NAME, LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ foreach(LVALUE[i]) begin \ if (!RVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%0d' not in RHS", NAME, i)); \ end \ else begin \ `uvm_compare_named_int($sformatf("%s[%d]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ RADIX, \ COMPARER) \ end \ end \ foreach(RVALUE[i]) begin \ if(!LVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%0d' not in LHS", NAME, i)); \ end \ end \ `m_uvm_compare_end `define uvm_compare_aa_object_int(LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `uvm_compare_named_aa_object_int(`"LVALUE`", LVALUE, RVALUE, POLICY, COMPARER) `define uvm_compare_named_aa_object_int(NAME, LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ uvm_recursion_policy_enum prev_rec__; \ prev_rec__ = COMPARER.get_recursion_policy(); \ if (POLICY != UVM_DEFAULT_POLICY) \ COMPARER.set_recursion_policy(POLICY); \ foreach(LVALUE[i]) begin \ if (!RVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%0d' not in RHS", NAME, i)); \ end \ else begin \ `m_uvm_compare_named_object($sformatf("%s[%s]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ COMPARER) \ end \ end \ foreach(RVALUE[i]) begin \ if(!LVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%0d' not in LHS", NAME, i)); \ end \ end \ if (POLICY != UVM_DEFAULT_POLICY) \ COMPARER.set_recursion_policy(prev_rec__); \ `m_uvm_compare_end `define uvm_compare_aa_string_int(LVALUE, RVALUE, COMPARER=comparer) \ `uvm_compare_named_aa_string_int(`"LVALUE`", LVALUE, RVALUE, COMPARER) `define uvm_compare_named_aa_string_int(NAME, LVALUE, RVALUE, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ foreach(LVALUE[i]) begin \ if (!RVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%d' not in RHS", NAME, i)); \ end \ else begin \ `uvm_compare_named_string($sformatf("%s[%d]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ COMPARER) \ end \ end \ foreach(RVALUE[i]) begin \ if(!LVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%d' not in LHS", NAME, i)); \ end \ end \ `m_uvm_compare_end `define UVM_RECORDER_DEFINES_SVH `define uvm_record_attribute(TR_HANDLE,NAME,VALUE,RECORDER=recorder) \ RECORDER.record_generic(NAME, $sformatf("%p", VALUE)); `define uvm_record_int(NAME,VALUE,SIZE,RADIX = UVM_NORADIX,RECORDER=recorder) \ if (RECORDER != null && RECORDER.is_open()) begin \ if (RECORDER.use_record_attribute()) \ `uvm_record_attribute(RECORDER.get_record_attribute_handle(),NAME,VALUE,RECORDER) \ else \ if (SIZE > 64) \ RECORDER.record_field(NAME, VALUE, SIZE, RADIX); \ else \ RECORDER.record_field_int(NAME, VALUE, SIZE, RADIX); \ end `define uvm_record_string(NAME,VALUE,RECORDER=recorder) \ if (RECORDER != null && RECORDER.is_open()) begin \ if (RECORDER.use_record_attribute()) \ `uvm_record_attribute(RECORDER.get_record_attribute_handle(),NAME,VALUE,RECORDER) \ else \ RECORDER.record_string(NAME,VALUE); \ end `define uvm_record_time(NAME,VALUE,RECORDER=recorder) \ if (RECORDER != null && RECORDER.is_open()) begin \ if (RECORDER.use_record_attribute()) \ `uvm_record_attribute(RECORDER.get_record_attribute_handle(),NAME,VALUE,RECORDER) \ else \ RECORDER.record_time(NAME,VALUE); \ end `define uvm_record_real(NAME,VALUE,RECORDER=recorder) \ if (RECORDER != null && RECORDER.is_open()) begin \ if (RECORDER.use_record_attribute()) \ `uvm_record_attribute(RECORDER.get_record_attribute_handle(),NAME,VALUE,RECORDER) \ else \ RECORDER.record_field_real(NAME,VALUE); \ end `define uvm_record_field(NAME,VALUE,RECORDER=recorder) \ if (RECORDER != null && RECORDER.is_open()) begin \ if (RECORDER.use_record_attribute()) begin \ `uvm_record_attribute(RECORDER.get_record_attribute_handle(),NAME,VALUE,RECORDER) \ end \ else \ RECORDER.record_generic(NAME, $sformatf("%p", VALUE)); \ end `define uvm_record_enum(NAME,VALUE,TYPE,RECORDER=recorder) \ if (RECORDER != null && RECORDER.is_open()) begin \ if (RECORDER.use_record_attribute()) begin \ `uvm_record_attribute(RECORDER.get_record_attribute_handle(),NAME,VALUE,RECORDER) \ end \ else begin \ if (VALUE.name() == "") \ RECORDER.record_generic(NAME, $sformatf("%0d", VALUE), `"TYPE`"); \ else \ RECORDER.record_generic(NAME, VALUE.name(), `"TYPE`"); \ end \ end `define uvm_record_object(VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, RECORDER=recorder) \ `uvm_record_named_object(`"VALUE`", VALUE, RECURSION_POLICY, RECORDER) `define uvm_record_named_object(NAME, VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, RECORDER=recorder) \ if ((RECURSION_POLICY != UVM_DEFAULT_POLICY) && \ (RECURSION_POLICY != RECORDER.get_recursion_policy())) begin \ uvm_recursion_policy_enum __saved_recursion_policy = RECORDER.get_recursion_policy(); \ RECORDER.set_recursion_policy(RECURSION_POLICY); \ `m_uvm_record_named_object(NAME, VALUE, RECORDER) \ RECORDER.set_recursion_policy(__saved_recursion_policy); \ end \ else begin \ `m_uvm_record_named_object(NAME, VALUE, RECORDER) \ end `define m_uvm_record_named_object(NAME, VALUE, RECORDER) \ if (RECORDER.object_recorded(VALUE, RECORDER.get_recursion_policy()) != uvm_policy::NEVER) begin \ uvm_recursion_policy_enum __saved_recursion_policy = RECORDER.get_recursion_policy(); \ RECORDER.set_recursion_policy(UVM_REFERENCE); \ RECORDER.record_object(NAME, VALUE); \ RECORDER.set_recursion_policy(__saved_recursion_policy); \ end \ else begin \ RECORDER.record_object(NAME, VALUE); \ end `define uvm_record_qda_int(ARG, RADIX,RECORDER=recorder) \ begin \ int sz__ = $size(ARG); \ if(sz__ == 0) begin \ `uvm_record_int(`"ARG`", 0, 32, UVM_DEC,RECORDER) \ end \ else if(sz__ < 10) begin \ foreach(ARG[i]) begin \ string nm__ = $sformatf("%s[%0d]", `"ARG`", i); \ `uvm_record_int(nm__, ARG[i], $bits(ARG[i]), RADIX, RECORDER) \ end \ end \ else begin \ for(int i=0; i<5; ++i) begin \ string nm__ = $sformatf("%s[%0d]", `"ARG`", i); \ `uvm_record_int(nm__, ARG[i], $bits(ARG[i]), RADIX, RECORDER) \ end \ for(int i=sz__-5; i sz__) \ void'(VAR.pop_back()); \ for (int i=0; i tmp_size__) \ void'(VAR.pop_back()); \ for (int i = 0; i < tmp_size__; i++) \ `uvm_unpack_real(VAR[i], PACKER) \ end `define UVM_COPIER_DEFINES_SVH `define uvm_copy_object(LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COPIER=copier) \ if (LVALUE != RVALUE) begin \ if ((RVALUE == null) || \ (POLICY == UVM_REFERENCE) || \ ((POLICY == UVM_DEFAULT_POLICY) && \ (COPIER.get_recursion_policy() == UVM_REFERENCE))) begin \ LVALUE = RVALUE; \ end \ else begin \ uvm_object lvalue_ref__; \ if (!COPIER.get_first_copy(RVALUE,lvalue_ref__) || !$cast(LVALUE,lvalue_ref__)) begin \ uvm_recursion_policy_enum prev_pol__ = COPIER.get_recursion_policy(); \ uvm_recursion_policy_enum curr_pol__; \ if (POLICY != UVM_DEFAULT_POLICY) \ COPIER.set_recursion_policy(POLICY); \ curr_pol__ = COPIER.get_recursion_policy(); \ if (LVALUE == null) begin \ if (($cast(LVALUE, RVALUE.create(RVALUE.get_name())) == 0) || \ (LVALUE == null)) begin \ `uvm_fatal("UVM/COPY/NULL_CREATE", \ {"Could not create '", RVALUE.get_full_name(), \ "' of type '", RVALUE.get_type_name(), \ "', into '", `"LVALUE`", "'."}) \ end \ else begin \ COPIER.copy_object(LVALUE, RVALUE); \ end \ end \ else begin \ if (COPIER.object_copied(LVALUE, RVALUE, curr_pol__) == uvm_policy::STARTED) begin \ `uvm_warning("UVM/COPY/LOOP", \ {"Loop detected in copy operation (LHS:'", \ LVALUE.get_full_name(), \ "', RHS:'", \ RVALUE.get_full_name(), \ "')"}) \ end \ else begin \ COPIER.copy_object(LVALUE, RVALUE); \ end \ end \ if (POLICY != UVM_DEFAULT_POLICY) \ COPIER.set_recursion_policy(prev_pol__); \ end \ end \ end `define uvm_copy_aa_object(LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COPIER=copier) \ if ((POLICY == UVM_REFERENCE) || !RVALUE.size()) \ LVALUE = RVALUE; \ else begin \ LVALUE.delete(); \ foreach(RVALUE[i]) \ `uvm_copy_object(LVALUE[i], RVALUE[i], POLICY, COPIER) \ end `define uvm_copier_get_function(FUNCTION) \ function int get_``FUNCTION``_copy(uvm_object rhs, ref uvm_object lhs); \ if (m_recur_states.exists(rhs)) \ return m_recur_states[rhs].FUNCTION(lhs); \ return 0; \ endfunction : get_``FUNCTION``_copy `define UVM_OBJECT_DEFINES_SVH `define UVM_FIELD_FLAG_SIZE UVM_FIELD_FLAG_RESERVED_BITS `define uvm_field_utils_begin(T) \ function void do_execute_op( uvm_field_op op ); \ super.do_execute_op(op); \ __m_uvm_execute_field_op(op); \ endfunction : do_execute_op \ local function void __m_uvm_execute_field_op( uvm_field_op __local_op__ ); \ uvm_field_flag_t local_op_type__; /* Used to avoid re-querying */ \ T local_rhs__; /* Used for $casting copy and compare */ \ uvm_resource_base local_rsrc__; /* Used for UVM_SET ops */ \ string local_rsrc_name__; \ uvm_object local_obj__; /* Used when trying to read uvm_object resources */ \ bit local_success__; /* Used when trying to read resources */ \ typedef T __local_type__; /* Used for referring to type T in field macros */ \ int local_size__; /* Used when unpacking size values */ \ /* All possible policy classes */ \ /* Using the same name as the do_* methods, allows macro reuse */ \ uvm_printer __local_printer__; \ uvm_comparer __local_comparer__; \ uvm_recorder __local_recorder__; \ uvm_packer __local_packer__; \ uvm_copier __local_copier__; \ uvm_queue#(uvm_acs_name_struct) __local_field_names__; \ void'($cast(local_rhs__, __local_op__.get_rhs())); \ if (($cast(local_rsrc__, __local_op__.get_rhs())) && \ (local_rsrc__ != null)) \ local_rsrc_name__ = local_rsrc__.get_name(); \ local_op_type__ = __local_op__.get_op_type(); \ case (local_op_type__) \ UVM_PRINT: begin \ $cast(__local_printer__, __local_op__.get_policy()); \ end \ UVM_COMPARE: begin \ if (local_rhs__ == null) return; \ $cast(__local_comparer__, __local_op__.get_policy()); \ end \ UVM_RECORD: begin \ $cast(__local_recorder__, __local_op__.get_policy()); \ end \ UVM_PACK, UVM_UNPACK: begin \ $cast(__local_packer__, __local_op__.get_policy()); \ end \ UVM_COPY: begin \ if (local_rhs__ == null) return; \ $cast(__local_copier__, __local_op__.get_policy()); \ end \ UVM_SET: begin \ if (local_rsrc__ == null) return; \ end \ UVM_CHECK_FIELDS: begin \ $cast(__local_field_names__, __local_op__.get_rhs()); \ end \ default: \ return; /* unknown op, just return */ \ endcase \ `define uvm_field_utils_end \ endfunction : __m_uvm_execute_field_op `define uvm_object_utils(T) \ `m_uvm_object_registry_internal(T,T) \ `m_uvm_object_create_func(T) \ `uvm_type_name_decl(`"T`") `define uvm_object_param_utils(T) \ `m_uvm_object_registry_param(T) \ `m_uvm_object_create_func(T) `define uvm_object_utils_begin(T) \ `uvm_object_utils(T) \ `uvm_field_utils_begin(T) `define uvm_object_param_utils_begin(T) \ `uvm_object_param_utils(T) \ `uvm_field_utils_begin(T) `define uvm_object_abstract_utils(T) \ `m_uvm_object_abstract_registry_internal(T,T) \ `uvm_type_name_decl(`"T`") `define uvm_object_abstract_param_utils(T) \ `m_uvm_object_abstract_registry_param(T) `define uvm_object_abstract_utils_begin(T) \ `uvm_object_abstract_utils(T) \ `uvm_field_utils_begin(T) `define uvm_object_abstract_param_utils_begin(T) \ `uvm_object_abstract_param_utils(T) \ `uvm_field_utils_begin(T) `define uvm_object_utils_end \ `uvm_field_utils_end `define uvm_component_utils(T) \ `m_uvm_component_registry_internal(T,T) \ `uvm_type_name_decl(`"T`") \ `define uvm_component_param_utils(T) \ `m_uvm_component_registry_param(T) \ `define uvm_component_utils_begin(T) \ `uvm_component_utils(T) \ `uvm_field_utils_begin(T) `define uvm_component_param_utils_begin(T) \ `uvm_component_param_utils(T) \ `uvm_field_utils_begin(T) `define uvm_component_abstract_utils(T) \ `m_uvm_component_abstract_registry_internal(T,T) \ `uvm_type_name_decl(`"T`") \ `define uvm_component_abstract_param_utils(T) \ `m_uvm_component_abstract_registry_param(T) \ `define uvm_component_abstract_utils_begin(T) \ `uvm_component_abstract_utils(T) \ `uvm_field_utils_begin(T) `define uvm_component_abstract_param_utils_begin(T) \ `uvm_component_abstract_param_utils(T) \ `uvm_field_utils_begin(T) `define uvm_component_utils_end \ `uvm_field_utils_end `define uvm_object_registry(T,S) \ typedef uvm_object_registry#(T,S) type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define uvm_component_registry(T,S) \ typedef uvm_component_registry #(T,S) type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define uvm_declare_type_alias(TYPE,NAME,SFX=) \ static bit m__alias_declared``SFX = TYPE::type_id::set_type_alias(NAME); `define uvm_new_func \ function new (string name, uvm_component parent); \ super.new(name, parent); \ endfunction `define m_uvm_object_create_func(T) \ function uvm_object create (string name=""); \ T tmp; \ if (name=="") tmp = new(); \ else tmp = new(name); \ return tmp; \ endfunction `define uvm_type_name_decl(TNAME_STRING) \ static function string type_name(); \ return TNAME_STRING; \ endfunction : type_name \ virtual function string get_type_name(); \ return TNAME_STRING; \ endfunction : get_type_name `define m_uvm_object_registry_internal(T,S) \ typedef uvm_object_registry#(T,`"S`") type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define m_uvm_object_registry_param(T) \ typedef uvm_object_registry #(T) type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define m_uvm_object_abstract_registry_internal(T,S) \ typedef uvm_abstract_object_registry#(T,`"S`") type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define m_uvm_object_abstract_registry_param(T) \ typedef uvm_abstract_object_registry #(T) type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define m_uvm_component_registry_internal(T,S) \ typedef uvm_component_registry #(T,`"S`") type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define m_uvm_component_registry_param(T) \ typedef uvm_component_registry #(T) type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define m_uvm_component_abstract_registry_internal(T,S) \ typedef uvm_abstract_component_registry #(T,`"S`") type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define m_uvm_component_abstract_registry_param(T) \ typedef uvm_abstract_component_registry #(T) type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define m_uvm_field_radix(FLAG) uvm_radix_enum'((FLAG)&(UVM_RADIX)) `define m_uvm_field_recursion(FLAG) uvm_recursion_policy_enum'((FLAG)&(UVM_RECURSION)) `define m_warn_if_no_positive_ops(ARG,FLAG) \ begin \ static bit dont_warn_if_no_positive_ops ; \ if (!dont_warn_if_no_positive_ops && !((FLAG)&UVM_FLAGS_ON) && ((FLAG)&(~(UVM_COPY|UVM_COMPARE|UVM_PRINT|UVM_RECORD|UVM_PACK|UVM_UNPACK)))) begin \ string behavior; \ `ifdef UVM_LEGACY_FIELD_MACRO_SEMANTICS behavior = "As UVM_LEGACY_FIELD_MACRO_SEMANTICS is set, we will treat this as if UVM_ALL_ON had been bitwise-or'd with FLAG. This is not the behavior specified by IEEE 1800.2-2020."; \ `else behavior = "Previous Accellera UVM libraries treated this as if UVM_ALL_ON had been bitwise-or'd with this FLAG, but per IEEE 1800.2-2020, we will treat it as a NO-OP (see UVM Mantis 7187)"; \ `endif \ `uvm_warning("UVM/FIELDS/NO_FLAG",{"Field macro for ARG uses FLAG without or'ing any explicit UVM_xxx actions. ",behavior}) \ dont_warn_if_no_positive_ops = 1; \ end \ end `define m_uvm_field_begin(ARG, FLAG, REGEX="") \ `m_warn_if_no_positive_ops(ARG,FLAG) \ begin \ case (local_op_type__) \ UVM_CHECK_FIELDS: \ if ( \ `ifndef UVM_LEGACY_FIELD_MACRO_SEMANTICS (((FLAG)&UVM_SET)) && `endif \ (!((FLAG)&UVM_NOSET)) \ ) begin \ __local_field_names__.push_back('{`"ARG`", REGEX}); \ end `define m_uvm_field_end(ARG) \ endcase \ end `define m_uvm_field_op_begin(OP, FLAG) \ UVM_``OP: \ if ( \ `ifndef UVM_LEGACY_FIELD_MACRO_SEMANTICS (((FLAG)&UVM_``OP)) && `endif \ (!((FLAG)&UVM_NO``OP)) \ ) begin `define m_uvm_field_op_end(OP) \ end `define m_uvm_compat_physical_abstract(FLAG) \ if ((__local_comparer__.physical&&((FLAG)&UVM_PHYSICAL)) || \ (__local_comparer__.abstract&&((FLAG)&UVM_ABSTRACT)) || \ (!((FLAG)&UVM_PHYSICAL) && !((FLAG)&UVM_ABSTRACT)) ) `define uvm_field_int(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_int(ARG, local_rhs__.ARG, `m_uvm_field_radix(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_int(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_int(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_int(`"ARG`", \ ARG, \ $bits(ARG), \ `m_uvm_field_radix(FLAG), \ __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_int(ARG, $bits(ARG), `m_uvm_field_radix(FLAG),,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_builtin_int_read(local_success__, \ local_rsrc__, \ ARG, \ this) \ /* TODO if(local_success__ && printing matches) */ \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_object(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ `uvm_copy_object(ARG, local_rhs__.ARG, `m_uvm_field_recursion(FLAG), __local_copier__) \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_object(ARG, local_rhs__.ARG, `m_uvm_field_recursion(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ if (`m_uvm_field_recursion(FLAG) != UVM_REFERENCE) \ `uvm_pack_object(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ if (`m_uvm_field_recursion(FLAG) != UVM_REFERENCE) \ `uvm_unpack_object(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_object(ARG, `m_uvm_field_recursion(FLAG), __local_recorder__); \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_object(ARG, `m_uvm_field_recursion(FLAG),__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_read(local_success__, \ local_rsrc__, \ uvm_object, \ local_obj__, \ this) \ if (local_success__) begin \ if (local_obj__ == null) begin \ ARG = null; \ end else if (!$cast(ARG, local_obj__) && uvm_config_db_options::is_tracing()) begin \ `uvm_info("CFGDB/OBJ_TYPE", $sformatf("Can't set field '%s' on '%s' with '%s' type", \ `"ARG`", \ this.get_full_name(), \ local_obj__.get_type_name()),UVM_LOW) \ end \ /* TODO if(local_success__ && printing matches) */ \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_string(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_string(ARG, local_rhs__.ARG, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_string(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_string(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_string(`"ARG`", ARG, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ __local_printer__.print_string(`"ARG`", ARG); \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_read(local_success__, \ local_rsrc__, \ string, \ ARG, \ this) \ /* TODO if(local_success__ && printing matches) */ \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_enum(T,ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_enum(ARG, local_rhs__.ARG, T, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_enum(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_enum(ARG, T, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_enum(`"ARG`", ARG, T, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ if (`m_uvm_field_radix(FLAG) inside {UVM_NORADIX, UVM_ENUM, UVM_STRING}) \ `uvm_print_enum(T, ARG,__local_printer__) \ else \ `uvm_print_int(ARG, $bits(ARG), `m_uvm_field_radix(FLAG),T,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_enum_read(local_success__, \ local_rsrc__, \ T, \ ARG, \ this) \ /* TODO if(local_success__ && printing matches) */ \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_real(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_real(ARG, local_rhs__.ARG, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_real(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_real(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_real(`"ARG`", ARG, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ __local_printer__.print_real(`"ARG`", ARG); \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_real_read(local_success__, \ local_rsrc__, \ ARG, \ this) \ /* TODO if(local_success__ && printing matches) */ \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_event(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `m_uvm_compare_begin(ARG, local_rhs__.ARG, __local_comparer__) \ __local_comparer__.print_msg({`"ARG`", " event miscompare"}); \ `m_uvm_compare_end \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ __local_printer__.print_generic(`"ARG`", "event", -1, ""); \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_sarray_int(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG,`"ARG[+]`") \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `m_uvm_compat_physical_abstract(FLAG) \ `uvm_compare_sarray_int(ARG, local_rhs__.ARG, `m_uvm_field_radix(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_sarray(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_sarray(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_int(ARG, `m_uvm_field_radix(FLAG), __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_sarray_int(ARG, \ `m_uvm_field_radix(FLAG),, \ __local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/SARRAY_SIZE", $sformatf("Static array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if ((local_index__ >= $size(ARG)) || (local_index__ < 0)) begin \ `uvm_warning("UVM/FIELDS/SARRAY_IDX", $sformatf("Index '%d' is not valid for static array '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ $size(ARG))) \ end \ else begin \ `uvm_resource_builtin_int_read(local_success__, \ local_rsrc__, \ ARG[local_index__], \ this) \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_sarray_object(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG, `"ARG[+]`") \ `m_uvm_field_op_begin(COPY,FLAG) \ foreach(ARG[i]) begin \ `uvm_copy_object(ARG[i], local_rhs__.ARG[i], `m_uvm_field_recursion(FLAG), __local_copier__) \ end \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `m_uvm_compat_physical_abstract(FLAG) \ `uvm_compare_sarray_object(ARG, local_rhs__.ARG, `m_uvm_field_recursion(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ if (`m_uvm_field_recursion(FLAG) != UVM_REFERENCE) \ foreach(ARG[i]) \ `uvm_pack_object(ARG[i], __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ if (`m_uvm_field_recursion(FLAG) != UVM_REFERENCE) \ foreach(ARG[i]) \ `uvm_unpack_object(ARG[i], __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_object(ARG, `m_uvm_field_recursion(FLAG), __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_sarray_object(ARG, `m_uvm_field_recursion(FLAG), __local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/SARRAY_SIZE", $sformatf("Static array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if ((local_index__ >= $size(ARG)) || (local_index__ < 0)) begin \ `uvm_warning("UVM/FIELDS/SARRAY_IDX", $sformatf("Index '%d' is not valid for static array '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ $size(ARG))) \ end \ else begin \ `uvm_resource_read(local_success__, \ local_rsrc__, \ uvm_object, \ local_obj__, \ this) \ if (local_success__) begin \ if (local_obj__ == null) begin \ ARG[local_index__] = null; \ end else if (!$cast(ARG[local_index__], local_obj__) && uvm_config_db_options::is_tracing()) begin \ `uvm_info("CFGDB/OBJ_TYPE", $sformatf("Can't set field '%s[%d]' on '%s' with '%s' type", \ `"ARG`", \ local_index__, \ this.get_full_name(), \ local_obj__.get_type_name()),UVM_LOW) \ end \ end \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_sarray_string(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG,`"ARG[+]`") \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `m_uvm_compat_physical_abstract(FLAG) \ `uvm_compare_sarray_string(ARG, local_rhs__.ARG, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ foreach(ARG[i]) \ `uvm_pack_string(ARG[i], __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ foreach(ARG[i]) \ `uvm_unpack_string(ARG[i], __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_string(ARG, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_sarray_string(ARG,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/SARRAY_SIZE", $sformatf("Static array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if ((local_index__ >= $size(ARG)) || (local_index__ < 0)) begin \ `uvm_warning("UVM/FIELDS/SARRAY_IDX", $sformatf("Index '%d' is not valid for static array '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ $size(ARG))) \ end \ else begin \ `uvm_resource_read(local_success__, \ local_rsrc__, \ string, \ ARG[local_index__], \ this) \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_sarray_enum(T,ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG,`"ARG[+]`") \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `m_uvm_compat_physical_abstract(FLAG) \ `uvm_compare_sarray_enum(ARG, local_rhs__.ARG, T, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ foreach (ARG[i]) \ `uvm_pack_enumN(ARG[i], $bits(T), __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ foreach (ARG[i]) \ `uvm_unpack_enumN(ARG[i], $bits(T), T, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_enum(ARG, T, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_sarray_enum(T, ARG ,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/SARRAY_SIZE", $sformatf("Static array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if ((local_index__ >= $size(ARG)) || (local_index__ < 0)) begin \ `uvm_warning("UVM/FIELDS/SARRAY_IDX", $sformatf("Index '%d' is not valid for static array '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ $size(ARG))) \ end \ else begin \ `uvm_resource_enum_read(local_success__, \ local_rsrc__, \ T, \ ARG[local_index__], \ this) \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define m_uvm_queue_resize(ARG, SZ) \ if (ARG.size() > SZ) \ ARG = ARG[0:SZ-1]; \ else \ while (ARG.size() < SZ) ARG.push_back(ARG[SZ]); `define m_uvm_da_resize(ARG, SZ) \ if (ARG.size() != SZ) ARG = new[SZ](ARG); `define m_uvm_field_qda_int(TYPE,ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG,`"ARG[+]`") \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `m_uvm_compat_physical_abstract(FLAG) \ `uvm_compare_qda_int(ARG, local_rhs__.ARG, `m_uvm_field_radix(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_``TYPE``(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_``TYPE``(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_int(ARG, `m_uvm_field_radix(FLAG), __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_qda_int(TYPE, ARG, `m_uvm_field_radix(FLAG),,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_builtin_int_read(local_success__, \ local_rsrc__, \ local_size__, \ this) \ if (local_success__) \ `m_uvm_``TYPE``_resize(ARG, local_size__) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if (local_index__ < 0) begin \ `uvm_warning("UVM/FIELDS/QDA_IDX", $sformatf("Index '%0d' is not valid for field '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ ARG.size() ) ) \ end \ else begin \ bit tmp_stream__[]; \ `uvm_resource_builtin_int_read(local_success__, \ local_rsrc__, \ { << bit { tmp_stream__ }}, \ this) \ if (local_success__) begin \ if (local_index__ >= ARG.size()) \ `m_uvm_``TYPE``_resize(ARG, local_index__ + 1) \ tmp_stream__ = new[$bits(ARG[local_index__])] (tmp_stream__); \ ARG[local_index__] = { << bit { tmp_stream__ }}; \ end \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_array_int(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_qda_int(da,ARG,FLAG) `define m_uvm_field_qda_object(TYPE,ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG,`"ARG[+]`") \ `m_uvm_field_op_begin(COPY,FLAG) \ if ((`m_uvm_field_recursion(FLAG) == UVM_REFERENCE) || !local_rhs__.ARG.size()) \ ARG = local_rhs__.ARG; \ else begin \ `m_uvm_``TYPE``_resize(ARG, local_rhs__.ARG.size()) \ foreach (ARG[i]) \ `uvm_copy_object(ARG[i], local_rhs__.ARG[i], `m_uvm_field_recursion(FLAG), __local_copier__) \ end \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `m_uvm_compat_physical_abstract(FLAG) \ `uvm_compare_qda_object(ARG, local_rhs__.ARG, `m_uvm_field_recursion(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ __local_packer__.pack_field_int(ARG.size(), 32); \ foreach (ARG[i]) \ `uvm_pack_object(ARG[i], __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ local_size__ = __local_packer__.unpack_field_int(32); \ `m_uvm_``TYPE``_resize(ARG, local_size__); \ foreach (ARG[i]) \ `uvm_unpack_object(ARG[i], __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_object(ARG, `m_uvm_field_recursion(FLAG), __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_qda_object(TYPE, ARG, `m_uvm_field_recursion(FLAG),__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_builtin_int_read(local_success__, \ local_rsrc__, \ local_size__, \ this) \ if (local_success__) \ `m_uvm_``TYPE``_resize(ARG, local_size__) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if (local_index__ < 0) begin \ `uvm_warning("UVM/FIELDS/QDA_IDX", $sformatf("Index '%0d' is not valid for field '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ ARG.size() ) ) \ end \ else begin \ `uvm_resource_read(local_success__, \ local_rsrc__, \ uvm_object, \ local_obj__, \ this) \ if (local_success__) begin \ if (local_index__ >= ARG.size()) \ `m_uvm_``TYPE``_resize(ARG, local_index__ + 1) \ if (local_obj__ == null) begin \ ARG[local_index__] = null; \ end else if (!$cast(ARG[local_index__], local_obj__) && uvm_config_db_options::is_tracing()) begin \ `uvm_info("CFGDB/QDA_OBJ_TYPE", \ $sformatf("Can't set field '%s[%0d]' on '%s' with '%s' type", \ `"ARG`", \ local_index__, \ this.get_full_name(), \ local_obj__.get_type_name()),UVM_LOW) \ end \ end \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_array_object(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_qda_object(da,ARG,FLAG) `define uvm_field_array_string(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_qda_string(da,ARG,FLAG) `define m_uvm_field_qda_string(TYPE,ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG,`"ARG[+]`") \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `m_uvm_compat_physical_abstract(FLAG) \ `uvm_compare_qda_string(ARG, local_rhs__.ARG, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ __local_packer__.pack_field_int(ARG.size(), 32); \ foreach (ARG[i]) \ `uvm_pack_string(ARG[i], __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ local_size__ = __local_packer__.unpack_field_int(32); \ `m_uvm_``TYPE``_resize(ARG, local_size__) \ foreach (ARG[i]) \ `uvm_unpack_string(ARG[i], __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_string(ARG, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_qda_string(TYPE, ARG,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_builtin_int_read(local_success__, \ local_rsrc__, \ local_size__, \ this) \ if (local_success__) \ `m_uvm_``TYPE``_resize(ARG, local_size__) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if (local_index__ < 0) begin \ `uvm_warning("UVM/FIELDS/QDA_IDX", $sformatf("Index '%0d' is not valid for field '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ ARG.size() ) ) \ end \ else begin \ string tmp_string__; \ `uvm_resource_read(local_success__, \ local_rsrc__, \ string, \ tmp_string__, \ this) \ if (local_success__) begin \ if (local_index__ >= ARG.size()) \ `m_uvm_``TYPE``_resize(ARG, local_index__ + 1) \ ARG[local_index__] = tmp_string__; \ end \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_array_enum(T,ARG,FLAG=UVM_DEFAULT) \ `m_field_qda_enum(da,T,ARG,FLAG) `define m_field_qda_enum(TYPE,T,ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG,`"ARG[+]`") \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `m_uvm_compat_physical_abstract(FLAG) \ `uvm_compare_qda_enum(ARG, local_rhs__.ARG, T, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ __local_packer__.pack_field_int(ARG.size(), 32); \ foreach (ARG[i]) \ `uvm_pack_enumN(ARG[i], $bits(T), __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ local_size__ = __local_packer__.unpack_field_int(32); \ `m_uvm_``TYPE``_resize(ARG, local_size__) \ foreach (ARG[i]) \ `uvm_unpack_enumN(ARG[i], $bits(T), T, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_enum(ARG, T, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_qda_enum(TYPE, T, ARG,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_builtin_int_read(local_success__, \ local_rsrc__, \ local_size__, \ this) \ if (local_success__) \ `m_uvm_``TYPE``_resize(ARG, local_size__) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if (local_index__ < 0) begin \ `uvm_warning("UVM/FIELDS/QDA_IDX", $sformatf("Index '%0d' is not valid for field '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ ARG.size() ) ) \ end \ else begin \ T tmp_enum__; \ `uvm_resource_enum_read(local_success__, \ local_rsrc__, \ T, \ tmp_enum__, \ this) \ if (local_success__) begin \ if (local_index__ >= ARG.size()) \ `m_uvm_``TYPE``_resize(ARG, local_index__ + 1) \ ARG[local_index__] = tmp_enum__; \ end \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_queue_int(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_qda_int(queue,ARG,FLAG) `define uvm_field_queue_object(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_qda_object(queue,ARG,FLAG) `define uvm_field_queue_string(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_qda_string(queue,ARG,FLAG) `define uvm_field_queue_enum(T,ARG,FLAG=UVM_DEFAULT) \ `m_field_qda_enum(queue,T,ARG,FLAG) `define uvm_field_aa_int_string(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG,`"ARG[+]`") \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_aa_int_string(ARG, local_rhs__.ARG, `m_uvm_field_radix(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_aa_int_string(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_aa_int_string(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_aa_int_string(ARG, `m_uvm_field_radix(FLAG), int, __local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/AA_SIZE", $sformatf("Associative array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ `uvm_resource_builtin_int_read(local_success__, \ local_rsrc__, \ ARG[local_index__], \ this) \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_aa_object_string(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG,`"ARG[+]`") \ `m_uvm_field_op_begin(COPY,FLAG) \ `uvm_copy_aa_object(ARG, local_rhs__.ARG, `m_uvm_field_recursion(FLAG), __local_copier__) \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_aa_object_string(ARG, local_rhs__.ARG, `m_uvm_field_recursion(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ if (`m_uvm_field_recursion(FLAG) != UVM_REFERENCE) \ `uvm_pack_aa_object_string(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ if (`m_uvm_field_recursion(FLAG) != UVM_REFERENCE) \ `uvm_unpack_aa_object_string(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_aa_object_string(ARG, `m_uvm_field_recursion(FLAG),__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/AA_SIZE", $sformatf("Associative array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ `uvm_resource_read(local_success__, \ local_rsrc__, \ uvm_object, \ local_obj__, \ this) \ if (local_success__) begin \ if (local_obj__ == null) begin \ ARG[local_index__] = null; \ end else if (!$cast(ARG[local_index__], local_obj__) && uvm_config_db_options::is_tracing()) begin \ `uvm_info("CFGDB/OBJ_TYPE", $sformatf("Can't set field '%s[%s]' on '%s' with '%s' type", \ `"ARG`", \ local_index__, \ this.get_full_name(), \ local_obj__.get_type_name()),UVM_LOW) \ end \ end \ /* TODO if(local_success__ && printing matches) */ \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_aa_string_string(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG,`"ARG[+]`") \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_aa_string_string(ARG, local_rhs__.ARG, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_aa_string_string(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_aa_string_string(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_aa_string_string(ARG,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/AA_SIZE", $sformatf("Associative array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ `uvm_resource_read(local_success__, \ local_rsrc__, \ string, \ ARG[local_index__], \ this) \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_aa_object_int(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_object_key(int, ARG, FLAG) `define uvm_field_aa_object_key(KEY, ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG, `"ARG[+]`") \ `m_uvm_field_op_begin(COPY,FLAG) \ `uvm_copy_aa_object(ARG, local_rhs__.ARG, `m_uvm_field_recursion(FLAG), __local_copier__) \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_aa_object_int(ARG, local_rhs__.ARG, `m_uvm_field_recursion(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ if (`m_uvm_field_recursion(FLAG) != UVM_REFERENCE) \ `uvm_pack_aa_object_intN(ARG, $bits(KEY), __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ if (`m_uvm_field_recursion(FLAG) != UVM_REFERENCE) \ `uvm_unpack_aa_object_intN(ARG, $bits(KEY), __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_aa_object_int(ARG, `m_uvm_field_recursion(FLAG), KEY,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/SARRAY_SIZE", $sformatf("Static array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ KEY local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ `uvm_resource_read(local_success__, \ local_rsrc__, \ uvm_object, \ local_obj__, \ this) \ if (local_success__) begin \ if (local_obj__ == null) begin \ ARG[local_index__] = null; \ end else if (!$cast(ARG[local_index__], local_obj__) && uvm_config_db_options::is_tracing()) begin \ `uvm_info("CFGDB/OBJ_TYPE", $sformatf("Can't set field '%s[%d]' on '%s' with '%s' type", \ `"ARG`", \ local_index__, \ this.get_full_name(), \ local_obj__.get_type_name()),UVM_LOW) \ end \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_aa_string_int(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_string_key(int, ARG, FLAG) `define uvm_field_aa_string_key(KEY, ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG, `"ARG[+]`") \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_aa_string_int(ARG, local_rhs__.ARG, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_aa_string_intN(ARG, $bits(KEY), __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_aa_string_intN(ARG, $bits(KEY), __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(PRINT,FLAG) \ /* TODO */ \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/SARRAY_SIZE", $sformatf("Static array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ KEY local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ `uvm_resource_read(local_success__, \ local_rsrc__, \ string, \ ARG[local_index__], \ this) \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_aa_int_int(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(int, ARG, FLAG) \ `define uvm_field_aa_int_int_unsigned(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(int unsigned, ARG, FLAG) `define uvm_field_aa_int_integer(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(integer, ARG, FLAG) `define uvm_field_aa_int_integer_unsigned(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(integer unsigned, ARG, FLAG) `define uvm_field_aa_int_byte(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(byte, ARG, FLAG) `define uvm_field_aa_int_byte_unsigned(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(byte unsigned, ARG, FLAG) `define uvm_field_aa_int_shortint(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(shortint, ARG, FLAG) `define uvm_field_aa_int_shortint_unsigned(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(shortint unsigned, ARG, FLAG) `define uvm_field_aa_int_longint(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(longint, ARG, FLAG) `define uvm_field_aa_int_longint_unsigned(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(longint unsigned, ARG, FLAG) `define uvm_field_aa_int_key(KEY, ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG, `"ARG[+]`") \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_aa_int_int(ARG, local_rhs__.ARG, `m_uvm_field_radix(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_aa_int_intN(ARG, $bits(KEY), __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_aa_int_intN(ARG, $bits(KEY), __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_aa_int_int(ARG, `m_uvm_field_radix(FLAG), , KEY,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/AA_SIZE", $sformatf("Associative array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ KEY local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ `uvm_resource_int_read(local_success__, \ local_rsrc__, \ KEY, \ ARG[local_index__], \ this) \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_aa_int_enumkey(KEY, ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG, `"ARG[+]`") \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_aa_int_int(ARG, local_rhs__.ARG, `m_uvm_field_radix(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_aa_int_enum(ARG, KEY, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_aa_int_enum(ARG, KEY, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_aa_int_enum(KEY, ARG, `m_uvm_field_radix(FLAG),,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/AA_SIZE", $sformatf("Associative array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ KEY local_index__; \ bit[$bits(KEY)-1:0] local_bit_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_bit_index__); \ if (local_code__ > 0) begin \ local_index__ = KEY'(local_bit_index__); \ `uvm_resource_int_read(local_success__, \ local_rsrc__, \ KEY, \ ARG[local_index__], \ this) \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_sarray_real(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG, `"ARG[+]`") \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_sarray_real(ARG, local_rhs__.ARG, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_sarray_real(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_sarray_real(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_real(ARG, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_sarray_real(ARG,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/SARRAY_SIZE", $sformatf("Static array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if ((local_index__ >= $size(ARG)) || (local_index__ < 0)) begin \ `uvm_warning("UVM/FIELDS/SARRAY_IDX", $sformatf("Index '%d' is not valid for static array '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ $size(ARG))) \ end \ else begin \ `uvm_resource_real_read(local_success__, \ local_rsrc__, \ ARG[local_index__], \ this) \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define m_uvm_field_qda_real(TYPE,ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG, `"ARG[+]`") \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_qda_real(ARG, local_rhs__.ARG, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_``TYPE``_real(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_``TYPE``_real(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_real(ARG, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_qda_real(TYPE, ARG,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_real_read(local_success__, \ local_rsrc__, \ local_size__, \ this) \ if (local_success__) \ `m_uvm_``TYPE``_resize(ARG, local_size__) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if (local_index__ < 0) begin \ `uvm_warning("UVM/FIELDS/QDA_IDX", $sformatf("Index '%0d' is not valid for field '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ ARG.size() ) ) \ end \ else begin \ real tmp_real__; \ `uvm_resource_real_read(local_success__, \ local_rsrc__, \ tmp_real__, \ this) \ if (local_success__) begin \ if (local_index__ >= ARG.size()) \ `m_uvm_``TYPE``_resize(ARG, local_index__ + 1) \ ARG[local_index__] = tmp_real__; \ end \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_array_real(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_qda_real(da,ARG,FLAG) `define uvm_field_queue_real(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_qda_real(queue,ARG,FLAG) `define uvm_blocking_put_imp_decl(SFX) \ class uvm_blocking_put_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_BLOCKING_PUT_MASK,`"uvm_blocking_put_imp``SFX`",IMP) \ `UVM_BLOCKING_PUT_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_nonblocking_put_imp_decl(SFX) \ class uvm_nonblocking_put_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_NONBLOCKING_PUT_MASK,`"uvm_nonblocking_put_imp``SFX`",IMP) \ `UVM_NONBLOCKING_PUT_IMP_SFX( SFX, m_imp, T, t) \ endclass `define uvm_put_imp_decl(SFX) \ class uvm_put_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_PUT_MASK,`"uvm_put_imp``SFX`",IMP) \ `UVM_BLOCKING_PUT_IMP_SFX(SFX, m_imp, T, t) \ `UVM_NONBLOCKING_PUT_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_blocking_get_imp_decl(SFX) \ class uvm_blocking_get_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_BLOCKING_GET_MASK,`"uvm_blocking_get_imp``SFX`",IMP) \ `UVM_BLOCKING_GET_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_nonblocking_get_imp_decl(SFX) \ class uvm_nonblocking_get_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_NONBLOCKING_GET_MASK,`"uvm_nonblocking_get_imp``SFX`",IMP) \ `UVM_NONBLOCKING_GET_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_get_imp_decl(SFX) \ class uvm_get_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_GET_MASK,`"uvm_get_imp``SFX`",IMP) \ `UVM_BLOCKING_GET_IMP_SFX(SFX, m_imp, T, t) \ `UVM_NONBLOCKING_GET_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_blocking_peek_imp_decl(SFX) \ class uvm_blocking_peek_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_BLOCKING_PEEK_MASK,`"uvm_blocking_peek_imp``SFX`",IMP) \ `UVM_BLOCKING_PEEK_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_nonblocking_peek_imp_decl(SFX) \ class uvm_nonblocking_peek_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_NONBLOCKING_PEEK_MASK,`"uvm_nonblocking_peek_imp``SFX`",IMP) \ `UVM_NONBLOCKING_PEEK_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_peek_imp_decl(SFX) \ class uvm_peek_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_PEEK_MASK,`"uvm_peek_imp``SFX`",IMP) \ `UVM_BLOCKING_PEEK_IMP_SFX(SFX, m_imp, T, t) \ `UVM_NONBLOCKING_PEEK_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_blocking_get_peek_imp_decl(SFX) \ class uvm_blocking_get_peek_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_BLOCKING_GET_PEEK_MASK,`"uvm_blocking_get_peek_imp``SFX`",IMP) \ `UVM_BLOCKING_GET_IMP_SFX(SFX, m_imp, T, t) \ `UVM_BLOCKING_PEEK_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_nonblocking_get_peek_imp_decl(SFX) \ class uvm_nonblocking_get_peek_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_NONBLOCKING_GET_PEEK_MASK,`"uvm_nonblocking_get_peek_imp``SFX`",IMP) \ `UVM_NONBLOCKING_GET_IMP_SFX(SFX, m_imp, T, t) \ `UVM_NONBLOCKING_PEEK_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_get_peek_imp_decl(SFX) \ class uvm_get_peek_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_GET_PEEK_MASK,`"uvm_get_peek_imp``SFX`",IMP) \ `UVM_BLOCKING_GET_IMP_SFX(SFX, m_imp, T, t) \ `UVM_NONBLOCKING_GET_IMP_SFX(SFX, m_imp, T, t) \ `UVM_BLOCKING_PEEK_IMP_SFX(SFX, m_imp, T, t) \ `UVM_NONBLOCKING_PEEK_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_blocking_master_imp_decl(SFX) \ class uvm_blocking_master_imp``SFX #(type REQ=int, type RSP=int, type IMP=int, \ type REQ_IMP=IMP, type RSP_IMP=IMP) \ extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); \ typedef IMP this_imp_type; \ typedef REQ_IMP this_req_type; \ typedef RSP_IMP this_rsp_type; \ `UVM_MS_IMP_COMMON(`UVM_TLM_BLOCKING_MASTER_MASK,`"uvm_blocking_master_imp``SFX`") \ \ `UVM_BLOCKING_PUT_IMP_SFX(SFX, m_req_imp, REQ, t) \ \ `UVM_BLOCKING_GET_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ `UVM_BLOCKING_PEEK_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ \ endclass `define uvm_nonblocking_master_imp_decl(SFX) \ class uvm_nonblocking_master_imp``SFX #(type REQ=int, type RSP=int, type IMP=int, \ type REQ_IMP=IMP, type RSP_IMP=IMP) \ extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); \ typedef IMP this_imp_type; \ typedef REQ_IMP this_req_type; \ typedef RSP_IMP this_rsp_type; \ `UVM_MS_IMP_COMMON(`UVM_TLM_NONBLOCKING_MASTER_MASK,`"uvm_nonblocking_master_imp``SFX`") \ \ `UVM_NONBLOCKING_PUT_IMP_SFX(SFX, m_req_imp, REQ, t) \ \ `UVM_NONBLOCKING_GET_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ `UVM_NONBLOCKING_PEEK_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ \ endclass `define uvm_master_imp_decl(SFX) \ class uvm_master_imp``SFX #(type REQ=int, type RSP=int, type IMP=int, \ type REQ_IMP=IMP, type RSP_IMP=IMP) \ extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); \ typedef IMP this_imp_type; \ typedef REQ_IMP this_req_type; \ typedef RSP_IMP this_rsp_type; \ `UVM_MS_IMP_COMMON(`UVM_TLM_MASTER_MASK,`"uvm_master_imp``SFX`") \ \ `UVM_BLOCKING_PUT_IMP_SFX(SFX, m_req_imp, REQ, t) \ `UVM_NONBLOCKING_PUT_IMP_SFX(SFX, m_req_imp, REQ, t) \ \ `UVM_BLOCKING_GET_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ `UVM_BLOCKING_PEEK_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ `UVM_NONBLOCKING_GET_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ `UVM_NONBLOCKING_PEEK_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ \ endclass `define uvm_blocking_slave_imp_decl(SFX) \ class uvm_blocking_slave_imp``SFX #(type REQ=int, type RSP=int, type IMP=int, \ type REQ_IMP=IMP, type RSP_IMP=IMP) \ extends uvm_port_base #(uvm_tlm_if_base #(RSP, REQ)); \ typedef IMP this_imp_type; \ typedef REQ_IMP this_req_type; \ typedef RSP_IMP this_rsp_type; \ `UVM_MS_IMP_COMMON(`UVM_TLM_BLOCKING_SLAVE_MASK,`"uvm_blocking_slave_imp``SFX`") \ \ `UVM_BLOCKING_PUT_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ \ `UVM_BLOCKING_GET_IMP_SFX(SFX, m_req_imp, REQ, t) \ `UVM_BLOCKING_PEEK_IMP_SFX(SFX, m_req_imp, REQ, t) \ \ endclass `define uvm_nonblocking_slave_imp_decl(SFX) \ class uvm_nonblocking_slave_imp``SFX #(type REQ=int, type RSP=int, type IMP=int, \ type REQ_IMP=IMP, type RSP_IMP=IMP) \ extends uvm_port_base #(uvm_tlm_if_base #(RSP, REQ)); \ typedef IMP this_imp_type; \ typedef REQ_IMP this_req_type; \ typedef RSP_IMP this_rsp_type; \ `UVM_MS_IMP_COMMON(`UVM_TLM_NONBLOCKING_SLAVE_MASK,`"uvm_nonblocking_slave_imp``SFX`") \ \ `UVM_NONBLOCKING_PUT_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ \ `UVM_NONBLOCKING_GET_IMP_SFX(SFX, m_req_imp, REQ, t) \ `UVM_NONBLOCKING_PEEK_IMP_SFX(SFX, m_req_imp, REQ, t) \ \ endclass `define uvm_slave_imp_decl(SFX) \ class uvm_slave_imp``SFX #(type REQ=int, type RSP=int, type IMP=int, \ type REQ_IMP=IMP, type RSP_IMP=IMP) \ extends uvm_port_base #(uvm_tlm_if_base #(RSP, REQ)); \ typedef IMP this_imp_type; \ typedef REQ_IMP this_req_type; \ typedef RSP_IMP this_rsp_type; \ `UVM_MS_IMP_COMMON(`UVM_TLM_SLAVE_MASK,`"uvm_slave_imp``SFX`") \ \ `UVM_BLOCKING_PUT_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ `UVM_NONBLOCKING_PUT_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ \ `UVM_BLOCKING_GET_IMP_SFX(SFX, m_req_imp, REQ, t) \ `UVM_BLOCKING_PEEK_IMP_SFX(SFX, m_req_imp, REQ, t) \ `UVM_NONBLOCKING_GET_IMP_SFX(SFX, m_req_imp, REQ, t) \ `UVM_NONBLOCKING_PEEK_IMP_SFX(SFX, m_req_imp, REQ, t) \ \ endclass `define uvm_blocking_transport_imp_decl(SFX) \ class uvm_blocking_transport_imp``SFX #(type REQ=int, type RSP=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); \ `UVM_IMP_COMMON(`UVM_TLM_BLOCKING_TRANSPORT_MASK,`"uvm_blocking_transport_imp``SFX`",IMP) \ `UVM_BLOCKING_TRANSPORT_IMP_SFX(SFX, m_imp, REQ, RSP, req, rsp) \ endclass `define uvm_nonblocking_transport_imp_decl(SFX) \ class uvm_nonblocking_transport_imp``SFX #(type REQ=int, type RSP=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); \ `UVM_IMP_COMMON(`UVM_TLM_NONBLOCKING_TRANSPORT_MASK,`"uvm_nonblocking_transport_imp``SFX`",IMP) \ `UVM_NONBLOCKING_TRANSPORT_IMP_SFX(SFX, m_imp, REQ, RSP, req, rsp) \ endclass `define uvm_non_blocking_transport_imp_decl(SFX) \ `uvm_nonblocking_transport_imp_decl(SFX) `define uvm_transport_imp_decl(SFX) \ class uvm_transport_imp``SFX #(type REQ=int, type RSP=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); \ `UVM_IMP_COMMON(`UVM_TLM_TRANSPORT_MASK,`"uvm_transport_imp``SFX`",IMP) \ `UVM_BLOCKING_TRANSPORT_IMP_SFX(SFX, m_imp, REQ, RSP, req, rsp) \ `UVM_NONBLOCKING_TRANSPORT_IMP_SFX(SFX, m_imp, REQ, RSP, req, rsp) \ endclass `define uvm_analysis_imp_decl(SFX) \ class uvm_analysis_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_ANALYSIS_MASK,`"uvm_analysis_imp``SFX`",IMP) \ function void write( input T t); \ m_imp.write``SFX( t); \ endfunction \ \ endclass `define UVM_BLOCKING_PUT_IMP_SFX(SFX, imp, TYPE, arg) \ task put( input TYPE arg); imp.put``SFX( arg); endtask `define UVM_BLOCKING_GET_IMP_SFX(SFX, imp, TYPE, arg) \ task get( output TYPE arg); imp.get``SFX( arg); endtask `define UVM_BLOCKING_PEEK_IMP_SFX(SFX, imp, TYPE, arg) \ task peek( output TYPE arg);imp.peek``SFX( arg); endtask `define UVM_NONBLOCKING_PUT_IMP_SFX(SFX, imp, TYPE, arg) \ function bit try_put( input TYPE arg); \ if( !imp.try_put``SFX( arg)) return 0; \ return 1; \ endfunction \ function bit can_put(); return imp.can_put``SFX(); endfunction `define UVM_NONBLOCKING_GET_IMP_SFX(SFX, imp, TYPE, arg) \ function bit try_get( output TYPE arg); \ if( !imp.try_get``SFX( arg)) return 0; \ return 1; \ endfunction \ function bit can_get(); return imp.can_get``SFX(); endfunction `define UVM_NONBLOCKING_PEEK_IMP_SFX(SFX, imp, TYPE, arg) \ function bit try_peek( output TYPE arg); \ if( !imp.try_peek``SFX( arg)) return 0; \ return 1; \ endfunction \ function bit can_peek(); return imp.can_peek``SFX(); endfunction `define UVM_BLOCKING_TRANSPORT_IMP_SFX(SFX, imp, REQ, RSP, req_arg, rsp_arg) \ task transport( input REQ req_arg, output RSP rsp_arg); \ imp.transport``SFX(req_arg, rsp_arg); \ endtask `define UVM_NONBLOCKING_TRANSPORT_IMP_SFX(SFX, imp, REQ, RSP, req_arg, rsp_arg) \ function bit nb_transport( input REQ req_arg, output RSP rsp_arg); \ if(imp) return imp.nb_transport``SFX(req_arg, rsp_arg); \ endfunction `define UVM_SEQ_ITEM_PULL_IMP(imp, REQ, RSP, req_arg, rsp_arg) \ function void disable_auto_item_recording(); imp.disable_auto_item_recording(); endfunction \ function bit is_auto_item_recording_enabled(); return imp.is_auto_item_recording_enabled(); endfunction \ task get_next_item(output REQ req_arg); imp.get_next_item(req_arg); endtask \ task try_next_item(output REQ req_arg); imp.try_next_item(req_arg); endtask \ function void item_done(input RSP rsp_arg = null); imp.item_done(rsp_arg); endfunction \ task wait_for_sequences(); imp.wait_for_sequences(); endtask \ function bit has_do_available(); return imp.has_do_available(); endfunction \ function void put_response(input RSP rsp_arg); imp.put_response(rsp_arg); endfunction \ task get(output REQ req_arg); imp.get(req_arg); endtask \ task peek(output REQ req_arg); imp.peek(req_arg); endtask \ task put(input RSP rsp_arg); imp.put(rsp_arg); endtask `define UVM_TLM_BLOCKING_PUT_MASK (1<<0) `define UVM_TLM_BLOCKING_GET_MASK (1<<1) `define UVM_TLM_BLOCKING_PEEK_MASK (1<<2) `define UVM_TLM_BLOCKING_TRANSPORT_MASK (1<<3) `define UVM_TLM_NONBLOCKING_PUT_MASK (1<<4) `define UVM_TLM_NONBLOCKING_GET_MASK (1<<5) `define UVM_TLM_NONBLOCKING_PEEK_MASK (1<<6) `define UVM_TLM_NONBLOCKING_TRANSPORT_MASK (1<<7) `define UVM_TLM_ANALYSIS_MASK (1<<8) `define UVM_TLM_MASTER_BIT_MASK (1<<9) `define UVM_TLM_SLAVE_BIT_MASK (1<<10) `define UVM_TLM_PUT_MASK (`UVM_TLM_BLOCKING_PUT_MASK | `UVM_TLM_NONBLOCKING_PUT_MASK) `define UVM_TLM_GET_MASK (`UVM_TLM_BLOCKING_GET_MASK | `UVM_TLM_NONBLOCKING_GET_MASK) `define UVM_TLM_PEEK_MASK (`UVM_TLM_BLOCKING_PEEK_MASK | `UVM_TLM_NONBLOCKING_PEEK_MASK) `define UVM_TLM_BLOCKING_GET_PEEK_MASK (`UVM_TLM_BLOCKING_GET_MASK | `UVM_TLM_BLOCKING_PEEK_MASK) `define UVM_TLM_BLOCKING_MASTER_MASK (`UVM_TLM_BLOCKING_PUT_MASK | `UVM_TLM_BLOCKING_GET_MASK | `UVM_TLM_BLOCKING_PEEK_MASK | `UVM_TLM_MASTER_BIT_MASK) `define UVM_TLM_BLOCKING_SLAVE_MASK (`UVM_TLM_BLOCKING_PUT_MASK | `UVM_TLM_BLOCKING_GET_MASK | `UVM_TLM_BLOCKING_PEEK_MASK | `UVM_TLM_SLAVE_BIT_MASK) `define UVM_TLM_NONBLOCKING_GET_PEEK_MASK (`UVM_TLM_NONBLOCKING_GET_MASK | `UVM_TLM_NONBLOCKING_PEEK_MASK) `define UVM_TLM_NONBLOCKING_MASTER_MASK (`UVM_TLM_NONBLOCKING_PUT_MASK | `UVM_TLM_NONBLOCKING_GET_MASK | `UVM_TLM_NONBLOCKING_PEEK_MASK | `UVM_TLM_MASTER_BIT_MASK) `define UVM_TLM_NONBLOCKING_SLAVE_MASK (`UVM_TLM_NONBLOCKING_PUT_MASK | `UVM_TLM_NONBLOCKING_GET_MASK | `UVM_TLM_NONBLOCKING_PEEK_MASK | `UVM_TLM_SLAVE_BIT_MASK) `define UVM_TLM_GET_PEEK_MASK (`UVM_TLM_GET_MASK | `UVM_TLM_PEEK_MASK) `define UVM_TLM_MASTER_MASK (`UVM_TLM_BLOCKING_MASTER_MASK | `UVM_TLM_NONBLOCKING_MASTER_MASK) `define UVM_TLM_SLAVE_MASK (`UVM_TLM_BLOCKING_SLAVE_MASK | `UVM_TLM_NONBLOCKING_SLAVE_MASK) `define UVM_TLM_TRANSPORT_MASK (`UVM_TLM_BLOCKING_TRANSPORT_MASK | `UVM_TLM_NONBLOCKING_TRANSPORT_MASK) `define UVM_SEQ_ITEM_GET_NEXT_ITEM_MASK (1<<0) `define UVM_SEQ_ITEM_TRY_NEXT_ITEM_MASK (1<<1) `define UVM_SEQ_ITEM_ITEM_DONE_MASK (1<<2) `define UVM_SEQ_ITEM_HAS_DO_AVAILABLE_MASK (1<<3) `define UVM_SEQ_ITEM_WAIT_FOR_SEQUENCES_MASK (1<<4) `define UVM_SEQ_ITEM_PUT_RESPONSE_MASK (1<<5) `define UVM_SEQ_ITEM_PUT_MASK (1<<6) `define UVM_SEQ_ITEM_GET_MASK (1<<7) `define UVM_SEQ_ITEM_PEEK_MASK (1<<8) `define UVM_SEQ_ITEM_PULL_MASK (`UVM_SEQ_ITEM_GET_NEXT_ITEM_MASK | `UVM_SEQ_ITEM_TRY_NEXT_ITEM_MASK | \ `UVM_SEQ_ITEM_ITEM_DONE_MASK | `UVM_SEQ_ITEM_HAS_DO_AVAILABLE_MASK | \ `UVM_SEQ_ITEM_WAIT_FOR_SEQUENCES_MASK | `UVM_SEQ_ITEM_PUT_RESPONSE_MASK | \ `UVM_SEQ_ITEM_PUT_MASK | `UVM_SEQ_ITEM_GET_MASK | `UVM_SEQ_ITEM_PEEK_MASK) `define UVM_SEQ_ITEM_UNI_PULL_MASK (`UVM_SEQ_ITEM_GET_NEXT_ITEM_MASK | `UVM_SEQ_ITEM_TRY_NEXT_ITEM_MASK | \ `UVM_SEQ_ITEM_ITEM_DONE_MASK | `UVM_SEQ_ITEM_HAS_DO_AVAILABLE_MASK | \ `UVM_SEQ_ITEM_WAIT_FOR_SEQUENCES_MASK | `UVM_SEQ_ITEM_GET_MASK | \ `UVM_SEQ_ITEM_PEEK_MASK) `define UVM_SEQ_ITEM_PUSH_MASK (`UVM_SEQ_ITEM_PUT_MASK) `define UVM_TLM_IMPS_SVH `define UVM_BLOCKING_PUT_IMP(imp, TYPE, arg) \ task put (TYPE arg); \ imp.put(arg); \ endtask `define UVM_NONBLOCKING_PUT_IMP(imp, TYPE, arg) \ function bit try_put (TYPE arg); \ return imp.try_put(arg); \ endfunction \ function bit can_put(); \ return imp.can_put(); \ endfunction `define UVM_BLOCKING_GET_IMP(imp, TYPE, arg) \ task get (output TYPE arg); \ imp.get(arg); \ endtask `define UVM_NONBLOCKING_GET_IMP(imp, TYPE, arg) \ function bit try_get (output TYPE arg); \ return imp.try_get(arg); \ endfunction \ function bit can_get(); \ return imp.can_get(); \ endfunction `define UVM_BLOCKING_PEEK_IMP(imp, TYPE, arg) \ task peek (output TYPE arg); \ imp.peek(arg); \ endtask `define UVM_NONBLOCKING_PEEK_IMP(imp, TYPE, arg) \ function bit try_peek (output TYPE arg); \ return imp.try_peek(arg); \ endfunction \ function bit can_peek(); \ return imp.can_peek(); \ endfunction `define UVM_BLOCKING_TRANSPORT_IMP(imp, REQ, RSP, req_arg, rsp_arg) \ task transport (REQ req_arg, output RSP rsp_arg); \ imp.transport(req_arg, rsp_arg); \ endtask `define UVM_NONBLOCKING_TRANSPORT_IMP(imp, REQ, RSP, req_arg, rsp_arg) \ function bit nb_transport (REQ req_arg, output RSP rsp_arg); \ return imp.nb_transport(req_arg, rsp_arg); \ endfunction `define UVM_PUT_IMP(imp, TYPE, arg) \ `UVM_BLOCKING_PUT_IMP(imp, TYPE, arg) \ `UVM_NONBLOCKING_PUT_IMP(imp, TYPE, arg) `define UVM_GET_IMP(imp, TYPE, arg) \ `UVM_BLOCKING_GET_IMP(imp, TYPE, arg) \ `UVM_NONBLOCKING_GET_IMP(imp, TYPE, arg) `define UVM_PEEK_IMP(imp, TYPE, arg) \ `UVM_BLOCKING_PEEK_IMP(imp, TYPE, arg) \ `UVM_NONBLOCKING_PEEK_IMP(imp, TYPE, arg) `define UVM_BLOCKING_GET_PEEK_IMP(imp, TYPE, arg) \ `UVM_BLOCKING_GET_IMP(imp, TYPE, arg) \ `UVM_BLOCKING_PEEK_IMP(imp, TYPE, arg) `define UVM_NONBLOCKING_GET_PEEK_IMP(imp, TYPE, arg) \ `UVM_NONBLOCKING_GET_IMP(imp, TYPE, arg) \ `UVM_NONBLOCKING_PEEK_IMP(imp, TYPE, arg) `define UVM_GET_PEEK_IMP(imp, TYPE, arg) \ `UVM_BLOCKING_GET_PEEK_IMP(imp, TYPE, arg) \ `UVM_NONBLOCKING_GET_PEEK_IMP(imp, TYPE, arg) `define UVM_TRANSPORT_IMP(imp, REQ, RSP, req_arg, rsp_arg) \ `UVM_BLOCKING_TRANSPORT_IMP(imp, REQ, RSP, req_arg, rsp_arg) \ `UVM_NONBLOCKING_TRANSPORT_IMP(imp, REQ, RSP, req_arg, rsp_arg) `define UVM_TLM_GET_TYPE_NAME(NAME) \ virtual function string get_type_name(); \ return NAME; \ endfunction `define UVM_PORT_COMMON(MASK,TYPE_NAME) \ function new (string name, uvm_component parent, \ int min_size=1, int max_size=1); \ super.new (name, parent, UVM_PORT, min_size, max_size); \ m_if_mask = MASK; \ endfunction \ `UVM_TLM_GET_TYPE_NAME(TYPE_NAME) `define UVM_SEQ_PORT(MASK,TYPE_NAME) \ function new (string name, uvm_component parent, \ int min_size=0, int max_size=1); \ super.new (name, parent, UVM_PORT, min_size, max_size); \ m_if_mask = MASK; \ endfunction \ `UVM_TLM_GET_TYPE_NAME(TYPE_NAME) `define UVM_EXPORT_COMMON(MASK,TYPE_NAME) \ function new (string name, uvm_component parent, \ int min_size=1, int max_size=1); \ super.new (name, parent, UVM_EXPORT, min_size, max_size); \ m_if_mask = MASK; \ endfunction \ `UVM_TLM_GET_TYPE_NAME(TYPE_NAME) `define UVM_IMP_COMMON(MASK,TYPE_NAME,IMP) \ local IMP m_imp; \ function new (string name, IMP imp); \ super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); \ m_imp = imp; \ m_if_mask = MASK; \ endfunction \ `UVM_TLM_GET_TYPE_NAME(TYPE_NAME) `define UVM_MS_IMP_COMMON(MASK,TYPE_NAME) \ local this_req_type m_req_imp; \ local this_rsp_type m_rsp_imp; \ function new (string name, this_imp_type imp, \ this_req_type req_imp = null, this_rsp_type rsp_imp = null); \ super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); \ if(req_imp==null) begin \ $cast(req_imp, imp); \ end \ if(rsp_imp==null) begin \ $cast(rsp_imp, imp); \ end \ m_req_imp = req_imp; \ m_rsp_imp = rsp_imp; \ m_if_mask = MASK; \ endfunction \ `UVM_TLM_GET_TYPE_NAME(TYPE_NAME) `define uvm_create(SEQ_OR_ITEM, SEQR=get_sequencer()) \ begin \ uvm_object_wrapper w_; \ w_ = SEQ_OR_ITEM.get_type(); \ $cast(SEQ_OR_ITEM , create_item(w_, SEQR, `"SEQ_OR_ITEM`"));\ end `define uvm_do(SEQ_OR_ITEM, SEQR=get_sequencer(), PRIORITY=-1, CONSTRAINTS={}) \ begin \ `uvm_create(SEQ_OR_ITEM, SEQR) \ `uvm_rand_send(SEQ_OR_ITEM, PRIORITY, CONSTRAINTS) \ end `define uvm_send(SEQ_OR_ITEM, PRIORITY=-1) \ begin \ uvm_sequence_base __seq; \ if (!$cast(__seq,SEQ_OR_ITEM)) begin \ start_item(SEQ_OR_ITEM, PRIORITY);\ finish_item(SEQ_OR_ITEM, PRIORITY);\ end \ else __seq.start(__seq.get_sequencer(), this, PRIORITY, 0);\ end `define uvm_rand_send(SEQ_OR_ITEM, PRIORITY=-1, CONSTRAINTS={}) \ begin \ uvm_sequence_base __seq; \ if ( SEQ_OR_ITEM.is_item() ) begin \ start_item(SEQ_OR_ITEM, PRIORITY);\ if ( ! SEQ_OR_ITEM.randomize() with CONSTRAINTS ) begin \ `uvm_warning("RNDFLD", "Randomization failed in uvm_rand_send action") \ end\ finish_item(SEQ_OR_ITEM, PRIORITY);\ end \ else if ( $cast( __seq, SEQ_OR_ITEM ) ) begin \ __seq.set_item_context(this,SEQ_OR_ITEM.get_sequencer()); \ if ( __seq.get_randomize_enabled() ) begin \ if ( ! SEQ_OR_ITEM.randomize() with CONSTRAINTS ) begin \ `uvm_warning("RNDFLD", "Randomization failed in uvm_rand_send action") \ end \ end \ __seq.start(__seq.get_sequencer(), this, PRIORITY, 0);\ end \ else begin \ `uvm_warning("NOT_SEQ_OR_ITEM", "Object passed uvm_rand_send appears to be neither a sequence or item." ) \ end \ end `define uvm_add_to_seq_lib(TYPE,LIBTYPE) \ static bit add_``TYPE``_to_seq_lib_``LIBTYPE =\ LIBTYPE::m_add_typewide_sequence(TYPE::get_type()); `define uvm_sequence_library_utils(TYPE) \ \ static protected uvm_object_wrapper m_typewide_sequences[$]; \ \ function void init_sequence_library(); \ foreach (TYPE::m_typewide_sequences[i]) \ sequences.push_back(TYPE::m_typewide_sequences[i]); \ endfunction \ \ static function void add_typewide_sequence(uvm_object_wrapper seq_type); \ if (m_static_check(seq_type)) \ TYPE::m_typewide_sequences.push_back(seq_type); \ endfunction \ \ static function void add_typewide_sequences(uvm_object_wrapper seq_types[$]); \ foreach (seq_types[i]) \ TYPE::add_typewide_sequence(seq_types[i]); \ endfunction \ \ static function bit m_add_typewide_sequence(uvm_object_wrapper seq_type); \ TYPE::add_typewide_sequence(seq_type); \ return 1; \ endfunction `define uvm_declare_p_sequencer(SEQUENCER) \ SEQUENCER p_sequencer;\ virtual function void m_set_p_sequencer();\ super.m_set_p_sequencer(); \ if( !$cast(p_sequencer, m_sequencer)) \ `uvm_fatal("DCLPSQ", \ $sformatf("%m %s Error casting p_sequencer, please verify that this sequence/sequence item is intended to execute on this type of sequencer", get_full_name())) \ endfunction `define UVM_CB_MACROS_SVH `define uvm_register_cb(T,CB) \ static local bit m_register_cb_``CB = uvm_callbacks#(T,CB)::m_register_pair(`"T`",`"CB`"); `define uvm_set_super_type(T,ST) \ static local bit m_register_``T``ST = uvm_derived_callbacks#(T,ST)::register_super_type(`"T`",`"ST`"); `define uvm_do_callbacks(T,CB,METHOD) \ `uvm_do_obj_callbacks(T,CB,this,METHOD) `define uvm_do_obj_callbacks(T,CB,OBJ,METHOD) \ begin \ uvm_callback_iter#(T,CB) iter = new(OBJ); \ CB cb = iter.first(); \ while(cb != null) begin \ `uvm_cb_trace_noobj(cb,$sformatf(`"Executing callback method 'METHOD' for callback %s (CB) from %s (T)`",cb.get_name(), OBJ.get_full_name())) \ cb.METHOD; \ cb = iter.next(); \ end \ end `define uvm_do_callbacks_exit_on(T,CB,METHOD,VAL) \ `uvm_do_obj_callbacks_exit_on(T,CB,this,METHOD,VAL) \ `define uvm_do_obj_callbacks_exit_on(T,CB,OBJ,METHOD,VAL) \ begin \ uvm_callback_iter#(T,CB) iter = new(OBJ); \ CB cb = iter.first(); \ while(cb != null) begin \ if (cb.METHOD == VAL) begin \ `uvm_cb_trace_noobj(cb,$sformatf(`"Executed callback method 'METHOD' for callback %s (CB) from %s (T) : returned value VAL (other callbacks will be ignored)`",cb.get_name(), OBJ.get_full_name())) \ return VAL; \ end \ `uvm_cb_trace_noobj(cb,$sformatf(`"Executed callback method 'METHOD' for callback %s (CB) from %s (T) : did not return value VAL`",cb.get_name(), OBJ.get_full_name())) \ cb = iter.next(); \ end \ return 1-VAL; \ end `define uvm_cb_trace_noobj(CB,OPER) /* null */ `define uvm_cb_trace(OBJ,CB,OPER) /* null */ `define UVM_REG_ADDR_WIDTH 64 `define UVM_REG_DATA_WIDTH 64 `define UVM_REG_BYTENABLE_WIDTH ((`UVM_REG_DATA_WIDTH-1)/8+1) `define UVM_REG_CVR_WIDTH 32 `define uvm_do_pri(SEQ_OR_ITEM, PRIORITY) \ `uvm_do(SEQ_OR_ITEM, get_sequencer(), PRIORITY, {}) `define uvm_do_with(SEQ_OR_ITEM, CONSTRAINTS) \ `uvm_do(SEQ_OR_ITEM, get_sequencer(), -1, CONSTRAINTS) `define uvm_do_pri_with(SEQ_OR_ITEM, PRIORITY, CONSTRAINTS) \ `uvm_do(SEQ_OR_ITEM, get_sequencer(), PRIORITY, CONSTRAINTS) `define uvm_create_on(SEQ_OR_ITEM, SEQR) \ `uvm_create(SEQ_OR_ITEM, SEQR) `define uvm_do_on(SEQ_OR_ITEM, SEQR) \ `uvm_do(SEQ_OR_ITEM, SEQR, -1, {}) `define uvm_do_on_pri(SEQ_OR_ITEM, SEQR, PRIORITY) \ `uvm_do(SEQ_OR_ITEM, SEQR, PRIORITY, {}) `define uvm_do_on_with(SEQ_OR_ITEM, SEQR, CONSTRAINTS) \ `uvm_do(SEQ_OR_ITEM, SEQR, -1, CONSTRAINTS) `define uvm_do_on_pri_with(SEQ_OR_ITEM, SEQR, PRIORITY, CONSTRAINTS) \ `uvm_do(SEQ_OR_ITEM, SEQR, PRIORITY, CONSTRAINTS) `define uvm_send_pri(SEQ_OR_ITEM, PRIORITY) \ `uvm_send(SEQ_OR_ITEM, PRIORITY) `define uvm_rand_send_pri(SEQ_OR_ITEM, PRIORITY) \ `uvm_rand_send(SEQ_OR_ITEM, PRIORITY, {}) `define uvm_rand_send_with(SEQ_OR_ITEM, CONSTRAINTS) \ `uvm_rand_send(SEQ_OR_ITEM, -1, CONSTRAINTS) `define uvm_rand_send_pri_with(SEQ_OR_ITEM, PRIORITY, CONSTRAINTS) \ `uvm_rand_send(SEQ_OR_ITEM, PRIORITY, CONSTRAINTS) `define uvm_create_seq(UVM_SEQ, SEQR_CONS_IF) \ `uvm_create(UVM_SEQ, SEQR_CONS_IF.consumer_seqr) \ `define uvm_do_seq(UVM_SEQ, SEQR_CONS_IF) \ `uvm_do(UVM_SEQ, SEQR_CONS_IF.consumer_seqr, -1, {}) \ `define uvm_do_seq_with(UVM_SEQ, SEQR_CONS_IF, CONSTRAINTS) \ `uvm_do(UVM_SEQ, SEQR_CONS_IF.consumer_seqr, -1, CONSTRAINTS) \ package uvm_pkg; `define UVM_DPI_SVH `define UVM_HDL_NO_DPI `define UVM_REGEX_NO_DPI `define UVM_CMDLINE_NO_DPI `define UVM_HDL__SVH `define UVM_HDL_MAX_WIDTH 1024 parameter int UVM_HDL_MAX_WIDTH = 1024; typedef logic [UVM_HDL_MAX_WIDTH-1:0] uvm_hdl_data_t; function int uvm_hdl_check_path(string path); uvm_report_fatal("UVM_HDL_CHECK_PATH", $sformatf("uvm_hdl DPI routines are compiled off. Recompile without +define+UVM_HDL_NO_DPI")); return 0; endfunction function int uvm_hdl_deposit(string path, uvm_hdl_data_t value); uvm_report_fatal("UVM_HDL_DEPOSIT", $sformatf("uvm_hdl DPI routines are compiled off. Recompile without +define+UVM_HDL_NO_DPI")); return 0; endfunction function int uvm_hdl_force(string path, uvm_hdl_data_t value); uvm_report_fatal("UVM_HDL_FORCE", $sformatf("uvm_hdl DPI routines are compiled off. Recompile without +define+UVM_HDL_NO_DPI")); return 0; endfunction task uvm_hdl_force_time(string path, uvm_hdl_data_t value, time force_time=0); uvm_report_fatal("UVM_HDL_FORCE_TIME", $sformatf("uvm_hdl DPI routines are compiled off. Recompile without +define+UVM_HDL_NO_DPI")); endtask function int uvm_hdl_release(string path); uvm_report_fatal("UVM_HDL_RELEASE", $sformatf("uvm_hdl DPI routines are compiled off. Recompile without +define+UVM_HDL_NO_DPI")); return 0; endfunction function int uvm_hdl_read(string path, output uvm_hdl_data_t value); uvm_report_fatal("UVM_HDL_READ", $sformatf("uvm_hdl DPI routines are compiled off. Recompile without +define+UVM_HDL_NO_DPI")); return 0; endfunction function string uvm_dpi_get_next_arg(int init=0); return ""; endfunction function string uvm_dpi_get_tool_name(); return "?"; endfunction function string uvm_dpi_get_tool_version(); return "?"; endfunction function chandle uvm_dpi_regcomp(string regex); return null; endfunction function int uvm_dpi_regexec(chandle preg, string str); return 0; endfunction function void uvm_dpi_regfree(chandle preg); endfunction function int uvm_re_match(string re, string str, bit deglob = 0); int e, es, s, ss; string tmp; e = 0; s = 0; es = 0; ss = 0; if(re.len() == 0) return 0; if(re[0] == "^") re = re.substr(1, re.len()-1); while (s != str.len() && re.getc(e) != "*") begin if ((re.getc(e) != str.getc(s)) && (re.getc(e) != "?")) return 1; e++; s++; end while (s != str.len()) begin if (re.getc(e) == "*") begin e++; if (e == re.len()) begin return 0; end es = e; ss = s+1; end else if (re.getc(e) == str.getc(s) || re.getc(e) == "?") begin e++; s++; end else begin e = es; s = ss++; end end while (e < re.len() && re.getc(e) == "*") e++; if(e == re.len()) begin return 0; end else begin return 1; end endfunction function string uvm_glob_to_re(string glob); return glob; endfunction `define UVM_BASE_SVH typedef class uvm_cmdline_processor; `define UVM_VERSION_SVH parameter string UVM_VERSION_STRING = "Accellera:1800.2:UVM:2020.3.1"; function string uvm_revision_string(); return UVM_VERSION_STRING; endfunction parameter UVM_STREAMBITS = 4096; typedef logic signed [UVM_STREAMBITS-1:0] uvm_bitstream_t; typedef logic signed [63:0] uvm_integral_t; typedef int uvm_transaction_id_t; typedef int uvm_tr_handle_t; parameter UVM_FIELD_FLAG_RESERVED_BITS = 28; typedef bit [UVM_FIELD_FLAG_RESERVED_BITS-1 : 0] uvm_field_flag_t; typedef enum uvm_field_flag_t { UVM_BIN = 'h1000000, UVM_DEC = 'h2000000, UVM_UNSIGNED = 'h3000000, UVM_UNFORMAT2 = 'h4000000, UVM_UNFORMAT4 = 'h5000000, UVM_OCT = 'h6000000, UVM_HEX = 'h7000000, UVM_STRING = 'h8000000, UVM_TIME = 'h9000000, UVM_ENUM = 'ha000000, UVM_REAL = 'hb000000, UVM_REAL_DEC = 'hc000000, UVM_REAL_EXP = 'hd000000, UVM_NORADIX = 0 } uvm_radix_enum; parameter UVM_RADIX = 'hf000000; function string uvm_radix_to_string(uvm_radix_enum radix); case(radix) UVM_BIN: begin return "b"; end UVM_OCT: begin return "o"; end UVM_DEC: begin return "d"; end UVM_HEX: begin return "h"; end UVM_UNSIGNED: begin return "u"; end UVM_UNFORMAT2: begin return "u"; end UVM_UNFORMAT4: begin return "z"; end UVM_STRING: begin return "s"; end UVM_TIME: begin return "t"; end UVM_ENUM: begin return "s"; end UVM_REAL: begin return "g"; end UVM_REAL_DEC: begin return "f"; end UVM_REAL_EXP: begin return "e"; end default: begin return "x"; end endcase endfunction typedef enum uvm_field_flag_t { UVM_DEFAULT_POLICY = 0, UVM_DEEP = (1<<16), UVM_SHALLOW = (1<<17), UVM_REFERENCE = (1<<18) } uvm_recursion_policy_enum; parameter UVM_RECURSION = (UVM_DEEP|UVM_SHALLOW|UVM_REFERENCE); typedef enum bit { UVM_PASSIVE=0, UVM_ACTIVE=1 } uvm_active_passive_enum; parameter uvm_field_flag_t UVM_MACRO_NUMFLAGS = 19; parameter uvm_field_flag_t UVM_COPY = (1<<0); parameter uvm_field_flag_t UVM_NOCOPY = (1<<1); parameter uvm_field_flag_t UVM_COMPARE = (1<<2); parameter uvm_field_flag_t UVM_NOCOMPARE = (1<<3); parameter uvm_field_flag_t UVM_PRINT = (1<<4); parameter uvm_field_flag_t UVM_NOPRINT = (1<<5); parameter uvm_field_flag_t UVM_RECORD = (1<<6); parameter uvm_field_flag_t UVM_NORECORD = (1<<7); parameter uvm_field_flag_t UVM_PACK = (1<<8); parameter uvm_field_flag_t UVM_NOPACK = (1<<9); parameter uvm_field_flag_t UVM_UNPACK = (1<<10); parameter uvm_field_flag_t UVM_NOUNPACK = UVM_NOPACK; parameter uvm_field_flag_t UVM_SET = (1<<11); parameter uvm_field_flag_t UVM_NOSET = (1<<12); parameter uvm_field_flag_t UVM_PHYSICAL = (1<<13); parameter uvm_field_flag_t UVM_ABSTRACT = (1<<14); parameter uvm_field_flag_t UVM_READONLY = UVM_NOSET; parameter uvm_field_flag_t UVM_NODEFPRINT = (1<<15); parameter uvm_field_flag_t UVM_FLAGS_ON = UVM_COPY | UVM_COMPARE | UVM_PRINT | UVM_RECORD | UVM_PACK | UVM_UNPACK | UVM_SET ; parameter uvm_field_flag_t UVM_FLAGS_OFF = 0; parameter uvm_field_flag_t UVM_ALL_ON = UVM_FLAGS_ON; parameter uvm_field_flag_t UVM_DEFAULT = UVM_ALL_ON; parameter uvm_field_flag_t UVM_MACRO_EXTRAS = (1<"; end uvm_object_value_str.itoa(v.get_inst_id()); uvm_object_value_str = {"@",uvm_object_value_str}; endfunction function string uvm_leaf_scope (string full_name, byte scope_separator = "."); byte bracket_match; int pos; int bmatches; bmatches = 0; case(scope_separator) "[": begin bracket_match = "]"; end "(": begin bracket_match = ")"; end "<": begin bracket_match = ">"; end "{": begin bracket_match = "}"; end default: begin bracket_match = ""; end endcase if(bracket_match != "" && bracket_match != full_name[full_name.len()-1]) begin bracket_match = ""; end for(pos=full_name.len()-1; pos>0; --pos) begin if(full_name[pos] == bracket_match) begin bmatches++; end else if(full_name[pos] == scope_separator) begin bmatches--; if(!bmatches || (bracket_match == "")) begin break; end end end if(pos) begin if(scope_separator != ".") begin pos--; end uvm_leaf_scope = full_name.substr(pos+1,full_name.len()-1); end else begin uvm_leaf_scope = full_name; end endfunction virtual class uvm_bit_vector_utils#(type T=int); static function string to_string(T value, int size, uvm_radix_enum radix=UVM_NORADIX, string radix_str=""); if (radix == UVM_DEC && value[size-1] === 1) begin return $sformatf("%0d", value); end if($isunknown(value)) begin T _t; _t=0; for(int idx=0;idx 1) begin byte char; char = val_str.getc(0); if (char == "-") begin is_negative = 1; tmp = val_str.substr(1, val_str.len()-1); end else if (char == "+") begin tmp = val_str.substr(1, val_str.len()-1); end else begin tmp = val_str; end end else begin tmp = val_str; end if(tmp.len() > 2) begin base = tmp.substr(0,1); extval = tmp.substr(2,tmp.len()-1); case(base) "'b" : begin success= $sscanf(extval,"%b", val); end "0b" : begin success= $sscanf(extval,"%b", val); end "'o" : begin success= $sscanf(extval,"%o", val); end "'d" : begin success= $sscanf(extval,"%d", val); end "'h" : begin success= $sscanf(extval,"%x", val); end "'x" : begin success= $sscanf(extval,"%x", val); end "0x" : begin success= $sscanf(extval,"%x", val); end default : begin success = $sscanf(val_str,"%d", val); end endcase end else begin success = $sscanf(tmp,"%d", val); end if ((success == 1) && (is_negative)) begin val = -val; end return success; endfunction : from_string endclass : uvm_bit_vector_utils function string uvm_bitstream_to_string (uvm_bitstream_t value, int size, uvm_radix_enum radix=UVM_NORADIX, string radix_str=""); return uvm_bit_vector_utils#(uvm_bitstream_t)::to_string(value,size,radix,radix_str); endfunction function string uvm_integral_to_string (uvm_integral_t value, int size, uvm_radix_enum radix=UVM_NORADIX, string radix_str=""); return uvm_bit_vector_utils#(uvm_integral_t)::to_string(value, size, radix, radix_str); endfunction function int uvm_get_array_index_int(string arg, output bit is_wildcard); int i; int rt_val; uvm_get_array_index_int = 0; is_wildcard = 1; i = arg.len() - 1; if(arg[i] == "]") begin while(i > 0 && (arg[i] != "[")) begin --i; if((arg[i] == "*") || (arg[i] == "?")) begin i=0; end else if((arg[i] < "0") || (arg[i] > "9") && (arg[i] != "[")) begin uvm_get_array_index_int = -1; i=0; end end end else begin is_wildcard = 0; return 0; end if(i>0) begin arg = arg.substr(i+1, arg.len()-2); rt_val = $sscanf(arg, "%d" ,uvm_get_array_index_int ); is_wildcard = 0; end endfunction function string uvm_get_array_index_string(string arg, output bit is_wildcard); int i; uvm_get_array_index_string = ""; is_wildcard = 1; i = arg.len() - 1; if(arg[i] == "]") begin while(i > 0 && (arg[i] != "[")) begin if((arg[i] == "*") || (arg[i] == "?")) begin i=0; end --i; end end if(i>0) begin uvm_get_array_index_string = arg.substr(i+1, arg.len()-2); is_wildcard = 0; end endfunction function bit uvm_is_array(string arg); return arg[arg.len()-1] == "]"; endfunction function automatic bit uvm_has_wildcard (string arg); uvm_has_wildcard = 0; if( (arg.len() > 1) && (arg[0] == "/") && (arg[arg.len()-1] == "/") ) begin return 1; end foreach(arg[i]) begin if( (arg[i] == "*") || (arg[i] == "+") || (arg[i] == "?") ) begin uvm_has_wildcard = 1; end end endfunction typedef class uvm_component; typedef class uvm_root; typedef class uvm_report_object; class uvm_utils #(type TYPE=int, string FIELD="config"); typedef TYPE types_t[$]; static function types_t find_all(uvm_component start); uvm_component list[$]; types_t types; uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); top.find_all("*",list,start); foreach (list[i]) begin TYPE typ; if ($cast(typ,list[i])) begin types.push_back(typ); end end if (types.size() == 0) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "find_type-no match") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "find_type-no match") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("find_type-no match", {"Instance of type '",TYPE::type_name, " not found in component hierarchy beginning at ",start.get_full_name()}, uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_misc.svh", 636, "", 1); end end end return types; endfunction static function TYPE find(uvm_component start); types_t types = find_all(start); if (types.size() == 0) begin return null; end if (types.size() > 1) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "find_type-multi match") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "find_type-multi match") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("find_type-multi match", {"More than one instance of type '",TYPE::type_name, " found in component hierarchy beginning at ",start.get_full_name()}, uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_misc.svh", 650, "", 1); end end return null; end return types[0]; endfunction static function TYPE create_type_by_name(string type_name, string contxt); uvm_object obj; TYPE typ; uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); obj = factory.create_object_by_name(type_name,contxt,type_name); if (!$cast(typ,obj)) begin uvm_report_error("WRONG_TYPE",{"The type_name given '",type_name, "' with context '",contxt,"' did not produce the expected type."}); end return typ; endfunction static function TYPE get_config(uvm_component comp, bit is_fatal); uvm_object obj; TYPE cfg; if (!m_uvm_config_obj_misc::get(comp,"",FIELD, obj)) begin if (is_fatal) begin comp.uvm_report_fatal("NO_SET_CFG", {"no set_config to field '", FIELD, "' for component '",comp.get_full_name(),"'"}, UVM_MEDIUM, "t/uvm/src/base/uvm_misc.svh" , 689 ); end else begin comp.uvm_report_warning("NO_SET_CFG", {"no set_config to field '", FIELD, "' for component '",comp.get_full_name(),"'"}, UVM_MEDIUM, "t/uvm/src/base/uvm_misc.svh" , 696 ); end return null; end if (!$cast(cfg, obj)) begin if (is_fatal) begin comp.uvm_report_fatal( "GET_CFG_TYPE_FAIL", {"set_config_object with field name ",FIELD, " is not of type '",TYPE::type_name,"'"}, UVM_NONE , "t/uvm/src/base/uvm_misc.svh" , 708 ); end else begin comp.uvm_report_warning( "GET_CFG_TYPE_FAIL", {"set_config_object with field name ",FIELD, " is not of type '",TYPE::type_name,"'"}, UVM_NONE , "t/uvm/src/base/uvm_misc.svh" , 716 ); end end return cfg; endfunction endclass function automatic string m_uvm_string_queue_join(ref string i[$]); m_uvm_string_queue_join = {>>{i}}; endfunction typedef class uvm_factory; typedef class uvm_default_factory; typedef class uvm_report_server; typedef class uvm_default_report_server; typedef class uvm_root; typedef class uvm_visitor; typedef class uvm_component_name_check_visitor; typedef class uvm_component; typedef class uvm_comparer; typedef class uvm_copier; typedef class uvm_packer; typedef class uvm_printer; typedef class uvm_table_printer; typedef class uvm_phase_hopper; typedef class uvm_tr_database; typedef class uvm_text_tr_database; typedef class uvm_resource_pool; typedef class uvm_resource_base; typedef class uvm_default_coreservice_t; virtual class uvm_coreservice_t extends uvm_void; pure virtual function uvm_factory get_factory(); pure virtual function void set_factory(uvm_factory f); pure virtual function uvm_report_server get_report_server(); pure virtual function void set_report_server(uvm_report_server server); pure virtual function uvm_tr_database get_default_tr_database(); pure virtual function void set_default_tr_database(uvm_tr_database db); pure virtual function void set_component_visitor(uvm_visitor#(uvm_component) v); pure virtual function uvm_visitor#(uvm_component) get_component_visitor(); pure virtual function uvm_root get_root(); pure virtual function void set_phase_max_ready_to_end(int max); pure virtual function int get_phase_max_ready_to_end(); pure virtual function void set_default_printer(uvm_printer printer); pure virtual function uvm_printer get_default_printer(); pure virtual function void set_default_packer(uvm_packer packer); pure virtual function uvm_packer get_default_packer(); pure virtual function void set_default_comparer(uvm_comparer comparer); pure virtual function uvm_comparer get_default_comparer(); pure virtual function int unsigned get_global_seed(); pure virtual function void set_default_copier(uvm_copier copier); pure virtual function uvm_copier get_default_copier(); pure virtual function bit get_uvm_seeding(); pure virtual function void set_uvm_seeding(bit enable); pure virtual function void set_resource_pool (uvm_resource_pool pool); pure virtual function uvm_resource_pool get_resource_pool(); pure virtual function void set_resource_pool_default_precedence(int unsigned precedence); pure virtual function int unsigned get_resource_pool_default_precedence(); pure virtual function uvm_phase_hopper get_phase_hopper(); local static uvm_coreservice_t inst; static function uvm_coreservice_t get(); if(inst==null) begin uvm_init(null); end return inst; endfunction static function void set(uvm_coreservice_t cs); inst=cs; endfunction endclass class uvm_default_coreservice_t extends uvm_coreservice_t; local uvm_factory factory; virtual function uvm_factory get_factory(); if(factory==null) begin uvm_default_factory f; f=new; factory=f; end return factory; endfunction virtual function void set_factory(uvm_factory f); factory = f; endfunction local uvm_tr_database tr_database; virtual function uvm_tr_database get_default_tr_database(); if (tr_database == null) begin process p = process::self(); uvm_text_tr_database tx_db; string s; if(p != null) begin s = p.get_randstate(); end tx_db = new("default_tr_database"); tr_database = tx_db; if(p != null) begin p.set_randstate(s); end end return tr_database; endfunction : get_default_tr_database virtual function void set_default_tr_database(uvm_tr_database db); tr_database = db; endfunction : set_default_tr_database local uvm_report_server report_server; virtual function uvm_report_server get_report_server(); if(report_server==null) begin uvm_default_report_server f; f=new; report_server=f; end return report_server; endfunction virtual function void set_report_server(uvm_report_server server); report_server=server; endfunction virtual function uvm_root get_root(); return uvm_root::m_uvm_get_root(); endfunction local uvm_visitor#(uvm_component) _visitor; virtual function void set_component_visitor(uvm_visitor#(uvm_component) v); _visitor=v; endfunction virtual function uvm_visitor#(uvm_component) get_component_visitor(); if(_visitor==null) begin uvm_component_name_check_visitor v = new("name-check-visitor"); _visitor=v; end return _visitor; endfunction virtual function void set_default_printer(uvm_printer printer); uvm_default_printer = printer ; endfunction virtual function uvm_printer get_default_printer(); if (uvm_default_printer == null) begin uvm_default_printer = uvm_table_printer::get_default() ; end return uvm_default_printer ; endfunction virtual function void set_default_packer(uvm_packer packer); uvm_default_packer = packer ; endfunction virtual function uvm_packer get_default_packer(); if (uvm_default_packer == null) begin uvm_default_packer = new("uvm_default_packer") ; end return uvm_default_packer ; endfunction virtual function void set_default_comparer(uvm_comparer comparer); uvm_default_comparer = comparer ; endfunction virtual function uvm_comparer get_default_comparer(); if (uvm_default_comparer == null) begin uvm_default_comparer = new("uvm_default_comparer") ; end return uvm_default_comparer ; endfunction local int m_default_max_ready_to_end_iters = 20; virtual function void set_phase_max_ready_to_end(int max); m_default_max_ready_to_end_iters = max; endfunction virtual function int get_phase_max_ready_to_end(); return m_default_max_ready_to_end_iters; endfunction local uvm_resource_pool m_rp ; virtual function void set_resource_pool (uvm_resource_pool pool); m_rp = pool; endfunction virtual function uvm_resource_pool get_resource_pool(); if(m_rp == null) begin m_rp = new(); end return m_rp; endfunction virtual function void set_resource_pool_default_precedence(int unsigned precedence); uvm_resource_base::default_precedence = precedence; endfunction virtual function int unsigned get_resource_pool_default_precedence(); return uvm_resource_base::default_precedence; endfunction local uvm_phase_hopper m_hopper; virtual function uvm_phase_hopper get_phase_hopper(); if (m_hopper == null) begin m_hopper = uvm_phase_hopper::type_id::create("default_hopper"); end return m_hopper; endfunction local int unsigned m_uvm_global_seed = $urandom; virtual function int unsigned get_global_seed(); return m_uvm_global_seed; endfunction virtual function bit get_uvm_seeding(); return uvm_object::use_uvm_seeding; endfunction : get_uvm_seeding virtual function void set_uvm_seeding(bit enable); uvm_object::use_uvm_seeding = enable; endfunction : set_uvm_seeding local uvm_copier m_copier ; virtual function void set_default_copier(uvm_copier copier); m_copier = copier ; endfunction virtual function uvm_copier get_default_copier(); if (m_copier == null) begin m_copier = new("uvm_default_copier") ; end return m_copier ; endfunction endclass typedef class uvm_root; typedef class uvm_report_object; typedef class uvm_report_message; task run_test (string test_name=""); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); top.run_test(test_name); endtask function uvm_report_object uvm_get_report_object(); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); return top; endfunction function int uvm_report_enabled (int verbosity, uvm_severity severity=UVM_INFO, string id=""); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); return top.uvm_report_enabled(verbosity,severity,id); endfunction function void uvm_report( uvm_severity severity, string id, string message, int verbosity = (severity == uvm_severity'(UVM_ERROR)) ? UVM_LOW : (severity == uvm_severity'(UVM_FATAL)) ? UVM_NONE : UVM_MEDIUM, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); top.uvm_report(severity, id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction export "DPI-C" function m__uvm_report_dpi; function void m__uvm_report_dpi(int severity, string id, string message, int verbosity, string filename, int line); uvm_report(uvm_severity'(severity), id, message, verbosity, filename, line); endfunction : m__uvm_report_dpi function void uvm_report_info(string id, string message, int verbosity = UVM_MEDIUM, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); top.uvm_report_info(id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction function void uvm_report_warning(string id, string message, int verbosity = UVM_MEDIUM, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); top.uvm_report_warning(id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction function void uvm_report_error(string id, string message, int verbosity = UVM_NONE, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); top.uvm_report_error(id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction function void uvm_report_fatal(string id, string message, int verbosity = UVM_NONE, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); top.uvm_report_fatal(id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction function void uvm_process_report_message(uvm_report_message report_message); uvm_root top; uvm_coreservice_t cs; process p; p = process::self(); cs = uvm_coreservice_t::get(); top = cs.get_root(); top.uvm_process_report_message(report_message); endfunction function bit uvm_string_to_severity (string sev_str, output uvm_severity sev); case (sev_str) "UVM_INFO": begin sev = UVM_INFO; end "UVM_WARNING": begin sev = UVM_WARNING; end "UVM_ERROR": begin sev = UVM_ERROR; end "UVM_FATAL": begin sev = UVM_FATAL; end default: begin return 0; end endcase return 1; endfunction function automatic bit uvm_string_to_action (string action_str, output uvm_action action); string actions[$]; uvm_string_split(action_str,"|",actions); uvm_string_to_action = 1; action = 0; foreach(actions[i]) begin case (actions[i]) "UVM_NO_ACTION": begin action |= UVM_NO_ACTION; end "UVM_DISPLAY": begin action |= UVM_DISPLAY; end "UVM_LOG": begin action |= UVM_LOG; end "UVM_COUNT": begin action |= UVM_COUNT; end "UVM_EXIT": begin action |= UVM_EXIT; end "UVM_CALL_HOOK": begin action |= UVM_CALL_HOOK; end "UVM_STOP": begin action |= UVM_STOP; end "UVM_RM_RECORD": begin action |= UVM_RM_RECORD; end default: begin uvm_string_to_action = 0; end endcase end endfunction function automatic bit uvm_string_to_verbosity(string verb_str, output uvm_verbosity verb_enum); case (verb_str) "NONE" : begin verb_enum = UVM_NONE; return 1; end "UVM_NONE" : begin verb_enum = UVM_NONE; return 1; end "LOW" : begin verb_enum = UVM_LOW; return 1; end "UVM_LOW" : begin verb_enum = UVM_LOW; return 1; end "MEDIUM" : begin verb_enum = UVM_MEDIUM; return 1; end "UVM_MEDIUM" : begin verb_enum = UVM_MEDIUM; return 1; end "HIGH" : begin verb_enum = UVM_HIGH; return 1; end "UVM_HIGH" : begin verb_enum = UVM_HIGH; return 1; end "FULL" : begin verb_enum = UVM_FULL; return 1; end "UVM_FULL" : begin verb_enum = UVM_FULL; return 1; end "DEBUG" : begin verb_enum = UVM_DEBUG; return 1; end "UVM_DEBUG" : begin verb_enum = UVM_DEBUG; return 1; end default : begin return 0; end endcase endfunction function bit uvm_is_match (string expr, string str); return (uvm_re_match(.re(expr), .str(str), .deglob(1)) == 0); endfunction parameter UVM_LINE_WIDTH = 120; parameter UVM_NUM_LINES = 120; parameter UVM_SMALL_STRING = UVM_LINE_WIDTH*8-1; parameter UVM_LARGE_STRING = UVM_LINE_WIDTH*UVM_NUM_LINES*8-1; function logic[UVM_LARGE_STRING:0] uvm_string_to_bits(string str); $swrite(uvm_string_to_bits, "%0s", str); endfunction function uvm_core_state get_core_state(); if (m_uvm_core_state.size() == 0) begin return UVM_CORE_UNINITIALIZED; end else begin return m_uvm_core_state[0]; end endfunction function void uvm_init(uvm_coreservice_t cs=null); uvm_default_coreservice_t dcs; if(get_core_state()!=UVM_CORE_UNINITIALIZED) begin if (get_core_state() == UVM_CORE_PRE_INIT) begin dcs = new(); uvm_coreservice_t::set(dcs); begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "UVM/INIT/MULTI") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "UVM/INIT/MULTI") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("UVM/INIT/MULTI", "Non-recoverable race during uvm_init", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_globals.svh", 411, "", 1); end end end else begin uvm_coreservice_t actual; actual = uvm_coreservice_t::get(); if ((cs != actual) && (cs != null)) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "UVM/INIT/MULTI") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "UVM/INIT/MULTI") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("UVM/INIT/MULTI", "uvm_init() called after library has already completed initialization, subsequent calls are ignored!", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_globals.svh", 420, "", 1); end end end end return; end m_uvm_core_state.push_front(UVM_CORE_PRE_INIT); if(cs == null) begin dcs = new(); cs = dcs; end uvm_coreservice_t::set(cs); m_uvm_core_state.push_front(UVM_CORE_INITIALIZING); foreach(uvm_deferred_init[idx]) begin uvm_deferred_init[idx].initialize(); end uvm_deferred_init.delete(); begin uvm_root top; top = uvm_root::get(); top.report_header(); top.m_check_uvm_field_flag_size(); top.m_check_verbosity(); end m_uvm_core_state.push_front(UVM_CORE_INITIALIZED); uvm_default_table_printer = new(); uvm_default_tree_printer = new(); uvm_default_line_printer = new(); uvm_default_printer = uvm_default_table_printer; uvm_default_packer = new(); uvm_default_comparer = new(); endfunction function string uvm_bits_to_string(logic [UVM_LARGE_STRING:0] str); $swrite(uvm_bits_to_string, "%0s", str); endfunction task uvm_wait_for_nba_region; static int nba; static int next_nba; next_nba++; nba <= next_nba; @(nba); endtask function automatic void uvm_split_string (string str, byte sep, ref string values[$]); int s = 0, e = 0; values.delete(); while(e < str.len()) begin for(s=e; e"; endfunction virtual function uvm_object create (string name=""); return null; endfunction extern virtual function uvm_object clone (); extern function void print (uvm_printer printer=null); extern function string sprint (uvm_printer printer=null); extern virtual function void do_print (uvm_printer printer); extern virtual function string convert2string(); extern function void record (uvm_recorder recorder=null); extern virtual function void do_record (uvm_recorder recorder); extern function void copy (uvm_object rhs, uvm_copier copier=null); extern virtual function void do_copy (uvm_object rhs); extern function bit compare (uvm_object rhs, uvm_comparer comparer=null); extern virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); extern function int pack (ref bit bitstream[], input uvm_packer packer=null); extern function int pack_bytes (ref byte unsigned bytestream[], input uvm_packer packer=null); extern function int pack_ints (ref int unsigned intstream[], input uvm_packer packer=null); extern function int pack_longints (ref longint unsigned longintstream[], input uvm_packer packer=null); extern virtual function void do_pack (uvm_packer packer); extern function int unpack (ref bit bitstream[], input uvm_packer packer=null); extern function int unpack_bytes (ref byte unsigned bytestream[], input uvm_packer packer=null); extern function int unpack_ints (ref int unsigned intstream[], input uvm_packer packer=null); extern function int unpack_longints (ref longint unsigned longintstream[], input uvm_packer packer=null); extern virtual function void do_unpack (uvm_packer packer); extern virtual function void do_execute_op ( uvm_field_op op); extern virtual function void set_local(uvm_resource_base rsrc) ; extern local function void m_pack (inout uvm_packer packer); extern local function void m_unpack_pre (inout uvm_packer packer); extern local function int m_unpack_post (uvm_packer packer); extern virtual function void m_unsupported_set_local(uvm_resource_base rsrc); local string m_leaf_name; local int m_inst_id; static protected int m_inst_count; extern virtual function void __m_uvm_field_automation (uvm_object tmp_data__, uvm_field_flag_t what__, string str__); extern protected virtual function uvm_report_object m_get_report_object(); extern virtual function void set_int_local (string field_name, uvm_bitstream_t value, bit recurse=1); extern virtual function void set_string_local (string field_name, string value, bit recurse=1); extern virtual function void set_object_local (string field_name, uvm_object value, bit clone=1, bit recurse=1); endclass function uvm_object::new (string name=""); m_inst_id = m_inst_count++; m_leaf_name = name; endfunction function bit uvm_object::get_uvm_seeding(); uvm_coreservice_t cs = uvm_coreservice_t::get(); return cs.get_uvm_seeding(); endfunction function void uvm_object::set_uvm_seeding(bit enable); uvm_coreservice_t cs = uvm_coreservice_t::get(); cs.set_uvm_seeding(enable); endfunction function void uvm_object::reseed (); if(get_uvm_seeding()) begin this.srandom(uvm_create_random_seed(get_type_name(), get_full_name())); end endfunction function uvm_object_wrapper uvm_object::get_type(); uvm_report_error("NOTYPID", "get_type not implemented in derived class.", UVM_NONE); return null; endfunction function int uvm_object::get_inst_id(); return m_inst_id; endfunction function uvm_object_wrapper uvm_object::get_object_type(); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); if(get_type_name() == "") begin return null; end return factory.find_wrapper_by_name(get_type_name()); endfunction function int uvm_object::get_inst_count(); return m_inst_count; endfunction function string uvm_object::get_name (); return m_leaf_name; endfunction function string uvm_object::get_full_name (); return get_name(); endfunction function void uvm_object::set_name (string name); m_leaf_name = name; endfunction function void uvm_object::print(uvm_printer printer=null); if (printer==null) begin printer = uvm_printer::get_default(); end $fwrite(printer.get_file(),sprint(printer)); endfunction function string uvm_object::sprint(uvm_printer printer=null); string name; if(printer==null) begin printer = uvm_printer::get_default(); end if (printer.get_active_object_depth() == 0) begin printer.flush() ; name = printer.get_root_enabled() ? get_full_name() : get_name(); end else begin name = get_name(); end printer.print_object(name,this); return printer.emit(); endfunction function string uvm_object::convert2string(); return ""; endfunction function void uvm_object::set_local(uvm_resource_base rsrc) ; if(rsrc==null) begin return ; end else begin begin uvm_field_op op; op = uvm_field_op::m_get_available_op(); op.set(UVM_SET,null,rsrc); this.do_execute_op(op); op.m_recycle(); end end endfunction function void uvm_object::m_unsupported_set_local(uvm_resource_base rsrc); return; endfunction function uvm_object uvm_object::clone(); uvm_object tmp; tmp = this.create(get_name()); if(tmp == null) begin uvm_report_warning("CRFLD", $sformatf("The create method failed for %s, object cannot be cloned", get_name()), UVM_NONE); end else begin tmp.copy(this); end return(tmp); endfunction function void uvm_object::copy (uvm_object rhs, uvm_copier copier=null); uvm_coreservice_t coreservice ; uvm_copier m_copier; if(rhs == null) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "OBJ/COPY") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "OBJ/COPY") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("OBJ/COPY", "Passing a null object to be copied", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_object.svh", 986, "", 1); end end return; end if(copier == null) begin coreservice = uvm_coreservice_t::get() ; m_copier = coreservice.get_default_copier() ; end else begin m_copier = copier; end if(m_copier.get_active_object_depth() == 0) begin m_copier.flush(); end m_copier.copy_object(this,rhs); endfunction function void uvm_object::do_copy (uvm_object rhs); return; endfunction function bit uvm_object::compare (uvm_object rhs, uvm_comparer comparer=null); if (comparer == null) begin comparer = uvm_comparer::get_default(); end if (comparer.get_active_object_depth() == 0) begin comparer.flush() ; end compare = comparer.compare_object(get_name(),this,rhs); endfunction function bit uvm_object::do_compare (uvm_object rhs, uvm_comparer comparer); return 1; endfunction function void uvm_object::__m_uvm_field_automation (uvm_object tmp_data__, uvm_field_flag_t what__, string str__ ); return; endfunction function void uvm_object::do_print(uvm_printer printer); return; endfunction function void uvm_object::m_pack (inout uvm_packer packer); if (packer == null) begin packer = uvm_packer::get_default(); end if(packer.get_active_object_depth() == 0) begin packer.flush(); end packer.pack_object(this); endfunction function int uvm_object::pack (ref bit bitstream [], input uvm_packer packer =null ); m_pack(packer); packer.get_packed_bits(bitstream); return packer.get_packed_size(); endfunction function int uvm_object::pack_bytes (ref byte unsigned bytestream [], input uvm_packer packer=null ); m_pack(packer); packer.get_packed_bytes(bytestream); return packer.get_packed_size(); endfunction function int uvm_object::pack_ints (ref int unsigned intstream [], input uvm_packer packer=null ); m_pack(packer); packer.get_packed_ints(intstream); return packer.get_packed_size(); endfunction function int uvm_object::pack_longints (ref longint unsigned longintstream [], input uvm_packer packer=null ); m_pack(packer); packer.get_packed_longints(longintstream); return packer.get_packed_size(); endfunction function void uvm_object::do_pack (uvm_packer packer ); if (packer == null) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM/OBJ/PACK/NULL") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM/OBJ/PACK/NULL") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM/OBJ/PACK/NULL", "uvm_object::do_pack called with null packer!", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_object.svh", 1131, "", 1); end end end return; endfunction function void uvm_object::m_unpack_pre (inout uvm_packer packer); if (packer == null) begin packer = uvm_packer::get_default(); end if(packer.get_active_object_depth() == 0) begin packer.flush(); end endfunction function int uvm_object::m_unpack_post (uvm_packer packer); int size_before_unpack = packer.get_packed_size(); packer.unpack_object(this); return size_before_unpack - packer.get_packed_size(); endfunction function int uvm_object::unpack (ref bit bitstream [], input uvm_packer packer=null); m_unpack_pre(packer); packer.set_packed_bits(bitstream); return m_unpack_post(packer); endfunction function int uvm_object::unpack_bytes (ref byte unsigned bytestream [], input uvm_packer packer=null); m_unpack_pre(packer); packer.set_packed_bytes(bytestream); return m_unpack_post(packer); endfunction function int uvm_object::unpack_ints (ref int unsigned intstream [], input uvm_packer packer=null); m_unpack_pre(packer); packer.set_packed_ints(intstream); return m_unpack_post(packer); endfunction function int uvm_object::unpack_longints (ref longint unsigned longintstream [], input uvm_packer packer=null); m_unpack_pre(packer); packer.set_packed_longints(longintstream); return m_unpack_post(packer); endfunction function void uvm_object::do_execute_op ( uvm_field_op op); endfunction function void uvm_object::do_unpack (uvm_packer packer); if (packer == null) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM/OBJ/UNPACK/NULL") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM/OBJ/UNPACK/NULL") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM/OBJ/UNPACK/NULL", "uvm_object::do_unpack called with null packer!", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_object.svh", 1218, "", 1); end end end return; endfunction function void uvm_object::record (uvm_recorder recorder=null); if(recorder == null) begin return; end recorder.record_object(get_name(), this); endfunction function void uvm_object::do_record (uvm_recorder recorder); return; endfunction function uvm_report_object uvm_object::m_get_report_object(); return null; endfunction uvm_resource_base m_set_local_rsrc; function void uvm_object::set_int_local (string field_name, uvm_bitstream_t value, bit recurse=1); uvm_field_op field_op = uvm_field_op::m_get_available_op(); uvm_resource_base rsrc_base = m_set_local_rsrc; if (rsrc_base == null) begin uvm_resource#(uvm_bitstream_t) rsrc = new(field_name); rsrc.write(value); rsrc_base = rsrc; end field_op.set(UVM_SET, null, rsrc_base); do_execute_op(field_op); field_op.m_recycle(); m_set_local_rsrc = null; endfunction function void uvm_object::set_object_local (string field_name, uvm_object value, bit clone=1, bit recurse=1); uvm_field_op field_op = uvm_field_op::m_get_available_op(); uvm_resource_base rsrc_base = m_set_local_rsrc; if (rsrc_base == null) begin uvm_resource#(uvm_object) rsrc = new(field_name); if (clone && (value != null)) begin uvm_object cc = value.clone(); if (cc != null) begin cc.set_name(field_name); end rsrc.write(cc); end else begin rsrc.write(value); end rsrc_base = rsrc; end field_op.set(UVM_SET, null, rsrc_base); do_execute_op(field_op); field_op.m_recycle(); m_set_local_rsrc = null; endfunction function void uvm_object::set_string_local (string field_name, string value, bit recurse=1); uvm_field_op field_op = uvm_field_op::m_get_available_op(); uvm_resource_base rsrc_base = m_set_local_rsrc; if (rsrc_base == null) begin uvm_resource#(string) rsrc = new(field_name); rsrc.write(value); rsrc_base = rsrc; end field_op.set(UVM_SET, null, rsrc_base); do_execute_op(field_op); field_op.m_recycle(); m_set_local_rsrc = null; endfunction typedef class uvm_object; typedef class uvm_component; typedef class uvm_object_wrapper; typedef class uvm_factory_override; typedef struct {uvm_object_wrapper m_type; string m_type_name;} m_uvm_factory_type_pair_t; class uvm_factory_queue_class; uvm_factory_override queue[$]; endclass virtual class uvm_factory extends uvm_void; static function uvm_factory get(); uvm_coreservice_t s; s = uvm_coreservice_t::get(); return s.get_factory(); endfunction static function void set(uvm_factory f); uvm_coreservice_t s; s = uvm_coreservice_t::get(); s.set_factory(f); endfunction pure virtual function void register (uvm_object_wrapper obj); pure virtual function void set_inst_override_by_type (uvm_object_wrapper original_type, uvm_object_wrapper override_type, string full_inst_path); pure virtual function void set_inst_override_by_name (string original_type_name, string override_type_name, string full_inst_path); pure virtual function void set_type_override_by_type (uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace=1); pure virtual function void set_type_override_by_name (string original_type_name, string override_type_name, bit replace=1); pure virtual function uvm_object create_object_by_type (uvm_object_wrapper requested_type, string parent_inst_path="", string name=""); pure virtual function uvm_component create_component_by_type (uvm_object_wrapper requested_type, string parent_inst_path="", string name, uvm_component parent); pure virtual function uvm_object create_object_by_name (string requested_type_name, string parent_inst_path="", string name=""); pure virtual function bit is_type_name_registered (string type_name); pure virtual function bit is_type_registered (uvm_object_wrapper obj); pure virtual function uvm_component create_component_by_name (string requested_type_name, string parent_inst_path="", string name, uvm_component parent); pure virtual function void set_type_alias(string alias_type_name, uvm_object_wrapper original_type); pure virtual function void set_inst_alias(string alias_type_name, uvm_object_wrapper original_type, string full_inst_path); pure virtual function void debug_create_by_type (uvm_object_wrapper requested_type, string parent_inst_path="", string name=""); pure virtual function void debug_create_by_name (string requested_type_name, string parent_inst_path="", string name=""); pure virtual function uvm_object_wrapper find_override_by_type (uvm_object_wrapper requested_type, string full_inst_path); pure virtual function uvm_object_wrapper find_override_by_name (string requested_type_name, string full_inst_path); pure virtual function uvm_object_wrapper find_wrapper_by_name (string type_name); pure virtual function void print (int all_types=1); endclass class uvm_default_factory extends uvm_factory; extern virtual function void register (uvm_object_wrapper obj); extern virtual function void set_inst_override_by_type (uvm_object_wrapper original_type, uvm_object_wrapper override_type, string full_inst_path); extern virtual function void set_inst_override_by_name (string original_type_name, string override_type_name, string full_inst_path); extern virtual function void set_type_override_by_type (uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace=1); extern virtual function void set_type_override_by_name (string original_type_name, string override_type_name, bit replace=1); extern virtual function void set_type_alias(string alias_type_name, uvm_object_wrapper original_type); extern virtual function void set_inst_alias(string alias_type_name, uvm_object_wrapper original_type, string full_inst_path); extern virtual function uvm_object create_object_by_type (uvm_object_wrapper requested_type, string parent_inst_path="", string name=""); extern virtual function uvm_component create_component_by_type (uvm_object_wrapper requested_type, string parent_inst_path="", string name, uvm_component parent); extern virtual function uvm_object create_object_by_name (string requested_type_name, string parent_inst_path="", string name=""); extern virtual function uvm_component create_component_by_name (string requested_type_name, string parent_inst_path="", string name, uvm_component parent); extern virtual function bit is_type_name_registered (string type_name); extern virtual function bit is_type_registered (uvm_object_wrapper obj); extern virtual function void debug_create_by_type (uvm_object_wrapper requested_type, string parent_inst_path="", string name=""); extern virtual function void debug_create_by_name (string requested_type_name, string parent_inst_path="", string name=""); extern virtual function uvm_object_wrapper find_override_by_type (uvm_object_wrapper requested_type, string full_inst_path); extern function uvm_object_wrapper m_find_override_by_type (uvm_object_wrapper requested_type, string full_inst_path, ref uvm_factory_override override_info[$]); extern virtual function uvm_object_wrapper find_override_by_name (string requested_type_name, string full_inst_path); extern virtual function uvm_object_wrapper find_wrapper_by_name (string type_name); extern virtual function void print (int all_types=1); extern protected function void m_debug_create (string requested_type_name, uvm_object_wrapper requested_type, string parent_inst_path, string name); extern protected function void m_debug_display(string requested_type_name, uvm_object_wrapper result, string full_inst_path); extern function uvm_object_wrapper m_resolve_type_name(string requested_type_name); extern function uvm_object_wrapper m_resolve_type_name_by_inst(string requested_type_name, string full_inst_path); extern function bit m_matches_type_pair(m_uvm_factory_type_pair_t match_type_pair, uvm_object_wrapper requested_type, string requested_type_name); extern function bit m_matches_type_override(uvm_factory_override override, uvm_object_wrapper requested_type, string requested_type_name, string full_inst_path="", bit match_original_type = 1, bit resolve_null_type_by_inst=0); extern function bit m_matches_inst_override(uvm_factory_override override, uvm_object_wrapper requested_type, string requested_type_name, string full_inst_path=""); typedef struct { m_uvm_factory_type_pair_t orig; string alias_type_name; string full_inst_path; } m_inst_typename_alias_t; protected bit m_types[uvm_object_wrapper]; protected bit m_lookup_strs[string]; protected uvm_object_wrapper m_type_names[string]; protected m_inst_typename_alias_t m_inst_aliases[$]; protected uvm_factory_override m_type_overrides[$]; protected uvm_factory_override m_inst_overrides[$]; local uvm_factory_override m_override_info[$]; local static bit m_debug_pass; extern function bit check_inst_override_exists (uvm_object_wrapper original_type, string original_type_name, uvm_object_wrapper override_type, string override_type_name, string full_inst_path); endclass virtual class uvm_object_wrapper extends uvm_void; virtual function uvm_object create_object (string name=""); return null; endfunction virtual function uvm_component create_component (string name, uvm_component parent); return null; endfunction pure virtual function string get_type_name(); virtual function void initialize(); endfunction endclass class uvm_factory_override; string full_inst_path; m_uvm_factory_type_pair_t orig; m_uvm_factory_type_pair_t ovrd; bit replace; bit selected; int unsigned used; bit has_wildcard; function new (string full_inst_path="", string orig_type_name="", uvm_object_wrapper orig_type=null, uvm_object_wrapper ovrd_type, string ovrd_type_name="", bit replace=0); this.full_inst_path= full_inst_path; this.orig.m_type_name = orig_type_name; this.orig.m_type = orig_type; this.ovrd.m_type_name = ovrd_type_name; this.ovrd.m_type = ovrd_type; this.replace = replace; this.has_wildcard = m_has_wildcard(full_inst_path); endfunction function bit m_has_wildcard(string nm); foreach (nm[i]) begin if(nm[i] == "*" || nm[i] == "?") begin return 1; end end return 0; endfunction endclass function void uvm_default_factory::register (uvm_object_wrapper obj); if (obj == null) begin uvm_report_fatal ("NULLWR", "Attempting to register a null object with the factory", UVM_NONE); end if (obj.get_type_name() != "" && obj.get_type_name() != "") begin if (m_type_names.exists(obj.get_type_name())) begin uvm_report_warning("TPRGED", {"Type name '",obj.get_type_name(), "' already registered with factory. No string-based lookup ", "support for multiple types with the same type name."}, UVM_NONE); end else begin m_type_names[obj.get_type_name()] = obj; end end if (m_types.exists(obj)) begin if (obj.get_type_name() != "" && obj.get_type_name() != "") begin uvm_report_warning("TPRGED", {"Object type '",obj.get_type_name(), "' already registered with factory. "}, UVM_NONE); end end else begin uvm_factory_override overrides[$]; m_types[obj] = 1; overrides = {m_type_overrides, m_inst_overrides}; foreach (overrides[index]) begin if(m_matches_type_pair(.match_type_pair(overrides[index].orig), .requested_type(null), .requested_type_name(obj.get_type_name()))) begin overrides[index].orig.m_type = obj; end if(m_matches_type_pair(.match_type_pair(overrides[index].ovrd), .requested_type(null), .requested_type_name(obj.get_type_name()))) begin overrides[index].ovrd.m_type = obj; end end end endfunction function void uvm_default_factory::set_type_override_by_type (uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace=1); bit replaced; if (original_type == override_type) begin if (original_type.get_type_name() == "" || original_type.get_type_name() == "") begin uvm_report_warning("TYPDUP", {"Original and override type ", "arguments are identical"}, UVM_NONE); end else begin uvm_report_warning("TYPDUP", {"Original and override type ", "arguments are identical: ", original_type.get_type_name()}, UVM_NONE); end end if (!m_types.exists(original_type)) begin register(original_type); end if (!m_types.exists(override_type)) begin register(override_type); end foreach (m_type_overrides[index]) begin if(m_matches_type_override(.override(m_type_overrides[index]), .requested_type(original_type), .requested_type_name(original_type.get_type_name()))) begin string msg; msg = {"Original object type '",original_type.get_type_name(), "' already registered to produce '", m_type_overrides[index].ovrd.m_type_name,"'"}; if (!replace) begin msg = {msg, ". Set 'replace' argument to replace the existing entry."}; uvm_report_info("TPREGD", msg, UVM_MEDIUM); return; end msg = {msg, ". Replacing with override to produce type '", override_type.get_type_name(),"'."}; uvm_report_info("TPREGR", msg, UVM_MEDIUM); replaced = 1; m_type_overrides[index].orig.m_type = original_type; m_type_overrides[index].orig.m_type_name = original_type.get_type_name(); m_type_overrides[index].ovrd.m_type = override_type; m_type_overrides[index].ovrd.m_type_name = override_type.get_type_name(); m_type_overrides[index].replace = replace; end else if (m_type_overrides[index].orig.m_type == null) begin break; end end if (!replaced) begin uvm_factory_override override; override = new(.orig_type(original_type), .orig_type_name(original_type.get_type_name()), .ovrd_type(override_type), .ovrd_type_name(override_type.get_type_name()), .replace(replace)); m_type_overrides.push_front(override); end endfunction function void uvm_default_factory::set_type_override_by_name (string original_type_name, string override_type_name, bit replace=1); bit replaced; uvm_object_wrapper original_type; uvm_object_wrapper override_type; if(m_type_names.exists(original_type_name)) begin original_type = m_type_names[original_type_name]; end if(m_type_names.exists(override_type_name)) begin override_type = m_type_names[override_type_name]; end if (original_type_name == override_type_name) begin uvm_report_warning("TYPDUP", {"Requested and actual type name ", " arguments are identical: ",original_type_name,". Ignoring this override."}, UVM_NONE); return; end foreach (m_type_overrides[index]) begin if(m_matches_type_override(.override(m_type_overrides[index]), .requested_type(original_type), .requested_type_name(original_type_name))) begin if (!replace) begin uvm_report_info("TPREGD", {"Original type '",original_type_name, "'/'",m_type_overrides[index].orig.m_type_name, "' already registered to produce '",m_type_overrides[index].ovrd.m_type_name, "'. Set 'replace' argument to replace the existing entry."}, UVM_MEDIUM); return; end uvm_report_info("TPREGR", {"Original object type '",original_type_name, "'/'",m_type_overrides[index].orig.m_type_name, "' already registered to produce '",m_type_overrides[index].ovrd.m_type_name, "'. Replacing with override to produce type '",override_type_name,"'."}, UVM_MEDIUM); replaced = 1; m_type_overrides[index].ovrd.m_type = override_type; m_type_overrides[index].ovrd.m_type_name = override_type_name; m_type_overrides[index].replace = replace; end else if ((m_type_overrides[index].orig.m_type == null) || (original_type == null)) begin break; end end if (original_type == null) begin m_lookup_strs[original_type_name] = 1; end if (!replaced) begin uvm_factory_override override; override = new(.orig_type(original_type), .orig_type_name(original_type_name), .ovrd_type(override_type), .ovrd_type_name(override_type_name), .replace(replace) ); m_type_overrides.push_front(override); end endfunction function bit uvm_default_factory::check_inst_override_exists (uvm_object_wrapper original_type, string original_type_name, uvm_object_wrapper override_type, string override_type_name, string full_inst_path); uvm_factory_override override; foreach (m_inst_overrides[i]) begin override = m_inst_overrides[i]; if (override.full_inst_path == full_inst_path && override.orig.m_type == original_type && override.orig.m_type_name == original_type_name && override.ovrd.m_type == override_type && override.ovrd.m_type_name == override_type_name) begin uvm_report_info("DUPOVRD",{"Instance override for '", original_type_name,"' already exists: override type '", override_type_name,"' with full_inst_path '", full_inst_path,"'"},UVM_HIGH); return 1; end end return 0; endfunction function void uvm_default_factory::set_inst_override_by_type (uvm_object_wrapper original_type, uvm_object_wrapper override_type, string full_inst_path); uvm_factory_override override; if (!m_types.exists(original_type)) begin register(original_type); end if (!m_types.exists(override_type)) begin register(override_type); end if (check_inst_override_exists(original_type, original_type.get_type_name(), override_type, override_type.get_type_name(), full_inst_path)) begin return; end override = new(.full_inst_path(full_inst_path), .orig_type(original_type), .orig_type_name(original_type.get_type_name()), .ovrd_type(override_type), .ovrd_type_name(override_type.get_type_name())); m_inst_overrides.push_back(override); endfunction function void uvm_default_factory::set_inst_override_by_name (string original_type_name, string override_type_name, string full_inst_path); uvm_factory_override override; uvm_object_wrapper original_type; uvm_object_wrapper override_type; if(m_type_names.exists(original_type_name)) begin original_type = m_type_names[original_type_name]; end if(m_type_names.exists(override_type_name)) begin override_type = m_type_names[override_type_name]; end if (original_type == null) begin m_lookup_strs[original_type_name] = 1; end override = new(.full_inst_path(full_inst_path), .orig_type(original_type), .orig_type_name(original_type_name), .ovrd_type(override_type), .ovrd_type_name(override_type_name)); if (check_inst_override_exists(original_type, original_type_name, override_type, override_type_name, full_inst_path)) begin return; end m_inst_overrides.push_back(override); endfunction function void uvm_default_factory::set_type_alias(string alias_type_name, uvm_object_wrapper original_type); if (!is_type_registered(original_type)) begin uvm_report_warning("BDTYP",{"Cannot define alias of type '", original_type.get_type_name(),"' because it is not registered with the factory."}, UVM_NONE); end else begin if (!m_type_names.exists(alias_type_name)) begin uvm_factory_override overrides[$]; m_type_names[alias_type_name] = original_type; overrides = {m_type_overrides, m_inst_overrides}; foreach (overrides[index]) begin if(m_matches_type_pair(.match_type_pair(overrides[index].orig), .requested_type(null), .requested_type_name(alias_type_name))) begin overrides[index].orig.m_type = original_type; end if(m_matches_type_pair(.match_type_pair(overrides[index].ovrd), .requested_type(null), .requested_type_name(alias_type_name))) begin overrides[index].ovrd.m_type = original_type; end end end end endfunction function void uvm_default_factory::set_inst_alias(string alias_type_name, uvm_object_wrapper original_type, string full_inst_path); string original_type_name; m_inst_typename_alias_t orig_type_alias_per_inst; original_type_name = original_type.get_type_name(); if (!is_type_registered(original_type)) begin uvm_report_warning("BDTYP",{"Cannot define alias of type '", original_type_name,"' because it is not registered with the factory."}, UVM_NONE); end else begin orig_type_alias_per_inst.alias_type_name = alias_type_name; orig_type_alias_per_inst.full_inst_path = full_inst_path; orig_type_alias_per_inst.orig.m_type_name = original_type_name; orig_type_alias_per_inst.orig.m_type = original_type; m_inst_aliases.push_back(orig_type_alias_per_inst); end endfunction function uvm_object uvm_default_factory::create_object_by_name (string requested_type_name, string parent_inst_path="", string name=""); uvm_object_wrapper wrapper; string inst_path; if (parent_inst_path == "") begin inst_path = name; end else if (name != "") begin inst_path = {parent_inst_path,".",name}; end else begin inst_path = parent_inst_path; end m_override_info.delete(); wrapper = find_override_by_name(requested_type_name, inst_path); if (wrapper==null) begin wrapper = m_resolve_type_name_by_inst(requested_type_name,inst_path); if(wrapper == null) begin uvm_report_warning("BDTYP",{"Cannot create an object of type '", requested_type_name,"' because it is not registered with the factory."}, UVM_NONE); return null; end end return wrapper.create_object(name); endfunction function uvm_object uvm_default_factory::create_object_by_type (uvm_object_wrapper requested_type, string parent_inst_path="", string name=""); string full_inst_path; if (parent_inst_path == "") begin full_inst_path = name; end else if (name != "") begin full_inst_path = {parent_inst_path,".",name}; end else begin full_inst_path = parent_inst_path; end requested_type = find_override_by_type(requested_type, full_inst_path); return requested_type.create_object(name); endfunction function bit uvm_default_factory::is_type_name_registered (string type_name); return (m_type_names.exists(type_name)); endfunction function bit uvm_default_factory::is_type_registered (uvm_object_wrapper obj); return (m_types.exists(obj)); endfunction function uvm_component uvm_default_factory::create_component_by_name (string requested_type_name, string parent_inst_path="", string name, uvm_component parent); uvm_object_wrapper wrapper; string inst_path; if (parent_inst_path == "") begin inst_path = name; end else if (name != "") begin inst_path = {parent_inst_path,".",name}; end else begin inst_path = parent_inst_path; end m_override_info.delete(); wrapper = find_override_by_name(requested_type_name, inst_path); if (wrapper == null) begin if(!m_type_names.exists(requested_type_name)) begin uvm_report_warning("BDTYP",{"Cannot create a component of type '", requested_type_name,"' because it is not registered with the factory."}, UVM_NONE); return null; end wrapper = m_type_names[requested_type_name]; end return wrapper.create_component(name, parent); endfunction function uvm_component uvm_default_factory::create_component_by_type (uvm_object_wrapper requested_type, string parent_inst_path="", string name, uvm_component parent); string full_inst_path; if (parent_inst_path == "") begin full_inst_path = name; end else if (name != "") begin full_inst_path = {parent_inst_path,".",name}; end else begin full_inst_path = parent_inst_path; end requested_type = find_override_by_type(requested_type, full_inst_path); return requested_type.create_component(name, parent); endfunction function uvm_object_wrapper uvm_default_factory::find_wrapper_by_name(string type_name); uvm_object_wrapper wrapper = m_resolve_type_name(type_name); if (wrapper != null) begin return wrapper; end uvm_report_warning("UnknownTypeName", {"find_wrapper_by_name: Type name '",type_name, "' not registered with the factory."}, UVM_NONE); endfunction function uvm_object_wrapper uvm_default_factory::find_override_by_name (string requested_type_name, string full_inst_path); uvm_object_wrapper rtype; uvm_factory_override lindex; rtype = m_resolve_type_name_by_inst(requested_type_name,full_inst_path); if(full_inst_path != "") begin foreach(m_inst_overrides[i]) begin if(m_matches_inst_override(.override(m_inst_overrides[i]), .requested_type(rtype), .requested_type_name(requested_type_name), .full_inst_path(full_inst_path))) begin m_override_info.push_back(m_inst_overrides[i]); if (lindex == null) begin lindex = m_inst_overrides[i]; if (!m_debug_pass) begin break; end end end end end if ((lindex == null) || m_debug_pass) begin uvm_factory_override matched_overrides[$]; foreach (m_type_overrides[index]) begin if(m_matches_type_override(.override(m_type_overrides[index]), .requested_type(rtype), .requested_type_name(requested_type_name), .full_inst_path(full_inst_path), .resolve_null_type_by_inst(1))) begin matched_overrides.push_back(m_type_overrides[index]); if ((lindex == null) || (lindex.replace == 0)) begin lindex = m_type_overrides[index]; if (!m_debug_pass && lindex.replace) begin break; end end end end if(matched_overrides.size() != 0) begin if (m_debug_pass) begin m_override_info = {m_override_info,matched_overrides}; end else begin m_override_info.push_back(matched_overrides[$]); end end end if (lindex != null) begin uvm_object_wrapper override = lindex.ovrd.m_type; lindex.used++; if (m_debug_pass) begin lindex.selected = 1; end if(!m_matches_type_override(.override(lindex), .requested_type(rtype), .requested_type_name(requested_type_name), .full_inst_path(full_inst_path), .match_original_type(0), .resolve_null_type_by_inst(1))) begin if(override == null) begin override = find_override_by_name(lindex.ovrd.m_type_name,full_inst_path); end else begin override = find_override_by_type(override,full_inst_path); end end else if(override == null) begin override = m_resolve_type_name_by_inst(lindex.ovrd.m_type_name,full_inst_path); end if(override == null) begin uvm_report_error("TYPNTF", {"Cannot resolve override for original type '", lindex.orig.m_type_name,"' because the override type '", lindex.ovrd.m_type_name, "' is not registered with the factory."}, UVM_NONE); end return override; end return null; endfunction function uvm_object_wrapper uvm_default_factory::find_override_by_type(uvm_object_wrapper requested_type, string full_inst_path); uvm_factory_override override_info[$]; return m_find_override_by_type(requested_type, full_inst_path, override_info); endfunction function uvm_object_wrapper uvm_default_factory::m_find_override_by_type(uvm_object_wrapper requested_type, string full_inst_path, ref uvm_factory_override override_info[$]); uvm_object_wrapper override; uvm_factory_override lindex; uvm_factory_queue_class qc; foreach (override_info[index]) begin if ( override_info[index].orig.m_type == requested_type) begin uvm_report_error("OVRDLOOP", "Recursive loop detected while finding override.", UVM_NONE); override_info[index].used++; if (!m_debug_pass) begin debug_create_by_type (requested_type, full_inst_path); end return requested_type; end end if(full_inst_path != "") begin foreach(m_inst_overrides[i]) begin if(m_matches_inst_override(.override(m_inst_overrides[i]), .requested_type(requested_type), .requested_type_name(requested_type.get_type_name()), .full_inst_path(full_inst_path))) begin override_info.push_back(m_inst_overrides[i]); if (lindex == null) begin lindex = m_inst_overrides[i]; if (!m_debug_pass) begin break; end end end end end if ((lindex == null) || m_debug_pass) begin uvm_factory_override matched_overrides[$]; foreach (m_type_overrides[index]) begin if(m_matches_type_override(.override(m_type_overrides[index]), .requested_type(requested_type), .requested_type_name(requested_type.get_type_name()), .full_inst_path(full_inst_path), .resolve_null_type_by_inst(1))) begin matched_overrides.push_back(m_type_overrides[index]); if ((lindex == null) || (lindex.replace == 0)) begin lindex = m_type_overrides[index]; if (!m_debug_pass && lindex.replace) begin break; end end end end if(matched_overrides.size() != 0) begin if (m_debug_pass) begin override_info = {override_info,matched_overrides}; end else begin override_info.push_back(matched_overrides[$]); end end end if (lindex != null) begin uvm_object_wrapper override = lindex.ovrd.m_type; lindex.used++; if (m_debug_pass) begin lindex.selected = 1; end if(!m_matches_type_override(.override(lindex), .requested_type(requested_type), .requested_type_name(requested_type.get_type_name()), .full_inst_path(full_inst_path), .match_original_type(0), .resolve_null_type_by_inst(1))) begin if(override == null) begin override = find_override_by_name(lindex.ovrd.m_type_name,full_inst_path); end else begin override = find_override_by_type(override,full_inst_path); end end else if(override == null) begin override = m_resolve_type_name_by_inst(lindex.ovrd.m_type_name,full_inst_path); end if(override == null) begin uvm_report_error("TYPNTF", {"Cannot resolve override for original type '", lindex.orig.m_type_name,"' because the override type '", lindex.ovrd.m_type_name, "' is not registered with the factory."}, UVM_NONE); end return override; end return requested_type; endfunction function void uvm_default_factory::print (int all_types=1); string key; string qs[$]; qs.push_back("\n#### Factory Configuration (*)\n\n"); if(!m_type_overrides.size() && !m_inst_overrides.size()) begin qs.push_back(" No instance or type overrides are registered with this factory\n"); end else begin int max1,max2,max3; string dash = "---------------------------------------------------------------------------------------------------"; string space= " "; if(!m_inst_overrides.size()) begin qs.push_back("No instance overrides are registered with this factory\n"); end else begin foreach(m_inst_overrides[j]) begin if (m_inst_overrides[j].orig.m_type_name.len() > max1) begin max1=m_inst_overrides[j].orig.m_type_name.len(); end if (m_inst_overrides[j].full_inst_path.len() > max2) begin max2=m_inst_overrides[j].full_inst_path.len(); end if (m_inst_overrides[j].ovrd.m_type_name.len() > max3) begin max3=m_inst_overrides[j].ovrd.m_type_name.len(); end end if (max1 < 14) begin max1 = 14; end if (max2 < 13) begin max2 = 13; end if (max3 < 13) begin max3 = 13; end qs.push_back("Instance Overrides:\n\n"); qs.push_back($sformatf(" %0s%0s %0s%0s %0s%0s\n","Requested Type",space.substr(1,max1-14), "Override Path", space.substr(1,max2-13), "Override Type", space.substr(1,max3-13))); qs.push_back($sformatf(" %0s %0s %0s\n",dash.substr(1,max1), dash.substr(1,max2), dash.substr(1,max3))); foreach(m_inst_overrides[j]) begin qs.push_back($sformatf(" %0s%0s %0s%0s",m_inst_overrides[j].orig.m_type_name, space.substr(1,max1-m_inst_overrides[j].orig.m_type_name.len()), m_inst_overrides[j].full_inst_path, space.substr(1,max2-m_inst_overrides[j].full_inst_path.len()))); qs.push_back($sformatf(" %0s\n", m_inst_overrides[j].ovrd.m_type_name)); end end if (!m_type_overrides.size()) begin qs.push_back("\nNo type overrides are registered with this factory\n"); end else begin if (max1 < 14) begin max1 = 14; end if (max2 < 13) begin max2 = 13; end if (max3 < 13) begin max3 = 13; end foreach (m_type_overrides[i]) begin if (m_type_overrides[i].orig.m_type_name.len() > max1) begin max1=m_type_overrides[i].orig.m_type_name.len(); end if (m_type_overrides[i].ovrd.m_type_name.len() > max2) begin max2=m_type_overrides[i].ovrd.m_type_name.len(); end end if (max1 < 14) begin max1 = 14; end if (max2 < 13) begin max2 = 13; end qs.push_back("\nType Overrides:\n\n"); qs.push_back($sformatf(" %0s%0s %0s%0s\n","Requested Type",space.substr(1,max1-14), "Override Type", space.substr(1,max2-13))); qs.push_back($sformatf(" %0s %0s\n",dash.substr(1,max1), dash.substr(1,max2))); for (int index=m_type_overrides.size()-1; index>=0; index--) begin qs.push_back($sformatf(" %0s%0s %0s\n", m_type_overrides[index].orig.m_type_name, space.substr(1,max1-m_type_overrides[index].orig.m_type_name.len()), m_type_overrides[index].ovrd.m_type_name)); end end end if (all_types >= 1 && m_type_names.first(key)) begin bit banner; qs.push_back($sformatf("\nAll types registered with the factory: %0d total\n",m_types.num())); do begin if (!(all_types < 2 && uvm_is_match("uvm_*", m_type_names[key].get_type_name())) && key == m_type_names[key].get_type_name()) begin if (!banner) begin qs.push_back(" Type Name\n"); qs.push_back(" ---------\n"); banner=1; end qs.push_back($sformatf(" %s\n", m_type_names[key].get_type_name())); end end while(m_type_names.next(key)); end qs.push_back("(*) Types with no associated type name will be printed as \n\n####\n\n"); begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "UVM/FACTORY/PRINT") >= UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "UVM/FACTORY/PRINT") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("UVM/FACTORY/PRINT", uvm_pkg::m_uvm_string_queue_join(qs), UVM_NONE, "t/uvm/src/base/uvm_factory.svh", 2050, "", 1); end end endfunction function void uvm_default_factory::debug_create_by_name (string requested_type_name, string parent_inst_path="", string name=""); m_debug_create(requested_type_name, null, parent_inst_path, name); endfunction function void uvm_default_factory::debug_create_by_type (uvm_object_wrapper requested_type, string parent_inst_path="", string name=""); m_debug_create("", requested_type, parent_inst_path, name); endfunction function void uvm_default_factory::m_debug_create (string requested_type_name, uvm_object_wrapper requested_type, string parent_inst_path, string name); string full_inst_path; uvm_object_wrapper result; if (parent_inst_path == "") begin full_inst_path = name; end else if (name != "") begin full_inst_path = {parent_inst_path,".",name}; end else begin full_inst_path = parent_inst_path; end m_override_info.delete(); if (requested_type == null) begin if (!m_type_names.exists(requested_type_name) && !m_lookup_strs.exists(requested_type_name)) begin uvm_report_warning("Factory Warning", {"The factory does not recognize '", requested_type_name,"' as a registered type."}, UVM_NONE); return; end m_debug_pass = 1; result = find_override_by_name(requested_type_name,full_inst_path); end else begin m_debug_pass = 1; if (!m_types.exists(requested_type)) begin register(requested_type); end result = find_override_by_type(requested_type,full_inst_path); if (requested_type_name == "") begin requested_type_name = requested_type.get_type_name(); end end m_debug_display(requested_type_name, result, full_inst_path); m_debug_pass = 0; foreach (m_override_info[index]) begin m_override_info[index].selected = 0; end endfunction function void uvm_default_factory::m_debug_display (string requested_type_name, uvm_object_wrapper result, string full_inst_path); int max1,max2,max3; string dash = "---------------------------------------------------------------------------------------------------"; string space= " "; string qs[$]; qs.push_back("\n#### Factory Override Information (*)\n\n"); qs.push_back( $sformatf("Given a request for an object of type '%s' with an instance\npath of '%s' the factory encountered\n\n", requested_type_name,full_inst_path)); if (m_override_info.size() == 0) begin qs.push_back("no relevant overrides.\n\n"); end else begin qs.push_back("the following relevant overrides. An 'x' next to a match indicates a\nmatch that was ignored.\n\n"); foreach (m_override_info[i]) begin if (m_override_info[i].orig.m_type_name.len() > max1) begin max1=m_override_info[i].orig.m_type_name.len(); end if (m_override_info[i].full_inst_path.len() > max2) begin max2=m_override_info[i].full_inst_path.len(); end if (m_override_info[i].ovrd.m_type_name.len() > max3) begin max3=m_override_info[i].ovrd.m_type_name.len(); end end if (max1 < 13) begin max1 = 13; end if (max2 < 13) begin max2 = 13; end if (max3 < 13) begin max3 = 13; end qs.push_back($sformatf("Original Type%0s Instance Path%0s Override Type%0s\n", space.substr(1,max1-13),space.substr(1,max2-13),space.substr(1,max3-13))); qs.push_back($sformatf(" %0s %0s %0s\n",dash.substr(1,max1), dash.substr(1,max2), dash.substr(1,max3))); foreach (m_override_info[i]) begin qs.push_back($sformatf("%s%0s%0s\n", m_override_info[i].selected ? " " : "x ", m_override_info[i].orig.m_type_name, space.substr(1,max1-m_override_info[i].orig.m_type_name.len()))); qs.push_back($sformatf(" %0s%0s", m_override_info[i].full_inst_path, space.substr(1,max2-m_override_info[i].full_inst_path.len()))); qs.push_back($sformatf(" %0s%0s", m_override_info[i].ovrd.m_type_name, space.substr(1,max3-m_override_info[i].ovrd.m_type_name.len()))); if (m_override_info[i].full_inst_path == "*") begin qs.push_back(" "); end else begin qs.push_back("\n"); end end qs.push_back("\n"); end qs.push_back("Result:\n\n"); qs.push_back($sformatf(" The factory will produce an object of type '%0s'\n", result == null ? requested_type_name : result.get_type_name())); qs.push_back("\n(*) Types with no associated type name will be printed as \n\n####\n\n"); begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "UVM/FACTORY/DUMP") >= UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "UVM/FACTORY/DUMP") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("UVM/FACTORY/DUMP", uvm_pkg::m_uvm_string_queue_join(qs), UVM_NONE, "t/uvm/src/base/uvm_factory.svh", 2235, "", 1); end end endfunction function uvm_object_wrapper uvm_default_factory::m_resolve_type_name(string requested_type_name); uvm_object_wrapper wrapper=null; if(m_type_names.exists(requested_type_name)) begin wrapper = m_type_names[requested_type_name]; end return wrapper; endfunction function uvm_object_wrapper uvm_default_factory::m_resolve_type_name_by_inst(string requested_type_name, string full_inst_path); uvm_object_wrapper wrapper=null; m_inst_typename_alias_t type_alias_inst[$]; type_alias_inst = m_inst_aliases.find(i) with ((i.alias_type_name == requested_type_name) && uvm_is_match(i.full_inst_path,full_inst_path)); if (type_alias_inst.size() > 0) begin wrapper = type_alias_inst[0].orig.m_type; end else begin wrapper = m_resolve_type_name(requested_type_name); end return wrapper; endfunction function bit uvm_default_factory::m_matches_type_pair(m_uvm_factory_type_pair_t match_type_pair, uvm_object_wrapper requested_type, string requested_type_name); return ((match_type_pair.m_type != null) && (match_type_pair.m_type == requested_type) || (match_type_pair.m_type_name != "" && match_type_pair.m_type_name != "" && match_type_pair.m_type_name == requested_type_name)); endfunction function bit uvm_default_factory::m_matches_inst_override(uvm_factory_override override, uvm_object_wrapper requested_type, string requested_type_name, string full_inst_path=""); m_uvm_factory_type_pair_t match_type_pair = override.orig ; if(match_type_pair.m_type == null) begin match_type_pair.m_type = m_resolve_type_name_by_inst(match_type_pair.m_type_name, full_inst_path); end if (m_matches_type_pair(.match_type_pair(match_type_pair), .requested_type(requested_type), .requested_type_name(requested_type_name))) begin if(override.has_wildcard) begin return (override.full_inst_path == "*" || uvm_is_match(override.full_inst_path,full_inst_path)); end else begin return (override.full_inst_path == full_inst_path); end end return 0; endfunction function bit uvm_default_factory::m_matches_type_override(uvm_factory_override override, uvm_object_wrapper requested_type, string requested_type_name, string full_inst_path="", bit match_original_type = 1, bit resolve_null_type_by_inst=0); m_uvm_factory_type_pair_t match_type_pair = match_original_type ? override.orig : override.ovrd; if(match_type_pair.m_type == null) begin if(resolve_null_type_by_inst) begin match_type_pair.m_type = m_resolve_type_name_by_inst(match_type_pair.m_type_name,full_inst_path); end else begin match_type_pair.m_type = m_resolve_type_name(match_type_pair.m_type_name); end end return m_matches_type_pair(.match_type_pair(match_type_pair), .requested_type(requested_type), .requested_type_name(requested_type_name)); endfunction `define UVM_REGISTRY_SVH typedef class uvm_registry_common; typedef class uvm_registry_component_creator; typedef class uvm_registry_object_creator; class uvm_component_registry #(type T=uvm_component, string Tname="") extends uvm_object_wrapper; typedef uvm_component_registry #(T,Tname) this_type; typedef uvm_registry_common#( this_type, uvm_registry_component_creator, T, Tname ) common_type; virtual function uvm_component create_component (string name, uvm_component parent); T obj; obj = new(name, parent); return obj; endfunction static function string type_name(); return common_type::type_name(); endfunction : type_name virtual function string get_type_name(); common_type common = common_type::get(); return common.get_type_name(); endfunction static function this_type get(); static this_type m_inst; if (m_inst == null) begin m_inst = new(); end return m_inst; endfunction virtual function void initialize(); common_type common = common_type::get(); common.initialize(); endfunction static function T create(string name, uvm_component parent, string contxt=""); return common_type::create( name, parent, contxt ); endfunction static function void set_type_override (uvm_object_wrapper override_type, bit replace=1); common_type::set_type_override( override_type, replace ); endfunction static function void set_inst_override(uvm_object_wrapper override_type, string inst_path, uvm_component parent=null); common_type::set_inst_override( override_type, inst_path, parent ); endfunction static function bit set_type_alias(string alias_name); common_type::set_type_alias( alias_name ); return 1; endfunction endclass class uvm_object_registry #(type T=uvm_object, string Tname="") extends uvm_object_wrapper; typedef uvm_object_registry #(T,Tname) this_type; typedef uvm_registry_common#( this_type, uvm_registry_object_creator, T, Tname ) common_type; virtual function uvm_object create_object(string name=""); T obj; if (name=="") begin obj = new(); end else begin obj = new(name); end return obj; endfunction static function string type_name(); return common_type::type_name(); endfunction : type_name virtual function string get_type_name(); common_type common = common_type::get(); return common.get_type_name(); endfunction static function this_type get(); static this_type m_inst; if (m_inst == null) begin m_inst = new(); end return m_inst; endfunction static function T create (string name="", uvm_component parent=null, string contxt=""); return common_type::create( name, parent, contxt ); endfunction static function void set_type_override (uvm_object_wrapper override_type, bit replace=1); common_type::set_type_override( override_type, replace ); endfunction static function void set_inst_override(uvm_object_wrapper override_type, string inst_path, uvm_component parent=null); common_type::set_inst_override( override_type, inst_path, parent ); endfunction static function bit set_type_alias(string alias_name); common_type::set_type_alias( alias_name ); return 1; endfunction virtual function void initialize(); common_type common = common_type::get(); common.initialize(); endfunction endclass class uvm_abstract_component_registry #(type T=uvm_component, string Tname="") extends uvm_object_wrapper; typedef uvm_abstract_component_registry #(T,Tname) this_type; typedef uvm_registry_common#( this_type, uvm_registry_component_creator, T, Tname ) common_type; virtual function uvm_component create_component (string name, uvm_component parent); begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM/ABST_RGTRY/CREATE_ABSTRACT_CMPNT") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM/ABST_RGTRY/CREATE_ABSTRACT_CMPNT") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM/ABST_RGTRY/CREATE_ABSTRACT_CMPNT", $sformatf( "Cannot create an instance of abstract class %s (with name %s and parent %s). Check for missing factory overrides for %s.", this.get_type_name(), name, parent.get_full_name(), this.get_type_name() ), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_registry.svh", 330, "", 1); end end return null; endfunction static function string type_name(); return common_type::type_name(); endfunction : type_name virtual function string get_type_name(); common_type common = common_type::get(); return common.get_type_name(); endfunction static function this_type get(); static this_type m_inst; if (m_inst == null) begin m_inst = new(); end return m_inst; endfunction static function T create(string name, uvm_component parent, string contxt=""); return common_type::create( name, parent, contxt ); endfunction static function void set_type_override (uvm_object_wrapper override_type, bit replace=1); common_type::set_type_override( override_type, replace ); endfunction static function void set_inst_override(uvm_object_wrapper override_type, string inst_path, uvm_component parent=null); common_type::set_inst_override( override_type, inst_path, parent ); endfunction static function bit set_type_alias(string alias_name); common_type::set_type_alias( alias_name ); return 1; endfunction virtual function void initialize(); common_type common = common_type::get(); common.initialize(); endfunction endclass class uvm_abstract_object_registry #(type T=uvm_object, string Tname="") extends uvm_object_wrapper; typedef uvm_abstract_object_registry #(T,Tname) this_type; typedef uvm_registry_common#( this_type, uvm_registry_object_creator, T, Tname ) common_type; virtual function uvm_object create_object(string name=""); begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM/ABST_RGTRY/CREATE_ABSTRACT_OBJ") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM/ABST_RGTRY/CREATE_ABSTRACT_OBJ") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM/ABST_RGTRY/CREATE_ABSTRACT_OBJ", $sformatf( "Cannot create an instance of abstract class %s (with name %s). Check for missing factory overrides for %s.", this.get_type_name(), name, this.get_type_name() ), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_registry.svh", 453, "", 1); end end return null; endfunction static function string type_name(); return common_type::type_name(); endfunction : type_name virtual function string get_type_name(); common_type common = common_type::get(); return common.get_type_name(); endfunction static function this_type get(); static this_type m_inst; if (m_inst == null) begin m_inst = new(); end return m_inst; endfunction static function T create (string name="", uvm_component parent=null, string contxt=""); return common_type::create( name, parent, contxt ); endfunction static function void set_type_override (uvm_object_wrapper override_type, bit replace=1); common_type::set_type_override( override_type, replace ); endfunction static function void set_inst_override(uvm_object_wrapper override_type, string inst_path, uvm_component parent=null); common_type::set_inst_override( override_type, inst_path, parent ); endfunction static function bit set_type_alias(string alias_name); common_type::set_type_alias( alias_name ); return 1; endfunction virtual function void initialize(); common_type common = common_type::get(); common.initialize(); endfunction endclass class uvm_registry_common #( type Tregistry=int, type Tcreator=int, type Tcreated=int, string Tname="" ); typedef uvm_registry_common#(Tregistry,Tcreator,Tcreated,Tname) this_type; local static string m__type_aliases[$]; static function string type_name(); if((Tname == "") && (m__type_aliases.size() != 0)) begin return m__type_aliases[0]; end return Tname; endfunction : type_name virtual function string get_type_name(); return type_name(); endfunction static function this_type get(); static this_type m_inst; if (m_inst == null) begin m_inst = new(); end return m_inst; endfunction : get static function Tcreated create(string name, uvm_component parent, string contxt); uvm_object obj; if (contxt == "" && parent != null) begin contxt = parent.get_full_name(); end obj = Tcreator::create_by_type( Tregistry::get(), contxt, name, parent ); if (!$cast(create, obj)) begin string msg; msg = {"Factory did not return a ", Tcreator::base_type_name(), " of type '",Tregistry::type_name, "'. A component of type '",obj == null ? "null" : obj.get_type_name(), "' was returned instead. Name=",name," Parent=", parent==null?"null":parent.get_type_name()," contxt=",contxt}; uvm_report_fatal("FCTTYP", msg, UVM_NONE); end endfunction static function void set_type_override (uvm_object_wrapper override_type, bit replace); uvm_factory factory=uvm_factory::get(); factory.set_type_override_by_type(Tregistry::get(),override_type,replace); endfunction static function void set_inst_override(uvm_object_wrapper override_type, string inst_path, uvm_component parent); string full_inst_path; uvm_factory factory=uvm_factory::get(); if (parent != null) begin if (inst_path == "") begin inst_path = parent.get_full_name(); end else begin inst_path = {parent.get_full_name(),".",inst_path}; end end factory.set_inst_override_by_type(Tregistry::get(),override_type,inst_path); endfunction static function void set_type_alias(string alias_name); m__type_aliases.push_back(alias_name); m__type_aliases.sort(); if (uvm_pkg::get_core_state() != UVM_CORE_UNINITIALIZED) begin uvm_factory factory = uvm_factory::get(); Tregistry rgtry = Tregistry::get(); if (factory.is_type_registered(rgtry)) begin factory.set_type_alias(alias_name,rgtry); end end endfunction static function bit __deferred_init(); Tregistry rgtry = Tregistry::get(); if (uvm_pkg::get_core_state() == UVM_CORE_UNINITIALIZED) begin uvm_pkg::uvm_deferred_init.push_back(rgtry); end else begin rgtry.initialize(); end return 1; endfunction local static bit m__initialized=__deferred_init(); virtual function void initialize(); uvm_factory factory =uvm_factory::get(); Tregistry rgtry = Tregistry::get(); factory.register(rgtry); foreach(m__type_aliases[i]) begin factory.set_type_alias(m__type_aliases[i],rgtry); end endfunction endclass virtual class uvm_registry_component_creator; static function uvm_component create_by_type( uvm_object_wrapper obj_wrpr, string contxt, string name, uvm_component parent ); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory = cs.get_factory(); return factory.create_component_by_type( obj_wrpr, contxt, name, parent ); endfunction static function string base_type_name(); return "component"; endfunction endclass virtual class uvm_registry_object_creator; static function uvm_object create_by_type( uvm_object_wrapper obj_wrpr, string contxt, string name, uvm_object unused ); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory = cs.get_factory(); unused = unused; return factory.create_object_by_type( obj_wrpr, contxt, name ); endfunction static function string base_type_name(); return "object"; endfunction endclass class uvm_pool #(type KEY=int, T=uvm_void) extends uvm_object; typedef uvm_pool #(KEY,T) this_type; static protected this_type m_global_pool; protected T pool[KEY]; typedef uvm_object_registry #(uvm_pool #(KEY,T)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_pool #(KEY,T) tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_pool"; endfunction : type_name virtual function string get_type_name(); return "uvm_pool"; endfunction : get_type_name function new (string name=""); super.new(name); endfunction static function this_type get_global_pool (); if (m_global_pool==null) begin m_global_pool = new("pool"); end return m_global_pool; endfunction static function T get_global (KEY key); this_type gpool; gpool = get_global_pool(); return gpool.get(key); endfunction virtual function T get (KEY key); if (!pool.exists(key)) begin T default_value; pool[key] = default_value; end return pool[key]; endfunction virtual function void add (KEY key, T item); pool[key] = item; endfunction virtual function int num (); return pool.num(); endfunction virtual function void delete (KEY key); if (!exists(key)) begin uvm_report_warning("POOLDEL", $sformatf("delete: pool key doesn't exist. Ignoring delete request")); return; end pool.delete(key); endfunction virtual function int exists (KEY key); return pool.exists(key); endfunction virtual function int first (ref KEY key); return pool.first(key); endfunction virtual function int last (ref KEY key); return pool.last(key); endfunction virtual function int next (ref KEY key); return pool.next(key); endfunction virtual function int prev (ref KEY key); return pool.prev(key); endfunction virtual function void do_copy (uvm_object rhs); this_type p; KEY key; super.do_copy(rhs); if (rhs==null || !$cast(p, rhs)) begin return; end pool = p.pool; endfunction virtual function void do_print (uvm_printer printer); string v; int cnt; string item; KEY key; printer.print_array_header("pool",pool.num(),"aa_object_string"); if (pool.first(key)) begin do begin item.itoa(cnt); item = {"[-key",item,"--]"}; $swrite(v,pool[key]); printer.print_generic(item,"",-1,v,"["); end while (pool.next(key)); end printer.print_array_footer(); endfunction endclass class uvm_object_string_pool #(type T=uvm_object) extends uvm_pool #(string,T); typedef uvm_object_string_pool #(T) this_type; static protected this_type m_global_pool; typedef uvm_object_registry #(uvm_object_string_pool#(T)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_object_string_pool#(T) tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_obj_str_pool"; endfunction : type_name virtual function string get_type_name(); return "uvm_obj_str_pool"; endfunction : get_type_name function new (string name=""); super.new(name); endfunction static function this_type get_global_pool (); if (m_global_pool==null) begin m_global_pool = new("global_pool"); end return m_global_pool; endfunction static function T get_global (string key); this_type gpool; gpool = get_global_pool(); return gpool.get(key); endfunction virtual function T get (string key); if (!pool.exists(key)) begin pool[key] = new (key); end return pool[key]; endfunction virtual function void delete (string key); if (!exists(key)) begin uvm_report_warning("POOLDEL", $sformatf("delete: key '%s' doesn't exist", key)); return; end pool.delete(key); endfunction virtual function void do_print (uvm_printer printer); string key; printer.print_array_header("pool",pool.num(),"aa_object_string"); if (pool.first(key)) begin do begin printer.print_object({"[",key,"]"}, pool[key],"["); end while (pool.next(key)); end printer.print_array_footer(); endfunction endclass typedef class uvm_barrier; typedef class uvm_event; typedef uvm_object_string_pool #(uvm_barrier) uvm_barrier_pool ; typedef uvm_object_string_pool #(uvm_event#(uvm_object)) uvm_event_pool ; `define UVM_QUEUE_SVH class uvm_queue #(type T=int) extends uvm_object; typedef uvm_queue #(T) this_type; typedef uvm_object_registry #(uvm_queue#(T)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_queue#(T) tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_queue"; endfunction : type_name virtual function string get_type_name(); return "uvm_queue"; endfunction : get_type_name static local this_type m_global_queue; protected T queue[$]; function new (string name=""); super.new(name); endfunction static function this_type get_global_queue (); if (m_global_queue==null) begin m_global_queue = new("global_queue"); end return m_global_queue; endfunction static function T get_global (int index); this_type gqueue; gqueue = get_global_queue(); return gqueue.get(index); endfunction virtual function T get (int index); T default_value; if (index >= size() || index < 0) begin uvm_report_warning("QUEUEGET", $sformatf("get: given index out of range for queue of size %0d. Ignoring get request",size())); return default_value; end return queue[index]; endfunction virtual function int size (); return queue.size(); endfunction virtual function void insert (int index, T item); if (index >= size() || index < 0) begin uvm_report_warning("QUEUEINS", $sformatf("insert: given index out of range for queue of size %0d. Ignoring insert request",size())); return; end queue.insert(index,item); endfunction virtual function void delete (int index=-1); if (index >= size() || index < -1) begin uvm_report_warning("QUEUEDEL", $sformatf("delete: given index out of range for queue of size %0d. Ignoring delete request",size())); return; end if (index == -1) begin queue.delete(); end else begin queue.delete(index); end endfunction virtual function T pop_front(); return queue.pop_front(); endfunction virtual function T pop_back(); return queue.pop_back(); endfunction virtual function void push_front(T item); queue.push_front(item); endfunction virtual function void push_back(T item); queue.push_back(item); endfunction virtual task wait_until_not_empty(); wait(queue.size() > 0); endtask virtual function void do_copy (uvm_object rhs); this_type p; super.do_copy(rhs); if (rhs == null || !$cast(p, rhs)) begin return; end queue = p.queue; endfunction virtual function string convert2string(); return $sformatf("%p",queue); endfunction endclass class uvm_spell_chkr #(type T=int); typedef T tab_t[string]; localparam int unsigned max = '1; static function bit check ( ref tab_t strtab, input string s); string key; int distance; int unsigned min; string min_key[$]; if(strtab.exists(s)) begin return 1; end min = max; foreach(strtab[key]) begin distance = levenshtein_distance(key, s); if(distance < 0) begin continue; end if(distance < min) begin min = distance; min_key.delete(); min_key.push_back(key); continue; end if(distance == min) begin min_key.push_back(key); end end if(min == max) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "UVM/CONFIGDB/SPELLCHK") >= UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "UVM/CONFIGDB/SPELLCHK") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("UVM/CONFIGDB/SPELLCHK", $sformatf("%s not located, no alternatives to suggest", s), UVM_NONE, "t/uvm/src/base/uvm_spell_chkr.svh", 123, "", 1); end end end else begin string q[$]; foreach(min_key[i]) begin q.push_back(min_key[i]); q.push_back("|"); end if(q.size()) begin void'(q.pop_back()); end begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "UVM/CONFIGDB/SPELLCHK") >= UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "UVM/CONFIGDB/SPELLCHK") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("UVM/CONFIGDB/SPELLCHK", $sformatf("%s not located, did you mean %s", s, uvm_pkg::m_uvm_string_queue_join(q)), UVM_NONE, "t/uvm/src/base/uvm_spell_chkr.svh", 140, "", 1); end end end return 0; endfunction static local function int levenshtein_distance(string s, string t); int k, i, j, n, m, cost, distance; int d[]; n = s.len() + 1; m = t.len() + 1; if(n == 1 || m == 1) begin return -1; end d = new[m*n]; for(k = 0; k < n; k++) begin d[k] = k; end for(k = 0; k < m; k++) begin d[k*n] = k; end for(i = 1; i < n; i++) begin for(j = 1; j < m; j++) begin cost = !(s[i-1] == t[j-1]); d[j*n+i] = minimum(d[(j-1)*n+i]+1, d[j*n+i-1]+1, d[(j-1)*n+i-1]+cost); end end distance = d[n*m-1]; return distance; endfunction static local function int minimum(int a, int b, int c); int min = a; if(b < min) begin min = b; end if(c < min) begin min = c; end return min; endfunction endclass typedef class uvm_resource_base; class uvm_resource_types; typedef bit[1:0] override_t; typedef enum override_t { TYPE_OVERRIDE = 2'b01, NAME_OVERRIDE = 2'b10 } override_e; typedef uvm_queue#(uvm_resource_base) rsrc_q_t; typedef uvm_resource_base rsrc_sv_q_t[$]; typedef uvm_shared#(rsrc_sv_q_t) rsrc_shared_q_t; typedef enum { PRI_HIGH, PRI_LOW } priority_e; typedef struct { time read_time; time write_time; int unsigned read_count; int unsigned write_count; } access_t; endclass class uvm_resource_options; static local bit auditing = 1; static function void turn_on_auditing(); auditing = 1; endfunction static function void turn_off_auditing(); auditing = 0; endfunction static function bit is_auditing(); return auditing; endfunction endclass class uvm_resource_debug extends uvm_object ; uvm_resource_types::access_t access[string]; typedef uvm_object_registry#(uvm_resource_debug,"uvm_resource_debug") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_resource_debug tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_resource_debug"; endfunction : type_name virtual function string get_type_name(); return "uvm_resource_debug"; endfunction : get_type_name function new(string name = ""); super.new(name); endfunction virtual function void record_read_access(uvm_object accessor = null); string str; uvm_resource_types::access_t access_record; if(accessor != null) begin str = accessor.get_full_name(); end else begin str = ""; end if(access.exists(str)) begin access_record = access[str]; end else begin init_access_record(access_record); end access_record.read_count++; access_record.read_time = $realtime; access[str] = access_record; endfunction virtual function void record_write_access(uvm_object accessor = null); string str; if(accessor != null) begin uvm_resource_types::access_t access_record; string str; str = accessor.get_full_name(); if(access.exists(str)) begin access_record = access[str]; end else begin init_access_record(access_record); end access_record.write_count++; access_record.write_time = $realtime; access[str] = access_record; end endfunction virtual function void print_accessors(); string str; uvm_component comp; uvm_resource_types::access_t access_record; string qs[$]; if(access.num() == 0) begin return; end foreach (access[i]) begin str = i; access_record = access[str]; qs.push_back($sformatf("%s reads: %0d @ %0t writes: %0d @ %0t\n",str, access_record.read_count, access_record.read_time, access_record.write_count, access_record.write_time)); end begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "UVM/RESOURCE/ACCESSOR") >= UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "UVM/RESOURCE/ACCESSOR") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("UVM/RESOURCE/ACCESSOR", uvm_pkg::m_uvm_string_queue_join(qs), UVM_NONE, "t/uvm/src/base/uvm_resource_base.svh", 330, "", 1); end end endfunction function void init_access_record (inout uvm_resource_types::access_t access_record); access_record.read_time = 0; access_record.write_time = 0; access_record.read_count = 0; access_record.write_count = 0; endfunction endclass virtual class uvm_resource_base extends uvm_object; protected bit modified; protected bit read_only; uvm_resource_debug dbg ; protected string scope; int unsigned precedence; static int unsigned default_precedence = 1000; function new(string name = "",string s = ""); super.new(name); modified = 0; read_only = 0; if (s == "") begin scope = s; end else begin scope = uvm_glob_to_re(s) ; end precedence = default_precedence ; endfunction pure virtual function uvm_resource_base get_type_handle(); function void set_read_only(); read_only = 1; endfunction function void set_read_write(); read_only = 0; endfunction function bit is_read_only(); return read_only; endfunction task wait_modified(); wait (modified == 1); modified = 0; endtask function string convert2string(); return $sformatf("(%s) %s", m_value_type_name(), m_value_as_string()); endfunction pure virtual function string m_value_type_name(); pure virtual function string m_value_as_string(); function void do_print(uvm_printer printer); super.do_print(printer); printer.print_generic_element("val", m_value_type_name(), "", m_value_as_string()); endfunction : do_print function void record_read_access(uvm_object accessor = null); if (dbg==null) begin dbg = uvm_resource_debug::type_id::create("dbg") ; end dbg.record_read_access(accessor); endfunction function void record_write_access(uvm_object accessor = null); if (dbg==null) begin dbg = uvm_resource_debug::type_id::create("dbg") ; end dbg.record_write_access(accessor); endfunction virtual function void print_accessors(); if (dbg != null) begin dbg.print_accessors(); end endfunction function void init_access_record (inout uvm_resource_types::access_t access_record); if (dbg==null) begin dbg = uvm_resource_debug::type_id::create("dbg") ; end dbg.init_access_record(access_record); endfunction function void set_scope(string s); scope = uvm_glob_to_re(s); endfunction function void m_set_scope(string s); scope = s; endfunction function string get_scope(); return scope; endfunction function bit match_scope(string s); return uvm_is_match(scope, s); endfunction pure virtual function void set_priority (uvm_resource_types::priority_e pri); endclass class get_t; string name; string scope; uvm_resource_base rsrc; time t; endclass typedef class uvm_tree_printer ; class uvm_resource_pool extends uvm_void; typedef uvm_resource_types::rsrc_shared_q_t table_q_t; `define M__TABLE_Q(QUEUE_NAME) QUEUE_NAME``.value `define M__TABLE_GET(QUEUE_NAME, ITER) QUEUE_NAME``.value[ITER] `define M__TABLE_NAME "uvm_shared#(uvm_resource_base[$])" table_q_t rtab [string]; table_q_t ttab [uvm_resource_base]; get_t get_record [$]; function new(); endfunction static function uvm_resource_pool get(); uvm_resource_pool t_rp; uvm_coreservice_t cs = uvm_coreservice_t::get(); t_rp = cs.get_resource_pool(); return t_rp; endfunction function bit spell_check(string s); return uvm_spell_chkr#(table_q_t)::check(rtab, s); endfunction function void set (uvm_resource_base rsrc, uvm_resource_types::override_t override = 0); if (rsrc == null) begin return ; end if (override) begin set_override(rsrc, rsrc.get_scope()) ; end else begin set_scope(rsrc, rsrc.get_scope()) ; end endfunction function void set_scope (uvm_resource_base rsrc, string scope); table_q_t rq; string name; uvm_resource_base type_handle; uvm_resource_base r; int unsigned i; if(rsrc == null) begin uvm_report_warning("NULLRASRC", "attempting to set scope of a null resource"); return; end name = rsrc.get_name(); if ((name != "") && rtab.exists(name)) begin rq = rtab[name]; for (int iter=0; iter < rq.value.size(); iter++) begin if (rq.value[iter] == rsrc) begin rsrc.m_set_scope(scope); return; end end end if (rq == null) begin rq = new(); rtab[name] = rq; end rq.value.push_back(rsrc); type_handle = rsrc.get_type_handle(); if(ttab.exists(type_handle)) begin rq = ttab[type_handle]; end else begin rq = new(); ttab[type_handle] = rq; end rq.value.push_back(rsrc); rsrc.m_set_scope(scope); rsrc.precedence = get_default_precedence(); endfunction function void set_override(uvm_resource_base rsrc, string scope=""); string s ; if (rsrc == null) begin uvm_report_warning("NULLRASRC", "attempting to change the search priority of a null resource"); return; end if (scope == "") begin s = rsrc.get_scope(); end else begin s = scope ; end set_scope(rsrc, s); set_priority(rsrc, uvm_resource_types::PRI_HIGH); endfunction function void set_name_override(uvm_resource_base rsrc, string scope=""); string s ; if (rsrc == null) begin uvm_report_warning("NULLRASRC", "attempting to change the search priority of a null resource"); return; end if (scope == "") begin s = rsrc.get_scope(); end else begin s = scope ; end set_scope(rsrc, s); set_priority_name(rsrc, uvm_resource_types::PRI_HIGH); endfunction function void set_type_override(uvm_resource_base rsrc, string scope=""); string s ; if (rsrc == null) begin uvm_report_warning("NULLRASRC", "attempting to change the search priority of a null resource"); return; end if (scope == "") begin s = rsrc.get_scope(); end else begin s = scope ; end set_scope(rsrc, s); set_priority_type(rsrc, uvm_resource_types::PRI_HIGH); endfunction virtual function bit get_scope(uvm_resource_base rsrc, output string scope); table_q_t rq; string name; uvm_resource_base r, type_handle; int unsigned i; if(rsrc == null) begin return 0; end name = rsrc.get_name(); if((name != "") && rtab.exists(name)) begin rq = rtab[name]; for (int iter=0; iter < rq.value.size(); iter++) begin if (rq.value[iter] == rsrc) begin scope = rsrc.get_scope(); return 1; end end end type_handle = rsrc.get_type_handle(); if (ttab.exists(type_handle)) begin rq = ttab[type_handle]; for (int iter=0; iter < rq.value.size(); iter++) begin if (rq.value[iter] == rsrc) begin scope = rsrc.get_scope(); return 1; end end end scope = ""; return 0; endfunction virtual function void delete ( uvm_resource_base rsrc ); string name; table_q_t rq; uvm_resource_base type_handle; int iter; if (rsrc != null) begin name = rsrc.get_name(); if(name != "") begin if(rtab.exists(name)) begin rq = rtab[name]; iter = 0; while (iter < rq.value.size()) begin if (rq.value[iter] == rsrc) begin rq.value.delete(iter); break; end iter++; end end end type_handle = rsrc.get_type_handle(); if(ttab.exists(type_handle)) begin rq = ttab[type_handle]; iter = 0; while (iter < rq.value.size()) begin if (rq.value[iter] == rsrc) begin rq.value.delete(iter); break; end iter++; end end end endfunction function void push_get_record(string name, string scope, uvm_resource_base rsrc); get_t impt; if(!uvm_resource_options::is_auditing()) begin return; end impt = new(); impt.name = name; impt.scope = scope; impt.rsrc = rsrc; impt.t = $realtime; get_record.push_back(impt); endfunction function void dump_get_records(); get_t record; bit success; string qs[$]; qs.push_back("--- resource get records ---\n"); foreach (get_record[i]) begin record = get_record[i]; success = (record.rsrc != null); qs.push_back($sformatf("get: name=%s scope=%s %s @ %0t\n", record.name, record.scope, ((success)?"success":"fail"), record.t)); end begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "UVM/RESOURCE/GETRECORD") >= UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "UVM/RESOURCE/GETRECORD") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("UVM/RESOURCE/GETRECORD", uvm_pkg::m_uvm_string_queue_join(qs), UVM_NONE, "t/uvm/src/base/uvm_resource_pool.svh", 515, "", 1); end end endfunction function uvm_resource_types::rsrc_q_t lookup_name(string scope = "", string name, uvm_resource_base type_handle = null, bit rpterr = 1); table_q_t rq; uvm_resource_types::rsrc_q_t q; uvm_resource_base rsrc; uvm_resource_base r; string rsrcs; begin process p = process::self(); string s; if(p!=null) begin s=p.get_randstate(); end q=new(); if(p!=null) begin p.set_randstate(s); end end if(name == "") begin return q; end if(!rtab.exists(name)) begin if(rpterr) begin void'(spell_check(name)); end return q; end rsrc = null; rq = rtab[name]; for (int iter=0; iter < rq.value.size(); iter++) begin uvm_resource_base rsrc_iter; rsrc_iter = rq.value[iter]; rsrcs = rsrc_iter != null ? rsrc_iter.get_scope(): ""; if(((type_handle == null) || (rsrc_iter.get_type_handle() == type_handle)) && uvm_is_match(rsrcs, scope)) begin q.push_back(rsrc_iter); end end return q; endfunction static function uvm_resource_base get_highest_precedence(ref uvm_resource_types::rsrc_q_t q); uvm_resource_base rsrc; uvm_resource_base r; int unsigned i; int unsigned prec; int unsigned c_prec; if(q.size() == 0) begin return null; end rsrc = q.get(0); prec = (rsrc != null) ? rsrc.precedence: 0; for(int i = 1; i < q.size(); ++i) begin r = q.get(i); c_prec = (r != null) ? r.precedence: 0; if(c_prec > prec) begin rsrc = r; prec = c_prec; end end return rsrc; endfunction static function void sort_by_precedence(ref uvm_resource_types::rsrc_q_t q); uvm_resource_types::rsrc_sv_q_t all[int]; uvm_resource_base r; int unsigned prec; for(int i=0; i", scope, null); return null; end rq = ttab[type_handle]; for (int iter=0; iter < rq.value.size(); iter++) begin uvm_resource_base rsrc_iter; rsrc_iter = rq.value[iter]; if(rsrc_iter != null && uvm_is_match(rsrc_iter.get_scope(), scope)) begin push_get_record("", scope, rsrc_iter); return rsrc_iter; end end push_get_record("", scope, null); return null; endfunction function uvm_resource_types::rsrc_q_t lookup_regex_names(string scope, string name, uvm_resource_base type_handle = null); return lookup_name(scope, name, type_handle, 0); endfunction function uvm_resource_types::rsrc_q_t lookup_regex(string re, scope); table_q_t rq; uvm_resource_types::rsrc_q_t result_q; int unsigned i; uvm_resource_base r; string s; result_q = new(); foreach (rtab[name]) begin if ( ! uvm_is_match(re, name) ) begin continue; end rq = rtab[name]; for (int iter=0; iter < rq.value.size(); iter++) begin uvm_resource_base rsrc_iter; rsrc_iter = rq.value[iter]; if(rsrc_iter != null && uvm_is_match(rsrc_iter.get_scope(), scope)) begin result_q.push_back(rsrc_iter); end end end return result_q; endfunction function uvm_resource_types::rsrc_q_t lookup_scope(string scope); table_q_t rq; uvm_resource_base r; int unsigned i; int unsigned err; uvm_resource_types::rsrc_q_t q = new(); string name; if(rtab.last(name)) begin do begin rq = rtab[name]; for (int iter=0; iter < rq.value.size(); iter++) begin uvm_resource_base rsrc_iter; rsrc_iter = rq.value[iter]; if(rsrc_iter != null && uvm_is_match(rsrc_iter.get_scope(), scope)) begin q.push_back(rsrc_iter); end end end while(rtab.prev(name)); end return q; endfunction local function void set_priority_queue(uvm_resource_base rsrc, table_q_t rq, uvm_resource_types::priority_e pri); uvm_resource_base r; int unsigned i; string msg; string name = rsrc.get_name(); for (int iter=0; iter < rq.value.size(); iter++) begin r = rq.value[iter]; if (r == rsrc) begin i = iter; break; end end if(r != rsrc) begin $sformat(msg, "Handle for resource named %s is not in the name table; cannot change its priority", name); uvm_report_error("NORSRC", msg); return; end rq.value.delete(i); case(pri) uvm_resource_types::PRI_HIGH: begin rq.value.push_front(rsrc); end uvm_resource_types::PRI_LOW: begin rq.value.push_back(rsrc); end endcase endfunction function void set_priority_type(uvm_resource_base rsrc, uvm_resource_types::priority_e pri); uvm_resource_base type_handle; string msg; table_q_t rq; if(rsrc == null) begin uvm_report_warning("NULLRASRC", "attempting to change the search priority of a null resource"); return; end type_handle = rsrc.get_type_handle(); if(!ttab.exists(type_handle)) begin $sformat(msg, "Type handle for resrouce named %s not found in type map; cannot change its search priority", rsrc.get_name()); uvm_report_error("RNFTYPE", msg); return; end rq = ttab[type_handle]; set_priority_queue(rsrc, rq, pri); endfunction function void set_priority_name(uvm_resource_base rsrc, uvm_resource_types::priority_e pri); string name; string msg; if(rsrc == null) begin uvm_report_warning("NULLRASRC", "attempting to change the search priority of a null resource"); return; end name = rsrc.get_name(); if(!rtab.exists(name)) begin $sformat(msg, "Resrouce named %s not found in name map; cannot change its search priority", name); uvm_report_error("RNFNAME", msg); return; end set_priority_queue(rsrc, rtab[name], pri); endfunction function void set_priority (uvm_resource_base rsrc, uvm_resource_types::priority_e pri); set_priority_type(rsrc, pri); set_priority_name(rsrc, pri); endfunction static function void set_default_precedence( int unsigned precedence); uvm_coreservice_t cs = uvm_coreservice_t::get(); cs.set_resource_pool_default_precedence(precedence); endfunction static function int unsigned get_default_precedence(); uvm_coreservice_t cs = uvm_coreservice_t::get(); return cs.get_resource_pool_default_precedence(); endfunction virtual function void set_precedence(uvm_resource_base r, int unsigned p=uvm_resource_pool::get_default_precedence()); table_q_t rq; string name; int unsigned i; uvm_resource_base rsrc; if(r == null) begin uvm_report_warning("NULLRASRC", "attempting to set precedence of a null resource"); return; end name = r.get_name(); if(rtab.exists(name)) begin rq = rtab[name]; for (int iter=0; iter < rq.value.size(); iter++) begin rsrc = rq.value[iter]; if (rsrc == r) begin break; end end end if(r != rsrc) begin uvm_report_warning("NORSRC", $sformatf("resource named %s is not placed within the pool", name)); return; end r.precedence = p; endfunction virtual function int unsigned get_precedence(uvm_resource_base r); table_q_t rq; string name; int unsigned i; uvm_resource_base rsrc; if(r == null) begin uvm_report_warning("NULLRASRC", "attempting to get precedence of a null resource"); return uvm_resource_pool::get_default_precedence(); end name = r.get_name(); if(rtab.exists(name)) begin rq = rtab[name]; for (int iter=0; iter < rq.value.size(); iter++) begin rsrc = rq.value[iter]; if(rsrc == r) begin break; end end end if(r != rsrc) begin uvm_report_warning("NORSRC", $sformatf("resource named %s is not placed within the pool", name)); return uvm_resource_pool::get_default_precedence(); end return r.precedence; endfunction function uvm_resource_types::rsrc_q_t find_unused_resources(); table_q_t rq; uvm_resource_types::rsrc_q_t q = new; int unsigned i; uvm_resource_base r; uvm_resource_types::access_t a; int reads; int writes; foreach (rtab[name]) begin rq = rtab[name]; for (int iter=0; iter < rq.value.size(); iter++) begin uvm_resource_base rsrc_iter; rsrc_iter = rq.value[iter]; reads = 0; writes = 0; foreach(rsrc_iter.dbg.access[str]) begin a = rsrc_iter.dbg.access[str]; reads += a.read_count; writes += a.write_count; end if(writes > 0 && reads == 0) begin q.push_back(rsrc_iter); end end end return q; endfunction function void m_print_resource_element(uvm_printer printer, int unsigned iter, uvm_resource_base r, bit audit=0); string scope; printer.push_element($sformatf("[%0d]", iter), "uvm_resource", "-", "-"); void'(get_scope(r, scope)); printer.print_string("name", r.get_name()); printer.print_generic_element("value", r.m_value_type_name(), "", r.m_value_as_string()); printer.print_string("scope", scope); printer.print_field_int("precedence", get_precedence(r), 32, UVM_UNSIGNED); if (audit && (r.dbg!=null)) begin if (r.dbg.access.size()) begin printer.print_array_header("accesses", r.dbg.access.size(), "queue"); foreach(r.dbg.access[i]) begin printer.print_string($sformatf("[%s]", i), $sformatf("reads: %0d @ %0t writes: %0d @ %0t", r.dbg.access[i].read_count, r.dbg.access[i].read_time, r.dbg.access[i].write_count, r.dbg.access[i].write_time)); end printer.print_array_footer(r.dbg.access.size()); end end printer.pop_element(); endfunction : m_print_resource_element function void m_print_resources(uvm_printer printer, string name, table_q_t rq, bit audit = 0); printer.push_element(name, "uvm_shared#(uvm_resource_base[$])", $sformatf("%0d", rq.value.size())); for (int iter=0; iter < rq.value.size(); iter++) begin m_print_resource_element(printer, iter, rq.value[iter], audit); end printer.pop_element(); endfunction : m_print_resources function void print_resources(uvm_resource_types::rsrc_q_t rq, bit audit = 0); int unsigned i; string id; static uvm_tree_printer printer = new(); printer.flush(); if (rq == null) begin printer.print_generic_element("", "uvm_queue#(uvm_resource_base)", "", ""); end else begin printer.push_element(rq.get_name(), "uvm_queue#(uvm_resource_base)", $sformatf("%0d",rq.size()), uvm_object_value_str(rq)); for (int i = 0; i < rq.size(); i++) begin m_print_resource_element(printer, i, rq.get(i), audit); end printer.pop_element(); end begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "UVM/RESOURCE_POOL/PRINT_QUEUE") >= UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "UVM/RESOURCE_POOL/PRINT_QUEUE") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("UVM/RESOURCE_POOL/PRINT_QUEUE", printer.emit(), UVM_NONE, "t/uvm/src/base/uvm_resource_pool.svh", 1292, "", 1); end end endfunction function void dump(bit audit = 0, uvm_printer printer = null); string name; static uvm_tree_printer m_printer; if (m_printer == null) begin m_printer = new(); m_printer.set_type_name_enabled(1); end if (printer == null) begin printer = m_printer; end printer.flush(); printer.push_element("uvm_resource_pool", "", $sformatf("%0d",rtab.size()), ""); foreach (rtab[name]) begin m_print_resources(printer, name, rtab[name], audit); end printer.pop_element(); begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "UVM/RESOURCE/DUMP") >= UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "UVM/RESOURCE/DUMP") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("UVM/RESOURCE/DUMP", printer.emit(), UVM_NONE, "t/uvm/src/base/uvm_resource_pool.svh", 1332, "", 1); end end endfunction endclass `undef M__TABLE_Q `undef M__TABLE_GET `undef M__TABLE_NAME class uvm_resource #(type T=int) extends uvm_resource_base; typedef uvm_resource#(T) this_type; static this_type my_type = get_type(); protected T val; typedef uvm_object_registry#(this_type) type_id; virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction : get_object_type virtual function uvm_object create (string name=""); this_type tmp; if (name=="") begin tmp = new(); end else begin tmp = new(name); end return tmp; endfunction : create static function string type_name(); return $sformatf("uvm_resource#(%s)", $typename(T)); endfunction : type_name virtual function string get_type_name(); return $sformatf("uvm_resource#(%s)", $typename(T)); endfunction : get_type_name function new(string name="", string scope=""); super.new(name,scope); endfunction virtual function string m_value_type_name(); return $typename(T); endfunction : m_value_type_name virtual function string m_value_as_string(); return $sformatf("%p", val); endfunction : m_value_as_string static function this_type get_type(); if(my_type == null) begin my_type = new(); end return my_type; endfunction function uvm_resource_base get_type_handle(); return get_type(); endfunction function T read(uvm_object accessor = null); return do_read(accessor); endfunction virtual function T do_read(uvm_object accessor); if (uvm_resource_options::is_auditing()) begin record_read_access(accessor); end return val; endfunction : do_read function void write(T t, uvm_object accessor = null); do_write(t, accessor); endfunction virtual function void do_write(T t, uvm_object accessor); if(is_read_only()) begin uvm_report_error("resource", $sformatf("resource %s is read only -- cannot modify", get_name())); return; end if(val == t) begin return; end if (uvm_resource_options::is_auditing()) begin record_write_access(accessor); end val = t; modified = 1; endfunction : do_write static function this_type get_highest_precedence(ref uvm_resource_types::rsrc_q_t q); this_type rsrc; this_type r; uvm_resource_types::rsrc_q_t tq; uvm_resource_base rb; uvm_resource_pool rp = uvm_resource_pool::get(); if(q.size() == 0) begin return null; end tq = new(); rsrc = null; for(int i = 0; i < q.size(); ++i) begin if($cast(r, q.get(i))) begin tq.push_back(r) ; end end rb = rp.get_highest_precedence(tq); if (!$cast(rsrc, rb)) begin return null; end return rsrc; endfunction function void set_priority (uvm_resource_types::priority_e pri); uvm_resource_pool rp = uvm_resource_pool::get(); rp.set_priority(this, pri); endfunction static function this_type get_by_name(string scope, string name, bit rpterr = 1); uvm_resource_pool rp = uvm_resource_pool::get(); uvm_resource_base rsrc_base; this_type rsrc; string msg; rsrc_base = rp.get_by_name(scope, name, my_type, rpterr); if(rsrc_base == null) return null; if(!$cast(rsrc, rsrc_base)) begin if(rpterr) begin $sformat(msg, "Resource with name %s in scope %s has incorrect type", name, scope); begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "RSRCTYPE") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "RSRCTYPE") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("RSRCTYPE", msg, uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_resource.svh", 290, "", 1); end end; end return null; end return rsrc; endfunction static function this_type get_by_type(string scope = "", uvm_resource_base type_handle); uvm_resource_pool rp = uvm_resource_pool::get(); uvm_resource_base rsrc_base; this_type rsrc; string msg; if(type_handle == null) return null; rsrc_base = rp.get_by_type(scope, type_handle); if(rsrc_base == null) return null; if(!$cast(rsrc, rsrc_base)) begin $sformat(msg, "Resource with specified type handle in scope %s was not located", scope); begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "RSRCNF") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "RSRCNF") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("RSRCNF", msg, uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_resource.svh", 317, "", 1); end end; return null; end return rsrc; endfunction endclass `define UVM_RESOURCE_GET_FCNS(base_type) \ static function this_subtype get_by_name(string scope, string name, bit rpterr = 1); \ this_subtype t; \ uvm_resource_base b = uvm_resource#(base_type)::get_by_name(scope, name, rpterr); \ if(!$cast(t, b)) \ `uvm_fatal("BADCAST", "cannot cast resource to resource subtype") \ return t; \ endfunction \ \ static function this_subtype get_by_type(string scope = "", \ uvm_resource_base type_handle); \ this_subtype t; \ uvm_resource_base b = uvm_resource#(base_type)::get_by_type(scope, type_handle); \ if(!$cast(t, b)) \ `uvm_fatal("BADCAST", "cannot cast resource to resource subtype") \ return t; \ endfunction class uvm_int_rsrc extends uvm_resource #(int); typedef uvm_int_rsrc this_subtype; function new(string name, string s = "*"); uvm_resource_pool rp; super.new(name); rp = uvm_resource_pool::get(); rp.set_scope(this, s); endfunction function string convert2string(); string s; $sformat(s, "%0d", read()); return s; endfunction endclass class uvm_string_rsrc extends uvm_resource #(string); typedef uvm_string_rsrc this_subtype; function new(string name, string s = "*"); uvm_resource_pool rp; super.new(name); rp = uvm_resource_pool::get(); rp.set_scope(this, s); endfunction function string convert2string(); return read(); endfunction endclass class uvm_obj_rsrc extends uvm_resource #(uvm_object); typedef uvm_obj_rsrc this_subtype; function new(string name, string s = "*"); uvm_resource_pool rp; super.new(name); rp = uvm_resource_pool::get(); rp.set_scope(this, s); endfunction endclass class uvm_bit_rsrc #(int unsigned N=1) extends uvm_resource #(bit[N-1:0]); typedef uvm_bit_rsrc#(N) this_subtype; function new(string name, string s = "*"); uvm_resource_pool rp; super.new(name); rp = uvm_resource_pool::get(); rp.set_scope(this, s); endfunction function string convert2string(); string s; $sformat(s, "%0b", read()); return s; endfunction endclass class uvm_byte_rsrc #(int unsigned N=1) extends uvm_resource #(bit[7:0][N-1:0]); typedef uvm_byte_rsrc#(N) this_subtype; function new(string name, string s = "*"); uvm_resource_pool rp; super.new(name); rp = uvm_resource_pool::get(); rp.set_scope(this, s); endfunction function string convert2string(); string s; $sformat(s, "%0x", read()); return s; endfunction endclass typedef class uvm_resource_db_options; typedef class uvm_cmdline_processor; typedef class uvm_resource_db_default_implementation_t; virtual class uvm_resource_db_implementation_t #(type T=uvm_object) extends uvm_object; typedef uvm_resource #(T) rsrc_t; typedef uvm_abstract_object_registry #(uvm_resource_db_implementation_t #(T)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction local static uvm_resource_db_implementation_t #(T) m_rsrc_db_imp; static function void set_imp(uvm_resource_db_implementation_t #(T) imp = null); if (imp == null) begin uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory = cs.get_factory(); if (factory.find_override_by_type(uvm_resource_db_implementation_t#(T)::get_type(),"") == uvm_resource_db_implementation_t#(T)::get_type()) begin imp = uvm_resource_db_default_implementation_t #(T)::type_id::create(); end else begin imp = uvm_resource_db_implementation_t #(T)::type_id::create(); end end m_rsrc_db_imp = imp; endfunction : set_imp static function uvm_resource_db_implementation_t #(T) get_imp (); if (m_rsrc_db_imp == null) begin set_imp(); end return m_rsrc_db_imp; endfunction : get_imp pure virtual function rsrc_t get_by_type(string scope); pure virtual function rsrc_t get_by_name(string scope, string name, bit rpterr); pure virtual function rsrc_t set_default(string scope, string name); pure virtual function void show_msg(string id, string rtype, string action, string scope, string name, uvm_object accessor, rsrc_t rsrc); pure virtual function void set(string scope, string name, T val, uvm_object accessor); pure virtual function void set_anonymous(string scope, T val, uvm_object accessor); pure virtual function void set_override(string scope, string name, T val, uvm_object accessor); pure virtual function void set_override_type(string scope, string name, T val, uvm_object accessor); pure virtual function void set_override_name(string scope, string name, T val, uvm_object accessor); pure virtual function bit read_by_name(string scope, string name, inout T val, input uvm_object accessor); pure virtual function bit read_by_type(string scope, inout T val, input uvm_object accessor); pure virtual function bit write_by_name(string scope, string name, T val, uvm_object accessor); pure virtual function bit write_by_type(string scope, T val, uvm_object accessor); endclass class uvm_resource_db_default_implementation_t #(type T=uvm_object) extends uvm_resource_db_implementation_t #(T); typedef uvm_resource #(T) rsrc_t; typedef uvm_object_registry #(uvm_resource_db_default_implementation_t #(T)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_resource_db_default_implementation_t #(T) tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction function new(string name = "uvm_resource_db_default_implementation_t"); super.new(); endfunction : new virtual function rsrc_t get_by_type(string scope); uvm_resource_pool rp = uvm_resource_pool::get(); uvm_resource_base rsrc_base; rsrc_t rsrc; string msg; uvm_resource_base type_handle = rsrc_t::get_type(); if(type_handle == null) begin return null; end rsrc_base = rp.get_by_type(scope, type_handle); if(!$cast(rsrc, rsrc_base)) begin $sformat(msg, "Resource with specified type handle in scope %s was not located", scope); begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "RSRCNF") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "RSRCNF") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("RSRCNF", msg, uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_resource_db_implementation.svh", 246, "", 1); end end return null; end return rsrc; endfunction : get_by_type virtual function rsrc_t get_by_name(string scope, string name, bit rpterr); uvm_resource_pool rp = uvm_resource_pool::get(); uvm_resource_base rsrc_base; rsrc_t rsrc; string msg; rsrc_base = rp.get_by_name(scope, name, rsrc_t::get_type(), rpterr); if(rsrc_base == null) begin return null; end if(!$cast(rsrc, rsrc_base)) begin if(rpterr) begin $sformat(msg, "Resource with name %s in scope %s has incorrect type", name, scope); begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "RSRCTYPE") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "RSRCTYPE") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("RSRCTYPE", msg, uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_resource_db_implementation.svh", 280, "", 1); end end end return null; end return rsrc; endfunction : get_by_name virtual function rsrc_t set_default(string scope, string name); rsrc_t r; uvm_resource_pool rp = uvm_resource_pool::get(); r = new(name); rp.set_scope(r, scope); return r; endfunction : set_default virtual function void show_msg(string id, string rtype, string action, string scope, string name, uvm_object accessor, rsrc_t rsrc); T foo; string msg=$typename(foo); $sformat(msg, "%s scope='%s' name='%s' (type %s) %s accessor=%s = %s", rtype,scope,name, msg,action, (accessor != null) ? accessor.get_full_name() : "", rsrc==null?"null (failed lookup)":rsrc.convert2string()); begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, id) >= UVM_LOW) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, id) != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info(id, msg, UVM_LOW, "t/uvm/src/base/uvm_resource_db_implementation.svh", 323, "", 1); end end endfunction : show_msg virtual function void set(string scope, string name, T val, uvm_object accessor); uvm_resource_pool rp = uvm_resource_pool::get(); rsrc_t rsrc = new(name); rsrc.write(val, accessor); rp.set_scope(rsrc, scope); if(uvm_resource_db_options::is_tracing()) begin show_msg("RSRCDB/SET", "Resource","set", scope, name, accessor, rsrc); end endfunction : set virtual function void set_anonymous(string scope, T val, uvm_object accessor); uvm_resource_pool rp = uvm_resource_pool::get(); rsrc_t rsrc = new(""); rsrc.write(val, accessor); rp.set_scope(rsrc, scope); if(uvm_resource_db_options::is_tracing()) begin show_msg("RSRCDB/SETANON","Resource", "set", scope, "", accessor, rsrc); end endfunction : set_anonymous virtual function void set_override(string scope, string name, T val, uvm_object accessor); uvm_resource_pool rp = uvm_resource_pool::get(); rsrc_t rsrc = new(name); rsrc.write(val, accessor); rp.set_override(rsrc, scope); if(uvm_resource_db_options::is_tracing()) begin show_msg("RSRCDB/SETOVRD", "Resource","set", scope, name, accessor, rsrc); end endfunction : set_override virtual function void set_override_type(string scope, string name, T val, uvm_object accessor); uvm_resource_pool rp = uvm_resource_pool::get(); rsrc_t rsrc = new(name); rsrc.write(val, accessor); rp.set_type_override(rsrc, scope); if(uvm_resource_db_options::is_tracing()) begin show_msg("RSRCDB/SETOVRDTYP","Resource", "set", scope, name, accessor, rsrc); end endfunction : set_override_type virtual function void set_override_name(string scope, string name, T val, uvm_object accessor); uvm_resource_pool rp = uvm_resource_pool::get(); rsrc_t rsrc = new(name); rsrc.write(val, accessor); rp.set_name_override(rsrc, scope); if(uvm_resource_db_options::is_tracing()) begin show_msg("RSRCDB/SETOVRDNAM","Resource", "set", scope, name, accessor, rsrc); end endfunction : set_override_name virtual function bit read_by_name(string scope, string name, inout T val, input uvm_object accessor); rsrc_t rsrc = get_by_name(scope, name, 1); if(uvm_resource_db_options::is_tracing()) begin show_msg("RSRCDB/RDBYNAM","Resource", "read", scope, name, accessor, rsrc); end if(rsrc == null) begin return 0; end val = rsrc.read(accessor); return 1; endfunction : read_by_name virtual function bit read_by_type(input string scope, inout T val, input uvm_object accessor); rsrc_t rsrc = get_by_type(scope); if(uvm_resource_db_options::is_tracing()) begin show_msg("RSRCDB/RDBYTYP", "Resource","read", scope, "", accessor, rsrc); end if(rsrc == null) begin return 0; end val = rsrc.read(accessor); return 1; endfunction : read_by_type virtual function bit write_by_name(string scope, string name, T val, uvm_object accessor); rsrc_t rsrc = get_by_name(scope, name, 1); if(uvm_resource_db_options::is_tracing()) begin show_msg("RSRCDB/WR","Resource", "written", scope, name, accessor, rsrc); end if(rsrc == null) begin return 0; end rsrc.write(val, accessor); return 1; endfunction : write_by_name virtual function bit write_by_type(string scope, T val, uvm_object accessor); rsrc_t rsrc = get_by_type(scope); if(uvm_resource_db_options::is_tracing()) begin show_msg("RSRCDB/WRTYP", "Resource","written", scope, "", accessor, rsrc); end if(rsrc == null) begin return 0; end rsrc.write(val, accessor); return 1; endfunction : write_by_type endclass class uvm_resource_db #(type T=uvm_object) extends uvm_void; typedef uvm_resource #(T) rsrc_t; protected function new(); endfunction static function rsrc_t get_by_type(string scope); uvm_resource_db_implementation_t #(T) imp; imp = uvm_resource_db_implementation_t #(T)::get_imp(); return imp.get_by_type(scope); endfunction static function rsrc_t get_by_name(string scope, string name, bit rpterr=1); uvm_resource_db_implementation_t #(T) imp; imp = uvm_resource_db_implementation_t #(T)::get_imp(); return imp.get_by_name(scope, name, rpterr); endfunction static function rsrc_t set_default(string scope, string name); uvm_resource_db_implementation_t #(T) imp; imp = uvm_resource_db_implementation_t #(T)::get_imp(); return imp.set_default(scope, name); endfunction static function void set(input string scope, input string name, T val, input uvm_object accessor = null); uvm_resource_db_implementation_t #(T) imp; imp = uvm_resource_db_implementation_t #(T)::get_imp(); imp.set(scope, name, val, accessor); endfunction static function void set_anonymous(input string scope, T val, input uvm_object accessor = null); uvm_resource_db_implementation_t #(T) imp; imp = uvm_resource_db_implementation_t #(T)::get_imp(); imp.set_anonymous(scope, val, accessor); endfunction static function void set_override(input string scope, input string name, T val, uvm_object accessor = null); uvm_resource_db_implementation_t #(T) imp; imp = uvm_resource_db_implementation_t #(T)::get_imp(); imp.set_override(scope, name, val, accessor); endfunction static function void set_override_type(input string scope, input string name, T val, uvm_object accessor = null); uvm_resource_db_implementation_t #(T) imp; imp = uvm_resource_db_implementation_t #(T)::get_imp(); imp.set_override_type(scope, name, val, accessor); endfunction static function void set_override_name(input string scope, input string name, T val, uvm_object accessor = null); uvm_resource_db_implementation_t #(T) imp; imp = uvm_resource_db_implementation_t #(T)::get_imp(); imp.set_override_name(scope, name, val, accessor); endfunction static function bit read_by_name(input string scope, input string name, inout T val, input uvm_object accessor = null); uvm_resource_db_implementation_t #(T) imp; imp = uvm_resource_db_implementation_t #(T)::get_imp(); return imp.read_by_name(scope, name, val, accessor); endfunction static function bit read_by_type(input string scope, inout T val, input uvm_object accessor = null); uvm_resource_db_implementation_t #(T) imp; imp = uvm_resource_db_implementation_t #(T)::get_imp(); return imp.read_by_type(scope, val, accessor); endfunction static function bit write_by_name(input string scope, input string name, input T val, input uvm_object accessor = null); uvm_resource_db_implementation_t #(T) imp; imp = uvm_resource_db_implementation_t #(T)::get_imp(); return imp.write_by_name(scope, name, val, accessor); endfunction static function bit write_by_type(input string scope, input T val, input uvm_object accessor = null); uvm_resource_db_implementation_t #(T) imp; imp = uvm_resource_db_implementation_t #(T)::get_imp(); return imp.write_by_type(scope, val, accessor); endfunction static function void dump(); uvm_resource_pool rp = uvm_resource_pool::get(); rp.dump(); endfunction endclass class uvm_resource_db_options; static local bit ready; static local bit tracing; static function void turn_on_tracing(); if (!ready) begin init(); end tracing = 1; endfunction static function void turn_off_tracing(); if (!ready) begin init(); end tracing = 0; endfunction static function bit is_tracing(); if (!ready) begin init(); end return tracing; endfunction static local function void init(); uvm_cmdline_processor clp; string trace_args[$]; clp = uvm_cmdline_processor::get_inst(); if (clp.get_arg_matches("+UVM_RESOURCE_DB_TRACE", trace_args)) begin tracing = 1; end ready = 1; endfunction endclass typedef class uvm_phase; class m_uvm_waiter; string inst_name; string field_name; event trigger; function new (string inst_name, string field_name); this.inst_name = inst_name; this.field_name = field_name; endfunction endclass typedef class uvm_root; typedef class uvm_config_db_options; typedef class uvm_config_db_default_implementation_t; virtual class uvm_config_db_implementation_t #(type T=int) extends uvm_object; typedef uvm_resource #(T) rsrc_t; typedef uvm_abstract_object_registry #(uvm_config_db_implementation_t #(T)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction local static uvm_config_db_implementation_t #(T) m_config_db_imp; static function void set_imp(uvm_config_db_implementation_t #(T) imp = null); if (imp == null) begin uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory = cs.get_factory(); if (factory.find_override_by_type(uvm_config_db_implementation_t#(T)::get_type(),"") == uvm_config_db_implementation_t#(T)::get_type()) begin imp = uvm_config_db_default_implementation_t #(T)::type_id::create(); end else begin imp = uvm_config_db_implementation_t #(T)::type_id::create(); end end m_config_db_imp = imp ; endfunction : set_imp static function uvm_config_db_implementation_t #(T) get_imp(); if (m_config_db_imp == null) begin set_imp(); end return m_config_db_imp; endfunction : get_imp pure virtual function bit get (uvm_component cntxt, string inst_name, string field_name, inout T value); pure virtual function void set(string cntxt_name, string inst_name, string field_name, T value, int cntxt_depth, uvm_pool#(string, uvm_resource#(T)) pool, uvm_component cntxt); pure virtual function bit exists(uvm_component cntxt, string inst_name, string field_name, bit rpterr); pure virtual task wait_modified(uvm_component cntxt, string inst_name, string field_name); pure virtual function void trigger_modified(string inst_name, string field_name); pure virtual function void show_msg(string id, string rtype, string action, string scope, string name, uvm_object accessor, rsrc_t rsrc); endclass class uvm_config_db_default_implementation_t #(type T=int) extends uvm_config_db_implementation_t#(T); function new (string name = "uvm_config_db_default_implementation"); super.new(); endfunction : new typedef uvm_object_registry #(uvm_config_db_default_implementation_t #(T)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_config_db_default_implementation_t #(T) tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction virtual function bit get (uvm_component cntxt, string inst_name, string field_name, inout T value); uvm_resource#(T) r; uvm_resource_pool rp = uvm_resource_pool::get(); uvm_resource_types::rsrc_q_t rq; uvm_coreservice_t cs = uvm_coreservice_t::get(); if(cntxt == null) begin cntxt = cs.get_root(); end if(inst_name == "") begin inst_name = cntxt.get_full_name(); end else if(cntxt.get_full_name() != "") begin inst_name = {cntxt.get_full_name(), ".", inst_name}; end rq = rp.lookup_name(inst_name, field_name, uvm_resource#(T)::get_type(), 0); r = uvm_resource#(T)::get_highest_precedence(rq); if(uvm_config_db_options::is_tracing()) begin show_msg("CFGDB/GET", "Configuration","read", inst_name, field_name, cntxt, r); end if(r == null) begin return 0; end value = r.read(cntxt); return 1; endfunction : get static local uvm_queue#(m_uvm_waiter) m_waiters[string]; virtual task wait_modified(uvm_component cntxt, string inst_name, string field_name); process p = process::self(); string rstate; m_uvm_waiter waiter; uvm_coreservice_t cs; if (p != null) begin rstate = p.get_randstate(); end cs = uvm_coreservice_t::get(); if(cntxt == null) begin cntxt = cs.get_root(); end if(cntxt != cs.get_root()) begin if(inst_name != "") begin inst_name = {cntxt.get_full_name(),".",inst_name}; end else begin inst_name = cntxt.get_full_name(); end end waiter = new(inst_name, field_name); if(!m_waiters.exists(field_name)) begin m_waiters[field_name] = new; end m_waiters[field_name].push_back(waiter); if (p != null) begin p.set_randstate(rstate); end @waiter.trigger; for(int i=0; iw.trigger; end end end endfunction : trigger_modified virtual function void set(string cntxt_name, string inst_name, string field_name, T value, int cntxt_depth, uvm_pool#(string, uvm_resource#(T)) pool, uvm_component cntxt); uvm_root top; uvm_phase curr_phase; uvm_resource#(T) r; string lookup; string rstate; uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_resource_pool rp = cs.get_resource_pool(); int unsigned precedence; process p = process::self(); if (p != null) begin rstate = p.get_randstate(); end top = cs.get_root(); curr_phase = top.m_current_phase; if (cntxt == null) begin cntxt = top; end if (inst_name == "") begin inst_name = cntxt.get_full_name(); end else if(cntxt.get_full_name() != "") begin string slash_or_blank = "" ; string close_or_blank = "" ; string separator = "." ; if (inst_name[0] == "/" && inst_name.len()>2 && inst_name[inst_name.len()-1] == "/") begin slash_or_blank = "/"; close_or_blank = ")/" ; separator = "\.(" ; inst_name = inst_name.substr(1,inst_name.len()-2); end inst_name = {slash_or_blank, cntxt.get_full_name(), separator, inst_name, close_or_blank}; end lookup = {inst_name, "__M_UVM__", field_name}; if(!pool.exists(lookup)) begin r = new(field_name); rp.set_scope(r, inst_name); pool.add(lookup, r); end else begin r = pool.get(lookup); end if(curr_phase != null && curr_phase.get_name() == "build") begin precedence = cs.get_resource_pool_default_precedence() - (cntxt.get_depth()); end else begin precedence = cs.get_resource_pool_default_precedence(); end rp.set_precedence(r, precedence); r.write(value, cntxt); rp.set_priority_name(r, uvm_resource_types::PRI_HIGH); trigger_modified(inst_name, field_name); if (p != null) begin p.set_randstate(rstate); end if(uvm_config_db_options::is_tracing()) begin show_msg("CFGDB/SET", "Configuration","set", inst_name, field_name, cntxt, r); end endfunction : set virtual function bit exists(uvm_component cntxt, string inst_name, string field_name, bit rpterr); uvm_coreservice_t cs = uvm_coreservice_t::get(); if(cntxt == null) begin cntxt = cs.get_root(); end if(inst_name == "") begin inst_name = cntxt.get_full_name(); end else if(cntxt.get_full_name() != "") begin inst_name = {cntxt.get_full_name(), ".", inst_name}; end return (uvm_resource_db#(T)::get_by_name(inst_name,field_name,rpterr) != null); endfunction : exists virtual function void show_msg(string id, string rtype, string action, string scope, string name, uvm_object accessor, rsrc_t rsrc); T foo; string msg=$typename(foo); $sformat(msg, "%s scope='%s' name='%s' (type %s) %s accessor=%s = %s", rtype,scope,name, msg,action, (accessor != null) ? accessor.get_full_name() : "", rsrc==null?"null (failed lookup)":rsrc.convert2string()); begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, id) >= UVM_LOW) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, id) != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info(id, msg, UVM_LOW, "t/uvm/src/base/uvm_config_db_implementation.svh", 485, "", 1); end end endfunction : show_msg endclass : uvm_config_db_default_implementation_t typedef class uvm_phase; typedef class uvm_config_db_options; class uvm_config_db#(type T=int) extends uvm_resource_db#(T); static uvm_pool#(string,uvm_resource#(T)) m_rsc[uvm_component]; static function bit get(uvm_component cntxt, string inst_name, string field_name, inout T value); uvm_config_db_implementation_t #(T) imp; imp = uvm_config_db_implementation_t #(T)::get_imp(); return imp.get(cntxt, inst_name, field_name, value); endfunction static function void set(uvm_component cntxt, string inst_name, string field_name, T value); uvm_pool#(string,uvm_resource#(T)) pool; uvm_config_db_implementation_t #(T) imp; uvm_coreservice_t cs ; imp = uvm_config_db_implementation_t #(T)::get_imp(); cs = uvm_coreservice_t::get(); if(cntxt == null) begin cntxt = cs.get_root(); end if(!m_rsc.exists(cntxt)) begin m_rsc[cntxt] = new; end pool = m_rsc[cntxt]; imp.set(cntxt.get_full_name(), inst_name, field_name, value, cntxt.get_depth(), pool, cntxt); endfunction static function bit exists(uvm_component cntxt, string inst_name, string field_name, bit spell_chk=0); uvm_config_db_implementation_t #(T) imp; imp = uvm_config_db_implementation_t #(T)::get_imp(); return imp.exists(cntxt, inst_name, field_name, spell_chk); endfunction static task wait_modified(uvm_component cntxt, string inst_name, string field_name); uvm_config_db_implementation_t #(T) imp; imp = uvm_config_db_implementation_t #(T)::get_imp(); imp.wait_modified(cntxt, inst_name, field_name); endtask endclass typedef uvm_config_db#(uvm_bitstream_t) uvm_config_int ; typedef uvm_config_db#(string) uvm_config_string ; typedef uvm_config_db#(uvm_object) uvm_config_object ; typedef uvm_config_db#(uvm_object_wrapper) uvm_config_wrapper ; class uvm_config_db_options; static local bit ready; static local bit tracing; static function void turn_on_tracing(); if (!ready) begin init(); end tracing = 1; endfunction static function void turn_off_tracing(); if (!ready) begin init(); end tracing = 0; endfunction static function bit is_tracing(); if (!ready) begin init(); end return tracing; endfunction static local function void init(); uvm_cmdline_processor clp; string trace_args[$]; clp = uvm_cmdline_processor::get_inst(); if (clp.get_arg_matches("+UVM_CONFIG_DB_TRACE", trace_args)) begin tracing = 1; end ready = 1; endfunction endclass typedef class uvm_root; virtual class uvm_policy extends uvm_object; typedef enum { NEVER, STARTED, FINISHED } recursion_state_e; local uvm_object m_extensions[uvm_object_wrapper]; local uvm_object m_policy_stack[$]; function new (string name=""); super.new(name); endfunction virtual function void flush(); m_policy_stack.delete(); endfunction virtual function bit extension_exists( uvm_object_wrapper ext_type ); if (m_extensions.exists(ext_type)) begin extension_exists = 1; end else begin extension_exists = 0; end endfunction virtual function uvm_object set_extension( uvm_object extension ); uvm_object m_set_extension; if ( extension == null) begin uvm_report_fatal("NULLEXT", "Attempting to set null extension ", UVM_NONE); end if(m_extensions.exists(extension.get_object_type())) begin m_set_extension = m_extensions[extension.get_object_type()] ; m_extensions[extension.get_object_type()] = extension; return m_set_extension; end else begin m_extensions[extension.get_object_type()] = extension; return null; end endfunction virtual function uvm_object get_extension(uvm_object_wrapper ext_type ); if (m_extensions.exists(ext_type)) begin return m_extensions[ext_type]; end else begin return null; end endfunction virtual function void clear_extension( uvm_object_wrapper ext_type ); m_extensions.delete(ext_type); endfunction virtual function void clear_extensions(); m_extensions.delete(); endfunction virtual function void push_active_object( uvm_object obj ); if(obj != null) begin m_policy_stack.push_front(obj); end else begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM_POLICY_PUSHNULL") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM_POLICY_PUSHNULL") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM_POLICY_PUSHNULL", "Attempting to push an null object push_active_object onto the policy stack", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_policy.svh", 176, "", 1); end end end endfunction virtual function uvm_object pop_active_object(); uvm_object m_tmp; if(m_policy_stack.size() != 0) begin m_tmp = m_policy_stack.pop_front(); return m_tmp; end else begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "UVM_POLICY_EMPTY_POPACTIVE_OBJECT") >= UVM_DEBUG) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "UVM_POLICY_EMPTY_POPACTIVE_OBJECT") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("UVM_POLICY_EMPTY_POPACTIVE_OBJECT", "Attempting to pop an empty policy stack", UVM_DEBUG, "t/uvm/src/base/uvm_policy.svh", 193, "", 1); end end end endfunction virtual function uvm_object get_active_object(); if(m_policy_stack.size() != 0) begin return m_policy_stack[0]; end endfunction virtual function int unsigned get_active_object_depth(); return m_policy_stack.size(); endfunction endclass class uvm_field_op extends uvm_object; typedef uvm_object_registry#(uvm_field_op,"uvm_field_op") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_field_op tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_field_op"; endfunction : type_name virtual function string get_type_name(); return "uvm_field_op"; endfunction : get_type_name local uvm_policy m_policy; local bit m_user_hook; local uvm_object m_object; local bit m_is_set; local uvm_field_flag_t m_op_type; function new (string name=""); super.new(name); m_is_set = 1'b0; m_user_hook = 1'b1; endfunction virtual function void set( uvm_field_flag_t op_type, uvm_policy policy = null, uvm_object rhs = null); string matching_ops[$]; if (op_type & UVM_COPY) begin matching_ops.push_back("UVM_COPY"); end if (op_type & UVM_COMPARE) begin matching_ops.push_back("UVM_COMPARE"); end if (op_type & UVM_PRINT) begin matching_ops.push_back("UVM_PRINT"); end if (op_type & UVM_RECORD) begin matching_ops.push_back("UVM_RECORD"); end if (op_type & UVM_PACK) begin matching_ops.push_back("UVM_PACK"); end if (op_type & UVM_UNPACK) begin matching_ops.push_back("UVM_UNPACK"); end if (op_type & UVM_SET) begin matching_ops.push_back("UVM_SET"); end if (matching_ops.size() > 1) begin string msg_queue[$]; msg_queue.push_back("("); foreach (matching_ops[i]) begin msg_queue.push_back(matching_ops[i]); if (i != matching_ops.size() - 1) begin msg_queue.push_back(","); end end msg_queue.push_back(")"); begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM/FIELD_OP/SET_BAD_OP_TYPE") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM/FIELD_OP/SET_BAD_OP_TYPE") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM/FIELD_OP/SET_BAD_OP_TYPE", {"set() was passed op_type matching multiple operations: ", uvm_pkg::m_uvm_string_queue_join(msg_queue)}, uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_field_op.svh", 117, "", 1); end end end if(m_is_set == 0) begin m_op_type = op_type; m_policy = policy; m_object = rhs; m_is_set = 1'b1; end else begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM/FIELD_OP/SET") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM/FIELD_OP/SET") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM/FIELD_OP/SET", "Attempting to set values in policy without flushing", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_field_op.svh", 127, "", 1); end end end endfunction virtual function string get_op_name(); case(m_op_type) UVM_COPY : begin return "copy"; end UVM_COMPARE : begin return "compare"; end UVM_PRINT : begin return "print"; end UVM_RECORD : begin return "record"; end UVM_PACK : begin return "pack"; end UVM_UNPACK : begin return "unpack"; end UVM_SET : begin return "set"; end default: begin return ""; end endcase endfunction virtual function uvm_field_flag_t get_op_type(); if(m_is_set == 1'b1) begin return m_op_type; end else begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM/FIELD_OP/GET_OP_TYPE") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM/FIELD_OP/GET_OP_TYPE") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM/FIELD_OP/GET_OP_TYPE", "Calling get_op_type() before calling set() is not allowed", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_field_op.svh", 177, "", 1); end end end endfunction virtual function uvm_policy get_policy(); if(m_is_set == 1'b1) begin return m_policy; end else begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM/FIELD_OP/GET_POLICY") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM/FIELD_OP/GET_POLICY") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM/FIELD_OP/GET_POLICY", "Attempting to call get_policy() before calling set() is not allowed", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_field_op.svh", 190, "", 1); end end end endfunction virtual function uvm_object get_rhs(); if(m_is_set == 1'b1) begin return m_object; end else begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM/FIELD_OP/GET_RHS") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM/FIELD_OP/GET_RHS") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM/FIELD_OP/GET_RHS", "Calling get_rhs() before calling set() is not allowed", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_field_op.svh", 202, "", 1); end end end endfunction function bit user_hook_enabled(); if(m_is_set == 1'b1) begin return m_user_hook; end else begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM/FIELD_OP/GET_USER_HOOK") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM/FIELD_OP/GET_USER_HOOK") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM/FIELD_OP/GET_USER_HOOK", "Attempting to get_user_hook before calling set() is not allowed", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_field_op.svh", 214, "", 1); end end end endfunction function void disable_user_hook(); m_user_hook = 1'b0; endfunction static uvm_field_op m_recycled_op[$] ; virtual function void flush(); m_policy = null; m_object = null; m_user_hook = 1'b1; m_is_set = 0; endfunction function void m_recycle(); this.flush(); m_recycled_op.push_back(this); endfunction : m_recycle static function uvm_field_op m_get_available_op() ; uvm_field_op field_op ; if (m_recycled_op.size() > 0) begin field_op = m_recycled_op.pop_back() ; end else begin field_op = uvm_field_op::type_id::create("field_op"); end return field_op ; endfunction endclass class uvm_copier extends uvm_policy; typedef uvm_object_registry#(uvm_copier,"uvm_copier") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_copier tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_copier"; endfunction : type_name virtual function string get_type_name(); return "uvm_copier"; endfunction : get_type_name uvm_recursion_policy_enum policy = UVM_DEFAULT_POLICY; function new(string name="uvm_copier") ; super.new(name); endfunction recursion_state_e m_recur_states[uvm_object ][uvm_object ][uvm_recursion_policy_enum ]; virtual function void copy_object ( uvm_object lhs, uvm_object rhs); uvm_field_op field_op; if (get_recursion_policy() == UVM_REFERENCE) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM_COPY_POLICY") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM_COPY_POLICY") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM_COPY_POLICY", "Attempting to make a copy of a object which is a reference", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_copier.svh", 92, "", 1); end end return; end if (rhs == null || lhs == null) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM_COPY_NULL_OBJ") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM_COPY_NULL_OBJ") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM_COPY_NULL_OBJ", "Attempting to make a copy of a object with null src/target", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_copier.svh", 97, "", 1); end end return; end push_active_object(lhs); m_recur_states[rhs][lhs][get_recursion_policy()] = uvm_policy::STARTED; field_op = uvm_field_op::m_get_available_op() ; field_op.set(UVM_COPY,this,rhs); lhs.do_execute_op(field_op); if (field_op.user_hook_enabled()) begin lhs.do_copy(rhs); end field_op.m_recycle(); m_recur_states[rhs][lhs][get_recursion_policy()] = uvm_policy::FINISHED; void'(pop_active_object()); endfunction virtual function recursion_state_e object_copied( uvm_object lhs, uvm_object rhs, uvm_recursion_policy_enum recursion ); if (!m_recur_states.exists(rhs)) begin return NEVER ; end else if (!m_recur_states[rhs].exists(lhs)) begin return NEVER ; end else if (!m_recur_states[rhs][lhs].exists(recursion)) begin return NEVER ; end else begin return m_recur_states[rhs][lhs][recursion]; end endfunction function void flush(); m_recur_states.delete(); endfunction virtual function void set_recursion_policy (uvm_recursion_policy_enum policy); this.policy = policy; endfunction virtual function uvm_recursion_policy_enum get_recursion_policy(); return policy; endfunction function int unsigned get_num_copies(uvm_object rhs); if (m_recur_states.exists(rhs)) begin return m_recur_states[rhs].size(); end return 0; endfunction : get_num_copies function int get_first_copy(uvm_object rhs, ref uvm_object lhs); if (m_recur_states.exists(rhs)) return m_recur_states[rhs].first(lhs); return 0; endfunction : get_first_copy function int get_next_copy(uvm_object rhs, ref uvm_object lhs); if (m_recur_states.exists(rhs)) return m_recur_states[rhs].next(lhs); return 0; endfunction : get_next_copy function int get_last_copy(uvm_object rhs, ref uvm_object lhs); if (m_recur_states.exists(rhs)) return m_recur_states[rhs].last(lhs); return 0; endfunction : get_last_copy function int get_prev_copy(uvm_object rhs, ref uvm_object lhs); if (m_recur_states.exists(rhs)) return m_recur_states[rhs].prev(lhs); return 0; endfunction : get_prev_copy static function void set_default (uvm_copier copier) ; uvm_coreservice_t coreservice ; coreservice = uvm_coreservice_t::get() ; coreservice.set_default_copier(copier) ; endfunction static function uvm_copier get_default () ; uvm_coreservice_t coreservice ; coreservice = uvm_coreservice_t::get() ; return coreservice.get_default_copier() ; endfunction endclass typedef class m_uvm_printer_knobs; typedef class uvm_printer_element; typedef class uvm_structure_proxy; typedef struct { int level; string name; string type_name; string size; string val; } uvm_printer_row_info; virtual class uvm_printer extends uvm_policy; typedef uvm_abstract_object_registry#(uvm_printer,"uvm_printer") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_printer"; endfunction : type_name virtual function string get_type_name(); return "uvm_printer"; endfunction : get_type_name extern function new(string name="") ; bit m_flushed ; m_uvm_printer_knobs knobs ; protected function m_uvm_printer_knobs get_knobs() ; return knobs; endfunction extern static function void set_default(uvm_printer printer) ; extern static function uvm_printer get_default() ; extern virtual function void print_field (string name, uvm_bitstream_t value, int size, uvm_radix_enum radix=UVM_NORADIX, byte scope_separator=".", string type_name=""); virtual function void print_int (string name, uvm_bitstream_t value, int size, uvm_radix_enum radix=UVM_NORADIX, byte scope_separator=".", string type_name=""); print_field (name, value, size, radix, scope_separator, type_name); endfunction extern virtual function void print_field_int (string name, uvm_integral_t value, int size, uvm_radix_enum radix=UVM_NORADIX, byte scope_separator=".", string type_name=""); extern virtual function void print_object (string name, uvm_object value, byte scope_separator="."); extern virtual function void print_object_header (string name, uvm_object value, byte scope_separator="."); extern virtual function void print_string (string name, string value, byte scope_separator="."); uvm_policy::recursion_state_e m_recur_states[uvm_object][uvm_recursion_policy_enum ] ; extern virtual function uvm_policy::recursion_state_e object_printed ( uvm_object value, uvm_recursion_policy_enum recursion); extern virtual function void print_time (string name, time value, byte scope_separator="."); extern virtual function void print_real (string name, real value, byte scope_separator="."); extern virtual function void print_generic (string name, string type_name, int size, string value, byte scope_separator="."); extern virtual function void print_generic_element (string name, string type_name, string size, string value); extern virtual function string emit (); extern virtual function void flush (); extern virtual function void set_name_enabled (bit enabled); extern virtual function bit get_name_enabled (); extern virtual function void set_type_name_enabled (bit enabled); extern virtual function bit get_type_name_enabled (); extern virtual function void set_size_enabled (bit enabled); extern virtual function bit get_size_enabled (); extern virtual function void set_id_enabled (bit enabled); extern virtual function bit get_id_enabled (); extern virtual function void set_radix_enabled (bit enabled); extern virtual function bit get_radix_enabled (); extern virtual function void set_radix_string (uvm_radix_enum radix, string prefix); extern virtual function string get_radix_string (uvm_radix_enum radix); extern virtual function void set_default_radix (uvm_radix_enum radix); extern virtual function uvm_radix_enum get_default_radix (); extern virtual function void set_root_enabled (bit enabled); extern virtual function bit get_root_enabled (); extern virtual function void set_recursion_policy (uvm_recursion_policy_enum policy); extern virtual function uvm_recursion_policy_enum get_recursion_policy (); extern virtual function void set_max_depth (int depth); extern virtual function int get_max_depth (); extern virtual function void set_file (UVM_FILE fl); extern virtual function UVM_FILE get_file (); extern virtual function void set_line_prefix (string prefix); extern virtual function string get_line_prefix (); extern virtual function void set_begin_elements (int elements = 5); extern virtual function int get_begin_elements (); extern virtual function void set_end_elements (int elements = 5); extern virtual function int get_end_elements (); local uvm_printer_element m_element_stack[$] ; protected function int m_get_stack_size(); return m_element_stack.size(); endfunction extern protected virtual function uvm_printer_element get_bottom_element (); extern protected virtual function uvm_printer_element get_top_element (); extern virtual function void push_element ( string name, string type_name, string size, string value="" ); extern virtual function void pop_element (); extern function uvm_printer_element get_unused_element() ; uvm_printer_element m_recycled_elements[$]; extern virtual function void print_array_header(string name, int size, string arraytype="array", byte scope_separator="."); extern virtual function void print_array_range (int min, int max); extern virtual function void print_array_footer (int size = 0); virtual function string format_row (uvm_printer_row_info row); return ""; endfunction virtual function string format_header(); return ""; endfunction virtual function string format_footer(); return ""; endfunction virtual protected function string adjust_name (string id, byte scope_separator="."); if (get_root_enabled() && istop() || knobs.full_name || id == "...") begin return id; end return uvm_leaf_scope(id, scope_separator); endfunction extern function bit istop (); extern function string index_string (int index, string name=""); string m_string; extern function string get_radix_str(uvm_radix_enum radix); endclass class uvm_printer_element extends uvm_object; extern function new (string name=""); extern virtual function void set (string element_name = "", string element_type_name = "", string element_size = "", string element_value = "" ); extern virtual function void set_element_name (string element_name); extern virtual function string get_element_name (); extern virtual function void set_element_type_name (string element_type_name); extern virtual function string get_element_type_name (); extern virtual function void set_element_size (string element_size); extern virtual function string get_element_size (); extern virtual function void set_element_value (string element_value); extern virtual function string get_element_value (); extern function void add_child(uvm_printer_element child) ; extern function void get_children(ref uvm_printer_element children[$], input bit recurse) ; extern function void clear_children() ; local string m_name ; local string m_type_name ; local string m_size ; local string m_value ; local uvm_printer_element m_children[$] ; endclass class uvm_printer_element_proxy extends uvm_structure_proxy#(uvm_printer_element); extern function new (string name=""); extern virtual function void get_immediate_children(uvm_printer_element s, ref uvm_printer_element children[$]); endclass : uvm_printer_element_proxy class uvm_table_printer extends uvm_printer; typedef uvm_object_registry#(uvm_table_printer,"uvm_table_printer") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_table_printer tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_table_printer"; endfunction : type_name virtual function string get_type_name(); return "uvm_table_printer"; endfunction : get_type_name extern function new(string name=""); extern virtual function string emit(); extern virtual function string m_emit_element(uvm_printer_element element, int unsigned level); local static string m_space ; extern static function void set_default(uvm_table_printer printer) ; extern static function uvm_table_printer get_default() ; extern virtual function void set_indent(int indent) ; extern virtual function int get_indent() ; extern virtual function void flush() ; protected int m_max_name=4; protected int m_max_type=4; protected int m_max_size=4; protected int m_max_value=5; extern virtual function void pop_element(); endclass class uvm_tree_printer extends uvm_printer; protected string m_newline = "\n"; protected string m_linefeed ; typedef uvm_object_registry#(uvm_tree_printer,"uvm_tree_printer") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_tree_printer tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_tree_printer"; endfunction : type_name virtual function string get_type_name(); return "uvm_tree_printer"; endfunction : get_type_name extern function new(string name=""); extern static function void set_default(uvm_tree_printer printer) ; extern static function uvm_tree_printer get_default() ; extern virtual function void set_indent(int indent) ; extern virtual function int get_indent() ; extern virtual function void set_separators(string separators) ; extern virtual function string get_separators() ; extern virtual function void flush() ; extern virtual function string emit(); extern virtual function string m_emit_element(uvm_printer_element element, int unsigned level); endclass class uvm_line_printer extends uvm_tree_printer; typedef uvm_object_registry#(uvm_line_printer,"uvm_line_printer") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_line_printer tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_line_printer"; endfunction : type_name virtual function string get_type_name(); return "uvm_line_printer"; endfunction : get_type_name extern function new(string name=""); extern static function void set_default(uvm_line_printer printer) ; extern static function uvm_line_printer get_default() ; extern virtual function void set_separators(string separators) ; extern virtual function string get_separators() ; extern virtual function void flush() ; endclass class m_uvm_printer_knobs; bit identifier = 1; bit type_name = 1; bit size = 1; int depth = -1; bit reference = 1; int begin_elements = 5; int end_elements = 5; string prefix = ""; int indent = 2; bit show_root = 0; int mcd = UVM_STDOUT; string separator = "{}"; bit show_radix = 1; uvm_radix_enum default_radix = UVM_HEX; string dec_radix = "'d"; string bin_radix = "'b"; string oct_radix = "'o"; string unsigned_radix = "'d"; string hex_radix = "'h"; uvm_recursion_policy_enum recursion_policy ; bit header = 1; bit footer = 1; bit full_name = 0; endclass function uvm_printer::new(string name=""); super.new(name); knobs = new ; flush(); endfunction function void uvm_printer::set_default(uvm_printer printer) ; uvm_coreservice_t coreservice ; coreservice = uvm_coreservice_t::get() ; coreservice.set_default_printer(printer) ; endfunction function uvm_printer uvm_printer::get_default() ; uvm_coreservice_t coreservice ; coreservice = uvm_coreservice_t::get() ; return coreservice.get_default_printer() ; endfunction function void uvm_printer::print_field (string name, uvm_bitstream_t value, int size, uvm_radix_enum radix=UVM_NORADIX, byte scope_separator=".", string type_name=""); string sz_str, val_str; if(type_name == "") begin if(radix == UVM_TIME) begin type_name ="time"; end else if(radix == UVM_STRING) begin type_name ="string"; end else begin type_name ="integral"; end end sz_str.itoa(size); if(radix == UVM_NORADIX) begin radix = get_default_radix(); end val_str = uvm_bit_vector_utils#(uvm_bitstream_t)::to_string(value, size, radix, get_radix_string(radix)); name = adjust_name(name,scope_separator); push_element(name,type_name,sz_str,val_str); pop_element() ; endfunction function void uvm_printer::print_field_int (string name, uvm_integral_t value, int size, uvm_radix_enum radix=UVM_NORADIX, byte scope_separator=".", string type_name=""); string sz_str, val_str; if(type_name == "") begin if(radix == UVM_TIME) begin type_name ="time"; end else if(radix == UVM_STRING) begin type_name ="string"; end else begin type_name ="integral"; end end sz_str.itoa(size); if(radix == UVM_NORADIX) begin radix = get_default_radix(); end val_str = uvm_bit_vector_utils#(uvm_integral_t)::to_string(value, size, radix, get_radix_string(radix)); name = adjust_name(name,scope_separator); push_element(name,type_name,sz_str,val_str); pop_element() ; endfunction function string uvm_printer::emit (); begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "NO_OVERRIDE") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "NO_OVERRIDE") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("NO_OVERRIDE", "emit() method not overridden in printer subtype", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_printer.svh", 918, "", 1); end end return ""; endfunction function void uvm_printer::flush (); uvm_printer_element element = get_bottom_element() ; uvm_printer_element all_descendent_elements[$] ; element = get_bottom_element() ; if (element != null) begin element.get_children(all_descendent_elements,1) ; foreach (all_descendent_elements[i]) begin m_recycled_elements.push_back(all_descendent_elements[i]) ; all_descendent_elements[i].clear_children() ; end element.clear_children(); m_recycled_elements.push_back(element) ; m_element_stack.delete() ; end m_recur_states.delete(); m_flushed = 1 ; endfunction function void uvm_printer::set_name_enabled (bit enabled); knobs.identifier = enabled ; endfunction function bit uvm_printer::get_name_enabled (); return knobs.identifier ; endfunction function void uvm_printer::set_type_name_enabled (bit enabled); knobs.type_name = enabled ; endfunction function bit uvm_printer::get_type_name_enabled (); return knobs.type_name ; endfunction function void uvm_printer::set_size_enabled (bit enabled); knobs.size = enabled ; endfunction function bit uvm_printer::get_size_enabled (); return knobs.size ; endfunction function void uvm_printer::set_id_enabled (bit enabled); knobs.reference = enabled ; endfunction function bit uvm_printer::get_id_enabled (); return knobs.reference ; endfunction function void uvm_printer::set_radix_enabled (bit enabled); knobs.show_radix = enabled ; endfunction function bit uvm_printer::get_radix_enabled (); return knobs.show_radix ; endfunction function void uvm_printer::set_radix_string (uvm_radix_enum radix, string prefix); if (radix == UVM_DEC) begin knobs.dec_radix = prefix ; end else if (radix == UVM_BIN) begin knobs.bin_radix = prefix ; end else if (radix == UVM_OCT) begin knobs.oct_radix = prefix ; end else if (radix == UVM_UNSIGNED) begin knobs.unsigned_radix = prefix ; end else if (radix == UVM_HEX) begin knobs.hex_radix = prefix ; end else begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "PRINTER_UNKNOWN_RADIX") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "PRINTER_UNKNOWN_RADIX") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("PRINTER_UNKNOWN_RADIX", $sformatf("set_radix_string called with unsupported radix %s",radix), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_printer.svh", 1000, "", 1); end end end endfunction function string uvm_printer::get_radix_string (uvm_radix_enum radix); if (radix == UVM_DEC) begin return knobs.dec_radix ; end else if (radix == UVM_BIN) begin return knobs.bin_radix ; end else if (radix == UVM_OCT) begin return knobs.oct_radix ; end else if (radix == UVM_UNSIGNED) begin return knobs.unsigned_radix ; end else if (radix == UVM_HEX) begin return knobs.hex_radix ; end else begin return ""; end endfunction function void uvm_printer::set_default_radix (uvm_radix_enum radix); knobs.default_radix = radix ; endfunction function uvm_radix_enum uvm_printer::get_default_radix (); return knobs.default_radix ; endfunction function void uvm_printer::set_root_enabled (bit enabled); knobs.show_root = enabled ; endfunction function bit uvm_printer::get_root_enabled (); return knobs.show_root ; endfunction function void uvm_printer::set_recursion_policy (uvm_recursion_policy_enum policy); knobs.recursion_policy = policy ; endfunction function uvm_recursion_policy_enum uvm_printer::get_recursion_policy (); return knobs.recursion_policy ; endfunction function void uvm_printer::set_max_depth (int depth); knobs.depth = depth ; endfunction function int uvm_printer::get_max_depth (); return knobs.depth ; endfunction function void uvm_printer::set_file (UVM_FILE fl); knobs.mcd = fl ; endfunction function UVM_FILE uvm_printer::get_file (); return knobs.mcd ; endfunction function void uvm_printer::set_line_prefix (string prefix); knobs.prefix = prefix ; endfunction function string uvm_printer::get_line_prefix (); return knobs.prefix ; endfunction function void uvm_printer::set_begin_elements (int elements = 5); knobs.begin_elements = elements ; endfunction function int uvm_printer::get_begin_elements (); return knobs.begin_elements ; endfunction function void uvm_printer::set_end_elements (int elements = 5); knobs.end_elements = elements ; endfunction function int uvm_printer::get_end_elements (); return knobs.end_elements ; endfunction function uvm_printer_element uvm_printer::get_bottom_element (); if (m_element_stack.size() > 0) begin return m_element_stack[0] ; end else begin return null ; end endfunction function uvm_printer_element uvm_printer::get_top_element (); if (m_element_stack.size() > 0) begin return m_element_stack[$] ; end else begin return null ; end endfunction function uvm_printer_element_proxy::new (string name=""); super.new(name) ; endfunction function void uvm_printer_element_proxy::get_immediate_children(uvm_printer_element s, ref uvm_printer_element children[$]); s.get_children(children,0) ; endfunction function void uvm_printer::push_element ( string name, string type_name, string size, string value=""); uvm_printer_element element ; uvm_printer_element parent ; element = get_unused_element() ; parent = get_top_element() ; if (knobs.full_name && (parent != null)) begin name = $sformatf("%s.%s",parent.get_element_name(),name); end element.set(name,type_name,size,value); if (parent != null) begin parent.add_child(element) ; end m_element_stack.push_back(element) ; endfunction function void uvm_printer::pop_element (); if (m_element_stack.size() > 1) begin void'(m_element_stack.pop_back()); end endfunction function uvm_printer_element uvm_printer::get_unused_element() ; uvm_printer_element element ; if (m_recycled_elements.size() > 0) begin element = m_recycled_elements.pop_back() ; end else begin element = new() ; end return element ; endfunction function void uvm_printer::print_array_header (string name, int size, string arraytype="array", byte scope_separator="."); push_element(name,arraytype,$sformatf("%0d",size),"-"); endfunction function void uvm_printer::print_array_footer (int size=0); pop_element() ; endfunction function void uvm_printer::print_array_range(int min, int max); string tmpstr; if(min == -1 && max == -1) begin return; end if(min == -1) begin min = max; end if(max == -1) begin max = min; end if(max < min) begin return; end print_generic_element("...", "...", "...", "..."); endfunction function void uvm_printer::print_object_header (string name, uvm_object value, byte scope_separator="."); if(name == "") begin name = ""; end push_element(name, (value != null) ? value.get_type_name() : "object", "-", get_id_enabled() ? uvm_object_value_str(value) : "-"); endfunction function void uvm_printer::print_object (string name, uvm_object value, byte scope_separator="."); uvm_component comp, child_comp; uvm_field_op field_op ; uvm_recursion_policy_enum recursion_policy; recursion_policy = get_recursion_policy(); if ((value == null) || (recursion_policy == UVM_REFERENCE) || (get_max_depth() == get_active_object_depth())) begin print_object_header(name,value,scope_separator); pop_element(); end else begin push_active_object(value); m_recur_states[value][recursion_policy] = uvm_policy::STARTED ; print_object_header(name,value,scope_separator); field_op = uvm_field_op::m_get_available_op() ; field_op.set(UVM_PRINT,this,null); value.do_execute_op(field_op); if (field_op.user_hook_enabled()) begin value.do_print(this); end field_op.m_recycle(); pop_element() ; m_recur_states[value][recursion_policy] = uvm_policy::FINISHED ; void'(pop_active_object()); end endfunction function bit uvm_printer::istop (); return (get_active_object_depth() == 0); endfunction function void uvm_printer::print_generic (string name, string type_name, int size, string value, byte scope_separator="."); push_element(name, type_name, (size == -2 ? "..." : $sformatf("%0d",size)), value); pop_element(); endfunction function void uvm_printer::print_generic_element (string name, string type_name, string size, string value); push_element(name,type_name,size,value); pop_element() ; endfunction function void uvm_printer::print_time (string name, time value, byte scope_separator="."); print_field_int(name, value, 64, UVM_TIME, scope_separator); endfunction function void uvm_printer::print_string (string name, string value, byte scope_separator="."); push_element(name, "string", $sformatf("%0d",value.len()), (value == "" ? "\"\"" : value)); pop_element() ; endfunction function uvm_policy::recursion_state_e uvm_printer::object_printed (uvm_object value, uvm_recursion_policy_enum recursion); if (!m_recur_states.exists(value)) begin return NEVER ; end if (!m_recur_states[value].exists(recursion)) begin return NEVER ; end else begin return m_recur_states[value][recursion] ; end endfunction function void uvm_printer::print_real (string name, real value, byte scope_separator="."); push_element(name,"real","64",$sformatf("%f",value)); pop_element() ; endfunction function string uvm_printer::index_string(int index, string name=""); index_string.itoa(index); index_string = { name, "[", index_string, "]" }; endfunction function uvm_printer_element::new (string name = ""); super.new(name) ; endfunction function void uvm_printer_element::set (string element_name = "", string element_type_name = "", string element_size = "", string element_value = "" ); m_name = element_name ; m_type_name = element_type_name ; m_size = element_size ; m_value = element_value ; endfunction function void uvm_printer_element::set_element_name (string element_name); m_name = element_name ; endfunction function string uvm_printer_element::get_element_name (); return m_name ; endfunction function void uvm_printer_element::set_element_type_name (string element_type_name); m_type_name = element_type_name ; endfunction function string uvm_printer_element::get_element_type_name (); return m_type_name ; endfunction function void uvm_printer_element::set_element_size (string element_size); m_size = element_size ; endfunction function string uvm_printer_element::get_element_size (); return m_size ; endfunction function void uvm_printer_element::set_element_value (string element_value); m_value = element_value ; endfunction function string uvm_printer_element::get_element_value (); return m_value ; endfunction function void uvm_printer_element::add_child(uvm_printer_element child) ; m_children.push_back(child) ; endfunction function void uvm_printer_element::get_children(ref uvm_printer_element children[$], input bit recurse) ; foreach (m_children[i]) begin children.push_back(m_children[i]) ; if (recurse) begin m_children[i].get_children(children,1) ; end end endfunction function void uvm_printer_element::clear_children() ; m_children.delete() ; endfunction function uvm_table_printer::new(string name=""); super.new(name); endfunction function void uvm_table_printer::pop_element(); int name_len; int level ; uvm_printer_element popped ; string name_str ; string type_name_str ; string size_str ; string value_str ; popped = get_top_element() ; level = m_get_stack_size() - 1 ; name_str = popped.get_element_name() ; type_name_str = popped.get_element_type_name() ; size_str = popped.get_element_size() ; value_str = popped.get_element_value() ; if ((name_str.len() + (get_indent() * level)) > m_max_name) begin m_max_name = (name_str.len() + (get_indent() * level)); end if (type_name_str.len() > m_max_type) begin m_max_type = type_name_str.len(); end if (size_str.len() > m_max_size) begin m_max_size = size_str.len(); end if (value_str.len() > m_max_value) begin m_max_value = value_str.len(); end super.pop_element() ; endfunction function string uvm_table_printer::emit(); string s; string user_format; static string dash; string dashes; string linefeed; if (!m_flushed) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM/PRINT/NO_FLUSH") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM/PRINT/NO_FLUSH") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM/PRINT/NO_FLUSH", "printer emit() method called twice without intervening uvm_printer::flush()", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_printer.svh", 1484, "", 1); end end end else begin m_flushed = 0 ; end linefeed = {"\n", get_line_prefix()}; begin int q[5]; int m; int qq[$]; q = '{m_max_name,m_max_type,m_max_size,m_max_value,100}; qq = q.max; m = qq[0]; if(dash.len()= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM/PRINT/NO_FLUSH") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM/PRINT/NO_FLUSH", "printer emit() method called twice without intervening uvm_printer::flush()", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_printer.svh", 1663, "", 1); end end end else begin m_flushed = 0 ; end s = get_line_prefix() ; m_linefeed = m_newline == "" || m_newline == " " ? m_newline : {m_newline, get_line_prefix()}; if (knobs.header) begin user_format = format_header(); if (user_format != "") begin s = {s, user_format, m_linefeed}; end end s = {s,m_emit_element(get_bottom_element(),0)} ; if (knobs.footer) begin user_format = format_footer(); if (user_format != "") begin s = {s, user_format, m_linefeed}; end end if (m_newline == "" || m_newline == " ") begin s = {s, "\n"}; end return(s); endfunction function string uvm_tree_printer::m_emit_element(uvm_printer_element element, int unsigned level) ; string result ; string space= " "; static uvm_printer_element_proxy proxy = new("proxy") ; uvm_printer_element element_children[$]; string separators; string indent_str; string user_format ; separators=get_separators() ; indent_str = space.substr(1,level * get_indent()); proxy.get_immediate_children(element,element_children) ; begin uvm_printer_row_info row ; row.level = level ; row.name = element.get_element_name() ; row.type_name = element.get_element_type_name() ; row.size = element.get_element_size() ; row.val = element.get_element_value() ; user_format = format_row(row); end if (user_format != "") begin result = user_format; end else begin string value_str ; if (get_name_enabled()) begin result = {result,indent_str, element.get_element_name()}; if (element.get_element_name() != "" && element.get_element_name() != "...") begin result = {result, ": "}; end end value_str = element.get_element_value(); if ((value_str.len() > 0) && (value_str[0] == "@")) begin result = {result,"(",element.get_element_type_name(),value_str,") "}; end else if (get_type_name_enabled() && (element.get_element_type_name() != "" || element.get_element_type_name() != "-" || element.get_element_type_name() != "...")) begin result = {result,"(",element.get_element_type_name(),") "}; end if (get_size_enabled()) begin if (element.get_element_size() != "" || element.get_element_size() != "-") begin result = {result,"(",element.get_element_size(),") "}; end end if (element_children.size() > 0) begin result = {result, string'(separators[0]), m_linefeed}; end else begin result = {result, value_str, " ", m_linefeed}; end end foreach (element_children[i]) begin result = {result, m_emit_element(element_children[i],level+1)} ; end if ((user_format == "") && (element_children.size() > 0)) begin result = {result, indent_str, string'(separators[1]), m_linefeed}; end return result ; endfunction : m_emit_element function void uvm_table_printer::set_default(uvm_table_printer printer) ; uvm_default_table_printer = printer ; endfunction function uvm_table_printer uvm_table_printer::get_default() ; if (uvm_default_table_printer == null) begin uvm_default_table_printer = new() ; end return uvm_default_table_printer ; endfunction function void uvm_table_printer::set_indent(int indent) ; m_uvm_printer_knobs _knobs = get_knobs(); _knobs.indent = indent ; endfunction function int uvm_table_printer::get_indent() ; m_uvm_printer_knobs _knobs = get_knobs(); return _knobs.indent ; endfunction function void uvm_table_printer::flush() ; super.flush() ; m_max_name=4; m_max_type=4; m_max_size=4; m_max_value=5; endfunction function void uvm_tree_printer::set_default(uvm_tree_printer printer) ; uvm_default_tree_printer = printer ; endfunction function uvm_tree_printer uvm_tree_printer::get_default() ; if (uvm_default_tree_printer == null) begin uvm_default_tree_printer = new() ; end return uvm_default_tree_printer ; endfunction function uvm_line_printer::new(string name="") ; super.new(name); m_newline = " "; set_indent(0); endfunction function void uvm_line_printer::set_default(uvm_line_printer printer) ; uvm_default_line_printer = printer ; endfunction function uvm_line_printer uvm_line_printer::get_default() ; if (uvm_default_line_printer == null) begin uvm_default_line_printer = new() ; end return uvm_default_line_printer ; endfunction function void uvm_line_printer::set_separators(string separators) ; m_uvm_printer_knobs _knobs = get_knobs(); if (separators.len() < 2) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM/PRINT/SHORT_SEP") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM/PRINT/SHORT_SEP") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM/PRINT/SHORT_SEP", $sformatf("Bad call: set_separators(%s) (Argument must have at least 2 characters)",separators), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_printer.svh", 1856, "", 1); end end end _knobs.separator = separators ; endfunction function string uvm_line_printer::get_separators() ; m_uvm_printer_knobs _knobs = get_knobs(); return _knobs.separator ; endfunction function void uvm_line_printer::flush() ; super.flush() ; endfunction function string uvm_printer::get_radix_str(uvm_radix_enum radix); if(knobs.show_radix == 0) begin return ""; end if(radix == UVM_NORADIX) begin radix = knobs.default_radix; end return get_radix_string(radix); endfunction class uvm_comparer extends uvm_policy; typedef uvm_object_registry#(uvm_comparer,"uvm_comparer") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_comparer tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_comparer"; endfunction : type_name virtual function string get_type_name(); return "uvm_comparer"; endfunction : get_type_name extern virtual function void flush(); extern virtual function uvm_policy::recursion_state_e object_compared( uvm_object lhs, uvm_object rhs, uvm_recursion_policy_enum recursion, output bit ret_val ); extern virtual function string get_miscompares(); extern virtual function int unsigned get_result(); extern virtual function void set_result(int unsigned result) ; extern virtual function void set_recursion_policy( uvm_recursion_policy_enum policy); extern virtual function uvm_recursion_policy_enum get_recursion_policy(); extern virtual function void set_check_type( bit enabled ); extern virtual function bit get_check_type(); extern virtual function void set_show_max (int unsigned show_max); extern virtual function int unsigned get_show_max (); extern virtual function void set_verbosity (int unsigned verbosity); extern virtual function int unsigned get_verbosity (); extern virtual function void set_severity (uvm_severity severity); extern virtual function uvm_severity get_severity (); extern virtual function void set_threshold (int unsigned threshold); extern virtual function int unsigned get_threshold (); bit physical = 1; bit abstract = 1 ; typedef struct { recursion_state_e state; bit ret_val; } state_info_t ; state_info_t m_recur_states[uvm_object ][uvm_object ][uvm_recursion_policy_enum ]; uvm_recursion_policy_enum policy = UVM_DEFAULT_POLICY; int unsigned show_max = 1; int unsigned verbosity = UVM_LOW; uvm_severity sev = UVM_INFO; string miscompares = ""; bit check_type = 1; int unsigned result = 0; local int unsigned m_threshold; function new(string name=""); super.new(name); m_threshold = 1; endfunction static function void set_default (uvm_comparer comparer) ; uvm_coreservice_t coreservice ; coreservice = uvm_coreservice_t::get() ; coreservice.set_default_comparer(comparer) ; endfunction static function uvm_comparer get_default () ; uvm_coreservice_t coreservice ; coreservice = uvm_coreservice_t::get() ; return coreservice.get_default_comparer() ; endfunction virtual function bit compare_field (string name, uvm_bitstream_t lhs, uvm_bitstream_t rhs, int size, uvm_radix_enum radix=UVM_NORADIX); uvm_bitstream_t mask; string msg; if(size <= 64) begin return compare_field_int(name, lhs, rhs, size, radix); end mask = -1; mask >>= (UVM_STREAMBITS-size); if((lhs & mask) !== (rhs & mask)) begin case (radix) UVM_BIN: begin $swrite(msg, "%s: lhs = 'b%0b : rhs = 'b%0b", name, lhs&mask, rhs&mask); end UVM_OCT: begin $swrite(msg, "%s: lhs = 'o%0o : rhs = 'o%0o", name, lhs&mask, rhs&mask); end UVM_DEC: begin $swrite(msg, "%s: lhs = %0d : rhs = %0d", name, lhs&mask, rhs&mask); end UVM_TIME: begin $swrite(msg, "%s: lhs = %0t : rhs = %0t", name, lhs&mask, rhs&mask); end UVM_STRING: begin $swrite(msg, "%s: lhs = %0s : rhs = %0s", name, lhs&mask, rhs&mask); end UVM_ENUM: begin $swrite(msg, "%s: lhs = %0d : rhs = %0d", name, lhs&mask, rhs&mask); end default: begin $swrite(msg, "%s: lhs = 'h%0x : rhs = 'h%0x", name, lhs&mask, rhs&mask); end endcase print_msg(msg); return 0; end return 1; endfunction virtual function bit compare_field_int (string name, uvm_integral_t lhs, uvm_integral_t rhs, int size, uvm_radix_enum radix=UVM_NORADIX); logic [63:0] mask; string msg; if(size > 64) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM/COMPARER/INT/BAD_SIZE") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM/COMPARER/INT/BAD_SIZE") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM/COMPARER/INT/BAD_SIZE", $sformatf("compare_field_int cannot be called with operand size of more than 64 bits. Input argument size=%0d",size), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_comparer.svh", 295, "", 1); end end return 0; end mask = -1; mask >>= (64-size); if((lhs & mask) !== (rhs & mask)) begin case (radix) UVM_BIN: begin $swrite(msg, "%s: lhs = 'b%0b : rhs = 'b%0b", name, lhs&mask, rhs&mask); end UVM_OCT: begin $swrite(msg, "%s: lhs = 'o%0o : rhs = 'o%0o", name, lhs&mask, rhs&mask); end UVM_DEC: begin $swrite(msg, "%s: lhs = %0d : rhs = %0d", name, lhs&mask, rhs&mask); end UVM_TIME: begin $swrite(msg, "%s: lhs = %0t : rhs = %0t", name, lhs&mask, rhs&mask); end UVM_STRING: begin $swrite(msg, "%s: lhs = %0s : rhs = %0s", name, lhs&mask, rhs&mask); end UVM_ENUM: begin $swrite(msg, "%s: lhs = %0d : rhs = %0d", name, lhs&mask, rhs&mask); end default: begin $swrite(msg, "%s: lhs = 'h%0x : rhs = 'h%0x", name, lhs&mask, rhs&mask); end endcase print_msg(msg); return 0; end return 1; endfunction virtual function bit compare_field_real (string name, real lhs, real rhs); string msg; if(lhs != rhs) begin $swrite(msg, name, ": lhs = ", lhs, " : rhs = ", rhs); print_msg(msg); return 0; end return 1; endfunction local string m_object_names[$]; local function string m_current_context(string name=""); if (m_object_names.size() == 0) begin return name; end else if ((m_object_names.size() == 1) && (name=="")) begin return m_object_names[0]; end else begin string full_name; foreach(m_object_names[i]) begin if (i == m_object_names.size() - 1) begin full_name = {full_name, m_object_names[i]}; end else begin full_name = {full_name, m_object_names[i], "."}; end end if (name != "") begin return {full_name, ".", name}; end else begin return full_name; end end endfunction : m_current_context virtual function bit compare_object (string name, uvm_object lhs, uvm_object rhs); int old_result ; uvm_field_op field_op ; uvm_policy::recursion_state_e prev_state; bit ret_val = 1; if (rhs == lhs) begin return ret_val; end m_object_names.push_back(name); if (policy == UVM_REFERENCE && lhs != rhs) begin print_msg_object(lhs, rhs); ret_val = 0; end if (ret_val && (rhs == null || lhs == null)) begin print_msg_object(lhs, rhs); ret_val = 0; end if (ret_val) begin prev_state = object_compared(lhs,rhs,get_recursion_policy(),ret_val); if (prev_state != uvm_policy::NEVER) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "UVM/COPIER/LOOP") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "UVM/COPIER/LOOP") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("UVM/COPIER/LOOP", {"Possible loop when comparing '", lhs.get_full_name(), "' to '", rhs.get_full_name(), "'"}, uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_comparer.svh", 458, "", 1); end end end push_active_object(lhs); m_recur_states[lhs][rhs][get_recursion_policy()] = '{uvm_policy::STARTED,0}; old_result = get_result(); if (get_check_type() && (lhs.get_object_type() != rhs.get_object_type())) begin if(lhs.get_type_name() != rhs.get_type_name()) begin print_msg({"type: lhs = \"", lhs.get_type_name(), "\" : rhs = \"", rhs.get_type_name(), "\""}); end else begin print_msg({"get_object_type() for ",lhs.get_name()," does not match get_object_type() for ",rhs.get_name()}); end end field_op = uvm_field_op::m_get_available_op(); field_op.set(UVM_COMPARE,this,rhs); lhs.do_execute_op(field_op); if (field_op.user_hook_enabled()) begin ret_val = lhs.do_compare(rhs,this); end field_op.m_recycle(); if (ret_val && (get_result() > old_result)) begin ret_val = 0; end m_recur_states[lhs][rhs][get_recursion_policy()] = '{uvm_policy::FINISHED,ret_val}; void'(pop_active_object()); end void'(m_object_names.pop_back()); if (!ret_val && (get_active_object_depth() == 0)) begin string msg ; if(get_result()) begin if (get_show_max() && (get_show_max() < get_result())) begin $swrite(msg, "%0d Miscompare(s) (%0d shown) for object ", result, show_max); end else begin $swrite(msg, "%0d Miscompare(s) for object ", result); end end uvm_pkg::uvm_report(sev, "MISCMP", $sformatf("%s%s@%0d vs. %s@%0d", msg, (lhs == null) ? "" : lhs.get_name(), (lhs == null) ? 0 : lhs.get_inst_id(), (rhs == null) ? "" : rhs.get_name(), (rhs == null) ? 0 : rhs.get_inst_id()), get_verbosity(), "t/uvm/src/base/uvm_comparer.svh", 527); end return ret_val; endfunction virtual function bit compare_string (string name, string lhs, string rhs); string msg; if(lhs != rhs) begin msg = { name, ": lhs = \"", lhs, "\" : rhs = \"", rhs, "\""}; print_msg(msg); return 0; end return 1; endfunction function void print_msg (string msg); string tmp = m_current_context(msg); result++; if((get_show_max() == 0) || (get_result() <= get_show_max())) begin msg = {"Miscompare for ", tmp}; uvm_pkg::uvm_report(sev, "MISCMP", msg, get_verbosity(), "t/uvm/src/base/uvm_comparer.svh", 575); end miscompares = { miscompares, tmp, "\n" }; endfunction function void print_msg_object(uvm_object lhs, uvm_object rhs); string tmp = $sformatf("%s: lhs = @%0d : rhs = @%0d", m_current_context(), (lhs != null ? lhs.get_inst_id() : 0), (rhs != null ? rhs.get_inst_id() : 0)); result++; if((get_show_max() == 0) || (get_result() <= get_show_max())) begin uvm_pkg::uvm_report(sev, "MISCMP", {"Miscompare for ", tmp}, get_verbosity(), "t/uvm/src/base/uvm_comparer.svh", 601); end miscompares = { miscompares, tmp, "\n" }; endfunction int depth; bit compare_map[uvm_object][uvm_object]; endclass function void uvm_comparer::flush(); miscompares = "" ; check_type = 1 ; result = 0 ; m_recur_states.delete(); endfunction function uvm_policy::recursion_state_e uvm_comparer::object_compared( uvm_object lhs, uvm_object rhs, uvm_recursion_policy_enum recursion, output bit ret_val ); if (!m_recur_states.exists(lhs)) begin return NEVER ; end else if (!m_recur_states[lhs].exists(rhs)) begin return NEVER ; end else if (!m_recur_states[lhs][rhs].exists(recursion)) begin return NEVER ; end else begin if (m_recur_states[lhs][rhs][recursion].state == FINISHED) begin ret_val = m_recur_states[lhs][rhs][recursion].ret_val; end return m_recur_states[lhs][rhs][recursion].state ; end endfunction function string uvm_comparer::get_miscompares(); return miscompares ; endfunction function int unsigned uvm_comparer::get_result(); return result ; endfunction function void uvm_comparer::set_result(int unsigned result); this.result = result ; endfunction function void uvm_comparer::set_recursion_policy( uvm_recursion_policy_enum policy); this.policy = policy ; endfunction function uvm_recursion_policy_enum uvm_comparer::get_recursion_policy(); return policy ; endfunction function void uvm_comparer::set_check_type( bit enabled ); check_type = enabled ; endfunction function bit uvm_comparer::get_check_type(); return check_type ; endfunction function void uvm_comparer::set_show_max (int unsigned show_max); this.show_max = show_max ; endfunction function int unsigned uvm_comparer::get_show_max(); return show_max ; endfunction function void uvm_comparer::set_verbosity (int unsigned verbosity); this.verbosity = verbosity ; endfunction function int unsigned uvm_comparer::get_verbosity(); return verbosity ; endfunction function void uvm_comparer::set_severity (uvm_severity severity); sev = severity ; endfunction function uvm_severity uvm_comparer::get_severity(); return sev ; endfunction function void uvm_comparer::set_threshold (int unsigned threshold); m_threshold = threshold; endfunction function int unsigned uvm_comparer::get_threshold(); return m_threshold; endfunction typedef bit signed [(4096*8)-1:0] uvm_pack_bitstream_t; class uvm_packer extends uvm_policy; typedef uvm_object_registry#(uvm_packer,"uvm_packer") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_packer tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_packer"; endfunction : type_name virtual function string get_type_name(); return "uvm_packer"; endfunction : get_type_name uvm_factory m_factory; local uvm_object m_object_references[int]; extern virtual function void set_packed_bits (ref bit unsigned stream[]); extern virtual function void set_packed_bytes (ref byte unsigned stream[]); extern virtual function void set_packed_ints (ref int unsigned stream[]); extern virtual function void set_packed_longints (ref longint unsigned stream[]); extern virtual function void get_packed_bits (ref bit unsigned stream[]); extern virtual function void get_packed_bytes (ref byte unsigned stream[]); extern virtual function void get_packed_ints (ref int unsigned stream[]); extern virtual function void get_packed_longints (ref longint unsigned stream[]); static function void set_default (uvm_packer packer) ; uvm_coreservice_t coreservice ; coreservice = uvm_coreservice_t::get() ; coreservice.set_default_packer(packer) ; endfunction static function uvm_packer get_default () ; uvm_coreservice_t coreservice ; coreservice = uvm_coreservice_t::get() ; return coreservice.get_default_packer() ; endfunction extern virtual function void flush (); extern virtual function void pack_field (uvm_bitstream_t value, int size); extern function new(string name=""); extern virtual function void pack_field_int (uvm_integral_t value, int size); extern virtual function void pack_bits(ref bit value[], input int size = -1); extern virtual function void pack_bytes(ref byte value[], input int size = -1); extern virtual function void pack_ints(ref int value[], input int size = -1); extern virtual function void pack_string (string value); extern virtual function void pack_time (time value); extern virtual function void pack_real (real value); extern virtual function void pack_object (uvm_object value); extern virtual function void pack_object_with_meta (uvm_object value); extern virtual function void pack_object_wrapper (uvm_object_wrapper value); extern virtual function bit is_null (); extern virtual function bit is_object_wrapper(); extern virtual function uvm_bitstream_t unpack_field (int size); extern virtual function uvm_integral_t unpack_field_int (int size); extern virtual function void unpack_bits(ref bit value[], input int size = -1); extern virtual function void unpack_bytes(ref byte value[], input int size = -1); extern virtual function void unpack_ints(ref int value[], input int size = -1); extern virtual function string unpack_string (); extern virtual function time unpack_time (); extern virtual function real unpack_real (); extern virtual function void unpack_object (uvm_object value); extern virtual function void unpack_object_with_meta (inout uvm_object value); extern virtual function uvm_object_wrapper unpack_object_wrapper(); extern virtual function int get_packed_size(); static bit bitstream[]; static bit fabitstream[]; int m_pack_iter; int m_unpack_iter; bit reverse_order; byte byte_size = 8; int word_size = 16; bit nopack; uvm_pack_bitstream_t m_bits; bit physical = 1; bit abstract = 1 ; extern function void index_error(int index, string id, int sz); extern function bit enough_bits(int needed, string id); function string unpack_string_with_size (int num_chars=-1); return unpack_string(); endfunction endclass function void uvm_packer::index_error(int index, string id, int sz); uvm_report_error("PCKIDX", $sformatf("index %0d for get_%0s too large; valid index range is 0-%0d.", index,id,((m_pack_iter+sz-1)/sz)-1), UVM_NONE); endfunction function bit uvm_packer::enough_bits(int needed, string id); if ((m_pack_iter - m_unpack_iter) < needed) begin uvm_report_error("PCKSZ", $sformatf("%0d bits needed to unpack %0s, yet only %0d available.", needed, id, (m_pack_iter - m_unpack_iter)), UVM_NONE); return 0; end return 1; endfunction function int uvm_packer::get_packed_size(); return m_pack_iter - m_unpack_iter; endfunction function void uvm_packer::flush(); m_pack_iter = 64; m_unpack_iter = 64; m_bits = 0; m_object_references.delete(); m_object_references[0] = null; m_factory = null; super.flush(); endfunction : flush function void uvm_packer::get_packed_bits(ref bit unsigned stream[]); stream = new[m_pack_iter]; m_bits[31:0] = m_pack_iter; m_bits[63:32] = m_unpack_iter; for (int i=0;i> ($bits(T)-(m_pack_iter%$bits(T)))); \ end \ stream[i] = v; \ end \ endfunction function void uvm_packer::get_packed_bytes (ref byte unsigned stream[] ); int sz; byte v; sz = (m_pack_iter + $high(v)) / $bits(byte); m_bits[31:0] = m_pack_iter; m_bits[63:32] = m_unpack_iter; stream = new[sz]; foreach (stream[i]) begin if (i != sz-1 || (m_pack_iter % $bits(byte)) == 0) begin v = m_bits[ i* $bits(byte) +: $bits(byte) ]; end else begin v = m_bits[ i* $bits(byte) +: $bits(byte) ] & ({$bits(byte){1'b1}} >> ($bits(byte)-(m_pack_iter%$bits(byte)))); end stream[i] = v; end endfunction function void uvm_packer::get_packed_ints (ref int unsigned stream[] ); int sz; int v; sz = (m_pack_iter + $high(v)) / $bits(int); m_bits[31:0] = m_pack_iter; m_bits[63:32] = m_unpack_iter; stream = new[sz]; foreach (stream[i]) begin if (i != sz-1 || (m_pack_iter % $bits(int)) == 0) begin v = m_bits[ i* $bits(int) +: $bits(int) ]; end else begin v = m_bits[ i* $bits(int) +: $bits(int) ] & ({$bits(int){1'b1}} >> ($bits(int)-(m_pack_iter%$bits(int)))); end stream[i] = v; end endfunction function void uvm_packer::get_packed_longints (ref longint unsigned stream[] ); int sz; longint v; sz = (m_pack_iter + $high(v)) / $bits(longint); m_bits[31:0] = m_pack_iter; m_bits[63:32] = m_unpack_iter; stream = new[sz]; foreach (stream[i]) begin if (i != sz-1 || (m_pack_iter % $bits(longint)) == 0) begin v = m_bits[ i* $bits(longint) +: $bits(longint) ]; end else begin v = m_bits[ i* $bits(longint) +: $bits(longint) ] & ({$bits(longint){1'b1}} >> ($bits(longint)-(m_pack_iter%$bits(longint)))); end stream[i] = v; end endfunction `undef M__UVM_GET_PACKED function void uvm_packer::set_packed_bits (ref bit stream []); int bit_size; bit_size = stream.size(); for (int i=0;i value.size()) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM/BASE/PACKER/BAD_SIZE") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM/BASE/PACKER/BAD_SIZE") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM/BASE/PACKER/BAD_SIZE", $sformatf("pack_bits called with size '%0d', which exceeds value.size() of '%0d'", size, value.size()), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_packer.svh", 639, "", 1); end end return; end for (int i=0; i max_size) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM/BASE/PACKER/BAD_SIZE") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM/BASE/PACKER/BAD_SIZE") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM/BASE/PACKER/BAD_SIZE", $sformatf("pack_bytes called with size '%0d', which exceeds value size of '%0d'", size, max_size), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_packer.svh", 667, "", 1); end end return; end else begin int idx_select; for (int i=0; i max_size) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM/BASE/PACKER/BAD_SIZE") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM/BASE/PACKER/BAD_SIZE") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM/BASE/PACKER/BAD_SIZE", $sformatf("pack_ints called with size '%0d', which exceeds value size of '%0d'", size, max_size), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_packer.svh", 699, "", 1); end end return; end else begin int idx_select; for (int i=0; i= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM/BASE/PACKER/UNPACK/N2NN") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM/BASE/PACKER/UNPACK/N2NN", "attempt to unpack a null object into a not-null object!", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_packer.svh", 752, "", 1); end end return; end m_unpack_iter += 4; return; end else begin if (value == null) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM/BASE/PACKER/UNPACK/NN2N") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM/BASE/PACKER/UNPACK/NN2N") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM/BASE/PACKER/UNPACK/NN2N", "attempt to unpack a non-null object into a null object!", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_packer.svh", 760, "", 1); end end return; end m_unpack_iter += 4; push_active_object(value); field_op = uvm_field_op::m_get_available_op() ; field_op.set(UVM_UNPACK,this,value); value.do_execute_op(field_op); if (field_op.user_hook_enabled()) begin value.do_unpack(this); end field_op.m_recycle(); void'(pop_active_object()); end endfunction function void uvm_packer::unpack_object_with_meta(inout uvm_object value); int reference_id; reference_id = unpack_field_int(32); if (m_object_references.exists(reference_id)) begin value = m_object_references[reference_id]; return; end else begin uvm_object_wrapper __wrapper = unpack_object_wrapper(); if ((__wrapper != null) && ((value == null) || (value.get_object_type() != __wrapper))) begin value = __wrapper.create_object(""); if (value == null) begin value = __wrapper.create_component("",null); end end end m_object_references[reference_id] = value; unpack_object(value); endfunction function uvm_object_wrapper uvm_packer::unpack_object_wrapper(); string type_name; type_name = unpack_string(); if (m_factory == null) begin m_factory = uvm_factory::get(); end if (m_factory.is_type_name_registered(type_name)) begin return m_factory.find_wrapper_by_name(type_name); end return null; endfunction function real uvm_packer::unpack_real(); if (enough_bits(64,"real")) begin return $bitstoreal(unpack_field_int(64)); end endfunction function time uvm_packer::unpack_time(); if (enough_bits(64,"time")) begin return unpack_field_int(64); end endfunction function uvm_bitstream_t uvm_packer::unpack_field(int size); unpack_field = 'b0; if (enough_bits(size,"integral")) begin m_unpack_iter += size; for (int i=0; i max_size) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM/BASE/PACKER/BAD_SIZE") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM/BASE/PACKER/BAD_SIZE") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM/BASE/PACKER/BAD_SIZE", $sformatf("unpack_bytes called with size '%0d', which exceeds value size of '%0d'", size, value.size()), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_packer.svh", 930, "", 1); end end return; end else begin if (enough_bits(size, "integral")) begin m_unpack_iter += size; for (int i=0; i max_size) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM/BASE/PACKER/BAD_SIZE") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM/BASE/PACKER/BAD_SIZE") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM/BASE/PACKER/BAD_SIZE", $sformatf("unpack_ints called with size '%0d', which exceeds value size of '%0d'", size, value.size()), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_packer.svh", 960, "", 1); end end return; end else begin if (enough_bits(size, "integral")) begin m_unpack_iter += size; for (int i=0; i= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "UVM/TR_DB/BAD_LINK") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("UVM/TR_DB/BAD_LINK", "left hand side '' is not supported in links for 'uvm_tr_database'", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_tr_database.svh", 186, "", 1); end end return; end if (rhs == null) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "UVM/TR_DB/BAD_LINK") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "UVM/TR_DB/BAD_LINK") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("UVM/TR_DB/BAD_LINK", "right hand side '' is not supported in links for 'uvm_tr_database'", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_tr_database.svh", 191, "", 1); end end return; end if (!$cast(s_lhs, lhs) && !$cast(r_lhs, lhs)) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "UVM/TR_DB/BAD_LINK") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "UVM/TR_DB/BAD_LINK") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("UVM/TR_DB/BAD_LINK", $sformatf("left hand side of type '%s' not supported in links for 'uvm_tr_database'", lhs.get_type_name()), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_tr_database.svh", 199, "", 1); end end return; end if (!$cast(s_rhs, rhs) && !$cast(r_rhs, rhs)) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "UVM/TR_DB/BAD_LINK") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "UVM/TR_DB/BAD_LINK") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("UVM/TR_DB/BAD_LINK", $sformatf("right hand side of type '%s' not supported in links for 'uvm_record_datbasae'", rhs.get_type_name()), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_tr_database.svh", 206, "", 1); end end return; end if (r_lhs != null) begin s_lhs = r_lhs.get_stream(); end if (r_rhs != null) begin s_rhs = r_rhs.get_stream(); end if ((s_lhs != null) && (s_lhs.get_db() != this)) begin db = s_lhs.get_db(); begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "UVM/TR_DB/BAD_LINK") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "UVM/TR_DB/BAD_LINK") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("UVM/TR_DB/BAD_LINK", $sformatf("attempt to link stream from '%s' into '%s'", db.get_name(), this.get_name()), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_tr_database.svh", 221, "", 1); end end return; end if ((s_rhs != null) && (s_rhs.get_db() != this)) begin db = s_rhs.get_db(); begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "UVM/TR_DB/BAD_LINK") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "UVM/TR_DB/BAD_LINK") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("UVM/TR_DB/BAD_LINK", $sformatf("attempt to link stream from '%s' into '%s'", db.get_name(), this.get_name()), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_tr_database.svh", 228, "", 1); end end return; end do_establish_link(link); endfunction : establish_link pure virtual protected function bit do_open_db(); pure virtual protected function bit do_close_db(); pure virtual protected function uvm_tr_stream do_open_stream(string name, string scope, string type_name); pure virtual protected function void do_establish_link(uvm_link_base link); endclass : uvm_tr_database typedef class uvm_recorder; typedef class uvm_tr_stream; typedef class uvm_link_base; typedef class uvm_simple_lock_dap; typedef class uvm_text_tr_stream; class uvm_text_tr_database extends uvm_tr_database; local uvm_simple_lock_dap#(string) m_filename_dap; UVM_FILE m_file; typedef uvm_object_registry#(uvm_text_tr_database,"uvm_text_tr_database") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_text_tr_database tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_text_tr_database"; endfunction : type_name virtual function string get_type_name(); return "uvm_text_tr_database"; endfunction : get_type_name function new(string name="unnamed-uvm_text_tr_database"); super.new(name); m_filename_dap = new("filename_dap"); m_filename_dap.set("tr_db.log"); endfunction : new protected virtual function bit do_open_db(); if (m_file == 0) begin m_file = $fopen(m_filename_dap.get(), "a+"); if (m_file != 0) begin m_filename_dap.lock(); end end return (m_file != 0); endfunction : do_open_db protected virtual function bit do_close_db(); if (m_file != 0) begin fork begin $fclose(m_file); end join_none m_filename_dap.unlock(); end return 1; endfunction : do_close_db protected virtual function uvm_tr_stream do_open_stream(string name, string scope, string type_name); uvm_text_tr_stream m_stream = uvm_text_tr_stream::type_id::create(name); return m_stream; endfunction : do_open_stream protected virtual function void do_establish_link(uvm_link_base link); uvm_recorder r_lhs, r_rhs; uvm_object lhs = link.get_lhs(); uvm_object rhs = link.get_rhs(); void'($cast(r_lhs, lhs)); void'($cast(r_rhs, rhs)); if ((r_lhs == null) || (r_rhs == null)) begin return; end else begin uvm_parent_child_link pc_link; uvm_related_link re_link; if ($cast(pc_link, link)) begin $fdisplay(m_file," LINK @%0t {TXH1:%0d TXH2:%0d RELATION=%0s}", $time, r_lhs.get_handle(), r_rhs.get_handle(), "child"); end else if ($cast(re_link, link)) begin $fdisplay(m_file," LINK @%0t {TXH1:%0d TXH2:%0d RELATION=%0s}", $time, r_lhs.get_handle(), r_rhs.get_handle(), ""); end end endfunction : do_establish_link function void set_file_name(string filename); if (filename == "") begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "UVM/TXT_DB/EMPTY_NAME") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "UVM/TXT_DB/EMPTY_NAME") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("UVM/TXT_DB/EMPTY_NAME", "Ignoring attempt to set file name to ''!", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_text_tr_database.svh", 210, "", 1); end end return; end if (!m_filename_dap.try_set(filename)) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "UVM/TXT_DB/SET_AFTER_OPEN") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "UVM/TXT_DB/SET_AFTER_OPEN") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("UVM/TXT_DB/SET_AFTER_OPEN", "Ignoring attempt to change file name after opening the db!", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_text_tr_database.svh", 216, "", 1); end end return; end endfunction : set_file_name endclass : uvm_text_tr_database class m_uvm_tr_stream_cfg; uvm_tr_database db; string scope; string stream_type_name; endclass : m_uvm_tr_stream_cfg typedef class uvm_set_before_get_dap; typedef class uvm_text_recorder; virtual class uvm_tr_stream extends uvm_object; local uvm_set_before_get_dap#(m_uvm_tr_stream_cfg) m_cfg_dap; local bit m_records[uvm_recorder]; local bit m_warn_null_cfg; local bit m_is_opened; local bit m_is_closed; function new(string name="unnamed-uvm_tr_stream"); super.new(name); m_cfg_dap = new("cfg_dap"); endfunction : new local static int m_ids_by_stream[uvm_tr_stream]; function uvm_tr_database get_db(); m_uvm_tr_stream_cfg m_cfg; if (!m_cfg_dap.try_get(m_cfg)) begin if (m_warn_null_cfg == 1) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "UVM/REC_STR/NO_CFG") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "UVM/REC_STR/NO_CFG") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("UVM/REC_STR/NO_CFG", $sformatf("attempt to retrieve DB from '%s' before it was set!", get_name()), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_tr_stream.svh", 106, "", 1); end end end m_warn_null_cfg = 0; return null; end return m_cfg.db; endfunction : get_db function string get_scope(); m_uvm_tr_stream_cfg m_cfg; if (!m_cfg_dap.try_get(m_cfg)) begin if (m_warn_null_cfg == 1) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "UVM/REC_STR/NO_CFG") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "UVM/REC_STR/NO_CFG") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("UVM/REC_STR/NO_CFG", $sformatf("attempt to retrieve scope from '%s' before it was set!", get_name()), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_tr_stream.svh", 124, "", 1); end end end m_warn_null_cfg = 0; return ""; end return m_cfg.scope; endfunction : get_scope function string get_stream_type_name(); m_uvm_tr_stream_cfg m_cfg; if (!m_cfg_dap.try_get(m_cfg)) begin if (m_warn_null_cfg == 1) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "UVM/REC_STR/NO_CFG") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "UVM/REC_STR/NO_CFG") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("UVM/REC_STR/NO_CFG", $sformatf("attempt to retrieve STREAM_TYPE_NAME from '%s' before it was set!", get_name()), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_tr_stream.svh", 142, "", 1); end end end m_warn_null_cfg = 0; return ""; end return m_cfg.stream_type_name; endfunction : get_stream_type_name function void close(); if (!is_open()) begin return; end do_close(); foreach (m_records[idx]) begin if (idx.is_open()) begin idx.close(); end end m_is_opened = 0; m_is_closed = 1; endfunction : close function void free(); process p; string s; uvm_tr_database db; if (!is_open() && !is_closed()) begin return; end if (is_open()) begin close(); end do_free(); foreach (m_records[idx]) begin idx.free(); end db = get_db(); m_is_closed = 0; p = process::self(); if(p != null) begin s = p.get_randstate(); end m_cfg_dap = new("cfg_dap"); if(p != null) begin p.set_randstate(s); end m_warn_null_cfg = 1; if (m_ids_by_stream.exists(this)) begin m_free_id(m_ids_by_stream[this]); end if (db != null) begin db.m_free_stream(this); end endfunction : free function void m_do_open(uvm_tr_database db, string scope="", string stream_type_name=""); m_uvm_tr_stream_cfg m_cfg; uvm_tr_database m_db; if (db == null) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM/REC_STR/NULL_DB") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM/REC_STR/NULL_DB") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM/REC_STR/NULL_DB", $sformatf("Illegal attempt to set DB for '%s' to ''", this.get_full_name()), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_tr_stream.svh", 267, "", 1); end end return; end if (m_cfg_dap.try_get(m_cfg)) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM/REC_STR/RE_CFG") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM/REC_STR/RE_CFG") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM/REC_STR/RE_CFG", $sformatf("Illegal attempt to re-open '%s'", this.get_full_name()), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_tr_stream.svh", 275, "", 1); end end end else begin m_cfg = new(); m_cfg.db = db; m_cfg.scope = scope; m_cfg.stream_type_name = stream_type_name; m_cfg_dap.set(m_cfg); m_is_opened = 1; do_open(db, scope, stream_type_name); end endfunction : m_do_open function bit is_open(); return m_is_opened; endfunction : is_open function bit is_closed(); return m_is_closed; endfunction : is_closed function uvm_recorder open_recorder(string name, time open_time = 0, string type_name=""); time m_time = (open_time == 0) ? $time : open_time; if (!is_open()) begin return null; end else begin process p = process::self(); string s; if (p != null) begin s = p.get_randstate(); end open_recorder = do_open_recorder(name, m_time, type_name); if (open_recorder != null) begin m_records[open_recorder] = 1; open_recorder.m_do_open(this, m_time, type_name); end if (p != null) begin p.set_randstate(s); end end endfunction : open_recorder function void m_free_recorder(uvm_recorder recorder); if (m_records.exists(recorder)) begin m_records.delete(recorder); end endfunction : m_free_recorder function unsigned get_recorders(ref uvm_recorder q[$]); q.delete(); foreach (m_records[idx]) begin q.push_back(idx); end return q.size(); endfunction : get_recorders local static uvm_tr_stream m_streams_by_id[int]; function int get_handle(); if (!is_open() && !is_closed()) begin return 0; end else begin int handle = get_inst_id(); if (m_ids_by_stream.exists(this) && m_ids_by_stream[this] != handle) begin m_streams_by_id.delete(m_ids_by_stream[this]); end m_streams_by_id[handle] = this; m_ids_by_stream[this] = handle; return handle; end endfunction : get_handle static function uvm_tr_stream get_stream_from_handle(int id); if (id == 0) begin return null; end if ($isunknown(id) || !m_streams_by_id.exists(id)) begin return null; end return m_streams_by_id[id]; endfunction : get_stream_from_handle static function void m_free_id(int id); uvm_tr_stream stream; if (!$isunknown(id) && m_streams_by_id.exists(id)) begin stream = m_streams_by_id[id]; end if (stream != null) begin m_streams_by_id.delete(id); m_ids_by_stream.delete(stream); end endfunction : m_free_id protected virtual function void do_open(uvm_tr_database db, string scope, string stream_type_name); endfunction : do_open protected virtual function void do_close(); endfunction : do_close protected virtual function void do_free(); endfunction : do_free protected virtual function uvm_recorder do_open_recorder(string name, time open_time, string type_name); return null; endfunction : do_open_recorder endclass : uvm_tr_stream class uvm_text_tr_stream extends uvm_tr_stream; local uvm_text_tr_database m_text_db; typedef uvm_object_registry#(uvm_text_tr_stream,"uvm_text_tr_stream") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_text_tr_stream tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_text_tr_stream"; endfunction : type_name virtual function string get_type_name(); return "uvm_text_tr_stream"; endfunction : get_type_name function void do_execute_op( uvm_field_op op ); super.do_execute_op(op); __m_uvm_execute_field_op(op); endfunction : do_execute_op local function void __m_uvm_execute_field_op( uvm_field_op __local_op__ ); uvm_field_flag_t local_op_type__; uvm_text_tr_stream local_rhs__; uvm_resource_base local_rsrc__; string local_rsrc_name__; uvm_object local_obj__; bit local_success__; typedef uvm_text_tr_stream __local_type__; int local_size__; uvm_printer __local_printer__; uvm_comparer __local_comparer__; uvm_recorder __local_recorder__; uvm_packer __local_packer__; uvm_copier __local_copier__; uvm_queue#(uvm_acs_name_struct) __local_field_names__; void'($cast(local_rhs__, __local_op__.get_rhs())); if (($cast(local_rsrc__, __local_op__.get_rhs())) && (local_rsrc__ != null)) local_rsrc_name__ = local_rsrc__.get_name(); local_op_type__ = __local_op__.get_op_type(); case (local_op_type__) UVM_PRINT: begin $cast(__local_printer__, __local_op__.get_policy()); end UVM_COMPARE: begin if (local_rhs__ == null) return; $cast(__local_comparer__, __local_op__.get_policy()); end UVM_RECORD: begin $cast(__local_recorder__, __local_op__.get_policy()); end UVM_PACK, UVM_UNPACK: begin $cast(__local_packer__, __local_op__.get_policy()); end UVM_COPY: begin if (local_rhs__ == null) return; $cast(__local_copier__, __local_op__.get_policy()); end UVM_SET: begin if (local_rsrc__ == null) return; end UVM_CHECK_FIELDS: begin $cast(__local_field_names__, __local_op__.get_rhs()); end default: return; endcase endfunction : __m_uvm_execute_field_op function new(string name="unnamed-uvm_text_tr_stream"); super.new(name); endfunction : new protected virtual function void do_open(uvm_tr_database db, string scope, string stream_type_name); $cast(m_text_db, db); if (m_text_db.open_db()) begin $fdisplay(m_text_db.m_file, " CREATE_STREAM @%0t {NAME:%s T:%s SCOPE:%s STREAM:%0d}", $time, this.get_name(), stream_type_name, scope, this.get_handle()); end endfunction : do_open protected virtual function void do_close(); if (m_text_db.open_db()) begin $fdisplay(m_text_db.m_file, " CLOSE_STREAM @%0t {NAME:%s T:%s SCOPE:%s STREAM:%0d}", $time, this.get_name(), this.get_stream_type_name(), this.get_scope(), this.get_handle()); end endfunction : do_close protected virtual function void do_free(); if (m_text_db.open_db()) begin $fdisplay(m_text_db.m_file, " FREE_STREAM @%0t {NAME:%s T:%s SCOPE:%s STREAM:%0d}", $time, this.get_name(), this.get_stream_type_name(), this.get_scope(), this.get_handle()); end m_text_db = null; return; endfunction : do_free protected virtual function uvm_recorder do_open_recorder(string name, time open_time, string type_name); if (m_text_db.open_db()) begin return uvm_text_recorder::type_id::create(name); end return null; endfunction : do_open_recorder endclass : uvm_text_tr_stream typedef class uvm_report_message; virtual class uvm_recorder extends uvm_policy; typedef uvm_abstract_object_registry#(uvm_recorder,"uvm_recorder") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_recorder"; endfunction : type_name virtual function string get_type_name(); return "uvm_recorder"; endfunction : get_type_name local uvm_set_before_get_dap#(uvm_tr_stream) m_stream_dap; local bit m_warn_null_stream; local bit m_is_opened; local bit m_is_closed; local time m_open_time; local time m_close_time; int recording_depth; uvm_radix_enum default_radix = UVM_HEX; bit identifier = 1; bit physical = 1; bit abstract = 1 ; integer tr_handle; uvm_policy::recursion_state_e m_recur_states[uvm_object][uvm_recursion_policy_enum ] ; uvm_recursion_policy_enum policy = UVM_DEFAULT_POLICY; virtual function void set_recursion_policy(uvm_recursion_policy_enum policy); this.policy = policy; endfunction : set_recursion_policy virtual function uvm_recursion_policy_enum get_recursion_policy(); return this.policy; endfunction : get_recursion_policy virtual function void set_id_enabled(bit enabled); this.identifier = enabled; endfunction : set_id_enabled virtual function bit get_id_enabled(); return this.identifier; endfunction : get_id_enabled virtual function void set_default_radix(uvm_radix_enum radix); this.default_radix = radix; endfunction : set_default_radix virtual function uvm_radix_enum get_default_radix(); return this.default_radix; endfunction : get_default_radix virtual function void flush(); policy = UVM_DEFAULT_POLICY; identifier = 1; free(); m_recur_states.delete(); endfunction : flush local static int m_ids_by_recorder[uvm_recorder]; function new(string name = "uvm_recorder"); super.new(name); m_stream_dap = new("stream_dap"); m_warn_null_stream = 1; endfunction function uvm_tr_stream get_stream(); if (!m_stream_dap.try_get(get_stream)) begin if (m_warn_null_stream == 1) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "UVM/REC/NO_CFG") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "UVM/REC/NO_CFG") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("UVM/REC/NO_CFG", $sformatf("attempt to retrieve STREAM from '%s' before it was set!", get_name()), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_recorder.svh", 192, "", 1); end end end m_warn_null_stream = 0; end endfunction : get_stream function void close(time close_time = 0); if (close_time == 0) begin close_time = $realtime; end if (!is_open()) begin return; end do_close(close_time); m_is_opened = 0; m_is_closed = 1; m_close_time = close_time; endfunction : close function void free(time close_time = 0); process p=process::self(); string s; uvm_tr_stream stream; if (!is_open() && !is_closed()) begin return; end if (is_open()) begin close(close_time); end do_free(); stream = get_stream(); m_is_closed = 0; if(p != null) begin s=p.get_randstate(); end m_stream_dap = new("stream_dap"); if(p != null) begin p.set_randstate(s); end m_warn_null_stream = 1; if (m_ids_by_recorder.exists(this)) begin m_free_id(m_ids_by_recorder[this]); end if (stream != null) begin stream.m_free_recorder(this); end endfunction : free function bit is_open(); return m_is_opened; endfunction : is_open function time get_open_time(); return m_open_time; endfunction : get_open_time function bit is_closed(); return m_is_closed; endfunction : is_closed function time get_close_time(); return m_close_time; endfunction : get_close_time function void m_do_open(uvm_tr_stream stream, time open_time, string type_name); uvm_tr_stream m_stream; if (stream == null) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM/REC/NULL_STREAM") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM/REC/NULL_STREAM") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM/REC/NULL_STREAM", $sformatf("Illegal attempt to set STREAM for '%s' to ''", this.get_name()), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_recorder.svh", 323, "", 1); end end return; end if (m_stream_dap.try_get(m_stream)) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM/REC/RE_INIT") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM/REC/RE_INIT") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM/REC/RE_INIT", $sformatf("Illegal attempt to re-initialize '%s'", this.get_name()), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_recorder.svh", 330, "", 1); end end return; end m_stream_dap.set(stream); m_open_time = open_time; m_is_opened = 1; do_open(stream, open_time, type_name); endfunction : m_do_open local static uvm_recorder m_recorders_by_id[int]; local static int m_id; static function void m_free_id(int id); uvm_recorder recorder; if ((!$isunknown(id)) && (m_recorders_by_id.exists(id))) begin recorder = m_recorders_by_id[id]; end if (recorder != null) begin m_recorders_by_id.delete(id); m_ids_by_recorder.delete(recorder); end endfunction : m_free_id function int get_handle(); if (!is_open() && !is_closed()) begin return 0; end else begin int handle = get_inst_id(); if (m_ids_by_recorder.exists(this) && m_ids_by_recorder[this] != handle) begin m_recorders_by_id.delete(m_ids_by_recorder[this]); end m_recorders_by_id[handle] = this; m_ids_by_recorder[this] = handle; return handle; end endfunction : get_handle static function uvm_recorder get_recorder_from_handle(int id); if (id == 0) begin return null; end if (($isunknown(id)) || (!m_recorders_by_id.exists(id))) begin return null; end return m_recorders_by_id[id]; endfunction : get_recorder_from_handle function void record_field(string name, uvm_bitstream_t value, int size, uvm_radix_enum radix=UVM_NORADIX); if (get_stream() == null) begin return; end do_record_field(name, value, size, radix); endfunction : record_field function void record_field_int(string name, uvm_integral_t value, int size, uvm_radix_enum radix=UVM_NORADIX); if (get_stream() == null) begin return; end do_record_field_int(name, value, size, radix); endfunction : record_field_int function void record_field_real(string name, real value); if (get_stream() == null) begin return; end do_record_field_real(name, value); endfunction : record_field_real function void record_object(string name, uvm_object value); if (get_stream() == null) begin return; end if (value == null) begin do_record_object(name, value); end else begin push_active_object(value); m_recur_states[value][get_recursion_policy()] = uvm_policy::STARTED ; do_record_object(name, value); m_recur_states[value][get_recursion_policy()] = uvm_policy::FINISHED ; void'(pop_active_object()); end endfunction : record_object function void record_string(string name, string value); if (get_stream() == null) begin return; end do_record_string(name, value); endfunction : record_string function void record_time(string name, time value); if (get_stream() == null) begin return; end do_record_time(name, value); endfunction : record_time function void record_generic(string name, string value, string type_name=""); if (get_stream() == null) begin return; end do_record_generic(name, value, type_name); endfunction : record_generic virtual function bit use_record_attribute(); return 0; endfunction : use_record_attribute virtual function int get_record_attribute_handle(); return get_handle(); endfunction : get_record_attribute_handle protected virtual function void do_open(uvm_tr_stream stream, time open_time, string type_name); endfunction : do_open protected virtual function void do_close(time close_time); endfunction : do_close protected virtual function void do_free(); endfunction : do_free pure virtual protected function void do_record_field(string name, uvm_bitstream_t value, int size, uvm_radix_enum radix); pure virtual protected function void do_record_field_int(string name, uvm_integral_t value, int size, uvm_radix_enum radix); pure virtual protected function void do_record_field_real(string name, real value); virtual protected function void do_record_object(string name, uvm_object value); if ((get_recursion_policy() != UVM_REFERENCE) && (value != null)) begin uvm_field_op field_op = uvm_field_op::m_get_available_op(); field_op.set(UVM_RECORD, this, null); value.do_execute_op(field_op); if (field_op.user_hook_enabled()) begin value.do_record(this); end field_op.m_recycle(); end endfunction : do_record_object virtual function uvm_policy::recursion_state_e object_recorded ( uvm_object value, uvm_recursion_policy_enum recursion); if (!m_recur_states.exists(value)) begin return NEVER ; end if (!m_recur_states[value].exists(recursion)) begin return NEVER ; end else begin return m_recur_states[value][recursion] ; end endfunction pure virtual protected function void do_record_string(string name, string value); pure virtual protected function void do_record_time(string name, time value); pure virtual protected function void do_record_generic(string name, string value, string type_name); virtual function bit open_file(); return 0; endfunction virtual function integer create_stream (string name, string t, string scope); return -1; endfunction virtual function void m_set_attribute (int txh, string nm, string value); endfunction virtual function void set_attribute (int txh, string nm, logic [1023:0] value, uvm_radix_enum radix, int numbits=1024); endfunction virtual function int check_handle_kind (string htype, int handle); return 0; endfunction virtual function int begin_tr(string txtype, int stream, string nm, string label="", string desc="", time begin_time=0); return -1; endfunction virtual function void end_tr (int handle, time end_time=0); endfunction virtual function void link_tr(int h1, int h2, string relation=""); endfunction virtual function void free_tr(int handle); endfunction endclass class uvm_text_recorder extends uvm_recorder; typedef uvm_object_registry#(uvm_text_recorder,"uvm_text_recorder") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_text_recorder tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_text_recorder"; endfunction : type_name virtual function string get_type_name(); return "uvm_text_recorder"; endfunction : get_type_name uvm_text_tr_database m_text_db; function new(string name="unnamed-uvm_text_recorder"); super.new(name); endfunction : new protected virtual function void do_open(uvm_tr_stream stream, time open_time, string type_name); $cast(m_text_db, stream.get_db()); if (m_text_db.open_db()) begin $fdisplay(m_text_db.m_file, " OPEN_RECORDER @%0t {TXH:%0d STREAM:%0d NAME:%s TIME:%0t TYPE=\"%0s\"}", $realtime, this.get_handle(), stream.get_handle(), this.get_name(), open_time, type_name); end endfunction : do_open protected virtual function void do_close(time close_time); if (m_text_db.open_db()) begin $fdisplay(m_text_db.m_file, " CLOSE_RECORDER @%0t {TXH:%0d TIME=%0t}", $realtime, this.get_handle(), close_time); end endfunction : do_close protected virtual function void do_free(); if (m_text_db.open_db()) begin $fdisplay(m_text_db.m_file, " FREE_RECORDER @%0t {TXH:%0d}", $realtime, this.get_handle()); end m_text_db = null; endfunction : do_free protected virtual function void do_record_field(string name, uvm_bitstream_t value, int size, uvm_radix_enum radix); if(radix == UVM_NORADIX) begin radix = get_default_radix(); end write_attribute(m_current_context(name), value, radix, size); endfunction : do_record_field protected virtual function void do_record_field_int(string name, uvm_integral_t value, int size, uvm_radix_enum radix); if(radix == UVM_NORADIX) begin radix = get_default_radix(); end write_attribute_int(m_current_context(name), value, radix, size); endfunction : do_record_field_int protected virtual function void do_record_field_real(string name, real value); bit [63:0] ival = $realtobits(value); write_attribute_int(m_current_context(name), ival, UVM_REAL, 64); endfunction : do_record_field_real local string m_object_names[$]; local function string m_current_context(string name=""); if (m_object_names.size() == 0) begin return name; end else if ((m_object_names.size() == 1) && (name=="")) begin return m_object_names[0]; end else begin string full_name; foreach(m_object_names[i]) begin if (i == m_object_names.size() - 1) begin full_name = {full_name, m_object_names[i]}; end else begin full_name = {full_name, m_object_names[i], "."}; end end if (name != "") begin return {full_name, ".", name}; end else begin return full_name; end end endfunction : m_current_context protected virtual function void do_record_object(string name, uvm_object value); int v; string str; if(get_id_enabled()) begin if(value != null) begin v = value.get_inst_id(); end write_attribute_int("inst_id", v, UVM_DEC, 32); end if (get_active_object_depth() > 1) begin m_object_names.push_back(name); end super.do_record_object(name, value); if (get_active_object_depth() > 1) begin void'(m_object_names.pop_back()); end endfunction : do_record_object protected virtual function void do_record_string(string name, string value); if (m_text_db.open_db()) begin $fdisplay(m_text_db.m_file, " SET_ATTR @%0t {TXH:%0d NAME:%s VALUE:%s RADIX:%s BITS=%0d}", $realtime, this.get_handle(), m_current_context(name), value, "UVM_STRING", 8+value.len()); end endfunction : do_record_string protected virtual function void do_record_time(string name, time value); write_attribute_int(m_current_context(name), value, UVM_TIME, 64); endfunction : do_record_time protected virtual function void do_record_generic(string name, string value, string type_name); write_attribute(m_current_context(name), uvm_string_to_bits(value), UVM_STRING, 8+value.len()); endfunction : do_record_generic function void write_attribute(string nm, uvm_bitstream_t value, uvm_radix_enum radix, int numbits=$bits(uvm_bitstream_t)); if (m_text_db.open_db()) begin $fdisplay(m_text_db.m_file, " SET_ATTR @%0t {TXH:%0d NAME:%s VALUE:%s RADIX:%s BITS=%0d}", $realtime, this.get_handle(), nm, uvm_bit_vector_utils#(uvm_bitstream_t)::to_string(value, numbits, radix), radix.name(), numbits); end endfunction : write_attribute function void write_attribute_int(string nm, uvm_integral_t value, uvm_radix_enum radix, int numbits=$bits(uvm_bitstream_t)); if (m_text_db.open_db()) begin $fdisplay(m_text_db.m_file, " SET_ATTR @%0t {TXH:%0d NAME:%s VALUE:%s RADIX:%s BITS=%0d}", $realtime, this.get_handle(), nm, uvm_bit_vector_utils#(uvm_integral_t)::to_string(value, numbits, radix), radix.name(), numbits); end endfunction : write_attribute_int string filename; bit filename_set; virtual function bit open_file(); if (!filename_set) begin m_text_db.set_file_name(filename); end return m_text_db.open_db(); endfunction virtual function integer create_stream (string name, string t, string scope); uvm_text_tr_stream stream; if (open_file()) begin $cast(stream,m_text_db.open_stream(name, scope, t)); return stream.get_handle(); end return 0; endfunction virtual function void m_set_attribute (int txh, string nm, string value); if (open_file()) begin UVM_FILE file = m_text_db.m_file; $fdisplay(file," SET_ATTR @%0t {TXH:%0d NAME:%s VALUE:%s}", $realtime,txh,nm,value); end endfunction virtual function void set_attribute (int txh, string nm, logic [1023:0] value, uvm_radix_enum radix, int numbits=1024); if (open_file()) begin UVM_FILE file = m_text_db.m_file; $fdisplay(file, " SET_ATTR @%0t {TXH:%0d NAME:%s VALUE:%s RADIX:%s BITS=%0d}", $realtime, txh, nm, uvm_bit_vector_utils#(uvm_bitstream_t)::to_string(value, numbits, radix), radix.name(), numbits); end endfunction virtual function int check_handle_kind (string htype, int handle); return ((uvm_recorder::get_recorder_from_handle(handle) != null) || (uvm_tr_stream::get_stream_from_handle(handle) != null)); endfunction virtual function int begin_tr(string txtype, int stream, string nm, string label="", string desc="", time begin_time=0); if (open_file()) begin uvm_tr_stream stream_obj = uvm_tr_stream::get_stream_from_handle(stream); uvm_recorder recorder; if (stream_obj == null) begin return -1; end recorder = stream_obj.open_recorder(nm, begin_time, txtype); return recorder.get_handle(); end return -1; endfunction virtual function void end_tr (int handle, time end_time=0); if (open_file()) begin uvm_recorder record = uvm_recorder::get_recorder_from_handle(handle); if (record != null) begin record.close(end_time); end end endfunction virtual function void link_tr(int h1, int h2, string relation=""); if (open_file()) begin $fdisplay(m_text_db.m_file," LINK @%0t {TXH1:%0d TXH2:%0d RELATION=%0s}", $realtime,h1,h2,relation); end endfunction virtual function void free_tr(int handle); if (open_file()) begin uvm_recorder record = uvm_recorder::get_recorder_from_handle(handle); if (record != null) begin record.free(); end end endfunction endclass : uvm_text_recorder typedef class uvm_object; typedef class uvm_event; typedef class uvm_callback; typedef class uvm_callbacks; virtual class uvm_event_callback#(type T=uvm_object) extends uvm_callback; function new (string name=""); super.new(name); endfunction virtual function bit pre_trigger (uvm_event#(T) e, T data); return 0; endfunction virtual function void post_trigger (uvm_event#(T) e, T data); return; endfunction virtual function uvm_object create (string name=""); return null; endfunction endclass virtual class uvm_event_base extends uvm_object; typedef uvm_abstract_object_registry#(uvm_event_base,"uvm_event_base") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_event_base"; endfunction : type_name virtual function string get_type_name(); return "uvm_event_base"; endfunction : get_type_name protected event m_event; protected int num_waiters; protected bit on; protected time trigger_time=0; function new (string name=""); super.new(name); endfunction virtual task wait_on (bit delta = 0); if (on) begin if (delta) begin #0; end return; end num_waiters++; @on; endtask virtual task wait_off (bit delta = 0); if (!on) begin if (delta) begin #0; end return; end num_waiters++; @on; endtask virtual task wait_trigger (); num_waiters++; @m_event; endtask virtual task wait_ptrigger (); if (m_event.triggered) begin return; end num_waiters++; @m_event; endtask virtual function time get_trigger_time (); return trigger_time; endfunction virtual function bit is_on (); return (on == 1); endfunction virtual function bit is_off (); return (on == 0); endfunction virtual function void reset (bit wakeup = 0); event e; if (wakeup) begin ->m_event; end m_event = e; num_waiters = 0; on = 0; trigger_time = 0; endfunction virtual function void cancel (); if (num_waiters > 0) begin num_waiters--; end endfunction virtual function int get_num_waiters (); return num_waiters; endfunction virtual function void do_print (uvm_printer printer); printer.print_field_int("num_waiters", num_waiters, $bits(num_waiters), UVM_DEC, ".", "int"); printer.print_field_int("on", on, $bits(on), UVM_BIN, ".", "bit"); printer.print_time("trigger_time", trigger_time); endfunction virtual function void do_copy (uvm_object rhs); uvm_event_base e; super.do_copy(rhs); if(!$cast(e, rhs) || (e==null)) begin return; end m_event = e.m_event; num_waiters = e.num_waiters; on = e.on; trigger_time = e.trigger_time; endfunction endclass class uvm_event#(type T=uvm_object) extends uvm_event_base; typedef uvm_event#(T) this_type; typedef uvm_event_callback#(T) cb_type; typedef uvm_callbacks#(this_type, cb_type) cbs_type; static local function bit m_register_cb(); return cbs_type::m_register_pair("uvm_pkg::uvm_event#(T)", "uvm_pkg::uvm_event_callback#(T)" ); endfunction : m_register_cb static local bit m_cb_registered = m_register_cb(); typedef uvm_object_registry #(this_type) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); this_type tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction virtual function string get_type_name(); return "uvm_pkg::uvm_event#(T)"; endfunction : get_type_name local T trigger_data; local T default_data; function new (string name=""); super.new(name); endfunction virtual function void reset (bit wakeup = 0); trigger_data = get_default_data(); super.reset(wakeup); endfunction : reset virtual task wait_trigger_data (output T data); wait_trigger(); data = get_trigger_data(); endtask virtual task wait_ptrigger_data (output T data); wait_ptrigger(); data = get_trigger_data(); endtask virtual function void trigger (T data=get_default_data()); int skip; cb_type cb_q[$]; skip=0; cbs_type::get_all(cb_q, this); foreach (cb_q[i]) begin skip += cb_q[i].pre_trigger(this, data); end if (skip==0) begin on = 1; trigger_time = $realtime; trigger_data = data; ->m_event; foreach (cb_q[i]) begin cb_q[i].post_trigger(this, data); end num_waiters = 0; end endfunction virtual function T get_trigger_data (); return trigger_data; endfunction virtual function T get_default_data(); return default_data; endfunction : get_default_data virtual function void set_default_data(T data); default_data = data; endfunction : set_default_data virtual function void do_print (uvm_printer printer); uvm_event#(uvm_object) oe; cb_type cb_q[$]; super.do_print(printer); cbs_type::get_all(cb_q, this); printer.print_array_header("callbacks", cb_q.size(), "queue"); foreach(cb_q[e]) begin printer.print_object($sformatf("[%0d]", e), cb_q[e], "["); end printer.print_array_footer(cb_q.size()); if ($cast(oe, this)) begin printer.print_object("trigger_data", oe.get_trigger_data()); end else begin uvm_event#(string) se; if ($cast(se, this)) begin printer.print_string("trigger_data", se.get_trigger_data()); end end endfunction virtual function void do_copy (uvm_object rhs); this_type e; cb_type cb_q[$]; super.do_copy(rhs); if(!$cast(e, rhs) || (e==null)) begin return; end trigger_data = e.trigger_data; begin cbs_type::get_all(cb_q, this); foreach(cb_q[i]) begin cbs_type::delete(this, cb_q[i]); end cb_q.delete(); cbs_type::get_all(cb_q, e); foreach(cb_q[i]) begin cbs_type::add(this, cb_q[i]); end end endfunction virtual function void add_callback(cb_type cb, bit append=1); uvm_apprepend ordering; ordering = (append) ? UVM_APPEND : UVM_PREPEND; cbs_type::add(this, cb, ordering); endfunction virtual function void delete_callback(cb_type cb); cbs_type::delete(this, cb); endfunction endclass class uvm_barrier extends uvm_object; local int threshold; local int num_waiters; local bit at_threshold; local bit auto_reset; local uvm_event#(uvm_object) m_event; typedef uvm_object_registry#(uvm_barrier,"uvm_barrier") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_barrier tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_barrier"; endfunction : type_name virtual function string get_type_name(); return "uvm_barrier"; endfunction : get_type_name function new (string name="", int threshold=0); super.new(name); m_event = new({"barrier_",name}); this.threshold = threshold; num_waiters = 0; auto_reset = 1; at_threshold = 0; endfunction virtual task wait_for(); if (at_threshold) begin return; end num_waiters++; if (num_waiters >= threshold) begin if (!auto_reset) begin at_threshold=1; end m_trigger(); return; end m_event.wait_trigger(); endtask virtual function void reset (bit wakeup=1); at_threshold = 0; if (num_waiters) begin if (wakeup) begin m_event.trigger(); end else begin m_event.reset(); end end num_waiters = 0; endfunction virtual function void set_auto_reset (bit value=1); at_threshold = 0; auto_reset = value; endfunction virtual function void set_threshold (int threshold); this.threshold = threshold; if (threshold <= num_waiters) begin reset(1); end endfunction virtual function int get_threshold (); return threshold; endfunction virtual function int get_num_waiters (); return num_waiters; endfunction virtual function void cancel (); m_event.cancel(); num_waiters = m_event.get_num_waiters(); endfunction local task m_trigger(); m_event.trigger(); num_waiters=0; #0; endtask virtual function void do_print (uvm_printer printer); printer.print_field_int("threshold", threshold, $bits(threshold), UVM_DEC, ".", "int"); printer.print_field_int("num_waiters", num_waiters, $bits(num_waiters), UVM_DEC, ".", "int"); printer.print_field_int("at_threshold", at_threshold, $bits(at_threshold), UVM_BIN, ".", "bit"); printer.print_field_int("auto_reset", auto_reset, $bits(auto_reset), UVM_BIN, ".", "bit"); endfunction virtual function void do_copy (uvm_object rhs); uvm_barrier b; super.do_copy(rhs); if(!$cast(b, rhs) || (b==null)) begin return; end threshold = b.threshold; num_waiters = b.num_waiters; at_threshold = b.at_threshold; auto_reset = b.auto_reset; m_event = b.m_event; endfunction endclass typedef class uvm_root; typedef class uvm_callback; typedef class uvm_callbacks_base; class uvm_typeid_base; static string typename; static uvm_callbacks_base typeid_map[uvm_typeid_base]; static uvm_typeid_base type_map[uvm_callbacks_base]; endclass class uvm_typeid#(type T=uvm_object) extends uvm_typeid_base; static uvm_typeid#(T) m_b_inst; static function uvm_typeid#(T) get(); if(m_b_inst == null) begin m_b_inst = new; end return m_b_inst; endfunction endclass class uvm_callbacks_base extends uvm_object; typedef uvm_callbacks_base this_type; static bit m_tracing = 1; static this_type m_b_inst; static uvm_pool#(uvm_object,uvm_queue#(uvm_callback)) m_pool; static function this_type m_initialize(); if(m_b_inst == null) begin m_b_inst = new; m_pool = new; end return m_b_inst; endfunction this_type m_this_type[$]; uvm_typeid_base m_super_type; uvm_typeid_base m_derived_types[$]; virtual function bit m_am_i_a(uvm_object obj); return 0; endfunction virtual function bit m_is_for_me(uvm_callback cb); return 0; endfunction virtual function bit m_is_registered(uvm_object obj, uvm_callback cb); return 0; endfunction virtual function uvm_queue#(uvm_callback) m_get_tw_cb_q(uvm_object obj); return null; endfunction virtual function void m_add_tw_cbs(uvm_callback cb, uvm_apprepend ordering); endfunction virtual function bit m_delete_tw_cbs(uvm_callback cb); return 0; endfunction function bit check_registration(uvm_object obj, uvm_callback cb); this_type dt; if (m_is_registered(obj,cb)) begin return 1; end foreach(m_this_type[i]) begin if(m_b_inst != m_this_type[i] && m_this_type[i].m_is_registered(obj,cb)) begin return 1; end end if(obj == null) begin foreach(m_derived_types[i]) begin dt = uvm_typeid_base::typeid_map[m_derived_types[i] ]; if(dt != null && dt.check_registration(null,cb)) begin return 1; end end end return 0; endfunction endclass class uvm_typed_callbacks#(type T=uvm_object) extends uvm_callbacks_base; static uvm_queue#(uvm_callback) m_tw_cb_q; static string m_typename; typedef uvm_typed_callbacks#(T) this_type; typedef uvm_callbacks_base super_type; static this_type m_t_inst; static function this_type m_initialize(); if(m_t_inst == null) begin void'(super_type::m_initialize()); m_t_inst = new; m_t_inst.m_tw_cb_q = new("typewide_queue"); end return m_t_inst; endfunction virtual function bit m_am_i_a(uvm_object obj); T this_type_inst; if (obj == null) begin return 1; end return($cast(this_type_inst,obj)); endfunction virtual function uvm_queue#(uvm_callback) m_get_tw_cb_q(uvm_object obj); if(m_am_i_a(obj)) begin foreach(m_derived_types[i]) begin super_type dt; dt = uvm_typeid_base::typeid_map[m_derived_types[i] ]; if(dt != null && dt != this) begin m_get_tw_cb_q = dt.m_get_tw_cb_q(obj); if(m_get_tw_cb_q != null) begin return m_get_tw_cb_q; end end end return m_t_inst.m_tw_cb_q; end else begin return null; end endfunction static function int m_cb_find(uvm_queue#(uvm_callback) q, uvm_callback cb); for(int i=0; i str.len() ? max_cb_name : str.len(); str = "(*)"; max_inst_name = max_inst_name > str.len() ? max_inst_name : str.len(); end if(obj ==null) begin if(m_t_inst.m_pool.first(bobj)) begin do begin if($cast(me,bobj)) begin break; end end while(m_t_inst.m_pool.next(bobj)); end if(me != null || m_t_inst.m_tw_cb_q.size()) begin qs.push_back($sformatf("Registered callbacks for all instances of %s\n", tname)); qs.push_back("---------------------------------------------------------------\n"); end if(me != null) begin do begin if($cast(me,bobj)) begin q = m_t_inst.m_pool.get(bobj); if (q==null) begin q=new; m_t_inst.m_pool.add(bobj,q); end for(int i=0; i str.len() ? max_cb_name : str.len(); str = bobj.get_full_name(); max_inst_name = max_inst_name > str.len() ? max_inst_name : str.len(); end end end while (m_t_inst.m_pool.next(bobj)); end else begin qs.push_back($sformatf("No callbacks registered for any instances of type %s\n", tname)); end end else begin if(m_t_inst.m_pool.exists(bobj) || m_t_inst.m_tw_cb_q.size()) begin qs.push_back($sformatf("Registered callbacks for instance %s of %s\n", obj.get_full_name(), tname)); qs.push_back("---------------------------------------------------------------\n"); end if(m_t_inst.m_pool.exists(bobj)) begin q = m_t_inst.m_pool.get(bobj); if(q==null) begin q=new; m_t_inst.m_pool.add(bobj,q); end for(int i=0; i str.len() ? max_cb_name : str.len(); str = bobj.get_full_name(); max_inst_name = max_inst_name > str.len() ? max_inst_name : str.len(); end end end if(!cbq.size()) begin if(obj == null) begin str = "*"; end else begin str = obj.get_full_name(); end qs.push_back($sformatf("No callbacks registered for instance %s of type %s\n", str, tname)); end foreach (cbq[i]) begin qs.push_back($sformatf("%s %s %s on %s %s\n", cbq[i], blanks.substr(0,max_cb_name-cbq[i].len()-1), inst_q[i], blanks.substr(0,max_inst_name - inst_q[i].len()-1), mode_q[i])); end begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "UVM/CB/DISPLAY") >= UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "UVM/CB/DISPLAY") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("UVM/CB/DISPLAY", uvm_pkg::m_uvm_string_queue_join(qs), UVM_NONE, "t/uvm/src/base/uvm_callback.svh", 511, "", 1); end end m_tracing = 1; endfunction endclass class uvm_callbacks #(type T=uvm_object, type CB=uvm_callback) extends uvm_typed_callbacks#(T); typedef uvm_typed_callbacks#(T) super_type; typedef uvm_callbacks#(T,CB) this_type; local static this_type m_inst; static uvm_typeid_base m_typeid; static uvm_typeid_base m_cb_typeid; static string m_typename; static string m_cb_typename; static uvm_callbacks#(T,uvm_callback) m_base_inst; bit m_registered; static function this_type get(); if (m_inst == null) begin uvm_typeid_base cb_base_type; void'(super_type::m_initialize()); cb_base_type = uvm_typeid#(uvm_callback)::get(); m_cb_typeid = uvm_typeid#(CB)::get(); m_typeid = uvm_typeid#(T)::get(); m_inst = new; if (cb_base_type == m_cb_typeid) begin $cast(m_base_inst, m_inst); m_t_inst = m_base_inst; uvm_typeid_base::typeid_map[m_typeid] = m_inst; uvm_typeid_base::type_map[m_b_inst] = m_typeid; end else begin m_base_inst = uvm_callbacks#(T,uvm_callback)::get(); m_base_inst.m_this_type.push_back(m_inst); end if (m_inst == null) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "CB/INTERNAL") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "CB/INTERNAL") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("CB/INTERNAL", "get(): m_inst is null", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_callback.svh", 617, "", 1); end end end end return m_inst; endfunction static function bit m_register_pair(string tname="", cbname=""); this_type inst = get(); m_typename = tname; super_type::m_typename = tname; m_typeid.typename = tname; m_cb_typename = cbname; m_cb_typeid.typename = cbname; inst.m_registered = 1; return 1; endfunction virtual function bit m_is_registered(uvm_object obj, uvm_callback cb); if(m_is_for_me(cb) && m_am_i_a(obj)) begin return m_registered; end endfunction virtual function bit m_is_for_me(uvm_callback cb); CB this_cb; return($cast(this_cb,cb)); endfunction static function void add(T obj, uvm_callback cb, uvm_apprepend ordering=UVM_APPEND); uvm_queue#(uvm_callback) q; string nm,tnm; void'(get()); if (cb==null) begin if (obj==null) begin nm = "(*)"; end else begin nm = obj.get_full_name(); end if (m_base_inst.m_typename!="") begin tnm = m_base_inst.m_typename; end else if (obj != null) begin tnm = obj.get_type_name(); end else begin tnm = "uvm_object"; end uvm_report_error("CBUNREG", {"Null callback object cannot be registered with object ", nm, " (", tnm, ")"}, UVM_NONE); return; end if (!m_base_inst.check_registration(obj,cb)) begin if (obj==null) begin nm = "(*)"; end else begin nm = obj.get_full_name(); end if (m_base_inst.m_typename!="") begin tnm = m_base_inst.m_typename; end else if(obj != null) begin tnm = obj.get_type_name(); end else begin tnm = "uvm_object"; end uvm_report_warning("CBUNREG", {"Callback ", cb.get_name(), " cannot be registered with object ", nm, " because callback type ", cb.get_type_name(), " is not registered with object type ", tnm }, UVM_NONE); end if(obj == null) begin if (m_cb_find(m_t_inst.m_tw_cb_q,cb) != -1) begin if (m_base_inst.m_typename!="") begin tnm = m_base_inst.m_typename; end else begin tnm = "uvm_object"; end uvm_report_warning("CBPREG", {"Callback object ", cb.get_name(), " is already registered with type ", tnm }, UVM_NONE); end else begin m_t_inst.m_add_tw_cbs(cb,ordering); end end else begin q = m_base_inst.m_pool.get(obj); if (q==null) begin q=new; m_base_inst.m_pool.add(obj,q); end if(q.size() == 0) begin uvm_report_object o; if($cast(o,obj)) begin uvm_queue#(uvm_callback) qr; void'(uvm_callbacks#(uvm_report_object, uvm_callback)::get()); qr = uvm_callbacks#(uvm_report_object,uvm_callback)::m_t_inst.m_tw_cb_q; for(int i=0; i=0; --itr) begin if ($cast(cb, q.get(itr)) && cb.callback_mode()) begin return cb; end end return null; endfunction static function CB get_next (ref int itr, input T obj); uvm_queue#(uvm_callback) q; CB cb; void'(get()); m_get_q(q,obj); for(itr = itr+1; itr= 0; --itr) begin if($cast(cb, q.get(itr)) && cb.callback_mode()) begin return cb; end end return null; endfunction static function void get_all ( ref CB all_callbacks[$], input T obj=null ); uvm_queue#(uvm_callback) q; CB cb; CB callbacks_to_append[$]; CB unique_callbacks_to_append[$]; void'( get() ); if ((obj == null) || (!m_pool.exists(obj))) begin for (int qi=0; qi= UVM_LOW) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "UVM/REPORT/CATCHER") != uvm_pkg::UVM_NO_ACTION)) begin _local_report_object_.uvm_report_info("UVM/REPORT/CATCHER", uvm_pkg::m_uvm_string_queue_join(q), UVM_LOW, "t/uvm/src/base/uvm_report_catcher.svh", 369, "", 1); end end endfunction static function void debug_report_catcher(int what= 0); m_debug_flags = what; endfunction pure virtual function action_e catch(); protected function void uvm_report_fatal(string id, string message, int verbosity, string fname = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); this.uvm_report(UVM_FATAL, id, message, UVM_NONE, fname, line, context_name, report_enabled_checked); endfunction protected function void uvm_report_error(string id, string message, int verbosity, string fname = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); this.uvm_report(UVM_ERROR, id, message, UVM_NONE, fname, line, context_name, report_enabled_checked); endfunction protected function void uvm_report_warning(string id, string message, int verbosity, string fname = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); this.uvm_report(UVM_WARNING, id, message, UVM_NONE, fname, line, context_name, report_enabled_checked); endfunction protected function void uvm_report_info(string id, string message, int verbosity, string fname = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); this.uvm_report(UVM_INFO, id, message, verbosity, fname, line, context_name, report_enabled_checked); endfunction protected function void uvm_report(uvm_severity severity, string id, string message, int verbosity, string fname = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_report_message l_report_message; if (report_enabled_checked == 0) begin if (!uvm_report_enabled(verbosity, severity, id)) begin return; end end l_report_message = uvm_report_message::new_report_message(); l_report_message.set_report_message(severity, id, message, verbosity, fname, line, context_name); this.uvm_process_report_message(l_report_message); endfunction protected function void uvm_process_report_message(uvm_report_message msg); uvm_report_object ro = m_modified_report_message.get_report_object(); uvm_action a = ro.get_report_action(msg.get_severity(), msg.get_id()); if(a) begin string composed_message; uvm_report_server rs = m_modified_report_message.get_report_server(); msg.set_report_object(ro); msg.set_report_handler(m_modified_report_message.get_report_handler()); msg.set_report_server(rs); msg.set_file(ro.get_report_file_handle(msg.get_severity(), msg.get_id())); msg.set_action(a); if (a & (UVM_LOG|UVM_DISPLAY)) begin composed_message = rs.compose_report_message(msg); end rs.execute_report_message(msg, composed_message); end endfunction protected function void issue(); string composed_message; uvm_report_server rs = m_modified_report_message.get_report_server(); if(uvm_action_type'(m_modified_report_message.get_action()) != UVM_NO_ACTION) begin if (m_modified_report_message.get_action() & (UVM_LOG|UVM_DISPLAY)) begin composed_message = rs.compose_report_message(m_modified_report_message); end rs.execute_report_message(m_modified_report_message, composed_message); end endfunction static function int process_all_report_catchers(uvm_report_message rm); int iter; uvm_report_catcher catcher; int thrown = 1; uvm_severity orig_severity; static bit in_catcher; uvm_report_object l_report_object = rm.get_report_object(); if(in_catcher == 1) begin return 1; end in_catcher = 1; uvm_callbacks_base::m_tracing = 0; orig_severity = uvm_severity'(rm.get_severity()); m_modified_report_message = rm; catcher = uvm_report_cb::get_first(iter,l_report_object); if (catcher != null) begin if(m_debug_flags & DO_NOT_MODIFY) begin process p = process::self(); string randstate; if (p != null) begin randstate = p.get_randstate(); end $cast(m_orig_report_message, rm.clone()); if (p != null) begin p.set_randstate(randstate); end end end while(catcher != null) begin uvm_severity prev_sev; if (!catcher.callback_mode()) begin catcher = uvm_report_cb::get_next(iter,l_report_object); continue; end prev_sev = m_modified_report_message.get_severity(); m_set_action_called = 0; thrown = catcher.process_report_catcher(); if (!m_set_action_called && m_modified_report_message.get_severity() != prev_sev && m_modified_report_message.get_action() == l_report_object.get_report_action(prev_sev, "*@&*^*^*#")) begin m_modified_report_message.set_action( l_report_object.get_report_action(m_modified_report_message.get_severity(), "*@&*^*^*#")); end if(thrown == 0) begin case(orig_severity) UVM_FATAL: begin m_caught_fatal++; end UVM_ERROR: begin m_caught_error++; end UVM_WARNING: begin m_caught_warning++; end endcase break; end catcher = uvm_report_cb::get_next(iter,l_report_object); end case(orig_severity) UVM_FATAL: begin if(m_modified_report_message.get_severity() < orig_severity) begin m_demoted_fatal++; end end UVM_ERROR: begin if(m_modified_report_message.get_severity() < orig_severity) begin m_demoted_error++; end end UVM_WARNING: begin if(m_modified_report_message.get_severity() < orig_severity) begin m_demoted_warning++; end end endcase in_catcher = 0; uvm_callbacks_base::m_tracing = 1; return thrown; endfunction local function int process_report_catcher(); action_e act; act = this.catch(); if(act == UNKNOWN_ACTION) begin this.uvm_report_error("RPTCTHR", {"uvm_report_this.catch() in catcher instance ", this.get_name(), " must return THROW or CAUGHT"}, UVM_NONE, "t/uvm/src/base/uvm_report_catcher.svh", 683); end if(m_debug_flags & DO_NOT_MODIFY) begin m_modified_report_message.copy(m_orig_report_message); end if(act == CAUGHT && !(m_debug_flags & DO_NOT_CATCH)) begin return 0; end return 1; endfunction static function void summarize(UVM_FILE file = UVM_STDOUT); string s; uvm_root root = uvm_root::get(); uvm_action action; string q[$]; if(do_report) begin q.push_back("\n--- UVM Report catcher Summary ---\n\n\n"); q.push_back($sformatf("Number of demoted UVM_FATAL reports :%5d\n", m_demoted_fatal)); q.push_back($sformatf("Number of demoted UVM_ERROR reports :%5d\n", m_demoted_error)); q.push_back($sformatf("Number of demoted UVM_WARNING reports:%5d\n", m_demoted_warning)); q.push_back($sformatf("Number of caught UVM_FATAL reports :%5d\n", m_caught_fatal)); q.push_back($sformatf("Number of caught UVM_ERROR reports :%5d\n", m_caught_error)); q.push_back($sformatf("Number of caught UVM_WARNING reports :%5d\n", m_caught_warning)); if(file == UVM_STDOUT) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = root.uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "UVM/REPORT/CATCHER") >= UVM_LOW) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "UVM/REPORT/CATCHER") != uvm_pkg::UVM_NO_ACTION)) begin _local_report_object_.uvm_report_info("UVM/REPORT/CATCHER", uvm_pkg::m_uvm_string_queue_join(q), UVM_LOW, "t/uvm/src/base/uvm_report_catcher.svh", 720, "", 1); end end end else begin action = root.get_report_action(UVM_INFO, "UVM/REPORT/CATCHER"); root.set_report_id_action("UVM/REPORT/CATCHER", UVM_LOG); root.set_report_id_file("UVM/REPORT/CATCHER", file); begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = root.uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "UVM/REPORT/CATCHER") >= UVM_LOW) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "UVM/REPORT/CATCHER") != uvm_pkg::UVM_NO_ACTION)) begin _local_report_object_.uvm_report_info("UVM/REPORT/CATCHER", uvm_pkg::m_uvm_string_queue_join(q), UVM_LOW, "t/uvm/src/base/uvm_report_catcher.svh", 727, "", 1); end end root.set_report_id_action("UVM/REPORT/CATCHER", action); end end endfunction static function uvm_report_catcher get_report_catcher(string name); static uvm_report_cb_iter iter = new(null); get_report_catcher = iter.first(); while(get_report_catcher != null) begin if(get_report_catcher.get_name() == name) begin return get_report_catcher; end get_report_catcher = iter.next(); end return null; endfunction endclass `define UVM_REPORT_SERVER_SVH typedef class uvm_report_object; typedef class uvm_default_report_server; virtual class uvm_report_server extends uvm_object; function string get_type_name(); return "uvm_report_server"; endfunction function new(string name="base"); super.new(name); endfunction pure virtual function void set_max_quit_count(int count, bit overridable = 1); pure virtual function int get_max_quit_count(); pure virtual function void set_quit_count(int quit_count); pure virtual function int get_quit_count(); pure virtual function void set_severity_count(uvm_severity severity, int count); pure virtual function int get_severity_count(uvm_severity severity); pure virtual function void set_id_count(string id, int count); pure virtual function int get_id_count(string id); pure virtual function void get_id_set(output string q[$]); pure virtual function void get_severity_set(output uvm_severity q[$]); pure virtual function void set_message_database(uvm_tr_database database); pure virtual function uvm_tr_database get_message_database(); function void do_copy (uvm_object rhs); uvm_report_server rhs_; super.do_copy(rhs); if(!$cast(rhs_,rhs)) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM/REPORT/SERVER/RPTCOPY") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM/REPORT/SERVER/RPTCOPY") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM/REPORT/SERVER/RPTCOPY", "cannot copy to report_server from the given datatype", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_report_server.svh", 129, "", 1); end end end begin uvm_severity q[$]; rhs_.get_severity_set(q); foreach(q[s]) begin set_severity_count(q[s],rhs_.get_severity_count(q[s])); end end begin string q[$]; rhs_.get_id_set(q); foreach(q[s]) begin set_id_count(q[s],rhs_.get_id_count(q[s])); end end set_message_database(rhs_.get_message_database()); set_max_quit_count(rhs_.get_max_quit_count()); set_quit_count(rhs_.get_quit_count()); endfunction pure virtual function void process_report_message(uvm_report_message report_message); pure virtual function void execute_report_message(uvm_report_message report_message, string composed_message); pure virtual function string compose_report_message(uvm_report_message report_message, string report_object_name = ""); pure virtual function void report_summarize(UVM_FILE file = UVM_STDOUT); static function void set_server(uvm_report_server server); uvm_coreservice_t cs = uvm_coreservice_t::get(); server.copy(cs.get_report_server()); cs.set_report_server(server); endfunction static function uvm_report_server get_server(); uvm_coreservice_t cs = uvm_coreservice_t::get(); return cs.get_report_server(); endfunction function void dump_server_state(); this.report_summarize(); endfunction : dump_server_state endclass class uvm_default_report_server extends uvm_report_server; local int m_quit_count; local int m_max_quit_count; bit max_quit_overridable = 1; local int m_severity_count[uvm_severity]; protected int m_id_count[string]; protected uvm_tr_database m_message_db; protected uvm_tr_stream m_streams[string][string]; bit enable_report_id_count_summary=1; bit record_all_messages = 0; bit show_verbosity = 0; bit show_terminator = 0; function string get_type_name(); return "uvm_default_report_server"; endfunction function new(string name = "uvm_report_server"); super.new(name); set_max_quit_count(0); reset_quit_count(); reset_severity_counts(); endfunction virtual function void do_print (uvm_printer printer); uvm_severity l_severity_count_index; string l_id_count_index; printer.print_field("quit_count", m_quit_count, $bits(m_quit_count), UVM_DEC, ".", "int"); printer.print_field("max_quit_count", m_max_quit_count, $bits(m_max_quit_count), UVM_DEC, ".", "int"); printer.print_field("max_quit_overridable", max_quit_overridable, $bits(max_quit_overridable), UVM_BIN, ".", "bit"); if (m_severity_count.first(l_severity_count_index)) begin printer.print_array_header("severity_count",m_severity_count.size(),"severity counts"); do begin printer.print_field($sformatf("[%s]",l_severity_count_index.name()), m_severity_count[l_severity_count_index], 32, UVM_DEC); end while (m_severity_count.next(l_severity_count_index)); printer.print_array_footer(); end if (m_id_count.first(l_id_count_index)) begin printer.print_array_header("id_count",m_id_count.size(),"id counts"); do begin printer.print_field($sformatf("[%s]",l_id_count_index), m_id_count[l_id_count_index], 32, UVM_DEC); end while (m_id_count.next(l_id_count_index)); printer.print_array_footer(); end printer.print_field("enable_report_id_count_summary", enable_report_id_count_summary, $bits(enable_report_id_count_summary), UVM_BIN, ".", "bit"); printer.print_field("record_all_messages", record_all_messages, $bits(record_all_messages), UVM_BIN, ".", "bit"); printer.print_field("show_verbosity", show_verbosity, $bits(show_verbosity), UVM_BIN, ".", "bit"); printer.print_field("show_terminator", show_terminator, $bits(show_terminator), UVM_BIN, ".", "bit"); endfunction function int get_max_quit_count(); return m_max_quit_count; endfunction function void set_max_quit_count(int count, bit overridable = 1); if (max_quit_overridable == 0) begin uvm_report_info("NOMAXQUITOVR", $sformatf("The max quit count setting of %0d is not overridable to %0d due to a previous setting.", m_max_quit_count, count), UVM_NONE); return; end max_quit_overridable = overridable; m_max_quit_count = count < 0 ? 0 : count; endfunction function int get_quit_count(); return m_quit_count; endfunction function void set_quit_count(int quit_count); m_quit_count = quit_count < 0 ? 0 : quit_count; endfunction function void incr_quit_count(); m_quit_count++; endfunction function void reset_quit_count(); m_quit_count = 0; endfunction function bit is_quit_count_reached(); return (m_quit_count >= m_max_quit_count); endfunction function int get_severity_count(uvm_severity severity); return m_severity_count[severity]; endfunction function void set_severity_count(uvm_severity severity, int count); m_severity_count[severity] = count < 0 ? 0 : count; endfunction function void incr_severity_count(uvm_severity severity); m_severity_count[severity]++; endfunction function void reset_severity_counts(); uvm_severity s; s = s.first(); forever begin m_severity_count[s] = 0; if(s == s.last()) begin break; end s = s.next(); end endfunction function int get_id_count(string id); if(m_id_count.exists(id)) begin return m_id_count[id]; end return 0; endfunction function void set_id_count(string id, int count); m_id_count[id] = count < 0 ? 0 : count; endfunction function void incr_id_count(string id); if(m_id_count.exists(id)) begin m_id_count[id]++; end else begin m_id_count[id] = 1; end endfunction virtual function void set_message_database(uvm_tr_database database); m_message_db = database; endfunction : set_message_database virtual function uvm_tr_database get_message_database(); return m_message_db; endfunction : get_message_database virtual function void get_severity_set(output uvm_severity q[$]); foreach(m_severity_count[idx]) begin q.push_back(idx); end endfunction virtual function void get_id_set(output string q[$]); foreach(m_id_count[idx]) begin q.push_back(idx); end endfunction function void f_display(UVM_FILE file, string str); if (file == 0) begin $display("%s", str); end else begin $fdisplay(file, "%s", str); end endfunction virtual function void process_report_message(uvm_report_message report_message); uvm_report_handler l_report_handler = report_message.get_report_handler(); process p = process::self(); bit report_ok = 1; report_message.set_report_server(this); if(report_message.get_action() & UVM_CALL_HOOK) begin report_ok = l_report_handler.run_hooks( report_message.get_report_object(), report_message.get_severity(), report_message.get_id(), report_message.get_message(), report_message.get_verbosity(), report_message.get_filename(), report_message.get_line()); end if(report_ok) begin report_ok = uvm_report_catcher::process_all_report_catchers(report_message); end if(uvm_action_type'(report_message.get_action()) == UVM_NO_ACTION) begin report_ok = 0; end if(report_ok) begin string m; uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_report_server svr = cs.get_report_server(); if (report_message.get_action() & (UVM_LOG|UVM_DISPLAY)) begin m = svr.compose_report_message(report_message); end svr.execute_report_message(report_message, m); end endfunction virtual function void execute_report_message(uvm_report_message report_message, string composed_message); process p = process::self(); incr_severity_count(report_message.get_severity()); incr_id_count(report_message.get_id()); if (record_all_messages) begin report_message.set_action(report_message.get_action() | UVM_RM_RECORD); end if(report_message.get_action() & UVM_RM_RECORD) begin uvm_tr_stream stream; uvm_report_object ro = report_message.get_report_object(); uvm_report_handler rh = report_message.get_report_handler(); if (m_streams.exists(ro.get_name()) && (m_streams[ro.get_name()].exists(rh.get_name()))) begin stream = m_streams[ro.get_name()][rh.get_name()]; end if (stream == null) begin uvm_tr_database db; db = get_message_database(); if (db == null) begin uvm_coreservice_t cs = uvm_coreservice_t::get(); db = cs.get_default_tr_database(); end if (db != null) begin stream = db.open_stream(ro.get_name(), rh.get_name(), "MESSAGES"); m_streams[ro.get_name()][rh.get_name()] = stream; end end if (stream != null) begin uvm_recorder recorder = stream.open_recorder(report_message.get_name(),,report_message.get_type_name()); if (recorder != null) begin report_message.record(recorder); recorder.free(); end end end if(report_message.get_action() & UVM_DISPLAY) begin $display("%s", composed_message); end if(report_message.get_action() & UVM_LOG) begin if( (report_message.get_file() == 0) || (report_message.get_file() != 32'h8000_0001) ) begin UVM_FILE tmp_file = report_message.get_file(); if((report_message.get_file() & 32'h8000_0000) == 0) begin tmp_file = report_message.get_file() & 32'hffff_fffe; end f_display(tmp_file, composed_message); end end if(report_message.get_action() & UVM_COUNT) begin if(get_max_quit_count() != 0) begin incr_quit_count(); if(is_quit_count_reached()) begin report_message.set_action(report_message.get_action() | UVM_EXIT); end end end if(report_message.get_action() & UVM_EXIT) begin uvm_root l_root; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); l_root = cs.get_root(); l_root.die(); end if (report_message.get_action() & UVM_STOP) begin $stop; end endfunction virtual function string compose_report_message(uvm_report_message report_message, string report_object_name = ""); string sev_string; uvm_severity l_severity; uvm_verbosity l_verbosity; string filename_line_string; string time_str; string line_str; string context_str; string verbosity_str; string terminator_str; string msg_body_str; uvm_report_message_element_container el_container; string prefix; uvm_report_handler l_report_handler; l_severity = report_message.get_severity(); sev_string = l_severity.name(); if (report_message.get_filename() != "") begin line_str.itoa(report_message.get_line()); filename_line_string = {report_message.get_filename(), "(", line_str, ") "}; end $swrite(time_str, "%0t", $realtime); if (report_message.get_context() != "") begin context_str = {"@@", report_message.get_context()}; end if (show_verbosity) begin if ($cast(l_verbosity, report_message.get_verbosity())) begin verbosity_str = l_verbosity.name(); end else begin verbosity_str.itoa(report_message.get_verbosity()); end verbosity_str = {"(", verbosity_str, ")"}; end if (show_terminator) begin terminator_str = {" -",sev_string}; end el_container = report_message.get_element_container(); if (el_container.size() == 0) begin msg_body_str = report_message.get_message(); end else begin uvm_printer uvm_default_printer = uvm_printer::get_default() ; prefix = uvm_default_printer.get_line_prefix(); uvm_default_printer.set_line_prefix(" +"); msg_body_str = {report_message.get_message(), "\n", el_container.sprint()}; uvm_default_printer.set_line_prefix(prefix); end if (report_object_name == "") begin l_report_handler = report_message.get_report_handler(); report_object_name = l_report_handler.get_full_name(); end compose_report_message = {sev_string, verbosity_str, " ", filename_line_string, "@ ", time_str, ": ", report_object_name, context_str, " [", report_message.get_id(), "] ", msg_body_str, terminator_str}; endfunction protected bit m_report_summarize_in_stack = 0 ; virtual function void report_summarize(UVM_FILE file = UVM_STDOUT); m_report_summarize_in_stack = 1 ; summarize(file); m_report_summarize_in_stack = 0 ; endfunction virtual function void summarize(UVM_FILE file = UVM_STDOUT); if (!m_report_summarize_in_stack) begin report_summarize(file); end else begin m_report_summarize(file); end endfunction virtual function void m_report_summarize(UVM_FILE file = UVM_STDOUT); string id; string name; uvm_root root; uvm_action action; string output_str; string q[$]; uvm_report_catcher::summarize(file); q.push_back("\n--- UVM Report Summary ---\n\n"); if(m_max_quit_count != 0) begin if ( m_quit_count >= m_max_quit_count ) begin q.push_back("Quit count reached!\n"); end q.push_back($sformatf("Quit count : %5d of %5d\n",m_quit_count, m_max_quit_count)); end q.push_back("** Report counts by severity\n"); foreach(m_severity_count[s]) begin q.push_back($sformatf("%s :%5d\n", s.name(), m_severity_count[s])); end if (enable_report_id_count_summary) begin q.push_back("** Report counts by id\n"); foreach(m_id_count[id]) begin q.push_back($sformatf("[%s] %5d\n", id, m_id_count[id])); end end if(file == UVM_STDOUT) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "UVM/REPORT/SERVER") >= UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "UVM/REPORT/SERVER") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("UVM/REPORT/SERVER", uvm_pkg::m_uvm_string_queue_join(q), UVM_NONE, "t/uvm/src/base/uvm_report_server.svh", 1009, "", 1); end end end else begin root = uvm_root::get(); action = root.get_report_action(UVM_INFO, "UVM/REPORT/SERVER"); root.set_report_id_action("UVM/REPORT/SERVER", UVM_LOG); root.set_report_id_file("UVM/REPORT/SERVER", file); begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "UVM/REPORT/SERVER") >= UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "UVM/REPORT/SERVER") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("UVM/REPORT/SERVER", uvm_pkg::m_uvm_string_queue_join(q), UVM_NONE, "t/uvm/src/base/uvm_report_server.svh", 1017, "", 1); end end root.set_report_id_action("UVM/REPORT/SERVER", action); end endfunction endclass `define UVM_REPORT_HANDLER_SVH typedef class uvm_report_object; typedef class uvm_report_server; typedef uvm_pool#(string, uvm_action) uvm_id_actions_array; typedef uvm_pool#(string, UVM_FILE) uvm_id_file_array; typedef uvm_pool#(string, int) uvm_id_verbosities_array; typedef uvm_pool#(uvm_severity, uvm_severity) uvm_sev_override_array; class uvm_report_handler extends uvm_object; int m_max_verbosity_level; uvm_id_verbosities_array id_verbosities; uvm_id_verbosities_array severity_id_verbosities[uvm_severity]; uvm_id_actions_array id_actions; uvm_action severity_actions[uvm_severity]; uvm_id_actions_array severity_id_actions[uvm_severity]; uvm_sev_override_array sev_overrides; uvm_sev_override_array sev_id_overrides [string]; UVM_FILE default_file_handle; uvm_id_file_array id_file_handles; UVM_FILE severity_file_handles[uvm_severity]; uvm_id_file_array severity_id_file_handles[uvm_severity]; typedef uvm_object_registry#(uvm_report_handler,"uvm_report_handler") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_report_handler tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_report_handler"; endfunction : type_name virtual function string get_type_name(); return "uvm_report_handler"; endfunction : get_type_name function new(string name = "uvm_report_handler"); super.new(name); initialize(); endfunction virtual function void do_print (uvm_printer printer); uvm_verbosity l_verbosity; uvm_severity l_severity; string idx; int l_int; if ($cast(l_verbosity, m_max_verbosity_level)) begin printer.print_generic("max_verbosity_level", "uvm_verbosity", 32, l_verbosity.name()); end else begin printer.print_field("max_verbosity_level", m_max_verbosity_level, 32, UVM_DEC, ".", "int"); end if(id_verbosities.first(idx)) begin printer.print_array_header("id_verbosities",id_verbosities.num(), "uvm_pool"); do begin l_int = id_verbosities.get(idx); if ($cast(l_verbosity, l_int)) begin printer.print_generic($sformatf("[%s]", idx), "uvm_verbosity", 32, l_verbosity.name()); end else begin string l_str; l_str.itoa(l_int); printer.print_generic($sformatf("[%s]", idx), "int", 32, l_str); end end while(id_verbosities.next(idx)); printer.print_array_footer(); end if(severity_id_verbosities.size() != 0) begin int _total_cnt; foreach (severity_id_verbosities[l_severity]) begin _total_cnt += severity_id_verbosities[l_severity].num(); end printer.print_array_header("severity_id_verbosities", _total_cnt, "array"); if(severity_id_verbosities.first(l_severity)) begin do begin uvm_id_verbosities_array id_v_ary = severity_id_verbosities[l_severity]; if(id_v_ary.first(idx)) begin do begin l_int = id_v_ary.get(idx); if ($cast(l_verbosity, l_int)) begin printer.print_generic($sformatf("[%s:%s]", l_severity.name(), idx), "uvm_verbosity", 32, l_verbosity.name()); end else begin string l_str; l_str.itoa(l_int); printer.print_generic($sformatf("[%s:%s]", l_severity.name(), idx), "int", 32, l_str); end end while(id_v_ary.next(idx)); end end while(severity_id_verbosities.next(l_severity)); end printer.print_array_footer(); end if(id_actions.first(idx)) begin printer.print_array_header("id_actions",id_actions.num(), "uvm_pool"); do begin l_int = id_actions.get(idx); printer.print_generic($sformatf("[%s]", idx), "uvm_action", 32, format_action(l_int)); end while(id_actions.next(idx)); printer.print_array_footer(); end if(severity_actions.first(l_severity)) begin printer.print_array_header("severity_actions",4,"array"); do begin printer.print_generic($sformatf("[%s]", l_severity.name()), "uvm_action", 32, format_action(severity_actions[l_severity])); end while(severity_actions.next(l_severity)); printer.print_array_footer(); end if(severity_id_actions.size() != 0) begin int _total_cnt; foreach (severity_id_actions[l_severity]) begin _total_cnt += severity_id_actions[l_severity].num(); end printer.print_array_header("severity_id_actions", _total_cnt, "array"); if(severity_id_actions.first(l_severity)) begin do begin uvm_id_actions_array id_a_ary = severity_id_actions[l_severity]; if(id_a_ary.first(idx)) begin do begin printer.print_generic($sformatf("[%s:%s]", l_severity.name(), idx), "uvm_action", 32, format_action(id_a_ary.get(idx))); end while(id_a_ary.next(idx)); end end while(severity_id_actions.next(l_severity)); end printer.print_array_footer(); end if(sev_overrides.first(l_severity)) begin printer.print_array_header("sev_overrides",sev_overrides.num(), "uvm_pool"); do begin uvm_severity l_severity_new = sev_overrides.get(l_severity); printer.print_generic($sformatf("[%s]", l_severity.name()), "uvm_severity", 32, l_severity_new.name()); end while(sev_overrides.next(l_severity)); printer.print_array_footer(); end if(sev_id_overrides.size() != 0) begin int _total_cnt; foreach (sev_id_overrides[idx]) begin _total_cnt += sev_id_overrides[idx].num(); end printer.print_array_header("sev_id_overrides", _total_cnt, "array"); if(sev_id_overrides.first(idx)) begin do begin uvm_sev_override_array sev_o_ary = sev_id_overrides[idx]; if(sev_o_ary.first(l_severity)) begin do begin uvm_severity new_sev = sev_o_ary.get(l_severity); printer.print_generic($sformatf("[%s:%s]", l_severity.name(), idx), "uvm_severity", 32, new_sev.name()); end while(sev_o_ary.next(l_severity)); end end while(sev_id_overrides.next(idx)); end printer.print_array_footer(); end printer.print_field("default_file_handle", default_file_handle, 32, UVM_HEX, ".", "int"); if(id_file_handles.first(idx)) begin printer.print_array_header("id_file_handles",id_file_handles.num(), "uvm_pool"); do begin printer.print_field($sformatf("[%s]", idx), id_file_handles.get(idx), 32, UVM_HEX, ".", "UVM_FILE"); end while(id_file_handles.next(idx)); printer.print_array_footer(); end if(severity_file_handles.first(l_severity)) begin printer.print_array_header("severity_file_handles",4,"array"); do begin printer.print_field($sformatf("[%s]", l_severity.name()), severity_file_handles[l_severity], 32, UVM_HEX, ".", "UVM_FILE"); end while(severity_file_handles.next(l_severity)); printer.print_array_footer(); end if(severity_id_file_handles.size() != 0) begin int _total_cnt; foreach (severity_id_file_handles[l_severity]) begin _total_cnt += severity_id_file_handles[l_severity].num(); end printer.print_array_header("severity_id_file_handles", _total_cnt, "array"); if(severity_id_file_handles.first(l_severity)) begin do begin uvm_id_file_array id_f_ary = severity_id_file_handles[l_severity]; if(id_f_ary.first(idx)) begin do begin printer.print_field($sformatf("[%s:%s]", l_severity.name(), idx), id_f_ary.get(idx), 32, UVM_HEX, ".", "UVM_FILE"); end while(id_f_ary.next(idx)); end end while(severity_id_file_handles.next(l_severity)); end printer.print_array_footer(); end endfunction virtual function void process_report_message(uvm_report_message report_message); uvm_report_server srvr = uvm_report_server::get_server(); string id = report_message.get_id(); uvm_severity severity = report_message.get_severity(); if(sev_id_overrides.exists(id)) begin if(sev_id_overrides[id].exists(uvm_severity'(severity))) begin severity = sev_id_overrides[id].get(severity); report_message.set_severity(severity); end end else begin if(sev_overrides.exists(severity)) begin severity = sev_overrides.get(severity); report_message.set_severity(severity); end end report_message.set_file(get_file_handle(severity, id)); report_message.set_report_handler(this); report_message.set_action(get_action(severity, id)); srvr.process_report_message(report_message); endfunction static function string format_action(uvm_action action); string s; if(uvm_action_type'(action) == UVM_NO_ACTION) begin s = "NO ACTION"; end else begin s = ""; if(action & UVM_DISPLAY) begin s = {s, "DISPLAY "}; end if(action & UVM_LOG) begin s = {s, "LOG "}; end if(action & UVM_RM_RECORD) begin s = {s, "RM_RECORD "}; end if(action & UVM_COUNT) begin s = {s, "COUNT "}; end if(action & UVM_CALL_HOOK) begin s = {s, "CALL_HOOK "}; end if(action & UVM_EXIT) begin s = {s, "EXIT "}; end if(action & UVM_STOP) begin s = {s, "STOP "}; end end return s; endfunction function void initialize(); set_default_file(0); m_max_verbosity_level = UVM_MEDIUM; id_actions=new(); id_verbosities=new(); id_file_handles=new(); sev_overrides=new(); set_severity_action(UVM_INFO, UVM_DISPLAY); set_severity_action(UVM_WARNING, UVM_DISPLAY); set_severity_action(UVM_ERROR, UVM_DISPLAY | UVM_COUNT); set_severity_action(UVM_FATAL, UVM_DISPLAY | UVM_EXIT); set_severity_file(UVM_INFO, default_file_handle); set_severity_file(UVM_WARNING, default_file_handle); set_severity_file(UVM_ERROR, default_file_handle); set_severity_file(UVM_FATAL, default_file_handle); endfunction local function UVM_FILE get_severity_id_file(uvm_severity severity, string id); uvm_id_file_array array; if(severity_id_file_handles.exists(severity)) begin array = severity_id_file_handles[severity]; if(array.exists(id)) begin return array.get(id); end end if(id_file_handles.exists(id)) begin return id_file_handles.get(id); end if(severity_file_handles.exists(severity)) begin return severity_file_handles[severity]; end return default_file_handle; endfunction function void set_verbosity_level(int verbosity_level); m_max_verbosity_level = verbosity_level; endfunction function int get_verbosity_level(uvm_severity severity=UVM_INFO, string id="" ); uvm_id_verbosities_array array; if(severity_id_verbosities.exists(severity)) begin array = severity_id_verbosities[severity]; if(array.exists(id)) begin return array.get(id); end end if(id_verbosities.exists(id)) begin return id_verbosities.get(id); end return m_max_verbosity_level; endfunction function uvm_action get_action(uvm_severity severity, string id); uvm_id_actions_array array; if(severity_id_actions.exists(severity)) begin array = severity_id_actions[severity]; if(array.exists(id)) begin return array.get(id); end end if(id_actions.exists(id)) begin return id_actions.get(id); end return severity_actions[severity]; endfunction function UVM_FILE get_file_handle(uvm_severity severity, string id); UVM_FILE file; file = get_severity_id_file(severity, id); if (file != 0) begin return file; end if (id_file_handles.exists(id)) begin file = id_file_handles.get(id); if (file != 0) begin return file; end end if (severity_file_handles.exists(severity)) begin file = severity_file_handles[severity]; if(file != 0) begin return file; end end return default_file_handle; endfunction function void set_severity_action(input uvm_severity severity, input uvm_action action); severity_actions[severity] = action; endfunction function void set_id_action(input string id, input uvm_action action); id_actions.add(id, action); endfunction function void set_severity_id_action(uvm_severity severity, string id, uvm_action action); if(!severity_id_actions.exists(severity)) begin severity_id_actions[severity] = new; end severity_id_actions[severity].add(id,action); endfunction function void set_id_verbosity(input string id, input int verbosity); id_verbosities.add(id, verbosity); endfunction function void set_severity_id_verbosity(uvm_severity severity, string id, int verbosity); if(!severity_id_verbosities.exists(severity)) begin severity_id_verbosities[severity] = new; end severity_id_verbosities[severity].add(id,verbosity); endfunction function void set_default_file (UVM_FILE file); default_file_handle = file; endfunction function void set_severity_file (uvm_severity severity, UVM_FILE file); severity_file_handles[severity] = file; endfunction function void set_id_file (string id, UVM_FILE file); id_file_handles.add(id, file); endfunction function void set_severity_id_file(uvm_severity severity, string id, UVM_FILE file); if(!severity_id_file_handles.exists(severity)) begin severity_id_file_handles[severity] = new; end severity_id_file_handles[severity].add(id, file); endfunction function void set_severity_override(uvm_severity cur_severity, uvm_severity new_severity); sev_overrides.add(cur_severity, new_severity); endfunction function void set_severity_id_override(uvm_severity cur_severity, string id, uvm_severity new_severity); uvm_sev_override_array arr; if(!sev_id_overrides.exists(id)) begin sev_id_overrides[id] = new; end sev_id_overrides[id].add(cur_severity, new_severity); endfunction virtual function void report( uvm_severity severity, string name, string id, string message, int verbosity_level=UVM_MEDIUM, string filename="", int line=0, uvm_report_object client=null ); bit l_report_enabled = 0; uvm_report_message l_report_message; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); if (!uvm_report_enabled(verbosity_level, UVM_INFO, id)) begin return; end if (client==null) begin client = cs.get_root(); end l_report_message = uvm_report_message::new_report_message(); l_report_message.set_report_message(severity, id, message, verbosity_level, filename, line, name); l_report_message.set_report_object(client); l_report_message.set_action(get_action(severity,id)); process_report_message(l_report_message); endfunction function void dump_state(); string s; UVM_FILE file; uvm_action a; string idx; string q[$]; uvm_id_actions_array id_a_ary; uvm_id_verbosities_array id_v_ary; uvm_id_file_array id_f_ary; q.push_back("\n----------------------------------------------------------------------\n"); q.push_back("report handler state dump \n\n"); q.push_back("\n+-----------------+\n"); q.push_back("| Verbosities |\n"); q.push_back("+-----------------+\n\n"); q.push_back($sformatf("max verbosity level = %d\n", m_max_verbosity_level)); q.push_back("*** verbosities by id\n"); if(id_verbosities.first(idx)) begin do begin uvm_verbosity v = uvm_verbosity'(id_verbosities.get(idx)); q.push_back($sformatf("[%s] --> %s\n", idx, v.name())); end while(id_verbosities.next(idx)); end q.push_back("*** verbosities by id and severity\n"); foreach( severity_id_verbosities[severity] ) begin uvm_severity sev = uvm_severity'(severity); id_v_ary = severity_id_verbosities[severity]; if(id_v_ary.first(idx)) begin do begin uvm_verbosity v = uvm_verbosity'(id_v_ary.get(idx)); q.push_back($sformatf("%s:%s --> %s\n",sev.name(), idx, v.name())); end while(id_v_ary.next(idx)); end end q.push_back("\n+-------------+\n"); q.push_back("| actions |\n"); q.push_back("+-------------+\n\n"); q.push_back("*** actions by severity\n"); foreach( severity_actions[severity] ) begin uvm_severity sev = uvm_severity'(severity); q.push_back($sformatf("%s = %s\n",sev.name(), format_action(severity_actions[severity]))); end q.push_back("\n*** actions by id\n"); if(id_actions.first(idx)) begin do begin q.push_back($sformatf("[%s] --> %s\n", idx, format_action(id_actions.get(idx)))); end while(id_actions.next(idx)); end q.push_back("\n*** actions by id and severity\n"); foreach( severity_id_actions[severity] ) begin uvm_severity sev = uvm_severity'(severity); id_a_ary = severity_id_actions[severity]; if(id_a_ary.first(idx)) begin do begin q.push_back($sformatf("%s:%s --> %s\n",sev.name(), idx, format_action(id_a_ary.get(idx)))); end while(id_a_ary.next(idx)); end end q.push_back("\n+-------------+\n"); q.push_back("| files |\n"); q.push_back("+-------------+\n\n"); q.push_back($sformatf("default file handle = %d\n\n", default_file_handle)); q.push_back("*** files by severity\n"); foreach( severity_file_handles[severity] ) begin uvm_severity sev = uvm_severity'(severity); file = severity_file_handles[severity]; q.push_back($sformatf("%s = %d\n", sev.name(), file)); end q.push_back("\n*** files by id\n"); if(id_file_handles.first(idx)) begin do begin file = id_file_handles.get(idx); q.push_back($sformatf("id %s --> %d\n", idx, file)); end while (id_file_handles.next(idx)); end q.push_back("\n*** files by id and severity\n"); foreach( severity_id_file_handles[severity] ) begin uvm_severity sev = uvm_severity'(severity); id_f_ary = severity_id_file_handles[severity]; if(id_f_ary.first(idx)) begin do begin q.push_back($sformatf("%s:%s --> %d\n", sev.name(), idx, id_f_ary.get(idx))); end while(id_f_ary.next(idx)); end end q.push_back("----------------------------------------------------------------------\n"); begin uvm_report_server srvr; srvr=uvm_report_server::get_server(); srvr.report_summarize(); end begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "UVM/REPORT/HANDLER") >= UVM_LOW) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "UVM/REPORT/HANDLER") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("UVM/REPORT/HANDLER", uvm_pkg::m_uvm_string_queue_join(q), UVM_LOW, "t/uvm/src/base/uvm_report_handler.svh", 899, "", 1); end end endfunction virtual function bit run_hooks(uvm_report_object client, uvm_severity severity, string id, string message, int verbosity, string filename, int line); bit ok; ok = client.report_hook(id, message, verbosity, filename, line); case(severity) UVM_INFO: begin ok &= client.report_info_hook (id, message, verbosity, filename, line); end UVM_WARNING: begin ok &= client.report_warning_hook(id, message, verbosity, filename, line); end UVM_ERROR: begin ok &= client.report_error_hook (id, message, verbosity, filename, line); end UVM_FATAL: begin ok &= client.report_fatal_hook (id, message, verbosity, filename, line); end endcase return ok; endfunction endclass : uvm_report_handler `define UVM_REPORT_CLIENT_SVH typedef class uvm_component; typedef class uvm_env; typedef class uvm_root; class uvm_report_object extends uvm_object; uvm_report_handler m_rh; local bit m_rh_set; local function void m_rh_init(); if (!m_rh_set) begin set_report_handler(uvm_report_handler::type_id::create(get_name())); end endfunction : m_rh_init function new(string name = ""); super.new(name); endfunction function uvm_report_object uvm_get_report_object(); return this; endfunction function int uvm_report_enabled(int verbosity, uvm_severity severity = UVM_INFO, string id = ""); if (get_report_verbosity_level(severity, id) < verbosity) begin return 0; end return 1; endfunction virtual function void uvm_report( uvm_severity severity, string id, string message, int verbosity = (severity == uvm_severity'(UVM_ERROR)) ? UVM_NONE : (severity == uvm_severity'(UVM_FATAL)) ? UVM_NONE : (severity == uvm_severity'(UVM_WARNING)) ? UVM_NONE : UVM_MEDIUM, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked =0); uvm_report_message l_report_message; if ((severity == UVM_INFO) && (report_enabled_checked == 0)) begin if (!uvm_report_enabled(verbosity, severity, id)) begin return; end end l_report_message = uvm_report_message::new_report_message(); l_report_message.set_report_message(severity, id, message, verbosity, filename, line, context_name); uvm_process_report_message(l_report_message); endfunction virtual function void uvm_report_info( string id, string message, int verbosity = UVM_MEDIUM, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_report (UVM_INFO, id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction virtual function void uvm_report_warning( string id, string message, int verbosity = UVM_NONE, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_report (UVM_WARNING, id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction virtual function void uvm_report_error( string id, string message, int verbosity = UVM_NONE, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_report (UVM_ERROR, id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction virtual function void uvm_report_fatal( string id, string message, int verbosity = UVM_NONE, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_report (UVM_FATAL, id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction virtual function void uvm_process_report_message(uvm_report_message report_message); m_rh_init(); report_message.set_report_object(this); m_rh.process_report_message(report_message); endfunction function int get_report_verbosity_level(uvm_severity severity=UVM_INFO, string id=""); m_rh_init(); return m_rh.get_verbosity_level(severity, id); endfunction function int get_report_max_verbosity_level(); m_rh_init(); return m_rh.m_max_verbosity_level; endfunction function void set_report_verbosity_level (int verbosity_level); m_rh_init(); m_rh.set_verbosity_level(verbosity_level); endfunction function void set_report_id_verbosity (string id, int verbosity); m_rh_init(); m_rh.set_id_verbosity(id, verbosity); endfunction function void set_report_severity_id_verbosity (uvm_severity severity, string id, int verbosity); m_rh_init(); m_rh.set_severity_id_verbosity(severity, id, verbosity); endfunction function int get_report_action(uvm_severity severity, string id); m_rh_init(); return m_rh.get_action(severity,id); endfunction function void set_report_severity_action (uvm_severity severity, uvm_action action); m_rh_init(); m_rh.set_severity_action(severity, action); endfunction function void set_report_id_action (string id, uvm_action action); m_rh_init(); m_rh.set_id_action(id, action); endfunction function void set_report_severity_id_action (uvm_severity severity, string id, uvm_action action); m_rh_init(); m_rh.set_severity_id_action(severity, id, action); endfunction function int get_report_file_handle(uvm_severity severity, string id); m_rh_init(); return m_rh.get_file_handle(severity,id); endfunction function void set_report_default_file (UVM_FILE file); m_rh_init(); m_rh.set_default_file(file); endfunction function void set_report_id_file (string id, UVM_FILE file); m_rh_init(); m_rh.set_id_file(id, file); endfunction function void set_report_severity_file (uvm_severity severity, UVM_FILE file); m_rh_init(); m_rh.set_severity_file(severity, file); endfunction function void set_report_severity_id_file (uvm_severity severity, string id, UVM_FILE file); m_rh_init(); m_rh.set_severity_id_file(severity, id, file); endfunction function void set_report_severity_override(uvm_severity cur_severity, uvm_severity new_severity); m_rh_init(); m_rh.set_severity_override(cur_severity, new_severity); endfunction function void set_report_severity_id_override(uvm_severity cur_severity, string id, uvm_severity new_severity); m_rh_init(); m_rh.set_severity_id_override(cur_severity, id, new_severity); endfunction function void set_report_handler(uvm_report_handler handler); m_rh = handler; m_rh_set = 1; endfunction function uvm_report_handler get_report_handler(); m_rh_init(); return m_rh; endfunction function void reset_report_handler; m_rh_init(); m_rh.initialize(); endfunction virtual function void report_header(UVM_FILE file = 0); uvm_root top = uvm_root::get(); if (this == top) begin return; end top.report_header(file); endfunction : report_header virtual function void die(); uvm_root top = uvm_root::get(); if (this == top) begin return; end top.die(); endfunction : die virtual function void report_summarize(UVM_FILE file = 0); uvm_report_server svr = uvm_report_server::get_server(); svr.report_summarize(file); endfunction : report_summarize function void set_report_max_quit_count(int max_count); uvm_report_server svr = uvm_report_server::get_server(); svr.set_max_quit_count(max_count); endfunction : set_report_max_quit_count function void dump_report_state(); m_rh.dump_state(); endfunction virtual function bit report_info_hook( string id, string message, int verbosity, string filename, int line); return 1; endfunction virtual function bit report_error_hook( string id, string message, int verbosity, string filename, int line); return 1; endfunction virtual function bit report_warning_hook( string id, string message, int verbosity, string filename, int line); return 1; endfunction virtual function bit report_fatal_hook( string id, string message, int verbosity, string filename, int line); return 1; endfunction virtual function bit report_hook( string id, string message, int verbosity, string filename, int line); return 1; endfunction function uvm_report_server get_report_server(); return uvm_report_server::get_server(); endfunction endclass typedef class uvm_event; typedef class uvm_event_pool; typedef class uvm_component; typedef class uvm_parent_child_link; virtual class uvm_transaction extends uvm_object; extern function new (string name="", uvm_component initiator=null); extern function void accept_tr (time accept_time = 0); extern virtual protected function void do_accept_tr (); extern function uvm_tr_handle_t begin_tr ( time begin_time = 0 , uvm_tr_handle_t parent_handle = 0 ); extern function uvm_tr_handle_t begin_child_tr (time begin_time = 0, uvm_tr_handle_t parent_handle = 0); extern virtual protected function void do_begin_tr (); extern function void end_tr (time end_time=0, bit free_handle=1); extern virtual protected function void do_end_tr (); extern function uvm_tr_handle_t get_tr_handle (); extern function void disable_recording (); extern function void enable_recording (uvm_tr_stream stream); extern function bit is_recording_enabled(); extern function bit is_active (); extern function uvm_event_pool get_event_pool (); extern function void set_initiator (uvm_component initiator); extern function uvm_component get_initiator (); extern function time get_accept_time (); extern function time get_begin_time (); extern function time get_end_time (); extern function void set_transaction_id(uvm_transaction_id_t id); extern function uvm_transaction_id_t get_transaction_id(); const local uvm_event_pool events = new("events"); extern virtual function void do_print (uvm_printer printer); extern virtual function void do_record (uvm_recorder recorder); extern virtual function void do_copy (uvm_object rhs); extern protected function uvm_tr_handle_t m_begin_tr (time begin_time=0, uvm_tr_handle_t parent_handle=0); local uvm_transaction_id_t m_transaction_id = -1; local time begin_time=-1; local time end_time=-1; local time accept_time=-1; local uvm_component initiator; local uvm_tr_stream stream_handle; local uvm_recorder tr_recorder; uvm_event#(uvm_object) begin_event; uvm_event#(uvm_object) end_event; endclass function uvm_transaction::new (string name="", uvm_component initiator = null); super.new(name); this.initiator = initiator; m_transaction_id = -1; endfunction function void uvm_transaction::set_transaction_id(uvm_transaction_id_t id); m_transaction_id = id; endfunction function uvm_transaction_id_t uvm_transaction::get_transaction_id(); return (m_transaction_id); endfunction function void uvm_transaction::set_initiator(uvm_component initiator); this.initiator = initiator; endfunction function uvm_component uvm_transaction::get_initiator(); return initiator; endfunction function uvm_event_pool uvm_transaction::get_event_pool(); return events; endfunction function bit uvm_transaction::is_active(); return (end_time == -1); endfunction function time uvm_transaction::get_begin_time (); return begin_time; endfunction function time uvm_transaction::get_end_time (); return end_time; endfunction function time uvm_transaction::get_accept_time (); return accept_time; endfunction function void uvm_transaction::do_accept_tr(); return; endfunction function void uvm_transaction::do_begin_tr(); return; endfunction function void uvm_transaction::do_end_tr(); return; endfunction function void uvm_transaction::do_print (uvm_printer printer); string str; uvm_component tmp_initiator; super.do_print(printer); if(accept_time != -1) begin printer.print_time("accept_time", accept_time); end if(begin_time != -1) begin printer.print_time("begin_time", begin_time); end if(end_time != -1) begin printer.print_time("end_time", end_time); end if(initiator != null) begin tmp_initiator = initiator; $swrite(str,"@%0d", tmp_initiator.get_inst_id()); printer.print_generic("initiator", initiator.get_type_name(), -1, str); end endfunction function void uvm_transaction::do_copy (uvm_object rhs); uvm_transaction txn; super.do_copy(rhs); if(rhs == null) begin return; end if(!$cast(txn, rhs) ) begin return; end accept_time = txn.accept_time; begin_time = txn.begin_time; end_time = txn.end_time; initiator = txn.initiator; stream_handle = txn.stream_handle; tr_recorder = txn.tr_recorder; endfunction function void uvm_transaction::do_record (uvm_recorder recorder); string s; super.do_record(recorder); if(accept_time != -1) begin recorder.record_field("accept_time", accept_time, $bits(accept_time), UVM_TIME); end if(initiator != null) begin uvm_recursion_policy_enum p = recorder.get_recursion_policy(); recorder.set_recursion_policy(UVM_REFERENCE); recorder.record_object("initiator", initiator); recorder.set_recursion_policy(p); end endfunction function uvm_tr_handle_t uvm_transaction::get_tr_handle (); if (tr_recorder != null) begin return tr_recorder.get_handle(); end else begin return 0; end endfunction function void uvm_transaction::disable_recording (); this.stream_handle = null; endfunction function void uvm_transaction::enable_recording (uvm_tr_stream stream); this.stream_handle = stream; endfunction : enable_recording function bit uvm_transaction::is_recording_enabled (); return (this.stream_handle != null); endfunction function void uvm_transaction::accept_tr (time accept_time = 0); uvm_event#(uvm_object) e; if(accept_time != 0) begin this.accept_time = accept_time; end else begin this.accept_time = $realtime; end do_accept_tr(); e = events.get("accept"); if(e!=null) begin e.trigger(); end endfunction function uvm_tr_handle_t uvm_transaction::begin_tr ( time begin_time = 0 , uvm_tr_handle_t parent_handle = 0 ); return m_begin_tr( begin_time , parent_handle ); endfunction function uvm_tr_handle_t uvm_transaction::begin_child_tr (time begin_time=0, uvm_tr_handle_t parent_handle=0); return m_begin_tr(begin_time, parent_handle); endfunction function uvm_tr_handle_t uvm_transaction::m_begin_tr (time begin_time=0, uvm_tr_handle_t parent_handle=0); time tmp_time = (begin_time == 0) ? $realtime : begin_time; uvm_recorder parent_recorder; if (parent_handle != 0) begin parent_recorder = uvm_recorder::get_recorder_from_handle(parent_handle); end if (tr_recorder != null) begin end_tr(tmp_time); end if(is_recording_enabled()) begin uvm_tr_database db = stream_handle.get_db(); this.end_time = -1; this.begin_time = tmp_time; if(parent_recorder == null) begin tr_recorder = stream_handle.open_recorder(get_type_name(), this.begin_time, "Begin_No_Parent, Link"); end else begin tr_recorder = stream_handle.open_recorder(get_type_name(), this.begin_time, "Begin_End, Link"); if (tr_recorder != null) begin db.establish_link(uvm_parent_child_link::get_link(parent_recorder, tr_recorder)); end end if (tr_recorder != null) begin m_begin_tr = tr_recorder.get_handle(); end else begin m_begin_tr = 0; end end else begin tr_recorder = null; this.end_time = -1; this.begin_time = tmp_time; m_begin_tr = 0; end do_begin_tr(); begin begin_event = events.get("begin"); begin_event.trigger(); end endfunction function void uvm_transaction::end_tr (time end_time=0, bit free_handle=1); this.end_time = (end_time == 0) ? $realtime : end_time; do_end_tr(); if(is_recording_enabled() && (tr_recorder != null)) begin record(tr_recorder); tr_recorder.close(this.end_time); if(free_handle) begin tr_recorder.free(); end end tr_recorder = null; begin end_event = events.get("end") ; end_event.trigger(); end endfunction typedef class uvm_sequencer_base; typedef class uvm_domain; typedef class uvm_task_phase; typedef class uvm_phase_cb; typedef class uvm_phase_state_change; class uvm_phase extends uvm_object; static local bit m_register_cb_uvm_phase_cb = uvm_callbacks#(uvm_phase,uvm_phase_cb)::m_register_pair("uvm_phase","uvm_phase_cb"); extern function new(string name="uvm_phase", uvm_phase_type phase_type=UVM_PHASE_SCHEDULE, uvm_phase parent=null); extern function uvm_phase_type get_phase_type(); extern virtual function void set_max_ready_to_end_iterations(int max); extern virtual function int get_max_ready_to_end_iterations(); extern static function void set_default_max_ready_to_end_iterations(int max); extern static function int get_default_max_ready_to_end_iterations(); extern function void set_state(uvm_phase_state state); extern function uvm_phase_state get_state(); extern function int get_run_count(); extern function uvm_phase find_by_name(string name, bit stay_in_scope=1); extern function uvm_phase find(uvm_phase phase, bit stay_in_scope=1); extern function bit is(uvm_phase phase); extern function bit is_before(uvm_phase phase); extern function bit is_after(uvm_phase phase); virtual function void exec_func(uvm_component comp, uvm_phase phase); endfunction virtual task exec_task(uvm_component comp, uvm_phase phase); endtask extern function void add(uvm_phase phase, uvm_phase with_phase=null, uvm_phase after_phase=null, uvm_phase before_phase=null, uvm_phase start_with_phase=null, uvm_phase end_with_phase=null ); extern function uvm_phase get_parent(); extern virtual function string get_full_name(); extern function uvm_phase get_schedule(bit hier = 0); extern function string get_schedule_name(bit hier = 0); extern function uvm_domain get_domain(); extern function uvm_phase get_imp(); extern function string get_domain_name(); extern function void get_adjacent_predecessor_nodes(ref uvm_phase pred[]); extern function void get_adjacent_successor_nodes(ref uvm_phase succ[]); extern function void m_report_null_objection(uvm_object obj, string description, int count, string action); extern virtual function void raise_objection (uvm_object obj, string description="", int count=1); extern virtual function void drop_objection (uvm_object obj, string description="", int count=1); extern virtual function int get_objection_count( uvm_object obj=null ); extern virtual function int get_objection_total( uvm_object obj=null ); extern function void sync(uvm_domain target, uvm_phase phase=null, uvm_phase with_phase=null); extern function void unsync(uvm_domain target, uvm_phase phase=null, uvm_phase with_phase=null); extern task wait_for_state(uvm_phase_state state, uvm_wait_op op=UVM_EQ); extern function void jump(uvm_phase phase); extern function void set_jump_phase(uvm_phase phase) ; extern function bit is_jumping_forward(); extern function bit is_jumping_backward(); extern function void end_prematurely() ; extern function bit is_ending_prematurely(); extern static function void jump_all(uvm_phase phase); extern function uvm_phase get_jump_target(); typedef bit edges_t[uvm_phase]; protected uvm_phase_type m_phase_type; protected uvm_phase m_parent; uvm_phase m_imp; local uvm_phase_state m_state; local int m_run_count; protected uvm_phase_state_change m_state_chg; process m_phase_proc; local static int m_default_max_ready_to_end_iters = 20; local int max_ready_to_end_iters = get_default_max_ready_to_end_iterations(); int m_num_procs_not_yet_returned; extern function uvm_phase m_find_predecessor(uvm_phase phase, bit stay_in_scope=1, uvm_phase orig_phase=null); extern function uvm_phase m_find_successor(uvm_phase phase, bit stay_in_scope=1, uvm_phase orig_phase=null); extern function uvm_phase m_find_predecessor_by_name(string name, bit stay_in_scope=1, uvm_phase orig_phase=null); extern function uvm_phase m_find_successor_by_name(string name, bit stay_in_scope=1, uvm_phase orig_phase=null); extern function void m_print_successors(); virtual function void traverse(uvm_component comp, uvm_phase phase, uvm_phase_state state); endfunction virtual function void execute(uvm_component comp, uvm_phase phase); endfunction protected edges_t m_predecessors; protected edges_t m_successors; protected uvm_phase m_end_node; static protected edges_t m_executing_phases; function uvm_phase get_begin_node(); if (m_imp != null) begin return this; end return null; endfunction function uvm_phase get_end_node(); return m_end_node; endfunction local uvm_phase m_sync[$]; uvm_objection phase_done; extern function void get_predecessors(ref edges_t predecessors); extern function void get_successors(ref edges_t successors); extern function void get_sync_relationships(ref edges_t relationships); extern local function void get_predecessors_for_successors(output edges_t pred_of_succ); extern task m_wait_for_pred(); local bit m_jump_bkwd; local bit m_jump_fwd; local uvm_phase m_jump_phase; bit m_premature_end; extern function void clear(uvm_phase_state state = UVM_PHASE_DORMANT); extern function void clear_successors( uvm_phase_state state = UVM_PHASE_DORMANT, uvm_phase end_state=null); local static mailbox #(uvm_phase) m_phase_hopper = new(); extern local function void m_terminate_phase(); extern local function void m_print_termination_state(); extern task wait_for_self_and_siblings_to_drop(); extern function void kill(); extern function void kill_successors(); static bit m_phase_trace; static bit m_use_ovm_run_semantic; function string convert2string(); string s; s = $sformatf("phase: %s parent=%s pred=%s succ=%s",get_name(), (m_parent==null) ? "null" : get_schedule_name(), m_aa2string(m_predecessors), m_aa2string(m_successors)); return s; endfunction local function string m_aa2string(edges_t aa); string s; int i; s = "'{ "; foreach (aa[ph]) begin uvm_phase n = ph; s = {s, (n == null) ? "null" : n.get_name(), (i == aa.num()-1) ? "" : ", "}; i++; end s = {s, " }"}; return s; endfunction function bit is_domain(); return (m_phase_type == UVM_PHASE_DOMAIN); endfunction virtual function void m_get_transitive_children(ref uvm_phase phases[$]); foreach (m_successors[succ]) begin phases.push_back(succ); succ.m_get_transitive_children(phases); end endfunction function uvm_objection get_objection(); uvm_phase imp; uvm_task_phase tp; imp = get_imp(); if ((get_phase_type() != UVM_PHASE_NODE) || (imp == null) || !$cast(tp, imp)) begin return null; end if (phase_done == null) begin phase_done = uvm_objection::type_id::create({get_name(), "_objection"}); end return phase_done; endfunction endclass class uvm_phase_state_change extends uvm_object; typedef uvm_object_registry#(uvm_phase_state_change,"uvm_phase_state_change") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_phase_state_change tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_phase_state_change"; endfunction : type_name virtual function string get_type_name(); return "uvm_phase_state_change"; endfunction : get_type_name uvm_phase m_phase; uvm_phase_state m_prev_state; uvm_phase m_jump_to; function new(string name = "uvm_phase_state_change"); super.new(name); endfunction virtual function uvm_phase_state get_state(); return m_phase.get_state(); endfunction virtual function uvm_phase_state get_prev_state(); return m_prev_state; endfunction function uvm_phase jump_to(); return m_jump_to; endfunction endclass class uvm_phase_cb extends uvm_callback; function new(string name="unnamed-uvm_phase_cb"); super.new(name); endfunction : new virtual function void phase_state_change(uvm_phase phase, uvm_phase_state_change change); endfunction endclass typedef uvm_callbacks#(uvm_phase, uvm_phase_cb) uvm_phase_cb_pool ; typedef class uvm_cmdline_processor; `define UVM_PH_TRACE(ID,MSG,PH,VERB) \ if (uvm_phase::m_phase_trace) \ `uvm_info(ID, {$sformatf("Phase '%0s' (id=%0d) ", \ PH.get_full_name(), PH.get_inst_id()),MSG}, VERB) function uvm_phase::new(string name="uvm_phase", uvm_phase_type phase_type=UVM_PHASE_SCHEDULE, uvm_phase parent=null); super.new(name); m_state_chg = uvm_phase_state_change::type_id::create(name); m_state_chg.m_phase = this; m_phase_type = phase_type; if ((name == "common") && (phase_type == UVM_PHASE_DOMAIN)) begin m_state = UVM_PHASE_DORMANT; end m_run_count = 0; m_parent = parent; begin uvm_cmdline_processor clp = uvm_cmdline_processor::get_inst(); string val; if (clp.get_arg_value("+UVM_PHASE_TRACE", val)) begin m_phase_trace = 1; end else begin m_phase_trace = 0; end if (clp.get_arg_value("+UVM_USE_OVM_RUN_SEMANTIC", val)) begin m_use_ovm_run_semantic = 1; end else begin m_use_ovm_run_semantic = 0; end end if (parent == null && (phase_type == UVM_PHASE_SCHEDULE || phase_type == UVM_PHASE_DOMAIN )) begin m_end_node = new({name,"_end"}, UVM_PHASE_TERMINAL, this); this.m_successors[m_end_node] = 1; m_end_node.m_predecessors[this] = 1; end endfunction function void uvm_phase::add(uvm_phase phase, uvm_phase with_phase=null, uvm_phase after_phase=null, uvm_phase before_phase=null, uvm_phase start_with_phase=null, uvm_phase end_with_phase=null ); uvm_phase new_node, begin_node, end_node, tmp_node; uvm_phase_state_change state_chg; if (phase == null) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "PH/NULL") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "PH/NULL") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("PH/NULL", "add: phase argument is null", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 775, "", 1); end end end if (with_phase != null && with_phase.get_phase_type() == UVM_PHASE_IMP) begin string nm = with_phase.get_name(); with_phase = find(with_phase); if (with_phase == null) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "PH_BAD_ADD") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "PH_BAD_ADD") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("PH_BAD_ADD", {"cannot find with_phase '",nm,"' within node '",get_name(),"'"}, uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 783, "", 1); end end end end if (before_phase != null && before_phase.get_phase_type() == UVM_PHASE_IMP) begin string nm = before_phase.get_name(); before_phase = find(before_phase); if (before_phase == null) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "PH_BAD_ADD") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "PH_BAD_ADD") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("PH_BAD_ADD", {"cannot find before_phase '",nm,"' within node '",get_name(),"'"}, uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 792, "", 1); end end end end if (after_phase != null && after_phase.get_phase_type() == UVM_PHASE_IMP) begin string nm = after_phase.get_name(); after_phase = find(after_phase); if (after_phase == null) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "PH_BAD_ADD") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "PH_BAD_ADD") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("PH_BAD_ADD", {"cannot find after_phase '",nm,"' within node '",get_name(),"'"}, uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 801, "", 1); end end end end if (start_with_phase != null && start_with_phase.get_phase_type() == UVM_PHASE_IMP) begin string nm = start_with_phase.get_name(); start_with_phase = find(start_with_phase); if (start_with_phase == null) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "PH_BAD_ADD") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "PH_BAD_ADD") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("PH_BAD_ADD", {"cannot find start_with_phase '",nm,"' within node '",get_name(),"'"}, uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 810, "", 1); end end end end if (end_with_phase != null && end_with_phase.get_phase_type() == UVM_PHASE_IMP) begin string nm = end_with_phase.get_name(); end_with_phase = find(end_with_phase); if (end_with_phase == null) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "PH_BAD_ADD") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "PH_BAD_ADD") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("PH_BAD_ADD", {"cannot find end_with_phase '",nm,"' within node '",get_name(),"'"}, uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 819, "", 1); end end end end if (((with_phase != null) + (after_phase != null) + (start_with_phase != null)) > 1) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "PH_BAD_ADD") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "PH_BAD_ADD") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("PH_BAD_ADD", "only one of with_phase/after_phase/start_with_phase may be specified as they all specify predecessor", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 825, "", 1); end end end if (((with_phase != null) + (before_phase != null) + (end_with_phase != null)) > 1) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "PH_BAD_ADD") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "PH_BAD_ADD") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("PH_BAD_ADD", "only one of with_phase/before_phase/end_with_phase may be specified as they all specify successor", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 830, "", 1); end end end if (before_phase == this || after_phase == m_end_node || with_phase == m_end_node || start_with_phase == m_end_node || end_with_phase == m_end_node) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "PH_BAD_ADD") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "PH_BAD_ADD") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("PH_BAD_ADD", "cannot add before begin node, after end node, or with end nodes", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 839, "", 1); end end end if (before_phase != null && after_phase != null) begin if (!after_phase.is_before(before_phase)) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "PH_BAD_ADD") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "PH_BAD_ADD") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("PH_BAD_ADD", {"Phase '",before_phase.get_name(), "' is not before phase '",after_phase.get_name(),"'"}, uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 845, "", 1); end end end end if (before_phase != null && start_with_phase != null) begin if (!start_with_phase.is_before(before_phase)) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "PH_BAD_ADD") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "PH_BAD_ADD") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("PH_BAD_ADD", {"Phase '",before_phase.get_name(), "' is not before phase '",start_with_phase.get_name(),"'"}, uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 852, "", 1); end end end end if (end_with_phase != null && after_phase != null) begin if (!after_phase.is_before(end_with_phase)) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "PH_BAD_ADD") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "PH_BAD_ADD") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("PH_BAD_ADD", {"Phase '",end_with_phase.get_name(), "' is not before phase '",after_phase.get_name(),"'"}, uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 859, "", 1); end end end end if (phase.get_phase_type() == UVM_PHASE_IMP) begin uvm_task_phase tp; new_node = new(phase.get_name(),UVM_PHASE_NODE,this); new_node.m_imp = phase; begin_node = new_node; end_node = new_node; end else begin begin_node = phase; end_node = phase.m_end_node; phase.m_parent = this; end if (with_phase==null && after_phase==null && before_phase==null && start_with_phase==null && end_with_phase==null) begin before_phase = m_end_node; end if (m_phase_trace) begin uvm_phase_type typ = phase.get_phase_type(); begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH/TRC/ADD_PH") >= UVM_DEBUG) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH/TRC/ADD_PH") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH/TRC/ADD_PH", {get_name()," (",m_phase_type.name(),") ADD_PHASE: phase=",phase.get_full_name()," (", typ.name(),", inst_id=",$sformatf("%0d",phase.get_inst_id()),")", " with_phase=", (with_phase == null) ? "null" : with_phase.get_name(), " start_with_phase=", (start_with_phase == null) ? "null" : start_with_phase.get_name(), " end_with_phase=", (end_with_phase == null) ? "null" : end_with_phase.get_name(), " after_phase=", (after_phase == null) ? "null" : after_phase.get_name(), " before_phase=", (before_phase == null) ? "null" : before_phase.get_name(), " new_node=", (new_node == null) ? "null" : {new_node.get_name(), " inst_id=", $sformatf("%0d",new_node.get_inst_id())}, " begin_node=", (begin_node == null) ? "null" : begin_node.get_name(), " end_node=", (end_node == null) ? "null" : end_node.get_name()}, UVM_DEBUG, "t/uvm/src/base/uvm_phase.svh", 908, "", 1); end end end if (with_phase != null) begin begin_node.m_predecessors = with_phase.m_predecessors; foreach (with_phase.m_predecessors[pred]) begin pred.m_successors[begin_node] = 1; end end_node.m_successors = with_phase.m_successors; foreach (with_phase.m_successors[succ]) begin succ.m_predecessors[end_node] = 1; end end if (start_with_phase != null) begin begin_node.m_predecessors = start_with_phase.m_predecessors; foreach (start_with_phase.m_predecessors[pred]) begin pred.m_successors[begin_node] = 1; end if (before_phase == null && end_with_phase == null) begin end_node.m_successors = m_end_node.m_successors ; foreach (m_end_node.m_successors[succ]) begin succ.m_predecessors[end_node] = 1; end end end if (end_with_phase != null) begin end_node.m_successors = end_with_phase.m_successors; foreach (end_with_phase.m_successors[succ]) begin succ.m_predecessors[end_node] = 1; end if (after_phase == null && start_with_phase == null) begin begin_node.m_predecessors = this.m_predecessors ; foreach (this.m_predecessors[pred]) begin pred.m_successors[begin_node] = 1; end end end if (before_phase != null) begin if (after_phase == null && start_with_phase == null) begin foreach (before_phase.m_predecessors[pred]) begin pred.m_successors.delete(before_phase); pred.m_successors[begin_node] = 1; end begin_node.m_predecessors = before_phase.m_predecessors; before_phase.m_predecessors.delete(); end else if (before_phase.m_predecessors.exists(after_phase)) begin before_phase.m_predecessors.delete(after_phase); end before_phase.m_predecessors[end_node] = 1; end_node.m_successors.delete() ; end_node.m_successors[before_phase] = 1; end if (after_phase != null) begin if (before_phase == null && end_with_phase == null) begin foreach (after_phase.m_successors[succ]) begin succ.m_predecessors.delete(after_phase); succ.m_predecessors[end_node] = 1; end end_node.m_successors = after_phase.m_successors; after_phase.m_successors.delete(); end else if (after_phase.m_successors.exists(before_phase)) begin after_phase.m_successors.delete(before_phase); end after_phase.m_successors[begin_node] = 1; begin_node.m_predecessors.delete(); begin_node.m_predecessors[after_phase] = 1; end if (new_node == null) begin tmp_node = phase; end else begin tmp_node = new_node; end state_chg = uvm_phase_state_change::type_id::create(tmp_node.get_name()); state_chg.m_phase = tmp_node; state_chg.m_jump_to = null; state_chg.m_prev_state = tmp_node.m_state; tmp_node.m_state = UVM_PHASE_DORMANT; begin uvm_callback_iter#(uvm_phase,uvm_phase_cb) iter = new(this); uvm_phase_cb cb = iter.first(); while(cb != null) begin cb.phase_state_change(tmp_node, state_chg); cb = iter.next(); end end endfunction function uvm_phase uvm_phase::get_parent(); return m_parent; endfunction function uvm_phase uvm_phase::get_imp(); return m_imp; endfunction function uvm_phase uvm_phase::get_schedule(bit hier=0); uvm_phase sched; sched = this; if (hier) begin while (sched.m_parent != null && (sched.m_parent.get_phase_type() == UVM_PHASE_SCHEDULE)) begin sched = sched.m_parent; end end if (sched.m_phase_type == UVM_PHASE_SCHEDULE) begin return sched; end if (sched.m_phase_type == UVM_PHASE_NODE) begin if (m_parent != null && m_parent.m_phase_type != UVM_PHASE_DOMAIN) begin return m_parent; end end return null; endfunction function uvm_domain uvm_phase::get_domain(); uvm_phase phase; phase = this; while (phase != null && phase.m_phase_type != UVM_PHASE_DOMAIN) begin phase = phase.m_parent; end if (phase == null) begin return null; end if(!$cast(get_domain,phase)) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "PH/INTERNAL") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "PH/INTERNAL") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("PH/INTERNAL", "get_domain: m_phase_type is DOMAIN but $cast to uvm_domain fails", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1098, "", 1); end end end endfunction function string uvm_phase::get_domain_name(); uvm_domain domain; domain = get_domain(); if (domain == null) begin return "unknown"; end return domain.get_name(); endfunction function string uvm_phase::get_schedule_name(bit hier=0); uvm_phase sched; string s; sched = get_schedule(hier); if (sched == null) begin return ""; end s = sched.get_name(); while (sched.m_parent != null && sched.m_parent != sched && (sched.m_parent.get_phase_type() == UVM_PHASE_SCHEDULE)) begin sched = sched.m_parent; s = {sched.get_name(),(s.len()>0?".":""),s}; end return s; endfunction function string uvm_phase::get_full_name(); string dom, sch; if (m_phase_type == UVM_PHASE_IMP) begin return get_name(); end get_full_name = get_domain_name(); sch = get_schedule_name(); if (sch != "") begin get_full_name = {get_full_name, ".", sch}; end if (m_phase_type != UVM_PHASE_DOMAIN && m_phase_type != UVM_PHASE_SCHEDULE) begin get_full_name = {get_full_name, ".", get_name()}; end endfunction function uvm_phase_type uvm_phase::get_phase_type(); return m_phase_type; endfunction function void uvm_phase::set_max_ready_to_end_iterations(int max); max_ready_to_end_iters = max; endfunction function int uvm_phase::get_max_ready_to_end_iterations(); return max_ready_to_end_iters; endfunction function void uvm_phase::set_default_max_ready_to_end_iterations(int max); m_default_max_ready_to_end_iters = max; endfunction function int uvm_phase::get_default_max_ready_to_end_iterations(); return m_default_max_ready_to_end_iters; endfunction function void uvm_phase::set_state(uvm_phase_state state); if (m_state == state) begin return; end if (state == UVM_PHASE_STARTED) begin m_run_count++; end m_state_chg.m_jump_to = m_jump_phase; m_state_chg.m_prev_state = m_state; m_state = state; begin uvm_callback_iter#(uvm_phase,uvm_phase_cb) iter = new(this); uvm_phase_cb cb = iter.first(); while(cb != null) begin cb.phase_state_change(this, m_state_chg); cb = iter.next(); end end endfunction : set_state function uvm_phase_state uvm_phase::get_state(); return m_state; endfunction function int uvm_phase::get_run_count(); return m_run_count; endfunction function void uvm_phase::m_print_successors(); uvm_phase found; static string spaces = " "; static int level; if (m_phase_type == UVM_PHASE_DOMAIN) begin level = 0; end begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "UVM/PHASE/SUCC") >= UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "UVM/PHASE/SUCC") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("UVM/PHASE/SUCC", $sformatf("%s%s (%s) id=%0d",spaces.substr(0,level*2),get_name(), m_phase_type.name(),get_inst_id()), UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1252, "", 1); end end level++; foreach (m_successors[succ]) begin succ.m_print_successors(); end level--; endfunction function uvm_phase uvm_phase::m_find_predecessor(uvm_phase phase, bit stay_in_scope=1, uvm_phase orig_phase=null); uvm_phase found; if (phase == null) begin return null ; end if (phase == m_imp || phase == this) begin return this; end foreach (m_predecessors[pred]) begin uvm_phase orig; orig = (orig_phase==null) ? this : orig_phase; if (!stay_in_scope || (pred.get_schedule() == orig.get_schedule()) || (pred.get_domain() == orig.get_domain())) begin found = pred.m_find_predecessor(phase,stay_in_scope,orig); if (found != null) begin return found; end end end return null; endfunction function uvm_phase uvm_phase::m_find_predecessor_by_name(string name, bit stay_in_scope=1, uvm_phase orig_phase=null); uvm_phase found; if (get_name() == name) begin return this; end foreach (m_predecessors[pred]) begin uvm_phase orig; orig = (orig_phase==null) ? this : orig_phase; if (!stay_in_scope || (pred.get_schedule() == orig.get_schedule()) || (pred.get_domain() == orig.get_domain())) begin found = pred.m_find_predecessor_by_name(name,stay_in_scope,orig); if (found != null) begin return found; end end end return null; endfunction function uvm_phase uvm_phase::m_find_successor(uvm_phase phase, bit stay_in_scope=1, uvm_phase orig_phase=null); uvm_phase found; if (phase == null) begin return null ; end if (phase == m_imp || phase == this) begin return this; end foreach (m_successors[succ]) begin uvm_phase orig; orig = (orig_phase==null) ? this : orig_phase; if (!stay_in_scope || (succ.get_schedule() == orig.get_schedule()) || (succ.get_domain() == orig.get_domain())) begin found = succ.m_find_successor(phase,stay_in_scope,orig); if (found != null) begin return found; end end end return null; endfunction function uvm_phase uvm_phase::m_find_successor_by_name(string name, bit stay_in_scope=1, uvm_phase orig_phase=null); uvm_phase found; if (get_name() == name) begin return this; end foreach (m_successors[succ]) begin uvm_phase orig; orig = (orig_phase==null) ? this : orig_phase; if (!stay_in_scope || (succ.get_schedule() == orig.get_schedule()) || (succ.get_domain() == orig.get_domain())) begin found = succ.m_find_successor_by_name(name,stay_in_scope,orig); if (found != null) begin return found; end end end return null; endfunction function uvm_phase uvm_phase::find(uvm_phase phase, bit stay_in_scope=1); if (phase == m_imp || phase == this) begin return phase; end find = m_find_predecessor(phase,stay_in_scope,this); if (find == null) begin find = m_find_successor(phase,stay_in_scope,this); end endfunction function uvm_phase uvm_phase::find_by_name(string name, bit stay_in_scope=1); if (get_name() == name) begin return this; end find_by_name = m_find_predecessor_by_name(name,stay_in_scope,this); if (find_by_name == null) begin find_by_name = m_find_successor_by_name(name,stay_in_scope,this); end endfunction function bit uvm_phase::is(uvm_phase phase); return (m_imp == phase || this == phase); endfunction function bit uvm_phase::is_before(uvm_phase phase); return (!is(phase) && m_find_successor(phase,0,this) != null); endfunction function bit uvm_phase::is_after(uvm_phase phase); return (!is(phase) && m_find_predecessor(phase,0,this) != null); endfunction function void uvm_phase::get_adjacent_predecessor_nodes(ref uvm_phase pred[]); bit done; edges_t predecessors; int idx; foreach (m_predecessors[p]) begin predecessors[p] = 1; end do begin done = 1; foreach (predecessors[p]) begin if (p.get_phase_type() != UVM_PHASE_NODE) begin predecessors.delete(p); foreach (p.m_predecessors[next_p]) begin predecessors[next_p] = 1; end done = 0; end end end while (!done); pred = new [predecessors.size()]; foreach (predecessors[p]) begin pred[idx++] = p; end endfunction : get_adjacent_predecessor_nodes function void uvm_phase::get_adjacent_successor_nodes(ref uvm_phase succ[]); bit done; edges_t successors; int idx; foreach (m_successors[s]) begin successors[s] = 1; end do begin done = 1; foreach (successors[s]) begin if (s.get_phase_type() != UVM_PHASE_NODE) begin successors.delete(s); foreach (s.m_successors[next_s]) begin successors[next_s] = 1; end done = 0; end end end while (!done); succ = new [successors.size()]; foreach (successors[s]) begin succ[idx++] = s; end endfunction : get_adjacent_successor_nodes function void uvm_phase::get_predecessors(ref edges_t predecessors); foreach (m_predecessors[p]) begin predecessors[p] = 1; end endfunction : get_predecessors function void uvm_phase::get_successors(ref edges_t successors); foreach (m_successors[p]) begin successors[p] = 1; end endfunction : get_successors function void uvm_phase::get_sync_relationships(ref edges_t relationships); foreach (m_sync[i]) begin relationships[m_sync[i]] = 1; end endfunction : get_sync_relationships function void uvm_phase::get_predecessors_for_successors(output edges_t pred_of_succ); bit done; uvm_phase successors[]; get_adjacent_successor_nodes(successors); foreach (successors[s]) begin foreach (successors[s].m_predecessors[pred]) begin pred_of_succ[pred] = 1; end end do begin done=1; foreach (pred_of_succ[pred]) begin if (pred.get_phase_type() != UVM_PHASE_NODE) begin pred_of_succ.delete(pred); foreach (pred.m_predecessors[next_pred]) begin pred_of_succ[next_pred] = 1; end done =0; end end end while (!done); pred_of_succ.delete(this); endfunction task uvm_phase::m_wait_for_pred(); edges_t pred_of_succ; get_predecessors_for_successors(pred_of_succ); foreach (pred_of_succ[sibling]) begin if (m_phase_trace) begin string s; s = $sformatf("Waiting for phase '%s' (%0d) to be READY_TO_END. Current state is %s", sibling.get_name(),sibling.get_inst_id(),sibling.m_state.name()); if (uvm_phase::m_phase_trace) begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH/TRC/WAIT_PRED_OF_SUCC") >= UVM_HIGH) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH/TRC/WAIT_PRED_OF_SUCC") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH/TRC/WAIT_PRED_OF_SUCC", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),s}, UVM_HIGH, "t/uvm/src/base/uvm_phase.svh", 1597, "", 1); end end end sibling.wait_for_state(UVM_PHASE_READY_TO_END, UVM_GTE); if (m_phase_trace) begin string s; s = $sformatf("Phase '%s' (%0d) is now READY_TO_END. Releasing phase", sibling.get_name(),sibling.get_inst_id()); if (uvm_phase::m_phase_trace) begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH/TRC/WAIT_PRED_OF_SUCC") >= UVM_HIGH) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH/TRC/WAIT_PRED_OF_SUCC") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH/TRC/WAIT_PRED_OF_SUCC", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),s}, UVM_HIGH, "t/uvm/src/base/uvm_phase.svh", 1606, "", 1); end end end end if (m_phase_trace) begin if (pred_of_succ.num()) begin string s = "( "; foreach (pred_of_succ[pred]) begin s = {s, pred.get_full_name()," "}; end s = {s, ")"}; if (uvm_phase::m_phase_trace) begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH/TRC/WAIT_PRED_OF_SUCC") >= UVM_HIGH) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH/TRC/WAIT_PRED_OF_SUCC") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH/TRC/WAIT_PRED_OF_SUCC", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),{"*** All pred to succ ",s," in READY_TO_END state, so ending phase ***"}}, UVM_HIGH, "t/uvm/src/base/uvm_phase.svh", 1621, "", 1); end end end else begin if (uvm_phase::m_phase_trace) begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH/TRC/WAIT_PRED_OF_SUCC") >= UVM_HIGH) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH/TRC/WAIT_PRED_OF_SUCC") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH/TRC/WAIT_PRED_OF_SUCC", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),"*** No pred to succ other than myself, so ending phase ***"}, UVM_HIGH, "t/uvm/src/base/uvm_phase.svh", 1625, "", 1); end end end end #0; endtask function void uvm_phase::m_report_null_objection(uvm_object obj, string description, int count, string action); string m_action; string m_addon; string m_obj_name = (obj == null) ? "uvm_top" : obj.get_full_name(); if ((action == "raise") || (action == "drop")) begin if (count != 1) begin m_action = $sformatf("%s %0d objections", action, count); end else begin m_action = $sformatf("%s an objection", action); end end else if (action == "get_objection_count") begin m_action = "call get_objection_count"; end if (this.get_phase_type() == UVM_PHASE_IMP) begin m_addon = " (This is a UVM_PHASE_IMP, you have to query the schedule to find the UVM_PHASE_NODE)"; end begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM/PH/NULL_OBJECTION") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM/PH/NULL_OBJECTION") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM/PH/NULL_OBJECTION", $sformatf("'%s' attempted to %s on '%s', however '%s' is not a task-based phase node! %s", m_obj_name, m_action, get_name(), get_name(), m_addon), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1672, "", 1); end end endfunction : m_report_null_objection function void uvm_phase::raise_objection (uvm_object obj, string description="", int count=1); uvm_objection phase_done; phase_done = get_objection(); if (phase_done != null) begin phase_done.raise_objection(obj,description,count); end else begin m_report_null_objection(obj, description, count, "raise"); end endfunction function void uvm_phase::drop_objection (uvm_object obj, string description="", int count=1); uvm_objection phase_done; phase_done = get_objection(); if (phase_done != null) begin phase_done.drop_objection(obj,description,count); end else begin m_report_null_objection(obj, description, count, "drop"); end endfunction function int uvm_phase::get_objection_count (uvm_object obj=null); uvm_objection phase_done; phase_done = get_objection(); if (phase_done != null) begin return phase_done.get_objection_count(obj); end else begin m_report_null_objection(obj, "" , 0, "get_objection_count"); return 0; end endfunction : get_objection_count function int uvm_phase::get_objection_total (uvm_object obj=null); uvm_objection phase_done; phase_done = get_objection(); if (phase_done != null) begin return phase_done.get_objection_total(obj); end else begin m_report_null_objection(obj, "" , 0, "get_objection_total"); return 0; end endfunction : get_objection_total function void uvm_phase::sync(uvm_domain target, uvm_phase phase=null, uvm_phase with_phase=null); if (!this.is_domain()) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "PH_BADSYNC") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "PH_BADSYNC") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("PH_BADSYNC", "sync() called from a non-domain phase schedule node", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1758, "", 1); end end end else if (target == null) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "PH_BADSYNC") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "PH_BADSYNC") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("PH_BADSYNC", "sync() called with a null target domain", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1761, "", 1); end end end else if (!target.is_domain()) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "PH_BADSYNC") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "PH_BADSYNC") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("PH_BADSYNC", "sync() called with a non-domain phase schedule node as target", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1764, "", 1); end end end else if (phase == null && with_phase != null) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "PH_BADSYNC") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "PH_BADSYNC") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("PH_BADSYNC", "sync() called with null phase and non-null with phase", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1767, "", 1); end end end else if (phase == null) begin edges_t visited; uvm_phase queue[$]; queue.push_back(this); visited[this] = 1; while (queue.size()) begin uvm_phase node; node = queue.pop_front(); if (node.m_imp != null) begin sync(target, node.m_imp); end foreach (node.m_successors[succ]) begin if (!visited.exists(succ)) begin queue.push_back(succ); visited[succ] = 1; end end end end else begin uvm_phase from_node, to_node; int found_to[$], found_from[$]; if(with_phase == null) begin with_phase = phase; end from_node = find(phase); to_node = target.find(with_phase); if(from_node == null || to_node == null) begin return; end found_to = from_node.m_sync.find_index(node) with (node == to_node); found_from = to_node.m_sync.find_index(node) with (node == from_node); if (found_to.size() == 0) begin from_node.m_sync.push_back(to_node); end if (found_from.size() == 0) begin to_node.m_sync.push_back(from_node); end end endfunction function void uvm_phase::unsync(uvm_domain target, uvm_phase phase=null, uvm_phase with_phase=null); if (!this.is_domain()) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "PH_BADSYNC") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "PH_BADSYNC") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("PH_BADSYNC", "unsync() called from a non-domain phase schedule node", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1824, "", 1); end end end else if (target == null) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "PH_BADSYNC") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "PH_BADSYNC") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("PH_BADSYNC", "unsync() called with a null target domain", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1826, "", 1); end end end else if (!target.is_domain()) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "PH_BADSYNC") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "PH_BADSYNC") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("PH_BADSYNC", "unsync() called with a non-domain phase schedule node as target", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1828, "", 1); end end end else if (phase == null && with_phase != null) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "PH_BADSYNC") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "PH_BADSYNC") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("PH_BADSYNC", "unsync() called with null phase and non-null with phase", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1830, "", 1); end end end else if (phase == null) begin edges_t visited; uvm_phase queue[$]; queue.push_back(this); visited[this] = 1; while (queue.size()) begin uvm_phase node; node = queue.pop_front(); if (node.m_imp != null) begin unsync(target,node.m_imp); end foreach (node.m_successors[succ]) begin if (!visited.exists(succ)) begin queue.push_back(succ); visited[succ] = 1; end end end end else begin uvm_phase from_node, to_node; int found_to[$], found_from[$]; if(with_phase == null) begin with_phase = phase; end from_node = find(phase); to_node = target.find(with_phase); if(from_node == null || to_node == null) begin return; end found_to = from_node.m_sync.find_index(node) with (node == to_node); found_from = to_node.m_sync.find_index(node) with (node == from_node); if (found_to.size()) begin from_node.m_sync.delete(found_to[0]); end if (found_from.size()) begin to_node.m_sync.delete(found_from[0]); end end endfunction task uvm_phase::wait_for_state(uvm_phase_state state, uvm_wait_op op=UVM_EQ); case (op) UVM_EQ: begin wait((state&m_state) != 0); end UVM_NE: begin wait((state&m_state) == 0); end UVM_LT: begin wait(m_state < state); end UVM_LTE: begin wait(m_state <= state); end UVM_GT: begin wait(m_state > state); end UVM_GTE: begin wait(m_state >= state); end endcase endtask function void uvm_phase::set_jump_phase(uvm_phase phase) ; uvm_phase d; bit active; uvm_phase_state state; state = get_state(); active = (state >= UVM_PHASE_STARTED) && (state <= UVM_PHASE_ENDED); if (!active) begin if (phase == null) begin m_jump_phase = null; m_jump_fwd = 0; m_jump_bkwd = 0; m_premature_end = 0; return; end else begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "JMPPHIDL") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "JMPPHIDL") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("JMPPHIDL", { "Attempting to jump from phase \"", get_name(), "\" which is not currently active (current state is ", state.name(), "). The jump will not happen until the phase becomes ", "active."}, uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1942, "", 1); end end end end d = m_find_predecessor(phase,0); if (d == null) begin d = m_find_successor(phase,0); if (d == null) begin string msg; $sformat(msg,{"phase %s is neither a predecessor or successor of ", "phase %s or is non-existant, so we cannot jump to it. ", "Phase control flow is now undefined so the simulation ", "must terminate"}, phase.get_name(), get_name()); begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "PH_BADJUMP") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "PH_BADJUMP") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("PH_BADJUMP", msg, uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1967, "", 1); end end end else begin m_jump_fwd = 1; begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH_JUMPF") >= UVM_DEBUG) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH_JUMPF") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH_JUMPF", $sformatf("jumping forward to phase %s", phase.get_name()), UVM_DEBUG, "t/uvm/src/base/uvm_phase.svh", 1972, "", 1); end end end end else begin m_jump_bkwd = 1; begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH_JUMPB") >= UVM_DEBUG) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH_JUMPB") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH_JUMPB", $sformatf("jumping backward to phase %s", phase.get_name()), UVM_DEBUG, "t/uvm/src/base/uvm_phase.svh", 1978, "", 1); end end end m_jump_phase = d; endfunction function bit uvm_phase::is_jumping_forward(); return m_jump_fwd; endfunction : is_jumping_forward function bit uvm_phase::is_jumping_backward(); return m_jump_bkwd; endfunction : is_jumping_backward function void uvm_phase::end_prematurely() ; m_premature_end = 1 ; endfunction function bit uvm_phase::is_ending_prematurely(); return m_premature_end; endfunction : is_ending_prematurely function void uvm_phase::jump(uvm_phase phase); set_jump_phase(phase) ; end_prematurely() ; endfunction function void uvm_phase::jump_all(uvm_phase phase); begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "NOTIMPL") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "NOTIMPL") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("NOTIMPL", "uvm_phase::jump_all is not implemented and has been replaced by uvm_domain::jump_all", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 2026, "", 1); end end endfunction function uvm_phase uvm_phase::get_jump_target(); return m_jump_phase; endfunction function void uvm_phase::clear(uvm_phase_state state = UVM_PHASE_DORMANT); uvm_objection phase_done; phase_done = get_objection(); set_state(state); m_phase_proc = null; if (phase_done != null) begin phase_done.clear(this); end endfunction function void uvm_phase::clear_successors(uvm_phase_state state = UVM_PHASE_DORMANT, uvm_phase end_state=null); if(this == end_state) begin return; end clear(state); foreach(m_successors[succ]) begin succ.clear_successors(state, end_state); end endfunction task uvm_phase::wait_for_self_and_siblings_to_drop() ; bit need_to_check_all = 1 ; uvm_root top; uvm_coreservice_t cs; edges_t siblings; if (uvm_phase::m_phase_trace) begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH/TRC/WAIT_SELF_AND_SIBLINGS") >= UVM_HIGH) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH/TRC/WAIT_SELF_AND_SIBLINGS") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH/TRC/WAIT_SELF_AND_SIBLINGS", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),"WAITING FOR SELF AND SIBLINGS TO DROP"}, UVM_HIGH, "t/uvm/src/base/uvm_phase.svh", 2087, "", 1); end end cs = uvm_coreservice_t::get(); top = cs.get_root(); get_predecessors_for_successors(siblings); foreach (m_sync[i]) begin siblings[m_sync[i]] = 1; end siblings[this] = 1; while (need_to_check_all) begin uvm_objection phase_done; string msg; phase_done = get_objection(); need_to_check_all = 0 ; foreach(siblings[sib]) begin phase_done = sib.get_objection(); sib.wait_for_state(UVM_PHASE_EXECUTING, UVM_GTE); if ((phase_done != null) && (phase_done.get_objection_total(top) != 0)) begin if (m_phase_trace) begin msg = $sformatf("Waiting for phase '%s' (%0d) to be READY_TO_END. Current state is %s", sib.get_name(),sib.get_inst_id(),sib.m_state.name()); if (uvm_phase::m_phase_trace) begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH/TRC/WAIT_SELF_AND_SIBLINGS") >= UVM_HIGH) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH/TRC/WAIT_SELF_AND_SIBLINGS") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH/TRC/WAIT_SELF_AND_SIBLINGS", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),msg}, UVM_HIGH, "t/uvm/src/base/uvm_phase.svh", 2114, "", 1); end end end m_state = UVM_PHASE_EXECUTING ; phase_done.wait_for(UVM_ALL_DROPPED, top); if (m_phase_trace) begin msg = $sformatf("Phase '%s' (%0d) is now READY_TO_END. Releasing phase", sib.get_name(),sib.get_inst_id()); if (uvm_phase::m_phase_trace) begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH/TRC/WAIT_SELF_AND_SIBLINGS") >= UVM_HIGH) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH/TRC/WAIT_SELF_AND_SIBLINGS") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH/TRC/WAIT_SELF_AND_SIBLINGS", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),msg}, UVM_HIGH, "t/uvm/src/base/uvm_phase.svh", 2121, "", 1); end end end need_to_check_all = 1 ; end end end endtask function void uvm_phase::kill(); begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH_KILL") >= UVM_DEBUG) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH_KILL") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH_KILL", {"killing phase '", get_name(),"'"}, UVM_DEBUG, "t/uvm/src/base/uvm_phase.svh", 2134, "", 1); end end if (m_phase_proc != null) begin m_phase_proc.kill(); m_phase_proc = null; end endfunction function void uvm_phase::kill_successors(); foreach (m_successors[succ]) begin succ.kill_successors(); end kill(); endfunction function void uvm_phase::m_terminate_phase(); uvm_objection phase_done; phase_done = get_objection(); if (phase_done != null) begin phase_done.clear(this); end endfunction function void uvm_phase::m_print_termination_state(); uvm_root top; uvm_coreservice_t cs; uvm_objection phase_done; phase_done = get_objection(); cs = uvm_coreservice_t::get(); top = cs.get_root(); if (phase_done != null) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH_TERMSTATE") >= UVM_DEBUG) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH_TERMSTATE") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH_TERMSTATE", $sformatf("phase %s outstanding objections = %0d", get_name(), phase_done.get_objection_total(top)), UVM_DEBUG, "t/uvm/src/base/uvm_phase.svh", 2187, "", 1); end end end else begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH_TERMSTATE") >= UVM_DEBUG) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH_TERMSTATE") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH_TERMSTATE", $sformatf("phase %s has no outstanding objections", get_name()), UVM_DEBUG, "t/uvm/src/base/uvm_phase.svh", 2193, "", 1); end end end endfunction typedef class uvm_build_phase; typedef class uvm_connect_phase; typedef class uvm_end_of_elaboration_phase; typedef class uvm_start_of_simulation_phase; typedef class uvm_run_phase; typedef class uvm_extract_phase; typedef class uvm_check_phase; typedef class uvm_report_phase; typedef class uvm_final_phase; typedef class uvm_pre_reset_phase; typedef class uvm_reset_phase; typedef class uvm_post_reset_phase; typedef class uvm_pre_configure_phase; typedef class uvm_configure_phase; typedef class uvm_post_configure_phase; typedef class uvm_pre_main_phase; typedef class uvm_main_phase; typedef class uvm_post_main_phase; typedef class uvm_pre_shutdown_phase; typedef class uvm_shutdown_phase; typedef class uvm_post_shutdown_phase; uvm_phase build_ph; uvm_phase connect_ph; uvm_phase end_of_elaboration_ph; uvm_phase start_of_simulation_ph; uvm_phase run_ph; uvm_phase extract_ph; uvm_phase check_ph; uvm_phase report_ph; class uvm_domain extends uvm_phase; static local uvm_domain m_uvm_domain; static local uvm_domain m_domains[string]; static local uvm_phase m_uvm_schedule; static function void get_domains(output uvm_domain domains[string]); domains = m_domains; endfunction static function uvm_phase get_uvm_schedule(); void'(get_uvm_domain()); return m_uvm_schedule; endfunction static function uvm_domain get_common_domain(); uvm_domain domain; if(m_domains.exists("common")) begin domain = m_domains["common"]; end if (domain != null) begin return domain; end domain = new("common"); domain.add(uvm_build_phase::get()); domain.add(uvm_connect_phase::get()); domain.add(uvm_end_of_elaboration_phase::get()); domain.add(uvm_start_of_simulation_phase::get()); domain.add(uvm_run_phase::get()); domain.add(uvm_extract_phase::get()); domain.add(uvm_check_phase::get()); domain.add(uvm_report_phase::get()); domain.add(uvm_final_phase::get()); build_ph = domain.find(uvm_build_phase::get()); connect_ph = domain.find(uvm_connect_phase::get()); end_of_elaboration_ph = domain.find(uvm_end_of_elaboration_phase::get()); start_of_simulation_ph = domain.find(uvm_start_of_simulation_phase::get()); run_ph = domain.find(uvm_run_phase::get()); extract_ph = domain.find(uvm_extract_phase::get()); check_ph = domain.find(uvm_check_phase::get()); report_ph = domain.find(uvm_report_phase::get()); domain = get_uvm_domain(); m_domains["common"].add(domain, .with_phase(m_domains["common"].find(uvm_run_phase::get()))); return m_domains["common"]; endfunction static function void add_uvm_phases(uvm_phase schedule); schedule.add(uvm_pre_reset_phase::get()); schedule.add(uvm_reset_phase::get()); schedule.add(uvm_post_reset_phase::get()); schedule.add(uvm_pre_configure_phase::get()); schedule.add(uvm_configure_phase::get()); schedule.add(uvm_post_configure_phase::get()); schedule.add(uvm_pre_main_phase::get()); schedule.add(uvm_main_phase::get()); schedule.add(uvm_post_main_phase::get()); schedule.add(uvm_pre_shutdown_phase::get()); schedule.add(uvm_shutdown_phase::get()); schedule.add(uvm_post_shutdown_phase::get()); endfunction static function uvm_domain get_uvm_domain(); if (m_uvm_domain == null) begin m_uvm_domain = new("uvm"); m_uvm_schedule = new("uvm_sched", UVM_PHASE_SCHEDULE); add_uvm_phases(m_uvm_schedule); m_uvm_domain.add(m_uvm_schedule); end return m_uvm_domain; endfunction function new(string name); super.new(name,UVM_PHASE_DOMAIN); if (m_domains.exists(name)) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UNIQDOMNAM") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UNIQDOMNAM") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UNIQDOMNAM", $sformatf("Domain created with non-unique name '%s'", name), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_domain.svh", 201, "", 1); end end end m_domains[name] = this; endfunction function void jump(uvm_phase phase); uvm_phase phases[$]; m_get_transitive_children(phases); phases = phases.find(item) with (item.get_state() inside {[UVM_PHASE_STARTED:UVM_PHASE_CLEANUP]}); foreach(phases[idx]) begin if(phases[idx].is_before(phase) || phases[idx].is_after(phase)) begin phases[idx].jump(phase); end end endfunction static function void jump_all(uvm_phase phase); uvm_domain domains[string]; uvm_domain::get_domains(domains); foreach(domains[idx]) begin domains[idx].jump(phase); end endfunction endclass virtual class uvm_bottomup_phase extends uvm_phase; function new(string name); super.new(name,UVM_PHASE_IMP); endfunction virtual function void traverse(uvm_component comp, uvm_phase phase, uvm_phase_state state); string name; uvm_domain phase_domain =phase.get_domain(); uvm_domain comp_domain = comp.get_domain(); uvm_phase_hopper hopper; hopper = uvm_phase_hopper::get_global_hopper(); if (comp.get_first_child(name)) begin do begin hopper.traverse_on(this, comp.get_child(name), phase, state); end while(comp.get_next_child(name)); end if (m_phase_trace) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH_TRACE") >= UVM_DEBUG) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH_TRACE") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH_TRACE", $sformatf("bottomup-phase phase=%s state=%s comp=%s comp.domain=%s phase.domain=%s", phase.get_name(), state.name(), comp.get_full_name(),comp_domain.get_name(),phase_domain.get_name()), UVM_DEBUG, "t/uvm/src/base/uvm_bottomup_phase.svh", 82, "", 1); end end end if (phase_domain == uvm_domain::get_common_domain() || phase_domain == comp_domain) begin case (state) UVM_PHASE_STARTED: begin comp.m_current_phase = phase; comp.m_apply_verbosity_settings(phase); comp.phase_started(phase); end UVM_PHASE_EXECUTING: begin uvm_phase ph = this; if (comp.m_phase_imps.exists(this)) begin ph = comp.m_phase_imps[this]; end hopper.execute_on(ph, comp, phase); end UVM_PHASE_READY_TO_END: begin comp.phase_ready_to_end(phase); end UVM_PHASE_ENDED: begin comp.phase_ended(phase); comp.m_current_phase = null; end default: begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "PH_BADEXEC") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "PH_BADEXEC") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("PH_BADEXEC", "bottomup phase traverse internal error", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_bottomup_phase.svh", 110, "", 1); end end end endcase end endfunction virtual function void execute(uvm_component comp, uvm_phase phase); process proc = process::self(); proc.srandom(uvm_create_random_seed(phase.get_type_name(), comp.get_full_name())); comp.m_current_phase = phase; exec_func(comp,phase); endfunction endclass virtual class uvm_topdown_phase extends uvm_phase; function new(string name); super.new(name,UVM_PHASE_IMP); endfunction virtual function void traverse(uvm_component comp, uvm_phase phase, uvm_phase_state state); string name; uvm_domain phase_domain = phase.get_domain(); uvm_domain comp_domain = comp.get_domain(); uvm_phase_hopper hopper; hopper = uvm_phase_hopper::get_global_hopper(); if (m_phase_trace) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH_TRACE") >= UVM_DEBUG) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH_TRACE") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH_TRACE", $sformatf("topdown-phase phase=%s state=%s comp=%s comp.domain=%s phase.domain=%s", phase.get_name(), state.name(), comp.get_full_name(),comp_domain.get_name(),phase_domain.get_name()), UVM_DEBUG, "t/uvm/src/base/uvm_topdown_phase.svh", 71, "", 1); end end end if (phase_domain == uvm_domain::get_common_domain() || phase_domain == comp_domain) begin case (state) UVM_PHASE_STARTED: begin comp.m_current_phase = phase; comp.m_apply_verbosity_settings(phase); comp.phase_started(phase); end UVM_PHASE_EXECUTING: begin if (!(phase.get_name() == "build" && comp.m_build_done)) begin uvm_phase ph = this; comp.m_phasing_active++; if (comp.m_phase_imps.exists(this)) begin ph = comp.m_phase_imps[this]; end hopper.execute_on(ph, comp, phase); comp.m_phasing_active--; end end UVM_PHASE_READY_TO_END: begin comp.phase_ready_to_end(phase); end UVM_PHASE_ENDED: begin comp.phase_ended(phase); comp.m_current_phase = null; end default: begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "PH_BADEXEC") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "PH_BADEXEC") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("PH_BADEXEC", "topdown phase traverse internal error", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_topdown_phase.svh", 103, "", 1); end end end endcase end if(comp.get_first_child(name)) begin do begin hopper.traverse_on(this, comp.get_child(name), phase, state); end while(comp.get_next_child(name)); end endfunction virtual function void execute(uvm_component comp, uvm_phase phase); process proc = process::self(); proc.srandom(uvm_create_random_seed(phase.get_type_name(), comp.get_full_name())); comp.m_current_phase = phase; exec_func(comp,phase); endfunction endclass virtual class uvm_task_phase extends uvm_phase; function new(string name); super.new(name,UVM_PHASE_IMP); endfunction virtual function void traverse(uvm_component comp, uvm_phase phase, uvm_phase_state state); phase.m_num_procs_not_yet_returned = 0; m_traverse(comp, phase, state); endfunction function void m_traverse(uvm_component comp, uvm_phase phase, uvm_phase_state state); string name; uvm_domain phase_domain =phase.get_domain(); uvm_domain comp_domain = comp.get_domain(); uvm_sequencer_base seqr; uvm_phase_hopper hopper; hopper = uvm_phase_hopper::get_global_hopper(); if (comp.get_first_child(name)) begin do begin hopper.traverse_on(this, comp.get_child(name), phase, state); end while(comp.get_next_child(name)); end if (m_phase_trace) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH_TRACE") >= UVM_DEBUG) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH_TRACE") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH_TRACE", $sformatf("topdown-phase phase=%s state=%s comp=%s comp.domain=%s phase.domain=%s", phase.get_name(), state.name(), comp.get_full_name(),comp_domain.get_name(),phase_domain.get_name()), UVM_DEBUG, "t/uvm/src/base/uvm_task_phase.svh", 111, "", 1); end end end if (phase_domain == uvm_domain::get_common_domain() || phase_domain == comp_domain) begin case (state) UVM_PHASE_STARTED: begin comp.m_current_phase = phase; comp.m_apply_verbosity_settings(phase); comp.phase_started(phase); if ($cast(seqr, comp)) begin seqr.start_phase_sequence(phase); end end UVM_PHASE_EXECUTING: begin uvm_phase ph = this; if (comp.m_phase_imps.exists(this)) begin ph = comp.m_phase_imps[this]; end hopper.execute_on(ph, comp, phase); end UVM_PHASE_READY_TO_END: begin comp.phase_ready_to_end(phase); end UVM_PHASE_ENDED: begin if ($cast(seqr, comp)) begin seqr.stop_phase_sequence(phase); end comp.phase_ended(phase); comp.m_current_phase = null; end default: begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "PH_BADEXEC") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "PH_BADEXEC") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("PH_BADEXEC", "task phase traverse internal error", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_task_phase.svh", 149, "", 1); end end end endcase end endfunction virtual function void execute(uvm_component comp, uvm_phase phase); fork begin process proc; proc = process::self(); proc.srandom(uvm_create_random_seed(phase.get_type_name(), comp.get_full_name())); phase.m_num_procs_not_yet_returned++; exec_task(comp,phase); phase.m_num_procs_not_yet_returned--; end join_none endfunction endclass class uvm_build_phase extends uvm_topdown_phase; virtual function void exec_func(uvm_component comp, uvm_phase phase); comp.build_phase(phase); endfunction local static uvm_build_phase m_inst; static function string type_name(); return "uvm_build_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_build_phase"; endfunction : get_type_name static function uvm_build_phase get(); if(m_inst == null) begin m_inst = new(); end return m_inst; endfunction protected function new(string name="build"); super.new(name); endfunction endclass class uvm_connect_phase extends uvm_bottomup_phase; virtual function void exec_func(uvm_component comp, uvm_phase phase); comp.connect_phase(phase); endfunction local static uvm_connect_phase m_inst; static function string type_name(); return "uvm_connect_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_connect_phase"; endfunction : get_type_name static function uvm_connect_phase get(); if(m_inst == null) begin m_inst = new(); end return m_inst; endfunction protected function new(string name="connect"); super.new(name); endfunction endclass class uvm_end_of_elaboration_phase extends uvm_bottomup_phase; virtual function void exec_func(uvm_component comp, uvm_phase phase); comp.end_of_elaboration_phase(phase); endfunction local static uvm_end_of_elaboration_phase m_inst; static function string type_name(); return "uvm_end_of_elaboration_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_end_of_elaboration_phase"; endfunction : get_type_name static function uvm_end_of_elaboration_phase get(); if(m_inst == null) begin m_inst = new(); end return m_inst; endfunction protected function new(string name="end_of_elaboration"); super.new(name); endfunction endclass class uvm_start_of_simulation_phase extends uvm_bottomup_phase; virtual function void exec_func(uvm_component comp, uvm_phase phase); comp.start_of_simulation_phase(phase); endfunction local static uvm_start_of_simulation_phase m_inst; static function string type_name(); return "uvm_start_of_simulation_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_start_of_simulation_phase"; endfunction : get_type_name static function uvm_start_of_simulation_phase get(); if(m_inst == null) begin m_inst = new(); end return m_inst; endfunction protected function new(string name="start_of_simulation"); super.new(name); endfunction endclass class uvm_run_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.run_phase(phase); endtask local static uvm_run_phase m_inst; static function string type_name(); return "uvm_run_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_run_phase"; endfunction : get_type_name static function uvm_run_phase get(); if(m_inst == null) begin m_inst = new; end return m_inst; endfunction protected function new(string name="run"); super.new(name); endfunction endclass class uvm_extract_phase extends uvm_bottomup_phase; virtual function void exec_func(uvm_component comp, uvm_phase phase); comp.extract_phase(phase); endfunction local static uvm_extract_phase m_inst; static function string type_name(); return "uvm_extract_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_extract_phase"; endfunction : get_type_name static function uvm_extract_phase get(); if(m_inst == null) begin m_inst = new(); end return m_inst; endfunction protected function new(string name="extract"); super.new(name); endfunction endclass class uvm_check_phase extends uvm_bottomup_phase; virtual function void exec_func(uvm_component comp, uvm_phase phase); comp.check_phase(phase); endfunction local static uvm_check_phase m_inst; static function string type_name(); return "uvm_check_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_check_phase"; endfunction : get_type_name static function uvm_check_phase get(); if(m_inst == null) begin m_inst = new(); end return m_inst; endfunction protected function new(string name="check"); super.new(name); endfunction endclass class uvm_report_phase extends uvm_bottomup_phase; virtual function void exec_func(uvm_component comp, uvm_phase phase); comp.report_phase(phase); endfunction local static uvm_report_phase m_inst; static function string type_name(); return "uvm_report_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_report_phase"; endfunction : get_type_name static function uvm_report_phase get(); if(m_inst == null) begin m_inst = new(); end return m_inst; endfunction protected function new(string name="report"); super.new(name); endfunction endclass class uvm_final_phase extends uvm_topdown_phase; virtual function void exec_func(uvm_component comp, uvm_phase phase); comp.final_phase(phase); endfunction local static uvm_final_phase m_inst; static function string type_name(); return "uvm_final_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_final_phase"; endfunction : get_type_name static function uvm_final_phase get(); if(m_inst == null) begin m_inst = new(); end return m_inst; endfunction protected function new(string name="final"); super.new(name); endfunction endclass class uvm_pre_reset_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.pre_reset_phase(phase); endtask local static uvm_pre_reset_phase m_inst; static function string type_name(); return "uvm_pre_reset_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_pre_reset_phase"; endfunction : get_type_name static function uvm_pre_reset_phase get(); if(m_inst == null) begin m_inst = new; end return m_inst; endfunction protected function new(string name="pre_reset"); super.new(name); endfunction endclass class uvm_reset_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.reset_phase(phase); endtask local static uvm_reset_phase m_inst; static function string type_name(); return "uvm_reset_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_reset_phase"; endfunction : get_type_name static function uvm_reset_phase get(); if(m_inst == null) begin m_inst = new; end return m_inst; endfunction protected function new(string name="reset"); super.new(name); endfunction endclass class uvm_post_reset_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.post_reset_phase(phase); endtask local static uvm_post_reset_phase m_inst; static function string type_name(); return "uvm_post_reset_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_post_reset_phase"; endfunction : get_type_name static function uvm_post_reset_phase get(); if(m_inst == null) begin m_inst = new; end return m_inst; endfunction protected function new(string name="post_reset"); super.new(name); endfunction endclass class uvm_pre_configure_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.pre_configure_phase(phase); endtask local static uvm_pre_configure_phase m_inst; static function string type_name(); return "uvm_pre_configure_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_pre_configure_phase"; endfunction : get_type_name static function uvm_pre_configure_phase get(); if(m_inst == null) begin m_inst = new; end return m_inst; endfunction protected function new(string name="pre_configure"); super.new(name); endfunction endclass class uvm_configure_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.configure_phase(phase); endtask local static uvm_configure_phase m_inst; static function string type_name(); return "uvm_configure_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_configure_phase"; endfunction : get_type_name static function uvm_configure_phase get(); if(m_inst == null) begin m_inst = new; end return m_inst; endfunction protected function new(string name="configure"); super.new(name); endfunction endclass class uvm_post_configure_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.post_configure_phase(phase); endtask local static uvm_post_configure_phase m_inst; static function string type_name(); return "uvm_post_configure_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_post_configure_phase"; endfunction : get_type_name static function uvm_post_configure_phase get(); if(m_inst == null) begin m_inst = new; end return m_inst; endfunction protected function new(string name="post_configure"); super.new(name); endfunction endclass class uvm_pre_main_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.pre_main_phase(phase); endtask local static uvm_pre_main_phase m_inst; static function string type_name(); return "uvm_pre_main_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_pre_main_phase"; endfunction : get_type_name static function uvm_pre_main_phase get(); if(m_inst == null) begin m_inst = new; end return m_inst; endfunction protected function new(string name="pre_main"); super.new(name); endfunction endclass class uvm_main_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.main_phase(phase); endtask local static uvm_main_phase m_inst; static function string type_name(); return "uvm_main_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_main_phase"; endfunction : get_type_name static function uvm_main_phase get(); if(m_inst == null) begin m_inst = new; end return m_inst; endfunction protected function new(string name="main"); super.new(name); endfunction endclass class uvm_post_main_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.post_main_phase(phase); endtask local static uvm_post_main_phase m_inst; static function string type_name(); return "uvm_post_main_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_post_main_phase"; endfunction : get_type_name static function uvm_post_main_phase get(); if(m_inst == null) begin m_inst = new; end return m_inst; endfunction protected function new(string name="post_main"); super.new(name); endfunction endclass class uvm_pre_shutdown_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.pre_shutdown_phase(phase); endtask local static uvm_pre_shutdown_phase m_inst; static function string type_name(); return "uvm_pre_shutdown_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_pre_shutdown_phase"; endfunction : get_type_name static function uvm_pre_shutdown_phase get(); if(m_inst == null) begin m_inst = new; end return m_inst; endfunction protected function new(string name="pre_shutdown"); super.new(name); endfunction endclass class uvm_shutdown_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.shutdown_phase(phase); endtask local static uvm_shutdown_phase m_inst; static function string type_name(); return "uvm_shutdown_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_shutdown_phase"; endfunction : get_type_name static function uvm_shutdown_phase get(); if(m_inst == null) begin m_inst = new; end return m_inst; endfunction protected function new(string name="shutdown"); super.new(name); endfunction endclass class uvm_post_shutdown_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.post_shutdown_phase(phase); endtask local static uvm_post_shutdown_phase m_inst; static function string type_name(); return "uvm_post_shutdown_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_post_shutdown_phase"; endfunction : get_type_name static function uvm_post_shutdown_phase get(); if(m_inst == null) begin m_inst = new; end return m_inst; endfunction protected function new(string name="post_shutdown"); super.new(name); endfunction endclass class uvm_phase_hopper extends uvm_object; typedef uvm_object_registry#(uvm_phase_hopper,"uvm_phase_hopper") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_phase_hopper tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_phase_hopper"; endfunction : type_name virtual function string get_type_name(); return "uvm_phase_hopper"; endfunction : get_type_name extern function new(string name="uvm_phase_hopper"); extern static function uvm_phase_hopper get_global_hopper(); extern virtual function bit try_put(uvm_phase phase); extern protected virtual task get(output uvm_phase phase); extern protected virtual function bit try_get(inout uvm_phase phase); extern protected virtual task peek(output uvm_phase phase); extern protected virtual function bit try_peek(inout uvm_phase phase); extern protected virtual function uvm_objection get_objection(); extern protected virtual function void raise_objection(uvm_object obj, string description = "", int count=1); extern protected virtual function void drop_objection(uvm_object obj, string description = "", int count=1); extern virtual function int get_objection_count( uvm_object obj = null ); extern virtual function int get_objection_total( uvm_object obj = null ); extern virtual task wait_for_objection( uvm_objection_event objt_event, uvm_object obj = null ); extern virtual task run_phases(); extern protected virtual task schedule_phase(uvm_phase phase, uvm_phase from_phase = null); extern protected virtual task process_phase(uvm_phase phase); extern protected virtual task sync_phase(uvm_phase phase); extern protected virtual task start_phase(uvm_phase phase); extern protected virtual task execute_phase(uvm_phase phase); extern protected virtual task end_phase(uvm_phase phase); extern protected virtual task cleanup_phase(uvm_phase phase); extern protected virtual task finish_phase(uvm_phase phase); extern protected virtual task wait_for_waiters(uvm_phase phase, uvm_phase_state prev_state); extern virtual function void traverse_on(uvm_phase imp, uvm_component comp, uvm_phase node, uvm_phase_state state); extern virtual function void execute_on(uvm_phase imp, uvm_component comp, uvm_phase node); local uvm_phase m_queue[$]; local uvm_objection m_objection; endclass function uvm_phase_hopper::new(string name = "uvm_phase_hopper"); super.new(name); m_objection = new("phase_hopper_objection"); endfunction : new function uvm_phase_hopper uvm_phase_hopper::get_global_hopper(); uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); return cs.get_phase_hopper(); endfunction : get_global_hopper function bit uvm_phase_hopper::try_put(uvm_phase phase); raise_objection(phase, "phase scheduled"); m_queue.push_back(phase); return 1; endfunction : try_put task uvm_phase_hopper::get(output uvm_phase phase); wait (m_queue.size() != 0); phase = m_queue.pop_front(); endtask : get function bit uvm_phase_hopper::try_get(inout uvm_phase phase); if (m_queue.size() > 0) begin phase = m_queue.pop_front(); return 1; end else begin return 0; end endfunction : try_get task uvm_phase_hopper::peek(output uvm_phase phase); wait (m_queue.size() != 0); phase = m_queue[0]; endtask : peek function bit uvm_phase_hopper::try_peek(inout uvm_phase phase); if (m_queue.size() > 0) begin phase = m_queue[0]; return 1; end else begin return 0; end endfunction : try_peek function uvm_objection uvm_phase_hopper::get_objection(); if (m_objection == null) begin m_objection = new("phase_hopper_objection"); end return m_objection; endfunction : get_objection function void uvm_phase_hopper::raise_objection(uvm_object obj, string description = "", int count=1); uvm_objection objection; objection = get_objection(); objection.raise_objection(obj, description, count); endfunction : raise_objection function void uvm_phase_hopper::drop_objection(uvm_object obj, string description = "", int count=1); uvm_objection objection; objection = get_objection(); objection.drop_objection(obj, description, count); endfunction : drop_objection function int uvm_phase_hopper::get_objection_count(uvm_object obj = null); uvm_objection objection; objection = get_objection(); return objection.get_objection_count(obj); endfunction : get_objection_count function int uvm_phase_hopper::get_objection_total(uvm_object obj = null); uvm_objection objection; objection = get_objection(); return objection.get_objection_total(obj); endfunction : get_objection_total task uvm_phase_hopper::wait_for_objection( uvm_objection_event objt_event, uvm_object obj = null ); uvm_objection objection; objection = get_objection(); objection.wait_for(objt_event, obj); endtask : wait_for_objection task uvm_phase_hopper::run_phases(); uvm_phase ph; ph = uvm_domain::get_common_domain(); schedule_phase(ph); fork begin forever begin this.get(ph); fork automatic uvm_phase phase = ph; begin this.process_phase(phase); drop_objection(phase, "phase done"); end join_none end end join_none wait_for_objection(UVM_ALL_DROPPED); endtask : run_phases task uvm_phase_hopper::schedule_phase(uvm_phase phase, uvm_phase from_phase = null); uvm_phase_state prev_state; prev_state = phase.get_state(); if(prev_state < UVM_PHASE_SCHEDULED) begin phase.set_state(UVM_PHASE_SCHEDULED); wait_for_waiters(phase, prev_state); void'(this.try_put(phase)); if (uvm_phase::m_phase_trace) begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH/TRC/SCHEDULED") >= UVM_LOW) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH/TRC/SCHEDULED") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH/TRC/SCHEDULED", {$sformatf("Phase '%0s' (id=%0d) ", phase.get_full_name(), phase.get_inst_id()),{"Scheduled from ", (from_phase != null) ? {"phase ",from_phase.get_full_name()}:"run_test"}}, UVM_LOW, "t/uvm/src/base/uvm_phase_hopper.svh", 405, "", 1); end end end endtask : schedule_phase task uvm_phase_hopper::sync_phase(uvm_phase phase); uvm_phase::edges_t edges; uvm_phase_state prev_state; phase.get_predecessors(edges); foreach(edges[p]) begin p.wait_for_state(UVM_PHASE_DONE); end prev_state = phase.get_state(); phase.set_state(UVM_PHASE_SYNCING); wait_for_waiters(phase, prev_state); phase.get_sync_relationships(edges); foreach (edges[s]) begin s.wait_for_state(UVM_PHASE_SYNCING, UVM_GTE); end endtask : sync_phase task uvm_phase_hopper::start_phase(uvm_phase phase); uvm_phase_state prev_state; if (uvm_phase::m_phase_trace) begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH/TRC/STRT") >= UVM_LOW) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH/TRC/STRT") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH/TRC/STRT", {$sformatf("Phase '%0s' (id=%0d) ", phase.get_full_name(), phase.get_inst_id()),"Starting phase"}, UVM_LOW, "t/uvm/src/base/uvm_phase_hopper.svh", 436, "", 1); end end prev_state = phase.get_state(); phase.set_state(UVM_PHASE_STARTED); if (phase.get_phase_type() == UVM_PHASE_NODE) begin uvm_phase imp; imp = phase.get_imp(); traverse_on(imp, null, phase, UVM_PHASE_STARTED); end wait_for_waiters(phase, prev_state); endtask : start_phase task uvm_phase_hopper::execute_phase(uvm_phase phase); uvm_phase_state prev_state; prev_state = phase.get_state(); phase.set_state(UVM_PHASE_EXECUTING); if (phase.get_phase_type() != UVM_PHASE_NODE) begin wait_for_waiters(phase, prev_state); return; end else begin uvm_root top; uvm_phase imp; uvm_task_phase task_phase; top = uvm_root::get(); imp = phase.get_imp(); if (!$cast(task_phase, imp)) begin wait_for_waiters(phase, prev_state); traverse_on(imp, null, phase, UVM_PHASE_EXECUTING); end else begin fork : master_phase_process begin phase.m_phase_proc = process::self(); traverse_on(task_phase, null, phase, UVM_PHASE_EXECUTING); wait(0); end join_none uvm_wait_for_nba_region(); fork begin fork begin wait (phase.m_premature_end); if (uvm_phase::m_phase_trace) begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH/TRC/EXE/JUMP") >= UVM_DEBUG) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH/TRC/EXE/JUMP") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH/TRC/EXE/JUMP", {$sformatf("Phase '%0s' (id=%0d) ", phase.get_full_name(), phase.get_inst_id()),"PHASE EXIT ON JUMP REQUEST"}, UVM_DEBUG, "t/uvm/src/base/uvm_phase_hopper.svh", 499, "", 1); end end end begin int unsigned ready_to_end_count; bit do_ready_to_end; uvm_objection phase_done; phase_done = phase.get_objection(); if (phase_done.get_objection_total(top) || phase.m_use_ovm_run_semantic && imp.get_name() == "run") begin if (!phase_done.m_top_all_dropped) begin phase_done.wait_for(UVM_ALL_DROPPED, top); end if (uvm_phase::m_phase_trace) begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH/TRC/EXE/ALLDROP") >= UVM_DEBUG) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH/TRC/EXE/ALLDROP") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH/TRC/EXE/ALLDROP", {$sformatf("Phase '%0s' (id=%0d) ", phase.get_full_name(), phase.get_inst_id()),"PHASE EXIT ALL_DROPPED"}, UVM_DEBUG, "t/uvm/src/base/uvm_phase_hopper.svh", 515, "", 1); end end end else begin if (uvm_phase::m_phase_trace) begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH/TRC/SKIP") >= UVM_LOW) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH/TRC/SKIP") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH/TRC/SKIP", {$sformatf("Phase '%0s' (id=%0d) ", phase.get_full_name(), phase.get_inst_id()),"No objections raised, skipping phase"}, UVM_LOW, "t/uvm/src/base/uvm_phase_hopper.svh", 518, "", 1); end end end phase.wait_for_self_and_siblings_to_drop() ; do_ready_to_end = 1; while (do_ready_to_end) begin uvm_wait_for_nba_region(); if (uvm_phase::m_phase_trace) begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH_READY_TO_END") >= UVM_DEBUG) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH_READY_TO_END") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH_READY_TO_END", {$sformatf("Phase '%0s' (id=%0d) ", phase.get_full_name(), phase.get_inst_id()),"PHASE READY TO END"}, UVM_DEBUG, "t/uvm/src/base/uvm_phase_hopper.svh", 530, "", 1); end end ready_to_end_count++; if (uvm_phase::m_phase_trace) begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH_READY_TO_END_CB") >= UVM_HIGH) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH_READY_TO_END_CB") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH_READY_TO_END_CB", {$sformatf("Phase '%0s' (id=%0d) ", phase.get_full_name(), phase.get_inst_id()),"CALLING READY_TO_END CB"}, UVM_HIGH, "t/uvm/src/base/uvm_phase_hopper.svh", 532, "", 1); end end phase.set_state(UVM_PHASE_READY_TO_END); if (imp != null) begin traverse_on(imp, null, phase, UVM_PHASE_READY_TO_END); end uvm_wait_for_nba_region(); phase.wait_for_self_and_siblings_to_drop(); do_ready_to_end = (phase.get_state() == UVM_PHASE_EXECUTING) && (ready_to_end_count < phase.get_max_ready_to_end_iterations()) ; end end begin if (phase.get_name() == "run") begin string delay_type; time delay_time; uvm_object objectors[$]; if (top.phase_timeout == 0) begin wait(top.phase_timeout != 0); end if (uvm_phase::m_phase_trace) begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH/TRC/TO_WAIT") >= UVM_HIGH) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH/TRC/TO_WAIT") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH/TRC/TO_WAIT", {$sformatf("Phase '%0s' (id=%0d) ", phase.get_full_name(), phase.get_inst_id()),$sformatf("STARTING PHASE TIMEOUT WATCHDOG (timeout == %t)", top.phase_timeout)}, UVM_HIGH, "t/uvm/src/base/uvm_phase_hopper.svh", 560, "", 1); end end #(top.phase_timeout); if ($time == 9200s) begin delay_type = "Default"; delay_time = 9200s; end else begin delay_type = "Explicit"; delay_time = top.phase_timeout; end if (uvm_phase::m_phase_trace) begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH/TRC/TIMEOUT") >= UVM_LOW) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH/TRC/TIMEOUT") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH/TRC/TIMEOUT", {$sformatf("Phase '%0s' (id=%0d) ", phase.get_full_name(), phase.get_inst_id()),"PHASE TIMEOUT WATCHDOG EXPIRED"}, UVM_LOW, "t/uvm/src/base/uvm_phase_hopper.svh", 571, "", 1); end end m_objection.get_objectors(objectors); foreach (objectors[i]) begin uvm_phase p; if ($cast(p, objectors[i])) begin uvm_objection p_done; p_done = p.get_objection(); if ((p_done != null) && (p_done.get_objection_total() > 0)) begin if (uvm_phase::m_phase_trace) begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH/TRC/TIMEOUT/OBJCTN") >= UVM_LOW) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH/TRC/TIMEOUT/OBJCTN") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH/TRC/TIMEOUT/OBJCTN", {$sformatf("Phase '%0s' (id=%0d) ", phase.get_full_name(), phase.get_inst_id()),$sformatf("Phase '%s' has outstanding objections:\n%s", p.get_full_name(), p_done.convert2string())}, UVM_LOW, "t/uvm/src/base/uvm_phase_hopper.svh", 582, "", 1); end end end end end begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "PH_TIMEOUT") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "PH_TIMEOUT") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("PH_TIMEOUT", $sformatf("%s timeout of %0t hit, indicating a probable testbench issue", delay_type, delay_time), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_phase_hopper.svh", 590, "", 1); end end end else begin wait (0); end end join_any disable fork; end join end end endtask : execute_phase task uvm_phase_hopper::end_phase(uvm_phase phase); if (phase.get_phase_type() == UVM_PHASE_NODE) begin uvm_phase_state prev_state; uvm_phase imp; prev_state = phase.get_state(); imp = phase.get_imp(); if(phase.m_premature_end) begin uvm_phase jump_phase; jump_phase = phase.get_jump_target(); if(jump_phase != null) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH_JUMP") >= UVM_MEDIUM) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH_JUMP") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH_JUMP", $sformatf("phase %s (schedule %s, domain %s) is jumping to phase %s", phase.get_name(), phase.get_schedule_name(), phase.get_domain_name(), jump_phase.get_name()), UVM_MEDIUM, "t/uvm/src/base/uvm_phase_hopper.svh", 628, "", 1); end end end else begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH_JUMP") >= UVM_MEDIUM) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH_JUMP") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH_JUMP", $sformatf("phase %s (schedule %s, domain %s) is ending prematurely", phase.get_name(), phase.get_schedule_name(), phase.get_domain_name()), UVM_MEDIUM, "t/uvm/src/base/uvm_phase_hopper.svh", 636, "", 1); end end end wait_for_waiters(phase, prev_state); if (uvm_phase::m_phase_trace) begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH_END") >= UVM_HIGH) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH_END") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH_END", {$sformatf("Phase '%0s' (id=%0d) ", phase.get_full_name(), phase.get_inst_id()),"ENDING PHASE PREMATURELY"}, UVM_HIGH, "t/uvm/src/base/uvm_phase_hopper.svh", 640, "", 1); end end end else begin uvm_task_phase task_phase; if (!$cast(task_phase, phase.get_imp())) begin phase.m_wait_for_pred(); end end if (uvm_phase::m_phase_trace) begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH_END") >= UVM_HIGH) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH_END") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH_END", {$sformatf("Phase '%0s' (id=%0d) ", phase.get_full_name(), phase.get_inst_id()),"ENDING PHASE"}, UVM_HIGH, "t/uvm/src/base/uvm_phase_hopper.svh", 658, "", 1); end end phase.set_state(UVM_PHASE_ENDED); if (imp != null) begin traverse_on(imp, null, phase, UVM_PHASE_ENDED); end wait_for_waiters(phase, prev_state); end endtask : end_phase task uvm_phase_hopper::cleanup_phase(uvm_phase phase); if (phase.get_phase_type() == UVM_PHASE_NODE) begin uvm_objection phase_done; uvm_phase_state prev_state; prev_state = phase.get_state(); if(phase.m_premature_end) begin phase.set_state(UVM_PHASE_JUMPING); end else begin phase.set_state(UVM_PHASE_CLEANUP); end if (phase.m_phase_proc != null) begin phase.m_phase_proc.kill(); phase.m_phase_proc = null; end wait_for_waiters(phase, prev_state); phase_done = phase.get_objection(); if (phase_done != null) begin phase_done.clear(); end end endtask : cleanup_phase task uvm_phase_hopper::finish_phase(uvm_phase phase); uvm_objection phase_done; uvm_phase jump_phase; uvm_phase_state prev_state; phase_done = phase.get_objection(); jump_phase = phase.get_jump_target(); prev_state = phase.get_state(); if(jump_phase != null) begin if(phase.is_jumping_forward()) begin phase.clear_successors(UVM_PHASE_DONE,jump_phase); end jump_phase.clear_successors(); phase.set_jump_phase(null); end else begin if (uvm_phase::m_phase_trace) begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "PH/TRC/DONE") >= UVM_LOW) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "PH/TRC/DONE") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("PH/TRC/DONE", {$sformatf("Phase '%0s' (id=%0d) ", phase.get_full_name(), phase.get_inst_id()),"Completed phase"}, UVM_LOW, "t/uvm/src/base/uvm_phase_hopper.svh", 730, "", 1); end end phase.set_state(UVM_PHASE_DONE); phase.m_phase_proc = null; end wait_for_waiters(phase, prev_state); begin if (phase_done != null) begin phase_done.clear(); end end if(jump_phase != null) begin schedule_phase(jump_phase, phase); end else begin uvm_phase::edges_t edges; uvm_phase succ_q[$]; phase.get_successors(edges); if (edges.size() != 0) begin uvm_phase succ; foreach (edges[succ]) begin succ_q.push_back(succ); end succ_q.sort with ( item.get_full_name() ); foreach (succ_q[i]) begin schedule_phase(succ_q[i], phase); end end end endtask : finish_phase task uvm_phase_hopper::process_phase(uvm_phase phase); sync_phase(phase); start_phase(phase); execute_phase(phase); end_phase(phase); cleanup_phase(phase); finish_phase(phase); endtask : process_phase task uvm_phase_hopper::wait_for_waiters(uvm_phase phase, uvm_phase_state prev_state); #0; endtask : wait_for_waiters function void uvm_phase_hopper::traverse_on(uvm_phase imp, uvm_component comp, uvm_phase node, uvm_phase_state state); if (comp == null) begin comp = uvm_root::get(); end imp.traverse(comp, node, state); endfunction : traverse_on function void uvm_phase_hopper::execute_on(uvm_phase imp, uvm_component comp, uvm_phase node); imp.execute(comp, node); endfunction : execute_on virtual class uvm_run_test_callback extends uvm_callback; extern function new( string name="uvm_run_test_callback"); virtual function void pre_run_test(); endfunction virtual function void post_run_test(); endfunction virtual function void pre_abort(); endfunction extern static function bit add( uvm_run_test_callback cb ); extern static function bit delete( uvm_run_test_callback cb ); extern static function void m_do_pre_run_test(); extern static function void m_do_post_run_test(); extern static function void m_do_pre_abort(); local static uvm_run_test_callback m_registered_cbs[$]; endclass : uvm_run_test_callback function uvm_run_test_callback::new( string name="uvm_run_test_callback"); super.new( name ); endfunction function bit uvm_run_test_callback::add( uvm_run_test_callback cb ); bit found; int unsigned i; if ( cb == null ) begin return 0; end found = 0; i = 0; while ( ! found && ( i < m_registered_cbs.size() ) ) begin if ( m_registered_cbs[ i ] == cb ) begin found = 1; end ++i; end if ( ! found ) begin m_registered_cbs.push_back( cb ); end return ! found; endfunction function bit uvm_run_test_callback::delete( uvm_run_test_callback cb ); int cb_idxs[$]; if ( cb == null ) begin return 0; end cb_idxs = m_registered_cbs.find_index( item ) with ( item == cb ); foreach ( cb_idxs[ i ] ) begin m_registered_cbs.delete( i ); end return ( cb_idxs.size() > 0 ); endfunction function void uvm_run_test_callback::m_do_pre_run_test(); foreach ( m_registered_cbs[ i ] ) begin m_registered_cbs[ i ].pre_run_test(); end endfunction function void uvm_run_test_callback::m_do_post_run_test(); foreach ( m_registered_cbs[ i ] ) begin m_registered_cbs[ i ].post_run_test(); end endfunction function void uvm_run_test_callback::m_do_pre_abort(); foreach ( m_registered_cbs[ i ] ) begin m_registered_cbs[ i ].pre_abort(); end endfunction typedef class uvm_objection; typedef class uvm_sequence_base; typedef class uvm_sequence_item; typedef class uvm_cmdline_set_verbosity; typedef class uvm_cmdline_set_action; typedef class uvm_cmdline_set_severity; virtual class uvm_component extends uvm_report_object; extern function new (string name, uvm_component parent); extern virtual function uvm_component get_parent (); extern virtual function string get_full_name (); extern function void get_children(ref uvm_component children[$]); extern function uvm_component get_child (string name); extern function int get_next_child (ref string name); extern function int get_first_child (ref string name); extern function int get_num_children (); extern function int has_child (string name); extern virtual function void set_name (string name); extern function uvm_component lookup (string name); extern function int unsigned get_depth(); extern virtual function void build_phase(uvm_phase phase); extern virtual function void connect_phase(uvm_phase phase); extern virtual function void end_of_elaboration_phase(uvm_phase phase); extern virtual function void start_of_simulation_phase(uvm_phase phase); extern virtual task run_phase(uvm_phase phase); extern virtual task pre_reset_phase(uvm_phase phase); extern virtual task reset_phase(uvm_phase phase); extern virtual task post_reset_phase(uvm_phase phase); extern virtual task pre_configure_phase(uvm_phase phase); extern virtual task configure_phase(uvm_phase phase); extern virtual task post_configure_phase(uvm_phase phase); extern virtual task pre_main_phase(uvm_phase phase); extern virtual task main_phase(uvm_phase phase); extern virtual task post_main_phase(uvm_phase phase); extern virtual task pre_shutdown_phase(uvm_phase phase); extern virtual task shutdown_phase(uvm_phase phase); extern virtual task post_shutdown_phase(uvm_phase phase); extern virtual function void extract_phase(uvm_phase phase); extern virtual function void check_phase(uvm_phase phase); extern virtual function void report_phase(uvm_phase phase); extern virtual function void final_phase(uvm_phase phase); extern virtual function void phase_started (uvm_phase phase); extern virtual function void phase_ready_to_end (uvm_phase phase); extern virtual function void phase_ended (uvm_phase phase); extern function void set_domain(uvm_domain domain, int hier=1); extern function uvm_domain get_domain(); extern virtual protected function void define_domain(uvm_domain domain); extern function void set_phase_imp(uvm_phase phase, uvm_phase imp, int hier=1); extern virtual function void build(); extern virtual function void connect(); extern virtual function void end_of_elaboration(); extern virtual function void start_of_simulation(); extern virtual task run(); extern virtual function void extract(); extern virtual function void check(); extern virtual function void report(); extern virtual task suspend (); extern virtual task resume (); extern virtual function void resolve_bindings (); extern function string massage_scope(string scope); extern function void check_config_usage (bit recurse=1); extern virtual function void set_config_int (string inst_name, string field_name, uvm_bitstream_t value); extern virtual function void set_config_string (string inst_name, string field_name, string value); extern virtual function void set_config_object (string inst_name, string field_name, uvm_object value, bit clone=1); extern virtual function bit get_config_int (string field_name, inout uvm_bitstream_t value); extern virtual function bit get_config_string (string field_name, inout string value); extern virtual function bit get_config_object (string field_name, inout uvm_object value, input bit clone=1); extern virtual function void apply_config_settings (bit verbose = 0); extern virtual function bit use_automatic_config(); extern function void print_config(bit recurse = 0, bit audit = 0); extern function void print_config_settings(string field="", uvm_component comp=null, bit recurse=0); extern function void print_config_with_audit(bit recurse = 0); static bit print_config_matches; static function bit get_print_config_matches() ; return print_config_matches; endfunction static function void set_print_config_matches(bit val) ; print_config_matches = val; endfunction virtual function void raised (uvm_objection objection, uvm_object source_obj, string description, int count); endfunction virtual function void dropped (uvm_objection objection, uvm_object source_obj, string description, int count); endfunction virtual task all_dropped (uvm_objection objection, uvm_object source_obj, string description, int count); endtask extern function uvm_component create_component (string requested_type_name, string name); extern function uvm_object create_object (string requested_type_name, string name=""); extern static function void set_type_override_by_type (uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace=1); extern function void set_inst_override_by_type(string relative_inst_path, uvm_object_wrapper original_type, uvm_object_wrapper override_type); extern static function void set_type_override(string original_type_name, string override_type_name, bit replace=1); extern function void set_inst_override(string relative_inst_path, string original_type_name, string override_type_name); extern function void print_override_info(string requested_type_name, string name=""); extern function void set_report_id_verbosity_hier (string id, int verbosity); extern function void set_report_severity_id_verbosity_hier(uvm_severity severity, string id, int verbosity); extern function void set_report_severity_action_hier (uvm_severity severity, uvm_action action); extern function void set_report_id_action_hier (string id, uvm_action action); extern function void set_report_severity_id_action_hier(uvm_severity severity, string id, uvm_action action); extern function void set_report_default_file_hier (UVM_FILE file); extern function void set_report_severity_file_hier (uvm_severity severity, UVM_FILE file); extern function void set_report_id_file_hier (string id, UVM_FILE file); extern function void set_report_severity_id_file_hier(uvm_severity severity, string id, UVM_FILE file); extern function void set_report_verbosity_level_hier (int verbosity); virtual function void pre_abort; endfunction extern function void accept_tr (uvm_transaction tr, time accept_time = 0); extern virtual protected function void do_accept_tr (uvm_transaction tr); extern function int begin_tr (uvm_transaction tr, string stream_name="main", string label="", string desc="", time begin_time=0, int parent_handle=0); extern virtual protected function void do_begin_tr (uvm_transaction tr, string stream_name, int tr_handle); extern function void end_tr (uvm_transaction tr, time end_time=0, bit free_handle=1); extern virtual protected function void do_end_tr (uvm_transaction tr, int tr_handle); extern function int record_error_tr (string stream_name="main", uvm_object info=null, string label="error_tr", string desc="", time error_time=0, bit keep_active=0); extern function int record_event_tr (string stream_name="main", uvm_object info=null, string label="event_tr", string desc="", time event_time=0, bit keep_active=0); extern virtual function uvm_tr_stream get_tr_stream(string name, string stream_type_name=""); extern virtual function void free_tr_stream(uvm_tr_stream stream); bit print_enabled = 1; extern virtual function void do_execute_op( uvm_field_op op ); typedef bit [1:0] config_mode_t; typedef enum config_mode_t {CONFIG_STRICT=2'b00, CONFIG_HIGHEST_PRECEDENCE=2'b01, CONFIG_CHECK_NAMES=2'b10} config_mode_e; localparam config_mode_t CONFIG_DEFAULT = CONFIG_CHECK_NAMES; extern virtual function config_mode_t apply_config_settings_mode(); uvm_tr_database tr_database; extern virtual function uvm_tr_database get_tr_database(); extern virtual function void set_tr_database(uvm_tr_database db); protected uvm_domain m_domain; uvm_phase m_phase_imps[uvm_phase]; uvm_phase m_current_phase; protected process m_phase_process; bit m_build_done; int m_phasing_active; extern function void set_local(uvm_resource_base rsrc) ; uvm_component m_parent; protected uvm_component m_children[string]; protected uvm_component m_children_by_handle[uvm_component]; extern protected virtual function bit m_add_child(uvm_component child); extern local virtual function void m_set_full_name(); extern function void do_resolve_bindings(); extern function void do_flush(); extern virtual function void flush (); extern local function void m_extract_name(string name , output string leaf , output string remainder ); extern virtual function uvm_object create (string name=""); extern virtual function uvm_object clone (); local uvm_tr_stream m_streams[string][string]; local uvm_recorder m_tr_h[uvm_transaction]; extern protected function int m_begin_tr (uvm_transaction tr, int parent_handle=0, string stream_name="main", string label="", string desc="", time begin_time=0); string m_name; typedef uvm_abstract_component_registry#(uvm_component, "uvm_component") type_id; static function string type_name(); return "uvm_component"; endfunction : type_name virtual function string get_type_name(); return "uvm_component"; endfunction : get_type_name protected uvm_event_pool event_pool; int unsigned recording_detail = UVM_NONE; extern virtual function bit get_recording_enabled(); extern virtual function void set_recording_enabled(bit enabled); extern virtual function void set_recording_enabled_hier (bit enabled); extern function void do_print(uvm_printer printer); extern function void m_set_cl_msg_args; extern function void m_set_cl_verb; extern function void m_set_cl_action; extern function void m_set_cl_sev; extern function void m_apply_verbosity_settings(uvm_phase phase); uvm_cmdline_set_verbosity m_verbosity_settings[$]; extern function void m_do_pre_abort; uvm_resource_base m_unsupported_resource_base = null; extern function void m_unsupported_set_local(uvm_resource_base rsrc); extern function int begin_child_tr (uvm_transaction tr, int parent_handle=0, string stream_name="main", string label="", string desc="", time begin_time=0); endclass : uvm_component typedef class uvm_cmdline_processor; typedef class uvm_component_proxy; typedef class uvm_top_down_visitor_adapter; typedef class uvm_process_guard_base; typedef class uvm_report_message; typedef class uvm_report_object; typedef class uvm_report_handler; typedef class uvm_default_report_server; typedef class uvm_cmdline_verbosity; class uvm_root extends uvm_component; extern static function uvm_root get(); uvm_cmdline_processor clp; virtual function string get_type_name(); return "uvm_root"; endfunction extern virtual task run_test (string test_name=""); virtual function void die(); uvm_report_server l_rs; if (get_core_state() inside {UVM_CORE_PRE_ABORT,UVM_CORE_ABORTED}) begin return; end l_rs = uvm_report_server::get_server(); m_uvm_core_state.push_front(UVM_CORE_PRE_ABORT); m_do_pre_abort(); uvm_run_test_callback::m_do_pre_abort(); m_do_cmdline_checks(); l_rs.report_summarize(); m_uvm_core_state.push_front(UVM_CORE_ABORTED); $finish; endfunction extern function void set_timeout(time timeout, bit overridable=1); bit finish_on_completion = 1; virtual function bit get_finish_on_completion(); return finish_on_completion; endfunction : get_finish_on_completion virtual function void set_finish_on_completion(bit f); finish_on_completion = f; endfunction : set_finish_on_completion uvm_component top_levels[$]; extern function uvm_component find (string comp_match); extern function void find_all (string comp_match, ref uvm_component comps[$], input uvm_component comp=null); extern function void print_topology (uvm_printer printer=null); bit enable_print_topology = 0; extern function void set_enable_print_topology (bit enable); extern function bit get_enable_print_topology (); time phase_timeout = 9200s; extern function void m_find_all_recurse(string comp_match, ref uvm_component comps[$], input uvm_component comp=null); extern protected function new (); extern protected virtual function bit m_add_child (uvm_component child); extern function void build_phase(uvm_phase phase); extern local function void m_do_cl_init(); extern local function void m_do_verbosity_settings(); extern local function void m_do_cmdline_checks(); extern local function void m_do_timeout_settings(); extern local function void m_do_factory_settings(); extern local function void m_process_inst_override(string ovr); extern local function void m_process_type_override(string ovr); extern local function void m_do_config_settings(); extern local function void m_do_max_quit_settings(); extern local function void m_do_dump_args(); extern local function void m_process_config(string cfg, bit is_int, is_bitstream); extern local function void m_process_default_sequence(string cfg); local string m_uvm_verbosity_settings[$]; local uvm_cmdline_set_verbosity m_time_settings[$]; extern function void m_check_verbosity(); extern function void m_check_uvm_field_flag_size(); extern virtual function void report_header(UVM_FILE file = 0); static local uvm_root m_inst; extern virtual task run_phase (uvm_phase phase); function void phase_started(uvm_phase phase); if (phase == end_of_elaboration_ph) begin do_resolve_bindings(); if (enable_print_topology) begin print_topology(); end begin uvm_report_server srvr; srvr = uvm_report_server::get_server(); if(srvr.get_severity_count(UVM_ERROR) > 0) begin uvm_report_fatal("BUILDERR", "stopping due to build errors", UVM_NONE); end end end endfunction bit m_phase_all_done; extern static function uvm_root m_uvm_get_root(); static local bit m_relnotes_done=0; function void end_of_elaboration_phase(uvm_phase phase); uvm_component_proxy p = new("proxy"); uvm_top_down_visitor_adapter#(uvm_component) adapter = new("adapter"); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_visitor#(uvm_component) v = cs.get_component_visitor(); adapter.accept(this, v, p); endfunction endclass uvm_root uvm_top; function uvm_root uvm_root::get(); uvm_coreservice_t cs = uvm_coreservice_t::get(); return cs.get_root(); endfunction function uvm_root::new(); uvm_report_handler rh; super.new("__top__", null); rh = new("reporter"); set_report_handler(rh); if (m_inst != null) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = m_inst.uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "UVM/ROOT/MULTI") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "UVM/ROOT/MULTI") != uvm_pkg::UVM_NO_ACTION)) begin _local_report_object_.uvm_report_fatal("UVM/ROOT/MULTI", "Attempting to construct multiple roots", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_root.svh", 401, "", 1); end end return; end m_inst = this; clp = uvm_cmdline_processor::get_inst(); m_do_cl_init(); m_set_cl_msg_args(); endfunction function uvm_root uvm_root::m_uvm_get_root(); if (m_inst == null) begin uvm_root top; top = new(); uvm_top = top; if (top != m_inst) begin return null; end top.m_domain = uvm_domain::get_uvm_domain(); end if (m_inst != uvm_top) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = m_inst.uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "UVM/BAD_TOP") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "UVM/BAD_TOP") != uvm_pkg::UVM_NO_ACTION)) begin _local_report_object_.uvm_report_fatal("UVM/BAD_TOP", "The uvm_top variable has been overwritten outside of uvm_root!", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_root.svh", 433, "", 1); end end end return m_inst; endfunction function void uvm_root::report_header(UVM_FILE file = 0); string q[$]; uvm_report_server srvr; uvm_cmdline_processor clp; string args[$]; srvr = uvm_report_server::get_server(); clp = uvm_cmdline_processor::get_inst(); if (clp.get_arg_matches("+UVM_NO_RELNOTES", args)) begin return; end if (!m_relnotes_done) begin q.push_back("\n *********** IMPORTANT RELEASE NOTES ************\n"); m_relnotes_done = 1; q.push_back("\n This implementation of the UVM Library deviates from the 1800.2-2020\n"); q.push_back(" standard. See the DEVIATIONS.md file contained in the release\n"); q.push_back(" for more details.\n"); end q.push_back("\n----------------------------------------------------------------\n"); q.push_back({uvm_revision_string(),"\n"}); q.push_back("\n"); q.push_back("All copyright owners for this kit are listed in NOTICE.txt\n"); q.push_back("All Rights Reserved Worldwide\n"); q.push_back("----------------------------------------------------------------\n"); if(m_relnotes_done) begin q.push_back("\n (Specify +UVM_NO_RELNOTES to turn off this notice)\n"); end begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "UVM/RELNOTES") >= UVM_LOW) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "UVM/RELNOTES") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("UVM/RELNOTES", uvm_pkg::m_uvm_string_queue_join(q), UVM_LOW, "t/uvm/src/base/uvm_root.svh", 476, "", 1); end end endfunction task uvm_root::run_test(string test_name=""); uvm_report_server l_rs; uvm_factory factory; bit testname_plusarg; int test_name_count; string test_names[$]; string msg; uvm_component uvm_test_top; process phase_runner_proc; uvm_run_test_callback::m_do_pre_run_test(); factory=uvm_factory::get(); m_uvm_core_state.push_front(UVM_CORE_PRE_RUN); testname_plusarg = 0; uvm_objection::m_init_objections(); uvm_process_guard_base::m_init_process_guards(); m_do_dump_args(); begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "NO_DPI_USED") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "NO_DPI_USED") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("NO_DPI_USED", "We are thinking of removing support for UVM_NO_DPI. Please try this test without it and evaluate the impact", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_root.svh", 549, "", 1); end end if ($value$plusargs("UVM_TESTNAME=%s", test_name)) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "NO_DPI_TSTNAME") >= UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "NO_DPI_TSTNAME") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("NO_DPI_TSTNAME", "UVM_NO_DPI defined--getting UVM_TESTNAME directly, without DPI", UVM_NONE, "t/uvm/src/base/uvm_root.svh", 552, "", 1); end end testname_plusarg = 1; end if (test_name != "") begin if(m_children.exists("uvm_test_top")) begin uvm_report_fatal("TTINST", "An uvm_test_top already exists via a previous call to run_test", UVM_NONE); #0; end $cast(uvm_test_top, factory.create_component_by_name(test_name, "", "uvm_test_top", null)); if (uvm_test_top == null) begin msg = testname_plusarg ? {"command line +UVM_TESTNAME=",test_name} : {"call to run_test(",test_name,")"}; uvm_report_fatal("INVTST", {"Requested test from ",msg, " not found." }, UVM_NONE); end end if (m_children.num() == 0) begin uvm_report_fatal("NOCOMP", {"No components instantiated. You must either instantiate", " at least one component before calling run_test or use", " run_test to do so. To run a test using run_test,", " use +UVM_TESTNAME or supply the test name in", " the argument to run_test(). Exiting simulation."}, UVM_NONE); return; end begin if(test_name=="") begin uvm_report_info("RNTST", "Running test ...", UVM_LOW); end else if (test_name == uvm_test_top.get_type_name()) begin uvm_report_info("RNTST", {"Running test ",test_name,"..."}, UVM_LOW); end else begin uvm_report_info("RNTST", {"Running test ",uvm_test_top.get_type_name()," (via factory override for test \"",test_name,"\")..."}, UVM_LOW); end end fork begin uvm_phase_hopper hopper; hopper = uvm_phase_hopper::get_global_hopper(); m_uvm_core_state.push_front(UVM_CORE_RUNNING); hopper.run_phases(); end join m_uvm_core_state.push_front(UVM_CORE_POST_RUN); l_rs = uvm_report_server::get_server(); uvm_run_test_callback::m_do_post_run_test(); m_do_cmdline_checks(); l_rs.report_summarize(); m_uvm_core_state.push_front(UVM_CORE_FINISHED); if (get_finish_on_completion()) begin $finish; end endtask function void uvm_root::find_all(string comp_match, ref uvm_component comps[$], input uvm_component comp=null); if (comp==null) begin comp = this; end m_find_all_recurse(comp_match, comps, comp); endfunction function uvm_component uvm_root::find (string comp_match); uvm_component comp_list[$]; find_all(comp_match,comp_list); if (comp_list.size() > 1) begin uvm_report_warning("MMATCH", $sformatf("Found %0d components matching '%s'. Returning first match, %0s.", comp_list.size(),comp_match,comp_list[0].get_full_name()), UVM_NONE); end if (comp_list.size() == 0) begin uvm_report_warning("CMPNFD", {"Component matching '",comp_match, "' was not found in the list of uvm_components"}, UVM_NONE); return null; end return comp_list[0]; endfunction function void uvm_root::print_topology(uvm_printer printer=null); if (m_children.num()==0) begin uvm_report_warning("EMTCOMP", "print_topology - No UVM components to print.", UVM_NONE); return; end if (printer==null) begin printer = uvm_printer::get_default(); end begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "UVMTOP") >= UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "UVMTOP") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("UVMTOP", "UVM testbench topology:", UVM_NONE, "t/uvm/src/base/uvm_root.svh", 699, "", 1); end end print(printer) ; endfunction function void uvm_root::set_timeout(time timeout, bit overridable=1); static bit m_uvm_timeout_overridable = 1; if (m_uvm_timeout_overridable == 0) begin uvm_report_info("NOTIMOUTOVR", $sformatf("The global timeout setting of %0d is not overridable to %0d due to a previous setting.", phase_timeout, timeout), UVM_NONE); return; end m_uvm_timeout_overridable = overridable; phase_timeout = timeout; endfunction function void uvm_root::m_find_all_recurse(string comp_match, ref uvm_component comps[$], input uvm_component comp=null); string name; if (comp.get_first_child(name)) begin do begin this.m_find_all_recurse(comp_match, comps, comp.get_child(name)); end while (comp.get_next_child(name)); end if (uvm_is_match(comp_match, comp.get_full_name()) && comp.get_name() != "") begin comps.push_back(comp); end endfunction function bit uvm_root::m_add_child (uvm_component child); if(super.m_add_child(child)) begin if(child.get_name() == "uvm_test_top") begin top_levels.push_front(child); end else begin top_levels.push_back(child); end return 1; end else begin return 0; end endfunction function void uvm_root::build_phase(uvm_phase phase); super.build_phase(phase); m_do_verbosity_settings(); m_do_timeout_settings(); m_do_factory_settings(); m_do_config_settings(); m_do_max_quit_settings(); endfunction function void uvm_root::m_do_cl_init(); string values[$]; string args[$]; string message; uvm_cmdline_set_verbosity::init(this); foreach(uvm_cmdline_set_verbosity::settings[i]) begin if (uvm_cmdline_set_verbosity::settings[i].phase == "time" && uvm_cmdline_set_verbosity::settings[i].offset != 0) begin m_time_settings.push_back(uvm_cmdline_set_verbosity::settings[i]); end end uvm_cmdline_set_action::init(this); uvm_cmdline_set_severity::init(this); endfunction : m_do_cl_init function void uvm_root::m_do_verbosity_settings(); string set_verbosity_settings[$]; string split_vals[$]; uvm_verbosity tmp_verb; fork begin time last_time = 0; if (m_time_settings.size() > 0) begin m_time_settings.sort() with ( item.offset ); end foreach(m_time_settings[i]) begin uvm_component comps[$]; #(m_time_settings[i].offset - last_time); find_all(m_time_settings[i].comp,comps); last_time = m_time_settings[i].offset; if(m_time_settings[i].id == "_ALL_") begin foreach(comps[j]) begin m_time_settings[i].used[comps[j]] = 1; comps[j].set_report_verbosity_level(m_time_settings[i].verbosity); end end else begin foreach(comps[j]) begin m_time_settings[i].used[comps[j]] = 1; comps[j].set_report_id_verbosity(m_time_settings[i].id, m_time_settings[i].verbosity); end end end end join_none endfunction function void uvm_root::m_do_cmdline_checks(); string dump_args[$]; uvm_cmdline_set_verbosity::check(this); if(clp.get_arg_matches("+UVM_DUMP_REPORT_ARGS", dump_args)) begin string msgs[$]; msgs.push_back("\n!!! UVM_CMDLINE_NO_DPI IS DEFINED !!!"); msgs.push_back(uvm_cmdline_verbosity::dump()); msgs.push_back(uvm_cmdline_set_verbosity::dump()); msgs.push_back(uvm_cmdline_set_action::dump()); msgs.push_back(uvm_cmdline_set_severity::dump()); uvm_report_info("REPORTARGS", $sformatf("\n--- UVM Reporting Argument Summary ---\n%s\n", uvm_pkg::m_uvm_string_queue_join(msgs)), UVM_NONE); end endfunction function void uvm_root::m_do_timeout_settings(); string timeout_settings[$]; string timeout; string split_timeout[$]; int timeout_count; time timeout_int; string override_spec; timeout_count = clp.get_arg_values("+UVM_TIMEOUT=", timeout_settings); if (timeout_count == 0) begin return; end else begin timeout = timeout_settings[0]; if (timeout_count > 1) begin string timeout_list; string sep; for (int i = 0; i < timeout_settings.size(); i++) begin if (i != 0) begin sep = "; "; end timeout_list = {timeout_list, sep, timeout_settings[i]}; end uvm_report_warning("MULTTIMOUT", $sformatf("Multiple (%0d) +UVM_TIMEOUT arguments provided on the command line. '%s' will be used. Provided list: %s.", timeout_count, timeout, timeout_list), UVM_NONE); end uvm_report_info("TIMOUTSET", $sformatf("'+UVM_TIMEOUT=%s' provided on the command line is being applied.", timeout), UVM_NONE); void'($sscanf(timeout,"%d,%s",timeout_int,override_spec)); case(override_spec) "YES" : begin set_timeout(timeout_int, 1); end "NO" : begin set_timeout(timeout_int, 0); end default : begin set_timeout(timeout_int, 1); end endcase end endfunction function void uvm_root::m_do_factory_settings(); string args[$]; void'(clp.get_arg_matches("/^\\+(UVM_SET_INST_OVERRIDE|uvm_set_inst_override)=/",args)); foreach(args[i]) begin m_process_inst_override(args[i].substr(23, args[i].len()-1)); end void'(clp.get_arg_matches("/^\\+(UVM_SET_TYPE_OVERRIDE|uvm_set_type_override)=/",args)); foreach(args[i]) begin m_process_type_override(args[i].substr(23, args[i].len()-1)); end endfunction function void uvm_root::m_process_inst_override(string ovr); string split_val[$]; uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); uvm_string_split(ovr, ",", split_val); if(split_val.size() != 3 ) begin uvm_report_error("UVM_CMDLINE_PROC", {"Invalid setting for +uvm_set_inst_override=", ovr, ", setting must specify ,,"}, UVM_NONE); return; end uvm_report_info("INSTOVR", {"Applying instance override from the command line: +uvm_set_inst_override=", ovr}, UVM_NONE); factory.set_inst_override_by_name(split_val[0], split_val[1], split_val[2]); endfunction function void uvm_root::m_process_type_override(string ovr); string split_val[$]; int replace=1; uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); uvm_string_split(ovr, ",", split_val); if(split_val.size() > 3 || split_val.size() < 2) begin uvm_report_error("UVM_CMDLINE_PROC", {"Invalid setting for +uvm_set_type_override=", ovr, ", setting must specify ,[,]"}, UVM_NONE); return; end if(split_val.size() == 3) begin if(split_val[2]=="0") begin replace = 0; end else if (split_val[2] == "1") begin replace = 1; end else begin uvm_report_error("UVM_CMDLINE_PROC", {"Invalid replace arg for +uvm_set_type_override=", ovr ," value must be 0 or 1"}, UVM_NONE); return; end end uvm_report_info("UVM_CMDLINE_PROC", {"Applying type override from the command line: +uvm_set_type_override=", ovr}, UVM_NONE); factory.set_type_override_by_name(split_val[0], split_val[1], replace); endfunction function void uvm_root::m_process_config(string cfg, bit is_int, is_bitstream); uvm_bitstream_t v; string split_val[$]; uvm_root m_uvm_top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); m_uvm_top = cs.get_root(); uvm_string_split(cfg, ",", split_val); if(split_val.size() == 1) begin uvm_report_error("UVM_CMDLINE_PROC", {"Invalid +uvm_set_config command\"", cfg, "\" missing field and value: component is \"", split_val[0], "\""}, UVM_NONE); return; end if(split_val.size() == 2) begin uvm_report_error("UVM_CMDLINE_PROC", {"Invalid +uvm_set_config command\"", cfg, "\" missing value: component is \"", split_val[0], "\" field is \"", split_val[1], "\""}, UVM_NONE); return; end if(split_val.size() > 3) begin uvm_report_error("UVM_CMDLINE_PROC", $sformatf("Invalid +uvm_set_config command\"%s\" : expected only 3 fields (component, field and value).", cfg), UVM_NONE); return; end if(is_int) begin if(split_val[2].len() > 2) begin string base, extval; base = split_val[2].substr(0,1); extval = split_val[2].substr(2,split_val[2].len()-1); case(base) "'b" : begin v = extval.atobin(); end "0b" : begin v = extval.atobin(); end "'o" : begin v = extval.atooct(); end "'d" : begin v = extval.atoi(); end "'h" : begin v = extval.atohex(); end "'x" : begin v = extval.atohex(); end "0x" : begin v = extval.atohex(); end default : begin v = split_val[2].atoi(); end endcase end else begin v = split_val[2].atoi(); end uvm_report_info("UVM_CMDLINE_PROC", {"Applying config setting from the command line: +uvm_set_config_int=", cfg}, UVM_NONE); uvm_config_int::set(m_uvm_top, split_val[0], split_val[1], v); end else if(is_bitstream) begin int success ; success = uvm_bit_vector_utils#(uvm_bitstream_t)::from_string(split_val[2], v); if (success == 1) begin uvm_report_info("UVM_CMDLINE_PROC", {"Applying config setting from the command line: +uvm_set_config_bitstream=", cfg}, UVM_NONE); uvm_config_int::set(m_uvm_top, split_val[0], split_val[1], v); end end else begin uvm_report_info("UVM_CMDLINE_PROC", {"Applying config setting from the command line: +uvm_set_config_string=", cfg}, UVM_NONE); uvm_config_string::set(m_uvm_top, split_val[0], split_val[1], split_val[2]); end endfunction function void uvm_root::m_process_default_sequence(string cfg); string split_val[$]; uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_root m_uvm_top = cs.get_root(); uvm_factory f = cs.get_factory(); uvm_object_wrapper w; uvm_string_split(cfg, ",", split_val); if(split_val.size() == 1) begin uvm_report_error("UVM_CMDLINE_PROC", {"Invalid +uvm_set_default_sequence command\"", cfg, "\" missing phase and type: sequencer is \"", split_val[0], "\""}, UVM_NONE); return; end if(split_val.size() == 2) begin uvm_report_error("UVM_CMDLINE_PROC", {"Invalid +uvm_set_default_sequence command\"", cfg, "\" missing type: sequencer is \"", split_val[0], "\" phase is \"", split_val[1], "\""}, UVM_NONE); return; end if(split_val.size() > 3) begin uvm_report_error("UVM_CMDLINE_PROC", $sformatf("Invalid +uvm_set_default_sequence command\"%s\" : expected only 3 fields (sequencer, phase and type).", cfg), UVM_NONE); return; end w = f.find_wrapper_by_name(split_val[2]); if (w == null) begin uvm_report_error("UVM_CMDLINE_PROC", $sformatf("Invalid type '%s' provided to +uvm_set_default_sequence", split_val[2]), UVM_NONE); return; end else begin uvm_report_info("UVM_CMDLINE_PROC", {"Setting default sequence from the command line: +uvm_set_default_sequence=", cfg}, UVM_NONE); uvm_config_db#(uvm_object_wrapper)::set(this, {split_val[0], ".", split_val[1]}, "default_sequence", w); end endfunction : m_process_default_sequence function void uvm_root::m_do_config_settings(); string args[$]; void'(clp.get_arg_matches("/^\\+(UVM_SET_CONFIG_INT|uvm_set_config_int)=/",args)); foreach(args[i]) begin m_process_config(args[i].substr(20, args[i].len()-1), 1, 0); end void'(clp.get_arg_matches("/^\\+(UVM_SET_CONFIG_BITSTREAM|uvm_set_config_bitstream)=/",args)); foreach(args[i]) begin m_process_config(args[i].substr(26, args[i].len()-1), 0, 1); end void'(clp.get_arg_matches("/^\\+(UVM_SET_CONFIG_STRING|uvm_set_config_string)=/",args)); foreach(args[i]) begin m_process_config(args[i].substr(23, args[i].len()-1), 0, 0); end void'(clp.get_arg_matches("/^\\+(UVM_SET_DEFAULT_SEQUENCE|uvm_set_default_sequence)=/", args)); foreach(args[i]) begin m_process_default_sequence(args[i].substr(26, args[i].len()-1)); end endfunction function void uvm_root::m_do_max_quit_settings(); uvm_report_server srvr; string max_quit_settings[$]; int max_quit_count; string max_quit; string split_max_quit[$]; int max_quit_int; int i; string tmp; srvr = uvm_report_server::get_server(); max_quit_count = clp.get_arg_values("+UVM_MAX_QUIT_COUNT=", max_quit_settings); if (max_quit_count == 0) begin return; end else begin max_quit = max_quit_settings[0]; if (max_quit_count > 1) begin string max_quit_list; string sep; for (int i = 0; i < max_quit_settings.size(); i++) begin if (i != 0) begin sep = "; "; end max_quit_list = {max_quit_list, sep, max_quit_settings[i]}; end uvm_report_warning("MULTMAXQUIT", $sformatf("Multiple (%0d) +UVM_MAX_QUIT_COUNT arguments provided on the command line. '%s' will be used. Provided list: %s.", max_quit_count, max_quit, max_quit_list), UVM_NONE); end uvm_report_info("MAXQUITSET", $sformatf("'+UVM_MAX_QUIT_COUNT=%s' provided on the command line is being applied.", max_quit), UVM_NONE); uvm_string_split(max_quit, ",", split_max_quit); tmp = split_max_quit[0]; i = $sscanf(tmp,"%d", max_quit_int); case(split_max_quit[1]) "YES" : begin srvr.set_max_quit_count(max_quit_int, 1); end "NO" : begin srvr.set_max_quit_count(max_quit_int, 0); end default : begin srvr.set_max_quit_count(max_quit_int, 1); end endcase end endfunction function void uvm_root::m_do_dump_args(); string dump_args[$]; string all_args[$]; string out_string; if(clp.get_arg_matches("+UVM_DUMP_CMDLINE_ARGS", dump_args)) begin clp.get_args(all_args); foreach (all_args[idx]) begin uvm_report_info("DUMPARGS", $sformatf("idx=%0d arg=[%s]",idx,all_args[idx]), UVM_NONE); end end endfunction function void uvm_root::m_check_verbosity(); int verbosity = UVM_MEDIUM; uvm_cmdline_verbosity::init(this); uvm_cmdline_verbosity::check(this); if (uvm_cmdline_verbosity::settings.size() > 0) begin verbosity = uvm_cmdline_verbosity::settings[0].verbosity; end set_report_verbosity_level_hier(verbosity); endfunction function void uvm_root::m_check_uvm_field_flag_size(); if ( (UVM_FIELD_FLAG_RESERVED_BITS) < UVM_FIELD_FLAG_RESERVED_BITS ) begin uvm_report_fatal( "BAD_FIELD_FLAG_SZ", $sformatf( "Macro UVM_FIELD_FLAG_SIZE is set to %0d which is less than the required minimum of UVM_FIELD_FLAG_RESERVED_BITS (%0d).", UVM_FIELD_FLAG_RESERVED_BITS, UVM_FIELD_FLAG_RESERVED_BITS ) ); end endfunction task uvm_root::run_phase (uvm_phase phase); uvm_cmdline_set_action::check(this); uvm_cmdline_set_severity::check(this); if($time > 0) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "RUNPHSTIME") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "RUNPHSTIME") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("RUNPHSTIME", {"The run phase must start at time 0, current time is ", $sformatf("%0t", $realtime), ". No non-zero delays are allowed before ", "run_test(), and pre-run user defined phases may not consume ", "simulation time before the start of the run phase."}, uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_root.svh", 1291, "", 1); end end end endtask function void uvm_root::set_enable_print_topology (bit enable); enable_print_topology = enable; endfunction function bit uvm_root::get_enable_print_topology(); return enable_print_topology; endfunction function uvm_component::new (string name, uvm_component parent); string error_str; uvm_root top; uvm_coreservice_t cs; uvm_resource_pool rp; uvm_resource_types::rsrc_q_t rq; super.new(name); if (parent==null && name == "__top__") begin set_name(""); event_pool = new("event_pool"); return; end cs = uvm_coreservice_t::get(); top = cs.get_root(); begin uvm_phase bld; uvm_domain common; common = uvm_domain::get_common_domain(); bld = common.find(uvm_build_phase::get()); if (bld == null) begin uvm_report_fatal("COMP/INTERNAL", "attempt to find build phase object failed",UVM_NONE); end if (bld.get_state() == UVM_PHASE_DONE) begin uvm_report_fatal("ILLCRT", {"It is illegal to create a component ('", name,"' under '", (parent == null ? top.get_full_name() : parent.get_full_name()), "') after the build phase has ended."}, UVM_NONE); end end if (name == "") begin name.itoa(m_inst_count); name = {"COMP_", name}; end if(parent == this) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "THISPARENT") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "THISPARENT") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("THISPARENT", "cannot set the parent of a component to itself", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_component.svh", 1735, "", 1); end end end if (parent == null) begin parent = top; end if(uvm_report_enabled(UVM_MEDIUM+1, UVM_INFO, "NEWCOMP")) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "NEWCOMP") >= UVM_MEDIUM+1) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "NEWCOMP") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("NEWCOMP", {"Creating ", (parent==top?"uvm_top":parent.get_full_name()),".",name}, UVM_MEDIUM+1, "t/uvm/src/base/uvm_component.svh", 1746, "", 1); end end end if (parent.has_child(name) && this != parent.get_child(name)) begin if (parent == top) begin error_str = {"Name '",name,"' is not unique to other top-level ", "instances. If parent is a module, build a unique name by combining the ", "the module name and component name: $sformatf(\"\%m.\%s\",\"",name,"\")."}; begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "CLDEXT") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "CLDEXT") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("CLDEXT", error_str, uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_component.svh", 1754, "", 1); end end end else begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_FATAL, "CLDEXT") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_FATAL, "CLDEXT") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_fatal("CLDEXT", $sformatf("Cannot set '%s' as a child of '%s', %s", name, parent.get_full_name(), "which already has a child by that name."), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_component.svh", 1760, "", 1); end end end return; end m_parent = parent; set_name(name); if (!m_parent.m_add_child(this)) begin m_parent = null; end event_pool = new("event_pool"); m_domain = parent.m_domain; reseed(); rp = cs.get_resource_pool(); rq = rp.lookup_name(.scope(get_full_name()), .name("recording_detail"), .type_handle(null), .rpterr(0)); if (rq.size() > 0) begin uvm_resource_base rsrc; bit found; rp.sort_by_precedence(rq); do begin rsrc = rq.pop_front(); begin begin uvm_resource#(uvm_integral_t) __tmp_rsrc__; found = $cast(__tmp_rsrc__, rsrc); if (found) begin recording_detail = __tmp_rsrc__.read(this); end end if (!found) begin uvm_resource#(uvm_bitstream_t) __tmp_rsrc__; found = $cast(__tmp_rsrc__, rsrc); if (found) begin recording_detail = __tmp_rsrc__.read(this); end end if (!found) begin uvm_resource#(int) __tmp_rsrc__; found = $cast(__tmp_rsrc__, rsrc); if (found) begin recording_detail = __tmp_rsrc__.read(this); end end if (!found) begin uvm_resource#(int unsigned) __tmp_rsrc__; found = $cast(__tmp_rsrc__, rsrc); if (found) begin recording_detail = __tmp_rsrc__.read(this); end end end; end while (!found && (rq.size() > 0)); end m_rh.set_name(get_full_name()); set_report_verbosity_level(parent.get_report_verbosity_level()); m_set_cl_msg_args(); endfunction function bit uvm_component::m_add_child(uvm_component child); if (m_children.exists(child.get_name()) && m_children[child.get_name()] != child) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "BDCLD") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "BDCLD") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("BDCLD", $sformatf("A child with the name '%0s' (type=%0s) already exists.", child.get_name(), m_children[child.get_name()].get_type_name()), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_component.svh", 1817, "", 1); end end return 0; end if (m_children_by_handle.exists(child)) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "BDCHLD") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "BDCHLD") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("BDCHLD", $sformatf("A child with the name '%0s' %0s %0s'", child.get_name(), "already exists in parent under name '", m_children_by_handle[child].get_name()), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_component.svh", 1826, "", 1); end end return 0; end m_children[child.get_name()] = child; m_children_by_handle[child] = child; return 1; endfunction function void uvm_component::get_children(ref uvm_component children[$]); foreach(m_children[i]) begin children.push_back(m_children[i]); end endfunction function int uvm_component::get_first_child(ref string name); return m_children.first(name); endfunction function int uvm_component::get_next_child(ref string name); return m_children.next(name); endfunction function uvm_component uvm_component::get_child(string name); if (m_children.exists(name)) begin return m_children[name]; end begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "NOCHILD") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "NOCHILD") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("NOCHILD", {"Component with name '",name, "' is not a child of component '",get_full_name(),"'"}, uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_component.svh", 1882, "", 1); end end return null; endfunction function int uvm_component::has_child(string name); return m_children.exists(name); endfunction function int uvm_component::get_num_children(); return m_children.num(); endfunction function string uvm_component::get_full_name (); if(m_name == "") begin return get_name(); end else begin return m_name; end endfunction function uvm_component uvm_component::get_parent (); return m_parent; endfunction function void uvm_component::set_name (string name); if(m_name != "") begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "INVSTNM") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "INVSTNM") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("INVSTNM", $sformatf("It is illegal to change the name of a component. The component name will not be changed to \"%s\"", name), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_component.svh", 1935, "", 1); end end return; end super.set_name(name); m_set_full_name(); endfunction function void uvm_component::m_set_full_name(); uvm_root top; if ($cast(top, m_parent) || m_parent==null) begin m_name = get_name(); end else begin m_name = {m_parent.get_full_name(), ".", get_name()}; end foreach (m_children[c]) begin uvm_component tmp; tmp = m_children[c]; tmp.m_set_full_name(); end endfunction function uvm_component uvm_component::lookup( string name ); string leaf , remainder; uvm_component comp; uvm_root top; uvm_coreservice_t cs; int name_length; cs = uvm_coreservice_t::get(); top = cs.get_root(); comp = this; name_length = name.len(); for(int i = 0; i < name_length; i++) begin if((name.substr(i, (i+1)) == "..") || (name[i] == "*") || (name[i] == "?")) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "Lookup String Error") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "Lookup String Error") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("Lookup String Error", $sformatf("Malformed look up string: %s", name), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_component.svh", 1989, "", 1); end end return null; end end m_extract_name(name, leaf, remainder); if (leaf == "") begin comp = top; m_extract_name(remainder, leaf, remainder); end if (!comp.has_child(leaf)) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "Lookup Error") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "Lookup Error") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("Lookup Error", $sformatf("Cannot find child %0s",leaf), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_component.svh", 2003, "", 1); end end return null; end if( remainder != "" ) begin return comp.m_children[leaf].lookup(remainder); end return comp.m_children[leaf]; endfunction function int unsigned uvm_component::get_depth(); if(m_name == "") begin return 0; end get_depth = 1; foreach(m_name[i]) begin if(m_name[i] == ".") begin ++get_depth; end end endfunction function void uvm_component::m_extract_name(input string name , output string leaf , output string remainder ); int i , len; len = name.len(); for( i = 0; i < name.len(); i++ ) begin if( name[i] == "." ) begin break; end end if( i == len ) begin leaf = name; remainder = ""; return; end leaf = name.substr( 0 , i - 1 ); remainder = name.substr( i + 1 , len - 1 ); return; endfunction function void uvm_component::flush(); return; endfunction function void uvm_component::do_flush(); foreach( m_children[s] ) begin m_children[s].do_flush(); end flush(); endfunction function uvm_object uvm_component::create (string name =""); begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "ILLCRT") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "ILLCRT") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("ILLCRT", "create cannot be called on a uvm_component. Use create_component instead.", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_component.svh", 2100, "", 1); end end return null; endfunction function uvm_object uvm_component::clone (); begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "ILLCLN") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "ILLCLN") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("ILLCLN", $sformatf("Attempting to clone '%s'. Clone cannot be called on a uvm_component. The clone target variable will be set to null.", get_full_name()), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_component.svh", 2109, "", 1); end end return null; endfunction function void uvm_component::print_override_info (string requested_type_name, string name=""); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); factory.debug_create_by_name(requested_type_name, get_full_name(), name); endfunction function uvm_component uvm_component::create_component (string requested_type_name, string name); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); return factory.create_component_by_name(requested_type_name, get_full_name(), name, this); endfunction function uvm_object uvm_component::create_object (string requested_type_name, string name=""); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); return factory.create_object_by_name(requested_type_name, get_full_name(), name); endfunction function void uvm_component::set_type_override (string original_type_name, string override_type_name, bit replace=1); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); factory.set_type_override_by_name(original_type_name,override_type_name, replace); endfunction function void uvm_component::set_type_override_by_type (uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace=1); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); factory.set_type_override_by_type(original_type, override_type, replace); endfunction function void uvm_component::set_inst_override (string relative_inst_path, string original_type_name, string override_type_name); string full_inst_path; uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); if (relative_inst_path == "") begin full_inst_path = get_full_name(); end else begin full_inst_path = {get_full_name(), ".", relative_inst_path}; end factory.set_inst_override_by_name( original_type_name, override_type_name, full_inst_path); endfunction function void uvm_component::set_inst_override_by_type (string relative_inst_path, uvm_object_wrapper original_type, uvm_object_wrapper override_type); string full_inst_path; uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); if (relative_inst_path == "") begin full_inst_path = get_full_name(); end else begin full_inst_path = {get_full_name(), ".", relative_inst_path}; end factory.set_inst_override_by_type(original_type, override_type, full_inst_path); endfunction function void uvm_component::set_report_id_verbosity_hier( string id, int verbosity); set_report_id_verbosity(id, verbosity); foreach( m_children[c] ) begin m_children[c].set_report_id_verbosity_hier(id, verbosity); end endfunction function void uvm_component::set_report_severity_id_verbosity_hier( uvm_severity severity, string id, int verbosity); set_report_severity_id_verbosity(severity, id, verbosity); foreach( m_children[c] ) begin m_children[c].set_report_severity_id_verbosity_hier(severity, id, verbosity); end endfunction function void uvm_component::set_report_severity_action_hier( uvm_severity severity, uvm_action action); set_report_severity_action(severity, action); foreach( m_children[c] ) begin m_children[c].set_report_severity_action_hier(severity, action); end endfunction function void uvm_component::set_report_id_action_hier( string id, uvm_action action); set_report_id_action(id, action); foreach( m_children[c] ) begin m_children[c].set_report_id_action_hier(id, action); end endfunction function void uvm_component::set_report_severity_id_action_hier( uvm_severity severity, string id, uvm_action action); set_report_severity_id_action(severity, id, action); foreach( m_children[c] ) begin m_children[c].set_report_severity_id_action_hier(severity, id, action); end endfunction function void uvm_component::set_report_severity_file_hier( uvm_severity severity, UVM_FILE file); set_report_severity_file(severity, file); foreach( m_children[c] ) begin m_children[c].set_report_severity_file_hier(severity, file); end endfunction function void uvm_component::set_report_default_file_hier( UVM_FILE file); set_report_default_file(file); foreach( m_children[c] ) begin m_children[c].set_report_default_file_hier(file); end endfunction function void uvm_component::set_report_id_file_hier( string id, UVM_FILE file); set_report_id_file(id, file); foreach( m_children[c] ) begin m_children[c].set_report_id_file_hier(id, file); end endfunction function void uvm_component::set_report_severity_id_file_hier ( uvm_severity severity, string id, UVM_FILE file); set_report_severity_id_file(severity, id, file); foreach( m_children[c] ) begin m_children[c].set_report_severity_id_file_hier(severity, id, file); end endfunction function void uvm_component::set_report_verbosity_level_hier(int verbosity); set_report_verbosity_level(verbosity); foreach( m_children[c] ) begin m_children[c].set_report_verbosity_level_hier(verbosity); end endfunction function void uvm_component::build_phase(uvm_phase phase); build(); endfunction function void uvm_component::connect_phase(uvm_phase phase); connect(); return; endfunction function void uvm_component::start_of_simulation_phase(uvm_phase phase); start_of_simulation(); return; endfunction function void uvm_component::end_of_elaboration_phase(uvm_phase phase); end_of_elaboration(); return; endfunction task uvm_component::run_phase(uvm_phase phase); run(); return; endtask function void uvm_component::extract_phase(uvm_phase phase); extract(); return; endfunction function void uvm_component::check_phase(uvm_phase phase); check(); return; endfunction function void uvm_component::report_phase(uvm_phase phase); report(); return; endfunction function void uvm_component::final_phase(uvm_phase phase); return; endfunction task uvm_component::pre_reset_phase(uvm_phase phase); return; endtask task uvm_component::reset_phase(uvm_phase phase); return; endtask task uvm_component::post_reset_phase(uvm_phase phase); return; endtask task uvm_component::pre_configure_phase(uvm_phase phase); return; endtask task uvm_component::configure_phase(uvm_phase phase); return; endtask task uvm_component::post_configure_phase(uvm_phase phase); return; endtask task uvm_component::pre_main_phase(uvm_phase phase); return; endtask task uvm_component::main_phase(uvm_phase phase); return; endtask task uvm_component::post_main_phase(uvm_phase phase); return; endtask task uvm_component::pre_shutdown_phase(uvm_phase phase); return; endtask task uvm_component::shutdown_phase(uvm_phase phase); return; endtask task uvm_component::post_shutdown_phase(uvm_phase phase); return; endtask function void uvm_component::phase_started(uvm_phase phase); endfunction function void uvm_component::phase_ended(uvm_phase phase); endfunction function void uvm_component::phase_ready_to_end (uvm_phase phase); endfunction function void uvm_component::define_domain(uvm_domain domain); int num_children; uvm_phase succ[]; domain.get_adjacent_successor_nodes(succ); num_children = succ.size(); foreach(succ[iter]) begin if (succ[iter].get_parent() != domain) begin num_children--; end end if (num_children == 0) begin uvm_phase schedule; schedule = domain.find_by_name("uvm_sched"); if (schedule == null) begin uvm_domain common; schedule = new("uvm_sched", UVM_PHASE_SCHEDULE); uvm_domain::add_uvm_phases(schedule); domain.add(schedule); common = uvm_domain::get_common_domain(); if (common.find(domain,0) == null) begin common.add(domain,.with_phase(uvm_run_phase::get())); end end end endfunction function void uvm_component::set_domain(uvm_domain domain, int hier=1); m_domain = domain; define_domain(domain); if (hier) begin foreach (m_children[c]) begin m_children[c].set_domain(domain); end end endfunction function uvm_domain uvm_component::get_domain(); return m_domain; endfunction function void uvm_component::set_phase_imp(uvm_phase phase, uvm_phase imp, int hier=1); m_phase_imps[phase] = imp; if (hier) begin foreach (m_children[c]) begin m_children[c].set_phase_imp(phase,imp,hier); end end endfunction task uvm_component::suspend(); begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "COMP/SPND/UNIMP") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "COMP/SPND/UNIMP") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("COMP/SPND/UNIMP", "suspend() not implemented", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_component.svh", 2569, "", 1); end end endtask task uvm_component::resume(); begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "COMP/RSUM/UNIMP") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "COMP/RSUM/UNIMP") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("COMP/RSUM/UNIMP", "resume() not implemented", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_component.svh", 2577, "", 1); end end endtask function void uvm_component::resolve_bindings(); return; endfunction function void uvm_component::do_resolve_bindings(); foreach( m_children[s] ) begin m_children[s].do_resolve_bindings(); end resolve_bindings(); endfunction class uvm_config_object_wrapper; uvm_object obj; bit clone; endclass : uvm_config_object_wrapper function void uvm_component::set_config_int(string inst_name, string field_name, uvm_bitstream_t value); uvm_config_int::set(this, inst_name, field_name, value); endfunction function void uvm_component::set_config_string(string inst_name, string field_name, string value); uvm_config_string::set(this, inst_name, field_name, value); endfunction function void uvm_component::set_config_object(string inst_name, string field_name, uvm_object value, bit clone = 1); uvm_object tmp; uvm_config_object_wrapper wrapper; if(value == null) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "NULLCFG") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "NULLCFG") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("NULLCFG", {"A null object was provided as a ", $sformatf("configuration object for set_config_object(\"%s\",\"%s\")", inst_name, field_name), ". Verify that this is intended."}, uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_component.svh", 2641, "", 1); end end end if(clone && (value != null)) begin tmp = value.clone(); if(tmp == null) begin uvm_component comp; if ($cast(comp,value)) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "INVCLNC") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "INVCLNC") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("INVCLNC", {"Clone failed during set_config_object ", "with an object that is an uvm_component. Components cannot be cloned."}, uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_component.svh", 2650, "", 1); end end return; end else begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "INVCLN") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "INVCLN") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("INVCLN", {"Clone failed during set_config_object, ", "the original reference will be used for configuration. Check that ", "the create method for the object type is defined properly."}, uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_component.svh", 2656, "", 1); end end end end else begin value = tmp; end end uvm_config_object::set(this, inst_name, field_name, value); wrapper = new; wrapper.obj = value; wrapper.clone = clone; uvm_config_db#(uvm_config_object_wrapper)::set(this, inst_name, field_name, wrapper); endfunction function bit uvm_component::get_config_int (string field_name, inout uvm_bitstream_t value); return uvm_config_int::get(this, "", field_name, value); endfunction function bit uvm_component::get_config_string(string field_name, inout string value); return uvm_config_string::get(this, "", field_name, value); endfunction function bit uvm_component::get_config_object (string field_name, inout uvm_object value, input bit clone=1); if(!uvm_config_object::get(this, "", field_name, value)) begin return 0; end if(clone && value != null) begin value = value.clone(); end return 1; endfunction function void uvm_component::accept_tr (uvm_transaction tr, time accept_time=0); uvm_event#(uvm_object) e; if(tr == null) begin return; end tr.accept_tr(accept_time); do_accept_tr(tr); e = event_pool.get("accept_tr"); if(e!=null) begin e.trigger(); end endfunction function int uvm_component::begin_tr (uvm_transaction tr, string stream_name="main", string label="", string desc="", time begin_time=0, int parent_handle=0); return m_begin_tr(tr, parent_handle, stream_name, label, desc, begin_time); endfunction function uvm_tr_database uvm_component::get_tr_database(); if (tr_database == null) begin uvm_coreservice_t cs = uvm_coreservice_t::get(); tr_database = cs.get_default_tr_database(); end return tr_database; endfunction : get_tr_database function void uvm_component::set_tr_database(uvm_tr_database db); tr_database = db; endfunction : set_tr_database function uvm_tr_stream uvm_component::get_tr_stream( string name, string stream_type_name="" ); uvm_tr_database db = get_tr_database(); if (!m_streams.exists(name) || !m_streams[name].exists(stream_type_name)) begin m_streams[name][stream_type_name] = db.open_stream(name, this.get_full_name(), stream_type_name); end return m_streams[name][stream_type_name]; endfunction : get_tr_stream function void uvm_component::free_tr_stream(uvm_tr_stream stream); if (stream == null) begin return; end if (!m_streams.exists(stream.get_name()) || !m_streams[stream.get_name()].exists(stream.get_stream_type_name())) begin return; end if (m_streams[stream.get_name()][stream.get_stream_type_name()] != stream) begin return; end m_streams[stream.get_name()].delete(stream.get_type_name()); if (m_streams[stream.get_name()].size() == 0) begin m_streams.delete(stream.get_name()); end if (stream.is_open() || stream.is_closed()) begin stream.free(); end endfunction : free_tr_stream function int uvm_component::m_begin_tr (uvm_transaction tr, int parent_handle=0, string stream_name="main", string label="", string desc="", time begin_time=0); uvm_event#(uvm_object) e; string name; string kind; uvm_tr_database db; int handle, link_handle; uvm_tr_stream stream; uvm_recorder recorder, parent_recorder, link_recorder; if (tr == null) begin return 0; end db = get_tr_database(); if (parent_handle != 0) begin parent_recorder = uvm_recorder::get_recorder_from_handle(parent_handle); if (parent_recorder == null) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "ILLHNDL") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "ILLHNDL") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("ILLHNDL", "begin_tr was passed a non-0 parent handle that corresponds to a null recorder", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_component.svh", 2852, "", 1); end end end end else begin uvm_sequence_item seq; if ($cast(seq,tr)) begin uvm_sequence_base parent_seq = seq.get_parent_sequence(); if (parent_seq != null) begin parent_recorder = parent_seq.m_tr_recorder; end end end if(parent_recorder != null) begin link_handle = tr.begin_tr(begin_time, parent_recorder.get_handle()); end else begin link_handle = tr.begin_tr(begin_time); end if (link_handle != 0) begin link_recorder = uvm_recorder::get_recorder_from_handle(link_handle); end if (tr.get_name() != "") begin name = tr.get_name(); end else begin name = tr.get_type_name(); end if (get_recording_enabled()) begin if (stream_name == "") begin stream_name = "main"; end stream = get_tr_stream(stream_name, "TVM"); if (stream != null ) begin kind = (parent_recorder == null) ? "Begin_No_Parent, Link" : "Begin_End, Link"; recorder = stream.open_recorder(name, begin_time, kind); if (recorder != null) begin if (label != "") begin recorder.record_string("label", label); end if (desc != "") begin recorder.record_string("desc", desc); end if (parent_recorder != null) begin tr_database.establish_link(uvm_parent_child_link::get_link(parent_recorder, recorder)); end if (link_recorder != null) begin tr_database.establish_link(uvm_related_link::get_link(recorder, link_recorder)); end m_tr_h[tr] = recorder; end end handle = (recorder == null) ? 0 : recorder.get_handle(); end do_begin_tr(tr, stream_name, handle); e = event_pool.get("begin_tr"); if (e!=null) begin e.trigger(tr); end return handle; endfunction function void uvm_component::end_tr (uvm_transaction tr, time end_time=0, bit free_handle=1); uvm_event#(uvm_object) e; uvm_recorder recorder; if (tr == null) begin return; end tr.end_tr(end_time,free_handle); if (get_recording_enabled()) begin if (m_tr_h.exists(tr)) begin recorder = m_tr_h[tr]; end end do_end_tr(tr, (recorder == null) ? 0: recorder.get_handle()); if (recorder != null) begin m_tr_h.delete(tr); tr.record(recorder); recorder.close(end_time); if (free_handle) begin recorder.free(); end end e = event_pool.get("end_tr"); if(e!=null) begin e.trigger(); end endfunction function int uvm_component::record_error_tr (string stream_name="main", uvm_object info=null, string label="error_tr", string desc="", time error_time=0, bit keep_active=0); uvm_recorder recorder; string etype; uvm_tr_stream stream; int handle; if(keep_active) begin etype = "Error, Link"; end else begin etype = "Error"; end if(error_time == 0) begin error_time = $realtime; end if (stream_name == "") begin stream_name = "main"; end stream = get_tr_stream(stream_name, "TVM"); handle = 0; if (stream != null) begin recorder = stream.open_recorder(label, error_time, etype); if (recorder != null) begin if (label != "") begin recorder.record_string("label", label); end if (desc != "") begin recorder.record_string("desc", desc); end if (info!=null) begin info.record(recorder); end recorder.close(error_time); if (keep_active == 0) begin recorder.free(); end else begin handle = recorder.get_handle(); end end end return handle; endfunction function int uvm_component::record_event_tr (string stream_name="main", uvm_object info=null, string label="event_tr", string desc="", time event_time=0, bit keep_active=0); uvm_recorder recorder; string etype; int handle; uvm_tr_stream stream; if(keep_active) begin etype = "Event, Link"; end else begin etype = "Event"; end if(event_time == 0) begin event_time = $realtime; end if (stream_name == "") begin stream_name = "main"; end stream = get_tr_stream(stream_name, "TVM"); handle = 0; if (stream != null) begin recorder = stream.open_recorder(label, event_time, etype); if (recorder != null) begin if (label != "") begin recorder.record_string("label", label); end if (desc != "") begin recorder.record_string("desc", desc); end if (info!=null) begin info.record(recorder); end recorder.close(event_time); if (keep_active == 0) begin recorder.free(); end else begin handle = recorder.get_handle(); end end end return handle; endfunction function void uvm_component::do_accept_tr (uvm_transaction tr); return; endfunction function void uvm_component::do_begin_tr (uvm_transaction tr, string stream_name, int tr_handle); return; endfunction function void uvm_component::do_end_tr (uvm_transaction tr, int tr_handle); return; endfunction function string uvm_component::massage_scope(string scope); if(scope == "") begin return "^$"; end if(scope == "*") begin return {get_full_name(), ".*"}; end if(scope == "uvm_test_top") begin return "uvm_test_top"; end if(scope[0] == ".") begin return {get_full_name(), scope}; end return {get_full_name(), ".", scope}; endfunction function uvm_component::config_mode_t uvm_component::apply_config_settings_mode(); return CONFIG_DEFAULT; endfunction : apply_config_settings_mode function bit uvm_component::use_automatic_config(); return 1; endfunction function void uvm_component::check_config_usage ( bit recurse=1 ); uvm_resource_pool rp = uvm_resource_pool::get(); uvm_queue#(uvm_resource_base) rq; rq = rp.find_unused_resources(); if(rq.size() == 0) begin return; end uvm_report_info("CFGNRD"," ::: The following resources have at least one write and no reads :::",UVM_INFO); rp.print_resources(rq, 1); endfunction function void uvm_component::apply_config_settings (bit verbose=0); uvm_resource_types::rsrc_q_t all[string]; string name_order[$]; uvm_resource_pool rp = uvm_resource_pool::get(); uvm_queue#(uvm_resource_base) rq; uvm_resource_base r; config_mode_t mode; mode = apply_config_settings_mode(); if (mode & CONFIG_CHECK_NAMES) begin uvm_queue#(uvm_acs_name_struct) names; uvm_field_op op; names = new("names"); op = uvm_field_op::m_get_available_op(); op.set(UVM_CHECK_FIELDS, null, names); this.do_execute_op(op); op.m_recycle(); while (names.size()) begin uvm_acs_name_struct s; s = names.pop_front(); if (s.name != "") begin name_order.push_back(s.name); all[s.name] = rp.lookup_name(.scope(get_full_name()), .name(s.name), .type_handle(null), .rpterr(0)); if(verbose) begin uvm_report_info("CFGAPL",$sformatf("looking up configuration for field %s (%0d resources)", s.name, all[s.name].size()),UVM_NONE); end end if (s.regex != "") begin rq = rp.lookup_regex(.re(s.regex), .scope(get_full_name())); if(verbose) begin uvm_report_info("CFGAPL",$sformatf("looking up configuration for regex field %s (%0d resources)", s.regex, rq.size()),UVM_NONE); end for (int iter = 0; iter < rq.size(); iter++) begin string r_name; r = rq.get(iter); r_name = r.get_name(); if (!all.exists(r_name)) begin all[r_name] = new(r_name); name_order.push_back(r_name); end all[r_name].push_back(r); end end end end else begin rq = rp.lookup_scope(get_full_name()); while (rq.size()) begin string name; r = rq.pop_front(); name = r.get_name(); if (!all.exists(name)) begin name_order.push_back(name); all[name] = new(name); end all[name].push_back(r); end end foreach (name_order[iter]) begin rq = all[name_order[iter]]; rp.sort_by_precedence(rq); if (mode & CONFIG_HIGHEST_PRECEDENCE) begin int unsigned precedence_by_handle[uvm_resource_base]; uvm_resource_base type_handle; int idx; while (idx < rq.size()) begin r = rq.get(idx); type_handle = r.get_type_handle(); if (type_handle == null) begin idx++; end else if (!precedence_by_handle.exists(type_handle)) begin if(verbose) begin uvm_report_info("CFGAPL",$sformatf("found high precedence (%0d) configuration to field %s", rp.get_precedence(r), r.get_name()),UVM_NONE); end precedence_by_handle[type_handle] = rp.get_precedence(r); idx++; end else begin if (rp.get_precedence(r) < precedence_by_handle[type_handle]) begin if(verbose) begin uvm_report_info("CFGAPL",$sformatf("skipping low precedence (%0d<%0d) configuration to field %s", rp.get_precedence(r), precedence_by_handle[type_handle], r.get_name()),UVM_NONE); end rq.delete(idx); end else begin if(verbose) begin uvm_report_info("CFGAPL",$sformatf("found matching high precedence (%0d) configuration to field %s", rp.get_precedence(r), r.get_name()),UVM_NONE); end idx++; end end end end for (int i=rq.size()-1; i>=0; --i) begin r = rq.get(i); if(verbose) begin uvm_report_info("CFGAPL",$sformatf("applying configuration to field %s", r.get_name()),UVM_NONE); end set_local(r); end end endfunction function void uvm_component::print_config(bit recurse = 0, audit = 0); uvm_resource_pool rp = uvm_resource_pool::get(); uvm_report_info("CFGPRT","visible resources:",UVM_INFO); rp.print_resources(rp.lookup_scope(get_full_name()), audit); if(recurse) begin uvm_component c; foreach(m_children[name]) begin c = m_children[name]; c.print_config(recurse, audit); end end endfunction function void uvm_component::print_config_with_audit(bit recurse = 0); print_config(recurse, 1); endfunction function bit uvm_component::get_recording_enabled(); return (uvm_verbosity'(recording_detail) != UVM_NONE); endfunction function void uvm_component::print_config_settings (string field="", uvm_component comp=null, bit recurse=0); print_config(recurse, 1); endfunction function void uvm_component::set_recording_enabled(bit enabled); if (get_recording_enabled() != enabled) begin recording_detail = enabled ? UVM_LOW : UVM_NONE; end endfunction function void uvm_component::set_recording_enabled_hier(bit enabled); set_recording_enabled(enabled); foreach( m_children[c] ) begin m_children[c].set_recording_enabled_hier(enabled); end endfunction function void uvm_component::do_print(uvm_printer printer); super.do_print(printer); if(uvm_verbosity'(recording_detail) != UVM_NONE) begin case (recording_detail) UVM_LOW : begin printer.print_generic("recording_detail", "uvm_verbosity", $bits(recording_detail), "UVM_LOW"); end UVM_MEDIUM : begin printer.print_generic("recording_detail", "uvm_verbosity", $bits(recording_detail), "UVM_MEDIUM"); end UVM_HIGH : begin printer.print_generic("recording_detail", "uvm_verbosity", $bits(recording_detail), "UVM_HIGH"); end UVM_FULL : begin printer.print_generic("recording_detail", "uvm_verbosity", $bits(recording_detail), "UVM_FULL"); end default : begin printer.print_field_int("recording_detail", recording_detail, $bits(recording_detail), UVM_DEC, , "integral"); end endcase end endfunction function void uvm_component::do_execute_op( uvm_field_op op ); if (op.get_op_type == UVM_PRINT) begin uvm_component child_comp; string name; uvm_printer printer; if (!$cast(printer,op.get_policy())) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "INVPRINTOP") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "INVPRINTOP") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("INVPRINTOP", "do_execute_op() called with a field_op that has op_type UVM_PRINT but a policy that does not derive from uvm_printer", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_component.svh", 3500, "", 1); end end end else if (get_first_child(name)) begin do begin child_comp = get_child(name); if(child_comp.print_enabled) begin printer.print_object(name,child_comp); end end while (get_next_child(name)); end end super.do_execute_op(op); endfunction function void uvm_component::set_local(uvm_resource_base rsrc) ; bit success; if((rsrc != null) && (rsrc.get_name() == "recording_detail")) begin begin begin uvm_resource#(uvm_integral_t) __tmp_rsrc__; success = $cast(__tmp_rsrc__, rsrc); if (success) begin recording_detail = __tmp_rsrc__.read(this); end end if (!success) begin uvm_resource#(uvm_bitstream_t) __tmp_rsrc__; success = $cast(__tmp_rsrc__, rsrc); if (success) begin recording_detail = __tmp_rsrc__.read(this); end end if (!success) begin uvm_resource#(int) __tmp_rsrc__; success = $cast(__tmp_rsrc__, rsrc); if (success) begin recording_detail = __tmp_rsrc__.read(this); end end if (!success) begin uvm_resource#(int unsigned) __tmp_rsrc__; success = $cast(__tmp_rsrc__, rsrc); if (success) begin recording_detail = __tmp_rsrc__.read(this); end end end end if (!success) begin super.set_local(rsrc); end endfunction function void uvm_component::m_unsupported_set_local(uvm_resource_base rsrc); m_unsupported_resource_base = rsrc; endfunction typedef class uvm_cmdline_processor; function void uvm_component::m_set_cl_msg_args; string s_; process p_; p_=process::self(); if(p_!=null) begin s_=p_.get_randstate(); end else begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "UVM") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "UVM") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_warning("UVM", "run_test() invoked from a non process context", uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_component.svh", 3570, "", 1); end end end m_set_cl_verb(); m_set_cl_action(); m_set_cl_sev(); if(p_!=null) begin p_.set_randstate(s_); end endfunction function void uvm_component::m_set_cl_verb; string args[$]; foreach(uvm_cmdline_set_verbosity::settings[i]) begin uvm_cmdline_set_verbosity setting; setting = uvm_cmdline_set_verbosity::settings[i]; if (uvm_is_match(setting.comp, get_full_name()) ) begin if((setting.phase == "" || setting.phase == "build" ) || (setting.phase == "time" && setting.offset == 0) ) begin setting.used[this] = 1; if(setting.id == "_ALL_") begin set_report_verbosity_level(setting.verbosity); end else begin set_report_id_verbosity(setting.id, setting.verbosity); end end else begin setting.used[this] = 0; if(setting.phase != "time") begin m_verbosity_settings.push_back(setting); end end end end endfunction function void uvm_component::m_set_cl_action; uvm_cmdline_set_action setting; foreach(uvm_cmdline_set_action::settings[i]) begin setting = uvm_cmdline_set_action::settings[i]; if (!uvm_is_match(setting.comp, get_full_name()) ) begin continue; end setting.used[this] = 1; if(setting.id == "_ALL_") begin if(setting.all_sev) begin set_report_severity_action(UVM_INFO, setting.action); set_report_severity_action(UVM_WARNING, setting.action); set_report_severity_action(UVM_ERROR, setting.action); set_report_severity_action(UVM_FATAL, setting.action); end else begin set_report_severity_action(setting.sev, setting.action); end end else begin if(setting.all_sev) begin set_report_id_action(setting.id, setting.action); end else begin set_report_severity_id_action(setting.sev, setting.id, setting.action); end end end endfunction function void uvm_component::m_set_cl_sev; uvm_cmdline_set_severity setting; foreach(uvm_cmdline_set_severity::settings[i]) begin setting = uvm_cmdline_set_severity::settings[i]; if (!uvm_is_match(setting.comp, get_full_name()) ) begin continue; end setting.used[this] = 1; if(setting.id == "_ALL_" && setting.all_sev) begin set_report_severity_override(UVM_INFO,setting.sev); set_report_severity_override(UVM_WARNING,setting.sev); set_report_severity_override(UVM_ERROR,setting.sev); set_report_severity_override(UVM_FATAL,setting.sev); end else if(setting.id == "_ALL_") begin set_report_severity_override(setting.orig_sev,setting.sev); end else if(setting.all_sev) begin set_report_severity_id_override(UVM_INFO,setting.id,setting.sev); set_report_severity_id_override(UVM_WARNING,setting.id,setting.sev); set_report_severity_id_override(UVM_ERROR,setting.id,setting.sev); set_report_severity_id_override(UVM_FATAL,setting.id,setting.sev); end else begin set_report_severity_id_override(setting.orig_sev,setting.id,setting.sev); end end endfunction function void uvm_component::m_apply_verbosity_settings(uvm_phase phase); uvm_cmdline_set_verbosity setting; uvm_cmdline_set_verbosity remaining_settings[$]; foreach (m_verbosity_settings[i]) begin setting = m_verbosity_settings[i]; if(phase.get_name() == setting.phase) begin setting.used[this] = 1; if(m_verbosity_settings[i].id == "_ALL_") begin set_report_verbosity_level(m_verbosity_settings[i].verbosity); end else begin set_report_id_verbosity(m_verbosity_settings[i].id, m_verbosity_settings[i].verbosity); end end else begin remaining_settings.push_back(setting); end end m_verbosity_settings = remaining_settings; endfunction function void uvm_component::m_do_pre_abort; foreach(m_children[i]) begin m_children[i].m_do_pre_abort(); end pre_abort(); endfunction function int uvm_component::begin_child_tr (uvm_transaction tr, int parent_handle=0, string stream_name="main", string label="", string desc="", time begin_time=0); return begin_tr(tr, stream_name, label, desc, begin_time, parent_handle); endfunction function void uvm_component::build(); m_build_done = 1; if (use_automatic_config()) begin apply_config_settings(get_print_config_matches()); end endfunction function void uvm_component::connect(); return; endfunction function void uvm_component::start_of_simulation(); return; endfunction function void uvm_component::end_of_elaboration(); return; endfunction task uvm_component::run(); return; endtask function void uvm_component::extract(); return; endfunction function void uvm_component::check(); return; endfunction function void uvm_component::report(); return; endfunction `define UVM_OBJECTION_SVH typedef class uvm_objection_context_object; typedef class uvm_objection; typedef class uvm_sequence_base; typedef class uvm_objection_callback; typedef uvm_callbacks #(uvm_objection,uvm_objection_callback) uvm_objection_cbs_t ; typedef class uvm_cmdline_processor; class uvm_objection_events; int waiters; event raised; event dropped; event all_dropped; endclass class uvm_objection extends uvm_report_object; static local bit m_register_cb_uvm_objection_callback = uvm_callbacks#(uvm_objection,uvm_objection_callback)::m_register_pair("uvm_objection","uvm_objection_callback"); protected bit m_trace_mode; protected int m_source_count[uvm_object]; protected int m_total_count [uvm_object]; protected time m_drain_time [uvm_object]; protected uvm_objection_events m_events [uvm_object]; bit m_top_all_dropped; protected uvm_root m_top; static uvm_objection m_objections[$]; local static uvm_objection_context_object m_context_pool[$]; local process m_drain_proc[uvm_object]; local static uvm_objection_context_object m_scheduled_list[$]; local uvm_objection_context_object m_scheduled_contexts[uvm_object]; local uvm_objection_context_object m_forked_list[$]; local uvm_objection_context_object m_forked_contexts[uvm_object]; protected bit m_prop_mode = 1; protected bit m_cleared; function new(string name=""); uvm_cmdline_processor clp; uvm_coreservice_t cs_ ; string trace_args[$]; super.new(name); cs_ = uvm_coreservice_t::get(); m_top = cs_.get_root(); set_report_verbosity_level(m_top.get_report_verbosity_level()); clp = uvm_cmdline_processor::get_inst(); if(clp.get_arg_matches("+UVM_OBJECTION_TRACE", trace_args)) begin m_trace_mode=1; end m_objections.push_back(this); endfunction function bit trace_mode (int mode=-1); trace_mode = m_trace_mode; if(mode == 0) begin m_trace_mode = 0; end else if(mode == 1) begin m_trace_mode = 1; end endfunction function void m_report(uvm_object obj, uvm_object source_obj, string description, int count, string action); int _count = m_source_count.exists(obj) ? m_source_count[obj] : 0; int _total = m_total_count.exists(obj) ? m_total_count[obj] : 0; if (!uvm_report_enabled(UVM_NONE,UVM_INFO,"OBJTN_TRC") || !m_trace_mode) begin return; end if (source_obj == obj) begin uvm_report_info("OBJTN_TRC", $sformatf("Object %0s %0s %0d %0s objection(s)%s: count=%0d total=%0d", obj.get_full_name()==""?"uvm_top":obj.get_full_name(), action, count, get_full_name(), description != ""? {" (",description,")"}:"", _count, _total), UVM_NONE); end else begin int cpath = 0, last_dot=0; string sname = source_obj.get_full_name(), nm = obj.get_full_name(); int max = sname.len() > nm.len() ? nm.len() : sname.len(); while((sname[cpath] == nm[cpath]) && (cpath < max)) begin if(sname[cpath] == ".") begin last_dot = cpath; end cpath++; end if(last_dot) begin sname = sname.substr(last_dot+1, sname.len()); end uvm_report_info("OBJTN_TRC", $sformatf("Object %0s %0s %0d %0s objection(s) %0s its total (%s from source object %s%s): count=%0d total=%0d", obj.get_full_name()==""?"uvm_top":obj.get_full_name(), action=="raised"?"added":"subtracted", count, get_full_name(), action=="raised"?"to":"from", action, sname, description != ""?{", ",description}:"", _count, _total), UVM_NONE); end endfunction function uvm_object m_get_parent(uvm_object obj); uvm_component comp; uvm_sequence_base seq; if ($cast(comp, obj)) begin obj = comp.get_parent(); end else if ($cast(seq, obj)) begin obj = seq.get_sequencer(); end else begin obj = m_top; end if (obj == null) begin obj = m_top; end return obj; endfunction function void m_propagate (uvm_object obj, uvm_object source_obj, string description, int count, bit raise, int in_top_thread); if (obj != null && obj != m_top) begin obj = m_get_parent(obj); if(raise) begin m_raise(obj, source_obj, description, count); end else begin m_drop(obj, source_obj, description, count, in_top_thread); end end endfunction function void set_propagate_mode (bit prop_mode); if (!m_top_all_dropped && (get_objection_total() != 0)) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_ERROR, "UVM/BASE/OBJTN/PROP_MODE") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_ERROR, "UVM/BASE/OBJTN/PROP_MODE") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_error("UVM/BASE/OBJTN/PROP_MODE", {"The propagation mode of '", this.get_full_name(), "' cannot be changed while the objection is raised ", "or draining!"}, uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_objection.svh", 318, "", 1); end end return; end m_prop_mode = prop_mode; endfunction : set_propagate_mode function bit get_propagate_mode(); return m_prop_mode; endfunction : get_propagate_mode virtual function void raise_objection (uvm_object obj=null, string description="", int count=1); if(obj == null) begin obj = m_top; end m_cleared = 0; m_top_all_dropped = 0; m_raise (obj, obj, description, count); endfunction function void m_raise (uvm_object obj, uvm_object source_obj, string description="", int count=1); int idx; uvm_objection_context_object ctxt; if (count == 0) begin return; end if (m_total_count.exists(obj)) begin m_total_count[obj] += count; end else begin m_total_count[obj] = count; end if (source_obj==obj) begin if (m_source_count.exists(obj)) begin m_source_count[obj] += count; end else begin m_source_count[obj] = count; end end if (m_trace_mode) begin m_report(obj,source_obj,description,count,"raised"); end raised(obj, source_obj, description, count); idx = 0; while (idx < m_scheduled_list.size()) begin if ((m_scheduled_list[idx].obj == obj) && (m_scheduled_list[idx].objection == this)) begin ctxt = m_scheduled_list[idx]; m_scheduled_list.delete(idx); break; end idx++; end if (ctxt == null) begin idx = 0; while (idx < m_forked_list.size()) begin if (m_forked_list[idx].obj == obj) begin ctxt = m_forked_list[idx]; m_forked_list.delete(idx); m_scheduled_contexts.delete(ctxt.obj); break; end idx++; end end if (ctxt == null) begin if (m_forked_contexts.exists(obj)) begin ctxt = m_forked_contexts[obj]; m_forked_contexts.delete(obj); m_drain_proc[obj].kill(); m_drain_proc.delete(obj); end end if (ctxt == null) begin if (!m_prop_mode && obj != m_top) begin m_raise(m_top,source_obj,description,count); end else if (obj != m_top) begin m_propagate(obj, source_obj, description, count, 1, 0); end end else begin int diff_count; diff_count = count - ctxt.count; if (diff_count != 0) begin if (diff_count > 0) begin if (!m_prop_mode && obj != m_top) begin m_raise(m_top, source_obj, description, diff_count); end else if (obj != m_top) begin m_propagate(obj, source_obj, description, diff_count, 1, 0); end end else begin diff_count = -diff_count; if (!m_prop_mode && obj != m_top) begin m_drop(m_top, source_obj, description, diff_count); end else if (obj != m_top) begin m_propagate(obj, source_obj, description, diff_count, 0, 0); end end end ctxt.clear(); m_context_pool.push_back(ctxt); end endfunction virtual function void drop_objection (uvm_object obj=null, string description="", int count=1); if(obj == null) begin obj = m_top; end m_drop (obj, obj, description, count, 0); endfunction function void m_drop (uvm_object obj, uvm_object source_obj, string description="", int count=1, int in_top_thread=0); if (count == 0) begin return; end if (!m_total_count.exists(obj) || (count > m_total_count[obj])) begin if(m_cleared) begin return; end uvm_report_fatal("OBJTN_ZERO", {"Object \"", obj.get_full_name(), "\" attempted to drop objection '",this.get_name(),"' count below zero"}); return; end if (obj == source_obj) begin if (!m_source_count.exists(obj) || (count > m_source_count[obj])) begin if(m_cleared) begin return; end uvm_report_fatal("OBJTN_ZERO", {"Object \"", obj.get_full_name(), "\" attempted to drop objection '",this.get_name(),"' count below zero"}); return; end m_source_count[obj] -= count; end m_total_count[obj] -= count; if (m_trace_mode) begin m_report(obj,source_obj,description,count,"dropped"); end dropped(obj, source_obj, description, count); if (m_total_count[obj] != 0) begin if (!m_prop_mode && obj != m_top) begin m_drop(m_top,source_obj,description, count, in_top_thread); end else if (obj != m_top) begin this.m_propagate(obj, source_obj, description, count, 0, in_top_thread); end end else begin uvm_objection_context_object ctxt; if (m_context_pool.size()) begin ctxt = m_context_pool.pop_front(); end else begin ctxt = new; end ctxt.obj = obj; ctxt.source_obj = source_obj; ctxt.description = description; ctxt.count = count; ctxt.objection = this; m_scheduled_list.push_back(ctxt); end endfunction virtual function void clear(uvm_object obj=null); string name; int idx; if (obj==null) begin obj=m_top; end name = obj.get_full_name(); if (name == "") begin name = "uvm_top"; end else begin name = obj.get_full_name(); end if (!m_top_all_dropped && get_objection_total(m_top)) begin uvm_report_warning("OBJTN_CLEAR",{"Object '",name, "' cleared objection counts for ",get_name()}); end m_source_count.delete(); m_total_count.delete(); idx = 0; while (idx < m_scheduled_list.size()) begin if (m_scheduled_list[idx].objection == this) begin m_scheduled_list[idx].clear(); m_context_pool.push_back(m_scheduled_list[idx]); m_scheduled_list.delete(idx); end else begin idx++; end end m_scheduled_contexts.delete(); while (m_forked_list.size()) begin m_forked_list[0].clear(); m_context_pool.push_back(m_forked_list[0]); void'(m_forked_list.pop_front()); end foreach (m_forked_contexts[o]) begin m_drain_proc[o].kill(); m_drain_proc.delete(o); m_forked_contexts[o].clear(); m_context_pool.push_back(m_forked_contexts[o]); m_forked_contexts.delete(o); end m_top_all_dropped = 0; m_cleared = 1; if (m_events.exists(m_top)) begin ->m_events[m_top].all_dropped; end endfunction static task m_execute_scheduled_forks(); while(1) begin wait(m_scheduled_list.size() != 0); if(m_scheduled_list.size() != 0) begin uvm_objection_context_object c; c = m_scheduled_list.pop_front(); c.objection.m_scheduled_contexts[c.obj] = c; c.objection.m_forked_list.push_back(c); fork : guard automatic uvm_objection objection = c.objection; begin if (objection.m_forked_list.size() > 0) begin uvm_objection_context_object ctxt; ctxt = objection.m_forked_list.pop_front(); objection.m_scheduled_contexts.delete(ctxt.obj); objection.m_forked_contexts[ctxt.obj] = ctxt; objection.m_drain_proc[ctxt.obj] = process::self(); objection.m_forked_drain(ctxt.obj, ctxt.source_obj, ctxt.description, ctxt.count, 1); objection.m_drain_proc.delete(ctxt.obj); objection.m_forked_contexts.delete(ctxt.obj); ctxt.clear(); m_context_pool.push_back(ctxt); end end join_none : guard end end endtask task m_forked_drain (uvm_object obj, uvm_object source_obj, string description="", int count=1, int in_top_thread=0); if (m_drain_time.exists(obj)) begin #(m_drain_time[obj]); end if (m_trace_mode) begin m_report(obj,source_obj,description,count,"all_dropped"); end all_dropped(obj,source_obj,description, count); wait fork; if (m_source_count.exists(obj) && m_source_count[obj] == 0) begin m_source_count.delete(obj); end if (m_total_count.exists(obj) && m_total_count[obj] == 0) begin m_total_count.delete(obj); end if (!m_prop_mode && obj != m_top) begin m_drop(m_top,source_obj,description, count, 1); end else if (obj != m_top) begin m_propagate(obj, source_obj, description, count, 0, 1); end endtask static function void m_init_objections(); fork begin uvm_objection::m_execute_scheduled_forks(); end join_none endfunction function void set_drain_time (uvm_object obj=null, time drain); if (obj==null) begin obj = m_top; end m_drain_time[obj] = drain; endfunction virtual function void raised (uvm_object obj, uvm_object source_obj, string description, int count); uvm_component comp; if ($cast(comp,obj)) begin comp.raised(this, source_obj, description, count); end begin uvm_callback_iter#(uvm_objection,uvm_objection_callback) iter = new(this); uvm_objection_callback cb = iter.first(); while(cb != null) begin cb.raised(this,obj,source_obj,description,count); cb = iter.next(); end end if (m_events.exists(obj)) begin ->m_events[obj].raised; end endfunction virtual function void dropped (uvm_object obj, uvm_object source_obj, string description, int count); uvm_component comp; if($cast(comp,obj)) begin comp.dropped(this, source_obj, description, count); end begin uvm_callback_iter#(uvm_objection,uvm_objection_callback) iter = new(this); uvm_objection_callback cb = iter.first(); while(cb != null) begin cb.dropped(this,obj,source_obj,description,count); cb = iter.next(); end end if (m_events.exists(obj)) begin ->m_events[obj].dropped; end endfunction virtual task all_dropped (uvm_object obj, uvm_object source_obj, string description, int count); uvm_component comp; if($cast(comp,obj)) begin comp.all_dropped(this, source_obj, description, count); end begin uvm_callback_iter#(uvm_objection,uvm_objection_callback) iter = new(this); uvm_objection_callback cb = iter.first(); while(cb != null) begin cb.all_dropped(this,obj,source_obj,description,count); cb = iter.next(); end end if (m_events.exists(obj)) begin ->m_events[obj].all_dropped; end if (obj == m_top) begin m_top_all_dropped = 1; end endtask function void get_objectors(ref uvm_object list[$]); list.delete(); foreach (m_source_count[obj]) begin list.push_back(obj); end endfunction task wait_for(uvm_objection_event objt_event, uvm_object obj=null); if (obj==null) begin obj = m_top; end if (!m_events.exists(obj)) begin m_events[obj] = new; end m_events[obj].waiters++; case (objt_event) UVM_RAISED: begin @(m_events[obj].raised); end UVM_DROPPED: begin @(m_events[obj].dropped); end UVM_ALL_DROPPED: begin @(m_events[obj].all_dropped); end endcase m_events[obj].waiters--; if (m_events[obj].waiters == 0) begin m_events.delete(obj); end endtask task wait_for_total_count(uvm_object obj=null, int count=0); if (obj==null) begin obj = m_top; end if(!m_total_count.exists(obj) && count == 0) begin return; end if (count == 0) begin wait (!m_total_count.exists(obj) && count == 0); end else begin wait (m_total_count.exists(obj) && m_total_count[obj] == count); end endtask function int get_objection_count (uvm_object obj=null); if (obj==null) begin obj = m_top; end if (!m_source_count.exists(obj)) begin return 0; end return m_source_count[obj]; endfunction function int get_objection_total (uvm_object obj=null); if (obj==null) begin obj = m_top; end if (!m_total_count.exists(obj)) begin return 0; end else begin return m_total_count[obj]; end endfunction function time get_drain_time (uvm_object obj=null); if (obj==null) begin obj = m_top; end if (!m_drain_time.exists(obj)) begin return 0; end return m_drain_time[obj]; endfunction protected function string m_display_objections(uvm_object obj=null, bit show_header=1); static string blank=" "; string s; int total; uvm_object list[string]; uvm_object curr_obj; int depth; string name; string this_obj_name; string curr_obj_name; foreach (m_total_count[o]) begin uvm_object theobj = o; if ( m_total_count[o] > 0) begin list[theobj.get_full_name()] = theobj; end end if (obj==null) begin obj = m_top; end total = get_objection_total(obj); s = $sformatf("The total objection count is %0d\n",total); if (total == 0) begin return s; end s = {s,"---------------------------------------------------------\n"}; s = {s,"Source Total \n"}; s = {s,"Count Count Object\n"}; s = {s,"---------------------------------------------------------\n"}; this_obj_name = obj.get_full_name(); curr_obj_name = this_obj_name; do begin curr_obj = list[curr_obj_name]; depth=0; foreach (curr_obj_name[i]) begin if (curr_obj_name[i] == ".") begin depth++; end end name = curr_obj_name; for (int i=curr_obj_name.len()-1;i >= 0; i--) begin if (curr_obj_name[i] == ".") begin name = curr_obj_name.substr(i+1,curr_obj_name.len()-1); break; end end if (curr_obj_name == "") begin name = "uvm_top"; end else begin depth++; end s = {s, $sformatf("%-6d %-6d %s%s\n", m_source_count.exists(curr_obj) ? m_source_count[curr_obj] : 0, m_total_count.exists(curr_obj) ? m_total_count[curr_obj] : 0, blank.substr(0,2*depth), name)}; end while (list.next(curr_obj_name) && curr_obj_name.substr(0,this_obj_name.len()-1) == this_obj_name); s = {s,"---------------------------------------------------------\n"}; return s; endfunction function string convert2string(); return m_display_objections(m_top,1); endfunction function void display_objections(uvm_object obj=null, bit show_header=1); string m = m_display_objections(obj,show_header); begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = uvm_get_report_object().uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "UVM/OBJ/DISPLAY") >= UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "UVM/OBJ/DISPLAY") != uvm_pkg::UVM_NO_ACTION)) begin uvm_report_info("UVM/OBJ/DISPLAY", m, UVM_NONE, "t/uvm/src/base/uvm_objection.svh", 1319, "", 1); end end endfunction typedef uvm_object_registry#(uvm_objection,"uvm_objection") type_id; static function type_id get_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_objection tmp = new(name); return tmp; endfunction virtual function string get_type_name (); return "uvm_objection"; endfunction function void do_copy (uvm_object rhs); uvm_objection _rhs; $cast(_rhs, rhs); m_source_count = _rhs.m_source_count; m_total_count = _rhs.m_total_count; m_drain_time = _rhs.m_drain_time; m_prop_mode = _rhs.m_prop_mode; endfunction function void m_set_hier_mode (uvm_object obj); endfunction endclass typedef class uvm_cmdline_processor; class uvm_objection_context_object; uvm_object obj; uvm_object source_obj; string description; int count; uvm_objection objection; function void clear(); obj = null; source_obj = null; description = ""; count = 0; objection = null; endfunction : clear endclass typedef uvm_objection uvm_callbacks_objection; class uvm_objection_callback extends uvm_callback; function new(string name); super.new(name); endfunction virtual function void raised (uvm_objection objection, uvm_object obj, uvm_object source_obj, string description, int count); endfunction virtual function void dropped (uvm_objection objection, uvm_object obj, uvm_object source_obj, string description, int count); endfunction virtual task all_dropped (uvm_objection objection, uvm_object obj, uvm_object source_obj, string description, int count); endtask endclass class uvm_test_done_objection extends uvm_objection; protected static uvm_test_done_objection m_inst; protected bit m_forced; local bit m_executing_stop_processes; local int m_n_stop_threads; function new(string name="uvm_test_done"); super.new(name); endfunction virtual function void qualify(uvm_object obj=null, bit is_raise, string description); uvm_component c; uvm_sequence_base s; string nm = is_raise ? "raise_objection" : "drop_objection"; string desc = description == "" ? "" : {" (\"", description, "\")"}; if(! ($cast(c,obj) || $cast(s,obj))) begin uvm_report_error("TEST_DONE_NOHIER", {"A non-hierarchical object, '", obj.get_full_name(), "' (", obj.get_type_name(),") was used in a call ", "to uvm_test_done.", nm,"(). For this objection, a sequence ", "or component is required.", desc }); end endfunction typedef uvm_object_registry#(uvm_test_done_objection,"uvm_test_done") type_id; static function type_id get_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_test_done_objection tmp = new(name); return tmp; endfunction virtual function string get_type_name (); return "uvm_test_done"; endfunction static function uvm_test_done_objection get(); if(m_inst == null) begin m_inst = uvm_test_done_objection::type_id::create("run"); end return m_inst; endfunction endclass `define UVM_HEARTBEAT_SVH typedef enum { UVM_ALL_ACTIVE, UVM_ONE_ACTIVE, UVM_ANY_ACTIVE, UVM_NO_HB_MODE } uvm_heartbeat_modes; typedef class uvm_heartbeat_callback; typedef uvm_callbacks #(uvm_objection,uvm_heartbeat_callback) uvm_heartbeat_cbs_t; typedef class uvm_objection_callback; class uvm_heartbeat extends uvm_object; protected uvm_objection m_objection; protected uvm_heartbeat_callback m_cb; protected uvm_component m_cntxt; protected uvm_heartbeat_modes m_mode; protected uvm_component m_hblist[$]; protected uvm_event#(uvm_object) m_event; protected bit m_started; protected event m_stop_event; function new(string name, uvm_component cntxt, uvm_objection objection=null); uvm_coreservice_t cs; super.new(name); m_objection = objection; cs = uvm_coreservice_t::get(); if(cntxt != null) begin m_cntxt = cntxt; end else begin m_cntxt = cs.get_root(); end m_cb = new({name,"_cb"},m_cntxt); endfunction function uvm_heartbeat_modes set_mode (uvm_heartbeat_modes mode = UVM_NO_HB_MODE); set_mode = m_mode; if(mode == UVM_ANY_ACTIVE || mode == UVM_ONE_ACTIVE || mode == UVM_ALL_ACTIVE) begin m_mode = mode; end endfunction function void set_heartbeat (uvm_event#(uvm_object) e, ref uvm_component comps[$]); uvm_object c; foreach(comps[i]) begin c = comps[i]; if(!m_cb.cnt.exists(c)) begin m_cb.cnt[c]=0; end if(!m_cb.last_trigger.exists(c)) begin m_cb.last_trigger[c]=0; end end if(e==null && m_event==null) begin return; end start(e); endfunction function void add (uvm_component comp); uvm_object c = comp; if(m_cb.cnt.exists(c)) begin return; end m_cb.cnt[c]=0; m_cb.last_trigger[c]=0; endfunction function void remove (uvm_component comp); uvm_object c = comp; if(m_cb.cnt.exists(c)) begin m_cb.cnt.delete(c); end if(m_cb.last_trigger.exists(c)) begin m_cb.last_trigger.delete(c); end endfunction function void start (uvm_event#(uvm_object) e=null); if(m_event == null && e == null) begin m_cntxt.uvm_report_warning("NOEVNT", { "start() was called for: ", get_name(), " with a null trigger and no currently set trigger" }, UVM_NONE); return; end if((m_event != null) && (e != m_event) && m_started) begin m_cntxt.uvm_report_error("ILHBVNT", { "start() was called for: ", get_name(), " with trigger ", e.get_name(), " which is different ", "from the original trigger ", m_event.get_name() }, UVM_NONE); return; end if(e != null) begin m_event = e; end m_enable_cb(); m_start_hb_process(); endfunction function void stop (); m_started = 0; ->m_stop_event; m_disable_cb(); endfunction function void m_start_hb_process(); if(m_started) begin return; end m_started = 1; fork begin m_hb_process; end join_none endfunction protected bit m_added; function void m_enable_cb; void'(m_cb.callback_mode(1)); if(m_objection == null) begin return; end if(!m_added) begin uvm_heartbeat_cbs_t::add(m_objection, m_cb); end m_added = 1; endfunction function void m_disable_cb; void'(m_cb.callback_mode(0)); endfunction task m_hb_process; uvm_object obj; bit triggered; time last_trigger=0; fork begin while(1) begin m_event.wait_trigger(); if(triggered) begin case (m_mode) UVM_ALL_ACTIVE: begin foreach(m_cb.cnt[idx]) begin obj = idx; if(!m_cb.cnt[obj]) begin m_cntxt.uvm_report_fatal("HBFAIL", $sformatf("Did not recieve an update of %s for component %s since last event trigger at time %0t : last update time was %0t", m_objection.get_name(), obj.get_full_name(), last_trigger, m_cb.last_trigger[obj]), UVM_NONE); end end end UVM_ANY_ACTIVE: begin if(m_cb.cnt.num() && !m_cb.objects_triggered()) begin string s; foreach(m_cb.cnt[idx]) begin obj = idx; s={s,"\n ",obj.get_full_name()}; end m_cntxt.uvm_report_fatal("HBFAIL", $sformatf("Did not recieve an update of %s on any component since last event trigger at time %0t. The list of registered components is:%s", m_objection.get_name(), last_trigger, s), UVM_NONE); end end UVM_ONE_ACTIVE: begin if(m_cb.objects_triggered() > 1) begin string s; foreach(m_cb.cnt[idx]) begin obj = idx; if(m_cb.cnt[obj]) begin $swrite(s,"%s\n %s (updated: %0t)", s, obj.get_full_name(), m_cb.last_trigger[obj]); end end m_cntxt.uvm_report_fatal("HBFAIL", $sformatf("Recieved update of %s from more than one component since last event trigger at time %0t. The list of triggered components is:%s", m_objection.get_name(), last_trigger, s), UVM_NONE); end if(m_cb.cnt.num() && !m_cb.objects_triggered()) begin string s; foreach(m_cb.cnt[idx]) begin obj = idx; s={s,"\n ",obj.get_full_name()}; end m_cntxt.uvm_report_fatal("HBFAIL", $sformatf("Did not recieve an update of %s on any component since last event trigger at time %0t. The list of registered components is:%s", m_objection.get_name(), last_trigger, s), UVM_NONE); end end endcase end m_cb.reset_counts(); last_trigger = $realtime; triggered = 1; end end begin @(m_stop_event); end join_any disable fork; endtask endclass class uvm_heartbeat_callback extends uvm_objection_callback; int cnt [uvm_object]; time last_trigger [uvm_object]; uvm_object target; uvm_coreservice_t cs = uvm_coreservice_t::get(); function new(string name, uvm_object target); super.new(name); if (target != null) begin this.target = target; end else begin this.target = cs.get_root(); end endfunction virtual function void raised (uvm_objection objection, uvm_object obj, uvm_object source_obj, string description, int count); if(obj == target) begin if(!cnt.exists(source_obj)) begin cnt[source_obj] = 0; end cnt[source_obj] = cnt[source_obj]+1; last_trigger[source_obj] = $realtime; end endfunction virtual function void dropped (uvm_objection objection, uvm_object obj, uvm_object source_obj, string description, int count); raised(objection,obj,source_obj,description,count); endfunction function void reset_counts; foreach(cnt[i]) begin cnt[i] = 0; end endfunction function int objects_triggered; objects_triggered = 0; foreach(cnt[i]) begin if (cnt[i] != 0) begin objects_triggered++; end end endfunction endclass class uvm_cmd_line_verb; string comp_path; string id; uvm_verbosity verb; int exec_time; endclass typedef class uvm_cmdline_processor; uvm_cmdline_processor uvm_cmdline_proc; class uvm_cmdline_processor extends uvm_report_object; static local uvm_cmdline_processor m_inst; static function uvm_cmdline_processor get_inst(); if(m_inst == null) begin m_inst = new("uvm_cmdline_proc"); end uvm_cmdline_proc = m_inst; return m_inst; endfunction protected string m_argv[$]; protected string m_plus_argv[$]; protected string m_uvm_argv[$]; function void get_args (output string args[$]); args = m_argv; endfunction function void get_plusargs (output string args[$]); args = m_plus_argv; endfunction function void get_uvm_args (output string args[$]); args = m_uvm_argv; endfunction function int get_arg_matches (string match, ref string args[$]); bit match_is_regex = (match.len() > 2) && (match[0] == "/") && (match[match.len()-1] == "/"); int len = match.len(); args.delete(); foreach (m_argv[i]) begin if ( match_is_regex && uvm_is_match( match, m_argv[i] ) ) begin args.push_back( m_argv[i] ); end else if((m_argv[i].len() >= len) && (m_argv[i].substr(0,len - 1) == match)) begin args.push_back(m_argv[i]); end end return args.size(); endfunction function int get_arg_value (string match, ref string value); int chars = match.len(); get_arg_value = 0; foreach (m_argv[i]) begin if(m_argv[i].len() >= chars) begin if(m_argv[i].substr(0,chars-1) == match) begin get_arg_value++; if(get_arg_value == 1) begin value = m_argv[i].substr(chars,m_argv[i].len()-1); end end end end endfunction function int get_arg_values (string match, ref string values[$]); int chars = match.len(); values.delete(); foreach (m_argv[i]) begin if(m_argv[i].len() >= chars) begin if(m_argv[i].substr(0,chars-1) == match) begin values.push_back(m_argv[i].substr(chars,m_argv[i].len()-1)); end end end return values.size(); endfunction function string get_tool_name (); return uvm_dpi_get_tool_name(); endfunction function string get_tool_version (); return uvm_dpi_get_tool_version(); endfunction function new(string name = ""); string s; string sub; int doInit=1; super.new(name); do begin s = uvm_dpi_get_next_arg(doInit); doInit=0; if(s!="") begin m_argv.push_back(s); if(s[0] == "+") begin m_plus_argv.push_back(s); end if(s.len() >= 4 && (s[0]=="-" || s[0]=="+")) begin sub = s.substr(1,3); sub = sub.toupper(); if(sub == "UVM") begin m_uvm_argv.push_back(s); end end end end while(s!=""); endfunction endclass class uvm_cmdline_setting_base; string arg; bit used[uvm_component]; endclass : uvm_cmdline_setting_base class uvm_cmdline_verbosity extends uvm_cmdline_setting_base; int verbosity; enum {STANDARD, NON_STANDARD, ILLEGAL} src; localparam string prefix = "+UVM_VERBOSITY="; static uvm_cmdline_verbosity settings[$]; static function void init(input uvm_report_object ro); string setting_str[$]; int verbosity; int verb_count; string verb_string; bit skip; uvm_cmdline_processor clp = uvm_cmdline_processor::get_inst(); verb_count = $value$plusargs("UVM_VERBOSITY=%s", verb_string); if (verb_count) setting_str.push_back(verb_string); foreach(setting_str[i]) begin uvm_cmdline_verbosity setting; uvm_verbosity temp_verb; setting = new(); setting.arg = setting_str[i]; setting.src = STANDARD; if (!uvm_string_to_verbosity(setting_str[i], temp_verb)) begin int code; code = $sscanf(setting_str[i], "%d", setting.verbosity); if (code > 0) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = ro.uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_INFO, "NSTVERB") >= UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_INFO, "NSTVERB") != uvm_pkg::UVM_NO_ACTION)) begin _local_report_object_.uvm_report_info("NSTVERB", $sformatf("Non-standard verbosity value '%s', converted to '%0d'.", setting_str[i], verbosity), UVM_NONE, "t/uvm/src/base/uvm_cmdline_report.svh", 86, "", 1); end end setting.src = NON_STANDARD; end else begin setting.verbosity = UVM_MEDIUM; setting.src = ILLEGAL; end end else begin setting.verbosity = temp_verb; end settings.push_back(setting); end endfunction : init static function void check(uvm_report_object ro); string verb_q[$]; foreach (settings[i]) begin if (settings[i].src == ILLEGAL) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = ro.uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "ILLVERB") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "ILLVERB") != uvm_pkg::UVM_NO_ACTION)) begin _local_report_object_.uvm_report_warning("ILLVERB", $sformatf("Illegal verbosity value '%s', converted to default of UVM_MEDIUM.", settings[i].arg), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_cmdline_report.svh", 115, "", 1); end end end if (i != 0) begin verb_q.push_back(", "); end verb_q.push_back(settings[i].arg); end if (settings.size() > 1) begin begin uvm_pkg::uvm_report_object _local_report_object_; _local_report_object_ = ro.uvm_get_report_object() ; if ((_local_report_object_.get_report_verbosity_level(uvm_pkg::UVM_WARNING, "MULTVERB") >= uvm_pkg::UVM_NONE) && (_local_report_object_.get_report_action(uvm_pkg::UVM_WARNING, "MULTVERB") != uvm_pkg::UVM_NO_ACTION)) begin _local_report_object_.uvm_report_warning("MULTVERB", $sformatf("Multiple (%0d) +UVM_VERBOSITY arguments provided on the command line. '%s' will be used. Provided list: %s.", settings.size(), settings[0].arg, uvm_pkg::m_uvm_string_queue_join(verb_q)), uvm_pkg::UVM_NONE, "t/uvm/src/base/uvm_cmdline_report.svh", 131, "", 1); end end; end endfunction : check static function string dump(); string msgs[$]; int tmp_verb; foreach (settings[i]) begin msgs.push_back($sformatf("\n%s%s: ", prefix, settings[i].arg)); if (i == 0) begin msgs.push_back("Applied"); end else begin msgs.push_back("Not applied (not first on command line)"); end if (settings[i].src == NON_STANDARD) begin msgs.push_back($sformatf(", converted as non-standard to '%0d'", settings[i].verbosity)); end else if (settings[i].src == ILLEGAL) begin msgs.push_back(", converted as ILLEGAL to UVM_MEDIUM"); end end return uvm_pkg::m_uvm_string_queue_join(msgs); endfunction : dump endclass : uvm_cmdline_verbosity class uvm_cmdline_set_verbosity extends uvm_cmdline_setting_base; string comp; string id; int verbosity; string phase; time offset; localparam string prefix = "+uvm_set_verbosity="; static uvm_cmdline_set_verbosity settings[$]; static function void init(input uvm_report_object ro); string setting_str[$]; uvm_cmdline_processor clp = uvm_cmdline_processor::get_inst(); if (clp.get_arg_values(prefix, setting_str) > 0) begin uvm_verbosity temp_verb; string args[$]; string message; bit skip; foreach(setting_str[i]) begin skip = 0; uvm_string_split(setting_str[i], ",", args); if (args.size() < 4 || args.size() > 5) begin message = "Invalid number of arguments found, expected 4 or 5"; skip = 1; end if (args.size() == 5 && args[3] != "time") begin message = "Too many arguments found for , expected only 4"; skip = 1; end if (args.size() == 4 && args[3] == "time") begin message = "Too few arguments found for