pax_global_header 0000666 0000000 0000000 00000000064 14502055570 0014515 g ustar 00root root 0000000 0000000 52 comment=f0a9690c35e0dbc55cf9a1817ffc117e99bf210a
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/ 0000775 0000000 0000000 00000000000 14502055570 0017634 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/.github/ 0000775 0000000 0000000 00000000000 14502055570 0021174 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/.github/workflows/ 0000775 0000000 0000000 00000000000 14502055570 0023231 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/.github/workflows/push.yml 0000664 0000000 0000000 00000001224 14502055570 0024732 0 ustar 00root root 0000000 0000000 name: 'push'
on:
push:
pull_request:
schedule:
- cron: '0 0 * * 5'
env:
CI: true
DOCKER_BUILDKIT: 1
jobs:
test:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v3
- run: ./ci.sh
#- name: Trigger 'synth' in ghdl/docker
# if: github.ref == 'refs/heads/master' && github.event_name != 'pull_request'
# run: |
# curl -X POST https://api.github.com/repos/ghdl/docker/dispatches \
# -H "Content-Type: application/json" \
# -H 'Accept: application/vnd.github.everest-preview+json' \
# -H "Authorization: token ${{ secrets.GHDL_BOT }}" \
# --data '{"event_type": "synth"}'
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/.gitignore 0000664 0000000 0000000 00000000142 14502055570 0021621 0 ustar 00root root 0000000 0000000 *.d
.gdb_history
*.bin
*.asc
*.json
*.blif
*.edif
*.ilang
*.cf
*.rpt
*.o
*.so
testsuite/**/work/
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/LICENSE 0000664 0000000 0000000 00000104515 14502055570 0020647 0 ustar 00root root 0000000 0000000 GNU GENERAL PUBLIC LICENSE
Version 3, 29 June 2007
Copyright (C) 2007 Free Software Foundation, Inc.
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
Preamble
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or that patent license was granted, prior to 28 March 2007.
Nothing in this License shall be construed as excluding or limiting
any implied license or other defenses to infringement that may
otherwise be available to you under applicable patent law.
12. No Surrender of Others' Freedom.
If conditions are imposed on you (whether by court order, agreement or
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to collect a royalty for further conveying from those to whom you convey
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13. Use with the GNU Affero General Public License.
Notwithstanding any other provision of this License, you have
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combination as such.
14. Revised Versions of this License.
The Free Software Foundation may publish revised and/or new versions of
the GNU General Public License from time to time. Such new versions will
be similar in spirit to the present version, but may differ in detail to
address new problems or concerns.
Each version is given a distinguishing version number. If the
Program specifies that a certain numbered version of the GNU General
Public License "or any later version" applies to it, you have the
option of following the terms and conditions either of that numbered
version or of any later version published by the Free Software
Foundation. If the Program does not specify a version number of the
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by the Free Software Foundation.
If the Program specifies that a proxy can decide which future
versions of the GNU General Public License can be used, that proxy's
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to choose that version for the Program.
Later license versions may give you additional or different
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later version.
15. Disclaimer of Warranty.
THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
16. Limitation of Liability.
IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES.
17. Interpretation of Sections 15 and 16.
If the disclaimer of warranty and limitation of liability provided
above cannot be given local legal effect according to their terms,
reviewing courts shall apply local law that most closely approximates
an absolute waiver of all civil liability in connection with the
Program, unless a warranty or assumption of liability accompanies a
copy of the Program in return for a fee.
END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest
possible use to the public, the best way to achieve this is to make it
free software which everyone can redistribute and change under these terms.
To do so, attach the following notices to the program. It is safest
to attach them to the start of each source file to most effectively
state the exclusion of warranty; and each file should have at least
the "copyright" line and a pointer to where the full notice is found.
Copyright (C)
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see .
Also add information on how to contact you by electronic and paper mail.
If the program does terminal interaction, make it output a short
notice like this when it starts in an interactive mode:
Copyright (C)
This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
The hypothetical commands `show w' and `show c' should show the appropriate
parts of the General Public License. Of course, your program's commands
might be different; for a GUI interface, you would use an "about box".
You should also get your employer (if you work as a programmer) or school,
if any, to sign a "copyright disclaimer" for the program, if necessary.
For more information on this, and how to apply and follow the GNU GPL, see
.
The GNU General Public License does not permit incorporating your program
into proprietary programs. If your program is a subroutine library, you
may consider it more useful to permit linking proprietary applications with
the library. If this is what you want to do, use the GNU Lesser General
Public License instead of this License. But first, please read
.
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/Makefile 0000664 0000000 0000000 00000001624 14502055570 0021277 0 ustar 00root root 0000000 0000000 # Build ghdl module for yosys
# Name or path to the ghdl executable.
GHDL=ghdl
YOSYS_CONFIG=yosys-config
SOEXT=so
CFLAGS ?= -O
LIBGHDL_LIB:=$(shell $(GHDL) --libghdl-library-path)
LIBGHDL_INC:=$(shell $(GHDL) --libghdl-include-dir)
ALL_LDFLAGS=$(LIBGHDL_LIB) -Wl,-rpath,$(dir $(LIBGHDL_LIB)) $(LDFLAGS)
PLUGINDIR:=$(shell $(YOSYS_CONFIG) --datdir)/plugins
ALL_CFLAGS=-fPIC -DYOSYS_ENABLE_GHDL -I$(LIBGHDL_INC) $(CFLAGS)
VER_HASH=$(shell git rev-parse --short HEAD || echo "unknown")
all: ghdl.$(SOEXT)
ghdl.$(SOEXT): ghdl.o
$(YOSYS_CONFIG) --build $@ $< -shared $(ALL_LDFLAGS)
ghdl.o: src/ghdl.cc
$(YOSYS_CONFIG) --exec --cxx -c --cxxflags -o $@ $< $(ALL_CFLAGS) -DGHDL_VER_HASH="\"$(VER_HASH)\""
clean: force
$(RM) -f ghdl.$(SOEXT) ghdl.o
install: ghdl.$(SOEXT)
$(YOSYS_CONFIG) --exec mkdir -p $(DESTDIR)$(PLUGINDIR)
$(YOSYS_CONFIG) --exec cp $< $(DESTDIR)$(PLUGINDIR)
-include src/ghdl.d
force:
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/README.md 0000664 0000000 0000000 00000015257 14502055570 0021125 0 ustar 00root root 0000000 0000000
# ghdl-yosys-plugin: VHDL synthesis (based on [GHDL](https://github.com/ghdl/ghdl) and [Yosys](https://github.com/YosysHQ/yosys))
**This is experimental and work in progress!** See [ghdl.github.io/ghdl: Using/Synthesis](http://ghdl.github.io/ghdl/using/Synthesis.html).
> TODO: Create table with features of VHDL that are supported, WIP and pending.
## Build as a module (shared library)
> On Windows, Yosys does not support loading modules dynamically. Therefore, this build approach is not possible. See [*Build as part of Yosys*](#build-as-part-of-yosys-not-recommended) below.
- Get and install [Yosys](https://github.com/YosysHQ/yosys).
- Get sources, build and install [GHDL](https://github.com/ghdl/ghdl). Ensure that GHDL is configured with synthesis features (enabled by default since v0.37). See [Building GHDL](https://github.com/ghdl/ghdl#building-ghdl).
> NOTE: GHDL must be built with at least version of 8 GNAT (`gnat-8`).
> HINT: The default build prefix is `/usr/local`. Sudo permission might be required to install tools there.
- Get and build ghdl-yosys-plugin: `make`.
> HINT: If ghdl is not available in the PATH, set `GHDL` explicitly, e.g.: `make GHDL=/my/path/to/ghdl`.
The output is a shared library (`ghdl.so` on GNU/Linux), which can be used directly: `yosys -m ghdl.so`.
To install the module, the library must be copied to `YOSYS_PREFIX/share/yosys/plugins/ghdl.so`, where `YOSYS_PREFIX` is the installation path of yosys. This can be achieved through a make target: `make install`.
Alternatively, the shared library can be copied/installed along with GHDL:
```sh
cp ghdl.so "$GHDL_PREFIX/lib/ghdl_yosys.so"
yosys-config --exec mkdir -p --datdir/plugins
yosys-config --exec ln -s "$GHDL_PREFIX/lib/ghdl_yosys.so" --datdir/plugins/ghdl.so
```
## Build as part of yosys (not recommended)
- Get and build GHDL as in the previous section.
- Get [Yosys](https://github.com/YosysHQ/yosys) sources.
- Get ghdl-yosys-plugin and:
- Copy `src/*` to `yosys/frontends/ghdl`.
- Configure Yosys by adding (to) `Makefile.conf`:
```makefile
ENABLE_GHDL := 1
GHDL_PREFIX :=
```
- Build and install Yosys.
## Pre-built packages
Some projects provide pre-built packages including GHDL, Yosys and ghdl-yosys-plugin. Unless you have specific requirements (targeting a different arch, OS, build options...), we suggest using one of the following solutions before building ghdl-yosys-plugin from sources.
- [open-tool-forge/fpga-toolchain](https://github.com/open-tool-forge/fpga-toolchain) provides tarballs for GNU/Linux, Windows or macOS, including statically built EDA tools. Packages are available for x86 or amd64.
- On Windows, there is a package group in [MSYS2](https://www.msys2.org/) repositories named [mingw-w64-x86_64-eda](https://packages.msys2.org/group/mingw-w64-x86_64-eda)|[mingw-w64-i686-eda](https://packages.msys2.org/group/mingw-w64-i686-eda). See [hdl/MINGW-packages](https://github.com/hdl/MINGW-packages).
## Usage
Example for IceStick, using GHDL, Yosys, nextpnr and icestorm:
```sh
cd examples/icestick/leds/
# Analyse VHDL sources
ghdl -a leds.vhdl
ghdl -a spin1.vhdl
# Synthesize the design.
# NOTE: if GHDL is built as a module, set MODULE to '-m ghdl' or '-m path/to/ghdl.so',
# otherwise, unset it.
yosys $MODULE -p 'ghdl leds; synth_ice40 -json leds.json'
# P&R
nextpnr-ice40 --package hx1k --pcf leds.pcf --asc leds.asc --json leds.json
# Generate bitstream
icepack leds.asc leds.bin
# Program FPGA
iceprog leds.bin
```
Alternatively, it is possible to analyze, elaborate and synthesize VHDL sources at once, instead of calling GHDL and Yosys in two steps. In this example:
```
yosys $MODULE -p 'ghdl leds.vhdl spin1.vhdl -e leds; synth_ice40 -json leds.json'
```
## Containers
Container (aka Docker/Podman) image [`hdlc/ghdl:yosys`](https://hub.docker.com/r/hdlc/ghdl/tags) includes GHDL, Yosys and the ghdl-yosys-plugin module (shared library). These can be used to synthesize designs straightaway. For example:
```sh
docker run --rm -t \
-v $(pwd)/examples/icestick/leds:/src \
-w /src \
hdlc/ghdl:yosys \
yosys -m ghdl -p 'ghdl leds.vhdl blink.vhdl -e leds; synth_ice40 -json leds.json'
```
> In a system with [docker](https://docs.docker.com/install) installed, the image is automatically downloaded the first time invoked.
Furthermore, the snippet above can be extended in order to P&R the design with [nextpnr](https://github.com/YosysHQ/nextpnr) and generate a bitstream with [icestorm](https://github.com/cliffordwolf/icestorm) tools:
```sh
cd examples/icestick/leds/
DOCKER_CMD="$(command -v winpty) docker run --rm -it -v /$(pwd)://wrk -w //wrk"
$DOCKER_CMD hdlc/ghdl:yosys yosys -m ghdl -p 'ghdl leds.vhdl rotate4.vhdl -e leds; synth_ice40 -json leds.json'
$DOCKER_CMD hdlc/nextpnr:ice40 nextpnr-ice40 --hx1k --json leds.json --pcf leds.pcf --asc leds.asc
$DOCKER_CMD hdlc/icestorm icepack leds.asc leds.bin
iceprog leds.bin
```
See [hdl/containers](https://github.com/hdl/containers) for further info about containers including other EDA tools.
> NOTE: on GNU/Linux, it should be possible to use board programming tools through `hdlc/icestorm`. On Windows and macOS, accessing USB/COM ports of the host from containers is challenging. Therefore, board programming tools need to be available on the host. Windows users can find several board programming tools available as [MSYS2](https://www.msys2.org/) packages. See [mingw-w64-x86_64-eda](https://packages.msys2.org/group/mingw-w64-x86_64-eda)|[mingw-w64-i686-eda](https://packages.msys2.org/group/mingw-w64-i686-eda) and [hdl/MINGW-packages](https://github.com/hdl/MINGW-packages).
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/ci.sh 0000775 0000000 0000000 00000005230 14502055570 0020566 0 ustar 00root root 0000000 0000000 #!/bin/sh
set -e
cd "$(dirname $0)"
. ./utils.sh
#--
do_ghdl () {
gstart "[Build] tmp" "$ANSI_MAGENTA"
docker build -t tmp - <<-EOF
FROM ghdl/build:bullseye-mcode AS build
RUN apt-get update -qq && DEBIAN_FRONTEND=noninteractive apt-get -y install --no-install-recommends \
ca-certificates \
git \
&& update-ca-certificates \
&& git clone https://github.com/ghdl/ghdl \
&& cd ghdl \
&& ./configure --enable-libghdl --enable-synth \
&& make all \
&& make DESTDIR=/opt/ghdl install
FROM scratch
COPY --from=build /opt/ghdl /ghdl
EOF
export GHDL_PKG_IMAGE=tmp
gend
}
#--
do_plugin () {
# To build latest GHDL from sources, uncomment the following line
#do_ghdl
gstart "[Build] ghdl/synth:beta" "$ANSI_MAGENTA"
docker build -t ghdl/synth:beta . -f- <<-EOF
ARG REGISTRY='gcr.io/hdl-containers/debian/bullseye'
#---
# WORKAROUND: this is required because 'COPY --from' does not support ARGs
FROM \$REGISTRY/pkg/ghdl AS pkg-ghdl
FROM \$REGISTRY/yosys AS base
RUN apt-get update -qq \
&& DEBIAN_FRONTEND=noninteractive apt-get -y install --no-install-recommends \
libgnat-9 \
&& apt-get autoclean && apt-get clean && apt-get -y autoremove \
&& rm -rf /var/lib/apt/lists
COPY --from=${GHDL_PKG_IMAGE:-pkg-ghdl} /ghdl /
#---
FROM base AS build
COPY . /ghdlsynth
RUN cd /ghdlsynth \
&& make \
&& cp ghdl.so /tmp/ghdl_yosys.so
#---
FROM base
COPY --from=build /tmp/ghdl_yosys.so /usr/local/lib/
RUN yosys-config --exec mkdir -p --datdir/plugins \
&& yosys-config --exec ln -s /usr/local/lib/ghdl_yosys.so --datdir/plugins/ghdl.so
EOF
gend
}
#---
do_formal () {
gstart "[Build] ghdl/synth:formal" "$ANSI_MAGENTA"
docker build -t ghdl/synth:formal . -f- <<-EOF
ARG REGISTRY='gcr.io/hdl-containers/debian/bullseye'
#--
# WORKAROUND: this is required because 'COPY --from' does not support ARGs
FROM \$REGISTRY/pkg/z3 AS pkg-z3
FROM \$REGISTRY/pkg/symbiyosys AS pkg-symbiyosys
FROM ghdl/synth:beta
COPY --from=pkg-z3 /z3 /
COPY --from=pkg-symbiyosys /symbiyosys /
RUN apt-get update -qq \
&& DEBIAN_FRONTEND=noninteractive apt-get -y install --no-install-recommends \
python3 \
python3-pip \
&& apt-get autoclean && apt-get clean && apt-get -y autoremove \
&& rm -rf /var/lib/apt/lists/*\
&& python3 -m pip install click --progress-bar off
EOF
gend
}
#---
do_test () {
printf "${ANSI_MAGENTA}[Test] testsuite ${ANSI_NOCOLOR}\n"
docker run --rm -t -e CI -v /$(pwd)://src -w //src -e YOSYS='yosys -m ghdl' ghdl/synth:formal bash -c "$(cat <
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FifoBuffer is
generic (
ADDR_W : natural := 6;
DATA_W : natural := 16;
EXTRA_REGISTER : boolean := false;
SYN_RAMTYPE : string := "block_ram"
);
port (
-- Write enable
wren : in std_logic;
idata : in unsigned(DATA_W-1 downto 0);
iready : out std_logic;
-- Data stream output:
odata : out unsigned(DATA_W-1 downto 0);
oready : out std_logic;
rden : in std_logic;
err : out std_logic;
reset : in std_logic;
clk : in std_logic
);
end entity FifoBuffer;
architecture behaviour of FifoBuffer is
constant FULL_COUNT : unsigned(ADDR_W-1 downto 0) := (others => '1');
constant ZERO_COUNT : unsigned(ADDR_W-1 downto 0) := (others => '0');
constant INACTIVE_WRITE_PORT :
unsigned(DATA_W-1 downto 0) := (others => '0');
signal iptr : unsigned(ADDR_W-1 downto 0) := ZERO_COUNT;
signal optr : unsigned(ADDR_W-1 downto 0) := ZERO_COUNT;
signal next_iptr : unsigned(ADDR_W-1 downto 0) := ZERO_COUNT;
signal next_optr : unsigned(ADDR_W-1 downto 0) := ZERO_COUNT;
signal over : std_logic := '0';
signal rdata : unsigned(DATA_W-1 downto 0);
type state_t is (S_IDLE, S_READY, S_FULL, S_ERROR);
-- GHDLSYNTH_QUIRK
-- Needs this initialized, otherwise gets 'optimized away'
signal state : state_t := S_IDLE;
-- If we don't initialize, yosys feels like it wants to recode.
-- signal state : state_t;
signal int_full : std_logic; -- Internal "full" flag
signal int_rden : std_logic;
signal int_rden_d : std_logic;
signal maybe_full : std_logic;
signal maybe_empty : std_logic;
signal dready : std_logic;
component bram_2psync is
generic (
ADDR : natural := 6;
DATA : natural := 16
);
port (
-- Port A
a_we : in std_logic;
a_addr : in unsigned(ADDR-1 downto 0);
a_write : in unsigned(DATA-1 downto 0);
a_read : out unsigned(DATA-1 downto 0);
-- Port B
b_we : in std_logic;
b_addr : in unsigned(ADDR-1 downto 0);
b_write : in unsigned(DATA-1 downto 0);
b_read : out unsigned(DATA-1 downto 0);
clk : in std_logic
);
end component bram_2psync;
begin
count:
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
optr <= ZERO_COUNT;
iptr <= ZERO_COUNT;
else
if wren = '1' then
iptr <= next_iptr;
end if;
if int_rden = '1' then
optr <= next_optr;
end if;
end if;
end if;
end process;
next_iptr <= iptr + 1;
next_optr <= optr + 1;
-- These are ambiguous signals, need evaluation of wren/rden!
maybe_full <= '1' when optr = next_iptr else '0';
maybe_empty <= '1' when iptr = next_optr else '0';
dready <= '1' when state = S_READY or state = S_FULL else '0';
fsm:
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
state <= S_IDLE;
else
case state is
when S_IDLE =>
if wren = '1' then
state <= S_READY;
else
state <= S_IDLE;
end if;
when S_READY =>
if wren = '1' then
-- We're just getting full
if maybe_full = '1' and int_rden = '0' then
state <= S_FULL;
end if;
-- We're just getting empty
elsif maybe_empty = '1' and int_rden = '1' then
state <= S_IDLE;
end if;
-- All other conditions: Remain S_READY
when S_FULL =>
if wren = '1' then
-- It is actually allowed to read and write
-- simultaneously while FULL.
if int_rden = '0' then
state <= S_ERROR;
else
state <= S_FULL;
end if;
elsif int_rden = '1' then
state <= S_READY;
else
state <= S_FULL;
end if;
when S_ERROR =>
end case;
end if;
end if;
end process;
over <= '1' when state = S_ERROR else '0';
err <= over;
ram:
bram_2psync
generic map ( ADDR => ADDR_W, DATA => DATA_W)
port map (
a_we => '0',
a_addr => optr,
a_write => INACTIVE_WRITE_PORT,
a_read => rdata,
b_we => wren,
b_addr => iptr,
b_write => idata,
b_read => open,
clk => clk
);
-- This section appends a little pre-read unit to the FIFO
-- to allow higher speed on most architectures.
gen_register:
if EXTRA_REGISTER generate
int_rden <= (not int_full or rden) and dready;
preread:
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
int_full <= '0';
elsif dready = '1' then
if int_full = '0' then
int_full <= '1';
oready <= '1';
end if;
elsif int_full = '1' then
if rden = '1' then
oready <= '0';
int_full <= '0';
else
oready <= '1';
end if;
else
oready <= '0';
end if;
int_rden_d <= int_rden;
if int_rden_d = '1' then
odata <= rdata;
end if;
end if;
end process;
end generate;
gen_direct:
if not EXTRA_REGISTER generate
int_full <= '1' when state = S_FULL else '0';
int_rden <= rden;
odata <= rdata;
oready <= dready;
end generate;
iready <= not int_full;
-- synthesis translate_off
-- Synplify barfs on this, we need to comment out the whole shlorm.
errguard:
process(clk)
begin
if rising_edge(clk) then
if over = '1' then
assert false report "FIFO overrun in " & behaviour'path_name
severity failure;
end if;
end if;
end process;
-- synthesis translate_on
end behaviour;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/ecp5_versa/libram.vhdl 0000664 0000000 0000000 00000012534 14502055570 0025640 0 ustar 00root root 0000000 0000000 -- Common RAM library package
-- For MIPS specific RAM package: see pkg_ram.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package ram is
-- Unconstrained 16 bit RAM initialization type
type ram16_init_t is array(natural range <>) of
unsigned(15 downto 0);
-- Unconstrained 32 bit RAM initialization type
type ram32_init_t is array(natural range <>) of
unsigned(31 downto 0);
component DPRAM16_init is
generic (
ADDR_W : natural := 6;
DATA_W : natural := 16;
INIT_DATA : ram16_init_t;
SYN_RAMTYPE : string := "block_ram"
);
port (
clk : in std_logic;
-- Port A
a_we : in std_logic;
a_addr : in unsigned(ADDR_W-1 downto 0);
a_write : in unsigned(DATA_W-1 downto 0);
a_read : out unsigned(DATA_W-1 downto 0);
-- Port B
b_we : in std_logic;
b_addr : in unsigned(ADDR_W-1 downto 0);
b_write : in unsigned(DATA_W-1 downto 0);
b_read : out unsigned(DATA_W-1 downto 0)
);
end component DPRAM16_init;
component DPRAM16_init_ce is
generic (
ADDR_W : natural := 6;
DATA_W : natural := 16;
INIT_DATA : ram16_init_t;
SYN_RAMTYPE : string := "block_ram"
);
port (
clk : in std_logic;
-- Port A
a_ce : in std_logic;
a_we : in std_logic;
a_addr : in unsigned(ADDR_W-1 downto 0);
a_write : in unsigned(DATA_W-1 downto 0);
a_read : out unsigned(DATA_W-1 downto 0);
-- Port B
b_ce : in std_logic;
b_we : in std_logic;
b_addr : in unsigned(ADDR_W-1 downto 0);
b_write : in unsigned(DATA_W-1 downto 0);
b_read : out unsigned(DATA_W-1 downto 0)
);
end component DPRAM16_init_ce;
component DPRAM16_init_hex_ce is
generic (
ADDR_W : natural := 6;
DATA_W : natural := 16;
INIT_DATA : string := "mem.hex";
SYN_RAMTYPE : string := "block_ram"
);
port (
-- Port A
a_clk : in std_logic;
a_ce : in std_logic;
a_we : in std_logic;
a_addr : in unsigned(ADDR_W-1 downto 0);
a_write : in unsigned(DATA_W-1 downto 0);
a_read : out unsigned(DATA_W-1 downto 0);
-- Port B
b_clk : in std_logic;
b_ce : in std_logic;
b_we : in std_logic;
b_addr : in unsigned(ADDR_W-1 downto 0);
b_write : in unsigned(DATA_W-1 downto 0);
b_read : out unsigned(DATA_W-1 downto 0)
);
end component DPRAM16_init_hex_ce;
component DPRAM_init_hex is
generic (
ADDR_W : natural := 6;
DATA_W : natural := 32;
INIT_DATA : string := "mem32.hex";
SYN_RAMTYPE : string := "block_ram"
);
port (
clk : in std_logic;
-- Port A
a_ce : in std_logic;
a_we : in std_logic;
a_addr : in unsigned(ADDR_W-1 downto 0);
a_write : in unsigned(DATA_W-1 downto 0);
a_read : out unsigned(DATA_W-1 downto 0);
-- Port B
b_ce : in std_logic;
b_we : in std_logic;
b_addr : in unsigned(ADDR_W-1 downto 0);
b_write : in unsigned(DATA_W-1 downto 0);
b_read : out unsigned(DATA_W-1 downto 0)
);
end component DPRAM_init_hex;
component DPRAM32_init is
generic (
ADDR_W : natural := 6;
DATA_W : natural := 32;
INIT_DATA : ram32_init_t;
SYN_RAMTYPE : string := "block_ram"
);
port (
clk : in std_logic;
-- Port A
a_we : in std_logic;
a_addr : in unsigned(ADDR_W-1 downto 0);
a_write : in unsigned(DATA_W-1 downto 0);
a_read : out unsigned(DATA_W-1 downto 0);
-- Port B
b_we : in std_logic;
b_addr : in unsigned(ADDR_W-1 downto 0);
b_write : in unsigned(DATA_W-1 downto 0);
b_read : out unsigned(DATA_W-1 downto 0)
);
end component DPRAM32_init;
component DPRAM is
generic (
ADDR_W : natural := 6;
DATA_W : natural := 16;
EN_BYPASS : boolean := false;
SYN_RAMTYPE : string := "block_ram"
);
port (
clk : in std_logic;
-- Port A
a_we : in std_logic;
a_addr : in unsigned(ADDR_W-1 downto 0);
a_write : in unsigned(DATA_W-1 downto 0);
a_read : out unsigned(DATA_W-1 downto 0);
-- Port B
b_we : in std_logic;
b_addr : in unsigned(ADDR_W-1 downto 0);
b_write : in unsigned(DATA_W-1 downto 0);
b_read : out unsigned(DATA_W-1 downto 0)
);
end component DPRAM;
component DPRAM_clk2
generic(
ADDR_W : natural := 6;
DATA_W : natural := 16;
EN_BYPASS : boolean := true;
SYN_RAMTYPE : string := "block_ram"
);
port(
a_clk : in std_logic;
-- Port A
a_we : in std_logic;
a_addr : in unsigned(ADDR_W-1 downto 0);
a_write : in unsigned(DATA_W-1 downto 0);
a_read : out unsigned(DATA_W-1 downto 0);
-- Port B
b_clk : in std_logic;
b_we : in std_logic;
b_addr : in unsigned(ADDR_W-1 downto 0);
b_write : in unsigned(DATA_W-1 downto 0);
b_read : out unsigned(DATA_W-1 downto 0)
);
end component;
component bram_2psync is
generic (
ADDR_W : natural := 6;
DATA_W : natural := 16;
SYN_RAMTYPE : string := "block_ram"
);
port (
-- Port A
a_we : in std_logic;
a_addr : in unsigned(ADDR_W-1 downto 0);
a_write : in unsigned(DATA_W-1 downto 0);
a_read : out unsigned(DATA_W-1 downto 0);
-- Port B
b_we : in std_logic;
b_addr : in unsigned(ADDR_W-1 downto 0);
b_write : in unsigned(DATA_W-1 downto 0);
b_read : out unsigned(DATA_W-1 downto 0);
clk : in std_logic
);
end component bram_2psync;
end package;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/ecp5_versa/pll_mac.vhd 0000664 0000000 0000000 00000007201 14502055570 0025620 0 ustar 00root root 0000000 0000000 -- VHDL netlist generated by SCUBA Diamond (64-bit) 3.8.0.115.3
-- Module Version: 5.7
--/usr/local/diamond/3.8_x64/ispfpga/bin/lin64/scuba -w -n pll_mac -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 100.00 -fclkop 125 -fclkop_tol 0.0 -fclkos 25 -fclkos_tol 0.0 -phases 0 -fclkos2 50 -fclkos2_tol 0.0 -phases2 0 -fclkos3 75 -fclkos3_tol 0.0 -phases3 0 -phase_cntl STATIC -lock -fb_mode 1 -fdc /home/strubi/src/masocist/syn/lattice/versaECP5G/ipcores/pll/pll_mac/pll_mac.fdc
-- Wed May 10 17:35:30 2017
library IEEE;
use IEEE.std_logic_1164.all;
library ecp5um;
use ecp5um.components.all;
entity pll_mac is
port (
CLKI: in std_logic;
CLKOP: out std_logic;
CLKOS: out std_logic;
CLKOS2: out std_logic;
CLKOS3: out std_logic;
LOCK: out std_logic);
end pll_mac;
architecture Structure of pll_mac is
-- internal signal declarations
signal REFCLK: std_logic;
signal CLKOS3_t: std_logic;
signal CLKOS2_t: std_logic;
signal CLKOS_t: std_logic;
signal CLKOP_t: std_logic;
signal scuba_vhi: std_logic;
signal scuba_vlo: std_logic;
attribute FREQUENCY_PIN_CLKOS3 : string;
attribute FREQUENCY_PIN_CLKOS2 : string;
attribute FREQUENCY_PIN_CLKOS : string;
attribute FREQUENCY_PIN_CLKOP : string;
attribute FREQUENCY_PIN_CLKI : string;
attribute ICP_CURRENT : string;
attribute LPF_RESISTOR : string;
attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "75.000000";
attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "50.000000";
attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "25.000000";
attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "125.000000";
attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000";
attribute ICP_CURRENT of PLLInst_0 : label is "7";
attribute LPF_RESISTOR of PLLInst_0 : label is "16";
attribute syn_keep : boolean;
attribute NGD_DRC_MASK : integer;
attribute NGD_DRC_MASK of Structure : architecture is 1;
begin
-- component instantiation statements
scuba_vhi_inst: VHI
port map (Z=>scuba_vhi);
scuba_vlo_inst: VLO
port map (Z=>scuba_vlo);
PLLInst_0: EHXPLLL
generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 9, CLKOS2_FPHASE=> 0,
CLKOS2_CPHASE=> 14, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 29,
CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 5, PLL_LOCK_MODE=> 0,
CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING",
CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING",
OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "ENABLED",
OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "ENABLED",
OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "ENABLED",
OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 10,
CLKOS2_DIV=> 15, CLKOS_DIV=> 30, CLKOP_DIV=> 6, CLKFB_DIV=> 5,
CLKI_DIV=> 4, FEEDBK_PATH=> "CLKOP")
port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo,
PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo,
STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo,
ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo,
ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t,
CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>LOCK,
INTLOCK=>open, REFCLK=>REFCLK, CLKINTFB=>open);
CLKOS3 <= CLKOS3_t;
CLKOS2 <= CLKOS2_t;
CLKOS <= CLKOS_t;
CLKOP <= CLKOP_t;
end Structure;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/ecp5_versa/soc_iomap_pkg.vhdl 0000664 0000000 0000000 00000007625 14502055570 0027211 0 ustar 00root root 0000000 0000000 -- File generated by gensoc 394864f
-- (c) 2012-2018, Martin Strubel
--
-- Changes to this file will be lost. Edit the source file.
--
-- LICENSE: Evaluation license. Not for commercial usage.
----------------------------------------------------------------------------
-- This VHDL package is generated from
-- ../gen/syn-versa_ecp5/neo430-versa_ecp5.xml
-- Stylesheet: vhdlregs v0.1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Header:
package system_map is
-- HW revision tag. Use in your code to sync with firmware.
constant HWREV_system_map_MAJOR : natural := 0;
constant HWREV_system_map_MINOR : natural := 0;
constant HWREV_system_map_EXT : string := "";
subtype regaddr_t is unsigned(7 downto 0);
subtype regaddr16_t is unsigned(15 downto 0);
subtype REG_SIZE1B is integer range 7 downto 0;
subtype REG_SIZE2B is integer range 15 downto 0;
subtype REG_SIZE3B is integer range 23 downto 0;
subtype REG_SIZE4B is integer range 31 downto 0;
-- Register and bitfield constants:
-------------------------------------------------------------------------
-- Address segment 'UART'
-- Offset:
-- UART Control register
constant R_UART_UART_CONTROL : regaddr_t := x"00";
-- (16x) Clock divider
subtype BV_UART_CLKDIV is integer range 9 downto 0;
-- Enable receive IRQ
constant B_RX_IRQ_ENABLE : natural := 14;
-- '1': Reset UART. Clear to run.
constant B_UART_RESET : natural := 15;
-- UART status register
constant R_UART_UART_STATUS : regaddr_t := x"02";
-- Set when data ready in RX FIFO
constant B_RXREADY : natural := 0;
-- Set when TX FIFO ready for data
constant B_TXREADY : natural := 1;
-- '1' when TX in progress
constant B_TXBUSY : natural := 2;
-- Sticky framing error. Set when stop bit not null. Reset by UART_RESET.
constant B_FRERR : natural := 5;
-- Transmitter FIFO overrun. Cleared by UART_RESET.
constant B_TXOVR : natural := 6;
-- Receiver FIFO overrun. Cleared by UART_RESET.
constant B_RXOVR : natural := 7;
-- RX bit counter
subtype BV_BITCOUNT is integer range 10 downto 8;
-- UART receiver register
constant R_UART_UART_RXR : regaddr_t := x"04";
-- UART receive data
subtype BV_RXDATA is integer range 7 downto 0;
-- 1 when data valid (mirror of RXREADY bit)
constant B_DVALID : natural := 8;
-- UART transmitter register
constant R_UART_UART_TXR : regaddr_t := x"04";
type uart_ReadPort is record
--! Exported value for register 'R_UART_UART_STATUS'
--! Exported value for bit (vector) 'RXREADY'
rxready : std_logic;
--! Exported value for bit (vector) 'TXREADY'
txready : std_logic;
--! Exported value for bit (vector) 'TXBUSY'
txbusy : std_logic;
--! Exported value for bit (vector) 'FRERR'
frerr : std_logic;
--! Exported value for bit (vector) 'TXOVR'
txovr : std_logic;
--! Exported value for bit (vector) 'RXOVR'
rxovr : std_logic;
--! Exported value for bit (vector) 'BITCOUNT'
bitcount : unsigned(BV_BITCOUNT);
--! Exported value for register 'R_UART_UART_RXR'
--! Exported value for bit (vector) 'RXDATA'
rxdata : unsigned(BV_RXDATA);
--! Exported value for bit (vector) 'DVALID'
dvalid : std_logic;
end record;
type uart_WritePort is record
--! Exported value for register 'R_UART_UART_CONTROL'
--! Exported value for bit (vector) 'UART_CLKDIV'
uart_clkdiv : unsigned(BV_UART_CLKDIV);
--! Exported value for bit (vector) 'RX_IRQ_ENABLE'
rx_irq_enable : std_logic;
--! Exported value for bit (vector) 'UART_RESET'
uart_reset : std_logic;
--! Exported value for register 'R_UART_UART_TXR'
uart_txr : unsigned(REG_SIZE1B);
--! Notify access of Register 'UART_RXR'
select_uart_rxr : std_logic;
--! Notify access of Register 'UART_TXR'
select_uart_txr : std_logic;
end record;
end system_map;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/ecp5_versa/uart.vhdl 0000664 0000000 0000000 00000007507 14502055570 0025351 0 ustar 00root root 0000000 0000000 -- Simple UART core implementation
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.system_map.all;
entity uart_core is
generic (
FIFO_DEPTH : natural := 6;
-- Note: Currently ineffective. See library/wrappers/bram.v
SYN_RAMTYPE : string := "distributed"
);
port (
tx : out std_logic;
rx : in std_logic;
rxirq : out std_logic;
ctrl : in uart_WritePort;
stat : out uart_ReadPort;
clk : in std_logic
);
end uart_core;
architecture behaviour of uart_core is
signal count16 : unsigned(4-1 downto 0) := (others => '0');
signal counter : unsigned(16-1 downto 0) := (others => '0');
signal strobe_rx : std_logic;
signal rxd : unsigned(7 downto 0);
signal txd : unsigned(7 downto 0);
signal rxfifo_data : unsigned(7 downto 0);
signal rxfifo_rden : std_logic;
signal txfifo_wren : std_logic;
signal rxdata_ready : std_logic;
signal txfifo_dready : std_logic;
signal txfifo_strobe : std_logic;
signal clk16_enable : std_logic;
signal txclk_enable : std_logic;
component FifoBuffer is
generic (
ADDR_W : natural := 6;
DATA_W : natural := 16;
EXTRA_REGISTER : boolean := false;
SYN_RAMTYPE : string := "block_ram"
);
port (
-- Write enable
wren : in std_logic;
idata : in unsigned(DATA_W-1 downto 0);
iready : out std_logic;
-- Data stream output:
odata : out unsigned(DATA_W-1 downto 0);
oready : out std_logic;
rden : in std_logic;
err : out std_logic;
-- debug : out unsigned(16-1 downto 0);
reset : in std_logic;
clk : in std_logic
);
end component FifoBuffer;
begin
-- Clock divider:
clkdiv:
process (clk)
begin
if rising_edge(clk) then
clk16_enable <= '0';
txclk_enable <= '0';
-- Important to reset, otherwise, the counter might run away...
if ctrl.uart_reset = '1' then
counter <= (others => '0');
elsif counter = ctrl.uart_clkdiv then
counter <= (others => '0');
clk16_enable <= '1';
count16 <= count16 + 1;
if count16 = "1111" then
txclk_enable <= '1';
end if;
else
counter <= counter + 1;
end if;
end if;
end process;
rxfifo_rden <= ctrl.select_uart_rxr and rxdata_ready;
txfifo_wren <= ctrl.select_uart_txr;
uart_rx: entity work.UARTrx
port map (
d_bitcount => stat.bitcount,
rx => rx,
-- Data
err_frame => stat.frerr,
data => rxd,
strobe => strobe_rx,
reset => ctrl.uart_reset,
clk16en => clk16_enable,
clk => clk
);
uart_tx:
entity work.UARTtx
port map (
busy => stat.txbusy,
data => txd,
data_ready => txfifo_dready,
data_out_en => txfifo_strobe,
tx => tx,
reset => ctrl.uart_reset,
txclken => txclk_enable,
clk => clk
);
rxfifo:
FifoBuffer
generic map (
DATA_W => 8,
ADDR_W => FIFO_DEPTH,
SYN_RAMTYPE => SYN_RAMTYPE
)
port map (
wren => strobe_rx,
idata => rxd,
iready => open,
odata => rxfifo_data,
oready => rxdata_ready,
rden => rxfifo_rden,
err => stat.rxovr,
reset => ctrl.uart_reset,
clk => clk
);
stat.rxdata <= rxfifo_data;
stat.dvalid <= rxdata_ready;
stat.rxready <= rxdata_ready;
rxirq <= rxdata_ready and ctrl.rx_irq_enable;
txfifo:
FifoBuffer
generic map (
DATA_W => 8,
ADDR_W => FIFO_DEPTH,
SYN_RAMTYPE => SYN_RAMTYPE
)
port map (
wren => txfifo_wren,
idata => ctrl.uart_txr,
iready => stat.txready,
odata => txd,
oready => txfifo_dready,
rden => txfifo_strobe,
err => stat.txovr,
reset => ctrl.uart_reset,
clk => clk
);
end behaviour;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/ecp5_versa/uart_rx.vhdl 0000664 0000000 0000000 00000011336 14502055570 0026055 0 ustar 00root root 0000000 0000000 -- UART RX implementation
--
-- (c) 06/2008, Martin Strubel
-- This module implements a standard UART receive channel.
-- The clock divider has to be chosen such that the master clock
-- divided by k = (2 * (div + 1)) is the 16 fold of the desired baud
-- rate.
-- On reception of a start bit, the lock counter is starting and the
-- signal is sampled at the position of each lock marker which is at
-- 'count' = 8 by default.
-- Once a byte has arrived, it has to be read immediately by the
-- client (FIFO assumed). Valid data must be clocked on rising edge of
-- the 'strobe' pin from the 'data' bus.
-- This is a very primitive implementation:
-- * No Parity and other checks
-- * No debouncing. Must be done on top level input.
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all; -- for TO_UNSIGNED
entity UARTrx is
generic (
CLKDIV2 : positive := 3 -- power of 2 of (clkdiv)
);
port (
d_bitcount : out unsigned(2 downto 0);
rx : in std_logic; -- RX UART
err_frame : out std_logic;
-- Data
data : out unsigned(7 downto 0);
strobe : out std_logic; -- Data valid strobe pulse
reset : in std_logic; -- Reset pin, LOW active
clk16en : in std_logic; -- UART clock enable
clk : in std_logic -- UART clock x 16
);
end UARTrx;
architecture behaviour of UARTrx is
-- State machine states:
-- IDLE: Waiting for start bit
-- START: Getting start bit
-- SHIFT: Shifting data
-- STOP: Getting stop bit ( No longer used, identical with S_IDLE )
type uart_state_t is (S_IDLE, S_START, S_SHIFT, S_STOP);
signal state : uart_state_t := S_IDLE;
signal rxd : std_logic;
signal frame_err : std_logic := '0'; -- Frame Error flag
signal rxtrigger : std_logic;
-- signal start : std_logic := '0';
signal strobeq : std_logic;
signal strobe_i : std_logic;
signal bitcount : unsigned(2 downto 0) := "000"; -- Bit counter
-- This is the clk counter that is used to synchronize to the
-- middle of a data bit signal
signal count : unsigned(CLKDIV2 downto 0) := (others => '0');
signal is_count_begin : std_logic; -- When count == 0
signal is_count_mid : std_logic; -- When count == 8
-- Shift register:
signal dsr : unsigned(7 downto 0) := x"00";
begin
-- Detect RX start bit (synchronous to clk):
rx_posedge:
process (clk)
begin
if rising_edge(clk) then
if clk16en = '1' then
rxd <= rx;
rxtrigger <= rxd and (not rx);
end if;
end if;
end process;
-- This signal is:
-- HIGH on falling edge
-- LOW on rising edge, LOW when idle
-- It is not latched, thus it can be very short.
generate_rxclk_en:
process (clk)
begin
if rising_edge(clk) then
if clk16en = '1' then
case state is
when S_IDLE => count <= (others => '0');
when others => count <= count + 1;
end case;
end if;
end if;
end process;
is_count_begin <= '1' when count = "1111" else '0';
is_count_mid <= '1' when count = "0111" else '0';
state_decode:
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
state <= S_IDLE;
elsif clk16en = '1' then
case state is
when S_STOP | S_IDLE =>
if rxtrigger = '1' then
state <= S_START;
else
state <= S_IDLE;
end if;
when S_START =>
if is_count_begin = '1' then
state <= S_SHIFT;
end if;
when S_SHIFT =>
if is_count_begin = '1' and bitcount = "111" then
state <= S_STOP;
end if;
when others =>
state <= S_IDLE;
end case;
end if;
end if;
end process;
shift:
process (clk)
begin
if rising_edge(clk) then
if clk16en = '1' and is_count_mid = '1' then
if state = S_SHIFT then
dsr <= rx & dsr(7 downto 1);
end if;
end if;
end if;
end process;
-- Rising edge, when data valid
strobe_i <= '0' when state = S_SHIFT else '1';
-- From this, we generate a clk wide pulse:
tx_strobe:
process (clk)
begin
if rising_edge(clk) then
strobeq <= strobe_i;
data <= dsr;
end if;
end process;
strobe <= not(strobeq) and strobe_i; -- Pulse on rising edge
bitcounter:
process (clk)
begin
if rising_edge(clk) then
if clk16en = '1' and is_count_begin = '1' then
case state is
when S_SHIFT =>
bitcount <= bitcount + 1;
when others =>
bitcount <= "000";
end case;
end if;
end if;
end process;
-- Framing errors:
detect_frerr:
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
frame_err <= '0';
elsif state = S_STOP and is_count_mid = '1' and rx = '0' then
frame_err <= '1';
end if;
end if;
end process;
err_frame <= frame_err;
-- Debugging:
d_bitcount <= bitcount;
end behaviour;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/ecp5_versa/uart_tx.vhdl 0000664 0000000 0000000 00000005310 14502055570 0026052 0 ustar 00root root 0000000 0000000 -- UART TX implementation
--
-- (c) 2008 - 2015, Martin Strubel
--
-- This implementation depends on an external FIFO that can be emptied
-- as follows:
-- When 'data_out_en' == 1 on rising edge of 'clk', 'data' is latched
-- into the shift register and clocked out to the 'tx' pin. The FIFO
-- increments its pointer and asserts the next data byte to 'data'.
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all; -- for TO_UNSIGNED
entity UARTtx is
port (
busy : out std_logic;
data : in unsigned(7 downto 0);
data_ready : in std_logic; -- Data in FIFO ready
data_out_en : out std_logic; -- Data out enable
tx : out std_logic; -- TX UART
reset : in std_logic; -- Reset pin, LOW active
txclken : in std_logic;
clk : in std_logic
);
end UARTtx;
architecture behaviour of UARTtx is
type uart_state_t is (S_IDLE, S_START, S_SHIFT, S_STOP);
signal state : uart_state_t := S_IDLE;
signal nextstate : uart_state_t;
-- Data Shift register:
signal dsr : unsigned(7 downto 0) := x"00";
signal bitcount : unsigned(2 downto 0) := "000"; -- Bit counter
begin
sync_state_advance:
process (clk)
begin
if falling_edge(clk) then
if txclken = '1' then
if reset = '1' then
state <= S_IDLE;
else
state <= nextstate;
end if;
end if;
end if;
end process;
state_decode:
process (state, nextstate, bitcount, data_ready)
begin
case state is
when S_STOP =>
if data_ready = '1' then
nextstate <= S_START;
else
nextstate <= S_IDLE;
end if;
when S_IDLE =>
if data_ready = '1' then
nextstate <= S_START;
else
nextstate <= S_IDLE;
end if;
when S_START =>
nextstate <= S_SHIFT;
when S_SHIFT =>
if bitcount = "000" then
nextstate <= S_STOP;
else
nextstate <= S_SHIFT;
end if;
when others =>
nextstate <= S_IDLE;
end case;
end process;
bitcounter:
process (clk)
begin
if rising_edge(clk) then
if txclken = '1' then
case state is
when S_SHIFT =>
bitcount <= bitcount + 1;
when others =>
bitcount <= "000";
end case;
end if;
end if;
end process;
shift:
process (clk)
begin
if falling_edge(clk) then
data_out_en <= '0';
if txclken = '1' then
case state is
when S_START =>
dsr <= data;
data_out_en <= '1';
tx <= '0';
when S_SHIFT =>
dsr <= '1' & dsr(7 downto 1);
tx <= dsr(0);
when others =>
tx <= '1';
end case;
end if;
end if;
end process;
-- d_state <= std_logic_vector(TO_UNSIGNED(uart_state_t'pos(state), 4));
busy <= '1' when state /= S_IDLE else '0';
end behaviour;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/ecp5_versa/versa_ecp5.lpf 0000664 0000000 0000000 00000010110 14502055570 0026236 0 ustar 00root root 0000000 0000000 FREQUENCY NET "clk_in" 100.000000 MHz ;
IOBUF PORT "clk_in" IO_TYPE=LVDS DIFFRESISTOR=100 ;
# FREQUENCY NET "clk_serdes_c" 156.250000 MHz ;
IOBUF PORT "clk_serdes" IO_TYPE=LVDS DIFFRESISTOR=100 ;
# On board oscillator:
LOCATE COMP "clk_in" SITE "P3" ;
LOCATE COMP "dip_sw[7]" SITE "K20" ;
LOCATE COMP "dip_sw[6]" SITE "J19" ;
LOCATE COMP "dip_sw[5]" SITE "K18" ;
LOCATE COMP "dip_sw[4]" SITE "J18" ;
LOCATE COMP "dip_sw[3]" SITE "F2" ;
LOCATE COMP "dip_sw[2]" SITE "G3" ;
LOCATE COMP "dip_sw[1]" SITE "K3" ;
LOCATE COMP "dip_sw[0]" SITE "H2" ;
# LED bank
LOCATE COMP "oled[0]" SITE "E16" ;
LOCATE COMP "oled[1]" SITE "D17" ;
LOCATE COMP "oled[2]" SITE "D18" ;
LOCATE COMP "oled[3]" SITE "E18" ;
LOCATE COMP "oled[4]" SITE "F17" ;
LOCATE COMP "oled[5]" SITE "F18" ;
LOCATE COMP "oled[6]" SITE "E17" ;
LOCATE COMP "oled[7]" SITE "F16" ;
IOBUF PORT "oled[0]" ;
IOBUF PORT "oled[1]" ;
IOBUF PORT "oled[2]" ;
IOBUF PORT "oled[3]" ;
IOBUF PORT "oled[4]" ;
IOBUF PORT "oled[5]" ;
IOBUF PORT "oled[6]" ;
IOBUF PORT "oled[7]" ;
##################################################################
LOCATE COMP "rxd_uart" SITE "C11" ;
LOCATE COMP "txd_uart" SITE "A11" ;
# Internal SPI port:
LOCATE COMP "spi_mosi" SITE "W2" ;
LOCATE COMP "spi_miso" SITE "V2" ;
LOCATE COMP "spi_cs" SITE "R2" ;
# 14 segment LED I/O
LOCATE COMP "seg[0]" SITE "M20" ;
LOCATE COMP "seg[1]" SITE "L18" ;
LOCATE COMP "seg[2]" SITE "M19" ;
LOCATE COMP "seg[3]" SITE "L16" ;
LOCATE COMP "seg[4]" SITE "L17" ;
LOCATE COMP "seg[5]" SITE "M18" ;
LOCATE COMP "seg[6]" SITE "N16" ;
LOCATE COMP "seg[7]" SITE "M17" ;
LOCATE COMP "seg[8]" SITE "N18" ;
LOCATE COMP "seg[9]" SITE "P17" ;
LOCATE COMP "seg[10]" SITE "N17" ;
LOCATE COMP "seg[11]" SITE "P16" ;
LOCATE COMP "seg[12]" SITE "R16" ;
LOCATE COMP "seg[13]" SITE "R17" ;
LOCATE COMP "segdp" SITE "U1" ;
IOBUF PORT "segdp" PULLMODE=NONE OPENDRAIN=OFF CLAMP=ON DRIVE=8 ;
IOBUF PORT "seg[13]" ;
IOBUF PORT "seg[12]" ;
IOBUF PORT "seg[11]" ;
IOBUF PORT "seg[10]" ;
IOBUF PORT "seg[9]" ;
IOBUF PORT "seg[8]" ;
IOBUF PORT "seg[7]" ;
IOBUF PORT "seg[6]" ;
IOBUF PORT "seg[5]" ;
IOBUF PORT "seg[4]" ;
IOBUF PORT "seg[3]" ;
IOBUF PORT "seg[2]" ;
IOBUF PORT "seg[1]" ;
IOBUF PORT "seg[0]" ;
############################################################################
# Ethernet
#
# Not connected:
# LOCATE COMP "phy_clk125" SITE "L19" ;
# LOCATE COMP "phy_rgmii_rxclk" SITE "L20" ;
LOCATE COMP "phy_rgmii_rxctl" SITE "U19" ;
LOCATE COMP "phy_rgmii_rxd[3]" SITE "R18" ;
LOCATE COMP "phy_rgmii_rxd[2]" SITE "T19" ;
LOCATE COMP "phy_rgmii_rxd[1]" SITE "U20" ;
LOCATE COMP "phy_rgmii_rxd[0]" SITE "T20" ;
LOCATE COMP "eth_rst_n" SITE "U17" ;
LOCATE COMP "phy_rgmii_txclk" SITE "P19" ;
LOCATE COMP "phy_rgmii_txctl" SITE "R20" ;
LOCATE COMP "phy_rgmii_txd[3]" SITE "P20" ;
LOCATE COMP "phy_rgmii_txd[2]" SITE "P18" ;
LOCATE COMP "phy_rgmii_txd[1]" SITE "N20" ;
LOCATE COMP "phy_rgmii_txd[0]" SITE "N19" ;
LOCATE COMP "ts_mac_coremdc" SITE "T18" ;
LOCATE COMP "ts_mac_coremdio" SITE "U18" ;
LOCATE COMP "hw_config" SITE "T17" ;
############################################################################
# BLOCK JTAGPATHS ;
# SYSCONFIG SLAVE_SPI_PORT=DISABLE CONFIG_MODE=JTAG CONFIG_SECURE=OFF TRANSFR=OFF MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE MCCLK_FREQ=38.8 BACKGROUND_RECONFIG=OFF ;
IOBUF PORT "spi_miso" IO_TYPE=LVCMOS25 ;
IOBUF PORT "rxd_uart" IO_TYPE=LVCMOS33 ;
IOBUF PORT "txd_uart" IO_TYPE=LVCMOS33 ;
# BLOCK NET "soc/perio/rx_reset" ;
# BLOCK NET "soc/perio/tx_reset" ;
DEFINE PORT GROUP "rgmii_in" "phy_rgmii_rxctl"
"phy_rgmii_rxd[3]"
"phy_rgmii_rxd[2]"
"phy_rgmii_rxd[1]"
"phy_rgmii_rxd[0]" ;
# FREQUENCY PORT "phy_rgmii_rxclk" 125.000000 MHz ;
# INPUT_SETUP GROUP "rgmii_in"5.000000 ns CLKPORT "phy_rgmii_rxclk" ;
LOCATE COMP "clk_serdes" SITE "A4" ;
# JTAG pins:
# LOCATE COMP "tck" SITE "T5" ;
# LOCATE COMP "tdi" SITE "R5" ;
# LOCATE COMP "tms" SITE "U5" ;
# LOCATE COMP "tdo" SITE "V4" ;
LOCATE COMP "reset_n" SITE "T1" ;
# IOBUF PORT "reset_n" ;
IOBUF PORT "tck" IO_TYPE=LVCMOS33 ;
IOBUF PORT "tdi" IO_TYPE=LVCMOS33 ;
IOBUF PORT "tms" IO_TYPE=LVCMOS33 ;
# User code for rv32 TAP:
USERCODE HEX "CAFE1050" ;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/ecp5_versa/versa_ecp5_top.vhdl 0000664 0000000 0000000 00000007265 14502055570 0027315 0 ustar 00root root 0000000 0000000 --
-- Versa ECP5(G) top level module
--
--
-- 1/2017 Martin Strubel
--
-- Taken from MaSoCist and stripped down for the example.
-- Functionality:
-- * Blinks the first orange LED every second
-- * Loops back the UART (fixed at 115200 bps) through a FIFO and
-- turns lower cap alpha characters into upper case.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.system_map.all;
entity versa_ecp5_top is
generic(
CLK_FREQUENCY : positive := 25000000
);
port (
twi_scl : inout std_logic;
twi_sda : inout std_logic;
rxd_uart : in std_logic; -- FT2232 -> CPU
txd_uart : out std_logic; -- CPU -> FT2232
oled : out std_logic_vector(7 downto 0);
seg : out std_logic_vector(13 downto 0);
segdp : out std_logic;
dip_sw : in std_logic_vector(7 downto 0);
reset_n : in std_logic;
clk_in : in std_ulogic
);
end entity versa_ecp5_top;
architecture behaviour of versa_ecp5_top is
signal mclk : std_logic;
signal mclk_locked : std_logic;
-- Pixel clock:
signal pclk : std_logic;
signal comb_reset : std_logic;
constant f_half : integer := CLK_FREQUENCY / 2;
signal reset_delay : unsigned(3 downto 0);
signal led : unsigned(7 downto 0);
signal counter : integer range 0 to f_half;
signal toggle_led : std_ulogic := '0';
-- Uart signals:
signal uart_ctrl : uart_WritePort;
signal uart_stat : uart_ReadPort;
signal uart_idle : std_ulogic := '0';
signal rxready_d : std_ulogic := '0';
signal uart_data : unsigned(7 downto 0);
begin
comb_reset <= (not reset_n) or (not mclk_locked);
seg <= (others => '1'); -- low active
segdp <= '1'; -- low active
process(mclk)
begin
if rising_edge(mclk) then
counter <= counter + 1;
if counter = f_half then
toggle_led <= not toggle_led;
counter <= 0;
end if;
end if;
end process;
clk_pll1: entity work.pll_mac
port map (
CLKI => clk_in,
CLKOP => open,
CLKOS => mclk, -- 25 Mhz
CLKOS2 => open,
CLKOS3 => pclk,
LOCK => mclk_locked
);
-- Static config:
uart_ctrl.uart_clkdiv <= to_unsigned(CLK_FREQUENCY / 16 / 115200, 10);
uart_ctrl.rx_irq_enable <= '0';
uart_ctrl.uart_reset <= comb_reset;
-- UART loopback logic:
process (mclk)
begin
if rising_edge(mclk) then
uart_ctrl.select_uart_txr <= '0'; -- default 0
uart_ctrl.select_uart_rxr <= '0'; -- default 0
rxready_d <= uart_stat.rxready;
if uart_idle = '1' then
uart_idle <= '0';
else
if rxready_d = '1' then
-- Modify the data a bit:
if uart_data > x"40" and uart_data < x"ff" then
uart_ctrl.uart_txr <= uart_data and "01011111";
else
uart_ctrl.uart_txr <= uart_data;
end if;
uart_ctrl.select_uart_txr <= '1'; -- signal a write
end if;
if uart_stat.rxready = '1' then
uart_data <= uart_stat.rxdata; -- Read data
uart_ctrl.select_uart_rxr <= '1'; -- signal a read
uart_idle <= '1'; -- Wait state
end if;
end if;
end if;
end process;
uart_inst:
entity work.uart_core
port map (
tx => txd_uart,
rx => rxd_uart,
rxirq => open,
ctrl => uart_ctrl,
stat => uart_stat,
clk => mclk
);
led(0) <= toggle_led;
led(1) <= '0';
led(2) <= '1';
led(3) <= '0';
led(4) <= '0';
led(5) <= not rxd_uart;
led(6) <= '0';
led(7) <= uart_stat.rxovr;
-- Note LED are low active
oled <= not std_logic_vector(led);
twi_sda <= 'H';
twi_scl <= 'H';
-- txd_uart <= rxd_uart;
end behaviour;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/ghdlsynth.mk 0000664 0000000 0000000 00000001546 14502055570 0024015 0 ustar 00root root 0000000 0000000 # Common makefile for GHDL synthesis
# Specify:
#
# VHDL_SYN_FILES = VHDL files for synthesis, unordered
# VERILOG_FILES = auxiliary verilog wrappers that might be needed
# PLATFORM: 'ecp5' for now
# TOPLEVEL: top level entity name
# TOPLEVEL_PARAMETER: top level entity name parameters, when passed a generic
# LPF: I/O constraints file
PLATFORM ?= ecp5
ifneq ($(VERILOG_FILES),)
MAYBE_READ_VERILOG = read_verilog $(VERILOG_FILES);
endif
%.json: $(VHDL_SYN_FILES)
$(YOSYS) -m $(GHDLSYNTH) -p \
"ghdl $(GHDL_FLAGS) $(GHDL_GENERICS) $^ -e $(TOPLEVEL); \
$(MAYBE_READ_VERILOG) \
synth_$(PLATFORM) \
-top $(TOPLEVEL)$(TOPLEVEL_PARAMETER) -json $@" 2>&1 | tee $*-report.txt
%.config: %.json
$(NEXTPNR) --json $< --lpf $(LPF) \
--textcfg $@ $(NEXTPNR_FLAGS) --package $(PACKAGE)
%.svf: %.config
$(ECPPACK) --svf $*.svf $< $@
.PRECIOUS: %.json %.config
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/ice40hx8k/ 0000775 0000000 0000000 00000000000 14502055570 0023161 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/ice40hx8k/leds.vhdl 0000664 0000000 0000000 00000000304 14502055570 0024764 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity leds is
port (clk : in std_logic;
led1, led2, led3, led4, led5, led6, led7, led8 : out std_logic);
end leds;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/ice40hx8k/pinmap.pcf 0000664 0000000 0000000 00000000546 14502055570 0025144 0 ustar 00root root 0000000 0000000 # example.pcf
set_io --warn-no-port led1 B5
set_io --warn-no-port led2 B4
set_io --warn-no-port led3 A2
set_io --warn-no-port led4 A1
set_io --warn-no-port led5 C5
set_io --warn-no-port led6 C4
set_io --warn-no-port led7 B3
set_io --warn-no-port led8 C3
set_io --warn-no-port clk J3
# FTDI
set_io --warn-no-port ftdi_tx B12
set_io --warn-no-port ftdi_rx B10
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/ice40hx8k/spin1.vhdl 0000664 0000000 0000000 00000002216 14502055570 0025073 0 ustar 00root root 0000000 0000000 architecture spin1 of leds is
signal nrst : std_logic := '0';
signal clk_4hz: std_logic;
signal leds : std_ulogic_vector (1 to 5);
begin
(led1, led2, led3, led4, led5) <= leds;
led6 <= '0';
led7 <= '0';
led8 <= '0';
process (clk)
variable cnt : unsigned (1 downto 0) := "00";
begin
if rising_edge (clk) then
if cnt = 3 then
nrst <= '1';
else
cnt := cnt + 1;
end if;
end if;
end process;
process (clk)
-- 3_000_000 is 0x2dc6c0
variable counter : unsigned (23 downto 0);
begin
if rising_edge(clk) then
if nrst = '0' then
counter := x"000000";
else
if counter = 2_999_999 then
counter := x"000000";
clk_4hz <= '1';
else
counter := counter + 1;
clk_4hz <= '0';
end if;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if nrst = '0' then
-- Initialize
leds <= "11000";
elsif clk_4hz = '1' then
-- Rotate
leds <= (leds (4), leds (1), leds (2), leds (3), '0');
end if;
end if;
end process;
end spin1;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/ice40hx8k/spin2.vhdl 0000664 0000000 0000000 00000001337 14502055570 0025077 0 ustar 00root root 0000000 0000000 architecture spin2 of leds is
signal clk_4hz: std_logic;
signal leds : std_ulogic_vector (1 to 8) := "11000000";
begin
(led1, led2, led3, led4, led5, led6, led7, led8) <= leds;
process (clk)
-- 3_000_000 is 0x2dc6c0
variable counter : unsigned (23 downto 0);
begin
if rising_edge(clk) then
if counter = 2_999_999 then
counter := x"000000";
clk_4hz <= '1';
else
counter := counter + 1;
clk_4hz <= '0';
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) and clk_4hz = '1' then
-- Rotate
leds <= (leds (8), leds (1), leds (2), leds (3), leds (4), leds (5), leds (6), leds (7));
end if;
end process;
end spin2;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icestick/ 0000775 0000000 0000000 00000000000 14502055570 0023250 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icestick/leds/ 0000775 0000000 0000000 00000000000 14502055570 0024177 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icestick/leds/Makefile 0000664 0000000 0000000 00000001011 14502055570 0025630 0 ustar 00root root 0000000 0000000 PROJ = blink
#PROJ = fixed1
#PROJ = multi1
#PROJ = multi2
#PROJ = rotate1
#PROJ = rotate2
#PROJ = rotate3
#PROJ = rotate4
#PROJ = spin1
#PROJ = spin2
PIN_DEF = leds.pcf
DEVICE = hx1k
all: $(PROJ).bin
%.json: leds.vhdl %.vhdl
yosys -m ghdl -p 'ghdl $^ -e leds; synth_ice40 -json $@'
%.asc: %.json
nextpnr-ice40 --package $(DEVICE) --pcf $(PIN_DEF) --json $< --asc $@
%.bin: %.asc
icepack $< $@
prog: $(PROJ).bin
iceprog $<
clean:
rm -f $(PROJ).json $(PROJ).asc $(PROJ).bin
.SECONDARY:
.PHONY: all prog clean
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icestick/leds/blink.vhdl 0000664 0000000 0000000 00000000742 14502055570 0026160 0 ustar 00root root 0000000 0000000 architecture blink of leds is
signal clk_4hz: std_logic;
begin
process (clk)
-- 3_000_000 is 0x2dc6c0
variable counter : unsigned (23 downto 0);
begin
if rising_edge(clk) then
if counter = 2_999_999 then
counter := x"000000";
clk_4hz <= not clk_4hz;
else
counter := counter + 1;
end if;
end if;
end process;
led1 <= clk_4hz;
led2 <= clk_4hz;
led3 <= clk_4hz;
led4 <= clk_4hz;
led5 <= clk_4hz;
end blink;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icestick/leds/fixed1.vhdl 0000664 0000000 0000000 00000000161 14502055570 0026234 0 ustar 00root root 0000000 0000000 architecture fixed1 of leds is
begin
(led1, led2, led3, led4, led5) <= std_logic_vector'("00101");
end fixed1;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icestick/leds/leds.pcf 0000664 0000000 0000000 00000000137 14502055570 0025621 0 ustar 00root root 0000000 0000000 set_io led1 99
set_io led2 98
set_io led3 97
set_io led4 96
set_io led5 95
set_io clk 21
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icestick/leds/leds.vhdl 0000664 0000000 0000000 00000000415 14502055570 0026005 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Led positions
--
-- I D3
-- r
-- D D2 D5 D4
-- A
-- D1
--
entity leds is
port (clk : in std_logic;
led1, led2, led3, led4, led5 : out std_logic);
end leds;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icestick/leds/multi1.vhdl 0000664 0000000 0000000 00000004040 14502055570 0026267 0 ustar 00root root 0000000 0000000 architecture multi1 of leds is
signal clk_4hz: std_logic;
signal clk_5sec : std_logic;
signal leds : std_ulogic_vector (1 to 5);
begin
(led1, led2, led3, led4, led5) <= leds;
process (clk)
-- 3_000_000 is 0x2dc6c0
variable counter : unsigned (23 downto 0);
begin
if rising_edge(clk) then
if counter = 2_999_999 then
counter := x"000000";
clk_4hz <= '1';
else
counter := counter + 1;
clk_4hz <= '0';
end if;
end if;
end process;
process (clk)
variable counter5 : unsigned (4 downto 0);
begin
if rising_edge (clk) then
clk_5sec <= '0';
if clk_4hz = '1' then
if counter5 = 19 then
clk_5sec <= '1';
counter5 := "00000";
else
counter5 := counter5 + 1;
end if;
end if;
end if;
end process;
process (clk)
variable count : unsigned (1 downto 0);
variable pat_count : unsigned (0 downto 0);
begin
if rising_edge(clk) then
if clk_4hz = '1' then
case pat_count is
when "0" =>
case count is
when "00" =>
leds <= "10001";
when "01" =>
leds <= "01000";
when "10" =>
leds <= "00101";
when "11" =>
leds <= "00010";
when others =>
null;
end case;
when "1" =>
case count is
when "00" =>
leds <= "10000";
when "01" =>
leds <= "01011";
when "10" =>
leds <= "00100";
when "11" =>
leds <= "01011";
when others =>
null;
end case;
when others =>
null;
end case;
count := count + 1;
end if;
if clk_5sec = '1' then
pat_count := pat_count + 1;
count := "00";
end if;
end if;
end process;
end multi1;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icestick/leds/multi2.vhdl 0000664 0000000 0000000 00000001537 14502055570 0026300 0 ustar 00root root 0000000 0000000 architecture multi2 of leds is
signal clk_4hz: std_logic;
signal clk_5sec : std_logic;
begin
process (clk)
-- 3_000_000 is 0x2dc6c0
variable counter : unsigned (23 downto 0);
begin
if rising_edge(clk) then
if counter = 2_999_999 then
counter := x"000000";
clk_4hz <= '1';
else
counter := counter + 1;
clk_4hz <= '0';
end if;
end if;
end process;
process (clk)
variable counter5 : unsigned (4 downto 0);
begin
if rising_edge (clk) then
clk_5sec <= '0';
if clk_4hz = '1' then
if counter5 = 19 then
clk_5sec <= '1';
counter5 := "00000";
else
counter5 := counter5 + 1;
end if;
end if;
end if;
end process;
led1 <= clk_5sec;
led2 <= '0';
led3 <= '0';
led4 <= '0';
led5 <= '0';
end multi2;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icestick/leds/rotate1.vhdl 0000664 0000000 0000000 00000002112 14502055570 0026431 0 ustar 00root root 0000000 0000000 architecture rotate1 of leds is
signal clk_4hz: std_logic;
begin
process (clk)
-- 3_000_000 is 0x2dc6c0
variable counter : unsigned (23 downto 0);
begin
if rising_edge(clk) then
if counter = 2_999_999 then
counter := x"000000";
clk_4hz <= '1';
else
counter := counter + 1;
clk_4hz <= '0';
end if;
end if;
end process;
process (clk)
variable count : unsigned (1 downto 0);
begin
if rising_edge(clk) and clk_4hz = '1' then
count := count + 1;
if count = 0 then
led1 <= '1';
led2 <= '0';
led3 <= '0';
led4 <= '0';
led5 <= '1';
elsif count = 1 then
led1 <= '0';
led2 <= '1';
led3 <= '0';
led4 <= '0';
led5 <= '0';
elsif count = 2 then
led1 <= '0';
led2 <= '0';
led3 <= '1';
led4 <= '0';
led5 <= '1';
else
led1 <= '0';
led2 <= '0';
led3 <= '0';
led4 <= '1';
led5 <= '0';
end if;
end if;
end process;
end rotate1;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icestick/leds/rotate2.vhdl 0000664 0000000 0000000 00000001636 14502055570 0026444 0 ustar 00root root 0000000 0000000 architecture rotate2 of leds is
signal clk_4hz: std_logic;
begin
process (clk)
-- 3_000_000 is 0x2dc6c0
variable counter : unsigned (23 downto 0);
begin
if rising_edge(clk) then
if counter = 2_999_999 then
counter := x"000000";
clk_4hz <= '1';
else
counter := counter + 1;
clk_4hz <= '0';
end if;
end if;
end process;
process (clk)
variable count : unsigned (1 downto 0);
begin
if rising_edge(clk) and clk_4hz = '1' then
count := count + 1;
if count = 0 then
(led1, led2, led3, led4, led5) <= unsigned'("10001");
elsif count = 1 then
(led1, led2, led3, led4, led5) <= unsigned'("01000");
elsif count = 2 then
(led1, led2, led3, led4, led5) <= unsigned'("00101");
else
(led1, led2, led3, led4, led5) <= unsigned'("00010");
end if;
end if;
end process;
end rotate2;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icestick/leds/rotate3.vhdl 0000664 0000000 0000000 00000001736 14502055570 0026446 0 ustar 00root root 0000000 0000000 architecture rotate3 of leds is
signal clk_4hz: std_logic;
begin
process (clk)
-- 3_000_000 is 0x2dc6c0
variable counter : unsigned (23 downto 0);
begin
if rising_edge(clk) then
if counter = 2_999_999 then
counter := x"000000";
clk_4hz <= '1';
else
counter := counter + 1;
clk_4hz <= '0';
end if;
end if;
end process;
process (clk)
variable count : unsigned (1 downto 0);
begin
if rising_edge(clk) and clk_4hz = '1' then
case count is
when "00" =>
(led1, led2, led3, led4, led5) <= unsigned'("10001");
when "01" =>
(led1, led2, led3, led4, led5) <= unsigned'("01000");
when "10" =>
(led1, led2, led3, led4, led5) <= unsigned'("00101");
when "11" =>
(led1, led2, led3, led4, led5) <= unsigned'("00010");
when others =>
null;
end case;
count := count + 1;
end if;
end process;
end rotate3;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icestick/leds/rotate4.vhdl 0000664 0000000 0000000 00000001641 14502055570 0026442 0 ustar 00root root 0000000 0000000 architecture rotate4 of leds is
signal clk_4hz: std_logic;
signal leds : std_ulogic_vector (1 to 5);
begin
(led1, led2, led3, led4, led5) <= leds;
process (clk)
-- 3_000_000 is 0x2dc6c0
variable counter : unsigned (23 downto 0);
begin
if rising_edge(clk) then
if counter = 2_999_999 then
counter := x"000000";
clk_4hz <= '1';
else
counter := counter + 1;
clk_4hz <= '0';
end if;
end if;
end process;
process (clk)
variable count : unsigned (1 downto 0);
begin
if rising_edge(clk) and clk_4hz = '1' then
case count is
when "00" =>
leds <= "10001";
when "01" =>
leds <= "01000";
when "10" =>
leds <= "00101";
when "11" =>
leds <= "00010";
when others =>
null;
end case;
count := count + 1;
end if;
end process;
end rotate4;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icestick/leds/spin1.vhdl 0000664 0000000 0000000 00000002141 14502055570 0026106 0 ustar 00root root 0000000 0000000 architecture spin1 of leds is
signal nrst : std_logic := '0';
signal clk_4hz: std_logic;
signal leds : std_ulogic_vector (1 to 5);
begin
(led1, led2, led3, led4, led5) <= leds;
process (clk)
variable cnt : unsigned (1 downto 0) := "00";
begin
if rising_edge (clk) then
if cnt = 3 then
nrst <= '1';
else
cnt := cnt + 1;
end if;
end if;
end process;
process (clk)
-- 3_000_000 is 0x2dc6c0
variable counter : unsigned (23 downto 0);
begin
if rising_edge(clk) then
if nrst = '0' then
counter := x"000000";
else
if counter = 2_999_999 then
counter := x"000000";
clk_4hz <= '1';
else
counter := counter + 1;
clk_4hz <= '0';
end if;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if nrst = '0' then
-- Initialize
leds <= "11000";
elsif clk_4hz = '1' then
-- Rotate
leds <= (leds (4), leds (1), leds (2), leds (3), '0');
end if;
end if;
end process;
end spin1;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icestick/leds/spin2.vhdl 0000664 0000000 0000000 00000002143 14502055570 0026111 0 ustar 00root root 0000000 0000000 architecture spin1 of leds is
signal nrst : std_logic := '0';
signal clk_4hz: std_logic;
signal leds : std_ulogic_vector (1 to 5);
begin
(led1, led2, led3, led4, led5) <= leds;
process (clk)
variable cnt : unsigned (1 downto 0) := "00";
begin
if rising_edge (clk) then
if cnt = 3 then
nrst <= '1';
else
cnt := cnt + 1;
end if;
end if;
end process;
process (clk)
-- 3_000_000 is 0x2dc6c0
variable counter : unsigned (23 downto 0);
begin
if rising_edge(clk) then
if nrst = '0' then
counter := x"000000";
else
if counter = 2_999_999 then
counter := x"000000";
clk_4hz <= '1';
else
counter := counter + 1;
clk_4hz <= '0';
end if;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if nrst = '0' then
-- Initialize
leds <= "11000";
elsif clk_4hz = '1' then
-- Rotate
leds <= leds (4) & leds (1) & leds (2) & leds (3) & '0';
end if;
end if;
end process;
end spin1;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icestick/uart/ 0000775 0000000 0000000 00000000000 14502055570 0024223 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icestick/uart/README.md 0000775 0000000 0000000 00000000554 14502055570 0025511 0 ustar 00root root 0000000 0000000 # icestick-uart
Simple UART sender and receiver for the lattice icestick. It echoes every received word back.
Configuration: 115200 8N1
## Repository structure
- hdl: Contains the hardware design.
- syn: Contains the scripts and constraints for synthesis.
## Usage
- `cd syn && ./synth.sh`
- configure and open putty or another serial terminal and type something yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icestick/uart/hdl/ 0000775 0000000 0000000 00000000000 14502055570 0024772 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icestick/uart/hdl/uart_rx.vhd 0000775 0000000 0000000 00000003322 14502055570 0027164 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity uart_rx is
generic (
C_BITS : integer := 8;
C_CYCLES_PER_BIT : integer := 104
);
port (
isl_clk : in std_logic;
isl_data_n : in std_logic;
oslv_data : out std_logic_vector(C_BITS-1 downto 0);
osl_valid : out std_logic
);
end entity uart_rx;
architecture rtl of uart_rx is
signal int_cycle_cnt : integer range 0 to C_CYCLES_PER_BIT-1 := 0;
signal int_bit_cnt : integer range 0 to C_BITS+1 := 0;
signal slv_data : std_logic_vector(C_BITS-1 downto 0) := (others => '0');
signal sl_valid : std_logic := '0';
type t_state is (IDLE, INIT, RECEIVE);
signal state : t_state;
begin
process(isl_clk)
begin
if rising_edge(isl_clk) then
case state is
when IDLE =>
sl_valid <= '0';
if isl_data_n = '0' then
-- wait for the start bit
state <= INIT;
end if;
when INIT =>
int_cycle_cnt <= C_CYCLES_PER_BIT / 2;
int_bit_cnt <= 0;
state <= RECEIVE;
when RECEIVE =>
if int_bit_cnt < C_BITS+1 then
if int_cycle_cnt < C_CYCLES_PER_BIT-1 then
int_cycle_cnt <= int_cycle_cnt+1;
else
-- receive data bits
int_cycle_cnt <= 0;
int_bit_cnt <= int_bit_cnt+1;
slv_data <= not isl_data_n & slv_data(slv_data'LEFT downto 1); -- low active
end if;
elsif isl_data_n = '1' then
-- wait for the stop bit
sl_valid <= '1';
state <= IDLE;
end if;
end case;
end if;
end process;
oslv_data <= slv_data;
osl_valid <= sl_valid;
end architecture rtl;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icestick/uart/hdl/uart_top.vhd 0000775 0000000 0000000 00000002222 14502055570 0027333 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity uart_top is
generic (
C_BITS : integer := 8
);
port (
isl_clk : in std_logic;
isl_data_n : in std_logic;
osl_data_n : out std_logic;
osl_ready : out std_logic
);
end uart_top;
architecture behavioral of uart_top is
constant C_QUARTZ_FREQ : integer := 12000000; -- Hz
constant C_BAUDRATE : integer := 115200; -- words / s
constant C_CYCLES_PER_BIT : integer := C_QUARTZ_FREQ / C_BAUDRATE;
signal sl_valid_out_tx : std_logic := '0';
signal slv_data_out_tx : std_logic_vector(C_BITS-1 downto 0) := (others => '0');
begin
i_uart_rx: entity work.uart_rx
generic map (
C_BITS => C_BITS,
C_CYCLES_PER_BIT => C_CYCLES_PER_BIT
)
port map (
isl_clk => isl_clk,
isl_data_n => isl_data_n,
oslv_data => slv_data_out_tx,
osl_valid => sl_valid_out_tx
);
i_uart_tx: entity work.uart_tx
generic map (
C_BITS => C_BITS,
C_CYCLES_PER_BIT => C_CYCLES_PER_BIT
)
port map (
isl_clk => isl_clk,
isl_valid => sl_valid_out_tx,
islv_data => slv_data_out_tx,
osl_data_n => osl_data_n,
osl_ready => osl_ready
);
end behavioral; yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icestick/uart/hdl/uart_tx.vhd 0000775 0000000 0000000 00000003167 14502055570 0027175 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity uart_tx is
generic (
-- TODO: range in submodules is not yet supported by synthesis
-- it would be useful to limit between 5 to 8
C_BITS : integer := 8;
C_CYCLES_PER_BIT : integer := 104
);
port (
isl_clk : in std_logic;
isl_valid : in std_logic;
islv_data : in std_logic_vector(C_BITS-1 downto 0);
osl_ready : out std_logic;
osl_data_n : out std_logic
);
end entity uart_tx;
architecture rtl of uart_tx is
signal int_cycle_cnt : integer range 0 to C_CYCLES_PER_BIT-1 := 0;
signal int_bit_cnt : integer range 0 to C_BITS+2 := 0;
signal slv_data : std_logic_vector(C_BITS downto 0) := (others => '0');
type t_state is (IDLE, INIT, SEND);
signal state : t_state;
begin
process(isl_clk)
begin
if rising_edge(isl_clk) then
case state is
when IDLE =>
if isl_valid = '1' then
state <= INIT;
end if;
when INIT =>
int_cycle_cnt <= 0;
int_bit_cnt <= 0;
slv_data <= islv_data & '1';
state <= SEND;
when SEND =>
if int_cycle_cnt < C_CYCLES_PER_BIT-1 then
int_cycle_cnt <= int_cycle_cnt+1;
elsif int_bit_cnt < C_BITS+1 then
int_cycle_cnt <= 0;
int_bit_cnt <= int_bit_cnt+1;
slv_data <= '0' & slv_data(slv_data'LEFT downto 1);
else
state <= IDLE;
end if;
end case;
end if;
end process;
osl_ready <= '1' when state = IDLE else '0';
osl_data_n <= not slv_data(0); -- low active
end architecture rtl; yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icestick/uart/syn/ 0000775 0000000 0000000 00000000000 14502055570 0025034 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icestick/uart/syn/constraints/ 0000775 0000000 0000000 00000000000 14502055570 0027403 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icestick/uart/syn/constraints/uart.pcf 0000775 0000000 0000000 00000000163 14502055570 0031053 0 ustar 00root root 0000000 0000000 # FTDI Port B UART
set_io osl_data_n 8 # UART TX
set_io isl_data_n 9 # UART RX
# 12 MHz clock
set_io isl_clk 21
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icestick/uart/syn/synth.sh 0000775 0000000 0000000 00000000617 14502055570 0026544 0 ustar 00root root 0000000 0000000 set -e
ROOT="$(pwd)/.."
rm -rf build
mkdir -p build
cd build
ghdl -a "$ROOT"/hdl/uart_rx.vhd
ghdl -a "$ROOT"/hdl/uart_tx.vhd
ghdl -a "$ROOT"/hdl/uart_top.vhd
yosys -m ghdl -p 'ghdl uart_top; synth_ice40 -json uart_top.json'
nextpnr-ice40 --hx1k --json uart_top.json --pcf ../constraints/uart.pcf --asc uart_top.asc --pcf-allow-unconstrained
icepack uart_top.asc uart_top.bin
iceprog uart_top.bin
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icezum/ 0000775 0000000 0000000 00000000000 14502055570 0022746 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icezum/Makefile 0000664 0000000 0000000 00000000620 14502055570 0024404 0 ustar 00root root 0000000 0000000 PROJ ?= blink
PIN_DEF = icezum.pcf
DEVICE = hx1k
all: report bin
json: $(PROJ).vhdl
yosys -m ghdl -p 'ghdl $(PROJ).vhdl -e $(PROJ); synth_ice40 -json $@'
asc: $(PIN_DEF) json
nextpnr-ice40 --$(DEVICE) --json json --pcf $(PIN_DEF) --asc $@
bin: asc
icepack $< $@
report: asc
icetime -d $(DEVICE) -mtr $@ $<
clean:
rm -f json asc bin report work-obj93.cf
.SECONDARY:
.PHONY: all prog clean
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icezum/blink.vhdl 0000664 0000000 0000000 00000001275 14502055570 0024731 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity blink is
port (
clk : in std_logic;
led0, led1, led2, led3, led4, led5, led6, led7 : out std_logic
);
end blink;
architecture synth of blink is
signal blink: std_logic;
begin
process (clk)
variable cnt : unsigned (23 downto 0); -- 3_000_000 requires 24 bits
begin
if rising_edge(clk) then
if cnt = 2_999_999 then
cnt := x"000000";
blink <= not blink;
else
cnt := cnt + 1;
end if;
end if;
end process;
led0 <= blink;
led1 <= blink;
led2 <= blink;
led3 <= blink;
led4 <= blink;
led5 <= blink;
led6 <= blink;
led7 <= blink;
end synth;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icezum/counter.vhdl 0000664 0000000 0000000 00000001442 14502055570 0025305 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is
port (
clk : in std_logic;
led0, led1, led2, led3, led4, led5, led6, led7 : out std_logic
);
end counter;
architecture synth of counter is
signal clk_6hz : std_logic;
begin
-- Presscaler
prescaler: process(clk)
variable timer : unsigned (20 downto 0) := (others=>'0');
begin
if rising_edge(clk) then
timer := timer + 1;
clk_6hz <= timer(20);
end if;
end process;
-- 8 bits counter
process (clk_6hz)
variable temp : unsigned (7 downto 0);
begin
if rising_edge(clk_6hz) then
temp:= temp + 1;
-- Show the counter on the icezum Alhambra leds
(led7, led6, led5, led4, led3, led2, led1, led0) <= temp;
end if;
end process;
end synth;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icezum/icezum.pcf 0000664 0000000 0000000 00000000251 14502055570 0024732 0 ustar 00root root 0000000 0000000 set_io sw1 10
set_io sw2 11
set_io clk 21
set_io led0 95
set_io led1 96
set_io led2 97
set_io led3 98
set_io led4 99
set_io led5 101
set_io led6 102
set_io led7 104
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icezum/led_on.vhdl 0000664 0000000 0000000 00000000554 14502055570 0025071 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity led_on is
port (led0, led1, led2, led3, led4, led5, led6, led7 : out std_logic);
end led_on;
architecture test of led_on is
begin
-- Turn on the Led0
led0 <= '1';
-- Turn off the other leds
(led1, led2, led3, led4, led5, led6, led7) <= std_logic_vector'("0000000");
end test;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icezum/pushbutton.vhdl 0000664 0000000 0000000 00000000472 14502055570 0026043 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pushbutton is
port (
sw1, sw2 : in std_logic;
led0, led7 : out std_logic
);
end pushbutton;
architecture synth of pushbutton is
signal a : std_logic;
begin
a <= sw1 and sw2;
led0 <= a;
led7 <= not a;
end synth;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/examples/icezum/test.sh 0000775 0000000 0000000 00000000670 14502055570 0024267 0 ustar 00root root 0000000 0000000 #!/usr/bin/env sh
cd $(dirname $0)
DOCKER_CMD="docker run --rm -v /$(pwd)://wrk -w //wrk"
mkdir -p build
for prj in blink counter led_on pushbutton; do
$DOCKER_CMD ghdl/synth:beta yosys -m ghdl -p "ghdl $prj.vhdl -e $prj; synth_ice40 -json build/json"
$DOCKER_CMD ghdl/synth:nextpnr nextpnr-ice40 --hx1k --json build/json --pcf icezum.pcf --asc build/asc
$DOCKER_CMD ghdl/synth:icestorm icepack build/asc build/$prj.bin
done
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/library/ 0000775 0000000 0000000 00000000000 14502055570 0021300 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/library/ecp5u/ 0000775 0000000 0000000 00000000000 14502055570 0022321 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/library/ecp5u/components.vhdl 0000664 0000000 0000000 00000445333 14502055570 0025401 0 ustar 00root root 0000000 0000000 -- This module is generated by vhdl_pkg.xsl
-- (2016-2020, hackfin@section5.ch)
--
-- Changes may be void.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package components is
component CCU2C is
generic (
INJECT1_0 : string := "YES";
INJECT1_1 : string := "YES";
INIT0 : std_logic_vector := "0000000000000000";
INIT1 : std_logic_vector := "0000000000000000" );
port (
A0 : in std_ulogic;
A1 : in std_ulogic;
B0 : in std_ulogic;
B1 : in std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
CIN : in std_ulogic;
S0 : out std_ulogic;
S1 : out std_ulogic;
COUT : out std_ulogic );
end component;
component AND2 is
port (
A : in std_logic;
B : in std_logic;
Z : out std_logic );
end component;
component AND3 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
Z : out std_logic );
end component;
component AND4 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
Z : out std_logic );
end component;
component AND5 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
E : in std_logic;
Z : out std_logic );
end component;
component FD1P3AX is
generic (
GSR : string := "ENABLED" );
port (
D : in std_logic;
SP : in std_logic;
CK : in std_logic;
Q : out std_logic );
end component;
component FD1P3AY is
generic (
GSR : string := "ENABLED" );
port (
D : in std_logic;
SP : in std_logic;
CK : in std_logic;
Q : out std_logic );
end component;
component FD1P3BX is
generic (
GSR : string := "ENABLED" );
port (
D : in std_logic;
SP : in std_logic;
CK : in std_logic;
PD : in std_logic;
Q : out std_logic );
end component;
component FD1P3DX is
generic (
GSR : string := "ENABLED" );
port (
D : in std_logic;
SP : in std_logic;
CK : in std_logic;
CD : in std_logic;
Q : out std_logic );
end component;
component FD1P3IX is
generic (
GSR : string := "ENABLED" );
port (
D : in std_logic;
SP : in std_logic;
CK : in std_logic;
CD : in std_logic;
Q : out std_logic );
end component;
component FD1P3JX is
generic (
GSR : string := "ENABLED" );
port (
D : in std_logic;
SP : in std_logic;
CK : in std_logic;
PD : in std_logic;
Q : out std_logic );
end component;
component FD1S3AX is
generic (
GSR : string := "ENABLED" );
port (
D : in std_logic;
CK : in std_logic;
Q : out std_logic );
end component;
component FD1S3AY is
generic (
GSR : string := "ENABLED" );
port (
D : in std_logic;
CK : in std_logic;
Q : out std_logic );
end component;
component FD1S3BX is
generic (
GSR : string := "ENABLED" );
port (
D : in std_logic;
CK : in std_logic;
PD : in std_logic;
Q : out std_logic );
end component;
component FD1S3DX is
generic (
GSR : string := "ENABLED" );
port (
D : in std_logic;
CK : in std_logic;
CD : in std_logic;
Q : out std_logic );
end component;
component FD1S3IX is
generic (
GSR : string := "ENABLED" );
port (
D : in std_logic;
CK : in std_logic;
CD : in std_logic;
Q : out std_logic );
end component;
component FD1S3JX is
generic (
GSR : string := "ENABLED" );
port (
D : in std_logic;
CK : in std_logic;
PD : in std_logic;
Q : out std_logic );
end component;
component FL1P3AZ is
generic (
GSR : string := "ENABLED" );
port (
D0 : in std_logic;
D1 : in std_logic;
SP : in std_logic;
CK : in std_logic;
SD : in std_logic;
Q : out std_logic );
end component;
component FL1P3AY is
generic (
GSR : string := "ENABLED" );
port (
D0 : in std_logic;
D1 : in std_logic;
SP : in std_logic;
CK : in std_logic;
SD : in std_logic;
Q : out std_logic );
end component;
component FL1P3BX is
generic (
GSR : string := "ENABLED" );
port (
D0 : in std_logic;
D1 : in std_logic;
SP : in std_logic;
CK : in std_logic;
SD : in std_logic;
PD : in std_logic;
Q : out std_logic );
end component;
component FL1P3DX is
generic (
GSR : string := "ENABLED" );
port (
D0 : in std_logic;
D1 : in std_logic;
SP : in std_logic;
CK : in std_logic;
SD : in std_logic;
CD : in std_logic;
Q : out std_logic );
end component;
component FL1P3IY is
generic (
GSR : string := "ENABLED" );
port (
D0 : in std_logic;
D1 : in std_logic;
SP : in std_logic;
CK : in std_logic;
SD : in std_logic;
CD : in std_logic;
Q : out std_logic );
end component;
component FL1P3JY is
generic (
GSR : string := "ENABLED" );
port (
D0 : in std_logic;
D1 : in std_logic;
SP : in std_logic;
CK : in std_logic;
SD : in std_logic;
PD : in std_logic;
Q : out std_logic );
end component;
component FL1S3AX is
generic (
GSR : string := "ENABLED" );
port (
D0 : in std_logic;
D1 : in std_logic;
CK : in std_logic;
SD : in std_logic;
Q : out std_logic );
end component;
component FL1S3AY is
generic (
GSR : string := "ENABLED" );
port (
D0 : in std_logic;
D1 : in std_logic;
CK : in std_logic;
SD : in std_logic;
Q : out std_logic );
end component;
component GSR is
port (
GSR : in std_logic );
end component;
component SGSR is
port (
GSR : in std_logic;
CLK : in std_logic );
end component;
component INV is
port (
A : in std_logic;
Z : out std_logic );
end component;
component IFS1P3BX is
generic (
GSR : string := "ENABLED" );
port (
D : in std_logic;
SP : in std_logic;
SCLK : in std_logic;
PD : in std_logic;
Q : out std_logic );
end component;
component IFS1P3DX is
generic (
GSR : string := "ENABLED" );
port (
D : in std_logic;
SP : in std_logic;
SCLK : in std_logic;
CD : in std_logic;
Q : out std_logic );
end component;
component IFS1P3IX is
generic (
GSR : string := "ENABLED" );
port (
D : in std_logic;
SP : in std_logic;
SCLK : in std_logic;
CD : in std_logic;
Q : out std_logic );
end component;
component IFS1P3JX is
generic (
GSR : string := "ENABLED" );
port (
D : in std_logic;
SP : in std_logic;
SCLK : in std_logic;
PD : in std_logic;
Q : out std_logic );
end component;
component IFS1S1B is
generic (
GSR : string := "ENABLED" );
port (
D : in std_logic;
SCLK : in std_logic;
PD : in std_logic;
Q : out std_logic );
end component;
component IFS1S1D is
generic (
GSR : string := "ENABLED" );
port (
D : in std_logic;
SCLK : in std_logic;
CD : in std_logic;
Q : out std_logic );
end component;
component IFS1S1I is
generic (
GSR : string := "ENABLED" );
port (
D : in std_logic;
SCLK : in std_logic;
CD : in std_logic;
Q : out std_logic );
end component;
component IFS1S1J is
generic (
GSR : string := "ENABLED" );
port (
D : in std_logic;
SCLK : in std_logic;
PD : in std_logic;
Q : out std_logic );
end component;
component L6MUX21 is
port (
D0 : in std_logic;
D1 : in std_logic;
SD : in std_logic;
Z : out std_logic );
end component;
component MUX21 is
port (
D0 : in std_logic;
D1 : in std_logic;
SD : in std_logic;
Z : out std_logic );
end component;
component MUX41 is
port (
D0 : in std_logic;
D1 : in std_logic;
D2 : in std_logic;
D3 : in std_logic;
SD1 : in std_logic;
SD2 : in std_logic;
Z : out std_logic );
end component;
component MUX81 is
port (
D0 : in std_logic;
D1 : in std_logic;
D2 : in std_logic;
D3 : in std_logic;
D4 : in std_logic;
D5 : in std_logic;
D6 : in std_logic;
D7 : in std_logic;
SD1 : in std_logic;
SD2 : in std_logic;
SD3 : in std_logic;
Z : out std_logic );
end component;
component MUX161 is
port (
D0 : in std_logic;
D1 : in std_logic;
D2 : in std_logic;
D3 : in std_logic;
D4 : in std_logic;
D5 : in std_logic;
D6 : in std_logic;
D7 : in std_logic;
D8 : in std_logic;
D9 : in std_logic;
D10 : in std_logic;
D11 : in std_logic;
D12 : in std_logic;
D13 : in std_logic;
D14 : in std_logic;
D15 : in std_logic;
SD1 : in std_logic;
SD2 : in std_logic;
SD3 : in std_logic;
SD4 : in std_logic;
Z : out std_logic );
end component;
component MUX321 is
port (
D0 : in std_logic;
D1 : in std_logic;
D2 : in std_logic;
D3 : in std_logic;
D4 : in std_logic;
D5 : in std_logic;
D6 : in std_logic;
D7 : in std_logic;
D8 : in std_logic;
D9 : in std_logic;
D10 : in std_logic;
D11 : in std_logic;
D12 : in std_logic;
D13 : in std_logic;
D14 : in std_logic;
D15 : in std_logic;
D16 : in std_logic;
D17 : in std_logic;
D18 : in std_logic;
D19 : in std_logic;
D20 : in std_logic;
D21 : in std_logic;
D22 : in std_logic;
D23 : in std_logic;
D24 : in std_logic;
D25 : in std_logic;
D26 : in std_logic;
D27 : in std_logic;
D28 : in std_logic;
D29 : in std_logic;
D30 : in std_logic;
D31 : in std_logic;
SD1 : in std_logic;
SD2 : in std_logic;
SD3 : in std_logic;
SD4 : in std_logic;
SD5 : in std_logic;
Z : out std_logic );
end component;
component ND2 is
port (
A : in std_logic;
B : in std_logic;
Z : out std_logic );
end component;
component ND3 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
Z : out std_logic );
end component;
component ND4 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
Z : out std_logic );
end component;
component ND5 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
E : in std_logic;
Z : out std_logic );
end component;
component NR2 is
port (
A : in std_logic;
B : in std_logic;
Z : out std_logic );
end component;
component NR3 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
Z : out std_logic );
end component;
component NR4 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
Z : out std_logic );
end component;
component NR5 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
E : in std_logic;
Z : out std_logic );
end component;
component OFS1P3BX is
generic (
GSR : string := "ENABLED" );
port (
D : in std_logic;
SP : in std_logic;
SCLK : in std_logic;
PD : in std_logic;
Q : out std_logic );
end component;
component OFS1P3DX is
generic (
GSR : string := "ENABLED" );
port (
D : in std_logic;
SP : in std_logic;
SCLK : in std_logic;
CD : in std_logic;
Q : out std_logic );
end component;
component OFS1P3IX is
generic (
GSR : string := "ENABLED" );
port (
D : in std_logic;
SP : in std_logic;
SCLK : in std_logic;
CD : in std_logic;
Q : out std_logic );
end component;
component OFS1P3JX is
generic (
GSR : string := "ENABLED" );
port (
D : in std_logic;
SP : in std_logic;
SCLK : in std_logic;
PD : in std_logic;
Q : out std_logic );
end component;
component OR2 is
port (
A : in std_logic;
B : in std_logic;
Z : out std_logic );
end component;
component OR3 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
Z : out std_logic );
end component;
component OR4 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
Z : out std_logic );
end component;
component OR5 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
E : in std_logic;
Z : out std_logic );
end component;
component PFUMX is
port (
ALUT : in std_logic;
BLUT : in std_logic;
C0 : in std_logic;
Z : out std_logic );
end component;
component ROM16X1A is
generic (
INITVAL : std_logic_vector := "0000000000000000" );
port (
AD0 : in std_logic;
AD1 : in std_logic;
AD2 : in std_logic;
AD3 : in std_logic;
DO0 : out std_logic );
end component;
component ROM32X1A is
generic (
INITVAL : std_logic_vector := "00000000000000000000000000000000" );
port (
AD0 : in std_logic;
AD1 : in std_logic;
AD2 : in std_logic;
AD3 : in std_logic;
AD4 : in std_logic;
DO0 : out std_logic );
end component;
component ROM64X1A is
generic (
INITVAL : std_logic_vector := "0000000000000000000000000000000000000000000000000000000000000000" );
port (
AD0 : in std_logic;
AD1 : in std_logic;
AD2 : in std_logic;
AD3 : in std_logic;
AD4 : in std_logic;
AD5 : in std_logic;
DO0 : out std_logic );
end component;
component ROM128X1A is
generic (
INITVAL : std_logic_vector := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" );
port (
AD0 : in std_logic;
AD1 : in std_logic;
AD2 : in std_logic;
AD3 : in std_logic;
AD4 : in std_logic;
AD5 : in std_logic;
AD6 : in std_logic;
DO0 : out std_logic );
end component;
component ROM256X1A is
generic (
INITVAL : std_logic_vector := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" );
port (
AD0 : in std_logic;
AD1 : in std_logic;
AD2 : in std_logic;
AD3 : in std_logic;
AD4 : in std_logic;
AD5 : in std_logic;
AD6 : in std_logic;
AD7 : in std_logic;
DO0 : out std_logic );
end component;
component VHI is
port (
Z : out std_logic );
end component;
component VLO is
port (
Z : out std_logic );
end component;
component XOR2 is
port (
A : in std_logic;
B : in std_logic;
Z : out std_logic );
end component;
component XOR3 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
Z : out std_logic );
end component;
component XOR4 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
Z : out std_logic );
end component;
component XOR5 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
E : in std_logic;
Z : out std_logic );
end component;
component XOR11 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
E : in std_logic;
F : in std_logic;
G : in std_logic;
H : in std_logic;
I : in std_logic;
J : in std_logic;
K : in std_logic;
Z : out std_logic );
end component;
component XOR21 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
E : in std_logic;
F : in std_logic;
G : in std_logic;
H : in std_logic;
I : in std_logic;
J : in std_logic;
K : in std_logic;
L : in std_logic;
M : in std_logic;
N : in std_logic;
O : in std_logic;
P : in std_logic;
Q : in std_logic;
R : in std_logic;
S : in std_logic;
T : in std_logic;
U : in std_logic;
Z : out std_logic );
end component;
component XNOR2 is
port (
A : in std_logic;
B : in std_logic;
Z : out std_logic );
end component;
component XNOR3 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
Z : out std_logic );
end component;
component XNOR4 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
Z : out std_logic );
end component;
component XNOR5 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
E : in std_logic;
Z : out std_logic );
end component;
component ILVDS is
port (
A : in std_logic;
AN : in std_logic;
Z : out std_logic );
end component;
component OLVDS is
port (
A : in std_logic;
Z : out std_logic;
ZN : out std_logic );
end component;
component BB is
port (
B : inout std_logic;
I : in std_logic;
T : in std_logic;
O : out std_logic );
end component;
component BBPD is
port (
B : inout std_logic;
I : in std_logic;
T : in std_logic;
O : out std_logic );
end component;
component BBPU is
port (
B : inout std_logic;
I : in std_logic;
T : in std_logic;
O : out std_logic );
end component;
component IB is
port (
I : in std_logic;
O : out std_logic );
end component;
component IBPD is
port (
I : in std_logic;
O : out std_logic );
end component;
component IBPU is
port (
I : in std_logic;
O : out std_logic );
end component;
component OB is
port (
I : in std_logic;
O : out std_logic );
end component;
component OBCO is
port (
I : in std_logic;
OT : out std_logic;
OC : out std_logic );
end component;
component OBZ is
port (
I : in std_logic;
T : in std_logic;
O : out std_logic );
end component;
component OBZPU is
port (
I : in std_logic;
T : in std_logic;
O : out std_logic );
end component;
component LUT4 is
generic (
INIT : std_logic_vector := "" );
port (
A : in std_ulogic;
B : in std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
Z : out std_ulogic );
end component;
component LUT5 is
generic (
INIT : std_logic_vector := "" );
port (
A : in std_ulogic;
B : in std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
E : in std_ulogic;
Z : out std_ulogic );
end component;
component LUT6 is
generic (
INIT : std_logic_vector := "" );
port (
A : in std_ulogic;
B : in std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
E : in std_ulogic;
F : in std_ulogic;
Z : out std_ulogic );
end component;
component LUT7 is
generic (
INIT : std_logic_vector := "" );
port (
A : in std_ulogic;
B : in std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
E : in std_ulogic;
F : in std_ulogic;
G : in std_ulogic;
Z : out std_ulogic );
end component;
component LUT8 is
generic (
INIT : std_logic_vector := "" );
port (
A : in std_ulogic;
B : in std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
E : in std_ulogic;
F : in std_ulogic;
G : in std_ulogic;
H : in std_ulogic;
Z : out std_ulogic );
end component;
component MULT9X9C is
generic (
REG_INPUTA_CLK : string := "NONE";
REG_INPUTA_CE : string := "CE0";
REG_INPUTA_RST : string := "RST0";
REG_INPUTB_CLK : string := "NONE";
REG_INPUTB_CE : string := "CE0";
REG_INPUTB_RST : string := "RST0";
REG_PIPELINE_CLK : string := "NONE";
REG_PIPELINE_CE : string := "CE0";
REG_PIPELINE_RST : string := "RST0";
REG_OUTPUT_CLK : string := "NONE";
REG_OUTPUT_CE : string := "CE0";
REG_OUTPUT_RST : string := "RST0";
GSR : string := "ENABLED";
CAS_MATCH_REG : string := "FALSE";
MULT_BYPASS : string := "DISABLED";
RESETMODE : string := "SYNC" );
port (
A8 : in std_logic;
A7 : in std_logic;
A6 : in std_logic;
A5 : in std_logic;
A4 : in std_logic;
A3 : in std_logic;
A2 : in std_logic;
A1 : in std_logic;
A0 : in std_logic;
B8 : in std_logic;
B7 : in std_logic;
B6 : in std_logic;
B5 : in std_logic;
B4 : in std_logic;
B3 : in std_logic;
B2 : in std_logic;
B1 : in std_logic;
B0 : in std_logic;
SIGNEDA : in std_logic;
SIGNEDB : in std_logic;
SOURCEA : in std_logic;
SOURCEB : in std_logic;
CLK3 : in std_logic;
CLK2 : in std_logic;
CLK1 : in std_logic;
CLK0 : in std_logic;
CE3 : in std_logic;
CE2 : in std_logic;
CE1 : in std_logic;
CE0 : in std_logic;
RST3 : in std_logic;
RST2 : in std_logic;
RST1 : in std_logic;
RST0 : in std_logic;
SRIA8 : in std_logic;
SRIA7 : in std_logic;
SRIA6 : in std_logic;
SRIA5 : in std_logic;
SRIA4 : in std_logic;
SRIA3 : in std_logic;
SRIA2 : in std_logic;
SRIA1 : in std_logic;
SRIA0 : in std_logic;
SRIB8 : in std_logic;
SRIB7 : in std_logic;
SRIB6 : in std_logic;
SRIB5 : in std_logic;
SRIB4 : in std_logic;
SRIB3 : in std_logic;
SRIB2 : in std_logic;
SRIB1 : in std_logic;
SRIB0 : in std_logic;
SROA8 : out std_logic;
SROA7 : out std_logic;
SROA6 : out std_logic;
SROA5 : out std_logic;
SROA4 : out std_logic;
SROA3 : out std_logic;
SROA2 : out std_logic;
SROA1 : out std_logic;
SROA0 : out std_logic;
SROB8 : out std_logic;
SROB7 : out std_logic;
SROB6 : out std_logic;
SROB5 : out std_logic;
SROB4 : out std_logic;
SROB3 : out std_logic;
SROB2 : out std_logic;
SROB1 : out std_logic;
SROB0 : out std_logic;
ROA8 : out std_logic;
ROA7 : out std_logic;
ROA6 : out std_logic;
ROA5 : out std_logic;
ROA4 : out std_logic;
ROA3 : out std_logic;
ROA2 : out std_logic;
ROA1 : out std_logic;
ROA0 : out std_logic;
ROB8 : out std_logic;
ROB7 : out std_logic;
ROB6 : out std_logic;
ROB5 : out std_logic;
ROB4 : out std_logic;
ROB3 : out std_logic;
ROB2 : out std_logic;
ROB1 : out std_logic;
ROB0 : out std_logic;
P17 : out std_logic;
P16 : out std_logic;
P15 : out std_logic;
P14 : out std_logic;
P13 : out std_logic;
P12 : out std_logic;
P11 : out std_logic;
P10 : out std_logic;
P9 : out std_logic;
P8 : out std_logic;
P7 : out std_logic;
P6 : out std_logic;
P5 : out std_logic;
P4 : out std_logic;
P3 : out std_logic;
P2 : out std_logic;
P1 : out std_logic;
P0 : out std_logic;
SIGNEDP : out std_logic );
end component;
component MULT9X9D is
generic (
REG_INPUTA_CLK : string := "NONE";
REG_INPUTA_CE : string := "CE0";
REG_INPUTA_RST : string := "RST0";
REG_INPUTB_CLK : string := "NONE";
REG_INPUTB_CE : string := "CE0";
REG_INPUTB_RST : string := "RST0";
REG_INPUTC_CLK : string := "NONE";
REG_INPUTC_CE : string := "CE0";
REG_INPUTC_RST : string := "RST0";
REG_PIPELINE_CLK : string := "NONE";
REG_PIPELINE_CE : string := "CE0";
REG_PIPELINE_RST : string := "RST0";
REG_OUTPUT_CLK : string := "NONE";
REG_OUTPUT_CE : string := "CE0";
REG_OUTPUT_RST : string := "RST0";
CLK0_DIV : string := "ENABLED";
CLK1_DIV : string := "ENABLED";
CLK2_DIV : string := "ENABLED";
CLK3_DIV : string := "ENABLED";
HIGHSPEED_CLK : string := "NONE";
GSR : string := "ENABLED";
CAS_MATCH_REG : string := "FALSE";
SOURCEB_MODE : string := "B_SHIFT";
MULT_BYPASS : string := "DISABLED";
RESETMODE : string := "SYNC" );
port (
A8 : in std_logic;
A7 : in std_logic;
A6 : in std_logic;
A5 : in std_logic;
A4 : in std_logic;
A3 : in std_logic;
A2 : in std_logic;
A1 : in std_logic;
A0 : in std_logic;
B8 : in std_logic;
B7 : in std_logic;
B6 : in std_logic;
B5 : in std_logic;
B4 : in std_logic;
B3 : in std_logic;
B2 : in std_logic;
B1 : in std_logic;
B0 : in std_logic;
C8 : in std_logic;
C7 : in std_logic;
C6 : in std_logic;
C5 : in std_logic;
C4 : in std_logic;
C3 : in std_logic;
C2 : in std_logic;
C1 : in std_logic;
C0 : in std_logic;
SIGNEDA : in std_logic;
SIGNEDB : in std_logic;
SOURCEA : in std_logic;
SOURCEB : in std_logic;
CLK3 : in std_logic;
CLK2 : in std_logic;
CLK1 : in std_logic;
CLK0 : in std_logic;
CE3 : in std_logic;
CE2 : in std_logic;
CE1 : in std_logic;
CE0 : in std_logic;
RST3 : in std_logic;
RST2 : in std_logic;
RST1 : in std_logic;
RST0 : in std_logic;
SRIA8 : in std_logic;
SRIA7 : in std_logic;
SRIA6 : in std_logic;
SRIA5 : in std_logic;
SRIA4 : in std_logic;
SRIA3 : in std_logic;
SRIA2 : in std_logic;
SRIA1 : in std_logic;
SRIA0 : in std_logic;
SRIB8 : in std_logic;
SRIB7 : in std_logic;
SRIB6 : in std_logic;
SRIB5 : in std_logic;
SRIB4 : in std_logic;
SRIB3 : in std_logic;
SRIB2 : in std_logic;
SRIB1 : in std_logic;
SRIB0 : in std_logic;
SROA8 : out std_logic;
SROA7 : out std_logic;
SROA6 : out std_logic;
SROA5 : out std_logic;
SROA4 : out std_logic;
SROA3 : out std_logic;
SROA2 : out std_logic;
SROA1 : out std_logic;
SROA0 : out std_logic;
SROB8 : out std_logic;
SROB7 : out std_logic;
SROB6 : out std_logic;
SROB5 : out std_logic;
SROB4 : out std_logic;
SROB3 : out std_logic;
SROB2 : out std_logic;
SROB1 : out std_logic;
SROB0 : out std_logic;
ROA8 : out std_logic;
ROA7 : out std_logic;
ROA6 : out std_logic;
ROA5 : out std_logic;
ROA4 : out std_logic;
ROA3 : out std_logic;
ROA2 : out std_logic;
ROA1 : out std_logic;
ROA0 : out std_logic;
ROB8 : out std_logic;
ROB7 : out std_logic;
ROB6 : out std_logic;
ROB5 : out std_logic;
ROB4 : out std_logic;
ROB3 : out std_logic;
ROB2 : out std_logic;
ROB1 : out std_logic;
ROB0 : out std_logic;
ROC8 : out std_logic;
ROC7 : out std_logic;
ROC6 : out std_logic;
ROC5 : out std_logic;
ROC4 : out std_logic;
ROC3 : out std_logic;
ROC2 : out std_logic;
ROC1 : out std_logic;
ROC0 : out std_logic;
P17 : out std_logic;
P16 : out std_logic;
P15 : out std_logic;
P14 : out std_logic;
P13 : out std_logic;
P12 : out std_logic;
P11 : out std_logic;
P10 : out std_logic;
P9 : out std_logic;
P8 : out std_logic;
P7 : out std_logic;
P6 : out std_logic;
P5 : out std_logic;
P4 : out std_logic;
P3 : out std_logic;
P2 : out std_logic;
P1 : out std_logic;
P0 : out std_logic;
SIGNEDP : out std_logic );
end component;
component MULT18X18C is
generic (
REG_INPUTA_CLK : string := "NONE";
REG_INPUTA_CE : string := "CE0";
REG_INPUTA_RST : string := "RST0";
REG_INPUTB_CLK : string := "NONE";
REG_INPUTB_CE : string := "CE0";
REG_INPUTB_RST : string := "RST0";
REG_PIPELINE_CLK : string := "NONE";
REG_PIPELINE_CE : string := "CE0";
REG_PIPELINE_RST : string := "RST0";
REG_OUTPUT_CLK : string := "NONE";
REG_OUTPUT_CE : string := "CE0";
REG_OUTPUT_RST : string := "RST0";
CAS_MATCH_REG : string := "FALSE";
MULT_BYPASS : string := "DISABLED";
GSR : string := "ENABLED";
RESETMODE : string := "SYNC" );
port (
A17 : in std_logic;
A16 : in std_logic;
A15 : in std_logic;
A14 : in std_logic;
A13 : in std_logic;
A12 : in std_logic;
A11 : in std_logic;
A10 : in std_logic;
A9 : in std_logic;
A8 : in std_logic;
A7 : in std_logic;
A6 : in std_logic;
A5 : in std_logic;
A4 : in std_logic;
A3 : in std_logic;
A2 : in std_logic;
A1 : in std_logic;
A0 : in std_logic;
B17 : in std_logic;
B16 : in std_logic;
B15 : in std_logic;
B14 : in std_logic;
B13 : in std_logic;
B12 : in std_logic;
B11 : in std_logic;
B10 : in std_logic;
B9 : in std_logic;
B8 : in std_logic;
B7 : in std_logic;
B6 : in std_logic;
B5 : in std_logic;
B4 : in std_logic;
B3 : in std_logic;
B2 : in std_logic;
B1 : in std_logic;
B0 : in std_logic;
SIGNEDA : in std_logic;
SIGNEDB : in std_logic;
SOURCEA : in std_logic;
SOURCEB : in std_logic;
CLK3 : in std_logic;
CLK2 : in std_logic;
CLK1 : in std_logic;
CLK0 : in std_logic;
CE3 : in std_logic;
CE2 : in std_logic;
CE1 : in std_logic;
CE0 : in std_logic;
RST3 : in std_logic;
RST2 : in std_logic;
RST1 : in std_logic;
RST0 : in std_logic;
SRIA17 : in std_logic;
SRIA16 : in std_logic;
SRIA15 : in std_logic;
SRIA14 : in std_logic;
SRIA13 : in std_logic;
SRIA12 : in std_logic;
SRIA11 : in std_logic;
SRIA10 : in std_logic;
SRIA9 : in std_logic;
SRIA8 : in std_logic;
SRIA7 : in std_logic;
SRIA6 : in std_logic;
SRIA5 : in std_logic;
SRIA4 : in std_logic;
SRIA3 : in std_logic;
SRIA2 : in std_logic;
SRIA1 : in std_logic;
SRIA0 : in std_logic;
SRIB17 : in std_logic;
SRIB16 : in std_logic;
SRIB15 : in std_logic;
SRIB14 : in std_logic;
SRIB13 : in std_logic;
SRIB12 : in std_logic;
SRIB11 : in std_logic;
SRIB10 : in std_logic;
SRIB9 : in std_logic;
SRIB8 : in std_logic;
SRIB7 : in std_logic;
SRIB6 : in std_logic;
SRIB5 : in std_logic;
SRIB4 : in std_logic;
SRIB3 : in std_logic;
SRIB2 : in std_logic;
SRIB1 : in std_logic;
SRIB0 : in std_logic;
SROA17 : out std_logic;
SROA16 : out std_logic;
SROA15 : out std_logic;
SROA14 : out std_logic;
SROA13 : out std_logic;
SROA12 : out std_logic;
SROA11 : out std_logic;
SROA10 : out std_logic;
SROA9 : out std_logic;
SROA8 : out std_logic;
SROA7 : out std_logic;
SROA6 : out std_logic;
SROA5 : out std_logic;
SROA4 : out std_logic;
SROA3 : out std_logic;
SROA2 : out std_logic;
SROA1 : out std_logic;
SROA0 : out std_logic;
SROB17 : out std_logic;
SROB16 : out std_logic;
SROB15 : out std_logic;
SROB14 : out std_logic;
SROB13 : out std_logic;
SROB12 : out std_logic;
SROB11 : out std_logic;
SROB10 : out std_logic;
SROB9 : out std_logic;
SROB8 : out std_logic;
SROB7 : out std_logic;
SROB6 : out std_logic;
SROB5 : out std_logic;
SROB4 : out std_logic;
SROB3 : out std_logic;
SROB2 : out std_logic;
SROB1 : out std_logic;
SROB0 : out std_logic;
ROA17 : out std_logic;
ROA16 : out std_logic;
ROA15 : out std_logic;
ROA14 : out std_logic;
ROA13 : out std_logic;
ROA12 : out std_logic;
ROA11 : out std_logic;
ROA10 : out std_logic;
ROA9 : out std_logic;
ROA8 : out std_logic;
ROA7 : out std_logic;
ROA6 : out std_logic;
ROA5 : out std_logic;
ROA4 : out std_logic;
ROA3 : out std_logic;
ROA2 : out std_logic;
ROA1 : out std_logic;
ROA0 : out std_logic;
ROB17 : out std_logic;
ROB16 : out std_logic;
ROB15 : out std_logic;
ROB14 : out std_logic;
ROB13 : out std_logic;
ROB12 : out std_logic;
ROB11 : out std_logic;
ROB10 : out std_logic;
ROB9 : out std_logic;
ROB8 : out std_logic;
ROB7 : out std_logic;
ROB6 : out std_logic;
ROB5 : out std_logic;
ROB4 : out std_logic;
ROB3 : out std_logic;
ROB2 : out std_logic;
ROB1 : out std_logic;
ROB0 : out std_logic;
P35 : out std_logic;
P34 : out std_logic;
P33 : out std_logic;
P32 : out std_logic;
P31 : out std_logic;
P30 : out std_logic;
P29 : out std_logic;
P28 : out std_logic;
P27 : out std_logic;
P26 : out std_logic;
P25 : out std_logic;
P24 : out std_logic;
P23 : out std_logic;
P22 : out std_logic;
P21 : out std_logic;
P20 : out std_logic;
P19 : out std_logic;
P18 : out std_logic;
P17 : out std_logic;
P16 : out std_logic;
P15 : out std_logic;
P14 : out std_logic;
P13 : out std_logic;
P12 : out std_logic;
P11 : out std_logic;
P10 : out std_logic;
P9 : out std_logic;
P8 : out std_logic;
P7 : out std_logic;
P6 : out std_logic;
P5 : out std_logic;
P4 : out std_logic;
P3 : out std_logic;
P2 : out std_logic;
P1 : out std_logic;
P0 : out std_logic;
SIGNEDP : out std_logic );
end component;
component MULT18X18D is
generic (
REG_INPUTA_CLK : string := "NONE";
REG_INPUTA_CE : string := "CE0";
REG_INPUTA_RST : string := "RST0";
REG_INPUTB_CLK : string := "NONE";
REG_INPUTB_CE : string := "CE0";
REG_INPUTB_RST : string := "RST0";
REG_INPUTC_CLK : string := "NONE";
REG_INPUTC_CE : string := "CE0";
REG_INPUTC_RST : string := "RST0";
REG_PIPELINE_CLK : string := "NONE";
REG_PIPELINE_CE : string := "CE0";
REG_PIPELINE_RST : string := "RST0";
REG_OUTPUT_CLK : string := "NONE";
REG_OUTPUT_CE : string := "CE0";
REG_OUTPUT_RST : string := "RST0";
CLK0_DIV : string := "ENABLED";
CLK1_DIV : string := "ENABLED";
CLK2_DIV : string := "ENABLED";
CLK3_DIV : string := "ENABLED";
HIGHSPEED_CLK : string := "NONE";
GSR : string := "ENABLED";
CAS_MATCH_REG : string := "FALSE";
SOURCEB_MODE : string := "B_SHIFT";
MULT_BYPASS : string := "DISABLED";
RESETMODE : string := "SYNC" );
port (
A17 : in std_logic;
A16 : in std_logic;
A15 : in std_logic;
A14 : in std_logic;
A13 : in std_logic;
A12 : in std_logic;
A11 : in std_logic;
A10 : in std_logic;
A9 : in std_logic;
A8 : in std_logic;
A7 : in std_logic;
A6 : in std_logic;
A5 : in std_logic;
A4 : in std_logic;
A3 : in std_logic;
A2 : in std_logic;
A1 : in std_logic;
A0 : in std_logic;
B17 : in std_logic;
B16 : in std_logic;
B15 : in std_logic;
B14 : in std_logic;
B13 : in std_logic;
B12 : in std_logic;
B11 : in std_logic;
B10 : in std_logic;
B9 : in std_logic;
B8 : in std_logic;
B7 : in std_logic;
B6 : in std_logic;
B5 : in std_logic;
B4 : in std_logic;
B3 : in std_logic;
B2 : in std_logic;
B1 : in std_logic;
B0 : in std_logic;
C17 : in std_logic;
C16 : in std_logic;
C15 : in std_logic;
C14 : in std_logic;
C13 : in std_logic;
C12 : in std_logic;
C11 : in std_logic;
C10 : in std_logic;
C9 : in std_logic;
C8 : in std_logic;
C7 : in std_logic;
C6 : in std_logic;
C5 : in std_logic;
C4 : in std_logic;
C3 : in std_logic;
C2 : in std_logic;
C1 : in std_logic;
C0 : in std_logic;
SIGNEDA : in std_logic;
SIGNEDB : in std_logic;
SOURCEA : in std_logic;
SOURCEB : in std_logic;
CLK3 : in std_logic;
CLK2 : in std_logic;
CLK1 : in std_logic;
CLK0 : in std_logic;
CE3 : in std_logic;
CE2 : in std_logic;
CE1 : in std_logic;
CE0 : in std_logic;
RST3 : in std_logic;
RST2 : in std_logic;
RST1 : in std_logic;
RST0 : in std_logic;
SRIA17 : in std_logic;
SRIA16 : in std_logic;
SRIA15 : in std_logic;
SRIA14 : in std_logic;
SRIA13 : in std_logic;
SRIA12 : in std_logic;
SRIA11 : in std_logic;
SRIA10 : in std_logic;
SRIA9 : in std_logic;
SRIA8 : in std_logic;
SRIA7 : in std_logic;
SRIA6 : in std_logic;
SRIA5 : in std_logic;
SRIA4 : in std_logic;
SRIA3 : in std_logic;
SRIA2 : in std_logic;
SRIA1 : in std_logic;
SRIA0 : in std_logic;
SRIB17 : in std_logic;
SRIB16 : in std_logic;
SRIB15 : in std_logic;
SRIB14 : in std_logic;
SRIB13 : in std_logic;
SRIB12 : in std_logic;
SRIB11 : in std_logic;
SRIB10 : in std_logic;
SRIB9 : in std_logic;
SRIB8 : in std_logic;
SRIB7 : in std_logic;
SRIB6 : in std_logic;
SRIB5 : in std_logic;
SRIB4 : in std_logic;
SRIB3 : in std_logic;
SRIB2 : in std_logic;
SRIB1 : in std_logic;
SRIB0 : in std_logic;
SROA17 : out std_logic;
SROA16 : out std_logic;
SROA15 : out std_logic;
SROA14 : out std_logic;
SROA13 : out std_logic;
SROA12 : out std_logic;
SROA11 : out std_logic;
SROA10 : out std_logic;
SROA9 : out std_logic;
SROA8 : out std_logic;
SROA7 : out std_logic;
SROA6 : out std_logic;
SROA5 : out std_logic;
SROA4 : out std_logic;
SROA3 : out std_logic;
SROA2 : out std_logic;
SROA1 : out std_logic;
SROA0 : out std_logic;
SROB17 : out std_logic;
SROB16 : out std_logic;
SROB15 : out std_logic;
SROB14 : out std_logic;
SROB13 : out std_logic;
SROB12 : out std_logic;
SROB11 : out std_logic;
SROB10 : out std_logic;
SROB9 : out std_logic;
SROB8 : out std_logic;
SROB7 : out std_logic;
SROB6 : out std_logic;
SROB5 : out std_logic;
SROB4 : out std_logic;
SROB3 : out std_logic;
SROB2 : out std_logic;
SROB1 : out std_logic;
SROB0 : out std_logic;
ROA17 : out std_logic;
ROA16 : out std_logic;
ROA15 : out std_logic;
ROA14 : out std_logic;
ROA13 : out std_logic;
ROA12 : out std_logic;
ROA11 : out std_logic;
ROA10 : out std_logic;
ROA9 : out std_logic;
ROA8 : out std_logic;
ROA7 : out std_logic;
ROA6 : out std_logic;
ROA5 : out std_logic;
ROA4 : out std_logic;
ROA3 : out std_logic;
ROA2 : out std_logic;
ROA1 : out std_logic;
ROA0 : out std_logic;
ROB17 : out std_logic;
ROB16 : out std_logic;
ROB15 : out std_logic;
ROB14 : out std_logic;
ROB13 : out std_logic;
ROB12 : out std_logic;
ROB11 : out std_logic;
ROB10 : out std_logic;
ROB9 : out std_logic;
ROB8 : out std_logic;
ROB7 : out std_logic;
ROB6 : out std_logic;
ROB5 : out std_logic;
ROB4 : out std_logic;
ROB3 : out std_logic;
ROB2 : out std_logic;
ROB1 : out std_logic;
ROB0 : out std_logic;
ROC17 : out std_logic;
ROC16 : out std_logic;
ROC15 : out std_logic;
ROC14 : out std_logic;
ROC13 : out std_logic;
ROC12 : out std_logic;
ROC11 : out std_logic;
ROC10 : out std_logic;
ROC9 : out std_logic;
ROC8 : out std_logic;
ROC7 : out std_logic;
ROC6 : out std_logic;
ROC5 : out std_logic;
ROC4 : out std_logic;
ROC3 : out std_logic;
ROC2 : out std_logic;
ROC1 : out std_logic;
ROC0 : out std_logic;
P35 : out std_logic;
P34 : out std_logic;
P33 : out std_logic;
P32 : out std_logic;
P31 : out std_logic;
P30 : out std_logic;
P29 : out std_logic;
P28 : out std_logic;
P27 : out std_logic;
P26 : out std_logic;
P25 : out std_logic;
P24 : out std_logic;
P23 : out std_logic;
P22 : out std_logic;
P21 : out std_logic;
P20 : out std_logic;
P19 : out std_logic;
P18 : out std_logic;
P17 : out std_logic;
P16 : out std_logic;
P15 : out std_logic;
P14 : out std_logic;
P13 : out std_logic;
P12 : out std_logic;
P11 : out std_logic;
P10 : out std_logic;
P9 : out std_logic;
P8 : out std_logic;
P7 : out std_logic;
P6 : out std_logic;
P5 : out std_logic;
P4 : out std_logic;
P3 : out std_logic;
P2 : out std_logic;
P1 : out std_logic;
P0 : out std_logic;
SIGNEDP : out std_logic );
end component;
component ALU24A is
generic (
REG_OUTPUT_CLK : string := "NONE";
REG_OUTPUT_CE : string := "CE0";
REG_OUTPUT_RST : string := "RST0";
REG_OPCODE_0_CLK : string := "NONE";
REG_OPCODE_0_CE : string := "CE0";
REG_OPCODE_0_RST : string := "RST0";
REG_OPCODE_1_CLK : string := "NONE";
REG_OPCODE_1_CE : string := "CE0";
REG_OPCODE_1_RST : string := "RST0";
GSR : string := "ENABLED";
RESETMODE : string := "SYNC" );
port (
CE3 : in std_logic;
CE2 : in std_logic;
CE1 : in std_logic;
CE0 : in std_logic;
CLK3 : in std_logic;
CLK2 : in std_logic;
CLK1 : in std_logic;
CLK0 : in std_logic;
RST3 : in std_logic;
RST2 : in std_logic;
RST1 : in std_logic;
RST0 : in std_logic;
SIGNEDIA : in std_logic;
SIGNEDIB : in std_logic;
MA17 : in std_logic;
MA16 : in std_logic;
MA15 : in std_logic;
MA14 : in std_logic;
MA13 : in std_logic;
MA12 : in std_logic;
MA11 : in std_logic;
MA10 : in std_logic;
MA9 : in std_logic;
MA8 : in std_logic;
MA7 : in std_logic;
MA6 : in std_logic;
MA5 : in std_logic;
MA4 : in std_logic;
MA3 : in std_logic;
MA2 : in std_logic;
MA1 : in std_logic;
MA0 : in std_logic;
MB17 : in std_logic;
MB16 : in std_logic;
MB15 : in std_logic;
MB14 : in std_logic;
MB13 : in std_logic;
MB12 : in std_logic;
MB11 : in std_logic;
MB10 : in std_logic;
MB9 : in std_logic;
MB8 : in std_logic;
MB7 : in std_logic;
MB6 : in std_logic;
MB5 : in std_logic;
MB4 : in std_logic;
MB3 : in std_logic;
MB2 : in std_logic;
MB1 : in std_logic;
MB0 : in std_logic;
CIN23 : in std_logic;
CIN22 : in std_logic;
CIN21 : in std_logic;
CIN20 : in std_logic;
CIN19 : in std_logic;
CIN18 : in std_logic;
CIN17 : in std_logic;
CIN16 : in std_logic;
CIN15 : in std_logic;
CIN14 : in std_logic;
CIN13 : in std_logic;
CIN12 : in std_logic;
CIN11 : in std_logic;
CIN10 : in std_logic;
CIN9 : in std_logic;
CIN8 : in std_logic;
CIN7 : in std_logic;
CIN6 : in std_logic;
CIN5 : in std_logic;
CIN4 : in std_logic;
CIN3 : in std_logic;
CIN2 : in std_logic;
CIN1 : in std_logic;
CIN0 : in std_logic;
OPADDNSUB : in std_logic;
OPCINSEL : in std_logic;
R23 : out std_logic;
R22 : out std_logic;
R21 : out std_logic;
R20 : out std_logic;
R19 : out std_logic;
R18 : out std_logic;
R17 : out std_logic;
R16 : out std_logic;
R15 : out std_logic;
R14 : out std_logic;
R13 : out std_logic;
R12 : out std_logic;
R11 : out std_logic;
R10 : out std_logic;
R9 : out std_logic;
R8 : out std_logic;
R7 : out std_logic;
R6 : out std_logic;
R5 : out std_logic;
R4 : out std_logic;
R3 : out std_logic;
R2 : out std_logic;
R1 : out std_logic;
R0 : out std_logic );
end component;
component ALU54A is
generic (
REG_INPUTC0_CLK : string := "NONE";
REG_INPUTC0_CE : string := "CE0";
REG_INPUTC0_RST : string := "RST0";
REG_INPUTC1_CLK : string := "NONE";
REG_INPUTC1_CE : string := "CE0";
REG_INPUTC1_RST : string := "RST0";
REG_OPCODEOP0_0_CLK : string := "NONE";
REG_OPCODEOP0_0_CE : string := "CE0";
REG_OPCODEOP0_0_RST : string := "RST0";
REG_OPCODEOP1_0_CLK : string := "NONE";
REG_OPCODEOP0_1_CLK : string := "NONE";
REG_OPCODEOP0_1_CE : string := "CE0";
REG_OPCODEOP0_1_RST : string := "RST0";
REG_OPCODEOP1_1_CLK : string := "NONE";
REG_OPCODEIN_0_CLK : string := "NONE";
REG_OPCODEIN_0_CE : string := "CE0";
REG_OPCODEIN_0_RST : string := "RST0";
REG_OPCODEIN_1_CLK : string := "NONE";
REG_OPCODEIN_1_CE : string := "CE0";
REG_OPCODEIN_1_RST : string := "RST0";
REG_OUTPUT0_CLK : string := "NONE";
REG_OUTPUT0_CE : string := "CE0";
REG_OUTPUT0_RST : string := "RST0";
REG_OUTPUT1_CLK : string := "NONE";
REG_OUTPUT1_CE : string := "CE0";
REG_OUTPUT1_RST : string := "RST0";
REG_FLAG_CLK : string := "NONE";
REG_FLAG_CE : string := "CE0";
REG_FLAG_RST : string := "RST0";
MCPAT_SOURCE : string := "STATIC";
MASKPAT_SOURCE : string := "STATIC";
MASK01 : string := "0x00000000000000";
MCPAT : string := "0x00000000000000";
MASKPAT : string := "0x00000000000000";
RNDPAT : string := "0x00000000000000";
GSR : string := "ENABLED";
RESETMODE : string := "SYNC";
MULT9_MODE : string := "DISABLED";
LEGACY : string := "DISABLED" );
port (
CE3 : in std_logic;
CE2 : in std_logic;
CE1 : in std_logic;
CE0 : in std_logic;
CLK3 : in std_logic;
CLK2 : in std_logic;
CLK1 : in std_logic;
CLK0 : in std_logic;
RST3 : in std_logic;
RST2 : in std_logic;
RST1 : in std_logic;
RST0 : in std_logic;
SIGNEDIA : in std_logic;
SIGNEDIB : in std_logic;
SIGNEDCIN : in std_logic;
A35 : in std_logic;
A34 : in std_logic;
A33 : in std_logic;
A32 : in std_logic;
A31 : in std_logic;
A30 : in std_logic;
A29 : in std_logic;
A28 : in std_logic;
A27 : in std_logic;
A26 : in std_logic;
A25 : in std_logic;
A24 : in std_logic;
A23 : in std_logic;
A22 : in std_logic;
A21 : in std_logic;
A20 : in std_logic;
A19 : in std_logic;
A18 : in std_logic;
A17 : in std_logic;
A16 : in std_logic;
A15 : in std_logic;
A14 : in std_logic;
A13 : in std_logic;
A12 : in std_logic;
A11 : in std_logic;
A10 : in std_logic;
A9 : in std_logic;
A8 : in std_logic;
A7 : in std_logic;
A6 : in std_logic;
A5 : in std_logic;
A4 : in std_logic;
A3 : in std_logic;
A2 : in std_logic;
A1 : in std_logic;
A0 : in std_logic;
B35 : in std_logic;
B34 : in std_logic;
B33 : in std_logic;
B32 : in std_logic;
B31 : in std_logic;
B30 : in std_logic;
B29 : in std_logic;
B28 : in std_logic;
B27 : in std_logic;
B26 : in std_logic;
B25 : in std_logic;
B24 : in std_logic;
B23 : in std_logic;
B22 : in std_logic;
B21 : in std_logic;
B20 : in std_logic;
B19 : in std_logic;
B18 : in std_logic;
B17 : in std_logic;
B16 : in std_logic;
B15 : in std_logic;
B14 : in std_logic;
B13 : in std_logic;
B12 : in std_logic;
B11 : in std_logic;
B10 : in std_logic;
B9 : in std_logic;
B8 : in std_logic;
B7 : in std_logic;
B6 : in std_logic;
B5 : in std_logic;
B4 : in std_logic;
B3 : in std_logic;
B2 : in std_logic;
B1 : in std_logic;
B0 : in std_logic;
C53 : in std_logic;
C52 : in std_logic;
C51 : in std_logic;
C50 : in std_logic;
C49 : in std_logic;
C48 : in std_logic;
C47 : in std_logic;
C46 : in std_logic;
C45 : in std_logic;
C44 : in std_logic;
C43 : in std_logic;
C42 : in std_logic;
C41 : in std_logic;
C40 : in std_logic;
C39 : in std_logic;
C38 : in std_logic;
C37 : in std_logic;
C36 : in std_logic;
C35 : in std_logic;
C34 : in std_logic;
C33 : in std_logic;
C32 : in std_logic;
C31 : in std_logic;
C30 : in std_logic;
C29 : in std_logic;
C28 : in std_logic;
C27 : in std_logic;
C26 : in std_logic;
C25 : in std_logic;
C24 : in std_logic;
C23 : in std_logic;
C22 : in std_logic;
C21 : in std_logic;
C20 : in std_logic;
C19 : in std_logic;
C18 : in std_logic;
C17 : in std_logic;
C16 : in std_logic;
C15 : in std_logic;
C14 : in std_logic;
C13 : in std_logic;
C12 : in std_logic;
C11 : in std_logic;
C10 : in std_logic;
C9 : in std_logic;
C8 : in std_logic;
C7 : in std_logic;
C6 : in std_logic;
C5 : in std_logic;
C4 : in std_logic;
C3 : in std_logic;
C2 : in std_logic;
C1 : in std_logic;
C0 : in std_logic;
MA35 : in std_logic;
MA34 : in std_logic;
MA33 : in std_logic;
MA32 : in std_logic;
MA31 : in std_logic;
MA30 : in std_logic;
MA29 : in std_logic;
MA28 : in std_logic;
MA27 : in std_logic;
MA26 : in std_logic;
MA25 : in std_logic;
MA24 : in std_logic;
MA23 : in std_logic;
MA22 : in std_logic;
MA21 : in std_logic;
MA20 : in std_logic;
MA19 : in std_logic;
MA18 : in std_logic;
MA17 : in std_logic;
MA16 : in std_logic;
MA15 : in std_logic;
MA14 : in std_logic;
MA13 : in std_logic;
MA12 : in std_logic;
MA11 : in std_logic;
MA10 : in std_logic;
MA9 : in std_logic;
MA8 : in std_logic;
MA7 : in std_logic;
MA6 : in std_logic;
MA5 : in std_logic;
MA4 : in std_logic;
MA3 : in std_logic;
MA2 : in std_logic;
MA1 : in std_logic;
MA0 : in std_logic;
MB35 : in std_logic;
MB34 : in std_logic;
MB33 : in std_logic;
MB32 : in std_logic;
MB31 : in std_logic;
MB30 : in std_logic;
MB29 : in std_logic;
MB28 : in std_logic;
MB27 : in std_logic;
MB26 : in std_logic;
MB25 : in std_logic;
MB24 : in std_logic;
MB23 : in std_logic;
MB22 : in std_logic;
MB21 : in std_logic;
MB20 : in std_logic;
MB19 : in std_logic;
MB18 : in std_logic;
MB17 : in std_logic;
MB16 : in std_logic;
MB15 : in std_logic;
MB14 : in std_logic;
MB13 : in std_logic;
MB12 : in std_logic;
MB11 : in std_logic;
MB10 : in std_logic;
MB9 : in std_logic;
MB8 : in std_logic;
MB7 : in std_logic;
MB6 : in std_logic;
MB5 : in std_logic;
MB4 : in std_logic;
MB3 : in std_logic;
MB2 : in std_logic;
MB1 : in std_logic;
MB0 : in std_logic;
CIN53 : in std_logic;
CIN52 : in std_logic;
CIN51 : in std_logic;
CIN50 : in std_logic;
CIN49 : in std_logic;
CIN48 : in std_logic;
CIN47 : in std_logic;
CIN46 : in std_logic;
CIN45 : in std_logic;
CIN44 : in std_logic;
CIN43 : in std_logic;
CIN42 : in std_logic;
CIN41 : in std_logic;
CIN40 : in std_logic;
CIN39 : in std_logic;
CIN38 : in std_logic;
CIN37 : in std_logic;
CIN36 : in std_logic;
CIN35 : in std_logic;
CIN34 : in std_logic;
CIN33 : in std_logic;
CIN32 : in std_logic;
CIN31 : in std_logic;
CIN30 : in std_logic;
CIN29 : in std_logic;
CIN28 : in std_logic;
CIN27 : in std_logic;
CIN26 : in std_logic;
CIN25 : in std_logic;
CIN24 : in std_logic;
CIN23 : in std_logic;
CIN22 : in std_logic;
CIN21 : in std_logic;
CIN20 : in std_logic;
CIN19 : in std_logic;
CIN18 : in std_logic;
CIN17 : in std_logic;
CIN16 : in std_logic;
CIN15 : in std_logic;
CIN14 : in std_logic;
CIN13 : in std_logic;
CIN12 : in std_logic;
CIN11 : in std_logic;
CIN10 : in std_logic;
CIN9 : in std_logic;
CIN8 : in std_logic;
CIN7 : in std_logic;
CIN6 : in std_logic;
CIN5 : in std_logic;
CIN4 : in std_logic;
CIN3 : in std_logic;
CIN2 : in std_logic;
CIN1 : in std_logic;
CIN0 : in std_logic;
OP10 : in std_logic;
OP9 : in std_logic;
OP8 : in std_logic;
OP7 : in std_logic;
OP6 : in std_logic;
OP5 : in std_logic;
OP4 : in std_logic;
OP3 : in std_logic;
OP2 : in std_logic;
OP1 : in std_logic;
OP0 : in std_logic;
R53 : out std_logic;
R52 : out std_logic;
R51 : out std_logic;
R50 : out std_logic;
R49 : out std_logic;
R48 : out std_logic;
R47 : out std_logic;
R46 : out std_logic;
R45 : out std_logic;
R44 : out std_logic;
R43 : out std_logic;
R42 : out std_logic;
R41 : out std_logic;
R40 : out std_logic;
R39 : out std_logic;
R38 : out std_logic;
R37 : out std_logic;
R36 : out std_logic;
R35 : out std_logic;
R34 : out std_logic;
R33 : out std_logic;
R32 : out std_logic;
R31 : out std_logic;
R30 : out std_logic;
R29 : out std_logic;
R28 : out std_logic;
R27 : out std_logic;
R26 : out std_logic;
R25 : out std_logic;
R24 : out std_logic;
R23 : out std_logic;
R22 : out std_logic;
R21 : out std_logic;
R20 : out std_logic;
R19 : out std_logic;
R18 : out std_logic;
R17 : out std_logic;
R16 : out std_logic;
R15 : out std_logic;
R14 : out std_logic;
R13 : out std_logic;
R12 : out std_logic;
R11 : out std_logic;
R10 : out std_logic;
R9 : out std_logic;
R8 : out std_logic;
R7 : out std_logic;
R6 : out std_logic;
R5 : out std_logic;
R4 : out std_logic;
R3 : out std_logic;
R2 : out std_logic;
R1 : out std_logic;
R0 : out std_logic;
EQZ : out std_logic;
EQZM : out std_logic;
EQOM : out std_logic;
EQPAT : out std_logic;
EQPATB : out std_logic;
OVER : out std_logic;
UNDER : out std_logic;
OVERUNDER : out std_logic;
SIGNEDR : out std_logic );
end component;
component ALU24B is
generic (
REG_OUTPUT_CLK : string := "NONE";
REG_OUTPUT_CE : string := "CE0";
REG_OUTPUT_RST : string := "RST0";
REG_OPCODE_0_CLK : string := "NONE";
REG_OPCODE_0_CE : string := "CE0";
REG_OPCODE_0_RST : string := "RST0";
REG_OPCODE_1_CLK : string := "NONE";
REG_OPCODE_1_CE : string := "CE0";
REG_OPCODE_1_RST : string := "RST0";
REG_INPUTCFB_CLK : string := "NONE";
REG_INPUTCFB_CE : string := "CE0";
REG_INPUTCFB_RST : string := "RST0";
CLK0_DIV : string := "ENABLED";
CLK1_DIV : string := "ENABLED";
CLK2_DIV : string := "ENABLED";
CLK3_DIV : string := "ENABLED";
GSR : string := "ENABLED";
RESETMODE : string := "SYNC" );
port (
CE3 : in std_logic;
CE2 : in std_logic;
CE1 : in std_logic;
CE0 : in std_logic;
CLK3 : in std_logic;
CLK2 : in std_logic;
CLK1 : in std_logic;
CLK0 : in std_logic;
RST3 : in std_logic;
RST2 : in std_logic;
RST1 : in std_logic;
RST0 : in std_logic;
SIGNEDIA : in std_logic;
SIGNEDIB : in std_logic;
MA17 : in std_logic;
MA16 : in std_logic;
MA15 : in std_logic;
MA14 : in std_logic;
MA13 : in std_logic;
MA12 : in std_logic;
MA11 : in std_logic;
MA10 : in std_logic;
MA9 : in std_logic;
MA8 : in std_logic;
MA7 : in std_logic;
MA6 : in std_logic;
MA5 : in std_logic;
MA4 : in std_logic;
MA3 : in std_logic;
MA2 : in std_logic;
MA1 : in std_logic;
MA0 : in std_logic;
MB17 : in std_logic;
MB16 : in std_logic;
MB15 : in std_logic;
MB14 : in std_logic;
MB13 : in std_logic;
MB12 : in std_logic;
MB11 : in std_logic;
MB10 : in std_logic;
MB9 : in std_logic;
MB8 : in std_logic;
MB7 : in std_logic;
MB6 : in std_logic;
MB5 : in std_logic;
MB4 : in std_logic;
MB3 : in std_logic;
MB2 : in std_logic;
MB1 : in std_logic;
MB0 : in std_logic;
CFB23 : in std_logic;
CFB22 : in std_logic;
CFB21 : in std_logic;
CFB20 : in std_logic;
CFB19 : in std_logic;
CFB18 : in std_logic;
CFB17 : in std_logic;
CFB16 : in std_logic;
CFB15 : in std_logic;
CFB14 : in std_logic;
CFB13 : in std_logic;
CFB12 : in std_logic;
CFB11 : in std_logic;
CFB10 : in std_logic;
CFB9 : in std_logic;
CFB8 : in std_logic;
CFB7 : in std_logic;
CFB6 : in std_logic;
CFB5 : in std_logic;
CFB4 : in std_logic;
CFB3 : in std_logic;
CFB2 : in std_logic;
CFB1 : in std_logic;
CFB0 : in std_logic;
CIN23 : in std_logic;
CIN22 : in std_logic;
CIN21 : in std_logic;
CIN20 : in std_logic;
CIN19 : in std_logic;
CIN18 : in std_logic;
CIN17 : in std_logic;
CIN16 : in std_logic;
CIN15 : in std_logic;
CIN14 : in std_logic;
CIN13 : in std_logic;
CIN12 : in std_logic;
CIN11 : in std_logic;
CIN10 : in std_logic;
CIN9 : in std_logic;
CIN8 : in std_logic;
CIN7 : in std_logic;
CIN6 : in std_logic;
CIN5 : in std_logic;
CIN4 : in std_logic;
CIN3 : in std_logic;
CIN2 : in std_logic;
CIN1 : in std_logic;
CIN0 : in std_logic;
OPADDNSUB : in std_logic;
OPCINSEL : in std_logic;
R23 : out std_logic;
R22 : out std_logic;
R21 : out std_logic;
R20 : out std_logic;
R19 : out std_logic;
R18 : out std_logic;
R17 : out std_logic;
R16 : out std_logic;
R15 : out std_logic;
R14 : out std_logic;
R13 : out std_logic;
R12 : out std_logic;
R11 : out std_logic;
R10 : out std_logic;
R9 : out std_logic;
R8 : out std_logic;
R7 : out std_logic;
R6 : out std_logic;
R5 : out std_logic;
R4 : out std_logic;
R3 : out std_logic;
R2 : out std_logic;
R1 : out std_logic;
R0 : out std_logic;
CO23 : out std_logic;
CO22 : out std_logic;
CO21 : out std_logic;
CO20 : out std_logic;
CO19 : out std_logic;
CO18 : out std_logic;
CO17 : out std_logic;
CO16 : out std_logic;
CO15 : out std_logic;
CO14 : out std_logic;
CO13 : out std_logic;
CO12 : out std_logic;
CO11 : out std_logic;
CO10 : out std_logic;
CO9 : out std_logic;
CO8 : out std_logic;
CO7 : out std_logic;
CO6 : out std_logic;
CO5 : out std_logic;
CO4 : out std_logic;
CO3 : out std_logic;
CO2 : out std_logic;
CO1 : out std_logic;
CO0 : out std_logic );
end component;
component ALU54B is
generic (
REG_INPUTC0_CLK : string := "NONE";
REG_INPUTC0_CE : string := "CE0";
REG_INPUTC0_RST : string := "RST0";
REG_INPUTC1_CLK : string := "NONE";
REG_INPUTC1_CE : string := "CE0";
REG_INPUTC1_RST : string := "RST0";
REG_OPCODEOP0_0_CLK : string := "NONE";
REG_OPCODEOP0_0_CE : string := "CE0";
REG_OPCODEOP0_0_RST : string := "RST0";
REG_OPCODEOP1_0_CLK : string := "NONE";
REG_OPCODEOP0_1_CLK : string := "NONE";
REG_OPCODEOP0_1_CE : string := "CE0";
REG_OPCODEOP0_1_RST : string := "RST0";
REG_OPCODEOP1_1_CLK : string := "NONE";
REG_OPCODEIN_0_CLK : string := "NONE";
REG_OPCODEIN_0_CE : string := "CE0";
REG_OPCODEIN_0_RST : string := "RST0";
REG_OPCODEIN_1_CLK : string := "NONE";
REG_OPCODEIN_1_CE : string := "CE0";
REG_OPCODEIN_1_RST : string := "RST0";
REG_OUTPUT0_CLK : string := "NONE";
REG_OUTPUT0_CE : string := "CE0";
REG_OUTPUT0_RST : string := "RST0";
REG_OUTPUT1_CLK : string := "NONE";
REG_OUTPUT1_CE : string := "CE0";
REG_OUTPUT1_RST : string := "RST0";
REG_FLAG_CLK : string := "NONE";
REG_FLAG_CE : string := "CE0";
REG_FLAG_RST : string := "RST0";
MCPAT_SOURCE : string := "STATIC";
MASKPAT_SOURCE : string := "STATIC";
MASK01 : string := "0x00000000000000";
REG_INPUTCFB_CLK : string := "NONE";
REG_INPUTCFB_CE : string := "CE0";
REG_INPUTCFB_RST : string := "RST0";
CLK0_DIV : string := "ENABLED";
CLK1_DIV : string := "ENABLED";
CLK2_DIV : string := "ENABLED";
CLK3_DIV : string := "ENABLED";
MCPAT : string := "0x00000000000000";
MASKPAT : string := "0x00000000000000";
RNDPAT : string := "0x00000000000000";
GSR : string := "ENABLED";
RESETMODE : string := "SYNC";
MULT9_MODE : string := "DISABLED";
LEGACY : string := "DISABLED" );
port (
CE3 : in std_logic;
CE2 : in std_logic;
CE1 : in std_logic;
CE0 : in std_logic;
CLK3 : in std_logic;
CLK2 : in std_logic;
CLK1 : in std_logic;
CLK0 : in std_logic;
RST3 : in std_logic;
RST2 : in std_logic;
RST1 : in std_logic;
RST0 : in std_logic;
SIGNEDIA : in std_logic;
SIGNEDIB : in std_logic;
SIGNEDCIN : in std_logic;
A35 : in std_logic;
A34 : in std_logic;
A33 : in std_logic;
A32 : in std_logic;
A31 : in std_logic;
A30 : in std_logic;
A29 : in std_logic;
A28 : in std_logic;
A27 : in std_logic;
A26 : in std_logic;
A25 : in std_logic;
A24 : in std_logic;
A23 : in std_logic;
A22 : in std_logic;
A21 : in std_logic;
A20 : in std_logic;
A19 : in std_logic;
A18 : in std_logic;
A17 : in std_logic;
A16 : in std_logic;
A15 : in std_logic;
A14 : in std_logic;
A13 : in std_logic;
A12 : in std_logic;
A11 : in std_logic;
A10 : in std_logic;
A9 : in std_logic;
A8 : in std_logic;
A7 : in std_logic;
A6 : in std_logic;
A5 : in std_logic;
A4 : in std_logic;
A3 : in std_logic;
A2 : in std_logic;
A1 : in std_logic;
A0 : in std_logic;
B35 : in std_logic;
B34 : in std_logic;
B33 : in std_logic;
B32 : in std_logic;
B31 : in std_logic;
B30 : in std_logic;
B29 : in std_logic;
B28 : in std_logic;
B27 : in std_logic;
B26 : in std_logic;
B25 : in std_logic;
B24 : in std_logic;
B23 : in std_logic;
B22 : in std_logic;
B21 : in std_logic;
B20 : in std_logic;
B19 : in std_logic;
B18 : in std_logic;
B17 : in std_logic;
B16 : in std_logic;
B15 : in std_logic;
B14 : in std_logic;
B13 : in std_logic;
B12 : in std_logic;
B11 : in std_logic;
B10 : in std_logic;
B9 : in std_logic;
B8 : in std_logic;
B7 : in std_logic;
B6 : in std_logic;
B5 : in std_logic;
B4 : in std_logic;
B3 : in std_logic;
B2 : in std_logic;
B1 : in std_logic;
B0 : in std_logic;
C53 : in std_logic;
C52 : in std_logic;
C51 : in std_logic;
C50 : in std_logic;
C49 : in std_logic;
C48 : in std_logic;
C47 : in std_logic;
C46 : in std_logic;
C45 : in std_logic;
C44 : in std_logic;
C43 : in std_logic;
C42 : in std_logic;
C41 : in std_logic;
C40 : in std_logic;
C39 : in std_logic;
C38 : in std_logic;
C37 : in std_logic;
C36 : in std_logic;
C35 : in std_logic;
C34 : in std_logic;
C33 : in std_logic;
C32 : in std_logic;
C31 : in std_logic;
C30 : in std_logic;
C29 : in std_logic;
C28 : in std_logic;
C27 : in std_logic;
C26 : in std_logic;
C25 : in std_logic;
C24 : in std_logic;
C23 : in std_logic;
C22 : in std_logic;
C21 : in std_logic;
C20 : in std_logic;
C19 : in std_logic;
C18 : in std_logic;
C17 : in std_logic;
C16 : in std_logic;
C15 : in std_logic;
C14 : in std_logic;
C13 : in std_logic;
C12 : in std_logic;
C11 : in std_logic;
C10 : in std_logic;
C9 : in std_logic;
C8 : in std_logic;
C7 : in std_logic;
C6 : in std_logic;
C5 : in std_logic;
C4 : in std_logic;
C3 : in std_logic;
C2 : in std_logic;
C1 : in std_logic;
C0 : in std_logic;
CFB53 : in std_logic;
CFB52 : in std_logic;
CFB51 : in std_logic;
CFB50 : in std_logic;
CFB49 : in std_logic;
CFB48 : in std_logic;
CFB47 : in std_logic;
CFB46 : in std_logic;
CFB45 : in std_logic;
CFB44 : in std_logic;
CFB43 : in std_logic;
CFB42 : in std_logic;
CFB41 : in std_logic;
CFB40 : in std_logic;
CFB39 : in std_logic;
CFB38 : in std_logic;
CFB37 : in std_logic;
CFB36 : in std_logic;
CFB35 : in std_logic;
CFB34 : in std_logic;
CFB33 : in std_logic;
CFB32 : in std_logic;
CFB31 : in std_logic;
CFB30 : in std_logic;
CFB29 : in std_logic;
CFB28 : in std_logic;
CFB27 : in std_logic;
CFB26 : in std_logic;
CFB25 : in std_logic;
CFB24 : in std_logic;
CFB23 : in std_logic;
CFB22 : in std_logic;
CFB21 : in std_logic;
CFB20 : in std_logic;
CFB19 : in std_logic;
CFB18 : in std_logic;
CFB17 : in std_logic;
CFB16 : in std_logic;
CFB15 : in std_logic;
CFB14 : in std_logic;
CFB13 : in std_logic;
CFB12 : in std_logic;
CFB11 : in std_logic;
CFB10 : in std_logic;
CFB9 : in std_logic;
CFB8 : in std_logic;
CFB7 : in std_logic;
CFB6 : in std_logic;
CFB5 : in std_logic;
CFB4 : in std_logic;
CFB3 : in std_logic;
CFB2 : in std_logic;
CFB1 : in std_logic;
CFB0 : in std_logic;
MA35 : in std_logic;
MA34 : in std_logic;
MA33 : in std_logic;
MA32 : in std_logic;
MA31 : in std_logic;
MA30 : in std_logic;
MA29 : in std_logic;
MA28 : in std_logic;
MA27 : in std_logic;
MA26 : in std_logic;
MA25 : in std_logic;
MA24 : in std_logic;
MA23 : in std_logic;
MA22 : in std_logic;
MA21 : in std_logic;
MA20 : in std_logic;
MA19 : in std_logic;
MA18 : in std_logic;
MA17 : in std_logic;
MA16 : in std_logic;
MA15 : in std_logic;
MA14 : in std_logic;
MA13 : in std_logic;
MA12 : in std_logic;
MA11 : in std_logic;
MA10 : in std_logic;
MA9 : in std_logic;
MA8 : in std_logic;
MA7 : in std_logic;
MA6 : in std_logic;
MA5 : in std_logic;
MA4 : in std_logic;
MA3 : in std_logic;
MA2 : in std_logic;
MA1 : in std_logic;
MA0 : in std_logic;
MB35 : in std_logic;
MB34 : in std_logic;
MB33 : in std_logic;
MB32 : in std_logic;
MB31 : in std_logic;
MB30 : in std_logic;
MB29 : in std_logic;
MB28 : in std_logic;
MB27 : in std_logic;
MB26 : in std_logic;
MB25 : in std_logic;
MB24 : in std_logic;
MB23 : in std_logic;
MB22 : in std_logic;
MB21 : in std_logic;
MB20 : in std_logic;
MB19 : in std_logic;
MB18 : in std_logic;
MB17 : in std_logic;
MB16 : in std_logic;
MB15 : in std_logic;
MB14 : in std_logic;
MB13 : in std_logic;
MB12 : in std_logic;
MB11 : in std_logic;
MB10 : in std_logic;
MB9 : in std_logic;
MB8 : in std_logic;
MB7 : in std_logic;
MB6 : in std_logic;
MB5 : in std_logic;
MB4 : in std_logic;
MB3 : in std_logic;
MB2 : in std_logic;
MB1 : in std_logic;
MB0 : in std_logic;
CIN53 : in std_logic;
CIN52 : in std_logic;
CIN51 : in std_logic;
CIN50 : in std_logic;
CIN49 : in std_logic;
CIN48 : in std_logic;
CIN47 : in std_logic;
CIN46 : in std_logic;
CIN45 : in std_logic;
CIN44 : in std_logic;
CIN43 : in std_logic;
CIN42 : in std_logic;
CIN41 : in std_logic;
CIN40 : in std_logic;
CIN39 : in std_logic;
CIN38 : in std_logic;
CIN37 : in std_logic;
CIN36 : in std_logic;
CIN35 : in std_logic;
CIN34 : in std_logic;
CIN33 : in std_logic;
CIN32 : in std_logic;
CIN31 : in std_logic;
CIN30 : in std_logic;
CIN29 : in std_logic;
CIN28 : in std_logic;
CIN27 : in std_logic;
CIN26 : in std_logic;
CIN25 : in std_logic;
CIN24 : in std_logic;
CIN23 : in std_logic;
CIN22 : in std_logic;
CIN21 : in std_logic;
CIN20 : in std_logic;
CIN19 : in std_logic;
CIN18 : in std_logic;
CIN17 : in std_logic;
CIN16 : in std_logic;
CIN15 : in std_logic;
CIN14 : in std_logic;
CIN13 : in std_logic;
CIN12 : in std_logic;
CIN11 : in std_logic;
CIN10 : in std_logic;
CIN9 : in std_logic;
CIN8 : in std_logic;
CIN7 : in std_logic;
CIN6 : in std_logic;
CIN5 : in std_logic;
CIN4 : in std_logic;
CIN3 : in std_logic;
CIN2 : in std_logic;
CIN1 : in std_logic;
CIN0 : in std_logic;
OP10 : in std_logic;
OP9 : in std_logic;
OP8 : in std_logic;
OP7 : in std_logic;
OP6 : in std_logic;
OP5 : in std_logic;
OP4 : in std_logic;
OP3 : in std_logic;
OP2 : in std_logic;
OP1 : in std_logic;
OP0 : in std_logic;
R53 : out std_logic;
R52 : out std_logic;
R51 : out std_logic;
R50 : out std_logic;
R49 : out std_logic;
R48 : out std_logic;
R47 : out std_logic;
R46 : out std_logic;
R45 : out std_logic;
R44 : out std_logic;
R43 : out std_logic;
R42 : out std_logic;
R41 : out std_logic;
R40 : out std_logic;
R39 : out std_logic;
R38 : out std_logic;
R37 : out std_logic;
R36 : out std_logic;
R35 : out std_logic;
R34 : out std_logic;
R33 : out std_logic;
R32 : out std_logic;
R31 : out std_logic;
R30 : out std_logic;
R29 : out std_logic;
R28 : out std_logic;
R27 : out std_logic;
R26 : out std_logic;
R25 : out std_logic;
R24 : out std_logic;
R23 : out std_logic;
R22 : out std_logic;
R21 : out std_logic;
R20 : out std_logic;
R19 : out std_logic;
R18 : out std_logic;
R17 : out std_logic;
R16 : out std_logic;
R15 : out std_logic;
R14 : out std_logic;
R13 : out std_logic;
R12 : out std_logic;
R11 : out std_logic;
R10 : out std_logic;
R9 : out std_logic;
R8 : out std_logic;
R7 : out std_logic;
R6 : out std_logic;
R5 : out std_logic;
R4 : out std_logic;
R3 : out std_logic;
R2 : out std_logic;
R1 : out std_logic;
R0 : out std_logic;
CO53 : out std_logic;
CO52 : out std_logic;
CO51 : out std_logic;
CO50 : out std_logic;
CO49 : out std_logic;
CO48 : out std_logic;
CO47 : out std_logic;
CO46 : out std_logic;
CO45 : out std_logic;
CO44 : out std_logic;
CO43 : out std_logic;
CO42 : out std_logic;
CO41 : out std_logic;
CO40 : out std_logic;
CO39 : out std_logic;
CO38 : out std_logic;
CO37 : out std_logic;
CO36 : out std_logic;
CO35 : out std_logic;
CO34 : out std_logic;
CO33 : out std_logic;
CO32 : out std_logic;
CO31 : out std_logic;
CO30 : out std_logic;
CO29 : out std_logic;
CO28 : out std_logic;
CO27 : out std_logic;
CO26 : out std_logic;
CO25 : out std_logic;
CO24 : out std_logic;
CO23 : out std_logic;
CO22 : out std_logic;
CO21 : out std_logic;
CO20 : out std_logic;
CO19 : out std_logic;
CO18 : out std_logic;
CO17 : out std_logic;
CO16 : out std_logic;
CO15 : out std_logic;
CO14 : out std_logic;
CO13 : out std_logic;
CO12 : out std_logic;
CO11 : out std_logic;
CO10 : out std_logic;
CO9 : out std_logic;
CO8 : out std_logic;
CO7 : out std_logic;
CO6 : out std_logic;
CO5 : out std_logic;
CO4 : out std_logic;
CO3 : out std_logic;
CO2 : out std_logic;
CO1 : out std_logic;
CO0 : out std_logic;
EQZ : out std_logic;
EQZM : out std_logic;
EQOM : out std_logic;
EQPAT : out std_logic;
EQPATB : out std_logic;
OVER : out std_logic;
UNDER : out std_logic;
OVERUNDER : out std_logic;
SIGNEDR : out std_logic );
end component;
component PRADD9A is
generic (
REG_INPUTA_CLK : string := "NONE";
REG_INPUTA_CE : string := "CE0";
REG_INPUTA_RST : string := "RST0";
REG_INPUTB_CLK : string := "NONE";
REG_INPUTB_CE : string := "CE0";
REG_INPUTB_RST : string := "RST0";
REG_INPUTC_CLK : string := "NONE";
REG_INPUTC_CE : string := "CE0";
REG_INPUTC_RST : string := "RST0";
REG_OPPRE_CLK : string := "NONE";
REG_OPPRE_CE : string := "CE0";
REG_OPPRE_RST : string := "RST0";
CLK0_DIV : string := "ENABLED";
CLK1_DIV : string := "ENABLED";
CLK2_DIV : string := "ENABLED";
CLK3_DIV : string := "ENABLED";
HIGHSPEED_CLK : string := "NONE";
GSR : string := "ENABLED";
CAS_MATCH_REG : string := "FALSE";
SOURCEA_MODE : string := "A_SHIFT";
SOURCEB_MODE : string := "SHIFT";
FB_MUX : string := "SHIFT";
RESETMODE : string := "SYNC";
SYMMETRY_MODE : string := "DIRECT" );
port (
PA8 : in std_logic;
PA7 : in std_logic;
PA6 : in std_logic;
PA5 : in std_logic;
PA4 : in std_logic;
PA3 : in std_logic;
PA2 : in std_logic;
PA1 : in std_logic;
PA0 : in std_logic;
PB8 : in std_logic;
PB7 : in std_logic;
PB6 : in std_logic;
PB5 : in std_logic;
PB4 : in std_logic;
PB3 : in std_logic;
PB2 : in std_logic;
PB1 : in std_logic;
PB0 : in std_logic;
SRIA8 : in std_logic;
SRIA7 : in std_logic;
SRIA6 : in std_logic;
SRIA5 : in std_logic;
SRIA4 : in std_logic;
SRIA3 : in std_logic;
SRIA2 : in std_logic;
SRIA1 : in std_logic;
SRIA0 : in std_logic;
SRIB8 : in std_logic;
SRIB7 : in std_logic;
SRIB6 : in std_logic;
SRIB5 : in std_logic;
SRIB4 : in std_logic;
SRIB3 : in std_logic;
SRIB2 : in std_logic;
SRIB1 : in std_logic;
SRIB0 : in std_logic;
C8 : in std_logic;
C7 : in std_logic;
C6 : in std_logic;
C5 : in std_logic;
C4 : in std_logic;
C3 : in std_logic;
C2 : in std_logic;
C1 : in std_logic;
C0 : in std_logic;
SOURCEA : in std_logic;
OPPRE : in std_logic;
CLK3 : in std_logic;
CLK2 : in std_logic;
CLK1 : in std_logic;
CLK0 : in std_logic;
CE3 : in std_logic;
CE2 : in std_logic;
CE1 : in std_logic;
CE0 : in std_logic;
RST3 : in std_logic;
RST2 : in std_logic;
RST1 : in std_logic;
RST0 : in std_logic;
SROA8 : out std_logic;
SROA7 : out std_logic;
SROA6 : out std_logic;
SROA5 : out std_logic;
SROA4 : out std_logic;
SROA3 : out std_logic;
SROA2 : out std_logic;
SROA1 : out std_logic;
SROA0 : out std_logic;
SROB8 : out std_logic;
SROB7 : out std_logic;
SROB6 : out std_logic;
SROB5 : out std_logic;
SROB4 : out std_logic;
SROB3 : out std_logic;
SROB2 : out std_logic;
SROB1 : out std_logic;
SROB0 : out std_logic;
PO8 : out std_logic;
PO7 : out std_logic;
PO6 : out std_logic;
PO5 : out std_logic;
PO4 : out std_logic;
PO3 : out std_logic;
PO2 : out std_logic;
PO1 : out std_logic;
PO0 : out std_logic );
end component;
component PRADD18A is
generic (
REG_INPUTA_CLK : string := "NONE";
REG_INPUTA_CE : string := "CE0";
REG_INPUTA_RST : string := "RST0";
REG_INPUTB_CLK : string := "NONE";
REG_INPUTB_CE : string := "CE0";
REG_INPUTB_RST : string := "RST0";
REG_INPUTC_CLK : string := "NONE";
REG_INPUTC_CE : string := "CE0";
REG_INPUTC_RST : string := "RST0";
REG_OPPRE_CLK : string := "NONE";
REG_OPPRE_CE : string := "CE0";
REG_OPPRE_RST : string := "RST0";
CLK0_DIV : string := "ENABLED";
CLK1_DIV : string := "ENABLED";
CLK2_DIV : string := "ENABLED";
CLK3_DIV : string := "ENABLED";
HIGHSPEED_CLK : string := "NONE";
GSR : string := "ENABLED";
CAS_MATCH_REG : string := "FALSE";
SOURCEA_MODE : string := "A_SHIFT";
SOURCEB_MODE : string := "SHIFT";
FB_MUX : string := "SHIFT";
RESETMODE : string := "SYNC";
SYMMETRY_MODE : string := "DIRECT" );
port (
PA17 : in std_logic;
PA16 : in std_logic;
PA15 : in std_logic;
PA14 : in std_logic;
PA13 : in std_logic;
PA12 : in std_logic;
PA11 : in std_logic;
PA10 : in std_logic;
PA9 : in std_logic;
PA8 : in std_logic;
PA7 : in std_logic;
PA6 : in std_logic;
PA5 : in std_logic;
PA4 : in std_logic;
PA3 : in std_logic;
PA2 : in std_logic;
PA1 : in std_logic;
PA0 : in std_logic;
PB17 : in std_logic;
PB16 : in std_logic;
PB15 : in std_logic;
PB14 : in std_logic;
PB13 : in std_logic;
PB12 : in std_logic;
PB11 : in std_logic;
PB10 : in std_logic;
PB9 : in std_logic;
PB8 : in std_logic;
PB7 : in std_logic;
PB6 : in std_logic;
PB5 : in std_logic;
PB4 : in std_logic;
PB3 : in std_logic;
PB2 : in std_logic;
PB1 : in std_logic;
PB0 : in std_logic;
SRIA17 : in std_logic;
SRIA16 : in std_logic;
SRIA15 : in std_logic;
SRIA14 : in std_logic;
SRIA13 : in std_logic;
SRIA12 : in std_logic;
SRIA11 : in std_logic;
SRIA10 : in std_logic;
SRIA9 : in std_logic;
SRIA8 : in std_logic;
SRIA7 : in std_logic;
SRIA6 : in std_logic;
SRIA5 : in std_logic;
SRIA4 : in std_logic;
SRIA3 : in std_logic;
SRIA2 : in std_logic;
SRIA1 : in std_logic;
SRIA0 : in std_logic;
SRIB17 : in std_logic;
SRIB16 : in std_logic;
SRIB15 : in std_logic;
SRIB14 : in std_logic;
SRIB13 : in std_logic;
SRIB12 : in std_logic;
SRIB11 : in std_logic;
SRIB10 : in std_logic;
SRIB9 : in std_logic;
SRIB8 : in std_logic;
SRIB7 : in std_logic;
SRIB6 : in std_logic;
SRIB5 : in std_logic;
SRIB4 : in std_logic;
SRIB3 : in std_logic;
SRIB2 : in std_logic;
SRIB1 : in std_logic;
SRIB0 : in std_logic;
C17 : in std_logic;
C16 : in std_logic;
C15 : in std_logic;
C14 : in std_logic;
C13 : in std_logic;
C12 : in std_logic;
C11 : in std_logic;
C10 : in std_logic;
C9 : in std_logic;
C8 : in std_logic;
C7 : in std_logic;
C6 : in std_logic;
C5 : in std_logic;
C4 : in std_logic;
C3 : in std_logic;
C2 : in std_logic;
C1 : in std_logic;
C0 : in std_logic;
SOURCEA : in std_logic;
OPPRE : in std_logic;
CLK3 : in std_logic;
CLK2 : in std_logic;
CLK1 : in std_logic;
CLK0 : in std_logic;
CE3 : in std_logic;
CE2 : in std_logic;
CE1 : in std_logic;
CE0 : in std_logic;
RST3 : in std_logic;
RST2 : in std_logic;
RST1 : in std_logic;
RST0 : in std_logic;
SROA17 : out std_logic;
SROA16 : out std_logic;
SROA15 : out std_logic;
SROA14 : out std_logic;
SROA13 : out std_logic;
SROA12 : out std_logic;
SROA11 : out std_logic;
SROA10 : out std_logic;
SROA9 : out std_logic;
SROA8 : out std_logic;
SROA7 : out std_logic;
SROA6 : out std_logic;
SROA5 : out std_logic;
SROA4 : out std_logic;
SROA3 : out std_logic;
SROA2 : out std_logic;
SROA1 : out std_logic;
SROA0 : out std_logic;
SROB17 : out std_logic;
SROB16 : out std_logic;
SROB15 : out std_logic;
SROB14 : out std_logic;
SROB13 : out std_logic;
SROB12 : out std_logic;
SROB11 : out std_logic;
SROB10 : out std_logic;
SROB9 : out std_logic;
SROB8 : out std_logic;
SROB7 : out std_logic;
SROB6 : out std_logic;
SROB5 : out std_logic;
SROB4 : out std_logic;
SROB3 : out std_logic;
SROB2 : out std_logic;
SROB1 : out std_logic;
SROB0 : out std_logic;
PO17 : out std_logic;
PO16 : out std_logic;
PO15 : out std_logic;
PO14 : out std_logic;
PO13 : out std_logic;
PO12 : out std_logic;
PO11 : out std_logic;
PO10 : out std_logic;
PO9 : out std_logic;
PO8 : out std_logic;
PO7 : out std_logic;
PO6 : out std_logic;
PO5 : out std_logic;
PO4 : out std_logic;
PO3 : out std_logic;
PO2 : out std_logic;
PO1 : out std_logic;
PO0 : out std_logic );
end component;
component DP16KD is
generic (
DATA_WIDTH_A : integer := 18;
DATA_WIDTH_B : integer := 18;
REGMODE_A : string := "NOREG";
REGMODE_B : string := "NOREG";
RESETMODE : string := "SYNC";
ASYNC_RESET_RELEASE : string := "SYNC";
WRITEMODE_A : string := "NORMAL";
WRITEMODE_B : string := "NORMAL";
CSDECODE_A : string := "0b000";
CSDECODE_B : string := "0b000";
GSR : string := "ENABLED";
INITVAL_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_0A : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_0B : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_0C : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_0D : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_0E : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_0F : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_1A : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_1B : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_1C : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_1D : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_1E : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_1F : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_20 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_21 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_22 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_23 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_24 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_25 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_26 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_27 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_28 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_29 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_2A : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_2B : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_2C : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_2D : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_2E : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_2F : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_30 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_31 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_32 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_33 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_34 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_35 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_36 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_37 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_38 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_39 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_3A : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_3B : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_3C : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_3D : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_3E : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_3F : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_DATA : string := "STATIC" );
port (
DIA17 : in std_logic;
DIA16 : in std_logic;
DIA15 : in std_logic;
DIA14 : in std_logic;
DIA13 : in std_logic;
DIA12 : in std_logic;
DIA11 : in std_logic;
DIA10 : in std_logic;
DIA9 : in std_logic;
DIA8 : in std_logic;
DIA7 : in std_logic;
DIA6 : in std_logic;
DIA5 : in std_logic;
DIA4 : in std_logic;
DIA3 : in std_logic;
DIA2 : in std_logic;
DIA1 : in std_logic;
DIA0 : in std_logic;
ADA13 : in std_logic;
ADA12 : in std_logic;
ADA11 : in std_logic;
ADA10 : in std_logic;
ADA9 : in std_logic;
ADA8 : in std_logic;
ADA7 : in std_logic;
ADA6 : in std_logic;
ADA5 : in std_logic;
ADA4 : in std_logic;
ADA3 : in std_logic;
ADA2 : in std_logic;
ADA1 : in std_logic;
ADA0 : in std_logic;
CEA : in std_logic;
OCEA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
CSA2 : in std_logic;
CSA1 : in std_logic;
CSA0 : in std_logic;
RSTA : in std_logic;
DIB17 : in std_logic;
DIB16 : in std_logic;
DIB15 : in std_logic;
DIB14 : in std_logic;
DIB13 : in std_logic;
DIB12 : in std_logic;
DIB11 : in std_logic;
DIB10 : in std_logic;
DIB9 : in std_logic;
DIB8 : in std_logic;
DIB7 : in std_logic;
DIB6 : in std_logic;
DIB5 : in std_logic;
DIB4 : in std_logic;
DIB3 : in std_logic;
DIB2 : in std_logic;
DIB1 : in std_logic;
DIB0 : in std_logic;
ADB13 : in std_logic;
ADB12 : in std_logic;
ADB11 : in std_logic;
ADB10 : in std_logic;
ADB9 : in std_logic;
ADB8 : in std_logic;
ADB7 : in std_logic;
ADB6 : in std_logic;
ADB5 : in std_logic;
ADB4 : in std_logic;
ADB3 : in std_logic;
ADB2 : in std_logic;
ADB1 : in std_logic;
ADB0 : in std_logic;
CEB : in std_logic;
OCEB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
CSB2 : in std_logic;
CSB1 : in std_logic;
CSB0 : in std_logic;
RSTB : in std_logic;
DOA17 : out std_logic;
DOA16 : out std_logic;
DOA15 : out std_logic;
DOA14 : out std_logic;
DOA13 : out std_logic;
DOA12 : out std_logic;
DOA11 : out std_logic;
DOA10 : out std_logic;
DOA9 : out std_logic;
DOA8 : out std_logic;
DOA7 : out std_logic;
DOA6 : out std_logic;
DOA5 : out std_logic;
DOA4 : out std_logic;
DOA3 : out std_logic;
DOA2 : out std_logic;
DOA1 : out std_logic;
DOA0 : out std_logic;
DOB17 : out std_logic;
DOB16 : out std_logic;
DOB15 : out std_logic;
DOB14 : out std_logic;
DOB13 : out std_logic;
DOB12 : out std_logic;
DOB11 : out std_logic;
DOB10 : out std_logic;
DOB9 : out std_logic;
DOB8 : out std_logic;
DOB7 : out std_logic;
DOB6 : out std_logic;
DOB5 : out std_logic;
DOB4 : out std_logic;
DOB3 : out std_logic;
DOB2 : out std_logic;
DOB1 : out std_logic;
DOB0 : out std_logic );
end component;
component PDPW16KD is
generic (
DATA_WIDTH_W : integer := 36;
DATA_WIDTH_R : integer := 36;
GSR : string := "ENABLED";
REGMODE : string := "NOREG";
RESETMODE : string := "SYNC";
ASYNC_RESET_RELEASE : string := "SYNC";
CSDECODE_W : string := "0b000";
CSDECODE_R : string := "0b000";
INITVAL_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_0A : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_0B : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_0C : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_0D : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_0E : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_0F : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_1A : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_1B : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_1C : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_1D : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_1E : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_1F : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_20 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_21 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_22 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_23 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_24 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_25 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_26 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_27 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_28 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_29 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_2A : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_2B : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_2C : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_2D : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_2E : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_2F : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_30 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_31 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_32 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_33 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_34 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_35 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_36 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_37 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_38 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_39 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_3A : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_3B : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_3C : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_3D : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_3E : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_3F : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_DATA : string := "STATIC" );
port (
DI35 : in std_logic;
DI34 : in std_logic;
DI33 : in std_logic;
DI32 : in std_logic;
DI31 : in std_logic;
DI30 : in std_logic;
DI29 : in std_logic;
DI28 : in std_logic;
DI27 : in std_logic;
DI26 : in std_logic;
DI25 : in std_logic;
DI24 : in std_logic;
DI23 : in std_logic;
DI22 : in std_logic;
DI21 : in std_logic;
DI20 : in std_logic;
DI19 : in std_logic;
DI18 : in std_logic;
DI17 : in std_logic;
DI16 : in std_logic;
DI15 : in std_logic;
DI14 : in std_logic;
DI13 : in std_logic;
DI12 : in std_logic;
DI11 : in std_logic;
DI10 : in std_logic;
DI9 : in std_logic;
DI8 : in std_logic;
DI7 : in std_logic;
DI6 : in std_logic;
DI5 : in std_logic;
DI4 : in std_logic;
DI3 : in std_logic;
DI2 : in std_logic;
DI1 : in std_logic;
DI0 : in std_logic;
ADW8 : in std_logic;
ADW7 : in std_logic;
ADW6 : in std_logic;
ADW5 : in std_logic;
ADW4 : in std_logic;
ADW3 : in std_logic;
ADW2 : in std_logic;
ADW1 : in std_logic;
ADW0 : in std_logic;
BE3 : in std_logic;
BE2 : in std_logic;
BE1 : in std_logic;
BE0 : in std_logic;
CEW : in std_logic;
CLKW : in std_logic;
CSW2 : in std_logic;
CSW1 : in std_logic;
CSW0 : in std_logic;
ADR13 : in std_logic;
ADR12 : in std_logic;
ADR11 : in std_logic;
ADR10 : in std_logic;
ADR9 : in std_logic;
ADR8 : in std_logic;
ADR7 : in std_logic;
ADR6 : in std_logic;
ADR5 : in std_logic;
ADR4 : in std_logic;
ADR3 : in std_logic;
ADR2 : in std_logic;
ADR1 : in std_logic;
ADR0 : in std_logic;
CER : in std_logic;
OCER : in std_logic;
CLKR : in std_logic;
CSR2 : in std_logic;
CSR1 : in std_logic;
CSR0 : in std_logic;
RST : in std_logic;
DO35 : out std_logic;
DO34 : out std_logic;
DO33 : out std_logic;
DO32 : out std_logic;
DO31 : out std_logic;
DO30 : out std_logic;
DO29 : out std_logic;
DO28 : out std_logic;
DO27 : out std_logic;
DO26 : out std_logic;
DO25 : out std_logic;
DO24 : out std_logic;
DO23 : out std_logic;
DO22 : out std_logic;
DO21 : out std_logic;
DO20 : out std_logic;
DO19 : out std_logic;
DO18 : out std_logic;
DO17 : out std_logic;
DO16 : out std_logic;
DO15 : out std_logic;
DO14 : out std_logic;
DO13 : out std_logic;
DO12 : out std_logic;
DO11 : out std_logic;
DO10 : out std_logic;
DO9 : out std_logic;
DO8 : out std_logic;
DO7 : out std_logic;
DO6 : out std_logic;
DO5 : out std_logic;
DO4 : out std_logic;
DO3 : out std_logic;
DO2 : out std_logic;
DO1 : out std_logic;
DO0 : out std_logic );
end component;
component DPR16X4C is
generic (
INITVAL : string := "0x0000000000000000" );
port (
DI3 : in std_logic;
DI2 : in std_logic;
DI1 : in std_logic;
DI0 : in std_logic;
WAD3 : in std_logic;
WAD2 : in std_logic;
WAD1 : in std_logic;
WAD0 : in std_logic;
WCK : in std_logic;
WRE : in std_logic;
RAD3 : in std_logic;
RAD2 : in std_logic;
RAD1 : in std_logic;
RAD0 : in std_logic;
DO3 : out std_logic;
DO2 : out std_logic;
DO1 : out std_logic;
DO0 : out std_logic );
end component;
component SPR16X4C is
generic (
INITVAL : string := "0x0000000000000000" );
port (
DI3 : in std_logic;
DI2 : in std_logic;
DI1 : in std_logic;
DI0 : in std_logic;
AD3 : in std_logic;
AD2 : in std_logic;
AD1 : in std_logic;
AD0 : in std_logic;
CK : in std_logic;
WRE : in std_logic;
DO3 : out std_logic;
DO2 : out std_logic;
DO1 : out std_logic;
DO0 : out std_logic );
end component;
component DTR is
generic (
DTR_TEMP : integer := 25 );
port (
STARTPULSE : in std_logic;
DTROUT7 : out std_logic;
DTROUT6 : out std_logic;
DTROUT5 : out std_logic;
DTROUT4 : out std_logic;
DTROUT3 : out std_logic;
DTROUT2 : out std_logic;
DTROUT1 : out std_logic;
DTROUT0 : out std_logic );
end component;
component CLKDIVF is
generic (
GSR : string := "DISABLED";
DIV : string := "2.0" );
port (
CLKI : in std_logic;
RST : in std_logic;
ALIGNWD : in std_logic;
CDIVX : out std_logic );
end component;
component PCSCLKDIV is
generic (
GSR : string := "DISABLED" );
port (
CLKI : in std_logic;
RST : in std_logic;
SEL2 : in std_logic;
SEL1 : in std_logic;
SEL0 : in std_logic;
CDIV1 : out std_logic;
CDIVX : out std_logic );
end component;
component DCSC is
generic (
DCSMODE : string := "POS" );
port (
CLK1 : in std_logic;
CLK0 : in std_logic;
SEL1 : in std_logic;
SEL0 : in std_logic;
MODESEL : in std_logic;
DCSOUT : out std_logic );
end component;
component ECLKSYNCB is
port (
ECLKI : in std_logic;
STOP : in std_logic;
ECLKO : out std_logic );
end component;
component ECLKBRIDGECS is
port (
CLK0 : in std_logic;
CLK1 : in std_logic;
SEL : in std_logic;
ECSOUT : out std_logic );
end component;
component DCCA is
port (
CLKI : in std_logic;
CE : in std_logic;
CLKO : out std_logic );
end component;
component OSCG is
generic (
DIV : integer := 128 );
port (
OSC : out std_logic );
end component;
component EHXPLLL is
generic (
CLKI_DIV : integer := 1;
CLKFB_DIV : integer := 1;
CLKOP_DIV : integer := 8;
CLKOS_DIV : integer := 8;
CLKOS2_DIV : integer := 8;
CLKOS3_DIV : integer := 8;
CLKOP_ENABLE : string := "ENABLED";
CLKOS_ENABLE : string := "DISABLED";
CLKOS2_ENABLE : string := "DISABLED";
CLKOS3_ENABLE : string := "DISABLED";
CLKOP_CPHASE : integer := 0;
CLKOS_CPHASE : integer := 0;
CLKOS2_CPHASE : integer := 0;
CLKOS3_CPHASE : integer := 0;
CLKOP_FPHASE : integer := 0;
CLKOS_FPHASE : integer := 0;
CLKOS2_FPHASE : integer := 0;
CLKOS3_FPHASE : integer := 0;
FEEDBK_PATH : string := "CLKOP";
CLKOP_TRIM_POL : string := "RISING";
CLKOP_TRIM_DELAY : integer := 0;
CLKOS_TRIM_POL : string := "RISING";
CLKOS_TRIM_DELAY : integer := 0;
OUTDIVIDER_MUXA : string := "DIVA";
OUTDIVIDER_MUXB : string := "DIVB";
OUTDIVIDER_MUXC : string := "DIVC";
OUTDIVIDER_MUXD : string := "DIVD";
PLL_LOCK_MODE : integer := 0;
PLL_LOCK_DELAY : integer := 200;
STDBY_ENABLE : string := "DISABLED";
REFIN_RESET : string := "DISABLED";
SYNC_ENABLE : string := "DISABLED";
INT_LOCK_STICKY : string := "ENABLED";
DPHASE_SOURCE : string := "DISABLED";
PLLRST_ENA : string := "DISABLED";
INTFB_WAKE : string := "DISABLED" );
port (
CLKI : in std_logic;
CLKFB : in std_logic;
PHASESEL1 : in std_logic;
PHASESEL0 : in std_logic;
PHASEDIR : in std_logic;
PHASESTEP : in std_logic;
PHASELOADREG : in std_logic;
STDBY : in std_logic;
PLLWAKESYNC : in std_logic;
RST : in std_logic;
ENCLKOP : in std_logic;
ENCLKOS : in std_logic;
ENCLKOS2 : in std_logic;
ENCLKOS3 : in std_logic;
CLKOP : out std_logic;
CLKOS : out std_logic;
CLKOS2 : out std_logic;
CLKOS3 : out std_logic;
LOCK : out std_logic;
INTLOCK : out std_logic;
REFCLK : out std_logic;
CLKINTFB : out std_logic );
end component;
component PLLREFCS is
port (
CLK0 : in std_logic;
CLK1 : in std_logic;
SEL : in std_logic;
PLLCSOUT : out std_logic );
end component;
component BCINRD is
generic (
BANKID : integer := 2 );
port (
INRDENI : in std_logic );
end component;
component BCLVDSOB is
generic (
BANKID : integer := 2 );
port (
LVDSENI : in std_logic );
end component;
component INRDB is
port (
D : in std_logic;
E : in std_logic;
Q : out std_logic );
end component;
component LVDSOB is
port (
D : in std_logic;
E : in std_logic;
Q : out std_logic );
end component;
component START is
port (
STARTCLK : in std_logic );
end component;
component USRMCLK is
port (
USRMCLKI : in std_logic;
USRMCLKTS : in std_logic );
end component;
component DELAYF is
generic (
DEL_MODE : string := "USER_DEFINED";
DEL_VALUE : integer := 0 );
port (
A : in std_logic;
LOADN : in std_logic;
MOVE : in std_logic;
DIRECTION : in std_logic;
Z : out std_logic;
CFLAG : out std_logic );
end component;
component DELAYG is
generic (
DEL_MODE : string := "USER_DEFINED";
DEL_VALUE : integer := 0 );
port (
A : in std_logic;
Z : out std_logic );
end component;
component DQSBUFM is
generic (
DQS_LI_DEL_VAL : integer := 4;
DQS_LI_DEL_ADJ : string := "FACTORYONLY";
DQS_LO_DEL_VAL : integer := 0;
DQS_LO_DEL_ADJ : string := "FACTORYONLY";
GSR : string := "ENABLED" );
port (
DQSI : in std_logic;
READ1 : in std_logic;
READ0 : in std_logic;
READCLKSEL2 : in std_logic;
READCLKSEL1 : in std_logic;
READCLKSEL0 : in std_logic;
DDRDEL : in std_logic;
ECLK : in std_logic;
SCLK : in std_logic;
RST : in std_logic;
DYNDELAY7 : in std_logic;
DYNDELAY6 : in std_logic;
DYNDELAY5 : in std_logic;
DYNDELAY4 : in std_logic;
DYNDELAY3 : in std_logic;
DYNDELAY2 : in std_logic;
DYNDELAY1 : in std_logic;
DYNDELAY0 : in std_logic;
PAUSE : in std_logic;
RDLOADN : in std_logic;
RDMOVE : in std_logic;
RDDIRECTION : in std_logic;
WRLOADN : in std_logic;
WRMOVE : in std_logic;
WRDIRECTION : in std_logic;
DQSR90 : out std_logic;
DQSW : out std_logic;
DQSW270 : out std_logic;
RDPNTR2 : out std_logic;
RDPNTR1 : out std_logic;
RDPNTR0 : out std_logic;
WRPNTR2 : out std_logic;
WRPNTR1 : out std_logic;
WRPNTR0 : out std_logic;
DATAVALID : out std_logic;
BURSTDET : out std_logic;
RDCFLAG : out std_logic;
WRCFLAG : out std_logic );
end component;
component DDRDLLA is
generic (
FORCE_MAX_DELAY : string := "NO";
LOCK_CYC : integer := 200;
GSR : string := "ENABLED" );
port (
CLK : in std_logic;
RST : in std_logic;
UDDCNTLN : in std_logic;
FREEZE : in std_logic;
DDRDEL : out std_logic;
LOCK : out std_logic;
DCNTL7 : out std_logic;
DCNTL6 : out std_logic;
DCNTL5 : out std_logic;
DCNTL4 : out std_logic;
DCNTL3 : out std_logic;
DCNTL2 : out std_logic;
DCNTL1 : out std_logic;
DCNTL0 : out std_logic );
end component;
component DLLDELD is
port (
A : in std_logic;
DDRDEL : in std_logic;
LOADN : in std_logic;
MOVE : in std_logic;
DIRECTION : in std_logic;
Z : out std_logic;
CFLAG : out std_logic );
end component;
component IDDRX1F is
generic (
GSR : string := "ENABLED" );
port (
D : in std_logic;
SCLK : in std_logic;
RST : in std_logic;
Q0 : out std_logic;
Q1 : out std_logic );
end component;
component IDDRX2F is
generic (
GSR : string := "ENABLED" );
port (
D : in std_logic;
SCLK : in std_logic;
ECLK : in std_logic;
RST : in std_logic;
ALIGNWD : in std_logic;
Q3 : out std_logic;
Q2 : out std_logic;
Q1 : out std_logic;
Q0 : out std_logic );
end component;
component IDDR71B is
generic (
GSR : string := "ENABLED" );
port (
D : in std_logic;
SCLK : in std_logic;
ECLK : in std_logic;
RST : in std_logic;
ALIGNWD : in std_logic;
Q6 : out std_logic;
Q5 : out std_logic;
Q4 : out std_logic;
Q3 : out std_logic;
Q2 : out std_logic;
Q1 : out std_logic;
Q0 : out std_logic );
end component;
component ODDRX1F is
generic (
GSR : string := "ENABLED" );
port (
SCLK : in std_logic;
RST : in std_logic;
D0 : in std_logic;
D1 : in std_logic;
Q : out std_logic );
end component;
component ODDRX2F is
generic (
GSR : string := "ENABLED" );
port (
SCLK : in std_logic;
ECLK : in std_logic;
RST : in std_logic;
D3 : in std_logic;
D2 : in std_logic;
D1 : in std_logic;
D0 : in std_logic;
Q : out std_logic );
end component;
component ODDR71B is
generic (
GSR : string := "ENABLED" );
port (
SCLK : in std_logic;
ECLK : in std_logic;
RST : in std_logic;
D6 : in std_logic;
D5 : in std_logic;
D4 : in std_logic;
D3 : in std_logic;
D2 : in std_logic;
D1 : in std_logic;
D0 : in std_logic;
Q : out std_logic );
end component;
component IMIPI is
port (
A : in std_logic;
AN : in std_logic;
HSSEL : in std_logic;
OHSOLS1 : out std_logic;
OLS0 : out std_logic );
end component;
component IDDRX2DQA is
generic (
GSR : string := "ENABLED" );
port (
SCLK : in std_logic;
ECLK : in std_logic;
DQSR90 : in std_logic;
D : in std_logic;
RST : in std_logic;
RDPNTR2 : in std_logic;
RDPNTR1 : in std_logic;
RDPNTR0 : in std_logic;
WRPNTR2 : in std_logic;
WRPNTR1 : in std_logic;
WRPNTR0 : in std_logic;
Q3 : out std_logic;
Q2 : out std_logic;
Q1 : out std_logic;
Q0 : out std_logic;
QWL : out std_logic );
end component;
component ODDRX2DQA is
generic (
GSR : string := "ENABLED" );
port (
D3 : in std_logic;
D2 : in std_logic;
D1 : in std_logic;
D0 : in std_logic;
DQSW270 : in std_logic;
SCLK : in std_logic;
ECLK : in std_logic;
RST : in std_logic;
Q : out std_logic );
end component;
component ODDRX2DQSB is
generic (
GSR : string := "ENABLED" );
port (
D3 : in std_logic;
D2 : in std_logic;
D1 : in std_logic;
D0 : in std_logic;
SCLK : in std_logic;
ECLK : in std_logic;
DQSW : in std_logic;
RST : in std_logic;
Q : out std_logic );
end component;
component TSHX2DQA is
generic (
GSR : string := "ENABLED";
REGSET : string := "SET" );
port (
T1 : in std_logic;
T0 : in std_logic;
SCLK : in std_logic;
ECLK : in std_logic;
DQSW270 : in std_logic;
RST : in std_logic;
Q : out std_logic );
end component;
component TSHX2DQSA is
generic (
GSR : string := "ENABLED";
REGSET : string := "SET" );
port (
T1 : in std_logic;
T0 : in std_logic;
SCLK : in std_logic;
ECLK : in std_logic;
DQSW : in std_logic;
RST : in std_logic;
Q : out std_logic );
end component;
component OSHX2A is
generic (
GSR : string := "ENABLED" );
port (
D1 : in std_logic;
D0 : in std_logic;
SCLK : in std_logic;
ECLK : in std_logic;
RST : in std_logic;
Q : out std_logic );
end component;
component JTAGG is
generic (
ER1 : string := "ENABLED";
ER2 : string := "ENABLED" );
port (
TCK : in std_logic;
TMS : in std_logic;
TDI : in std_logic;
JTDO2 : in std_logic;
JTDO1 : in std_logic;
TDO : out std_logic;
JTDI : out std_logic;
JTCK : out std_logic;
JRTI2 : out std_logic;
JRTI1 : out std_logic;
JSHIFT : out std_logic;
JUPDATE : out std_logic;
JRSTN : out std_logic;
JCE2 : out std_logic;
JCE1 : out std_logic );
end component;
component SEDGA is
generic (
SED_CLK_FREQ : string := "2.4";
CHECKALWAYS : string := "DISABLED";
DEV_DENSITY : string := "85KUM" );
port (
SEDENABLE : in std_logic;
SEDSTART : in std_logic;
SEDFRCERR : in std_logic;
SEDERR : out std_logic;
SEDDONE : out std_logic;
SEDINPROG : out std_logic;
SEDCLKOUT : out std_logic );
end component;
component EXTREFB is
generic (
REFCK_PWDNB : string := "DONTCARE";
REFCK_RTERM : string := "DONTCARE";
REFCK_DCBIAS_EN : string := "DONTCARE" );
port (
REFCLKP : in std_logic;
REFCLKN : in std_logic;
REFCLKO : out std_logic );
end component;
component PUR is
generic (
RST_PULSE : integer := 1 );
port (
PUR : in std_logic );
end component;
component BUFBA is
port (
A : in std_logic;
Z : out std_logic );
end component;
component OBZPD is
port (
I : in std_logic;
T : in std_logic;
O : out std_logic );
end component;
component SLOGICB is
generic (
TIMINGCHECKSON : boolean := true;
XON : boolean := false;
MSGON : boolean := true;
INSTANCEPATH : string := "SLOGICB";
GSR : string := "ENABLED";
SRMODE : string := "LSR_OVER_CE";
M1MUX : string := "VLO";
M0MUX : string := "VLO";
LSRMUX : string := "VLO";
CEMUX : string := "VLO";
CLKMUX : string := "VLO";
REG1_SD : string := "VLO";
REG0_SD : string := "VLO";
LUT1_INITVAL : bit_vector := "0000000000000000";
LUT0_INITVAL : bit_vector := "0000000000000000";
REG1_REGSET : string := "RESET";
REG0_REGSET : string := "RESET";
LSRONMUX : string := "LSRMUX";
CHECK_M1 : boolean := false;
CHECK_DI1 : boolean := false;
CHECK_DI0 : boolean := false;
CHECK_M0 : boolean := false;
CHECK_CE : boolean := false;
CHECK_LSR : boolean := false );
port (
M1 : in std_ulogic;
FXA : in std_ulogic;
FXB : in std_ulogic;
A1 : in std_ulogic;
B1 : in std_ulogic;
C1 : in std_ulogic;
D1 : in std_ulogic;
DI1 : in std_ulogic;
DI0 : in std_ulogic;
A0 : in std_ulogic;
B0 : in std_ulogic;
C0 : in std_ulogic;
D0 : in std_ulogic;
M0 : in std_ulogic;
CE : in std_ulogic;
CLK : in std_ulogic;
LSR : in std_ulogic;
OFX1 : out std_ulogic;
F1 : out std_ulogic;
Q1 : out std_ulogic;
OFX0 : out std_ulogic;
F0 : out std_ulogic;
Q0 : out std_ulogic );
end component;
component SCCU2C is
generic (
TIMINGCHECKSON : boolean := true;
XON : boolean := false;
MSGON : boolean := true;
INSTANCEPATH : string := "SCCU2C";
GSR : string := "ENABLED";
SRMODE : string := "LSR_OVER_CE";
M1MUX : string := "VLO";
M0MUX : string := "VLO";
LSRMUX : string := "VLO";
CEMUX : string := "VLO";
CLKMUX : string := "VLO";
REG1_SD : string := "VLO";
REG0_SD : string := "VLO";
REG1_REGSET : string := "RESET";
REG0_REGSET : string := "RESET";
LSRONMUX : string := "LSRMUX";
CCU2_INJECT1_0 : string := "YES";
CCU2_INJECT1_1 : string := "YES";
INIT0_INITVAL : std_logic_vector := "0000000000000000";
INIT1_INITVAL : std_logic_vector := "0000000000000000";
CHECK_M1 : boolean := false;
CHECK_DI1 : boolean := false;
CHECK_DI0 : boolean := false;
CHECK_M0 : boolean := false;
CHECK_CE : boolean := false;
CHECK_LSR : boolean := false );
port (
M1 : in std_ulogic;
A1 : in std_ulogic;
B1 : in std_ulogic;
C1 : in std_ulogic;
D1 : in std_ulogic;
DI1 : in std_ulogic;
DI0 : in std_ulogic;
A0 : in std_ulogic;
B0 : in std_ulogic;
C0 : in std_ulogic;
D0 : in std_ulogic;
FCI : in std_ulogic;
M0 : in std_ulogic;
CE : in std_ulogic;
CLK : in std_ulogic;
LSR : in std_ulogic;
FCO : out std_ulogic;
F1 : out std_ulogic;
Q1 : out std_ulogic;
F0 : out std_ulogic;
Q0 : out std_ulogic );
end component;
component SRAMWB is
generic (
TIMINGCHECKSON : boolean := true;
XON : boolean := false;
MSGON : boolean := true;
INSTANCEPATH : string := "SRAMWB";
WD0MUX : string := "VLO";
WD1MUX : string := "VLO";
WD2MUX : string := "VLO";
WD3MUX : string := "VLO";
WAD0MUX : string := "VLO";
WAD1MUX : string := "VLO";
WAD2MUX : string := "VLO";
WAD3MUX : string := "VLO" );
port (
A1 : in std_ulogic;
B1 : in std_ulogic;
C1 : in std_ulogic;
D1 : in std_ulogic;
A0 : in std_ulogic;
B0 : in std_ulogic;
C0 : in std_ulogic;
D0 : in std_ulogic;
WDO0 : out std_ulogic;
WDO1 : out std_ulogic;
WDO2 : out std_ulogic;
WDO3 : out std_ulogic;
WADO0 : out std_ulogic;
WADO1 : out std_ulogic;
WADO2 : out std_ulogic;
WADO3 : out std_ulogic );
end component;
component SDPRAME is
generic (
TIMINGCHECKSON : boolean := true;
XON : boolean := false;
MSGON : boolean := true;
INSTANCEPATH : string := "SDPRAME";
GSR : string := "ENABLED";
SRMODE : string := "LSR_OVER_CE";
M1MUX : string := "VLO";
M0MUX : string := "VLO";
LSRMUX : string := "VLO";
CEMUX : string := "VLO";
CLKMUX : string := "VLO";
WREMUX : string := "VLO";
WCKMUX : string := "VLO";
REG1_SD : string := "VLO";
REG0_SD : string := "VLO";
REG1_REGSET : string := "RESET";
REG0_REGSET : string := "RESET";
LSRONMUX : string := "LSRMUX";
INITVAL : string := "0x0000000000000000";
DPRAM_RAD0 : string := "SIG";
DPRAM_RAD1 : string := "SIG";
DPRAM_RAD2 : string := "SIG";
DPRAM_RAD3 : string := "SIG";
CHECK_WD1 : boolean := false;
CHECK_WD0 : boolean := false;
CHECK_WAD0 : boolean := false;
CHECK_WAD1 : boolean := false;
CHECK_WAD2 : boolean := false;
CHECK_WAD3 : boolean := false;
CHECK_WRE : boolean := false;
CHECK_M0 : boolean := false;
CHECK_M1 : boolean := false;
CHECK_CE : boolean := false;
CHECK_LSR : boolean := false;
CHECK_DI1 : boolean := false;
CHECK_DI0 : boolean := false );
port (
M1 : in std_ulogic;
RAD0 : in std_ulogic;
RAD1 : in std_ulogic;
RAD2 : in std_ulogic;
RAD3 : in std_ulogic;
WD1 : in std_ulogic;
WD0 : in std_ulogic;
WAD0 : in std_ulogic;
WAD1 : in std_ulogic;
WAD2 : in std_ulogic;
WAD3 : in std_ulogic;
WRE : in std_ulogic;
WCK : in std_ulogic;
M0 : in std_ulogic;
CE : in std_ulogic;
CLK : in std_ulogic;
LSR : in std_ulogic;
DI1 : in std_ulogic;
DI0 : in std_ulogic;
F0 : out std_ulogic;
Q0 : out std_ulogic;
F1 : out std_ulogic;
Q1 : out std_ulogic );
end component;
component DCUA is
generic (
D_MACROPDB : string := "DONTCARE";
D_IB_PWDNB : string := "DONTCARE";
D_XGE_MODE : string := "DONTCARE";
D_LOW_MARK : string := "DONTCARE";
D_HIGH_MARK : string := "DONTCARE";
D_BUS8BIT_SEL : string := "DONTCARE";
D_CDR_LOL_SET : string := "DONTCARE";
D_BITCLK_LOCAL_EN : string := "DONTCARE";
D_BITCLK_ND_EN : string := "DONTCARE";
D_BITCLK_FROM_ND_EN : string := "DONTCARE";
D_SYNC_LOCAL_EN : string := "DONTCARE";
D_SYNC_ND_EN : string := "DONTCARE";
CH0_UC_MODE : string := "DONTCARE";
CH1_UC_MODE : string := "DONTCARE";
CH0_PCIE_MODE : string := "DONTCARE";
CH1_PCIE_MODE : string := "DONTCARE";
CH0_RIO_MODE : string := "DONTCARE";
CH1_RIO_MODE : string := "DONTCARE";
CH0_WA_MODE : string := "DONTCARE";
CH1_WA_MODE : string := "DONTCARE";
CH0_INVERT_RX : string := "DONTCARE";
CH1_INVERT_RX : string := "DONTCARE";
CH0_INVERT_TX : string := "DONTCARE";
CH1_INVERT_TX : string := "DONTCARE";
CH0_PRBS_SELECTION : string := "DONTCARE";
CH1_PRBS_SELECTION : string := "DONTCARE";
CH0_GE_AN_ENABLE : string := "DONTCARE";
CH1_GE_AN_ENABLE : string := "DONTCARE";
CH0_PRBS_LOCK : string := "DONTCARE";
CH1_PRBS_LOCK : string := "DONTCARE";
CH0_PRBS_ENABLE : string := "DONTCARE";
CH1_PRBS_ENABLE : string := "DONTCARE";
CH0_ENABLE_CG_ALIGN : string := "DONTCARE";
CH1_ENABLE_CG_ALIGN : string := "DONTCARE";
CH0_TX_GEAR_MODE : string := "DONTCARE";
CH1_TX_GEAR_MODE : string := "DONTCARE";
CH0_RX_GEAR_MODE : string := "DONTCARE";
CH1_RX_GEAR_MODE : string := "DONTCARE";
CH0_PCS_DET_TIME_SEL : string := "DONTCARE";
CH1_PCS_DET_TIME_SEL : string := "DONTCARE";
CH0_PCIE_EI_EN : string := "DONTCARE";
CH1_PCIE_EI_EN : string := "DONTCARE";
CH0_TX_GEAR_BYPASS : string := "DONTCARE";
CH1_TX_GEAR_BYPASS : string := "DONTCARE";
CH0_ENC_BYPASS : string := "DONTCARE";
CH1_ENC_BYPASS : string := "DONTCARE";
CH0_SB_BYPASS : string := "DONTCARE";
CH1_SB_BYPASS : string := "DONTCARE";
CH0_RX_SB_BYPASS : string := "DONTCARE";
CH1_RX_SB_BYPASS : string := "DONTCARE";
CH0_WA_BYPASS : string := "DONTCARE";
CH1_WA_BYPASS : string := "DONTCARE";
CH0_DEC_BYPASS : string := "DONTCARE";
CH1_DEC_BYPASS : string := "DONTCARE";
CH0_CTC_BYPASS : string := "DONTCARE";
CH1_CTC_BYPASS : string := "DONTCARE";
CH0_RX_GEAR_BYPASS : string := "DONTCARE";
CH1_RX_GEAR_BYPASS : string := "DONTCARE";
CH0_LSM_DISABLE : string := "DONTCARE";
CH1_LSM_DISABLE : string := "DONTCARE";
CH0_MATCH_2_ENABLE : string := "DONTCARE";
CH1_MATCH_2_ENABLE : string := "DONTCARE";
CH0_MATCH_4_ENABLE : string := "DONTCARE";
CH1_MATCH_4_ENABLE : string := "DONTCARE";
CH0_MIN_IPG_CNT : string := "DONTCARE";
CH1_MIN_IPG_CNT : string := "DONTCARE";
CH0_CC_MATCH_1 : string := "DONTCARE";
CH1_CC_MATCH_1 : string := "DONTCARE";
CH0_CC_MATCH_2 : string := "DONTCARE";
CH1_CC_MATCH_2 : string := "DONTCARE";
CH0_CC_MATCH_3 : string := "DONTCARE";
CH1_CC_MATCH_3 : string := "DONTCARE";
CH0_CC_MATCH_4 : string := "DONTCARE";
CH1_CC_MATCH_4 : string := "DONTCARE";
CH0_UDF_COMMA_MASK : string := "DONTCARE";
CH1_UDF_COMMA_MASK : string := "DONTCARE";
CH0_UDF_COMMA_A : string := "DONTCARE";
CH1_UDF_COMMA_A : string := "DONTCARE";
CH0_UDF_COMMA_B : string := "DONTCARE";
CH1_UDF_COMMA_B : string := "DONTCARE";
CH0_RX_DCO_CK_DIV : string := "DONTCARE";
CH1_RX_DCO_CK_DIV : string := "DONTCARE";
CH0_RCV_DCC_EN : string := "DONTCARE";
CH1_RCV_DCC_EN : string := "DONTCARE";
CH0_REQ_LVL_SET : string := "DONTCARE";
CH1_REQ_LVL_SET : string := "DONTCARE";
CH0_REQ_EN : string := "DONTCARE";
CH1_REQ_EN : string := "DONTCARE";
CH0_RTERM_RX : string := "DONTCARE";
CH1_RTERM_RX : string := "DONTCARE";
CH0_PDEN_SEL : string := "DONTCARE";
CH1_PDEN_SEL : string := "DONTCARE";
CH0_LDR_RX2CORE_SEL : string := "DONTCARE";
CH1_LDR_RX2CORE_SEL : string := "DONTCARE";
CH0_LDR_CORE2TX_SEL : string := "DONTCARE";
CH1_LDR_CORE2TX_SEL : string := "DONTCARE";
CH0_TPWDNB : string := "DONTCARE";
CH1_TPWDNB : string := "DONTCARE";
CH0_RATE_MODE_TX : string := "DONTCARE";
CH1_RATE_MODE_TX : string := "DONTCARE";
CH0_RTERM_TX : string := "DONTCARE";
CH1_RTERM_TX : string := "DONTCARE";
CH0_TX_CM_SEL : string := "DONTCARE";
CH1_TX_CM_SEL : string := "DONTCARE";
CH0_TDRV_PRE_EN : string := "DONTCARE";
CH1_TDRV_PRE_EN : string := "DONTCARE";
CH0_TDRV_SLICE0_SEL : string := "DONTCARE";
CH1_TDRV_SLICE0_SEL : string := "DONTCARE";
CH0_TDRV_SLICE1_SEL : string := "DONTCARE";
CH1_TDRV_SLICE1_SEL : string := "DONTCARE";
CH0_TDRV_SLICE2_SEL : string := "DONTCARE";
CH1_TDRV_SLICE2_SEL : string := "DONTCARE";
CH0_TDRV_SLICE3_SEL : string := "DONTCARE";
CH1_TDRV_SLICE3_SEL : string := "DONTCARE";
CH0_TDRV_SLICE4_SEL : string := "DONTCARE";
CH1_TDRV_SLICE4_SEL : string := "DONTCARE";
CH0_TDRV_SLICE5_SEL : string := "DONTCARE";
CH1_TDRV_SLICE5_SEL : string := "DONTCARE";
CH0_TDRV_SLICE0_CUR : string := "DONTCARE";
CH1_TDRV_SLICE0_CUR : string := "DONTCARE";
CH0_TDRV_SLICE1_CUR : string := "DONTCARE";
CH1_TDRV_SLICE1_CUR : string := "DONTCARE";
CH0_TDRV_SLICE2_CUR : string := "DONTCARE";
CH1_TDRV_SLICE2_CUR : string := "DONTCARE";
CH0_TDRV_SLICE3_CUR : string := "DONTCARE";
CH1_TDRV_SLICE3_CUR : string := "DONTCARE";
CH0_TDRV_SLICE4_CUR : string := "DONTCARE";
CH1_TDRV_SLICE4_CUR : string := "DONTCARE";
CH0_TDRV_SLICE5_CUR : string := "DONTCARE";
CH1_TDRV_SLICE5_CUR : string := "DONTCARE";
CH0_TDRV_DAT_SEL : string := "DONTCARE";
CH1_TDRV_DAT_SEL : string := "DONTCARE";
CH0_TX_DIV11_SEL : string := "DONTCARE";
CH1_TX_DIV11_SEL : string := "DONTCARE";
CH0_RPWDNB : string := "DONTCARE";
CH1_RPWDNB : string := "DONTCARE";
CH0_RATE_MODE_RX : string := "DONTCARE";
CH1_RATE_MODE_RX : string := "DONTCARE";
CH0_RLOS_SEL : string := "DONTCARE";
CH1_RLOS_SEL : string := "DONTCARE";
CH0_RX_LOS_LVL : string := "DONTCARE";
CH1_RX_LOS_LVL : string := "DONTCARE";
CH0_RX_LOS_CEQ : string := "DONTCARE";
CH1_RX_LOS_CEQ : string := "DONTCARE";
CH0_RX_LOS_HYST_EN : string := "DONTCARE";
CH1_RX_LOS_HYST_EN : string := "DONTCARE";
CH0_RX_LOS_EN : string := "DONTCARE";
CH1_RX_LOS_EN : string := "DONTCARE";
CH0_RX_DIV11_SEL : string := "DONTCARE";
CH1_RX_DIV11_SEL : string := "DONTCARE";
CH0_SEL_SD_RX_CLK : string := "DONTCARE";
CH1_SEL_SD_RX_CLK : string := "DONTCARE";
CH0_FF_RX_H_CLK_EN : string := "DONTCARE";
CH1_FF_RX_H_CLK_EN : string := "DONTCARE";
CH0_FF_RX_F_CLK_DIS : string := "DONTCARE";
CH1_FF_RX_F_CLK_DIS : string := "DONTCARE";
CH0_FF_TX_H_CLK_EN : string := "DONTCARE";
CH1_FF_TX_H_CLK_EN : string := "DONTCARE";
CH0_FF_TX_F_CLK_DIS : string := "DONTCARE";
CH1_FF_TX_F_CLK_DIS : string := "DONTCARE";
CH0_RX_RATE_SEL : string := "DONTCARE";
CH1_RX_RATE_SEL : string := "DONTCARE";
CH0_TDRV_POST_EN : string := "DONTCARE";
CH1_TDRV_POST_EN : string := "DONTCARE";
CH0_TX_POST_SIGN : string := "DONTCARE";
CH1_TX_POST_SIGN : string := "DONTCARE";
CH0_TX_PRE_SIGN : string := "DONTCARE";
CH1_TX_PRE_SIGN : string := "DONTCARE";
CH0_RXTERM_CM : string := "DONTCARE";
CH1_RXTERM_CM : string := "DONTCARE";
CH0_RXIN_CM : string := "DONTCARE";
CH1_RXIN_CM : string := "DONTCARE";
CH0_LEQ_OFFSET_SEL : string := "DONTCARE";
CH1_LEQ_OFFSET_SEL : string := "DONTCARE";
CH0_LEQ_OFFSET_TRIM : string := "DONTCARE";
CH1_LEQ_OFFSET_TRIM : string := "DONTCARE";
D_TX_MAX_RATE : string := "DONTCARE";
CH0_CDR_MAX_RATE : string := "DONTCARE";
CH1_CDR_MAX_RATE : string := "DONTCARE";
CH0_TXAMPLITUDE : string := "DONTCARE";
CH1_TXAMPLITUDE : string := "DONTCARE";
CH0_TXDEPRE : string := "DONTCARE";
CH1_TXDEPRE : string := "DONTCARE";
CH0_TXDEPOST : string := "DONTCARE";
CH1_TXDEPOST : string := "DONTCARE";
CH0_PROTOCOL : string := "DONTCARE";
CH1_PROTOCOL : string := "DONTCARE";
D_ISETLOS : string := "DONTCARE";
D_SETIRPOLY_AUX : string := "DONTCARE";
D_SETICONST_AUX : string := "DONTCARE";
D_SETIRPOLY_CH : string := "DONTCARE";
D_SETICONST_CH : string := "DONTCARE";
D_REQ_ISET : string := "DONTCARE";
D_PD_ISET : string := "DONTCARE";
D_DCO_CALIB_TIME_SEL : string := "DONTCARE";
CH0_DCOCTLGI : string := "DONTCARE";
CH1_DCOCTLGI : string := "DONTCARE";
CH0_DCOATDDLY : string := "DONTCARE";
CH1_DCOATDDLY : string := "DONTCARE";
CH0_DCOATDCFG : string := "DONTCARE";
CH1_DCOATDCFG : string := "DONTCARE";
CH0_DCOBYPSATD : string := "DONTCARE";
CH1_DCOBYPSATD : string := "DONTCARE";
CH0_DCOSCALEI : string := "DONTCARE";
CH1_DCOSCALEI : string := "DONTCARE";
CH0_DCOITUNE4LSB : string := "DONTCARE";
CH1_DCOITUNE4LSB : string := "DONTCARE";
CH0_DCOIOSTUNE : string := "DONTCARE";
CH1_DCOIOSTUNE : string := "DONTCARE";
CH0_DCODISBDAVOID : string := "DONTCARE";
CH1_DCODISBDAVOID : string := "DONTCARE";
CH0_DCOCALDIV : string := "DONTCARE";
CH1_DCOCALDIV : string := "DONTCARE";
CH0_DCONUOFLSB : string := "DONTCARE";
CH1_DCONUOFLSB : string := "DONTCARE";
CH0_DCOIUPDNX2 : string := "DONTCARE";
CH1_DCOIUPDNX2 : string := "DONTCARE";
CH0_DCOSTEP : string := "DONTCARE";
CH1_DCOSTEP : string := "DONTCARE";
CH0_DCOSTARTVAL : string := "DONTCARE";
CH1_DCOSTARTVAL : string := "DONTCARE";
CH0_DCOFLTDAC : string := "DONTCARE";
CH1_DCOFLTDAC : string := "DONTCARE";
CH0_DCOITUNE : string := "DONTCARE";
CH1_DCOITUNE : string := "DONTCARE";
CH0_DCOFTNRG : string := "DONTCARE";
CH1_DCOFTNRG : string := "DONTCARE";
CH0_CDR_CNT4SEL : string := "DONTCARE";
CH1_CDR_CNT4SEL : string := "DONTCARE";
CH0_CDR_CNT8SEL : string := "DONTCARE";
CH1_CDR_CNT8SEL : string := "DONTCARE";
CH0_BAND_THRESHOLD : string := "DONTCARE";
CH1_BAND_THRESHOLD : string := "DONTCARE";
CH0_AUTO_FACQ_EN : string := "DONTCARE";
CH1_AUTO_FACQ_EN : string := "DONTCARE";
CH0_AUTO_CALIB_EN : string := "DONTCARE";
CH1_AUTO_CALIB_EN : string := "DONTCARE";
CH0_CALIB_CK_MODE : string := "DONTCARE";
CH1_CALIB_CK_MODE : string := "DONTCARE";
CH0_REG_BAND_OFFSET : string := "DONTCARE";
CH1_REG_BAND_OFFSET : string := "DONTCARE";
CH0_REG_BAND_SEL : string := "DONTCARE";
CH1_REG_BAND_SEL : string := "DONTCARE";
CH0_REG_IDAC_SEL : string := "DONTCARE";
CH1_REG_IDAC_SEL : string := "DONTCARE";
CH0_REG_IDAC_EN : string := "DONTCARE";
CH1_REG_IDAC_EN : string := "DONTCARE";
D_TXPLL_PWDNB : string := "DONTCARE";
D_SETPLLRC : string := "DONTCARE";
D_REFCK_MODE : string := "DONTCARE";
D_TX_VCO_CK_DIV : string := "DONTCARE";
D_PLL_LOL_SET : string := "DONTCARE";
D_RG_EN : string := "DONTCARE";
D_RG_SET : string := "DONTCARE";
D_CMUSETISCL4VCO : string := "DONTCARE";
D_CMUSETI4VCO : string := "DONTCARE";
D_CMUSETINITVCT : string := "DONTCARE";
D_CMUSETZGM : string := "DONTCARE";
D_CMUSETP2AGM : string := "DONTCARE";
D_CMUSETP1GM : string := "DONTCARE";
D_CMUSETI4CPZ : string := "DONTCARE";
D_CMUSETI4CPP : string := "DONTCARE";
D_CMUSETICP4Z : string := "DONTCARE";
D_CMUSETICP4P : string := "DONTCARE";
D_CMUSETBIASI : string := "DONTCARE" );
port (
CH0_HDINP : in std_logic;
CH1_HDINP : in std_logic;
CH0_HDINN : in std_logic;
CH1_HDINN : in std_logic;
D_TXBIT_CLKP_FROM_ND : in std_logic;
D_TXBIT_CLKN_FROM_ND : in std_logic;
D_SYNC_ND : in std_logic;
D_TXPLL_LOL_FROM_ND : in std_logic;
CH0_RX_REFCLK : in std_logic;
CH1_RX_REFCLK : in std_logic;
CH0_FF_RXI_CLK : in std_logic;
CH1_FF_RXI_CLK : in std_logic;
CH0_FF_TXI_CLK : in std_logic;
CH1_FF_TXI_CLK : in std_logic;
CH0_FF_EBRD_CLK : in std_logic;
CH1_FF_EBRD_CLK : in std_logic;
CH0_FF_TX_D_0 : in std_logic;
CH1_FF_TX_D_0 : in std_logic;
CH0_FF_TX_D_1 : in std_logic;
CH1_FF_TX_D_1 : in std_logic;
CH0_FF_TX_D_2 : in std_logic;
CH1_FF_TX_D_2 : in std_logic;
CH0_FF_TX_D_3 : in std_logic;
CH1_FF_TX_D_3 : in std_logic;
CH0_FF_TX_D_4 : in std_logic;
CH1_FF_TX_D_4 : in std_logic;
CH0_FF_TX_D_5 : in std_logic;
CH1_FF_TX_D_5 : in std_logic;
CH0_FF_TX_D_6 : in std_logic;
CH1_FF_TX_D_6 : in std_logic;
CH0_FF_TX_D_7 : in std_logic;
CH1_FF_TX_D_7 : in std_logic;
CH0_FF_TX_D_8 : in std_logic;
CH1_FF_TX_D_8 : in std_logic;
CH0_FF_TX_D_9 : in std_logic;
CH1_FF_TX_D_9 : in std_logic;
CH0_FF_TX_D_10 : in std_logic;
CH1_FF_TX_D_10 : in std_logic;
CH0_FF_TX_D_11 : in std_logic;
CH1_FF_TX_D_11 : in std_logic;
CH0_FF_TX_D_12 : in std_logic;
CH1_FF_TX_D_12 : in std_logic;
CH0_FF_TX_D_13 : in std_logic;
CH1_FF_TX_D_13 : in std_logic;
CH0_FF_TX_D_14 : in std_logic;
CH1_FF_TX_D_14 : in std_logic;
CH0_FF_TX_D_15 : in std_logic;
CH1_FF_TX_D_15 : in std_logic;
CH0_FF_TX_D_16 : in std_logic;
CH1_FF_TX_D_16 : in std_logic;
CH0_FF_TX_D_17 : in std_logic;
CH1_FF_TX_D_17 : in std_logic;
CH0_FF_TX_D_18 : in std_logic;
CH1_FF_TX_D_18 : in std_logic;
CH0_FF_TX_D_19 : in std_logic;
CH1_FF_TX_D_19 : in std_logic;
CH0_FF_TX_D_20 : in std_logic;
CH1_FF_TX_D_20 : in std_logic;
CH0_FF_TX_D_21 : in std_logic;
CH1_FF_TX_D_21 : in std_logic;
CH0_FF_TX_D_22 : in std_logic;
CH1_FF_TX_D_22 : in std_logic;
CH0_FF_TX_D_23 : in std_logic;
CH1_FF_TX_D_23 : in std_logic;
CH0_FFC_EI_EN : in std_logic;
CH1_FFC_EI_EN : in std_logic;
CH0_FFC_PCIE_DET_EN : in std_logic;
CH1_FFC_PCIE_DET_EN : in std_logic;
CH0_FFC_PCIE_CT : in std_logic;
CH1_FFC_PCIE_CT : in std_logic;
CH0_FFC_SB_INV_RX : in std_logic;
CH1_FFC_SB_INV_RX : in std_logic;
CH0_FFC_ENABLE_CGALIGN : in std_logic;
CH1_FFC_ENABLE_CGALIGN : in std_logic;
CH0_FFC_SIGNAL_DETECT : in std_logic;
CH1_FFC_SIGNAL_DETECT : in std_logic;
CH0_FFC_FB_LOOPBACK : in std_logic;
CH1_FFC_FB_LOOPBACK : in std_logic;
CH0_FFC_SB_PFIFO_LP : in std_logic;
CH1_FFC_SB_PFIFO_LP : in std_logic;
CH0_FFC_PFIFO_CLR : in std_logic;
CH1_FFC_PFIFO_CLR : in std_logic;
CH0_FFC_RATE_MODE_RX : in std_logic;
CH1_FFC_RATE_MODE_RX : in std_logic;
CH0_FFC_RATE_MODE_TX : in std_logic;
CH1_FFC_RATE_MODE_TX : in std_logic;
CH0_FFC_DIV11_MODE_RX : in std_logic;
CH1_FFC_DIV11_MODE_RX : in std_logic;
CH0_FFC_RX_GEAR_MODE : in std_logic;
CH1_FFC_RX_GEAR_MODE : in std_logic;
CH0_FFC_TX_GEAR_MODE : in std_logic;
CH1_FFC_TX_GEAR_MODE : in std_logic;
CH0_FFC_DIV11_MODE_TX : in std_logic;
CH1_FFC_DIV11_MODE_TX : in std_logic;
CH0_FFC_LDR_CORE2TX_EN : in std_logic;
CH1_FFC_LDR_CORE2TX_EN : in std_logic;
CH0_FFC_LANE_TX_RST : in std_logic;
CH1_FFC_LANE_TX_RST : in std_logic;
CH0_FFC_LANE_RX_RST : in std_logic;
CH1_FFC_LANE_RX_RST : in std_logic;
CH0_FFC_RRST : in std_logic;
CH1_FFC_RRST : in std_logic;
CH0_FFC_TXPWDNB : in std_logic;
CH1_FFC_TXPWDNB : in std_logic;
CH0_FFC_RXPWDNB : in std_logic;
CH1_FFC_RXPWDNB : in std_logic;
CH0_LDR_CORE2TX : in std_logic;
CH1_LDR_CORE2TX : in std_logic;
D_SCIWDATA0 : in std_logic;
D_SCIWDATA1 : in std_logic;
D_SCIWDATA2 : in std_logic;
D_SCIWDATA3 : in std_logic;
D_SCIWDATA4 : in std_logic;
D_SCIWDATA5 : in std_logic;
D_SCIWDATA6 : in std_logic;
D_SCIWDATA7 : in std_logic;
D_SCIADDR0 : in std_logic;
D_SCIADDR1 : in std_logic;
D_SCIADDR2 : in std_logic;
D_SCIADDR3 : in std_logic;
D_SCIADDR4 : in std_logic;
D_SCIADDR5 : in std_logic;
D_SCIENAUX : in std_logic;
D_SCISELAUX : in std_logic;
CH0_SCIEN : in std_logic;
CH1_SCIEN : in std_logic;
CH0_SCISEL : in std_logic;
CH1_SCISEL : in std_logic;
D_SCIRD : in std_logic;
D_SCIWSTN : in std_logic;
D_CYAWSTN : in std_logic;
D_FFC_SYNC_TOGGLE : in std_logic;
D_FFC_DUAL_RST : in std_logic;
D_FFC_MACRO_RST : in std_logic;
D_FFC_MACROPDB : in std_logic;
D_FFC_TRST : in std_logic;
CH0_FFC_CDR_EN_BITSLIP : in std_logic;
CH1_FFC_CDR_EN_BITSLIP : in std_logic;
D_SCAN_ENABLE : in std_logic;
D_SCAN_IN_0 : in std_logic;
D_SCAN_IN_1 : in std_logic;
D_SCAN_IN_2 : in std_logic;
D_SCAN_IN_3 : in std_logic;
D_SCAN_IN_4 : in std_logic;
D_SCAN_IN_5 : in std_logic;
D_SCAN_IN_6 : in std_logic;
D_SCAN_IN_7 : in std_logic;
D_SCAN_MODE : in std_logic;
D_SCAN_RESET : in std_logic;
D_CIN0 : in std_logic;
D_CIN1 : in std_logic;
D_CIN2 : in std_logic;
D_CIN3 : in std_logic;
D_CIN4 : in std_logic;
D_CIN5 : in std_logic;
D_CIN6 : in std_logic;
D_CIN7 : in std_logic;
D_CIN8 : in std_logic;
D_CIN9 : in std_logic;
D_CIN10 : in std_logic;
D_CIN11 : in std_logic;
CH0_HDOUTP : out std_logic;
CH1_HDOUTP : out std_logic;
CH0_HDOUTN : out std_logic;
CH1_HDOUTN : out std_logic;
D_TXBIT_CLKP_TO_ND : out std_logic;
D_TXBIT_CLKN_TO_ND : out std_logic;
D_SYNC_PULSE2ND : out std_logic;
D_TXPLL_LOL_TO_ND : out std_logic;
CH0_FF_RX_F_CLK : out std_logic;
CH1_FF_RX_F_CLK : out std_logic;
CH0_FF_RX_H_CLK : out std_logic;
CH1_FF_RX_H_CLK : out std_logic;
CH0_FF_TX_F_CLK : out std_logic;
CH1_FF_TX_F_CLK : out std_logic;
CH0_FF_TX_H_CLK : out std_logic;
CH1_FF_TX_H_CLK : out std_logic;
CH0_FF_RX_PCLK : out std_logic;
CH1_FF_RX_PCLK : out std_logic;
CH0_FF_TX_PCLK : out std_logic;
CH1_FF_TX_PCLK : out std_logic;
CH0_FF_RX_D_0 : out std_logic;
CH1_FF_RX_D_0 : out std_logic;
CH0_FF_RX_D_1 : out std_logic;
CH1_FF_RX_D_1 : out std_logic;
CH0_FF_RX_D_2 : out std_logic;
CH1_FF_RX_D_2 : out std_logic;
CH0_FF_RX_D_3 : out std_logic;
CH1_FF_RX_D_3 : out std_logic;
CH0_FF_RX_D_4 : out std_logic;
CH1_FF_RX_D_4 : out std_logic;
CH0_FF_RX_D_5 : out std_logic;
CH1_FF_RX_D_5 : out std_logic;
CH0_FF_RX_D_6 : out std_logic;
CH1_FF_RX_D_6 : out std_logic;
CH0_FF_RX_D_7 : out std_logic;
CH1_FF_RX_D_7 : out std_logic;
CH0_FF_RX_D_8 : out std_logic;
CH1_FF_RX_D_8 : out std_logic;
CH0_FF_RX_D_9 : out std_logic;
CH1_FF_RX_D_9 : out std_logic;
CH0_FF_RX_D_10 : out std_logic;
CH1_FF_RX_D_10 : out std_logic;
CH0_FF_RX_D_11 : out std_logic;
CH1_FF_RX_D_11 : out std_logic;
CH0_FF_RX_D_12 : out std_logic;
CH1_FF_RX_D_12 : out std_logic;
CH0_FF_RX_D_13 : out std_logic;
CH1_FF_RX_D_13 : out std_logic;
CH0_FF_RX_D_14 : out std_logic;
CH1_FF_RX_D_14 : out std_logic;
CH0_FF_RX_D_15 : out std_logic;
CH1_FF_RX_D_15 : out std_logic;
CH0_FF_RX_D_16 : out std_logic;
CH1_FF_RX_D_16 : out std_logic;
CH0_FF_RX_D_17 : out std_logic;
CH1_FF_RX_D_17 : out std_logic;
CH0_FF_RX_D_18 : out std_logic;
CH1_FF_RX_D_18 : out std_logic;
CH0_FF_RX_D_19 : out std_logic;
CH1_FF_RX_D_19 : out std_logic;
CH0_FF_RX_D_20 : out std_logic;
CH1_FF_RX_D_20 : out std_logic;
CH0_FF_RX_D_21 : out std_logic;
CH1_FF_RX_D_21 : out std_logic;
CH0_FF_RX_D_22 : out std_logic;
CH1_FF_RX_D_22 : out std_logic;
CH0_FF_RX_D_23 : out std_logic;
CH1_FF_RX_D_23 : out std_logic;
CH0_FFS_PCIE_DONE : out std_logic;
CH1_FFS_PCIE_DONE : out std_logic;
CH0_FFS_PCIE_CON : out std_logic;
CH1_FFS_PCIE_CON : out std_logic;
CH0_FFS_RLOS : out std_logic;
CH1_FFS_RLOS : out std_logic;
CH0_FFS_LS_SYNC_STATUS : out std_logic;
CH1_FFS_LS_SYNC_STATUS : out std_logic;
CH0_FFS_CC_UNDERRUN : out std_logic;
CH1_FFS_CC_UNDERRUN : out std_logic;
CH0_FFS_CC_OVERRUN : out std_logic;
CH1_FFS_CC_OVERRUN : out std_logic;
CH0_FFS_RXFBFIFO_ERROR : out std_logic;
CH1_FFS_RXFBFIFO_ERROR : out std_logic;
CH0_FFS_TXFBFIFO_ERROR : out std_logic;
CH1_FFS_TXFBFIFO_ERROR : out std_logic;
CH0_FFS_RLOL : out std_logic;
CH1_FFS_RLOL : out std_logic;
CH0_FFS_SKP_ADDED : out std_logic;
CH1_FFS_SKP_ADDED : out std_logic;
CH0_FFS_SKP_DELETED : out std_logic;
CH1_FFS_SKP_DELETED : out std_logic;
CH0_LDR_RX2CORE : out std_logic;
CH1_LDR_RX2CORE : out std_logic;
D_SCIRDATA0 : out std_logic;
D_SCIRDATA1 : out std_logic;
D_SCIRDATA2 : out std_logic;
D_SCIRDATA3 : out std_logic;
D_SCIRDATA4 : out std_logic;
D_SCIRDATA5 : out std_logic;
D_SCIRDATA6 : out std_logic;
D_SCIRDATA7 : out std_logic;
D_SCIINT : out std_logic;
D_SCAN_OUT_0 : out std_logic;
D_SCAN_OUT_1 : out std_logic;
D_SCAN_OUT_2 : out std_logic;
D_SCAN_OUT_3 : out std_logic;
D_SCAN_OUT_4 : out std_logic;
D_SCAN_OUT_5 : out std_logic;
D_SCAN_OUT_6 : out std_logic;
D_SCAN_OUT_7 : out std_logic;
D_COUT0 : out std_logic;
D_COUT1 : out std_logic;
D_COUT2 : out std_logic;
D_COUT3 : out std_logic;
D_COUT4 : out std_logic;
D_COUT5 : out std_logic;
D_COUT6 : out std_logic;
D_COUT7 : out std_logic;
D_COUT8 : out std_logic;
D_COUT9 : out std_logic;
D_COUT10 : out std_logic;
D_COUT11 : out std_logic;
D_COUT12 : out std_logic;
D_COUT13 : out std_logic;
D_COUT14 : out std_logic;
D_COUT15 : out std_logic;
D_COUT16 : out std_logic;
D_COUT17 : out std_logic;
D_COUT18 : out std_logic;
D_COUT19 : out std_logic;
D_REFCLKI : in std_logic;
D_FFS_PLOL : out std_logic );
end component;
end package;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/library/wrapper/ 0000775 0000000 0000000 00000000000 14502055570 0022760 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/library/wrapper/README 0000664 0000000 0000000 00000000212 14502055570 0023633 0 ustar 00root root 0000000 0000000 This directory should leave - in future.
It contains hand woven Verilog wrappers for non resolving entities or
primitives with generics.
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/library/wrapper/bram.v 0000664 0000000 0000000 00000001461 14502055570 0024072 0 ustar 00root root 0000000 0000000 // Workaround BRAM implementation for fifo buffer
// 2020
module bram_2psync #(
parameter DATA = 8,
parameter ADDR = 6
) (
// Port A
input wire clk,
input wire a_we,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_write,
output reg [DATA-1:0] a_read,
// Port B
input wire b_we,
input wire [ADDR-1:0] b_addr,
input wire [DATA-1:0] b_write,
output reg [DATA-1:0] b_read
);
// Shared memory
reg [DATA-1:0] mem [(2**ADDR)-1:0];
reg [ADDR-1:0] addr_b;
reg [ADDR-1:0] addr_a;
assign a_read = mem[addr_a];
// assign b_read = mem[addr_b];
always @(posedge clk) begin: DUAL_RAW_PORT_A_PROC
addr_a <= a_addr;
end
always @(posedge clk) begin: DUAL_RAW_PORT_B_PROC
addr_b <= b_addr;
if (b_we) begin
mem[b_addr] <= b_write;
end
end
endmodule
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/library/wrapper/primitives.v 0000664 0000000 0000000 00000000252 14502055570 0025341 0 ustar 00root root 0000000 0000000 `timescale 1 ns / 1 ps
module VHI ( Z );
output Z ;
supply1 VDD;
buf (Z , VDD);
endmodule
module VLO ( Z );
output Z;
supply0 VSS;
buf (Z , VSS);
endmodule
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/library/wrapper/wrapper.v 0000664 0000000 0000000 00000004060 14502055570 0024627 0 ustar 00root root 0000000 0000000 // Wrapper for specific instantiation of EHXPLLL
//
// This is a workaround until we can automatically pass generics to
// instanced vendor primitives (black boxes)
//
module ehxplll_4_5_6_30_15_10_5_29_14_9_0_0_0_0_0_0_0_200_df43956727cb406e91ea03c3249c0f9d5327137e(clki, clkfb, phasesel1, phasesel0, phasedir, phasestep, phaseloadreg, stdby,
pllwakesync, rst, enclkop, enclkos, enclkos2, enclkos3,
clkop, clkos, clkos2, clkos3, lock, intlock,
refclk, clkintfb );
input clki, clkfb, phasesel1, phasesel0, phasedir, phasestep;
input phaseloadreg, stdby, pllwakesync, rst;
input enclkop, enclkos, enclkos2, enclkos3;
output clkop, clkos, clkos2, clkos3, lock, intlock, refclk;
output clkintfb;
wire clkop_int;
EHXPLLL #(
.PLLRST_ENA("DISABLED"),
.INTFB_WAKE("DISABLED"),
.STDBY_ENABLE("DISABLED"),
.DPHASE_SOURCE("DISABLED"),
.OUTDIVIDER_MUXA("DIVA"),
.OUTDIVIDER_MUXB("DIVB"),
.OUTDIVIDER_MUXC("DIVC"),
.OUTDIVIDER_MUXD("DIVD"),
.CLKI_DIV(4),
.CLKOP_ENABLE("ENABLED"),
.CLKOP_DIV(6),
.CLKOP_CPHASE(5),
.CLKOP_FPHASE(0),
// .CLKOP_TRIM_DELAY(0),
.CLKOP_TRIM_POL("FALLING"),
.CLKOS_ENABLE("ENABLED"),
.CLKOS_DIV(30),
.CLKOS_CPHASE(29),
.CLKOS_FPHASE(0),
// .CLKOS_TRIM_DELAY(0),
.CLKOS_TRIM_POL("FALLING"),
.CLKOS2_ENABLE("ENABLED"),
.CLKOS2_DIV(15),
.CLKOS2_CPHASE(14),
.CLKOS2_FPHASE(0),
.CLKOS3_ENABLE("ENABLED"),
.CLKOS3_DIV(10),
.CLKOS3_CPHASE(9),
.CLKOS3_FPHASE(0),
.FEEDBK_PATH("CLKOP"),
.CLKFB_DIV(5)
) pll_i (
.RST(1'b0),
.STDBY(1'b0),
.CLKI(clki),
.CLKOP(clkop_int),
.CLKOS(clkos),
.CLKFB(clkop_int),
.CLKINTFB(),
.PHASESEL0(1'b0),
.PHASESEL1(1'b0),
.PHASEDIR(1'b1),
.PHASESTEP(1'b1),
.PHASELOADREG(1'b1),
.PLLWAKESYNC(1'b0),
.ENCLKOP(1'b0),
.LOCK(lock)
);
assign clkop = clkop_int;
endmodule
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/openocd/ 0000775 0000000 0000000 00000000000 14502055570 0021263 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/openocd/LFE5U-25F.cfg 0000664 0000000 0000000 00000000066 14502055570 0023120 0 ustar 00root root 0000000 0000000 jtag newtap ecp5 tap -irlen 8 -expected-id 0x41111043
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/openocd/LFE5U-45F.cfg 0000664 0000000 0000000 00000000066 14502055570 0023122 0 ustar 00root root 0000000 0000000 jtag newtap ecp5 tap -irlen 8 -expected-id 0x41112043
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/openocd/LFE5U-85F.cfg 0000664 0000000 0000000 00000000066 14502055570 0023126 0 ustar 00root root 0000000 0000000 jtag newtap ecp5 tap -irlen 8 -expected-id 0x41113043
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/openocd/LFE5UM-25F.cfg 0000664 0000000 0000000 00000000066 14502055570 0023235 0 ustar 00root root 0000000 0000000 jtag newtap ecp5 tap -irlen 8 -expected-id 0x01111043
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/openocd/LFE5UM-45F.cfg 0000664 0000000 0000000 00000000066 14502055570 0023237 0 ustar 00root root 0000000 0000000 jtag newtap ecp5 tap -irlen 8 -expected-id 0x01112043
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/openocd/LFE5UM-85F.cfg 0000664 0000000 0000000 00000000066 14502055570 0023243 0 ustar 00root root 0000000 0000000 jtag newtap ecp5 tap -irlen 8 -expected-id 0x01113043
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/openocd/LFE5UM5G-25F.cfg 0000664 0000000 0000000 00000000066 14502055570 0023431 0 ustar 00root root 0000000 0000000 jtag newtap ecp5 tap -irlen 8 -expected-id 0x81111043
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/openocd/LFE5UM5G-45F.cfg 0000664 0000000 0000000 00000000066 14502055570 0023433 0 ustar 00root root 0000000 0000000 jtag newtap ecp5 tap -irlen 8 -expected-id 0x81112043
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/openocd/LFE5UM5G-85F.cfg 0000664 0000000 0000000 00000000066 14502055570 0023437 0 ustar 00root root 0000000 0000000 jtag newtap ecp5 tap -irlen 8 -expected-id 0x81113043
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/openocd/ecp5-evn.cfg 0000664 0000000 0000000 00000000461 14502055570 0023367 0 ustar 00root root 0000000 0000000 # this supports ECP5 Evaluation Board
interface ftdi
ftdi_device_desc "Lattice ECP5 Evaluation Board"
ftdi_vid_pid 0x0403 0x6010
# channel 1 does not have any functionality
ftdi_channel 0
# just TCK TDI TDO TMS, no reset
ftdi_layout_init 0xfff8 0xfffb
reset_config none
# default speed
adapter_khz 5000
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/openocd/ecp5-versa.cfg 0000664 0000000 0000000 00000000463 14502055570 0023721 0 ustar 00root root 0000000 0000000 # this supports ECP5 Evaluation Board
interface ftdi
# ftdi_device_desc "Lattice ECP5 Evaluation Board"
ftdi_vid_pid 0x0403 0x6010
# channel 1 does not have any functionality
ftdi_channel 0
# just TCK TDI TDO TMS, no reset
ftdi_layout_init 0xfff8 0xfffb
reset_config none
# default speed
adapter_khz 5000
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/openocd/olimex-arm-usb-tiny-h.cfg 0000664 0000000 0000000 00000000552 14502055570 0026015 0 ustar 00root root 0000000 0000000 #
# Olimex ARM-USB-TINY-H
#
# http://www.olimex.com/dev/arm-usb-tiny-h.html
#
interface ftdi
ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
ftdi_vid_pid 0x15ba 0x002a
ftdi_layout_init 0x0808 0x0a1b
ftdi_layout_signal nSRST -oe 0x0200
ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
ftdi_layout_signal LED -data 0x0800
# default speed
adapter_khz 5000
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/src/ 0000775 0000000 0000000 00000000000 14502055570 0020423 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/src/Makefile.inc 0000664 0000000 0000000 00000000037 14502055570 0022633 0 ustar 00root root 0000000 0000000
OBJS += frontends/ghdl/ghdl.o
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/src/ghdl.cc 0000664 0000000 0000000 00000112372 14502055570 0021656 0 ustar 00root root 0000000 0000000 /*
Copyright (C) 2016 Tristan Gingold
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see .
*/
#include "kernel/yosys.h"
#include "kernel/sigtools.h"
#include "kernel/log.h"
#include
#include
#include
USING_YOSYS_NAMESPACE
#ifdef YOSYS_ENABLE_GHDL
#include "ghdl/synth.h"
using namespace GhdlSynth;
static Name_Id nameid_gclk = {0};
// Convert an Sname_User to a string. Deals with extended names
// Subroutine of to_str
static std::string user_to_str(Name_Id id)
{
const char *s = get_cstr(id);
if (s[0] != '\\')
return string(s);
// Extended name
// Case it can be converted to a name without the
// escape sequence.
int len = 1;
while (1) {
char c = s[len];
if (c == 0)
break;
if (c == '\\' && s[len + 1] == 0 && len > 1)
break;
if (!((c >= 'a' && c <= 'z')
|| (c >= 'A' && c <= 'Z')
|| (c >= '0' && c <= '9')
|| (c == '_' || c == '.')))
// Unexpected character, return the name as is.
return string(s);
len++;
}
return string(s + 1, len - 1);
}
// Convert an Sname to a string.
static std::string to_str(Sname name)
{
std::string res;
bool is_sys = false;
log_assert(is_valid(name));
for (Sname pfx = name; is_valid(pfx); pfx = get_sname_prefix(pfx)) {
switch (get_sname_kind(pfx)) {
case Sname_Artificial:
is_sys = true;
// fallthrough
case Sname_User:
res = '.' + user_to_str(get_sname_suffix(pfx)) + res;
break;
case Sname_Version:
// Use ':' for versions. '%' is not supported by Xilinx ISE edif2ngc.
// ('$' is boring with tcl scripts)
res = ':' + stringf("%u", get_sname_version(pfx)) + res;
break;
}
}
res[0] = is_sys ? '$' : '\\';
return res;
}
// Get the corresponding wire for net N (or null if not found).
static Wire *get_wire(std::vector &net_map, Net n)
{
log_assert(n.id != 0);
// Search if N is the output of a cell.
Wire *res = n.id < net_map.size() ? net_map.at(n.id) : nullptr;
return res;
}
// Convert bit I of V to State.
static RTLIL::State logic32_to_state(struct logic_32 v, unsigned int i)
{
i &= 31;
switch((((v.va >> i)) & 1) + ((v.zx >> i) & 1)*2)
{
case 0:
return RTLIL::State::S0;
case 1:
return RTLIL::State::S1;
case 2:
return RTLIL::State::Sz;
case 3:
default:
return RTLIL::State::Sx;
}
}
// Convert V to a Const.
static RTLIL::Const pval_to_const(Pval v)
{
const unsigned wd = get_pval_length(v);
std::vector bits(wd);
struct logic_32 val;
for (unsigned i = 0; i < wd; i++) {
if (i % 32 == 0)
val = read_pval(v, i / 32);
bits[i] = logic32_to_state(val, i);
}
return RTLIL::Const(bits);
}
static RTLIL::SigSpec get_src(std::vector &net_map, Net n);
static RTLIL::SigSpec get_src_extract(std::vector &net_map, Net n, unsigned off, unsigned wd);
// Concatenate the NBR_IN inputs of INST (ie handle Id_ConcatX).
static RTLIL::SigSpec get_src_concat(std::vector &net_map, Instance inst, unsigned nbr_in)
{
RTLIL::SigSpec res;
// ConcatN means { I0; I1; .. IN}, but append() adds
// bits to the MSB side.
for (unsigned i = nbr_in; i > 0; i--)
res.append(get_src(net_map, get_input_net(inst, (i - 1))));
return res;
}
// Extract WD bits at OFF from concatenation INST. Do not compute unused bits.
static RTLIL::SigSpec get_src_concat_extract(std::vector &net_map, Instance inst, unsigned nbr_in, unsigned off, unsigned wd)
{
RTLIL::SigSpec res;
// ConcatN means { I0; I1; .. IN}, but append() adds
// bits to the MSB side.
for (unsigned i = nbr_in; i > 0; i--) {
Net p = get_input_net(inst, (i - 1));
unsigned pw = get_width(p);
if (off < pw) {
unsigned sub_wd = (off + wd < pw ? wd : pw - off);
res.append(get_src_extract(net_map, p, off, sub_wd));
// sub_wd bits have been extracted.
wd -= sub_wd;
if (wd == 0)
break;
off = 0;
}
else {
off -= pw;
}
}
return res;
}
// Extract WD bits at OFF from N. Try to avoid computing unused bits as it may result in an infinite recursion if parts of a concatenation are defined by the concatenation.
static RTLIL::SigSpec get_src_extract(std::vector &net_map, Net n, unsigned off, unsigned wd)
{
Instance inst = get_net_parent(n);
switch(get_id(inst)) {
case Id_Port:
case Id_Output:
return get_src_extract(net_map, get_input_net(inst, 0), off, wd);
case Id_Extract:
log_assert(wd <= get_width(n));
return get_src_extract(net_map, get_input_net(inst, 0), get_param_uns32(inst, 0) + off, wd);
case Id_Concat2:
return get_src_concat_extract(net_map, inst, 2, off, wd);
case Id_Concat3:
return get_src_concat_extract(net_map, inst, 3, off, wd);
case Id_Concat4:
return get_src_concat_extract(net_map, inst, 4, off, wd);
case Id_Concatn:
return get_src_concat_extract(net_map, inst, get_param_uns32(inst, 0), off, wd);
default:
RTLIL::SigSpec res = get_src(net_map, n);
return res.extract(off, wd);
}
}
static RTLIL::SigSpec get_src(std::vector &net_map, Net n)
{
log_assert(n.id != 0);
// Search if N is the output of a cell.
Wire *w = get_wire(net_map, n);
if (w != nullptr)
return w;
Instance inst = get_net_parent(n);
switch(get_id(inst)) {
#define IN(N) get_src(net_map, get_input_net(inst, (N)))
case Id_Port:
case Id_Output:
return IN(0);
case Id_Uextend:
{
RTLIL::SigSpec res = IN(0);
res.extend_u0(get_width(n), false);
return res;
}
case Id_Sextend:
{
RTLIL::SigSpec res = IN(0);
res.extend_u0(get_width(n), true);
return res;
}
case Id_Utrunc:
case Id_Strunc:
{
RTLIL::SigSpec res = IN(0);
return res.extract(0, get_width(n));
}
case Id_Const_Bit: // arbitrary width binary
{
const unsigned wd = get_width(n);
std::vector bits(wd);
unsigned int val = 0;
for (unsigned i = 0; i < wd; i++) {
if (i % 32 == 0)
val = get_param_uns32(inst, i / 32);
bits[i] = (val >> (i%32)) & 1 ? RTLIL::State::S1 : RTLIL::State::S0;
}
return RTLIL::SigSpec(RTLIL::Const(bits));
}
case Id_Const_UB32: // zero padded binary
{
const unsigned wd = get_width(n);
std::vector bits(wd);
unsigned int val = get_param_uns32(inst, 0);
for (unsigned i = 0; i < wd && i < 32; i++) {
bits[i] = (val >> i) & 1 ? RTLIL::State::S1 : RTLIL::State::S0;
}
return RTLIL::SigSpec(RTLIL::Const(bits));
}
case Id_Const_SB32: // sign extended binary
{
const unsigned wd = get_width(n);
std::vector bits(wd);
unsigned int val = get_param_uns32(inst, 0);
for (unsigned i = 0; i < wd; i++) {
unsigned idx = i < 32 ? i : 31;
bits[i] = (val >> idx) & 1 ? RTLIL::State::S1 : RTLIL::State::S0;
}
return RTLIL::SigSpec(RTLIL::Const(bits));
}
case Id_Const_Z:
{
return SigSpec(RTLIL::State::Sz, get_width(n));
}
case Id_Const_X:
{
return SigSpec(RTLIL::State::Sx, get_width(n));
}
case Id_Const_0:
{
return SigSpec(RTLIL::State::S0, get_width(n));
}
case Id_Const_Log: // arbitrary length 01ZX
{
const unsigned wd = get_width(n);
std::vector bits(wd);
struct logic_32 v;
for (unsigned i = 0; i < wd; i++) {
if (i % 32 == 0) {
v.va = get_param_uns32(inst, 2*(i / 32));
v.zx = get_param_uns32(inst, 2*(i / 32) + 1);
}
bits[i] = logic32_to_state(v, i);
}
return RTLIL::SigSpec(RTLIL::Const(bits));
}
case Id_Const_UL32: // zero padded 01ZX
{
const unsigned wd = get_width(n);
std::vector bits(wd);
unsigned int val01 = get_param_uns32(inst, 0);
unsigned int valzx = get_param_uns32(inst, 1);
for (unsigned i = 0; i < wd && i < 32; i++) {
switch(((val01 >> i)&1)+((valzx >> i)&1)*2)
{
case 0:
bits[i] = RTLIL::State::S0;
break;
case 1:
bits[i] = RTLIL::State::S1;
break;
case 2:
bits[i] = RTLIL::State::Sz;
break;
case 3:
bits[i] = RTLIL::State::Sx;
break;
}
}
return RTLIL::SigSpec(RTLIL::Const(bits));
}
case Id_Extract:
return get_src_extract(net_map, get_input_net(inst, 0), get_param_uns32(inst, 0), get_width(n));
case Id_Concat2:
return get_src_concat(net_map, inst, 2);
case Id_Concat3:
return get_src_concat(net_map, inst, 3);
case Id_Concat4:
return get_src_concat(net_map, inst, 4);
case Id_Concatn:
return get_src_concat(net_map, inst, get_param_uns32(inst, 0));
default:
log_cmd_error("wire not found for %s\n", to_str(get_module_name(get_module(inst))).c_str());
break;
}
#undef IN
}
static bool is_set(std::vector &net_map, Net n)
{
// If not in the map, then certainly not present.
if (n.id >= net_map.size())
return false;
Wire *res = net_map[n.id];
return (res != nullptr);
}
static void set_src(std::vector &net_map, Net n, Wire *wire)
{
if (n.id >= net_map.size())
net_map.resize(n.id + 1, nullptr);
log_assert(net_map[n.id] == nullptr);
net_map[n.id] = wire;
}
// Create a value from an attribute
static RTLIL::Const build_attribute_val(Attribute attr)
{
RTLIL::Const cst = pval_to_const(get_attribute_pval(attr));
if (get_attribute_type(attr) == Param_Pval_String)
cst.flags |= RTLIL::CONST_FLAG_STRING;
return cst;
}
// Create the identifier of an attribute
static IdString build_attribute_id(Attribute attr)
{
return IdString('\\' + string(get_cstr(get_attribute_name(attr))));
}
static void add_attributes_chain(RTLIL::AttrObject &obj, Attribute attr)
{
while (attr.id != 0) {
IdString id = build_attribute_id(attr);
obj.attributes[id] = build_attribute_val(attr);
attr = get_attribute_next(attr);
}
}
// Convert attributes of INST to OBJ.
static void add_attributes_from_instance(RTLIL::AttrObject &obj, Instance inst)
{
add_attributes_chain(obj, get_instance_first_attribute (inst));
}
// Extract the polarity from net N (output of an edge gate).
static RTLIL::State extract_clk_pol(Net n)
{
Instance edge = get_net_parent(n);
switch (get_id(edge)) {
case Id_Posedge:
return RTLIL::State::S1;
case Id_Negedge:
return RTLIL::State::S0;
default:
log_cmd_error("clock edge expected\n");
return RTLIL::State::S1;
}
}
// Extract the clock from net N (output of an edge gate).
static RTLIL::SigSpec extract_clk_sig(std::vector &net_map, Net n)
{
Instance edge = get_net_parent(n);
return get_src(net_map, get_input_net(edge, 0));
}
// INST is an Id_Memory or an Id_Memory_Init
// All the inputs have been connected, all the outputs have been pushed.
static void import_memory(RTLIL::Module *module, std::vector &net_map, Instance inst)
{
Net mem_o = get_output(inst, 0);
Input first_port = get_first_sink (mem_o);
std::string mem_str = to_str(get_instance_name(inst));
// Memories appear only once.
log_assert(!is_set(net_map, mem_o));
// Count number of read and write ports.
// Extract width, size, abits.
int nbr_rd = 0;
int nbr_wr = 0;
unsigned width = 0;
unsigned abits = 0;
for (Input port = first_port; ;) {
Instance port_inst = get_input_parent(port);
Net addr;
Net dat;
switch(get_id(port_inst)) {
case Id_Mem_Rd:
case Id_Mem_Rd_Sync:
dat = get_output(port_inst, 1);
addr = get_input_net(port_inst, 1);
nbr_rd++;
break;
case Id_Mem_Wr_Sync:
dat = get_input_net(port_inst, 4);
addr = get_input_net(port_inst, 1);
nbr_wr++;
break;
case Id_Memory:
case Id_Memory_Init:
port.id = 0;
break;
default:
log_assert(0);
}
if (port.id == 0)
break;
if (width == 0) {
width = get_width(dat);
abits = get_width(addr);
} else {
// All the ports must have the same width and abits.
log_assert(width == get_width(dat));
log_assert(abits == get_width(addr));
}
port = get_first_sink(get_output(port_inst, 0));
}
unsigned size = get_width(mem_o) / width;
// Create the memory.
RTLIL::Memory *mem1 = new RTLIL::Memory;
mem1->width = width;
mem1->start_offset = 0;
mem1->size = size;
RTLIL::Memory *mem = module->addMemory(mem_str, mem1);
delete mem1;
// Set attributes.
add_attributes_from_instance(*mem, inst);
// Initial value
if (get_id(inst) == Id_Memory_Init) {
Cell *init = module->addCell(mem_str + "$init", ID($meminit_v2));
init->parameters[ID::MEMID] = Const(mem_str);
init->parameters[ID::ABITS] = Const(abits);
init->parameters[ID::WIDTH] = Const(width);
init->parameters[ID::PRIORITY] = Const(0);
init->parameters[ID::WORDS] = Const(size);
init->setPort(ID::EN, Const(RTLIL::State::S1, width));
init->setPort(ID::ADDR, SigSpec(0, abits));
Net iinp = get_input_net(inst, 1);
Instance iinst = get_net_parent(iinp);
Module_Id imod = get_id(iinst);
if (imod == Id_Signal || imod == Id_Isignal)
iinp = get_input_net(iinst, 0);
init->setPort(ID::DATA, get_src(net_map, iinp));
}
// Ports
// The first port is the output of the memory_init/memory cell.
// It points to the first actor (so the one with the least priority).
std::vector vec;
Net clk_net;
int ridx = -1;
int widx = -1;
for (Input port = first_port; ; ) {
Instance port_inst = get_input_parent(port);
Input next_port = get_first_sink(get_output(port_inst, 0));
Module_Id id = get_id(port_inst);
#define IN(N) get_src(net_map, get_input_net(port_inst, (N)))
#define OUT(N) get_src(net_map, get_output(port_inst, (N)))
Cell *p;
// Create the cell
switch(id) {
case Id_Mem_Rd:
case Id_Mem_Rd_Sync:
p = module->addCell(mem_str + stringf("$r%u", ++ridx),
ID($memrd_v2));
break;
case Id_Mem_Wr_Sync:
p = module->addCell(mem_str + stringf("$w%u", ++widx),
ID($memwr_v2));
break;
case Id_Memory:
case Id_Memory_Init:
// Finished
return;
default:
log_abort();
}
// Common parameters
p->parameters[ID::MEMID] = Const(mem_str);
p->parameters[ID::ABITS] = Const(abits);
p->parameters[ID::WIDTH] = Const(width);
// Common ports
p->setPort(ID::ADDR, IN(1));
// Common to memrd ports
switch(id) {
case Id_Mem_Rd:
case Id_Mem_Rd_Sync:
p->setPort(ID::DATA, OUT(1));
p->setPort(ID::ARST, Const(RTLIL::State::S0));
p->setPort(ID::SRST, Const(RTLIL::State::S0));
p->parameters[ID::ARST_VALUE] = Const(RTLIL::State::Sx, width);
p->parameters[ID::SRST_VALUE] = Const(RTLIL::State::Sx, width);
p->parameters[ID::INIT_VALUE] = Const(RTLIL::State::Sx, width);
p->parameters[ID::CE_OVER_SRST] = Const(RTLIL::State::S1);
// The read port is transparent to the emitted write ports.
vec.resize(nbr_wr);
for (int j = 0; j < nbr_wr; j++)
vec[j] = j <= widx ? RTLIL::State::S1 : RTLIL::State::S0;
p->parameters[ID::TRANSPARENCY_MASK] = Const(vec);
for (int j = 0; j < nbr_wr; j++)
vec[j] = RTLIL::State::S0;
p->parameters[ID::COLLISION_X_MASK] = Const(vec);
break;
case Id_Mem_Wr_Sync:
p->setPort(ID::DATA, IN(4));
p->parameters[ID::PORTID] = Const(widx);
vec.resize(nbr_wr);
// Emitted write ports (ie j <= widx) don't have priority.
for (int j = 0; j < nbr_wr; j++)
vec[j] = j < widx ? RTLIL::State::S1 : RTLIL::State::S0;
p->parameters[ID::PRIORITY_MASK] = Const(vec);
break;
default:
log_abort();
}
// Clocks
switch(id) {
case Id_Mem_Rd:
p->parameters[ID::CLK_ENABLE] = Const(RTLIL::State::S0);
p->parameters[ID::CLK_POLARITY] = Const(RTLIL::State::S1);
p->setPort(ID::CLK, Const(RTLIL::State::S0));
p->setPort(ID::EN, Const(RTLIL::State::S1));
break;
case Id_Mem_Rd_Sync:
case Id_Mem_Wr_Sync:
p->parameters[ID::CLK_ENABLE] = Const(RTLIL::State::S1);
clk_net = get_input_net(port_inst, 2);
p->parameters[ID::CLK_POLARITY] = extract_clk_pol(clk_net);
p->setPort(ID::CLK, extract_clk_sig(net_map, clk_net));
p->setPort(ID::EN, SigSpec(SigBit(IN(3)), width));
break;
default:
log_abort();
}
// EN
switch(id) {
case Id_Mem_Rd:
p->setPort(ID::EN, Const(RTLIL::State::S1));
break;
case Id_Mem_Rd_Sync:
p->setPort(ID::EN, IN(3));
break;
case Id_Mem_Wr_Sync:
p->setPort(ID::EN, SigSpec(SigBit(IN(3)), width));
break;
default:
log_abort();
}
port = next_port;
}
#undef IN
#undef OUT
}
static void add_formal_input(RTLIL::Module *module, std::vector &net_map, Instance inst, const char *cellname)
{
RTLIL::Cell *cell = module->addCell(to_str(get_instance_name(inst)), cellname);
Net n = get_output(inst, 0);
cell->setParam(ID::WIDTH, get_width(n));
cell->setPort(ID::Y, get_src(net_map, n));
}
static bool has_attribute_gclk(Net n)
{
Instance inst = get_net_parent(n);
switch(get_id(inst)) {
case Id_Signal:
case Id_Isignal:
break;
default:
return false;
}
Attribute attr = get_instance_first_attribute (inst);
while (attr.id != 0) {
if (get_attribute_name(attr).id == nameid_gclk.id)
return true;
attr = get_attribute_next(attr);
}
return false;
}
static void import_module(RTLIL::Design *design, GhdlSynth::Module m)
{
Instance self_inst = get_self_instance (m);
std::string module_name = to_str(get_module_name(m));
if (design->has(module_name)) {
if (is_valid(self_inst)) {
// Error message only for non-black-boxes.
log_cmd_error("Re-definition of module `%s'.\n", module_name.c_str());
}
return;
}
RTLIL::Module *module = new RTLIL::Module;
module->name = module_name;
design->add(module);
log("Importing module %s.\n", RTLIL::id2cstr(module->name));
// TODO: support submodules (currently they aren't generated)
if (is_valid(get_first_sub_module(m))) {
log_cmd_error("Unsupported: submodules in `%s'.\n", module_name.c_str());
return;
}
// List of all memories.
std::vector memories;
if (!is_valid(self_inst)) { // blackbox
module->set_bool_attribute(ID::blackbox);
Port_Idx nbr_inputs = get_nbr_inputs(m);
for (Port_Idx idx = 0; idx < nbr_inputs; idx++) {
RTLIL::Wire *wire = module->addWire(
to_str(get_input_name(m, idx)),
get_input_width(m, idx));
wire->port_input = true;
add_attributes_chain(*wire, get_input_port_first_attribute(m, idx));
}
Port_Idx nbr_outputs = get_nbr_outputs(m);
for (Port_Idx idx = 0; idx < nbr_outputs; idx++) {
RTLIL::Wire *wire = module->addWire(
to_str(get_output_name(m, idx)),
get_output_width(m, idx));
if (get_inout_flag(m, idx))
wire->port_input = true;
wire->port_output = true;
add_attributes_chain(*wire, get_output_port_first_attribute(m, idx));
}
Param_Idx nbr_params = get_nbr_params(m);
for (Param_Idx idx = 0; idx < nbr_params; idx++) {
module->avail_parameters(to_str(get_param_name(m, idx)));
}
module->fixup_ports();
return;
}
// Create input ports.
std::vector net_map;
Port_Idx nbr_inputs = get_nbr_inputs(m);
for (Port_Idx idx = 0; idx < nbr_inputs; idx++) {
// They correspond to ouputs of the self instance.
Net port = get_output(self_inst, idx);
RTLIL::Wire *wire = module->addWire(to_str(get_input_name(m, idx)));
wire->port_id = idx + 1;
wire->port_input = true;
wire->width = get_width(port);
set_src(net_map, port, wire);
add_attributes_chain(*wire, get_input_port_first_attribute(m, idx));
}
// Create inout ports, so that they can be read.
Port_Idx nbr_outputs = get_nbr_outputs(m);
for (Port_Idx idx = 0; idx < nbr_outputs; idx++) {
if (!get_inout_flag(m, idx))
continue;
// They correspond to inputs of the self instance.
Net output_out = get_input_net(self_inst, idx);
// Create wire
RTLIL::Wire *wire = module->addWire(to_str(get_output_name(m, idx)));
wire->port_id = nbr_inputs + idx + 1;
wire->port_output = true;
wire->port_input = true;
wire->width = get_width(output_out);
add_attributes_chain(*wire, get_output_port_first_attribute(m, idx));
Instance inout_inst = get_net_parent(output_out);
Net inout_rd = get_output(inout_inst, 0);
set_src(net_map, inout_rd, wire);
}
// Create wires for outputs of (real) cells.
for (Instance inst = get_first_instance(m);
is_valid(inst);
inst = get_next_instance(inst)) {
GhdlSynth::Module im = get_module(inst);
Module_Id id = get_id(im);
switch (id) {
case Id_And:
case Id_Or:
case Id_Xor:
case Id_Nand:
case Id_Nor:
case Id_Xnor:
case Id_Add:
case Id_Sub:
case Id_Neg:
case Id_Mux2:
case Id_Mux4:
case Id_Pmux:
case Id_Dff:
case Id_Idff:
case Id_Adff:
case Id_Iadff:
case Id_Dlatch:
case Id_Eq:
case Id_Ne:
case Id_Ult:
case Id_Ule:
case Id_Ugt:
case Id_Uge:
case Id_Slt:
case Id_Sle:
case Id_Sgt:
case Id_Sge:
case Id_Not:
case Id_Abs:
case Id_Red_Or:
case Id_Red_And:
case Id_Red_Xor:
case Id_Lsr:
case Id_Lsl:
case Id_Asr:
case Id_Smin:
case Id_Umin:
case Id_Smax:
case Id_Umax:
case Id_Smul:
case Id_Umul:
case Id_Sdiv:
case Id_Udiv:
case Id_Srem:
case Id_Smod:
case Id_Umod:
case Id_Allconst:
case Id_Allseq:
case Id_Anyconst:
case Id_Anyseq:
case Id_Mem_Rd:
case Id_Mem_Rd_Sync:
case Id_Tri:
case Id_Resolver:
case Id_User_None:
case Id_User_Parameters:
for (Port_Idx idx = 0; idx < get_nbr_outputs(im); idx++) {
Net o = get_output(inst, idx);
// The wire may have been created for a module output
if (is_set(net_map, o))
continue;
RTLIL::Wire *wire =
module->addWire(NEW_ID, get_width(o));
set_src(net_map, o, wire);
}
break;
case Id_Signal:
case Id_Isignal: {
Net s = get_output(inst, 0);
// The wire may have been created for a module output
if (is_set(net_map, s))
break;
Sname iname = get_instance_name(inst);
RTLIL::Wire *wire =
module->addWire(to_str(iname), get_width(s));
set_src(net_map, s, wire);
// Attributes
add_attributes_from_instance(*wire, inst);
break;
}
case Id_Output:
case Id_Inout:
case Id_Iinout:
// The wire was created when the port was.
break;
case Id_Assert:
case Id_Assume:
case Id_Cover:
case Id_Assert_Cover:
// No output
break;
case Id_Memory:
case Id_Memory_Init:
case Id_Mem_Wr_Sync:
// Handled by import_memory.
break;
case Id_Port:
case Id_Const_UB32:
case Id_Const_SB32:
case Id_Const_UL32:
case Id_Const_Bit:
case Id_Const_Log:
case Id_Const_Z:
case Id_Const_X:
case Id_Const_0:
case Id_Uextend:
case Id_Sextend:
case Id_Utrunc:
case Id_Strunc:
case Id_Extract:
case Id_Concat2:
case Id_Concat3:
case Id_Concat4:
case Id_Concatn:
// Skip: these won't create cells.
break;
case Id_Posedge:
case Id_Negedge:
// The cell is ignored.
break;
default:
log_cmd_error("Unsupported(1): instance %s of %s.\n",
to_str(get_instance_name(inst)).c_str(),
to_str(get_module_name(get_module(inst))).c_str());
return;
}
}
// Create cells and connect.
for (Instance inst = get_first_instance(m);
is_valid(inst);
inst = get_next_instance(inst)) {
Module_Id id = get_id(inst);
Sname iname = get_instance_name(inst);
switch (id) {
#define IN(N) get_src(net_map, get_input_net(inst, (N)))
#define OUT(N) get_src(net_map, get_output(inst, (N)))
case Id_And:
module->addAnd(to_str(iname), IN(0), IN(1), OUT(0));
break;
case Id_Or:
module->addOr(to_str(iname), IN(0), IN(1), OUT(0));
break;
case Id_Xor:
module->addXor(to_str(iname), IN(0), IN(1), OUT(0));
break;
case Id_Nand:
{
SigSpec r = OUT(0);
RTLIL::Wire *w = module->addWire(NEW_ID, r.size());
module->addAnd(NEW_ID, IN(0), IN(1), w);
module->addNot(to_str(iname), w, r);
}
break;
case Id_Nor:
{
SigSpec r = OUT(0);
RTLIL::Wire *w = module->addWire(NEW_ID, r.size());
module->addOr(NEW_ID, IN(0), IN(1), w);
module->addNot(to_str(iname), w, r);
}
break;
case Id_Xnor:
module->addXnor(to_str(iname), IN(0), IN(1), OUT(0));
break;
case Id_Add:
module->addAdd(to_str(iname), IN(0), IN(1), OUT(0));
break;
case Id_Sub:
module->addSub(to_str(iname), IN(0), IN(1), OUT(0));
break;
case Id_Neg:
module->addNeg(to_str(iname), IN(0), OUT(0), true);
break;
case Id_Not:
module->addNot(to_str(iname), IN(0), OUT(0));
break;
case Id_Abs:
{
SigSpec isNegative = IN(0).extract(IN(0).size() - 1, 1);
RTLIL::Wire *negated = module->addWire(NEW_ID, IN(0).size());
module->addNeg(NEW_ID, IN(0), negated);
module->addMux(NEW_ID, IN(0), negated, isNegative, OUT(0));
}
break;
case Id_Eq:
module->addEq(to_str(iname), IN(0), IN(1), OUT(0));
break;
case Id_Ne:
module->addNe(to_str(iname), IN(0), IN(1), OUT(0));
break;
case Id_Ult:
module->addLt(to_str(iname), IN(0), IN(1), OUT(0));
break;
case Id_Ule:
module->addLe(to_str(iname), IN(0), IN(1), OUT(0));
break;
case Id_Ugt:
module->addGt(to_str(iname), IN(0), IN(1), OUT(0));
break;
case Id_Uge:
module->addGe(to_str(iname), IN(0), IN(1), OUT(0));
break;
case Id_Slt:
module->addLt(to_str(iname), IN(0), IN(1), OUT(0), true);
break;
case Id_Sle:
module->addLe(to_str(iname), IN(0), IN(1), OUT(0), true);
break;
case Id_Sgt:
module->addGt(to_str(iname), IN(0), IN(1), OUT(0), true);
break;
case Id_Sge:
module->addGe(to_str(iname), IN(0), IN(1), OUT(0), true);
break;
case Id_Red_Or:
module->addReduceOr(to_str(iname), IN(0), OUT(0));
break;
case Id_Red_And:
module->addReduceAnd(to_str(iname), IN(0), OUT(0));
break;
case Id_Red_Xor:
module->addReduceXor(to_str(iname), IN(0), OUT(0));
break;
case Id_Lsl:
module->addShl(to_str(iname), IN(0), IN(1), OUT(0));
break;
case Id_Lsr:
module->addShr(to_str(iname), IN(0), IN(1), OUT(0));
break;
case Id_Asr:
module->addSshr(to_str(iname), IN(0), IN(1), OUT(0), true);
break;
case Id_Smin:
case Id_Umin:
case Id_Smax:
case Id_Umax:
{
bool is_signed = (id == Id_Smin || id == Id_Smax);
RTLIL::Wire *select_rhs = module->addWire(NEW_ID);
if (id == Id_Smin || id == Id_Umin) {
module->addGt(NEW_ID, IN(0), IN(1), select_rhs, is_signed);
} else {
module->addLt(NEW_ID, IN(0), IN(1), select_rhs, is_signed);
}
module->addMux(to_str(iname), IN(0), IN(1), select_rhs, OUT(0));
}
break;
case Id_Smul:
module->addMul(to_str(iname), IN(0), IN(1), OUT(0), true);
break;
case Id_Umul:
module->addMul(to_str(iname), IN(0), IN(1), OUT(0), false);
break;
case Id_Sdiv:
module->addDiv(to_str(iname), IN(0), IN(1), OUT(0), true);
break;
case Id_Udiv:
module->addDiv(to_str(iname), IN(0), IN(1), OUT(0), false);
break;
case Id_Srem:
// Id_Urem would be the same as Id_Umod, so only the latter exists
// $mod: modulo of truncating division, "rem" in VHDL
module->addMod(to_str(iname), IN(0), IN(1), OUT(0), true);
break;
case Id_Smod:
case Id_Umod:
// $modfloor: modulo of flooring division, "mod" in VHDL
module->addModFloor(to_str(iname), IN(0), IN(1), OUT(0), id == Id_Smod);
break;
case Id_Mux2:
module->addMux(to_str(iname), IN(1), IN(2), IN(0), OUT(0));
break;
case Id_Mux4:
{
SigSpec Sel0 = IN(0).extract(0, 1);
SigSpec Sel1 = IN(0).extract(1, 1);
SigSpec in1 = IN(1);
RTLIL::Wire *w0 = module->addWire(NEW_ID, in1.size());
RTLIL::Wire *w1 = module->addWire(NEW_ID, in1.size());
module->addMux(NEW_ID, in1, IN (2), Sel0, w0);
module->addMux(NEW_ID, IN (3), IN (4), Sel0, w1);
module->addMux(NEW_ID, w0, w1, Sel1, OUT (0));
}
break;
case Id_Pmux:
{
RTLIL::SigSpec b;
RTLIL::SigSpec s = IN(0);
for (int i = 0; i < s.size(); i++)
b.append(IN(2 + i));
module->addPmux(to_str(iname), IN(1), b, s, OUT(0));
}
break;
case Id_Dff:
case Id_Idff:
{
Net edge_clk = get_input_net(inst, 0);
Net clk = get_input_net(get_net_parent(edge_clk), 0);
RTLIL::SigSpec sig_clk = get_src(net_map, clk);
if (has_attribute_gclk(clk))
module->addFf(to_str(iname), IN(1), OUT(0));
else
module->addDff(to_str(iname), sig_clk, IN(1), OUT(0), extract_clk_pol(edge_clk) == RTLIL::State::S1);
// For idff, the initial value is set on the output wire.
if (id == Id_Idff) {
net_map[get_output(inst, 0).id]->attributes[ID::init] = IN(2).as_const();
}
}
break;
case Id_Adff:
case Id_Iadff:
{
Net clk = get_input_net(inst, 0);
SigSpec rval = IN(3);
SigSpec clk_sig = extract_clk_sig(net_map, clk);
bool clk_pol = extract_clk_pol(clk) == RTLIL::State::S1;
SigSpec arst = IN(2);
SigSpec d = IN(1);
SigSpec q = OUT(0);
// If the reset value (rval) is a constant, use a classic asynchronous dff.
if (rval.is_fully_const())
module->addAdff(to_str(iname), clk_sig, arst, d, q, rval.as_const(), clk_pol);
else {
// Otherwise, use a dffsr.
// set <= arst ? d : 0
SigSpec zero = SigSpec(RTLIL::State::S0, d.size());
RTLIL::Wire *set = module->addWire(NEW_ID, d.size());
module->addMux(NEW_ID, zero, d, arst, set);
// clr <= arst ? ~d : 0
RTLIL::Wire *d_n = module->addWire(NEW_ID, d.size());
module->addNot(NEW_ID, d, d_n);
RTLIL::Wire *clr = module->addWire(NEW_ID, d.size());
module->addMux(NEW_ID, zero, d_n, arst, clr);
// Use dffsr
module->addDffsr(to_str(iname), clk_sig, set, clr, d, q, clk_pol);
}
// For iadff, the initial value is set on the output
// wire.
if (id == Id_Iadff) {
net_map[get_output(inst, 0).id]->attributes[ID::init] = IN(4).as_const();
}
}
break;
case Id_Dlatch:
module->addDlatch(to_str(iname), IN(1), IN(0), OUT(0));
break;
case Id_User_None:
case Id_User_Parameters:
{
RTLIL::Cell *cell = module->addCell(
to_str(iname),
to_str(get_module_name(get_module(inst))));
GhdlSynth::Module submod = get_module(inst);
Port_Idx nbr_inputs = get_nbr_inputs(submod);
for (Port_Idx idx = 0; idx < nbr_inputs; idx++) {
cell->setPort(to_str(get_input_name(submod, idx)), IN(idx));
}
Port_Idx nbr_outputs = get_nbr_outputs(submod);
for (Port_Idx idx = 0; idx < nbr_outputs; idx++) {
cell->setPort(to_str(get_output_name(submod, idx)), OUT(idx));
}
if (id == Id_User_Parameters) {
Param_Idx nbr_params = get_nbr_params(submod);
for (Param_Idx idx = 0; idx < nbr_params; idx++) {
RTLIL::Const cst = pval_to_const(get_param_pval(inst, idx));
if (get_param_type(submod, idx) == Param_Pval_String)
cst.flags |= RTLIL::CONST_FLAG_STRING;
cell->setParam(to_str(get_param_name(submod, idx)), cst);
}
}
}
break;
case Id_Signal:
case Id_Isignal:
module->connect(OUT (0), IN (0));
break;
case Id_Output:
case Id_Port:
module->connect(OUT (0), IN (0));
break;
case Id_Inout:
case Id_Iinout:
// Virtual gate.
// Connect input to output.
module->connect(OUT(0), IN(0));
break;
case Id_Assert:
module->addAssert(to_str(iname), IN(0), State::S1);
break;
case Id_Assume:
module->addAssume(to_str(iname), IN(0), State::S1);
break;
case Id_Cover:
case Id_Assert_Cover:
module->addCover(to_str(iname), IN(0), State::S1);
break;
case Id_Allconst:
add_formal_input(module, net_map, inst, "$allconst");
break;
case Id_Allseq:
add_formal_input(module, net_map, inst, "$allseq");
break;
case Id_Anyconst:
add_formal_input(module, net_map, inst, "$anyconst");
break;
case Id_Anyseq:
add_formal_input(module, net_map, inst, "$anyseq");
break;
case Id_Tri:
module->addTribuf(to_str(iname), IN(1), IN(0), OUT(0));
break;
case Id_Resolver:
module->connect(OUT(0), IN(0));
module->connect(OUT(0), IN(1));
break;
case Id_Memory:
case Id_Memory_Init:
// Will be handled later.
memories.push_back(inst);
break;
case Id_Mem_Rd:
case Id_Mem_Rd_Sync:
case Id_Mem_Wr_Sync:
break;
case Id_Const_UB32:
case Id_Const_SB32:
case Id_Const_UL32:
case Id_Const_Bit:
case Id_Const_Log:
case Id_Const_Z:
case Id_Const_X:
case Id_Const_0:
case Id_Uextend:
case Id_Sextend:
case Id_Utrunc:
case Id_Strunc:
case Id_Extract:
case Id_Concat2:
case Id_Concat3:
case Id_Concat4:
case Id_Concatn:
case Id_Posedge:
case Id_Negedge:
break;
#undef IN
#undef OUT
default:
log_cmd_error("Unsupported(2): instance %s of %s.\n",
to_str(get_instance_name(inst)).c_str(),
to_str(get_module_name(get_module(inst))).c_str());
return;
}
}
for (auto i : memories) {
import_memory(module, net_map, i);
}
// Create output ports
for (Port_Idx idx = 0; idx < nbr_outputs; idx++) {
if (get_inout_flag(m, idx))
continue;
Net output_out = get_input_net(self_inst, idx);
// Create wire
RTLIL::Wire *wire = module->addWire(to_str(get_output_name(m, idx)));
wire->port_id = nbr_inputs + idx + 1;
wire->port_output = true;
wire->width = get_width(output_out);
add_attributes_chain(*wire, get_output_port_first_attribute(m, idx));
module->connect(wire, get_src(net_map, output_out));
Instance inst = get_net_parent(output_out);
switch(get_id(inst)) {
case Id_Output:
add_attributes_from_instance(*wire, inst);
break;
default:
break;
}
}
module->fixup_ports();
}
static void import_netlist(RTLIL::Design *design, GhdlSynth::Module top)
{
for (GhdlSynth::Module m = get_first_sub_module (top);
is_valid(m);
m = get_next_sub_module (m)) {
// Do not try to synthesize predefined gates.
if (get_id (m) < Id_User_None)
continue;
import_module(design, m);
}
}
#endif /* YOSYS_ENABLE_GHDL */
YOSYS_NAMESPACE_BEGIN
struct GhdlPass : public Pass {
GhdlPass() : Pass("ghdl", "load VHDL designs using GHDL") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
#if 0
log("\n");
log(" ghdl -a [OPTIONS] ..\n");
log("\n");
log("Analyze the specified VHDL files.\n");
log("\n");
#endif
log("\n");
log(" ghdl [options] unit [arch]\n");
log("\n");
log("Elaborate the already analyzed unit design and import it\n");
log("\n");
log(" ghdl [options] files... -e [unit]\n");
log("\n");
log("Analyse files, elaborate unit and import it\n");
log("If unit is not specified, it is automatically found\n");
log("\n");
log("Full list of options are described in ghdl documentation.\n");
log("\n");
log(" --std=(93|08)\n");
log(" set the vhdl standard.\n");
log("\n");
log(" -C\n");
log(" allow UTF-8 in comments.\n");
log("\n");
log(" --ieee=synopsys\n");
log(" allow use of ieee.std_logic_arith.\n");
log("\n");
log(" -fpsl\n");
log(" parse PSL in comments.\n");
log("\n");
log(" --top-name=hash\n");
log(" use hash to encode the top entity name\n");
}
#ifdef YOSYS_ENABLE_GHDL
virtual void execute(std::vector args, RTLIL::Design *design)
{
static bool lib_initialized;
static unsigned work_initialized;
log_header(design, "Executing GHDL.\n");
// Initialize the library.
if (!lib_initialized) {
lib_initialized = 1;
libghdl_init ();
ghdlsynth__init_for_ghdl_synth();
}
if (args.size() == 2 && args[1] == "--disp-config") {
ghdlcomp__disp_config();
log("yosys plugin compiled on " __DATE__ " " __TIME__
#ifdef GHDL_VER_HASH
", git hash:" GHDL_VER_HASH
#endif
"\n");
}
else {
int cmd_argc = args.size() - 1;
const char **cmd_argv = new const char *[cmd_argc];
for (int i = 0; i < cmd_argc; i++)
cmd_argv[i] = args[i + 1].c_str();
GhdlSynth::Module top;
top = ghdl_synth(!work_initialized, cmd_argc, cmd_argv);
work_initialized++;
if (!is_valid(top)) {
log_cmd_error("vhdl import failed.\n");
}
// For the gclk attribute.
nameid_gclk = get_identifier("gclk");
import_netlist(design, top);
}
}
#else /* YOSYS_ENABLE_GHDL */
virtual void execute(std::vector, RTLIL::Design *) {
log_cmd_error("This version of Yosys is built without GHDL support.\n");
}
#endif
} GhdlPass;
YOSYS_NAMESPACE_END
// vim: ts=8:sw=8:noet
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ 0000775 0000000 0000000 00000000000 14502055570 0021665 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/examples/ 0000775 0000000 0000000 00000000000 14502055570 0023503 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/examples/00version/ 0000775 0000000 0000000 00000000000 14502055570 0025330 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/examples/00version/testsuite.sh 0000775 0000000 0000000 00000000131 14502055570 0027713 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
run_yosys -p "ghdl --disp-config"
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/examples/blackbox/ 0000775 0000000 0000000 00000000000 14502055570 0025270 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/examples/blackbox/blackbox1.vhdl 0000664 0000000 0000000 00000000534 14502055570 0030017 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity blackbox1 is
port (a, b : std_logic;
o : out std_logic);
end blackbox1;
architecture behav of blackbox1 is
component my_blackbox is
port (a, b : std_logic;
o : out std_logic);
end component;
begin
inst: my_blackbox
port map (a => a, b => b, o => o);
end behav;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/examples/blackbox/blackbox2.vhdl 0000664 0000000 0000000 00000000532 14502055570 0030016 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity blackbox2 is
port (a, b : std_logic;
o : out std_logic);
end;
architecture behav of blackbox2 is
component my_blackbox is
port (a, b : std_logic;
\OUT\ : out std_logic);
end component;
begin
inst: my_blackbox
port map (a => a, b => b, \OUT\ => o);
end behav;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/examples/blackbox/blackbox3.vhdl 0000664 0000000 0000000 00000000546 14502055570 0030024 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity blackbox3 is
port (a, b : std_logic;
o : out std_logic);
end;
architecture behav of blackbox3 is
component \lib__cell__box2.3\ is
port (a, b : std_logic;
\O\ : out std_logic);
end component;
begin
inst: \lib__cell__box2.3\
port map (a => a, b => b, \O\ => o);
end behav;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/examples/blackbox/testsuite.sh 0000775 0000000 0000000 00000000621 14502055570 0027657 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
run_yosys -q -p "ghdl blackbox1.vhdl -e; write_verilog blackbox1.v"
fgrep -q "my_blackbox" blackbox1.v
run_yosys -q -p "ghdl blackbox2.vhdl -e; write_verilog blackbox2.v"
fgrep -q ".OUT(" blackbox2.v
run_yosys -q -p "ghdl blackbox3.vhdl -e; write_verilog blackbox3.v"
fgrep -q "\lib__cell__box2.3 " blackbox3.v
fgrep -q ".O(" blackbox3.v
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/examples/dff/ 0000775 0000000 0000000 00000000000 14502055570 0024242 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/examples/dff/adff.vhdl 0000664 0000000 0000000 00000000612 14502055570 0026020 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity adff is
port(
clk : in std_logic;
rst : in std_logic;
d : in std_logic;
q : out std_logic
);
end entity;
architecture arch of adff is
begin
process (clk, rst)
begin
if rst = '1' then
q <= '1';
elsif rising_edge(clk) then
q <= d;
end if;
end process;
end architecture;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/examples/dff/dff.vhdl 0000664 0000000 0000000 00000000430 14502055570 0025655 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity dff is
port(
clk : in std_logic;
d : in std_logic;
q : out std_logic
);
end entity;
architecture arch of dff is
begin
process (clk)
begin
if rising_edge(clk) then
q <= d;
end if;
end process;
end architecture;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/examples/dff/negadff.vhdl 0000664 0000000 0000000 00000000621 14502055570 0026512 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity negadff is
port(
clk : in std_logic;
rst : in std_logic;
d : in std_logic;
q : out std_logic
);
end entity;
architecture arch of negadff is
begin
process (clk, rst)
begin
if rst = '1' then
q <= '0';
elsif falling_edge(clk) then
q <= d;
end if;
end process;
end architecture;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/examples/dff/negdff.vhdl 0000664 0000000 0000000 00000000437 14502055570 0026356 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity negdff is
port(
clk : in std_logic;
d : in std_logic;
q : out std_logic
);
end entity;
architecture arch of negdff is
begin
process (clk)
begin
if falling_edge(clk) then
q <= d;
end if;
end process;
end architecture;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/examples/dff/testsuite.sh 0000775 0000000 0000000 00000001525 14502055570 0026635 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
run_yosys -q -p "ghdl negdff.vhdl -e; write_ilang negdff.ilang"
fgrep -q "cell \$dff" negdff.ilang
fgrep -q "CLK_POLARITY 0" negdff.ilang
fgrep -q "WIDTH 1" negdff.ilang
run_yosys -q -p "ghdl dff.vhdl -e; write_ilang dff.ilang"
fgrep -q "CLK_POLARITY 1" dff.ilang
fgrep -q "WIDTH 1" dff.ilang
run_yosys -q -p "ghdl adff.vhdl -e; opt; write_ilang adff.ilang"
fgrep -q 'cell $adff' adff.ilang
fgrep -q 'ARST_POLARITY 1' adff.ilang
fgrep -q "ARST_VALUE 1'1" adff.ilang
fgrep -q 'CLK_POLARITY 1' adff.ilang
fgrep -q 'WIDTH 1' adff.ilang
run_yosys -q -p "ghdl negadff.vhdl -e; write_ilang negadff.ilang"
fgrep -q 'cell $adff' negadff.ilang
fgrep -q 'ARST_POLARITY 1' negadff.ilang
fgrep -q "ARST_VALUE 1'0" negadff.ilang
fgrep -q 'CLK_POLARITY 0' negadff.ilang
fgrep -q 'WIDTH 1' negadff.ilang
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/examples/test-ecp5_versa/ 0000775 0000000 0000000 00000000000 14502055570 0026514 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/examples/test-ecp5_versa/testsuite.sh 0000775 0000000 0000000 00000001111 14502055570 0031076 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
top=../../..
src=$top/examples/ecp5_versa
VHDL_SYN_FILES="$src/versa_ecp5_top.vhdl \
$src/pll_mac.vhd \
$src/soc_iomap_pkg.vhdl \
$src/uart.vhdl \
$src/uart_tx.vhdl \
$src/uart_rx.vhdl \
$src/fifobuf.vhdl"
VERILOG_FILES="\
$top/library/wrapper/primitives.v \
$top/library/wrapper/bram.v
"
FREQ=25000000
run_yosys -p "ghdl -gCLK_FREQUENCY=$FREQ --work=ecp5um $top/library/ecp5u/components.vhdl --work=work $VHDL_SYN_FILES -e; read_verilog $VERILOG_FILES; synth_ecp5 -top versa_ecp5_top -json top_ecp5_top.json" -l report.txt -q
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/examples/test-ice40hx8k/ 0000775 0000000 0000000 00000000000 14502055570 0026167 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/examples/test-ice40hx8k/testsuite.sh 0000775 0000000 0000000 00000000274 14502055570 0030562 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
src=../../../examples/ice40hx8k
synth_ice40 $src/leds.vhdl $src/spin1.vhdl -e leds
synth_ice40 $src/leds.vhdl $src/spin2.vhdl -e leds
clean
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/examples/test-icestick/ 0000775 0000000 0000000 00000000000 14502055570 0026256 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/examples/test-icestick/testsuite.sh 0000775 0000000 0000000 00000000564 14502055570 0030653 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
src=../../../examples/icestick
# spin2
LEDS_SRC=$src/leds
for f in fixed1 blink multi1 multi2 spin1 rotate1 rotate2 rotate3 rotate4; do
synth_ice40 $LEDS_SRC/leds.vhdl $LEDS_SRC/${f}.vhdl -e leds
done
UART_SRC=$src/uart/hdl
synth_ice40 $UART_SRC/uart_rx.vhd $UART_SRC/uart_tx.vhd $UART_SRC/uart_top.vhd -e uart_top
clean
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/examples/test-icezum/ 0000775 0000000 0000000 00000000000 14502055570 0025754 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/examples/test-icezum/testsuite.sh 0000775 0000000 0000000 00000000367 14502055570 0030352 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
src=../../../examples/icezum
synth_ice40 $src/led_on.vhdl -e led_on
synth_ice40 $src/blink.vhdl -e blink
synth_ice40 $src/pushbutton.vhdl -e pushbutton
synth_ice40 $src/counter.vhdl -e counter
clean
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/formal/ 0000775 0000000 0000000 00000000000 14502055570 0023145 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/formal/gates/ 0000775 0000000 0000000 00000000000 14502055570 0024250 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/formal/gates/test_abs.sby 0000664 0000000 0000000 00000000203 14502055570 0026566 0 ustar 00root root 0000000 0000000 [options]
#depth 6
mode prove
[engines]
smtbmc z3
[script]
ghdl --std=08 test_abs.vhd -e ent
prep -top ent
[files]
test_abs.vhd
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/formal/gates/test_abs.vhd 0000664 0000000 0000000 00000001175 14502055570 0026563 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
port (
clk : in std_logic;
a : in signed(7 downto 0);
b : out signed(7 downto 0)
);
end;
architecture a of ent is
begin
process(clk)
begin
if rising_edge(clk) then
b <= abs a;
end if;
end process;
formal: block
signal last_a : signed(7 downto 0);
signal has_run : std_logic := '0';
begin
process(clk)
begin
if rising_edge(clk) then
has_run <= '1';
last_a <= a;
end if;
end process;
default clock is rising_edge(clk);
assert always has_run -> b >= 0 or (last_a = x"80" and last_a = b);
end block;
end;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/formal/gates/test_asr.sby 0000664 0000000 0000000 00000000215 14502055570 0026611 0 ustar 00root root 0000000 0000000 [options]
depth 20
mode prove
[engines]
smtbmc z3
[script]
ghdl --std=08 test_asr.vhd -e test_asr
prep -top test_asr
[files]
test_asr.vhd
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/formal/gates/test_asr.vhd 0000664 0000000 0000000 00000004444 14502055570 0026605 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test_asr is
port (
-- globals
reset : in std_logic;
clk : in std_logic;
-- inputs
sig : in signed(7 downto 0);
-- outputs
asr : out signed(7 downto 0)
);
end entity test_asr;
architecture rtl of test_asr is
signal index : natural;
begin
process (clk) is
begin
if rising_edge(clk) then
if reset = '1' then
index <= 0;
asr <= x"00";
else
asr <= shift_right(sig, index);
if index < natural'high then
index <= index + 1;
end if;
end if;
end if;
end process;
Formal : block is
signal sig_d : signed(7 downto 0);
signal sig_d_7 : signed(7 downto 0);
begin
default clock is rising_edge(clk);
restrict {reset[*1]; not reset[+]}[*1];
-- Register inputs
-- Workaround for missing prev() PSL function
process (clk) is
begin
if rising_edge(clk) then
sig_d <= sig;
end if;
end process;
-- helper signal for sign extension
sig_d_7 <= (others => sig_d(7));
assert reset -> next asr = "00000000";
-- Workaround for missing IIR_PREDEFINED_IEEE_NUMERIC_STD_EQ_SGN_INT
-- Comparing with hex literals like x"00" in PSL code generates an error:
-- no declaration for ""
shift_aright_0 : assert always not reset and index = 0 -> next asr = sig_d;
shift_aright_1 : assert always not reset and index = 1 -> next asr = sig_d_7(7) & sig_d(7 downto 1);
shift_aright_2 : assert always not reset and index = 2 -> next asr = sig_d_7(7 downto 6) & sig_d(7 downto 2);
shift_aright_3 : assert always not reset and index = 3 -> next asr = sig_d_7(7 downto 5) & sig_d(7 downto 3);
shift_aright_4 : assert always not reset and index = 4 -> next asr = sig_d_7(7 downto 4) & sig_d(7 downto 4);
shift_aright_5 : assert always not reset and index = 5 -> next asr = sig_d_7(7 downto 3) & sig_d(7 downto 5);
shift_aright_6 : assert always not reset and index = 6 -> next asr = sig_d_7(7 downto 2) & sig_d(7 downto 6);
shift_aright_7 : assert always not reset and index = 7 -> next asr = sig_d_7(7 downto 1) & sig_d(7);
shift_aright_8 : assert always not reset and index >= 8 -> next asr = sig_d_7;
end block Formal;
end architecture rtl;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/formal/gates/test_lsl.sby 0000664 0000000 0000000 00000000215 14502055570 0026616 0 ustar 00root root 0000000 0000000 [options]
depth 20
mode prove
[engines]
smtbmc z3
[script]
ghdl --std=08 test_lsl.vhd -e test_lsl
prep -top test_lsl
[files]
test_lsl.vhd
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/formal/gates/test_lsl.vhd 0000664 0000000 0000000 00000006337 14502055570 0026615 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test_lsl is
port (
-- globals
reset : in std_logic;
clk : in std_logic;
-- inputs
unsig : in unsigned(7 downto 0);
sig : in signed(7 downto 0);
-- outputs
lslu : out unsigned(7 downto 0);
lsls : out signed(7 downto 0)
);
end entity test_lsl;
architecture rtl of test_lsl is
signal index : natural;
begin
process (clk) is
begin
if rising_edge(clk) then
if reset = '1' then
index <= 0;
lslu <= x"00";
lsls <= x"00";
else
lslu <= shift_left(unsig, index);
lsls <= shift_left(sig, index);
if index < natural'high then
index <= index + 1;
end if;
end if;
end if;
end process;
Formal : block is
signal uns_d : unsigned(7 downto 0);
signal sig_d : signed(7 downto 0);
begin
default clock is rising_edge(clk);
restrict {reset[*1]; not reset[+]}[*1];
-- Register inputs
-- Workaround for missing prev() PSL function
process (clk) is
begin
if rising_edge(clk) then
uns_d <= unsig;
sig_d <= sig;
end if;
end process;
assert reset -> next lslu = 0;
assert reset -> next lsls = "00000000";
-- Workaround for missing IIR_PREDEFINED_IEEE_NUMERIC_STD_EQ_SGN_INT
-- Comparing with hex literals like x"00" in PSL code generates an error:
-- no declaration for ""
shift_left_uns_0 : assert always not reset and index = 0 -> next lslu = uns_d;
shift_left_uns_1 : assert always not reset and index = 1 -> next lslu = uns_d(6 downto 0) & '0';
shift_left_uns_2 : assert always not reset and index = 2 -> next lslu = uns_d(5 downto 0) & "00";
shift_left_uns_3 : assert always not reset and index = 3 -> next lslu = uns_d(4 downto 0) & "000";
shift_left_uns_4 : assert always not reset and index = 4 -> next lslu = uns_d(3 downto 0) & "0000";
shift_left_uns_5 : assert always not reset and index = 5 -> next lslu = uns_d(2 downto 0) & "00000";
shift_left_uns_6 : assert always not reset and index = 6 -> next lslu = uns_d(1 downto 0) & "000000";
shift_left_uns_7 : assert always not reset and index = 7 -> next lslu = uns_d(0) & "0000000";
shift_left_uns_8 : assert always not reset and index >= 8 -> next lslu = 0;
shift_left_sgn_0 : assert always not reset and index = 0 -> next lsls = sig_d;
shift_left_sgn_1 : assert always not reset and index = 1 -> next lsls = sig_d(6 downto 0) & '0';
shift_left_sgn_2 : assert always not reset and index = 2 -> next lsls = sig_d(5 downto 0) & "00";
shift_left_sgn_3 : assert always not reset and index = 3 -> next lsls = sig_d(4 downto 0) & "000";
shift_left_sgn_4 : assert always not reset and index = 4 -> next lsls = sig_d(3 downto 0) & "0000";
shift_left_sgn_5 : assert always not reset and index = 5 -> next lsls = sig_d(2 downto 0) & "00000";
shift_left_sgn_6 : assert always not reset and index = 6 -> next lsls = sig_d(1 downto 0) & "000000";
shift_left_sgn_7 : assert always not reset and index = 7 -> next lsls = sig_d(0) & "0000000";
shift_left_sgn_8 : assert always not reset and index >= 8 -> next lsls = "00000000";
end block Formal;
end architecture rtl;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/formal/gates/test_lsr.sby 0000664 0000000 0000000 00000000215 14502055570 0026624 0 ustar 00root root 0000000 0000000 [options]
depth 20
mode prove
[engines]
smtbmc z3
[script]
ghdl --std=08 test_lsr.vhd -e test_lsr
prep -top test_lsr
[files]
test_lsr.vhd
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/formal/gates/test_lsr.vhd 0000664 0000000 0000000 00000004112 14502055570 0026610 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test_lsr is
port (
-- globals
reset : in std_logic;
clk : in std_logic;
-- inputs
unsig : in unsigned(7 downto 0);
-- outputs
lsr : out unsigned(7 downto 0)
);
end entity test_lsr;
architecture rtl of test_lsr is
signal index : natural;
begin
process (clk) is
begin
if rising_edge(clk) then
if reset = '1' then
index <= 0;
lsr <= x"00";
else
lsr <= shift_right(unsig, index);
if index < natural'high then
index <= index + 1;
end if;
end if;
end if;
end process;
Formal : block is
signal uns_d : unsigned(7 downto 0);
begin
default clock is rising_edge(clk);
restrict {reset[*1]; not reset[+]}[*1];
-- Register inputs
-- Workaround for missing prev() PSL function
process (clk) is
begin
if rising_edge(clk) then
uns_d <= unsig;
end if;
end process;
assert reset -> next lsr = 0;
-- Workaround for missing IIR_PREDEFINED_IEEE_NUMERIC_STD_EQ_SGN_INT
-- Comparing with hex literals like x"00" in PSL code generates an error:
-- no declaration for ""
shift_right_0 : assert always not reset and index = 0 -> next lsr = uns_d;
shift_right_1 : assert always not reset and index = 1 -> next lsr = '0' & uns_d(7 downto 1);
shift_right_2 : assert always not reset and index = 2 -> next lsr = "00" & uns_d(7 downto 2);
shift_right_3 : assert always not reset and index = 3 -> next lsr = "000" & uns_d(7 downto 3);
shift_right_4 : assert always not reset and index = 4 -> next lsr = "0000" & uns_d(7 downto 4);
shift_right_5 : assert always not reset and index = 5 -> next lsr = "00000" & uns_d(7 downto 5);
shift_right_6 : assert always not reset and index = 6 -> next lsr = "000000" & uns_d(7 downto 6);
shift_right_7 : assert always not reset and index = 7 -> next lsr = "0000000" & uns_d(7);
shift_right_8 : assert always not reset and index >= 8 -> next lsr = 0;
end block Formal;
end architecture rtl;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/formal/gates/test_minmax.sby 0000664 0000000 0000000 00000000200 14502055570 0027307 0 ustar 00root root 0000000 0000000 [options]
mode prove
[engines]
smtbmc z3
[script]
ghdl --std=08 test_minmax.vhd -e ent
prep -top ent
[files]
test_minmax.vhd
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/formal/gates/test_minmax.vhd 0000664 0000000 0000000 00000002757 14502055570 0027316 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
port (
clk : in std_logic;
a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
min_sgn : out signed(7 downto 0);
max_sgn : out signed(7 downto 0);
min_uns : out unsigned(7 downto 0);
max_uns : out unsigned(7 downto 0)
);
end;
architecture a of ent is
begin
process(clk)
begin
if rising_edge(clk) then
min_sgn <= minimum(signed(a), signed(b));
max_sgn <= maximum(signed(a), signed(b));
min_uns <= minimum(unsigned(a), unsigned(b));
max_uns <= maximum(unsigned(a), unsigned(b));
end if;
end process;
formal: block
signal prev_a : std_logic_vector(7 downto 0);
signal prev_b : std_logic_vector(7 downto 0);
signal has_run : std_logic := '0';
begin
process(clk)
begin
if rising_edge(clk) then
has_run <= '1';
prev_a <= a;
prev_b <= b;
end if;
end process;
default clock is rising_edge(clk);
assert eventually! has_run;
assert always has_run and signed(prev_a) <= signed(prev_b) ->
min_sgn = signed(prev_a) and max_sgn = signed(prev_b);
assert always has_run and signed(prev_a) >= signed(prev_b) ->
min_sgn = signed(prev_b) and max_sgn = signed(prev_a);
assert always has_run and unsigned(prev_a) <= unsigned(prev_b) ->
min_uns = unsigned(prev_a) and max_uns = unsigned(prev_b);
assert always has_run and unsigned(prev_a) >= unsigned(prev_b) ->
min_uns = unsigned(prev_b) and max_uns = unsigned(prev_a);
end block;
end;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/formal/gates/test_mod_rem.sby 0000664 0000000 0000000 00000000212 14502055570 0027443 0 ustar 00root root 0000000 0000000 [options]
mode prove
depth 3
[engines]
smtbmc z3
[script]
ghdl --std=08 test_mod_rem.vhd -e ent
prep -top ent
[files]
test_mod_rem.vhd
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/formal/gates/test_mod_rem.vhd 0000664 0000000 0000000 00000005135 14502055570 0027440 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
port (
clk : in std_logic;
a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
rem_sgn : out signed(7 downto 0);
mod_sgn : out signed(7 downto 0);
rem_uns : out unsigned(7 downto 0);
mod_uns : out unsigned(7 downto 0)
);
end;
architecture a of ent is
begin
process(clk)
begin
if rising_edge(clk) then
rem_sgn <= signed(a) rem signed(b);
mod_sgn <= signed(a) mod signed(b);
rem_uns <= unsigned(a) rem unsigned(b);
mod_uns <= unsigned(a) mod unsigned(b);
end if;
end process;
formal: block
signal prev_a : std_logic_vector(7 downto 0);
signal prev_b : std_logic_vector(7 downto 0);
signal has_run : std_logic := '0';
function same_sign(x, y : signed) return boolean is
begin
return x = 0 or y = 0 or (x > 0) = (y > 0);
end function;
function longer(x : signed) return signed is
begin
return resize(x, x'length+1);
end function;
-- artificial flooring integer division, constructed from native
-- truncating integer division operator (/)
function floordiv(x, y : signed) return signed is
begin
-- same signs on inputs will give positive result - rounded in same
-- direction as truncating division
if same_sign(x, y) then
return x / y;
-- otherwise, increase the absolute value of x by abs(y)-1
elsif x < 0 then
-- x is negative, y is positive
return (x - (y - 1)) / y;
else
-- x is positive, y is negative
return (x - (y + 1)) / y;
end if;
end function;
begin
process(clk)
begin
if rising_edge(clk) then
has_run <= '1';
prev_a <= a;
prev_b <= b;
end if;
end process;
default clock is rising_edge(clk);
mod_sgn_sign: assert always has_run -> same_sign(signed(prev_b), mod_sgn);
mod_sgn_correct: assert always has_run ->
floordiv(
longer(signed(prev_a)),
longer(signed(prev_b))
)
* signed(prev_b)
+ mod_sgn = signed(prev_a);
rem_sgn_sign: assert always has_run -> same_sign(signed(prev_a), rem_sgn);
rem_sgn_correct: assert always has_run ->
longer(signed(prev_a)) / longer(signed(prev_b))
* signed(prev_b)
+ rem_sgn = signed(prev_a);
-- calculating modulo from remainder
assert always has_run ->
(rem_sgn = 0 and mod_sgn = rem_sgn) or
(same_sign(signed(prev_a), signed(prev_b)) and mod_sgn = rem_sgn) or
mod_sgn = rem_sgn + signed(prev_b);
uns_mod_correct: assert always has_run ->
unsigned(prev_a) / unsigned(prev_b) * unsigned(prev_b) + mod_uns = unsigned(prev_a);
unsigned_equal: assert always has_run -> mod_uns = rem_uns;
end block;
end;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/formal/gates/test_pmux.sby 0000664 0000000 0000000 00000000174 14502055570 0027021 0 ustar 00root root 0000000 0000000 [options]
mode prove
[engines]
smtbmc z3
[script]
ghdl --std=08 test_pmux.vhd -e ent
prep -top ent
[files]
test_pmux.vhd
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/formal/gates/test_pmux.vhd 0000664 0000000 0000000 00000001471 14502055570 0027006 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
port (
clk : in std_logic;
a : in std_logic_vector(1 downto 0);
b : out std_logic_vector(1 downto 0)
);
end entity;
architecture a of ent is
begin
process(clk)
begin
if rising_edge(clk) then
case a is
when "00" =>
b <= "01";
when "01" =>
b <= "10";
when "11" =>
b <= "00";
when others =>
b <= "11";
end case;
end if;
end process;
formal: block
signal has_run : std_logic := '0';
signal prev_a : std_logic_vector(1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
prev_a <= a;
has_run <= '1';
end if;
end process;
default clock is rising_edge(clk);
assert always has_run -> unsigned(prev_a) + 1 = unsigned(b);
end block;
end architecture;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/formal/gates/testsuite.sh 0000775 0000000 0000000 00000000210 14502055570 0026631 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
for f in abs minmax pmux lsl lsr asr mod_rem; do
formal "test_${f}"
done
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/formal/ram/ 0000775 0000000 0000000 00000000000 14502055570 0023724 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/formal/ram/testsuite.sh 0000775 0000000 0000000 00000000114 14502055570 0026310 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
formal wbr_ram
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/formal/ram/wbr_ram.sby 0000664 0000000 0000000 00000000236 14502055570 0026075 0 ustar 00root root 0000000 0000000 [tasks]
bmc
[options]
bmc: mode bmc
bmc: depth 10
[engines]
smtbmc z3
[script]
ghdl --std=08 wbr_ram.vhd -e wbr_ram
prep -top wbr_ram
[files]
wbr_ram.vhd
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/formal/ram/wbr_ram.vhd 0000664 0000000 0000000 00000001746 14502055570 0026070 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity wbr_ram is
port (
clk_i : in std_logic;
addr_i : in std_logic_vector(7 downto 0);
wr_data_i : in std_logic_vector(15 downto 0);
wr_en_i : in std_logic;
rd_data_o : out std_logic_vector(15 downto 0)
);
end entity wbr_ram;
architecture synthesis of wbr_ram is
type mem_t is array (0 to 255) of std_logic_vector(15 downto 0);
begin
p_write_first : process (clk_i)
variable mem : mem_t := (others => (others => '0'));
begin
if rising_edge(clk_i) then
if wr_en_i = '1' then
mem(to_integer(unsigned(addr_i))) := wr_data_i;
end if;
rd_data_o <= mem(to_integer(unsigned(addr_i)));
end if;
end process p_write_first;
-- All is sensitive to rising edge of clk
default clock is rising_edge(clk_i);
f_wbr : assert always {wr_en_i = '1'} |=> {rd_data_o = prev(wr_data_i)};
end architecture synthesis;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/ 0000775 0000000 0000000 00000000000 14502055570 0024114 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1000/ 0000775 0000000 0000000 00000000000 14502055570 0025545 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1000/test.vhdl 0000664 0000000 0000000 00000002542 14502055570 0027406 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
port(
clk : in std_logic;
read1_reg : in std_ulogic_vector(4 downto 0);
read1_data : out std_ulogic_vector(63 downto 0);
read2_reg : in std_ulogic_vector(4 downto 0);
read2_data : out std_ulogic_vector(63 downto 0);
read3_reg : in std_ulogic_vector(4 downto 0);
read3_data : out std_ulogic_vector(63 downto 0);
write_enable : in std_ulogic;
write_reg : in std_ulogic_vector(4 downto 0);
write_data : in std_ulogic_vector(63 downto 0)
);
end entity test;
architecture behaviour of test is
type regfile is array(0 to 31) of std_ulogic_vector(63 downto 0);
signal registers : regfile;
begin
register_write_0: process(clk)
begin
if rising_edge(clk) then
if write_enable = '1' then
registers(to_integer(unsigned(write_reg))) <= write_data;
end if;
end if;
end process register_write_0;
register_read_0: process(all)
begin
read1_data <= registers(to_integer(unsigned(read1_reg)));
read2_data <= registers(to_integer(unsigned(read2_reg)));
read3_data <= registers(to_integer(unsigned(read3_reg)));
end process register_read_0;
end architecture behaviour;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1000/testsuite.sh 0000775 0000000 0000000 00000000140 14502055570 0030130 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
synth_import --std=08 test.vhdl -e
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1001/ 0000775 0000000 0000000 00000000000 14502055570 0025546 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1001/async.vhdl 0000664 0000000 0000000 00000001456 14502055570 0027550 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity test is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Wen_i : in std_logic;
Addr_i : in natural range 0 to 2**8-1;
Din_i : in std_logic_vector(7 downto 0);
Dout_o : out std_logic_vector(7 downto 0)
);
end entity test;
architecture rtl of test is
type t_register is array(0 to 7) of std_logic_vector(7 downto 0);
signal s_register : t_register;
begin
Dout_o <= s_register(Addr_i);
WriteP : process (Clk_i, Reset_n_i) is
begin
if Reset_n_i = '0' then
s_register <= (others => (others => '0'));
elsif rising_edge(Clk_i) then
if Wen_i = '1' then
s_register(Addr_i) <= Din_i;
end if;
end if;
end process WriteP;
end architecture rtl;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1001/sync.vhdl 0000664 0000000 0000000 00000001503 14502055570 0027400 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity test is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Wen_i : in std_logic;
Addr_i : in natural range 0 to 2**8-1;
Din_i : in std_logic_vector(7 downto 0);
Dout_o : out std_logic_vector(7 downto 0)
);
end entity test;
architecture rtl of test is
type t_register is array(0 to 7) of std_logic_vector(7 downto 0);
signal s_register : t_register;
begin
Dout_o <= s_register(Addr_i);
WriteP : process (Clk_i) is
begin
if rising_edge(Clk_i) then
if Reset_n_i = '0' then
s_register <= (others => (others => '0'));
else
if Wen_i = '1' then
s_register(Addr_i) <= Din_i;
end if;
end if;
end if;
end process WriteP;
end architecture rtl;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1001/testsuite.sh 0000775 0000000 0000000 00000000162 14502055570 0030135 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
synth_import sync.vhdl -e
synth_import async.vhdl -e
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1107/ 0000775 0000000 0000000 00000000000 14502055570 0025555 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1107/testsuite.sh 0000775 0000000 0000000 00000000136 14502055570 0030145 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
synth_import unconnected.vhdl -e
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1107/unconnected.vhdl 0000664 0000000 0000000 00000000352 14502055570 0030741 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity unconnected is
port (
output: out std_logic
);
end entity;
architecture arch of unconnected is
signal no_value: std_logic;
begin
output <= no_value;
end architecture;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1238/ 0000775 0000000 0000000 00000000000 14502055570 0025562 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1238/multiplexers_3.vhdl 0000664 0000000 0000000 00000001150 14502055570 0031415 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity multiplexers_3 is
port (di : in std_logic_vector(7 downto 0);
sel : in std_logic_vector(7 downto 0);
do : out std_logic);
end multiplexers_3;
architecture archi of multiplexers_3 is
begin
do <= di(0) when sel(0)='0' else 'Z';
do <= di(1) when sel(1)='0' else 'Z';
do <= di(2) when sel(2)='0' else 'Z';
do <= di(3) when sel(3)='0' else 'Z';
do <= di(4) when sel(4)='0' else 'Z';
do <= di(5) when sel(5)='0' else 'Z';
do <= di(6) when sel(6)='0' else 'Z';
do <= di(7) when sel(7)='0' else 'Z';
end archi;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1238/testsuite.sh 0000775 0000000 0000000 00000000152 14502055570 0030150 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
synth_import --std=08 multiplexers_3.vhdl -e
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1307/ 0000775 0000000 0000000 00000000000 14502055570 0025557 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1307/NexysVideo.xdc 0000664 0000000 0000000 00000014752 14502055570 0030365 0 ustar 00root root 0000000 0000000 #------------------------------------------------------------------------------------
# HDMI and clock Constraints for the Digilent Nexys Video FPGA development board.
#------------------------------------------------------------------------------------
##Clock Signal
set_property -dict { PACKAGE_PIN R4 IOSTANDARD LVCMOS33 } [get_ports { clk100 }];
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk100]
##HDMI in
create_clock -add -name hdmi_clk -period 6.7 -waveform {0 5} [get_ports hdmi_rx_clk_p]
set_property -dict { PACKAGE_PIN AA5 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L10P_T1_34 Sch=hdmi_rx_cec
set_property -dict { PACKAGE_PIN W4 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_n }]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n
set_property -dict { PACKAGE_PIN V4 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_p }]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p
set_property -dict { PACKAGE_PIN AB12 IOSTANDARD LVCMOS25 } [get_ports { hdmi_rx_hpa }]; #IO_L7N_T1_13 Sch=hdmi_rx_hpa
set_property -dict { PACKAGE_PIN Y4 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L11P_T1_SRCC_34 Sch=hdmi_rx_scl
set_property -dict { PACKAGE_PIN AB5 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L10N_T1_34 Sch=hdmi_rx_sda
set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_txen }]; #IO_L3P_T0_DQS_34 Sch=hdmi_rx_txen
set_property -dict { PACKAGE_PIN AA3 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[0] }]; #IO_L9N_T1_DQS_34 Sch=hdmi_rx_n[0]
set_property -dict { PACKAGE_PIN Y3 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[0] }]; #IO_L9P_T1_DQS_34 Sch=hdmi_rx_p[0]
set_property -dict { PACKAGE_PIN Y2 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[1] }]; #IO_L4N_T0_34 Sch=hdmi_rx_n[1]
set_property -dict { PACKAGE_PIN W2 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[1] }]; #IO_L4P_T0_34 Sch=hdmi_rx_p[1]
set_property -dict { PACKAGE_PIN V2 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[2] }]; #IO_L2N_T0_34 Sch=hdmi_rx_n[2]
set_property -dict { PACKAGE_PIN U2 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[2] }]; #IO_L2P_T0_34 Sch=hdmi_rx_p[2]
##HDMI out
set_property -dict { PACKAGE_PIN AA4 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L11N_T1_SRCC_34 Sch=hdmi_tx_cec
set_property -dict { PACKAGE_PIN U1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_n }]; #IO_L1N_T0_34 Sch=hdmi_tx_clk_n
set_property -dict { PACKAGE_PIN T1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_p }]; #IO_L1P_T0_34 Sch=hdmi_tx_clk_p
set_property -dict { PACKAGE_PIN AB13 IOSTANDARD LVCMOS25 } [get_ports { hdmi_tx_hpd }]; #IO_L3N_T0_DQS_13 Sch=hdmi_tx_hpd
set_property -dict { PACKAGE_PIN U3 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_rscl }]; #IO_L6P_T0_34 Sch=hdmi_tx_rscl
set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_rsda }]; #IO_L6N_T0_VREF_34 Sch=hdmi_tx_rsda
set_property -dict { PACKAGE_PIN Y1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[0] }]; #IO_L5N_T0_34 Sch=hdmi_tx_n[0]
set_property -dict { PACKAGE_PIN W1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[0] }]; #IO_L5P_T0_34 Sch=hdmi_tx_p[0]
set_property -dict { PACKAGE_PIN AB1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[1] }]; #IO_L7N_T1_34 Sch=hdmi_tx_n[1]
set_property -dict { PACKAGE_PIN AA1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[1] }]; #IO_L7P_T1_34 Sch=hdmi_tx_p[1]
set_property -dict { PACKAGE_PIN AB2 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[2] }]; #IO_L8N_T1_34 Sch=hdmi_tx_n[2]
set_property -dict { PACKAGE_PIN AB3 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[2] }]; #IO_L8P_T1_34 Sch=hdmi_tx_p[2]
# DEBUG on JA
set_property -dict { PACKAGE_PIN AB22 IOSTANDARD LVCMOS33 } [get_ports { debug_pmod[0] }]; #IO_L10N_T1_D15_14 Sch=ja[1]
set_property -dict { PACKAGE_PIN AB21 IOSTANDARD LVCMOS33 } [get_ports { debug_pmod[1] }]; #IO_L10P_T1_D14_14 Sch=ja[2]
set_property -dict { PACKAGE_PIN AB20 IOSTANDARD LVCMOS33 } [get_ports { debug_pmod[2] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ja[3]
set_property -dict { PACKAGE_PIN AB18 IOSTANDARD LVCMOS33 } [get_ports { debug_pmod[3] }]; #IO_L17N_T2_A13_D29_14 Sch=ja[4]
set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { debug_pmod[4] }]; #IO_L9P_T1_DQS_14 Sch=ja[7]
set_property -dict { PACKAGE_PIN AA21 IOSTANDARD LVCMOS33 } [get_ports { debug_pmod[5] }]; #IO_L8N_T1_D12_14 Sch=ja[8]
set_property -dict { PACKAGE_PIN AA20 IOSTANDARD LVCMOS33 } [get_ports { debug_pmod[6] }]; #IO_L8P_T1_D11_14 Sch=ja[9]
set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS33 } [get_ports { debug_pmod[7] }]; #IO_L17P_T2_A14_D30_14 Sch=ja[10
##Switches
set_property -dict { PACKAGE_PIN E22 IOSTANDARD LVCMOS25 } [get_ports { sw[0] }]; #IO_L22P_T3_16 Sch=sw[0]
set_property -dict { PACKAGE_PIN F21 IOSTANDARD LVCMOS25 } [get_ports { sw[1] }]; #IO_25_16 Sch=sw[1]
set_property -dict { PACKAGE_PIN G21 IOSTANDARD LVCMOS25 } [get_ports { sw[2] }]; #IO_L24P_T3_16 Sch=sw[2]
set_property -dict { PACKAGE_PIN G22 IOSTANDARD LVCMOS25 } [get_ports { sw[3] }]; #IO_L24N_T3_16 Sch=sw[3]
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS25 } [get_ports { sw[4] }]; #IO_L6P_T0_15 Sch=sw[4]
set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS25 } [get_ports { sw[5] }]; #IO_0_15 Sch=sw[5]
set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS25 } [get_ports { sw[6] }]; #IO_L19P_T3_A22_15 Sch=sw[6]
set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS25 } [get_ports { sw[7] }]; #IO_25_15 Sch=sw[7]
##LEDs
set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS25 } [get_ports { led[0] }]; #IO_L15P_T2_DQS_13 Sch=led[0]
set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS25 } [get_ports { led[1] }]; #IO_L15N_T2_DQS_13 Sch=led[1]
set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS25 } [get_ports { led[2] }]; #IO_L17P_T2_13 Sch=led[2]
set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS25 } [get_ports { led[3] }]; #IO_L17N_T2_13 Sch=led[3]
set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS25 } [get_ports { led[4] }]; #IO_L14N_T2_SRCC_13 Sch=led[4]
set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS25 } [get_ports { led[5] }]; #IO_L16N_T2_13 Sch=led[5]
set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS25 } [get_ports { led[6] }]; #IO_L16P_T2_13 Sch=led[6]
set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS25 } [get_ports { led[7] }]; #IO_L5P_T0_13 Sch=led[7]
##UART
set_property -dict { PACKAGE_PIN AA19 IOSTANDARD LVCMOS33 } [get_ports { rs232_tx }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=uart_rx_out
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1307/conversion_to_RGB.vhd 0000664 0000000 0000000 00000001125 14502055570 0031642 0 ustar 00root root 0000000 0000000 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity conversion_to_RGB is
port ( clk : in std_Logic;
in_V : in std_logic_vector(11 downto 0);
in_W : in std_logic_vector(11 downto 0);
out_G : out std_logic_vector(11 downto 0);
out_R : out std_logic_vector(11 downto 0));
end entity;
architecture Behavioral of conversion_to_RGB is
begin
clk_proc: process(clk)
begin
if rising_edge(clk) then
out_G <= in_V;
out_R <= in_W;
end if;
end process;
end architecture;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1307/hdmi_design.vhd 0000664 0000000 0000000 00000017431 14502055570 0030542 0 ustar 00root root 0000000 0000000 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity hdmi_design is
Port (
clk100 : in STD_LOGIC;
-- Control signals
led : out std_logic_vector(7 downto 0) :=(others => '0');
sw : in std_logic_vector(7 downto 0) :=(others => '0');
debug_pmod : out std_logic_vector(7 downto 0) :=(others => '0');
--HDMI input signals
hdmi_rx_cec : inout std_logic;
hdmi_rx_hpa : out std_logic;
hdmi_rx_scl : in std_logic;
hdmi_rx_sda : inout std_logic;
hdmi_rx_txen : out std_logic;
hdmi_rx_clk_n : in std_logic;
hdmi_rx_clk_p : in std_logic;
hdmi_rx_n : in std_logic_vector(2 downto 0);
hdmi_rx_p : in std_logic_vector(2 downto 0);
--- HDMI out
hdmi_tx_cec : inout std_logic;
hdmi_tx_clk_n : out std_logic;
hdmi_tx_clk_p : out std_logic;
hdmi_tx_hpd : in std_logic;
hdmi_tx_rscl : inout std_logic;
hdmi_tx_rsda : inout std_logic;
hdmi_tx_p : out std_logic_vector(2 downto 0);
hdmi_tx_n : out std_logic_vector(2 downto 0);
-- For dumping symbols
rs232_tx : out std_logic
);
end hdmi_design;
architecture Behavioral of hdmi_design is
component hdmi_io is
Port (
clk100 : in STD_LOGIC;
-------------------------------
-- Control signals
-------------------------------
clock_locked : out std_logic;
data_synced : out std_logic;
debug : out std_logic_vector(7 downto 0);
-------------------------------
--HDMI input signals
-------------------------------
hdmi_rx_cec : inout std_logic;
hdmi_rx_hpa : out std_logic;
hdmi_rx_scl : in std_logic;
hdmi_rx_sda : inout std_logic;
hdmi_rx_txen : out std_logic;
hdmi_rx_clk_n : in std_logic;
hdmi_rx_clk_p : in std_logic;
hdmi_rx_n : in std_logic_vector(2 downto 0);
hdmi_rx_p : in std_logic_vector(2 downto 0);
-------------
-- HDMI out
-------------
hdmi_tx_cec : inout std_logic;
hdmi_tx_clk_n : out std_logic;
hdmi_tx_clk_p : out std_logic;
hdmi_tx_hpd : in std_logic;
hdmi_tx_rscl : inout std_logic;
hdmi_tx_rsda : inout std_logic;
hdmi_tx_p : out std_logic_vector(2 downto 0);
hdmi_tx_n : out std_logic_vector(2 downto 0);
pixel_clk : out std_logic;
-------------------------------
-- VGA data recovered from HDMI
-------------------------------
in_hdmi_detected : out std_logic;
in_blank : out std_logic;
in_hsync : out std_logic;
in_vsync : out std_logic;
in_red : out std_logic_vector(7 downto 0);
in_green : out std_logic_vector(7 downto 0);
in_blue : out std_logic_vector(7 downto 0);
is_interlaced : out std_logic;
is_second_field : out std_logic;
-------------------------------------
-- Audio Levels
-------------------------------------
audio_channel : out std_logic_vector(2 downto 0);
audio_de : out std_logic;
audio_sample : out std_logic_vector(23 downto 0);
-----------------------------------
-- VGA data to be converted to HDMI
-----------------------------------
out_blank : in std_logic;
out_hsync : in std_logic;
out_vsync : in std_logic;
out_red : in std_logic_vector(7 downto 0);
out_green : in std_logic_vector(7 downto 0);
out_blue : in std_logic_vector(7 downto 0);
-----------------------------------
-- For symbol dump or retransmit
-----------------------------------
symbol_sync : out std_logic; -- indicates a fixed reference point in the frame.
symbol_ch0 : out std_logic_vector(9 downto 0);
symbol_ch1 : out std_logic_vector(9 downto 0);
symbol_ch2 : out std_logic_vector(9 downto 0)
);
end component;
signal symbol_sync : std_logic;
signal symbol_ch0 : std_logic_vector(9 downto 0);
signal symbol_ch1 : std_logic_vector(9 downto 0);
signal symbol_ch2 : std_logic_vector(9 downto 0);
signal pixel_clk : std_logic;
signal in_blank : std_logic;
signal in_hsync : std_logic;
signal in_vsync : std_logic;
signal in_red : std_logic_vector(7 downto 0);
signal in_green : std_logic_vector(7 downto 0);
signal in_blue : std_logic_vector(7 downto 0);
signal is_interlaced : std_logic;
signal is_second_field : std_logic;
signal out_blank : std_logic;
signal out_hsync : std_logic;
signal out_vsync : std_logic;
signal out_red : std_logic_vector(7 downto 0);
signal out_green : std_logic_vector(7 downto 0);
signal out_blue : std_logic_vector(7 downto 0);
signal audio_channel : std_logic_vector(2 downto 0);
signal audio_de : std_logic;
signal audio_sample : std_logic_vector(23 downto 0);
signal debug : std_logic_vector(7 downto 0);
begin
-- debug_pmod <= debug;
-- led <= debug;
i_hdmi_io: hdmi_io port map (
clk100 => clk100,
---------------------
-- Control signals
---------------------
clock_locked => open,
data_synced => open,
debug => debug,
---------------------
-- HDMI input signals
---------------------
hdmi_rx_cec => hdmi_rx_cec,
hdmi_rx_hpa => hdmi_rx_hpa,
hdmi_rx_scl => hdmi_rx_scl,
hdmi_rx_sda => hdmi_rx_sda,
hdmi_rx_txen => hdmi_rx_txen,
hdmi_rx_clk_n => hdmi_rx_clk_n,
hdmi_rx_clk_p => hdmi_rx_clk_p,
hdmi_rx_p => hdmi_rx_p,
hdmi_rx_n => hdmi_rx_n,
----------------------
-- HDMI output signals
----------------------
hdmi_tx_cec => hdmi_tx_cec,
hdmi_tx_clk_n => hdmi_tx_clk_n,
hdmi_tx_clk_p => hdmi_tx_clk_p,
hdmi_tx_hpd => hdmi_tx_hpd,
hdmi_tx_rscl => hdmi_tx_rscl,
hdmi_tx_rsda => hdmi_tx_rsda,
hdmi_tx_p => hdmi_tx_p,
hdmi_tx_n => hdmi_tx_n,
pixel_clk => pixel_clk,
-------------------------------
-- VGA data recovered from HDMI
-------------------------------
in_blank => in_blank,
in_hsync => in_hsync,
in_vsync => in_vsync,
in_red => in_red,
in_green => in_green,
in_blue => in_blue,
is_interlaced => is_interlaced,
is_second_field => is_second_field,
-----------------------------------
-- For symbol dump or retransmit
-----------------------------------
audio_channel => audio_channel,
audio_de => audio_de,
audio_sample => audio_sample,
-----------------------------------
-- VGA data to be converted to HDMI
-----------------------------------
out_blank => out_blank,
out_hsync => out_hsync,
out_vsync => out_vsync,
out_red => out_red,
out_green => out_green,
out_blue => out_blue,
symbol_sync => symbol_sync,
symbol_ch0 => symbol_ch0,
symbol_ch1 => symbol_ch1,
symbol_ch2 => symbol_ch2
);
end Behavioral;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1307/hdmi_io.vhd 0000664 0000000 0000000 00000010017 14502055570 0027671 0 ustar 00root root 0000000 0000000 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity hdmi_io is
port (
clk100 : in STD_LOGIC;
-------------------------------
-- Control signals
-------------------------------
clock_locked : out std_logic;
data_synced : out std_logic;
debug : out std_logic_vector(7 downto 0);
-------------------------------
--HDMI input signals
-------------------------------
hdmi_rx_cec : inout std_logic;
hdmi_rx_hpa : out std_logic;
hdmi_rx_scl : in std_logic;
hdmi_rx_sda : inout std_logic;
hdmi_rx_txen : out std_logic;
hdmi_rx_clk_n : in std_logic;
hdmi_rx_clk_p : in std_logic;
hdmi_rx_n : in std_logic_vector(2 downto 0);
hdmi_rx_p : in std_logic_vector(2 downto 0);
-------------
-- HDMI out
-------------
hdmi_tx_cec : inout std_logic;
hdmi_tx_clk_n : out std_logic;
hdmi_tx_clk_p : out std_logic;
hdmi_tx_hpd : in std_logic;
hdmi_tx_rscl : inout std_logic;
hdmi_tx_rsda : inout std_logic;
hdmi_tx_p : out std_logic_vector(2 downto 0);
hdmi_tx_n : out std_logic_vector(2 downto 0);
pixel_clk : out std_logic;
-------------------------------
-- VGA data recovered from HDMI
-------------------------------
in_hdmi_detected : out std_logic;
in_blank : out std_logic;
in_hsync : out std_logic;
in_vsync : out std_logic;
in_red : out std_logic_vector(7 downto 0);
in_green : out std_logic_vector(7 downto 0);
in_blue : out std_logic_vector(7 downto 0);
is_interlaced : out std_logic;
is_second_field : out std_logic;
-----------------------------------
-- VGA data to be converted to HDMI
-----------------------------------
out_blank : in std_logic;
out_hsync : in std_logic;
out_vsync : in std_logic;
out_red : in std_logic_vector(7 downto 0);
out_green : in std_logic_vector(7 downto 0);
out_blue : in std_logic_vector(7 downto 0);
-------------------------------------
-- Audio Levels
-------------------------------------
audio_channel : out std_logic_vector(2 downto 0);
audio_de : out std_logic;
audio_sample : out std_logic_vector(23 downto 0);
-----------------------------------
-- For symbol dump or retransmit
-----------------------------------
symbol_sync : out std_logic; -- indicates a fixed reference point in the frame.
symbol_ch0 : out std_logic_vector(9 downto 0);
symbol_ch1 : out std_logic_vector(9 downto 0);
symbol_ch2 : out std_logic_vector(9 downto 0)
);
end entity;
architecture Behavioral of hdmi_io is
signal fourfourfour_V : std_logic_vector(11 downto 0);
signal fourfourfour_W : std_logic_vector(11 downto 0);
component conversion_to_RGB is
port ( clk : in std_Logic;
in_V : in std_logic_vector(11 downto 0);
in_W : in std_logic_vector(11 downto 0);
out_R : out std_logic_vector(11 downto 0);
out_G : out std_logic_vector(11 downto 0)
);
end component;
signal rgb_R : std_logic_vector(11 downto 0);
signal rgb_G : std_logic_vector(11 downto 0);
begin
i_conversion_to_RGB: conversion_to_RGB
port map (
clk => clk100,
in_V => fourfourfour_V,
in_W => fourfourfour_W,
out_G => rgb_G,
out_R => rgb_R
);
in_green <= rgb_G(11 downto 4);
in_red <= rgb_R(11 downto 4);
end Behavioral;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1307/run_vivado.tcl 0000664 0000000 0000000 00000000317 14502055570 0030440 0 ustar 00root root 0000000 0000000 read_xdc NexysVideo.xdc
read_edif hdmi_design.edif
link_design -part xc7a35tcpg236-1 -top hdmi_design
opt_design
place_design
route_design
report_utilization
report_timing
write_bitstream -force example.bit
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1307/testsuite.sh 0000775 0000000 0000000 00000000261 14502055570 0030146 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
run_yosys -q -p "ghdl hdmi_design.vhd hdmi_io.vhd conversion_to_RGB.vhd -e; synth_xilinx -flatten -edif hdmi_design.edif"
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1309/ 0000775 0000000 0000000 00000000000 14502055570 0025561 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1309/axis_squarer.sby 0000664 0000000 0000000 00000001114 14502055570 0031003 0 ustar 00root root 0000000 0000000 [tasks]
verify_bmc
prove
cover
[options]
verify_bmc: mode bmc
verify_bmc: depth 40
prove: mode prove
prove: depth 20
cover: mode cover
cover: depth 40
[engines]
smtbmc z3 parallel.enable=true
[script]
ghdl axis_squarer.vhd -e axis_squarer
read_verilog -formal faxis_master.v
read_verilog -formal faxis_slave.v
read_verilog -formal tb_formal_top.v
--pycode-begin--
cmd = "hierarchy -top tb_formal_top"
if "cover" in tags:
cmd += " -chparam no_backpressure 1"
output(cmd);
--pycode-end--
prep -top tb_formal_top
[files]
axis_squarer.vhd
faxis_master.v
faxis_slave.v
tb_formal_top.v
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1309/axis_squarer.vhd 0000664 0000000 0000000 00000007573 14502055570 0031006 0 ustar 00root root 0000000 0000000 ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04/08/2020 11:41:37 AM
-- Design Name:
-- Module Name: axis_squarer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity axis_squarer is
Port ( clk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR (31 downto 0);
s_axis_tlast : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR (31 downto 0);
m_axis_tlast : out STD_LOGIC;
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC);
end axis_squarer;
architecture Behavioral of axis_squarer is
signal idle_counter: UNSIGNED(7 downto 0) := (others => '0');
signal counter_start_long: UNSIGNED(3 downto 0) := (others => '0');
type FSM_STATES is (IDLE, TX_RESULT, LONG_COMPUTATION);
signal fsm: FSM_STATES := IDLE;
begin
fsm_main: process(clk) is
begin
if rising_edge(clk) then
if aresetn = '0' then
fsm <= IDLE;
-- Reset stuff added below in response to fv
m_axis_tlast <= '0';
counter_start_long <= (others => '0');
else
case fsm is
when IDLE =>
-- Wait for input valid, then put data onto output bus
if s_axis_tvalid = '1' then
m_axis_tdata <= not s_axis_tdata;
if s_axis_tlast = '1' or counter_start_long = 2 then
m_axis_tlast <= '1';
else
m_axis_tlast <= '0';
end if;
fsm <= TX_RESULT;
end if;
when TX_RESULT =>
-- Wait for output ready
-- Do 8 fast returns before a single slow return
if m_axis_tready = '1' then
m_axis_tlast <= '0';
counter_start_long <= counter_start_long+1;
if counter_start_long = 2 then
fsm <= LONG_COMPUTATION;
counter_start_long <= (others => '0');
else
fsm <= IDLE;
end if;
end if;
when LONG_COMPUTATION =>
-- Wait for 16 cycles
-- In actuality a longer computation goes here but simplify by reducing it to a wait
idle_counter <= idle_counter + 1;
if idle_counter = 5 then
fsm <= IDLE;
end if;
end case;
end if;
end if;
end process;
fsm_axis_handshake_outputs: process(fsm,aresetn) is
begin
case fsm is
when IDLE =>
s_axis_tready <= aresetn; -- Ready when not reset
m_axis_tvalid <= '0';
when TX_RESULT =>
s_axis_tready <= '0';
m_axis_tvalid <= '1';
when LONG_COMPUTATION =>
s_axis_tready <= '0';
m_axis_tvalid <= '0';
end case;
end process;
end Behavioral;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1309/faxis_master.v 0000664 0000000 0000000 00000014541 14502055570 0030442 0 ustar 00root root 0000000 0000000 ////////////////////////////////////////////////////////////////////////////////
//
// Filename: faxis_master.v
//
// Project: WB2AXIPSP: bus bridges and other odds and ends
//
// Purpose: Formal properties for verifying the proper functionality of an
// AXI Stream master.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2019-2020, Gisselquist Technology, LLC
//
// This file is part of the WB2AXIP project.
//
// The WB2AXIP project contains free software and gateware, licensed under the
// Apache License, Version 2.0 (the "License"). You may not use this project,
// or this file, except in compliance with the License. You may obtain a copy
// of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations
// under the License.
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
module faxis_master #(
parameter F_MAX_PACKET = 0,
parameter F_MIN_PACKET = 0,
parameter F_MAX_STALL = 0,
parameter C_S_AXI_DATA_WIDTH = 32,
parameter C_S_AXI_ID_WIDTH = 1,
parameter C_S_AXI_ADDR_WIDTH = 1,
parameter C_S_AXI_USER_WIDTH = 1,
parameter [0:0] OPT_ASYNC_RESET = 1'b0,
//
// F_LGDEPTH is the number of bits necessary to represent a packets
// length
parameter F_LGDEPTH = 32,
//
localparam AW = C_S_AXI_ADDR_WIDTH,
localparam DW = C_S_AXI_DATA_WIDTH,
localparam IDW = C_S_AXI_ID_WIDTH,
localparam UW = C_S_AXI_USER_WIDTH
//
) (
//
input wire i_aclk, i_aresetn,
input wire i_tvalid,
input wire i_tready = 1,
input wire [DW-1:0] i_tdata,
input wire [DW/8-1:0] i_tstrb = {(DW/8){1'b1}},
input wire [DW/8-1:0] i_tkeep = {(DW/8){1'b1}},
input wire i_tlast,
input wire [(IDW>0?IDW:1)-1:0] i_tid = {(IDW){1'b0}},
input wire [(AW>0?AW:1)-1:0] i_tdest = {(AW){1'b0}},
input wire [(UW>0?UW:1)-1:0] i_tuser = {(UW){1'b0}},
//
output reg [F_LGDEPTH-1:0] f_bytecount,
//(* anyconst *) output reg [AW+IDW-1:0] f_routecheck
);
`define SLAVE_ASSUME assert
`define SLAVE_ASSERT assume
localparam F_STALLBITS = (F_MAX_STALL <= 1)
? 1 : $clog2(F_MAX_STALL+2);
reg f_past_valid;
reg [F_LGDEPTH-1:0] f_vbytes;
reg [F_STALLBITS-1:0] f_stall_count;
integer iB;
genvar k;
//
// f_past_valid is used to make certain that temporal assertions
// depending upon past values depend upon *valid* past values.
// It is true for all clocks other than the first clock.
initial f_past_valid = 1'b0;
always @(posedge i_aclk)
f_past_valid <= 1'b1;
//
// Reset should always be active (low) initially
always @(posedge i_aclk)
if (!f_past_valid)
`SLAVE_ASSUME(!i_aresetn);
//
// During and following a reset, TVALID should be deasserted
always @(posedge i_aclk)
if ((!f_past_valid)||(!i_aresetn && OPT_ASYNC_RESET)||($past(!i_aresetn)))
`SLAVE_ASSUME(!i_tvalid);
//
// If TVALID but not TREADY, then the master isn't allowed to change
// anything until the slave asserts TREADY.
always @(posedge i_aclk)
if ((f_past_valid)&&($past(i_aresetn))&&(!OPT_ASYNC_RESET || i_aresetn)
&&($past(i_tvalid))&&(!$past(i_tready)))
begin
`SLAVE_ASSUME(i_tvalid);
`SLAVE_ASSUME($stable(i_tstrb));
`SLAVE_ASSUME($stable(i_tkeep));
`SLAVE_ASSUME($stable(i_tlast));
//`SLAVE_ASSUME($stable(i_tid));
//`SLAVE_ASSUME($stable(i_tdest));
//`SLAVE_ASSUME($stable(i_tuser));
end
generate for(k=0; k 0)
begin : MAX_PACKET
always @(*)
`SLAVE_ASSUME(f_bytecount + f_vbytes <= F_MAX_PACKET);
end endgenerate
//
// F_MIN_PACKET
//
// An optoinal check, forcing a minimum packet length
generate if (F_MIN_PACKET > 0)
begin : MIN_PACKET
always @(*)
if (i_tvalid && i_tlast)
`SLAVE_ASSUME(f_bytecount + f_vbytes >= F_MIN_PACKET);
end endgenerate
//
// F_MAX_STALL
//
// Another optional check, this time insisting that the READY flag can
// only be low for up to F_MAX_STALL clocks.
//
generate if (F_MAX_STALL > 0)
begin : MAX_STALL_CHECK
always @(*)
`SLAVE_ASSERT(f_stall_count < F_MAX_STALL);
end endgenerate
endmodule
`undef SLAVE_ASSUME
`undef SLAVE_ASSERT
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1309/faxis_slave.v 0000664 0000000 0000000 00000014530 14502055570 0030257 0 ustar 00root root 0000000 0000000 ////////////////////////////////////////////////////////////////////////////////
//
// Filename: faxis_slave.v
//
// Project: WB2AXIPSP: bus bridges and other odds and ends
//
// Purpose: Formal properties for verifying the proper functionality of an
// AXI Stream slave.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2019-2020, Gisselquist Technology, LLC
//
// This file is part of the WB2AXIP project.
//
// The WB2AXIP project contains free software and gateware, licensed under the
// Apache License, Version 2.0 (the "License"). You may not use this project,
// or this file, except in compliance with the License. You may obtain a copy
// of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations
// under the License.
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
module faxis_slave #(
parameter F_MAX_PACKET = 0,
parameter F_MIN_PACKET = 0,
parameter F_MAX_STALL = 0,
parameter C_S_AXI_DATA_WIDTH = 32,
parameter C_S_AXI_ID_WIDTH = 1,
parameter C_S_AXI_ADDR_WIDTH = 1,
parameter C_S_AXI_USER_WIDTH = 1,
parameter [0:0] OPT_ASYNC_RESET = 1'b0,
//
// F_LGDEPTH is the number of bits necessary to represent a packets
// length
parameter F_LGDEPTH = 32,
//
localparam AW = C_S_AXI_ADDR_WIDTH,
localparam DW = C_S_AXI_DATA_WIDTH,
localparam IDW = C_S_AXI_ID_WIDTH,
localparam UW = C_S_AXI_USER_WIDTH
//
) (
//
input wire i_aclk, i_aresetn,
input wire i_tvalid,
input wire i_tready = 1,
input wire [DW-1:0] i_tdata,
input wire [DW/8-1:0] i_tstrb = {(DW/8){1'b1}},
input wire [DW/8-1:0] i_tkeep = {(DW/8){1'b1}},
input wire i_tlast,
input wire [(IDW>0?IDW:1)-1:0] i_tid = {(IDW){1'b0}},
input wire [(AW>0?AW:1)-1:0] i_tdest = {(AW){1'b0}},
input wire [(UW>0?UW:1)-1:0] i_tuser = {(UW){1'b0}},
//
output reg [F_LGDEPTH-1:0] f_bytecount,
//(* anyconst *) output reg [AW+IDW-1:0] f_routecheck
);
`define SLAVE_ASSUME assume
`define SLAVE_ASSERT assert
localparam F_STALLBITS = (F_MAX_STALL <= 1)
? 1 : $clog2(F_MAX_STALL+2);
reg f_past_valid;
reg [F_LGDEPTH-1:0] f_vbytes;
reg [F_STALLBITS-1:0] f_stall_count;
integer iB;
genvar k;
//
// f_past_valid is used to make certain that temporal assertions
// depending upon past values depend upon *valid* past values.
// It is true for all clocks other than the first clock.
initial f_past_valid = 1'b0;
always @(posedge i_aclk)
f_past_valid <= 1'b1;
//
// Reset should always be active (low) initially
always @(posedge i_aclk)
if (!f_past_valid)
`SLAVE_ASSUME(!i_aresetn);
//
// During and following a reset, TVALID should be deasserted
always @(posedge i_aclk)
if ((!f_past_valid)||(!i_aresetn && OPT_ASYNC_RESET)||($past(!i_aresetn)))
`SLAVE_ASSUME(!i_tvalid);
//
// If TVALID but not TREADY, then the master isn't allowed to change
// anything until the slave asserts TREADY.
always @(posedge i_aclk)
if ((f_past_valid)&&($past(i_aresetn))&&(!OPT_ASYNC_RESET || i_aresetn)
&&($past(i_tvalid))&&(!$past(i_tready)))
begin
`SLAVE_ASSUME(i_tvalid);
`SLAVE_ASSUME($stable(i_tstrb));
`SLAVE_ASSUME($stable(i_tkeep));
`SLAVE_ASSUME($stable(i_tlast));
`SLAVE_ASSUME($stable(i_tid));
`SLAVE_ASSUME($stable(i_tdest));
`SLAVE_ASSUME($stable(i_tuser));
end
generate for(k=0; k 0)
begin : MAX_PACKET
always @(*)
`SLAVE_ASSUME(f_bytecount + f_vbytes <= F_MAX_PACKET);
end endgenerate
//
// F_MIN_PACKET
//
// An optoinal check, forcing a minimum packet length
generate if (F_MIN_PACKET > 0)
begin : MIN_PACKET
always @(*)
if (i_tvalid && i_tlast)
`SLAVE_ASSUME(f_bytecount + f_vbytes >= F_MIN_PACKET);
end endgenerate
//
// F_MAX_STALL
//
// Another optional check, this time insisting that the READY flag can
// only be low for up to F_MAX_STALL clocks.
//
generate if (F_MAX_STALL > 0)
begin : MAX_STALL_CHECK
always @(*)
`SLAVE_ASSERT(f_stall_count < F_MAX_STALL);
end endgenerate
endmodule
`undef SLAVE_ASSUME
`undef SLAVE_ASSERT
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1309/tb_formal_top.v 0000664 0000000 0000000 00000006433 14502055570 0030605 0 ustar 00root root 0000000 0000000 `default_nettype none
module tb_formal_top #(
parameter no_backpressure = 0
) (
input wire clk,
input wire aresetn,
input wire [31:0] s_axis_tdata,
input wire s_axis_tlast,
input wire s_axis_tvalid,
output wire s_axis_tready,
output wire [31:0] m_axis_tdata,
output wire m_axis_tlast,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire signed [31:0] discrepancy
);
reg [31:0] input_byte_count;
reg [31:0] output_byte_count;
//reg [0+0-1:0] input_routecheck;
//reg [0+0-1:0] output_routecheck;
reg f_past_valid;
wire signed [31:0] byte_count_discrepancy;
reg packet_end;
faxis_slave #(
.F_MAX_PACKET(0),
.F_MIN_PACKET(0),
.F_MAX_STALL(0),
.C_S_AXI_DATA_WIDTH(32),
.C_S_AXI_ID_WIDTH(0),
.C_S_AXI_ADDR_WIDTH(0),
.C_S_AXI_USER_WIDTH(0),
.OPT_ASYNC_RESET(1'b0)
) axis_slave_formal_properties (
.i_aclk(clk),
.i_aresetn(aresetn),
.i_tvalid(s_axis_tvalid),
.i_tready(s_axis_tready),
.i_tdata(s_axis_tdata),
.i_tlast(s_axis_tlast),
.f_bytecount(input_byte_count)
//.f_routecheck(input_routecheck)
);
faxis_master #(
.F_MAX_PACKET(0),
.F_MIN_PACKET(0),
.F_MAX_STALL(0),
.C_S_AXI_DATA_WIDTH(32),
.C_S_AXI_ID_WIDTH(0),
.C_S_AXI_ADDR_WIDTH(0),
.C_S_AXI_USER_WIDTH(0),
.OPT_ASYNC_RESET(1'b0)
) axis_master_formal_properties (
.i_aclk(clk),
.i_aresetn(aresetn),
.i_tvalid(m_axis_tvalid),
.i_tready(m_axis_tready),
.i_tdata(m_axis_tdata),
.i_tlast(m_axis_tlast),
.f_bytecount(output_byte_count)
//.f_routecheck(output_routecheck)
);
axis_squarer axis_dut (
.clk(clk),
.aresetn(aresetn),
.s_axis_tdata(s_axis_tdata),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.m_axis_tdata(m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast)
);
// f_past_valid is used to make certain that temporal assertions
// depending upon past values depend upon *valid* past values.
// It is true for all clocks other than the first clock.
initial f_past_valid = 1'b0;
always @(posedge clk)
f_past_valid <= 1'b1;
always @(*)
begin
assert(input_byte_count%4==0);
assert(output_byte_count%4==0);
byte_count_discrepancy = input_byte_count-output_byte_count;
discrepancy <= byte_count_discrepancy;
assume(input_byte_count<=32'h7fffffff);
assert(output_byte_count<=32'h20);
if (aresetn == 1) begin
//assert(byte_count_discrepancy>=-36);
/*assert(byte_count_discrepancy%32 == 0
|| byte_count_discrepancy%32 == 4
|| byte_count_discrepancy%32 == -4);*/
end
// Hints below are only for the cover property
//assume(aresetn == f_past_valid);
//assume(s_axis_tvalid == 1'b1);
//assume(m_axis_tready == 1'b1);
//assume(input_byte_count & 32'hFFFF0000 == 0);
//cover(byte_count_discrepancy < -4);
//cover(output_byte_count==16);
end
always @(posedge clk)
begin
if (f_past_valid && $past(aresetn)==1 && aresetn ==1) begin
if ($past(s_axis_tvalid) == 1'b1 && $past(s_axis_tready) == 1'b1) begin
assert(m_axis_tvalid == 1'b1);
assert(~$past(s_axis_tdata)==m_axis_tdata);
end
end
if (no_backpressure==1) begin
assume(m_axis_tready==1);
assume(s_axis_tlast==0);
end
cover(f_past_valid && $past(aresetn)==1 && aresetn==1
&& $past(s_axis_tready)==1'b0 && $past(m_axis_tvalid)==1'b0
&& s_axis_tready==1'b1 && m_axis_tvalid==1'b0);
//cover(output_byte_count==16'h10);
end
endmodule
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1309/testsuite.sh 0000775 0000000 0000000 00000000173 14502055570 0030152 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
#formal axis_squarer
run_symbiyosys -f axis_squarer.sby cover
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1309b/ 0000775 0000000 0000000 00000000000 14502055570 0025723 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1309b/psl_test.sby 0000664 0000000 0000000 00000000261 14502055570 0030276 0 ustar 00root root 0000000 0000000 [tasks]
prove
[options]
depth 25
prove: mode bmc
[engines]
prove: smtbmc z3
[script]
prove: ghdl --std=08 psl_test.vhdl -e psl_test
prep -top psl_test
[files]
psl_test.vhdl
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1309b/psl_test.vhdl 0000664 0000000 0000000 00000002731 14502055570 0030442 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic
);
end entity sequencer;
architecture rtl of sequencer is
signal index : natural := seq'low;
signal ch : character;
function to_bit (a : in character) return std_logic is
variable ret : std_logic;
begin
case a is
when '0' | '_' => ret := '0';
when '1' | '-' => ret := '1';
when others => ret := 'X';
end case;
return ret;
end function to_bit;
begin
process (clk) is
begin
if rising_edge(clk) then
if (index < seq'high) then
index <= index + 1;
end if;
end if;
end process;
ch <= seq(index);
data <= to_bit(ch);
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
entity psl_test is
port (
clk : in std_logic
);
end entity psl_test;
architecture psl of psl_test is
component sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic
);
end component sequencer;
signal a, b : std_logic;
begin
-- 0123
SEQ_A : sequencer generic map ("--___") port map (clk, a);
SEQ_B : sequencer generic map ("__---") port map (clk, b);
-- All is sensitive to rising edge of clk
default clock is rising_edge(clk);
-- This assertion holds
SERE_2_a : assert always {a; a} |=> {b};
end architecture psl;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1309b/testsuite.sh 0000775 0000000 0000000 00000000161 14502055570 0030311 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
run_symbiyosys -fd work/psl_test psl_test.sby prove
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1312/ 0000775 0000000 0000000 00000000000 14502055570 0025553 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1312/ent.vhdl 0000664 0000000 0000000 00000000316 14502055570 0027220 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (
a : inout std_logic := '0';
d_out : out std_logic
);
end;
architecture a of ent is
begin
d_out <= a;
end;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1312/testsuite.sh 0000775 0000000 0000000 00000000137 14502055570 0030144 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
synth_import --std=08 ent.vhdl -e
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1314/ 0000775 0000000 0000000 00000000000 14502055570 0025555 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1314/issue.vhdl 0000664 0000000 0000000 00000007617 14502055570 0027577 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic
);
end entity sequencer;
architecture rtl of sequencer is
signal index : natural := seq'low;
function to_bit (a : in character) return std_logic is
variable ret : std_logic;
begin
case a is
when '0' | '_' => ret := '0';
when '1' | '-' => ret := '1';
when others => ret := 'X';
end case;
return ret;
end function to_bit;
begin
process (clk) is
begin
if rising_edge(clk) then
if (index < seq'high) then
index <= index + 1;
end if;
end if;
end process;
data <= to_bit(seq(index));
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
entity hex_sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic_vector(3 downto 0)
);
end entity hex_sequencer;
architecture rtl of hex_sequencer is
signal index : natural := seq'low;
function to_hex (a : in character) return std_logic_vector is
variable ret : std_logic_vector(3 downto 0);
begin
case a is
when '0' | '_' => ret := x"0";
when '1' => ret := x"1";
when '2' => ret := x"2";
when '3' => ret := x"3";
when '4' => ret := x"4";
when '5' => ret := x"5";
when '6' => ret := x"6";
when '7' => ret := x"7";
when '8' => ret := x"8";
when '9' => ret := x"9";
when 'a' | 'A' => ret := x"A";
when 'b' | 'B' => ret := x"B";
when 'c' | 'C' => ret := x"C";
when 'd' | 'D' => ret := x"D";
when 'e' | 'E' => ret := x"E";
when 'f' | 'F' | '-' => ret := x"F";
when others => ret := x"X";
end case;
return ret;
end function to_hex;
begin
process (clk) is
begin
if rising_edge(clk) then
if (index < seq'high) then
index <= index + 1;
end if;
end if;
end process;
data <= to_hex(seq(index));
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity issue is
port (
clk : in std_logic
);
end entity issue;
architecture psl of issue is
component sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic
);
end component sequencer;
component hex_sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic_vector(3 downto 0)
);
end component hex_sequencer;
signal req, ack : std_logic;
signal din, dout : std_logic_vector(3 downto 0);
begin
-- 0123456789
SEQ_REQ : sequencer generic map ("_-______-____") port map (clk, req);
SEQ_DIN : hex_sequencer generic map ("4433344774444") port map (clk, din);
SEQ_ACK : sequencer generic map ("___-______-__") port map (clk, ack);
SEQ_DOUT : hex_sequencer generic map ("2244333447744") port map (clk, dout);
-- All is sensitive to rising edge of clk
default clock is rising_edge(clk);
-- Check for two possible values of din/dout
NEXT_EVENT_0_a : assert always ((req and din = x"4") -> next_event(ack)(dout = x"4"));
NEXT_EVENT_1_a : assert always ((req and din = x"7") -> next_event(ack)(dout = x"7"));
-- Check for all possible values of din/dout
check_transfer : for i in 0 to 15 generate
signal i_slv : std_logic_vector(din'range);
begin
i_slv <= std_logic_vector(to_unsigned(i, 4));
-- Without name it works
assert always ((req and din = i_slv) -> next_event(ack)(dout = i_slv));
-- This errors because of similar names of all asserts
-- ERROR: Assert `count_id(cell->name) == 0' failed in kernel/rtlil.cc:1613.
NEXT_EVENT_a : assert always ((req and din = i_slv) -> next_event(ack)(dout = i_slv));
end generate check_transfer;
end architecture psl;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1314/testsuite.sh 0000775 0000000 0000000 00000000141 14502055570 0030141 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
synth_import --std=08 issue.vhdl -e
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1318/ 0000775 0000000 0000000 00000000000 14502055570 0025561 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1318/ram_blk.vhdl 0000664 0000000 0000000 00000002006 14502055570 0030045 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram_blk is
generic (
AWIDTH : integer := 8;
DWIDTH : integer := 64
);
port (
clk : in std_logic;
rd_addr : in std_logic_vector(AWIDTH - 1 downto 0);
rd_data : out std_logic_vector(DWIDTH - 1 downto 0);
wr_en : in std_logic;
wr_addr : in std_logic_vector(AWIDTH - 1 downto 0);
wr_data : in std_logic_vector(DWIDTH - 1 downto 0)
);
end ram_blk;
architecture rtl of ram_blk is
type ram_type is
array (0 to 2**AWIDTH - 1) of std_logic_vector(DWIDTH - 1 downto 0);
signal ram : ram_type;
attribute ram_style : string;
attribute ram_style of ram : signal is "block";
attribute ram_decomp : string;
attribute ram_decomp of ram : signal is "power";
begin
process(clk)
begin
if rising_edge(clk) then
if wr_en = '1' then
ram(to_integer(unsigned(wr_addr))) <= wr_data;
end if;
rd_data <= ram(to_integer(unsigned(rd_addr)));
end if;
end process;
end;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1318/testsuite.sh 0000775 0000000 0000000 00000000226 14502055570 0030151 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
run_yosys -q -p "ghdl ram_blk.vhdl -e; write_verilog ram_blk.v"
grep ram_style ram_blk.v
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1421a/ 0000775 0000000 0000000 00000000000 14502055570 0025715 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1421a/aes_pkg.vhdl 0000664 0000000 0000000 00000002074 14502055570 0030210 0 ustar 00root root 0000000 0000000
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package aes_pkg is
type t_usig_1d is array(natural range <>) of unsigned(7 downto 0);
type t_usig_2d is array(natural range <>, natural range <>) of unsigned(7 downto 0);
constant C_STATE_ROWS : integer := 2;
constant C_STATE_COLS : integer := 2;
subtype st_word is t_usig_1d(0 to C_STATE_COLS - 1);
subtype st_state is t_usig_2d(0 to C_STATE_ROWS - 1, 0 to C_STATE_COLS - 1);
subtype st_sbox is t_usig_1d(0 to 255);
type t_key is array(natural range <>) of st_word;
function mix_columns (a_in : st_state) return st_state;
end package aes_pkg;
package body aes_pkg is
-- FIPS 197, 5.1.3 MixColumns() Transformation
function mix_columns (a_in : st_state) return st_state is
variable a_out : st_state;
begin
for col in 0 to C_STATE_COLS - 1 loop
a_out(0, col) := a_in(0, col) xor
a_in(1, col);
a_out(1, col) := a_in(0, col) xor
a_in(1, col);
end loop;
return a_out;
end mix_columns;
end package body;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1421a/cipher.vhdl 0000664 0000000 0000000 00000004242 14502055570 0030050 0 ustar 00root root 0000000 0000000 -- cipher module, as described in: "FIPS 197, 5.1 Cipher"
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library aes_lib;
use aes_lib.aes_pkg.all;
entity cipher is
generic (
G_KEY_WORDS : integer := 4
);
port (
isl_clk : in std_logic;
isl_valid : in std_logic;
ia_data : in st_state;
ia_key : in t_key(0 to G_KEY_WORDS - 1);
oa_data : out st_state;
osl_valid : out std_logic
);
end entity cipher;
architecture rtl of cipher is
-- states
signal slv_stage : std_logic_vector(1 to 2) := (others => '0');
signal sl_next_round : std_logic := '0';
-- data container
-- data format in key expansion: words are rows
-- data format in cipher: words are columns
-- conversion: transpose matrix
signal a_data_in : st_state;
signal a_data_added : st_state;
signal a_data_srows : st_state;
-- keys
signal a_round_keys : st_state;
signal int_round_cnt : integer range 0 to 13 := 0;
begin
sl_next_round <= slv_stage(2);
proc_key_expansion : process (isl_clk) is
variable v_new_col : integer range 0 to C_STATE_COLS - 1;
variable v_data_sbox : st_state;
variable v_data_mcols : st_state;
begin
if (rising_edge(isl_clk)) then
slv_stage <= (isl_valid or sl_next_round) & slv_stage(1);
-- substitute bytes and shift rows
if (slv_stage(1) = '1') then
for row in 0 to C_STATE_ROWS - 1 loop
for col in 0 to 0 loop --C_STATE_COLS - 1 loop
-- substitute bytes
-- v_data_sbox(row, col) := C_SBOX(to_integer(a_data_added(row, col)));
v_data_sbox(row, col) := a_data_added(row, col);
-- shift rows
-- avoid modulo by using unsigned overflow
v_new_col := to_integer(to_unsigned(col, 1) - row);
a_data_srows(row, v_new_col) <= v_data_sbox(row, col);
end loop;
end loop;
end if;
-- mix columns and add key
if (slv_stage(2) = '1') then
a_data_added <= mix_columns(a_data_srows);
end if;
end if;
end process proc_key_expansion;
oa_data <= a_data_added;
osl_valid <= '0';
end architecture rtl;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1421a/testsuite.sh 0000775 0000000 0000000 00000000176 14502055570 0030311 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
synth_import --std=08 --work=aes_lib aes_pkg.vhdl cipher.vhdl -e
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1610/ 0000775 0000000 0000000 00000000000 14502055570 0025554 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1610/exp.vhdl 0000664 0000000 0000000 00000001033 14502055570 0027224 0 ustar 00root root 0000000 0000000 library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;
entity exp is
port (
clk : in std_logic
);
end entity exp;
architecture behav of exp is
signal ver_clk : std_logic;
signal count : integer := 0;
attribute gclk : boolean;
attribute gclk of ver_clk : signal is true;
begin
default Clock is rising_edge(clk);
process (ver_clk)
begin
if rising_edge(ver_clk) then
count <= count + 1;
end if;
end process;
assert always next count = prev(count) + 1;
end architecture behav;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1610/testsuite.sh 0000775 0000000 0000000 00000000225 14502055570 0030143 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
run_yosys -q -p "ghdl --std=08 exp.vhdl -e; write_rtlil exp.il"
fgrep 'cell $ff' exp.il
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1682/ 0000775 0000000 0000000 00000000000 14502055570 0025565 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1682/testsuite.sh 0000775 0000000 0000000 00000000243 14502055570 0030154 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
run_yosys -q -p "ghdl --std=08 top.vhdl -e; write_verilog exp.v"
fgrep 'loc = "13"' exp.v > /dev/null
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1682/top.vhdl 0000664 0000000 0000000 00000001156 14502055570 0027251 0 ustar 00root root 0000000 0000000 library ieee ;
context ieee.ieee_std_context;
--use work.components.all;
entity top is
port (
pin1: out std_logic
);
attribute LOC: string;
attribute LOC of pin1: signal is "13";
end;
architecture arch of top is
signal clk: std_logic;
signal led_timer: unsigned(23 downto 0) := (others=>'0');
begin
-- internal_oscillator_inst: OSCH
-- generic map (
-- NOM_FREQ => "16.63"
-- )
-- port map (
-- STDBY => '0',
-- OSC => clk
-- );
process(clk)
begin
if rising_edge(clk) then
led_timer <= led_timer + 1;
end if;
end process;
pin1 <= led_timer(led_timer'left);
end;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1699/ 0000775 0000000 0000000 00000000000 14502055570 0025575 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1699/test2.vhdl 0000664 0000000 0000000 00000001660 14502055570 0027520 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test2 is
port (
clk : in std_ulogic;
addr : in std_ulogic_vector(4 downto 0);
data : out std_ulogic_vector(2 downto 0)
);
end entity test2;
architecture rtl of test2 is
type result_t is array(integer range 0 to 15) of std_ulogic_vector(2 downto 0);
constant result_select : result_t := (
0 => "001",
1 => "001",
2 => "001",
3 => "001",
4 => "001",
5 => "001",
6 => "001",
7 => "001",
others => "000"
);
begin
--lookup_0: process(all)
--begin
--data <= result_select(to_integer(unsigned(addr)));
--end process;
lookup_0: process(clk)
begin
if rising_edge(clk) then
data <= result_select(to_integer(unsigned(addr)));
end if;
end process;
end;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue1699/testsuite.sh 0000775 0000000 0000000 00000000177 14502055570 0030172 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
run_yosys -p "ghdl --std=08 test2.vhdl -e; write_verilog test2.v"
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue2373/ 0000775 0000000 0000000 00000000000 14502055570 0025563 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue2373/async_test-plus.sby 0000664 0000000 0000000 00000000372 14502055570 0031441 0 ustar 00root root 0000000 0000000 [tasks]
prove
bmc
cover
[options]
bmc: mode bmc
cover: mode cover
prove: mode bmc
depth 50
[engines]
prove: smtbmc z3
[script]
ghdl --std=08 dut.vhdl tb_dut-plus.vhdl -e tb_dut
prep -top tb_dut
[files]
dut.vhdl
tb_dut-star.vhdl
tb_dut-plus.vhdl
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue2373/async_test-star.sby 0000664 0000000 0000000 00000000372 14502055570 0031427 0 ustar 00root root 0000000 0000000 [tasks]
prove
bmc
cover
[options]
bmc: mode bmc
cover: mode cover
prove: mode bmc
depth 50
[engines]
prove: smtbmc z3
[script]
ghdl --std=08 dut.vhdl tb_dut-star.vhdl -e tb_dut
prep -top tb_dut
[files]
dut.vhdl
tb_dut-star.vhdl
tb_dut-plus.vhdl
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue2373/dut.vhdl 0000664 0000000 0000000 00000001360 14502055570 0027236 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity dut is
port(
clk_in: in std_logic;
a1_in: in std_logic;
b1_out: out std_logic;
a2_in: in std_logic;
b2_out: out std_logic
);
end;
architecture rtl of dut is
signal cnt: integer range 0 to 20 := 0;
signal a2_prev: std_logic := '0';
begin
process(clk_in)
begin
if rising_edge(clk_in) then
if cnt /= 20 then
cnt <= cnt + 1;
end if;
end if;
end process;
process(clk_in)
begin
if rising_edge(clk_in) then
a2_prev <= a2_in;
b1_out <= not a1_in;
if cnt = 20 then
b1_out <= a1_in;
end if;
end if;
end process;
process(all)
begin
b2_out <= a2_prev;
if cnt = 20 then
b2_out <= not a2_in;
end if;
b2_out <= not a2_in;
end process;
end;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue2373/tb_dut-plus.vhdl 0000664 0000000 0000000 00000002362 14502055570 0030707 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity tb_dut is
port(
clk_in: in std_logic;
dut1_a1_in: in std_logic;
dut1_b1_out: out std_logic;
dut1_a2_in: in std_logic;
dut1_b2_out: out std_logic;
dut2_a1_in: in std_logic;
dut2_b1_out: out std_logic;
dut2_a2_in: in std_logic;
dut2_b2_out: out std_logic
);
end;
architecture tb of tb_dut is
begin
dut_1: entity work.dut
port map(
clk_in => clk_in,
a1_in => dut1_a1_in,
b1_out => dut1_b1_out,
a2_in => dut1_a2_in,
b2_out => dut1_b2_out
);
dut_2: entity work.dut
port map(
clk_in => clk_in,
a1_in => dut2_a1_in,
b1_out => dut2_b1_out,
a2_in => dut2_a2_in,
b2_out => dut2_b2_out
);
default clock is rising_edge(clk_in);
-- stability_1: assert
-- {(dut1_a1_in = dut2_a1_in and dut1_a2_in = dut2_a2_in)[+];
-- {(dut1_a1_in = dut2_a1_in and dut1_a2_in = dut2_a2_in)[*1 to inf];
-- dut1_a1_in /= dut2_a1_in and dut1_a2_in = dut2_a2_in} |->
-- {dut1_b1_out = dut2_b1_out}!;
stability_2: assert
{(dut1_a1_in = dut2_a1_in and dut1_a2_in = dut2_a2_in)[+];
-- {(dut1_a1_in = dut2_a1_in and dut1_a2_in = dut2_a2_in)[*1 to inf];
dut1_a1_in = dut2_a1_in and dut1_a2_in /= dut2_a2_in} |->
{dut1_b2_out = dut2_b2_out}!;
end;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue2373/tb_dut-star.vhdl 0000664 0000000 0000000 00000002362 14502055570 0030675 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity tb_dut is
port(
clk_in: in std_logic;
dut1_a1_in: in std_logic;
dut1_b1_out: out std_logic;
dut1_a2_in: in std_logic;
dut1_b2_out: out std_logic;
dut2_a1_in: in std_logic;
dut2_b1_out: out std_logic;
dut2_a2_in: in std_logic;
dut2_b2_out: out std_logic
);
end;
architecture tb of tb_dut is
begin
dut_1: entity work.dut
port map(
clk_in => clk_in,
a1_in => dut1_a1_in,
b1_out => dut1_b1_out,
a2_in => dut1_a2_in,
b2_out => dut1_b2_out
);
dut_2: entity work.dut
port map(
clk_in => clk_in,
a1_in => dut2_a1_in,
b1_out => dut2_b1_out,
a2_in => dut2_a2_in,
b2_out => dut2_b2_out
);
default clock is rising_edge(clk_in);
-- stability_1: assert
-- {(dut1_a1_in = dut2_a1_in and dut1_a2_in = dut2_a2_in)[+];
-- {(dut1_a1_in = dut2_a1_in and dut1_a2_in = dut2_a2_in)[*1 to inf];
-- dut1_a1_in /= dut2_a1_in and dut1_a2_in = dut2_a2_in} |->
-- {dut1_b1_out = dut2_b1_out}!;
stability_2: assert
-- {(dut1_a1_in = dut2_a1_in and dut1_a2_in = dut2_a2_in)[+];
{(dut1_a1_in = dut2_a1_in and dut1_a2_in = dut2_a2_in)[*1 to inf];
dut1_a1_in = dut2_a1_in and dut1_a2_in /= dut2_a2_in} |->
{dut1_b2_out = dut2_b2_out}!;
end;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue2373/testsuite.sh 0000775 0000000 0000000 00000000574 14502055570 0030161 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
run_symbiyosys -fd work async_test-plus.sby prove || true
if ! grep -q "BMC failed" work/engine_0/logfile.txt; then
echo "failure expected"
exit 1
fi
run_symbiyosys -fd work async_test-star.sby prove || true
if ! grep -q "BMC failed" work/engine_0/logfile.txt; then
echo "failure expected"
exit 1
fi
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue2392/ 0000775 0000000 0000000 00000000000 14502055570 0025564 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue2392/async_test-0.sby 0000664 0000000 0000000 00000000343 14502055570 0030614 0 ustar 00root root 0000000 0000000 [tasks]
prove
bmc
cover
[options]
bmc: mode bmc
cover: mode cover
prove: mode bmc
depth 50
[engines]
prove: smtbmc z3
[script]
ghdl --std=08 dut.vhdl tb_dut-0.vhdl -e tb_dut
prep -top tb_dut
[files]
dut.vhdl
tb_dut-0.vhdl
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue2392/async_test-1.sby 0000664 0000000 0000000 00000000334 14502055570 0030615 0 ustar 00root root 0000000 0000000 [tasks]
prove
bmc
cover
[options]
bmc: mode bmc
cover: mode cover
prove: mode bmc
depth 50
[engines]
smtbmc z3
[script]
ghdl --std=08 dut.vhdl tb_dut-1.vhdl -e tb_dut
prep -top tb_dut
[files]
dut.vhdl
tb_dut-1.vhdl
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue2392/async_test-2.sby 0000664 0000000 0000000 00000000343 14502055570 0030616 0 ustar 00root root 0000000 0000000 [tasks]
prove
bmc
cover
[options]
bmc: mode bmc
cover: mode cover
prove: mode bmc
depth 50
[engines]
prove: smtbmc z3
[script]
ghdl --std=08 dut.vhdl tb_dut-2.vhdl -e tb_dut
prep -top tb_dut
[files]
dut.vhdl
tb_dut-2.vhdl
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue2392/async_test.sby 0000664 0000000 0000000 00000000330 14502055570 0030453 0 ustar 00root root 0000000 0000000 [tasks]
prove
bmc
cover
[options]
bmc: mode bmc
cover: mode cover
prove: mode bmc
depth 50
[engines]
smtbmc z3
[script]
ghdl --std=08 dut.vhdl tb_dut.vhdl -e tb_dut
prep -top tb_dut
[files]
dut.vhdl
tb_dut.vhdl
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue2392/dut.vhdl 0000664 0000000 0000000 00000001401 14502055570 0027233 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity dut is
port(
clk_in: in std_logic;
a1_in: in std_logic;
b1_out: out std_logic := '0';
a2_in: in std_logic;
b2_out: out std_logic := '0'
);
end;
architecture rtl of dut is
signal cnt: integer range 0 to 20 := 0;
signal a2_prev: std_logic := '0';
begin
process(clk_in)
begin
if rising_edge(clk_in) then
if cnt /= 20 then
cnt <= cnt + 1;
end if;
end if;
end process;
process(clk_in)
begin
if rising_edge(clk_in) then
a2_prev <= a2_in;
b1_out <= not a1_in;
if cnt = 20 then
b1_out <= a1_in;
end if;
end if;
end process;
process(all)
begin
b2_out <= a2_prev;
if cnt = 20 then
b2_out <= not a2_in;
end if;
-- b2_out <= not a2_in;
end process;
end;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue2392/tb_dut-0.vhdl 0000664 0000000 0000000 00000004246 14502055570 0030067 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity tb_dut is
port(
clk_in: in std_logic;
dut1_a1_in: in std_logic;
dut1_b1_out: out std_logic;
dut1_a2_in: in std_logic;
dut1_b2_out: out std_logic;
dut2_a1_in: in std_logic;
dut2_b1_out: out std_logic;
dut2_a2_in: in std_logic;
dut2_b2_out: out std_logic
);
end;
architecture tb of tb_dut is
signal all_inputs_equal: std_logic;
signal a1_differ: std_logic;
signal a2_differ: std_logic;
signal b1_equal: std_logic;
signal b2_equal: std_logic;
begin
dut_1: entity work.dut
port map(
clk_in => clk_in,
a1_in => dut1_a1_in,
b1_out => dut1_b1_out,
a2_in => dut1_a2_in,
b2_out => dut1_b2_out
);
dut_2: entity work.dut
port map(
clk_in => clk_in,
a1_in => dut2_a1_in,
b1_out => dut2_b1_out,
a2_in => dut2_a2_in,
b2_out => dut2_b2_out
);
-- Formal part =>
process(all)
begin
all_inputs_equal <= '1';
if dut1_a1_in /= dut2_a1_in or dut1_a2_in /= dut2_a2_in then
all_inputs_equal <= '0';
end if;
a1_differ <= '0';
if dut1_a1_in /= dut2_a1_in then
a1_differ <= '1';
end if;
a2_differ <= '0';
if dut1_a2_in /= dut2_a2_in then
a2_differ <= '1';
end if;
b1_equal <= '0';
if dut1_b1_out = dut2_b1_out then
b1_equal <= '1';
end if;
b2_equal <= '0';
if dut1_b2_out = dut2_b2_out then
b2_equal <= '1';
end if;
end process;
default clock is rising_edge(clk_in);
b1_nonasync: assert {all_inputs_equal[*1 to inf]; a1_differ} |-> {b1_equal};
-- This _should_ generate an assert at cycle 20:
-- b2_nonasync_1: assert {all_inputs_equal[*1 to inf]; a2_differ} |-> {b2_equal};
-- This _should_ generate an assert at cycle 20:
-- b2_nonasync_2: assert {all_inputs_equal[+]; a2_differ} |-> {b2_equal};
-- This generates an assert at cycle 20:
-- b2_nonasync_3: assert {all_inputs_equal[*2 to inf]; a2_differ} |-> {b2_equal};
-- This generates an assert at cycle 20:
-- b2_nonasync_4: assert {all_inputs_equal[*0 to inf]; a2_differ} |-> {b2_equal};
-- This generates an assert at cycle 20:
-- b2_nonasync_5: assert {all_inputs_equal[*]; a2_differ} |-> {b2_equal};
--cover_tester: cover {all_inputs_equal[*21]; a2_differ; all_inputs_equal[*5]};
end;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue2392/tb_dut-1.vhdl 0000664 0000000 0000000 00000004246 14502055570 0030070 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity tb_dut is
port(
clk_in: in std_logic;
dut1_a1_in: in std_logic;
dut1_b1_out: out std_logic;
dut1_a2_in: in std_logic;
dut1_b2_out: out std_logic;
dut2_a1_in: in std_logic;
dut2_b1_out: out std_logic;
dut2_a2_in: in std_logic;
dut2_b2_out: out std_logic
);
end;
architecture tb of tb_dut is
signal all_inputs_equal: std_logic;
signal a1_differ: std_logic;
signal a2_differ: std_logic;
signal b1_equal: std_logic;
signal b2_equal: std_logic;
begin
dut_1: entity work.dut
port map(
clk_in => clk_in,
a1_in => dut1_a1_in,
b1_out => dut1_b1_out,
a2_in => dut1_a2_in,
b2_out => dut1_b2_out
);
dut_2: entity work.dut
port map(
clk_in => clk_in,
a1_in => dut2_a1_in,
b1_out => dut2_b1_out,
a2_in => dut2_a2_in,
b2_out => dut2_b2_out
);
-- Formal part =>
process(all)
begin
all_inputs_equal <= '1';
if dut1_a1_in /= dut2_a1_in or dut1_a2_in /= dut2_a2_in then
all_inputs_equal <= '0';
end if;
a1_differ <= '0';
if dut1_a1_in /= dut2_a1_in then
a1_differ <= '1';
end if;
a2_differ <= '0';
if dut1_a2_in /= dut2_a2_in then
a2_differ <= '1';
end if;
b1_equal <= '0';
if dut1_b1_out = dut2_b1_out then
b1_equal <= '1';
end if;
b2_equal <= '0';
if dut1_b2_out = dut2_b2_out then
b2_equal <= '1';
end if;
end process;
default clock is rising_edge(clk_in);
-- b1_nonasync: assert {all_inputs_equal[*1 to inf]; a1_differ} |-> {b1_equal};
-- This _should_ generate an assert at cycle 20:
b2_nonasync_1: assert {all_inputs_equal[*1 to inf]; a2_differ} |-> {b2_equal};
-- This _should_ generate an assert at cycle 20:
-- b2_nonasync_2: assert {all_inputs_equal[+]; a2_differ} |-> {b2_equal};
-- This generates an assert at cycle 20:
-- b2_nonasync_3: assert {all_inputs_equal[*2 to inf]; a2_differ} |-> {b2_equal};
-- This generates an assert at cycle 20:
-- b2_nonasync_4: assert {all_inputs_equal[*0 to inf]; a2_differ} |-> {b2_equal};
-- This generates an assert at cycle 20:
-- b2_nonasync_5: assert {all_inputs_equal[*]; a2_differ} |-> {b2_equal};
--cover_tester: cover {all_inputs_equal[*21]; a2_differ; all_inputs_equal[*5]};
end;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue2392/tb_dut-2.vhdl 0000664 0000000 0000000 00000004246 14502055570 0030071 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity tb_dut is
port(
clk_in: in std_logic;
dut1_a1_in: in std_logic;
dut1_b1_out: out std_logic;
dut1_a2_in: in std_logic;
dut1_b2_out: out std_logic;
dut2_a1_in: in std_logic;
dut2_b1_out: out std_logic;
dut2_a2_in: in std_logic;
dut2_b2_out: out std_logic
);
end;
architecture tb of tb_dut is
signal all_inputs_equal: std_logic;
signal a1_differ: std_logic;
signal a2_differ: std_logic;
signal b1_equal: std_logic;
signal b2_equal: std_logic;
begin
dut_1: entity work.dut
port map(
clk_in => clk_in,
a1_in => dut1_a1_in,
b1_out => dut1_b1_out,
a2_in => dut1_a2_in,
b2_out => dut1_b2_out
);
dut_2: entity work.dut
port map(
clk_in => clk_in,
a1_in => dut2_a1_in,
b1_out => dut2_b1_out,
a2_in => dut2_a2_in,
b2_out => dut2_b2_out
);
-- Formal part =>
process(all)
begin
all_inputs_equal <= '1';
if dut1_a1_in /= dut2_a1_in or dut1_a2_in /= dut2_a2_in then
all_inputs_equal <= '0';
end if;
a1_differ <= '0';
if dut1_a1_in /= dut2_a1_in then
a1_differ <= '1';
end if;
a2_differ <= '0';
if dut1_a2_in /= dut2_a2_in then
a2_differ <= '1';
end if;
b1_equal <= '0';
if dut1_b1_out = dut2_b1_out then
b1_equal <= '1';
end if;
b2_equal <= '0';
if dut1_b2_out = dut2_b2_out then
b2_equal <= '1';
end if;
end process;
default clock is rising_edge(clk_in);
-- b1_nonasync: assert {all_inputs_equal[*1 to inf]; a1_differ} |-> {b1_equal};
-- This _should_ generate an assert at cycle 20:
-- b2_nonasync_1: assert {all_inputs_equal[*1 to inf]; a2_differ} |-> {b2_equal};
-- This _should_ generate an assert at cycle 20:
b2_nonasync_2: assert {all_inputs_equal[+]; a2_differ} |-> {b2_equal};
-- This generates an assert at cycle 20:
-- b2_nonasync_3: assert {all_inputs_equal[*2 to inf]; a2_differ} |-> {b2_equal};
-- This generates an assert at cycle 20:
-- b2_nonasync_4: assert {all_inputs_equal[*0 to inf]; a2_differ} |-> {b2_equal};
-- This generates an assert at cycle 20:
-- b2_nonasync_5: assert {all_inputs_equal[*]; a2_differ} |-> {b2_equal};
--cover_tester: cover {all_inputs_equal[*21]; a2_differ; all_inputs_equal[*5]};
end;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue2392/tb_dut.vhdl 0000664 0000000 0000000 00000004242 14502055570 0027726 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity tb_dut is
port(
clk_in: in std_logic;
dut1_a1_in: in std_logic;
dut1_b1_out: out std_logic;
dut1_a2_in: in std_logic;
dut1_b2_out: out std_logic;
dut2_a1_in: in std_logic;
dut2_b1_out: out std_logic;
dut2_a2_in: in std_logic;
dut2_b2_out: out std_logic
);
end;
architecture tb of tb_dut is
signal all_inputs_equal: std_logic;
signal a1_differ: std_logic;
signal a2_differ: std_logic;
signal b1_equal: std_logic;
signal b2_equal: std_logic;
begin
dut_1: entity work.dut
port map(
clk_in => clk_in,
a1_in => dut1_a1_in,
b1_out => dut1_b1_out,
a2_in => dut1_a2_in,
b2_out => dut1_b2_out
);
dut_2: entity work.dut
port map(
clk_in => clk_in,
a1_in => dut2_a1_in,
b1_out => dut2_b1_out,
a2_in => dut2_a2_in,
b2_out => dut2_b2_out
);
-- Formal part =>
process(all)
begin
all_inputs_equal <= '1';
if dut1_a1_in /= dut2_a1_in or dut1_a2_in /= dut2_a2_in then
all_inputs_equal <= '0';
end if;
a1_differ <= '0';
if dut1_a1_in /= dut2_a1_in then
a1_differ <= '1';
end if;
a2_differ <= '0';
if dut1_a2_in /= dut2_a2_in then
a2_differ <= '1';
end if;
b1_equal <= '0';
if dut1_b1_out = dut2_b1_out then
b1_equal <= '1';
end if;
b2_equal <= '0';
if dut1_b2_out = dut2_b2_out then
b2_equal <= '1';
end if;
end process;
default clock is rising_edge(clk_in);
b1_nonasync: assert {all_inputs_equal[*1 to inf]; a1_differ} |-> {b1_equal};
-- This _should_ generate an assert at cycle 20:
b2_nonasync_1: assert {all_inputs_equal[*1 to inf]; a2_differ} |-> {b2_equal};
-- This _should_ generate an assert at cycle 20:
b2_nonasync_2: assert {all_inputs_equal[+]; a2_differ} |-> {b2_equal};
-- This generates an assert at cycle 20:
-- b2_nonasync_3: assert {all_inputs_equal[*2 to inf]; a2_differ} |-> {b2_equal};
-- This generates an assert at cycle 20:
-- b2_nonasync_4: assert {all_inputs_equal[*0 to inf]; a2_differ} |-> {b2_equal};
-- This generates an assert at cycle 20:
-- b2_nonasync_5: assert {all_inputs_equal[*]; a2_differ} |-> {b2_equal};
--cover_tester: cover {all_inputs_equal[*21]; a2_differ; all_inputs_equal[*5]};
end;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue2392/testsuite.sh 0000775 0000000 0000000 00000000647 14502055570 0030163 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
run_symbiyosys -fd work async_test-0.sby prove
run_symbiyosys -fd work async_test-1.sby prove || true
if ! grep -q "BMC failed" work/engine_0/logfile.txt; then
echo "failure expected"
exit 1
fi
run_symbiyosys -fd work async_test-2.sby prove || true
if ! grep -q "BMC failed" work/engine_0/logfile.txt; then
echo "failure expected"
exit 1
fi
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue2392b/ 0000775 0000000 0000000 00000000000 14502055570 0025726 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue2392b/compare_psl_p_plus.sby 0000664 0000000 0000000 00000000433 14502055570 0032333 0 ustar 00root root 0000000 0000000 [tasks]
compare
cover
[options]
compare: mode bmc
cover: mode cover
depth 100
[engines]
smtbmc z3
[script]
read_verilog synth_psl_p_plus.v
ghdl --std=08 compare_psl_p_plus.vhdl -e compare_psl_p_plus
prep -top compare_psl_p_plus
[files]
synth_psl_p_plus.v
compare_psl_p_plus.vhdl
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue2392b/compare_psl_p_plus.vhdl 0000664 0000000 0000000 00000003275 14502055570 0032502 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity compare_psl_p_plus is
port(
clk_in: in std_logic;
a_in: in std_logic;
b_in: in std_logic;
c_in: in std_logic
);
end;
architecture rtl of compare_psl_p_plus is
component psl_p_plus is
port(
clk_in: in std_logic;
a_in: in std_logic;
b_in: in std_logic;
c_in: in std_logic;
\p_plus_psl.A\: out std_logic;
\p_plus_psl.EN\: out std_logic
);
end component;
signal first_cycle: std_logic := '1';
signal nda_r0: std_logic := '0';
signal nda_res: std_logic;
signal p_plus_psl_a: std_logic;
signal p_plus_psl_en: std_logic;
signal p_plus_psl: std_logic;
begin
dut: psl_p_plus
port map(
clk_in => clk_in,
a_in => a_in,
b_in => b_in,
c_in => c_in,
\p_plus_psl.A\ => p_plus_psl_a,
\p_plus_psl.EN\ => p_plus_psl_en
);
p_plus_psl <= p_plus_psl_en and p_plus_psl_a;
reference_model_sync_pr: process(clk_in)
begin
if rising_edge(clk_in) then
first_cycle <= '0';
nda_r0 <= '0';
if first_cycle = '1' and a_in = '1' then
nda_r0 <= '1';
end if;
if nda_r0 = '1' and a_in = '1' then
nda_r0 <= '1';
end if;
end if;
end process;
reference_model_async_pr: process(all)
begin
nda_res <= '1';
if nda_r0 = '1' and b_in = '1' and c_in = '0' then
nda_res <= '0';
end if;
end process;
default clock is rising_edge(clk_in);
comparison_assert: postponed assert nda_res = p_plus_psl;
cover_psl: cover {true; true; p_plus_psl = '0'};
cover_psl_first: cover {true; true; [*]; p_plus_psl = '0'};
end;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue2392b/psl_p_plus.vhdl 0000664 0000000 0000000 00000000534 14502055570 0030767 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity psl_p_plus is
generic(
DATA_BITS: natural := 8
);
port(
clk_in: in std_logic;
a_in: in std_logic;
b_in: in std_logic;
c_in: in std_logic
);
end;
architecture psl of psl_p_plus is
begin
default clock is rising_edge(clk_in);
p_plus_psl: assert {a_in[+]; b_in} |-> {c_in};
end;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue2392b/psl_p_plus.ys 0000664 0000000 0000000 00000000450 14502055570 0030462 0 ustar 00root root 0000000 0000000 ghdl --std=08 psl_p_plus.vhdl -e psl_p_plus
flatten
rename -enumerate -pattern unnamed_assert_% t:$assert
rename -enumerate -pattern unnamed_assume_% t:$assume
rename -enumerate -pattern unnamed_cover_% t:$cover
expose -evert t:$assert t:$assume t:$cover
opt
write_verilog synth_psl_p_plus.v
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue2392b/testsuite.sh 0000775 0000000 0000000 00000000207 14502055570 0030315 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
run_yosys psl_p_plus.ys
run_symbiyosys -f compare_psl_p_plus.sby compare cover
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue999/ 0000775 0000000 0000000 00000000000 14502055570 0025517 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue999/test.vhdl 0000664 0000000 0000000 00000002013 14502055570 0027351 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
port(
clk : in std_logic;
read_reg : in std_ulogic_vector(4 downto 0);
read_data : out std_ulogic_vector(63 downto 0);
write_enable : in std_ulogic;
write_reg : in std_ulogic_vector(4 downto 0);
write_data : in std_ulogic_vector(63 downto 0)
);
end entity test;
architecture behaviour of test is
type regfile is array(0 to 31) of std_ulogic_vector(63 downto 0);
signal registers : regfile := (others => (others => '0'));
begin
register_write_0: process(clk)
begin
if rising_edge(clk) then
if write_enable = '1' then
registers(to_integer(unsigned(write_reg))) <= write_data;
end if;
end if;
end process register_write_0;
register_read_0: process(all)
begin
read_data <= registers(to_integer(unsigned(read_reg)));
end process register_read_0;
end architecture behaviour;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/issue999/testsuite.sh 0000775 0000000 0000000 00000000140 14502055570 0030102 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
synth_import --std=08 test.vhdl -e
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/xfail1/ 0000775 0000000 0000000 00000000000 14502055570 0025300 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/xfail1/test.vhdl 0000664 0000000 0000000 00000000332 14502055570 0027134 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity test is
port(
clk : in std_logic
);
end entity test;
architecture behaviour of test is
begin
clk <= '1';
end architecture behaviour;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/xfail1/testfail.sh 0000775 0000000 0000000 00000000217 14502055570 0027452 0 ustar 00root root 0000000 0000000 #!/bin/sh
# Same as testsuite.sh but should really fail.
topdir=../..
. $topdir/testenv.sh
synth_import --std=08 test.vhdl -e
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/ghdl-issues/xfail1/testsuite.sh 0000775 0000000 0000000 00000000227 14502055570 0027671 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
if synth_import --std=08 test.vhdl -e; then
echo "test is expected to fail"
exit 1
fi
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/ 0000775 0000000 0000000 00000000000 14502055570 0023200 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/bug-loop1/ 0000775 0000000 0000000 00000000000 14502055570 0025005 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/bug-loop1/loop1.vhdl 0000664 0000000 0000000 00000000441 14502055570 0026715 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity loop1 is
port (a : std_logic_vector (7 downto 0);
o : out std_logic_vector (15 downto 0));
end;
architecture behav of loop1 is
signal s : std_logic_vector (15 downto 0);
begin
s <= a & s (15 downto 8);
o <= s;
end behav;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/bug-loop1/testsuite.sh 0000775 0000000 0000000 00000000161 14502055570 0027373 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
for f in loop1; do
synth "${f}.vhdl -e ${f}"
done
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue101/ 0000775 0000000 0000000 00000000000 14502055570 0024552 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue101/counters_3.v 0000664 0000000 0000000 00000000323 14502055570 0027023 0 ustar 00root root 0000000 0000000 module counters_3 (input wire c, input wire aload, input wire [3:0]d,
output reg [3:0] q);
always @(posedge c, posedge aload) begin
if (aload)
q <= d;
else
q <= q + 1;
end
endmodule
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue101/counters_3.vhdl 0000664 0000000 0000000 00000001040 14502055570 0027510 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counters_3 is
port(C, ALOAD : in std_logic;
D : in std_logic_vector(3 downto 0);
Q : out std_logic_vector(3 downto 0));
end counters_3;
architecture archi of counters_3 is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C, ALOAD, D)
begin
if (ALOAD='1') then
tmp <= D;
elsif (C'event and C='1') then
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end archi;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue101/testsuite.sh 0000775 0000000 0000000 00000000150 14502055570 0027136 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
synth_import -fsynopsys counters_3.vhdl -e
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue102/ 0000775 0000000 0000000 00000000000 14502055570 0024553 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue102/counters_8.vhdl 0000664 0000000 0000000 00000001012 14502055570 0027515 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity counters_8 is
generic (MAX : integer := 12);
port(C, CLR : in std_logic;
Q : out integer range 0 to MAX-1);
end counters_8;
architecture archi of counters_8 is
signal cnt : integer range 0 to MAX-1;
begin
process (C, CLR)
begin
if (CLR='1') then
cnt <= 0;
elsif (rising_edge(C)) then
cnt <= (cnt + 1) mod MAX ;
end if;
end process;
Q <= cnt;
end archi;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue102/testsuite.sh 0000775 0000000 0000000 00000000150 14502055570 0027137 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
synth_import -fsynopsys counters_8.vhdl -e
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue11/ 0000775 0000000 0000000 00000000000 14502055570 0024472 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue11/test_nand.vhdl 0000664 0000000 0000000 00000000333 14502055570 0027327 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity test_nand is port (
sel0, sel1: in std_logic;
c: out std_logic);
end test_nand;
architecture synth of test_nand is
begin
c <= sel1 nand sel0;
end synth;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue11/test_nor.vhdl 0000664 0000000 0000000 00000000327 14502055570 0027210 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity test_nor is port (
sel0, sel1: in std_logic;
c: out std_logic);
end test_nor;
architecture synth of test_nor is
begin
c <= sel1 nor sel0;
end synth;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue11/test_or.vhdl 0000664 0000000 0000000 00000000323 14502055570 0027026 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity test_or is port (
sel0, sel1: in std_logic;
c: out std_logic);
end test_or;
architecture synth of test_or is
begin
c <= sel1 or sel0;
end synth;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue11/test_xnor.vhdl 0000664 0000000 0000000 00000000333 14502055570 0027375 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity test_xnor is port (
sel0, sel1: in std_logic;
c: out std_logic);
end test_xnor;
architecture synth of test_xnor is
begin
c <= sel1 xnor sel0;
end synth;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue11/test_xor.vhdl 0000664 0000000 0000000 00000000327 14502055570 0027222 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity test_xor is port (
sel0, sel1: in std_logic;
c: out std_logic);
end test_xor;
architecture synth of test_xor is
begin
c <= sel1 xor sel0;
end synth;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue11/testsuite.sh 0000775 0000000 0000000 00000000212 14502055570 0027055 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
for f in or xor nor nand xnor; do
synth "test_${f}.vhdl -e test_${f}"
done
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue154/ 0000775 0000000 0000000 00000000000 14502055570 0024562 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue154/keep.vhdl 0000664 0000000 0000000 00000002142 14502055570 0026364 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Led positions
--
-- I D3
-- r
-- D D2 D5 D4
-- A
-- D1
--
entity leds is
port (clk : in std_logic;
led1, led2, led3, led4, led5 : out std_logic);
end leds;
architecture blink of leds is
signal clk_4hz: std_logic := '0';
constant gates: integer := 3 - 1;
signal max: integer := 3e6;
signal A: std_logic_vector(0 to gates) := ( others => '0');
attribute keep: boolean;
attribute keep of A: signal is true;
signal B: std_logic := '1';
signal C: std_logic := '1';
signal val: std_logic := '0';
signal data: std_logic := '0';
begin
process (clk)
variable counter : unsigned (23 downto 0) := (others => '0');
begin
if rising_edge(clk) then
if counter >= max then
counter := x"000000";
clk_4hz <= not clk_4hz;
else
counter := counter + 1;
end if;
end if;
end process;
GEN:
for i in 0 to gates generate
A(i) <= not A(gates - i);
end generate GEN;
led2 <= clk_4hz;
led3 <= clk_4hz;
led4 <= clk_4hz;
led5 <= clk_4hz;
end;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue154/testsuite.sh 0000775 0000000 0000000 00000000276 14502055570 0027157 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
run_yosys -Q -q -p "ghdl keep.vhdl -e; write_verilog keep.v"
# Check the signal still exists
fgrep -q "wire [2:0] a" keep.v
rm -f *.v
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue158/ 0000775 0000000 0000000 00000000000 14502055570 0024566 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue158/repro.vhdl 0000664 0000000 0000000 00000001761 14502055570 0026601 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity MUX_uint4 is
port(
iftrue : in std_logic_vector(3 downto 0);
return_output : out std_logic_vector(3 downto 0));
end;
architecture arch of MUX_uint4 is
begin
return_output <= iftrue;
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity repro is
port(
clk : in std_logic;
module_to_clk_cross : out std_ulogic);
end;
architecture arch of repro is
type variables_t is record
iftrue : std_logic_vector(3 downto 0);
return_output : std_logic_vector(3 downto 0);
end record;
signal iftrue : std_logic_vector(3 downto 0);
signal return_output : std_logic_vector(3 downto 0);
begin
c3_8e8a : entity work.MUX_uint4 port map (iftrue, return_output);
process (clk) is
variable read_pipe : variables_t;
variable write_pipe : variables_t;
begin
write_pipe := read_pipe;
iftrue <= write_pipe.iftrue;
-- write_pipe.return_output := return_output;
read_pipe := write_pipe;
end process;
end arch;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue158/repro1.vhdl 0000664 0000000 0000000 00000003131 14502055570 0026653 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity MUX_uint4 is
port(
cond : in std_logic_vector(0 downto 0);
iftrue : in std_logic_vector(3 downto 0);
iffalse : in std_logic_vector(3 downto 0);
return_output : out std_logic_vector(3 downto 0));
end;
architecture arch of MUX_uint4 is
begin
return_output <= iftrue when cond = "1" else iffalse;
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity repro1 is
port(
clk : in std_logic;
CLOCK_ENABLE : in std_logic_vector(0 downto 0);
module_to_clk_cross : out std_ulogic);
end;
architecture arch of repro1 is
type variables_t is record
c3_8e8a_cond : std_logic_vector(0 downto 0);
c3_8e8a_iffalse : std_logic_vector(3 downto 0);
c3_8e8a_iftrue : std_logic_vector(3 downto 0);
c3_8e8a_return_output : std_logic_vector(3 downto 0);
end record;
signal c3_8e8a_cond : std_logic_vector(0 downto 0);
signal c3_8e8a_iftrue : std_logic_vector(3 downto 0);
signal c3_8e8a_iffalse : std_logic_vector(3 downto 0);
signal c3_8e8a_return_output : std_logic_vector(3 downto 0);
begin
c3_8e8a : entity work.MUX_uint4 port map (
c3_8e8a_cond,
c3_8e8a_iftrue,
c3_8e8a_iffalse,
c3_8e8a_return_output);
process (CLOCK_ENABLE) is
variable read_pipe : variables_t;
variable write_pipe : variables_t;
begin
write_pipe := read_pipe;
c3_8e8a_cond <= write_pipe.c3_8e8a_cond;
c3_8e8a_iftrue <= write_pipe.c3_8e8a_iftrue;
c3_8e8a_iffalse <= write_pipe.c3_8e8a_iffalse;
write_pipe.c3_8e8a_return_output := c3_8e8a_return_output;
read_pipe := write_pipe;
end process;
end arch;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue158/repro3.vhdl 0000664 0000000 0000000 00000001070 14502055570 0026655 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity repro3 is
port(
clk : in std_logic;
inp : std_logic;
module_to_clk_cross : out std_ulogic);
end;
architecture arch of repro3 is
type variables_t is record
iftrue : std_logic_vector(3 downto 0);
inp : std_logic;
return_output : std_logic_vector(3 downto 0);
end record;
begin
process (clk) is
variable read_pipe : variables_t;
variable write_pipe : variables_t;
begin
write_pipe := read_pipe;
write_pipe.inp := inp;
read_pipe := write_pipe;
end process;
end arch;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue158/repro4.vhdl 0000664 0000000 0000000 00000000743 14502055570 0026664 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity repro4 is
port(
clk : in std_logic;
iftrue : out std_logic);
end;
architecture arch of repro4 is
type variables_t is record
iftrue : std_logic;
return_output : std_logic;
end record;
begin
process (clk) is
variable read_pipe : variables_t;
variable write_pipe : variables_t;
begin
write_pipe := read_pipe;
iftrue <= write_pipe.iftrue;
read_pipe := write_pipe;
end process;
end arch;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue158/testsuite.sh 0000775 0000000 0000000 00000000206 14502055570 0027154 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
for f in repro repro1 repro3 repro4; do
synth "${f}.vhdl -e ${f}"
done
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue159/ 0000775 0000000 0000000 00000000000 14502055570 0024567 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue159/repro.vhdl 0000664 0000000 0000000 00000000366 14502055570 0026602 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity repro is
port (i : std_logic;
o : out std_logic);
end;
architecture behav of repro is
begin
process(i)
variable v : std_logic;
begin
o <= i or v;
end process;
end behav;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue159/repro2.vhdl 0000664 0000000 0000000 00000000364 14502055570 0026662 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity repro2 is
port (i : std_logic;
o : out std_logic);
end;
architecture behav of repro2 is
signal v : std_logic;
begin
process(i)
begin
o <= i or v;
end process;
end behav;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue159/testsuite.sh 0000775 0000000 0000000 00000000177 14502055570 0027164 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
for f in repro repro2; do
synth_import "${f}.vhdl -e ${f}"
done
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue160/ 0000775 0000000 0000000 00000000000 14502055570 0024557 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue160/fpu.vhdl 0000664 0000000 0000000 00000001276 14502055570 0026236 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fpu is
port (
clk : in std_ulogic;
addr : in std_ulogic_vector(1 downto 0);
inverse_est : out std_ulogic_vector(17 downto 0)
);
end entity fpu;
architecture behaviour of fpu is
type lookup_table is array(0 to 3) of std_ulogic_vector(17 downto 0);
signal inverse_table : lookup_table := (
18x"3fc01", 18x"3f411", 18x"3ec31", 18x"3e460"
);
begin
lut_access: process(clk)
begin
if rising_edge(clk) then
inverse_est <= inverse_table(to_integer(unsigned(addr)));
end if;
end process;
end architecture behaviour;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue160/fpu2.vhdl 0000664 0000000 0000000 00000001300 14502055570 0026304 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fpu is
port (
clk : in std_ulogic;
addr : in std_ulogic_vector(1 downto 0);
inverse_est : out std_ulogic_vector(17 downto 0)
);
end entity fpu;
architecture behaviour of fpu is
type lookup_table is array(0 to 3) of std_ulogic_vector(17 downto 0);
constant inverse_table : lookup_table := (
18x"3fc01", 18x"3f411", 18x"3ec31", 18x"3e460"
);
begin
lut_access: process(clk)
begin
if rising_edge(clk) then
inverse_est <= inverse_table(to_integer(unsigned(addr)));
end if;
end process;
end architecture behaviour;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue160/testsuite.sh 0000775 0000000 0000000 00000000171 14502055570 0027146 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
for f in fpu fpu2; do
synth_import "--std=08 ${f}.vhdl -e"
done
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue36/ 0000775 0000000 0000000 00000000000 14502055570 0024501 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue36/bram.vhdl 0000664 0000000 0000000 00000001445 14502055570 0026305 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bram is
generic (
addr_width : integer := 9;
data_width : integer := 8
);
port (
clk : in std_logic;
we : in std_logic;
addr : in std_logic_vector(addr_width-1 downto 0);
data_in : in std_logic_vector(data_width-1 downto 0);
data_out : out std_logic_vector(data_width-1 downto 0)
);
end bram;
architecture rtl of bram is
type mem_type is array (0 to (2**addr_width)-1) of std_logic_vector(data_width-1 downto 0);
signal mem : mem_type;
begin
process(clk)
begin
if rising_edge(clk) then
if we = '1' then
mem(to_integer(unsigned(addr))) <= data_in;
end if;
end if;
end process;
data_out <= mem(to_integer(unsigned(addr)));
end rtl;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue36/bram2.vhdl 0000664 0000000 0000000 00000001645 14502055570 0026371 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bram is
generic (
addr_width : integer := 8;
data_width : integer := 32
);
port (
clk : in std_logic;
we : in std_logic;
re : in std_logic;
waddr : in std_logic_vector(addr_width-1 downto 0);
raddr : in std_logic_vector(addr_width-1 downto 0);
wdata : in std_logic_vector(data_width-1 downto 0);
rdata : out std_logic_vector(data_width-1 downto 0)
);
end bram;
architecture rtl of bram is
type mem_type is array (0 to (2**addr_width)-1) of std_logic_vector(data_width-1 downto 0);
signal mem : mem_type;
begin
process(clk)
begin
if rising_edge(clk) then
if we = '1' then
mem(to_integer(unsigned(waddr))) <= wdata;
end if;
if re = '1' then
rdata <= mem(to_integer(unsigned(raddr)));
end if;
end if;
end process;
end rtl;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue36/bram3.vhdl 0000664 0000000 0000000 00000001541 14502055570 0026365 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bram is
generic (
addr_width : integer := 8;
data_width : integer := 32
);
port (
clk : in std_logic;
we : in std_logic;
waddr : in std_logic_vector(addr_width-1 downto 0);
raddr : in std_logic_vector(addr_width-1 downto 0);
wdata : in std_logic_vector(data_width-1 downto 0);
rdata : out std_logic_vector(data_width-1 downto 0)
);
end bram;
architecture rtl of bram is
type mem_type is array (0 to (2**addr_width)-1) of std_logic_vector(data_width-1 downto 0);
signal mem : mem_type;
begin
process(clk)
begin
if rising_edge(clk) then
if we = '1' then
mem(to_integer(unsigned(waddr))) <= wdata;
end if;
rdata <= mem(to_integer(unsigned(raddr)));
end if;
end process;
end rtl;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue36/testsuite.sh 0000775 0000000 0000000 00000000215 14502055570 0027067 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
synth_import bram.vhdl -e
synth_import bram2.vhdl -e
synth_import bram3.vhdl -e
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue4/ 0000775 0000000 0000000 00000000000 14502055570 0024414 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue4/counter8.vhdl 0000664 0000000 0000000 00000000604 14502055570 0027042 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter8 is
port (clk : in std_logic;
led0 : out std_logic);
end counter8;
architecture synth of counter8 is
begin
process (clk)
variable temp : unsigned (7 downto 0);
begin
if rising_edge(clk) then
temp:= temp + 1;
led0 <= temp(0);
end if;
end process;
end synth;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue4/no_vector.vhdl 0000664 0000000 0000000 00000000360 14502055570 0027270 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity no_vector is
port (led0: out std_logic);
end no_vector;
architecture synth of no_vector is
signal nv : std_logic;
begin
nv <= '1';
led0 <= nv;
end synth;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue4/testsuite.sh 0000775 0000000 0000000 00000000205 14502055570 0027001 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
for f in no_vector counter8 vector; do
synth "${f}.vhdl -e ${f}"
done
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue4/vector.vhdl 0000664 0000000 0000000 00000000424 14502055570 0026575 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vector is
port (led0: out std_logic);
end vector;
architecture synth of vector is
signal v : std_logic_vector(7 downto 0);
begin
v <= std_logic_vector'("10101010");
led0 <= v(0);
end synth;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue6/ 0000775 0000000 0000000 00000000000 14502055570 0024416 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue6/testsuite.sh 0000775 0000000 0000000 00000000133 14502055570 0027003 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
synth 'vector.vhdl -e vector'
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue6/vector.vhdl 0000664 0000000 0000000 00000000462 14502055570 0026601 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vector is
port (led0: out std_logic);
end vector;
architecture synth of vector is
signal v : std_logic_vector(7 downto 0);
begin
v <= std_logic_vector'("10101010");
led0 <= v(1); --- But led0 <= v(0) works ok
end synth;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue61/ 0000775 0000000 0000000 00000000000 14502055570 0024477 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue61/testsuite.sh 0000775 0000000 0000000 00000001007 14502055570 0027065 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
run_yosys -q -p "ghdl vector.vhdl -e vector; dump -o vector.il"
#grep -q 0000000000000000000000000000000011111111111111111111111111111010 vector.il || exit 1
grep -q 0000000011111111111111111111111111111111111111111111111100000000 vector.il || exit 1
grep -q 1111111111111111111111111111111111111111111111111111111111111111 vector.il || exit 1
grep -q 0000111111111111111111111111111111111111111111111111111111110000 vector.il || exit 1
rm -f vector.il
clean
echo "OK"
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue61/vector.vhdl 0000664 0000000 0000000 00000000650 14502055570 0026661 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vector is
port (v: out signed(63 downto 0);
u: out unsigned(63 downto 0));
end vector;
architecture synth of vector is
signal v1 : signed (63 downto 0);
signal u1 : unsigned (63 downto 0);
begin
v1 <= x"0ffffffffffffff0";
v <= v1+(-1);
u1 <= x"00ffffffffffff00";
-- u <= u1 + (-6); -- +4294967290;
u <= u1 + 6;
end synth;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue65/ 0000775 0000000 0000000 00000000000 14502055570 0024503 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue65/latch3.vhdl 0000664 0000000 0000000 00000000560 14502055570 0026541 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity latch is
port (
signal clk : in std_logic;
signal data : in std_logic
);
end entity;
architecture rtl of latch is
signal other : std_logic := '0';
begin
default clock is rising_edge(clk);
assert always {true}
|=> next (data = other);
end architecture;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue65/testsuite.sh 0000775 0000000 0000000 00000000142 14502055570 0027070 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
synth_import --std=08 latch3.vhdl -e
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue68/ 0000775 0000000 0000000 00000000000 14502055570 0024506 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue68/demux.vhdl 0000664 0000000 0000000 00000000757 14502055570 0026520 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity demux is port (
j : in integer range 0 to 3;
k : in std_logic;
l : in std_logic;
y : out std_logic_vector(1 to 5));
end demux;
architecture beh of demux is
function to_slv(C:integer; B:std_logic; E:std_logic) return std_logic_vector is
variable ret : std_logic_vector(1 to 5) := (others => '0');
begin
ret(C+1) := E;
ret(5) := B;
return ret;
end to_slv;
begin
y <= to_slv(j, k, l);
end beh;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue68/testsuite.sh 0000775 0000000 0000000 00000000131 14502055570 0027071 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
synth_ice40 "demux.vhdl -e"
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue7/ 0000775 0000000 0000000 00000000000 14502055570 0024417 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue7/ref.vhdl 0000664 0000000 0000000 00000000514 14502055570 0026052 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity vector is
port (led0, led1, led2, led3, led4, led5, led6, led7: out std_logic);
end vector;
architecture ref of vector is
signal v : std_logic_vector(7 downto 0);
begin
-- It works ok
(led7, led6, led5, led4, led3, led2, led1, led0) <= std_logic_vector'("10101010");
end;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue7/testsuite.sh 0000775 0000000 0000000 00000000617 14502055570 0027013 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
run_yosys -Q -q -p "ghdl ref.vhdl -e vector ref; write_verilog ref.v"
run_yosys -Q -q -p "ghdl ref.vhdl vector.vhdl -e vector synth; write_verilog vector.v"
run_yosys -q -p '
read_verilog ref.v
rename vector ref
read_verilog vector.v
equiv_make ref vector equiv
hierarchy -top equiv
equiv_simple
equiv_status -assert'
clean
rm -f *.v
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue7/vector.vhdl 0000664 0000000 0000000 00000001271 14502055570 0026601 0 ustar 00root root 0000000 0000000 architecture synth of vector is
signal v : std_logic_vector(7 downto 0);
begin
-- It works ok
--(led7, led6, led5, led4, led3, led2, led1, led0) <= std_logic_vector'("10101010");
-- It is assigned in reverse order (led7 should be MSB, but it is assigned
-- the lsb. led0 should be the lsb, but is assigned as the MSB)
v <= std_logic_vector'("10101010");
led7 <= v(7);
led6 <= v(6);
led5 <= v(5);
led4 <= v(4);
led3 <= v(3);
led2 <= v(2);
led1 <= v(1);
led0 <= v(0);
end synth;
architecture ok of vector is
signal v : std_logic_vector(7 downto 0);
begin
-- It works ok
(led7, led6, led5, led4, led3, led2, led1, led0) <= std_logic_vector'("10101010");
end ok;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue73/ 0000775 0000000 0000000 00000000000 14502055570 0024502 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue73/cell1.vhdl 0000664 0000000 0000000 00000000270 14502055570 0026360 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity cell1 is
port (
O: out std_logic
);
end entity cell1;
architecture rtl of cell1 is
begin
O <= '0';
end architecture rtl;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue73/cell2.vhdl 0000664 0000000 0000000 00000000267 14502055570 0026367 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity cell2 is
port (
O: out std_logic
);
end entity cell2;
architecture rtl of cell2 is
begin
O <= '1';
end architecture rtl;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue73/multi.vhdl 0000664 0000000 0000000 00000000557 14502055570 0026522 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity cell1 is
port (
O: out std_logic
);
end entity cell1;
architecture rtl of cell1 is
begin
O <= '0';
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
entity cell2 is
port (
O: out std_logic
);
end entity cell2;
architecture rtl of cell2 is
begin
O <= '1';
end architecture rtl;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue73/testsuite.sh 0000775 0000000 0000000 00000000202 14502055570 0027064 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
run_yosys -q -p "ghdl cell1.vhdl -e cell1; ghdl cell2.vhdl -e cell2"
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue75/ 0000775 0000000 0000000 00000000000 14502055570 0024504 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue75/testsuite.sh 0000775 0000000 0000000 00000000177 14502055570 0027101 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
run_yosys -q -p "ghdl top.vhdl -e top; hierarchy -check -top top"
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue75/top.vhdl 0000664 0000000 0000000 00000001341 14502055570 0026164 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.ALL;
entity child is
port (
CLK: in std_logic;
I: in std_logic;
O: out std_logic
);
end entity child;
architecture rtl of child is
signal Ialias: std_logic;
begin
process (CLK)
begin
if rising_edge(CLK) then
O <= Ialias;
end if;
end process;
Ialias <= I;
end architecture rtl;
library ieee;
use ieee.std_logic_1164.ALL;
entity top is
port (
CLK: in std_logic;
I: in std_logic;
O: out std_logic
);
end entity top;
architecture rtl of top is
component child is
port (
CLK: in std_logic;
I: in std_logic;
O: out std_logic
);
end component child;
begin
inst : child port map(CLK, I, O);
end architecture rtl;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue76/ 0000775 0000000 0000000 00000000000 14502055570 0024505 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue76/dff01.vhdl 0000664 0000000 0000000 00000001136 14502055570 0026265 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity dff01 is
port (q : out std_logic_vector (3 downto 0);
d : std_logic_vector (3 downto 0);
en : std_logic;
rst : std_logic;
clk : std_logic);
end dff01;
architecture behav of dff01 is
signal t : std_logic_vector (7 downto 0);
signal a : std_logic_vector (3 downto 0);
begin
a <= d xor b"0101";
process (clk) is
begin
if rst = '1' then
q <= x"0";
elsif rising_edge (clk) then
if en = '1' then
q <= d;
t (7 downto 4) <= a;
end if;
end if;
end process;
end behav;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue76/testsuite.sh 0000775 0000000 0000000 00000000177 14502055570 0027102 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
run_yosys -q -p "ghdl dff01.vhdl -e; hierarchy -check -top dff01"
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue96/ 0000775 0000000 0000000 00000000000 14502055570 0024507 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue96/ent.vhdl 0000664 0000000 0000000 00000000622 14502055570 0026154 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (
a : inout std_logic;
enable : in std_logic;
d_in : in std_logic;
d_out : out std_logic
);
end;
architecture a of ent is
begin
process(all)
begin
if enable then
a <= d_in;
else
a <= 'Z';
end if;
end process;
d_out <= a;
end;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/issue96/testsuite.sh 0000775 0000000 0000000 00000000137 14502055570 0027100 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
synth_import --std=08 ent.vhdl -e
clean
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/pr171/ 0000775 0000000 0000000 00000000000 14502055570 0024052 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/pr171/bootrom.vhdl 0000664 0000000 0000000 00000005705 14502055570 0026421 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package interface is
constant maxAddrBitBRAMLimit : integer := 32;
constant minAddrBit : integer := 2;
constant wordSize : integer := 32;
type ToROM is record
memAWriteEnable : std_logic;
memAAddr : std_logic_vector(maxAddrBitBRAMLimit downto minAddrBit);
memAWrite : std_logic_vector(wordSize-1 downto 0);
memBWriteEnable : std_logic;
memBAddr : std_logic_vector(maxAddrBitBRAMLimit downto minAddrBit);
memBWrite : std_logic_vector(wordSize-1 downto 0);
end record;
type FromROM is record
memARead : std_logic_vector(wordSize-1 downto 0);
memBRead : std_logic_vector(wordSize-1 downto 0);
end record;
end package;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.interface.all;
entity BootROM is
generic
(
maxAddrBitBRAM : integer := 7
);
port (
clk : in std_logic;
areset : in std_logic := '0';
from_sys : in ToROM;
to_sys : out FromROM
);
end entity;
architecture arch of BootROM is
type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
shared variable ram : ram_type :=
(
0 => x"84808080",
1 => x"8c0b8480",
2 => x"8081e004",
3 => x"00848080",
4 => x"808c04ff",
5 => x"0d800404",
6 => x"40000017",
7 => x"00000000",
8 => x"0b83ffe0",
9 => x"80080b83",
10 => x"ffe08408",
11 => x"0b83ffe0",
12 => x"88088480",
13 => x"80809808",
14 => x"2d0b83ff",
15 => x"e0880c0b",
16 => x"83ffe084",
17 => x"0c0b83ff",
18 => x"e0800c04",
19 => x"00000000",
20 => x"00000000",
21 => x"00000000",
22 => x"00000000",
23 => x"00000000",
24 => x"71fd0608",
25 => x"72830609",
26 => x"81058205",
27 => x"832b2a83",
28 => x"ffff0652",
29 => x"0471fc06",
30 => x"08728306",
31 => x"09810583",
others => x"00000000"
);
attribute no_rw_check: boolean;
attribute no_rw_check of ram : variable is true;
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (from_sys.memAWriteEnable = '1') and (from_sys.memBWriteEnable = '1') and (from_sys.memAAddr=from_sys.memBAddr) and (from_sys.memAWrite/=from_sys.memBWrite) then
report "write collision" severity failure;
end if;
if (from_sys.memAWriteEnable = '1') then
ram(to_integer(unsigned(from_sys.memAAddr(maxAddrBitBRAM downto 2)))) := from_sys.memAWrite;
to_sys.memARead <= from_sys.memAWrite;
else
to_sys.memARead <= ram(to_integer(unsigned(from_sys.memAAddr(maxAddrBitBRAM downto 2))));
end if;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
if (from_sys.memBWriteEnable = '1') then
ram(to_integer(unsigned(from_sys.memBAddr(maxAddrBitBRAM downto 2)))) := from_sys.memBWrite;
to_sys.memBRead <= from_sys.memBWrite;
else
to_sys.memBRead <= ram(to_integer(unsigned(from_sys.memBAddr(maxAddrBitBRAM downto 2))));
end if;
end if;
end process;
end arch;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/pr171/testsuite.sh 0000775 0000000 0000000 00000000243 14502055570 0026441 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
run_yosys -q -p "ghdl bootrom.vhdl -e bootrom; memory_libmap -lib +/ecp5/lutrams.txt -lib +/ecp5/brams.txt"
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/pr63/ 0000775 0000000 0000000 00000000000 14502055570 0023772 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/pr63/testsuite.sh 0000775 0000000 0000000 00000000356 14502055570 0026366 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
run_yosys -q -p "ghdl vector.vhdl -e vector; opt; dump -o vector.il"
grep -q 1111000000000000000000000000000000000000000000000000000000010000 vector.il || exit 1
clean
rm vector.il
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/pr63/vector.vhdl 0000664 0000000 0000000 00000000376 14502055570 0026161 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vector is
port (
u : out signed(63 downto 0)
);
end entity vector;
architecture synth of vector is
begin
u <= -signed'(x"0ffffffffffffff0");
end synth;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/pr64/ 0000775 0000000 0000000 00000000000 14502055570 0023773 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/pr64/testsuite.sh 0000775 0000000 0000000 00000000713 14502055570 0026364 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
run_yosys -q -p "ghdl vector.vhdl -e vector; opt; dump -o vector.il"
grep -q 11111111111011110000000000100000000000001101111111110000000000000001000011111111111011110000000000000001000000000000000000000000 vector.il || exit 1
grep -q 00000000000000000000000000001111111111111110111111110000000100000001000011111111111011110000000000000001000000000000000000000000 vector.il || exit 1
clean
rm vector.il
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/pr64/vector.vhdl 0000664 0000000 0000000 00000000617 14502055570 0026160 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vector is
port (
s : out signed(127 downto 0);
u : out unsigned(127 downto 0)
);
end entity vector;
architecture synth of vector is
begin
s <= signed'(x"ffff000000fffff0") * signed'(x"fff0000ffff00000");
u <= unsigned'(x"ffff000000fffff0") * unsigned'(x"fff0000ffff00000");
end synth;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/pr66/ 0000775 0000000 0000000 00000000000 14502055570 0023775 5 ustar 00root root 0000000 0000000 yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/pr66/testsuite.sh 0000775 0000000 0000000 00000000276 14502055570 0026372 0 ustar 00root root 0000000 0000000 #!/bin/sh
topdir=../..
. $topdir/testenv.sh
run_yosys -q -p "ghdl vector.vhdl -e vector; opt; dump -o vector.il"
grep -q 'connect \\v 63' vector.il || exit 1
clean
rm vector.il
echo OK
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/issues/pr66/vector.vhdl 0000664 0000000 0000000 00000000360 14502055570 0026155 0 ustar 00root root 0000000 0000000 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vector is
port (v: out integer
);
end vector;
architecture synth of vector is
begin
v <= to_integer(unsigned'(x"7fffffff")) mod 64;
end synth;
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/testenv.sh 0000664 0000000 0000000 00000002112 14502055570 0023705 0 ustar 00root root 0000000 0000000 # Testsuite environment
if [ x"$topdir" = x"" ]; then
echo "topdir must be defined"
exit 1
fi
. $topdir/../utils.sh
abs_topdir=`pwd`/$topdir
set -e
if [ x"$GHDL" = x ]; then
GHDL=ghdl
fi
if [ x"$YOSYS" = x ]; then
# Need to use abs_topdir because with sby yosys is executed in a subdir.
YOSYS="yosys -m $abs_topdir/../ghdl.so"
fi
if [ x"$SYMBIYOSYS" = x ]; then
SYMBIYOSYS="sby"
fi
cmd ()
{
echo "ยท $@"
"$@"
}
run_yosys ()
{
cmd $YOSYS "$@"
}
run_symbiyosys ()
{
cmd $SYMBIYOSYS --yosys "$YOSYS" "$@"
}
analyze ()
{
printf "${ANSI_BLUE}Analyze $@ $ANSI_NOCOLOR\n"
cmd "$GHDL" -a $GHDL_STD_FLAGS $GHDL_FLAGS $@
}
synth_import ()
{
gstart "Synthesize $*"
run_yosys -q -p "ghdl $*"
status=$?
gend
return $status
}
synth_ice40 ()
{
gstart "synth" "Synthesize $*"
run_yosys -q -p "ghdl $*; synth_ice40 -blif out.blif"
gend
}
synth ()
{
synth_ice40 "$*"
}
formal ()
{
gstart "Verify $@"
run_symbiyosys -f -d work $@.sby
gend
}
clean ()
{
"$GHDL" --remove $GHDL_STD_FLAGS
rm -f out.blif
}
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/testsuite/testsuite.sh 0000775 0000000 0000000 00000001017 14502055570 0024254 0 ustar 00root root 0000000 0000000 #!/usr/bin/env bash
cd "$(dirname $0)"
. ../utils.sh
for d in */*/; do
cd $d
printf "${ANSI_CYAN}test $d ${ANSI_NOCOLOR}\n"
if [ -f ./testsuite.sh ]; then
if ./testsuite.sh; then
printf "${ANSI_GREEN}OK${ANSI_NOCOLOR}\n"
else
printf "${ANSI_RED}FAILED!${ANSI_NOCOLOR}\n"
exit 1
fi
else
printf "${ANSI_YELLOW}Skip $d (no testsuite.sh)${ANSI_NOCOLOR}\n"
fi
cd ../..
done
printf "${ANSI_GREEN}All tests are OK${ANSI_NOCOLOR}\n"
exit 0
yosys-plugin-ghdl-0.0~git20230419.5b64ccf/utils.sh 0000664 0000000 0000000 00000001545 14502055570 0021335 0 ustar 00root root 0000000 0000000 # Utils for pretty printing logs
enable_color() {
ENABLECOLOR='-c '
ANSI_RED="\033[31m"
ANSI_GREEN="\033[32m"
ANSI_YELLOW="\033[33m"
ANSI_BLUE="\033[34m"
ANSI_MAGENTA="\033[35m"
ANSI_CYAN="\033[36;1m"
ANSI_DARKCYAN="\033[36m"
ANSI_NOCOLOR="\033[0m"
}
disable_color() { unset ENABLECOLOR ANSI_RED ANSI_GREEN ANSI_YELLOW ANSI_BLUE ANSI_MAGENTA ANSI_CYAN ANSI_DARKCYAN ANSI_NOCOLOR; }
enable_color
#--
print_start() {
if [ "x$2" != "x" ]; then
COL="$2"
elif [ "x$BASE_COL" != "x" ]; then
COL="$BASE_COL"
else
COL="$ANSI_MAGENTA"
fi
printf "${COL}${1}$ANSI_NOCOLOR\n"
}
gstart () {
print_start "$@"
}
gend () {
:
}
if [ -n "$GITHUB_EVENT_PATH" ]; then
export CI=true
fi
[ -n "$CI" ] && {
gstart () {
printf '::group::'
print_start "$@"
}
gend () {
echo '::endgroup::'
}
} || echo "INFO: not in CI"